* [PATCHv2 0/2] Improve RK3588 clocks and power domains support
@ 2023-04-03 19:32 ` Sebastian Reichel
0 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-04-03 19:32 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Peter Geis, Elaine Zhang, Finley Xiao, Jagan Teki,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, Sebastian Reichel, kernel
Hi,
After this patchset the power-domain support for RK3588 is basically on par
with the downstream implementation. More importantly the clock controller
change unblocks support for any IP blocks using linked clocks. The clock
controller change must be applied before the power-domain change to avoid
accessing unclocked registers.
Changes since PATCHv1:
* https://lore.kernel.org/all/20230331163058.5688-1-sebastian.reichel@collabora.com/
* Replace dsb(sy) with wmb() to fix COMPILE_TEST build on !arm64; direct replacement
would be mb(), but write memory barrier should be enough here as far as I can tell
* Added Tested-by from Vincent Legoll
-- Sebastian
Boris Brezillon (1):
soc: rockchip: power-domain: add rk3588 mem module support
Sebastian Reichel (1):
clk: rockchip: rk3588: make gate linked clocks ignore unused
drivers/clk/rockchip/clk-rk3588.c | 42 +++++---
drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++-------
2 files changed, 151 insertions(+), 51 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCHv2 0/2] Improve RK3588 clocks and power domains support
@ 2023-04-03 19:32 ` Sebastian Reichel
0 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-04-03 19:32 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Peter Geis, Elaine Zhang, Finley Xiao, Jagan Teki,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, Sebastian Reichel, kernel
Hi,
After this patchset the power-domain support for RK3588 is basically on par
with the downstream implementation. More importantly the clock controller
change unblocks support for any IP blocks using linked clocks. The clock
controller change must be applied before the power-domain change to avoid
accessing unclocked registers.
Changes since PATCHv1:
* https://lore.kernel.org/all/20230331163058.5688-1-sebastian.reichel@collabora.com/
* Replace dsb(sy) with wmb() to fix COMPILE_TEST build on !arm64; direct replacement
would be mb(), but write memory barrier should be enough here as far as I can tell
* Added Tested-by from Vincent Legoll
-- Sebastian
Boris Brezillon (1):
soc: rockchip: power-domain: add rk3588 mem module support
Sebastian Reichel (1):
clk: rockchip: rk3588: make gate linked clocks ignore unused
drivers/clk/rockchip/clk-rk3588.c | 42 +++++---
drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++-------
2 files changed, 151 insertions(+), 51 deletions(-)
--
2.39.2
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCHv2 0/2] Improve RK3588 clocks and power domains support
@ 2023-04-03 19:32 ` Sebastian Reichel
0 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-04-03 19:32 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Peter Geis, Elaine Zhang, Finley Xiao, Jagan Teki,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, Sebastian Reichel, kernel
Hi,
After this patchset the power-domain support for RK3588 is basically on par
with the downstream implementation. More importantly the clock controller
change unblocks support for any IP blocks using linked clocks. The clock
controller change must be applied before the power-domain change to avoid
accessing unclocked registers.
Changes since PATCHv1:
* https://lore.kernel.org/all/20230331163058.5688-1-sebastian.reichel@collabora.com/
* Replace dsb(sy) with wmb() to fix COMPILE_TEST build on !arm64; direct replacement
would be mb(), but write memory barrier should be enough here as far as I can tell
* Added Tested-by from Vincent Legoll
-- Sebastian
Boris Brezillon (1):
soc: rockchip: power-domain: add rk3588 mem module support
Sebastian Reichel (1):
clk: rockchip: rk3588: make gate linked clocks ignore unused
drivers/clk/rockchip/clk-rk3588.c | 42 +++++---
drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++-------
2 files changed, 151 insertions(+), 51 deletions(-)
--
2.39.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
2023-04-03 19:32 ` Sebastian Reichel
(?)
@ 2023-04-03 19:32 ` Sebastian Reichel
-1 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-04-03 19:32 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Peter Geis, Elaine Zhang, Finley Xiao, Jagan Teki,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, Sebastian Reichel, kernel,
Vincent Legoll
RK3588 has a couple of hardware blocks called Native Interface Unit
(NIU) that gate the clocks to devices behind them. Effectively this
means that some clocks require two parent clocks being enabled.
Downstream implemented this by using a separate clock driver
("clk-link") for them, which enables the second clock using PM
framework.
In the upstream kernel we are currently missing support for the second
parent. The information about it is in the GATE_LINK() macro as
linkname, but that is not used. Thus the second parent clock is not
properly enabled. So far this did not really matter, since these clocks
are mostly required for the more advanced IP blocks, that are not yet
supported upstream. As this is about to change we need a fix. There
are three options available:
1. Properly implement support for having two parent clocks in the
clock framework.
2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
disabled. This wastes some power, but keeps the hack contained
within the clock driver. Going from this to the first solution
is easy once that has been implemented.
3. Enabling the extra clock in the consumer driver. This leaks some
implementation details into DT.
This patch implements the second option as an intermediate solution
until the first one is available. I used an alias for CLK_IS_CRITICAL,
so that it's easy to see which clocks are not really critical once
the clock framework supports a better way to implement this.
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk-rk3588.c | 42 +++++++++++++++++++------------
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index b7ce3fbd6fa6..6994165e0395 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -13,15 +13,25 @@
#include "clk.h"
/*
- * GATE with additional linked clock. Downstream enables the linked clock
- * (via runtime PM) whenever the gate is enabled. The downstream implementation
- * does this via separate clock nodes for each of the linked gate clocks,
- * which leaks parts of the clock tree into DT. It is unclear why this is
- * actually needed and things work without it for simple use cases. Thus
- * the linked clock is ignored for now.
+ * Recent Rockchip SoCs have a new hardware block called Native Interface
+ * Unit (NIU), which gates clocks to devices behind them. These effectively
+ * need two parent clocks.
+ *
+ * Downstream enables the linked clock via runtime PM whenever the gate is
+ * enabled. This implementation uses separate clock nodes for each of the
+ * linked gate clocks, which leaks parts of the clock tree into DT.
+ *
+ * The GATE_LINK macro instead takes the second parent via 'linkname', but
+ * ignores the information. Once the clock framework is ready to handle it, the
+ * information should be passed on here. But since these clocks are required to
+ * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
+ * clocks critical until a better solution is available. This will waste some
+ * power, but avoids leaking implementation details into DT or hanging the
+ * system.
*/
#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
GATE(_id, cname, pname, f, o, b, gf)
+#define RK3588_LINKED_CLK CLK_IS_CRITICAL
#define RK3588_GRF_SOC_STATUS0 0x600
@@ -1446,7 +1456,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(31), 0, GFLAGS),
- COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
+ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(31), 1, GFLAGS),
GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
@@ -1675,13 +1685,13 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(42), 9, GFLAGS),
/* vdpu */
- COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
+ COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(44), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 1, GFLAGS),
- COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
+ COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 2, GFLAGS),
COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
@@ -1732,9 +1742,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(47), 1, GFLAGS),
- GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
+ GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,
RK3588_CLKGATE_CON(47), 4, GFLAGS),
- GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
+ GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,
RK3588_CLKGATE_CON(47), 5, GFLAGS),
COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
@@ -1744,10 +1754,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(48), 6, GFLAGS),
/* vi */
- COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
+ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(49), 0, GFLAGS),
- COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
+ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(49), 1, GFLAGS),
COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
@@ -1919,10 +1929,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 0, GFLAGS),
- COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
+ COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 1, GFLAGS),
- COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
+ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 2, GFLAGS),
COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
@@ -2425,7 +2435,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS),
+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
--
2.39.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-04-03 19:32 ` Sebastian Reichel
0 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-04-03 19:32 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Peter Geis, Elaine Zhang, Finley Xiao, Jagan Teki,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, Sebastian Reichel, kernel,
Vincent Legoll
RK3588 has a couple of hardware blocks called Native Interface Unit
(NIU) that gate the clocks to devices behind them. Effectively this
means that some clocks require two parent clocks being enabled.
Downstream implemented this by using a separate clock driver
("clk-link") for them, which enables the second clock using PM
framework.
In the upstream kernel we are currently missing support for the second
parent. The information about it is in the GATE_LINK() macro as
linkname, but that is not used. Thus the second parent clock is not
properly enabled. So far this did not really matter, since these clocks
are mostly required for the more advanced IP blocks, that are not yet
supported upstream. As this is about to change we need a fix. There
are three options available:
1. Properly implement support for having two parent clocks in the
clock framework.
2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
disabled. This wastes some power, but keeps the hack contained
within the clock driver. Going from this to the first solution
is easy once that has been implemented.
3. Enabling the extra clock in the consumer driver. This leaks some
implementation details into DT.
This patch implements the second option as an intermediate solution
until the first one is available. I used an alias for CLK_IS_CRITICAL,
so that it's easy to see which clocks are not really critical once
the clock framework supports a better way to implement this.
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk-rk3588.c | 42 +++++++++++++++++++------------
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index b7ce3fbd6fa6..6994165e0395 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -13,15 +13,25 @@
#include "clk.h"
/*
- * GATE with additional linked clock. Downstream enables the linked clock
- * (via runtime PM) whenever the gate is enabled. The downstream implementation
- * does this via separate clock nodes for each of the linked gate clocks,
- * which leaks parts of the clock tree into DT. It is unclear why this is
- * actually needed and things work without it for simple use cases. Thus
- * the linked clock is ignored for now.
+ * Recent Rockchip SoCs have a new hardware block called Native Interface
+ * Unit (NIU), which gates clocks to devices behind them. These effectively
+ * need two parent clocks.
+ *
+ * Downstream enables the linked clock via runtime PM whenever the gate is
+ * enabled. This implementation uses separate clock nodes for each of the
+ * linked gate clocks, which leaks parts of the clock tree into DT.
+ *
+ * The GATE_LINK macro instead takes the second parent via 'linkname', but
+ * ignores the information. Once the clock framework is ready to handle it, the
+ * information should be passed on here. But since these clocks are required to
+ * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
+ * clocks critical until a better solution is available. This will waste some
+ * power, but avoids leaking implementation details into DT or hanging the
+ * system.
*/
#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
GATE(_id, cname, pname, f, o, b, gf)
+#define RK3588_LINKED_CLK CLK_IS_CRITICAL
#define RK3588_GRF_SOC_STATUS0 0x600
@@ -1446,7 +1456,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(31), 0, GFLAGS),
- COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
+ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(31), 1, GFLAGS),
GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
@@ -1675,13 +1685,13 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(42), 9, GFLAGS),
/* vdpu */
- COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
+ COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(44), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 1, GFLAGS),
- COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
+ COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 2, GFLAGS),
COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
@@ -1732,9 +1742,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(47), 1, GFLAGS),
- GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
+ GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,
RK3588_CLKGATE_CON(47), 4, GFLAGS),
- GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
+ GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,
RK3588_CLKGATE_CON(47), 5, GFLAGS),
COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
@@ -1744,10 +1754,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(48), 6, GFLAGS),
/* vi */
- COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
+ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(49), 0, GFLAGS),
- COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
+ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(49), 1, GFLAGS),
COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
@@ -1919,10 +1929,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 0, GFLAGS),
- COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
+ COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 1, GFLAGS),
- COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
+ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 2, GFLAGS),
COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
@@ -2425,7 +2435,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS),
+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
--
2.39.2
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-04-03 19:32 ` Sebastian Reichel
0 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-04-03 19:32 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Peter Geis, Elaine Zhang, Finley Xiao, Jagan Teki,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, Sebastian Reichel, kernel,
Vincent Legoll
RK3588 has a couple of hardware blocks called Native Interface Unit
(NIU) that gate the clocks to devices behind them. Effectively this
means that some clocks require two parent clocks being enabled.
Downstream implemented this by using a separate clock driver
("clk-link") for them, which enables the second clock using PM
framework.
In the upstream kernel we are currently missing support for the second
parent. The information about it is in the GATE_LINK() macro as
linkname, but that is not used. Thus the second parent clock is not
properly enabled. So far this did not really matter, since these clocks
are mostly required for the more advanced IP blocks, that are not yet
supported upstream. As this is about to change we need a fix. There
are three options available:
1. Properly implement support for having two parent clocks in the
clock framework.
2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
disabled. This wastes some power, but keeps the hack contained
within the clock driver. Going from this to the first solution
is easy once that has been implemented.
3. Enabling the extra clock in the consumer driver. This leaks some
implementation details into DT.
This patch implements the second option as an intermediate solution
until the first one is available. I used an alias for CLK_IS_CRITICAL,
so that it's easy to see which clocks are not really critical once
the clock framework supports a better way to implement this.
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk-rk3588.c | 42 +++++++++++++++++++------------
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index b7ce3fbd6fa6..6994165e0395 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -13,15 +13,25 @@
#include "clk.h"
/*
- * GATE with additional linked clock. Downstream enables the linked clock
- * (via runtime PM) whenever the gate is enabled. The downstream implementation
- * does this via separate clock nodes for each of the linked gate clocks,
- * which leaks parts of the clock tree into DT. It is unclear why this is
- * actually needed and things work without it for simple use cases. Thus
- * the linked clock is ignored for now.
+ * Recent Rockchip SoCs have a new hardware block called Native Interface
+ * Unit (NIU), which gates clocks to devices behind them. These effectively
+ * need two parent clocks.
+ *
+ * Downstream enables the linked clock via runtime PM whenever the gate is
+ * enabled. This implementation uses separate clock nodes for each of the
+ * linked gate clocks, which leaks parts of the clock tree into DT.
+ *
+ * The GATE_LINK macro instead takes the second parent via 'linkname', but
+ * ignores the information. Once the clock framework is ready to handle it, the
+ * information should be passed on here. But since these clocks are required to
+ * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
+ * clocks critical until a better solution is available. This will waste some
+ * power, but avoids leaking implementation details into DT or hanging the
+ * system.
*/
#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
GATE(_id, cname, pname, f, o, b, gf)
+#define RK3588_LINKED_CLK CLK_IS_CRITICAL
#define RK3588_GRF_SOC_STATUS0 0x600
@@ -1446,7 +1456,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(31), 0, GFLAGS),
- COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
+ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(31), 1, GFLAGS),
GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
@@ -1675,13 +1685,13 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(42), 9, GFLAGS),
/* vdpu */
- COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
+ COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(44), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 1, GFLAGS),
- COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
+ COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 2, GFLAGS),
COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
@@ -1732,9 +1742,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(47), 1, GFLAGS),
- GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
+ GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,
RK3588_CLKGATE_CON(47), 4, GFLAGS),
- GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
+ GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,
RK3588_CLKGATE_CON(47), 5, GFLAGS),
COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
@@ -1744,10 +1754,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(48), 6, GFLAGS),
/* vi */
- COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
+ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(49), 0, GFLAGS),
- COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
+ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(49), 1, GFLAGS),
COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
@@ -1919,10 +1929,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 0, GFLAGS),
- COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
+ COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 1, GFLAGS),
- COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
+ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 2, GFLAGS),
COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
@@ -2425,7 +2435,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS),
+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
--
2.39.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCHv2 2/2] soc: rockchip: power-domain: add rk3588 mem module support
2023-04-03 19:32 ` Sebastian Reichel
(?)
@ 2023-04-03 19:32 ` Sebastian Reichel
-1 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-04-03 19:32 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Peter Geis, Elaine Zhang, Finley Xiao, Jagan Teki,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, kernel, Vincent Legoll,
Sebastian Reichel
From: Boris Brezillon <boris.brezillon@collabora.com>
On RK3588 it's also possible to power down the memory used by the
particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds
support for this feature.
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Co-Developed-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++-------
1 file changed, 125 insertions(+), 35 deletions(-)
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 84bc022f9e5b..e3de49e671dc 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -43,8 +43,10 @@ struct rockchip_domain_info {
bool active_wakeup;
int pwr_w_mask;
int req_w_mask;
+ int mem_status_mask;
int repair_status_mask;
u32 pwr_offset;
+ u32 mem_offset;
u32 req_offset;
};
@@ -54,6 +56,9 @@ struct rockchip_pmu_info {
u32 req_offset;
u32 idle_offset;
u32 ack_offset;
+ u32 mem_pwr_offset;
+ u32 chain_status_offset;
+ u32 mem_status_offset;
u32 repair_status_offset;
u32 core_pwrcnt_offset;
@@ -119,13 +124,15 @@ struct rockchip_pmu {
.active_wakeup = wakeup, \
}
-#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \
+#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \
{ \
.name = _name, \
.pwr_offset = p_offset, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status), \
+ .mem_offset = m_offset, \
+ .mem_status_mask = (m_status), \
.repair_status_mask = (r_status), \
.req_offset = r_offset, \
.req_w_mask = (req) << 16, \
@@ -269,8 +276,8 @@ void rockchip_pmu_unblock(void)
}
EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
-#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \
- DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup)
+#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
+ DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup)
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
@@ -408,17 +415,92 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
return !(val & pd->info->status_mask);
}
+static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_read(pmu->regmap,
+ pmu->info->mem_status_offset + pd->info->mem_offset, &val);
+
+ /* 1'b0: power on, 1'b1: power off */
+ return !(val & pd->info->mem_status_mask);
+}
+
+static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_read(pmu->regmap,
+ pmu->info->chain_status_offset + pd->info->mem_offset, &val);
+
+ /* 1'b1: power on, 1'b0: power off */
+ return val & pd->info->mem_status_mask;
+}
+
+static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ struct generic_pm_domain *genpd = &pd->genpd;
+ bool is_on;
+ int ret = 0;
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
+ is_on == true, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get chain status '%s', target_on=1, val=%d\n",
+ genpd->name, is_on);
+ goto error;
+ }
+
+ udelay(20);
+
+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
+ (pd->info->pwr_mask | pd->info->pwr_w_mask));
+ wmb();
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
+ is_on == false, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get mem status '%s', target_on=0, val=%d\n",
+ genpd->name, is_on);
+ goto error;
+ }
+
+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
+ pd->info->pwr_w_mask);
+ wmb();
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
+ is_on == true, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get mem status '%s', target_on=1, val=%d\n",
+ genpd->name, is_on);
+ }
+
+error:
+ return ret;
+}
+
static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
bool on)
{
struct rockchip_pmu *pmu = pd->pmu;
struct generic_pm_domain *genpd = &pd->genpd;
u32 pd_pwr_offset = pd->info->pwr_offset;
- bool is_on;
+ bool is_on, is_mem_on = false;
if (pd->info->pwr_mask == 0)
return;
- else if (pd->info->pwr_w_mask)
+
+ if (on && pd->info->mem_status_mask)
+ is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
+
+ if (pd->info->pwr_w_mask)
regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
on ? pd->info->pwr_w_mask :
(pd->info->pwr_mask | pd->info->pwr_w_mask));
@@ -428,6 +510,9 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
wmb();
+ if (is_mem_on && rockchip_pmu_domain_mem_reset(pd))
+ return;
+
if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
is_on == on, 0, 10000)) {
dev_err(pmu->dev,
@@ -645,7 +730,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
pd->genpd.flags = GENPD_FLAG_PM_CLK;
if (pd_info->active_wakeup)
pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
- pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
+ pm_genpd_init(&pd->genpd, NULL,
+ !rockchip_pmu_domain_is_on(pd) ||
+ (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
pmu->genpd_data.domains[id] = &pd->genpd;
return 0;
@@ -1024,35 +1111,35 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
};
static const struct rockchip_domain_info rk3588_pm_domains[] = {
- [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false),
- [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false),
- [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false),
- [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false),
- [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false),
- [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false),
- [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false),
- [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false),
- [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false),
- [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false),
- [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false),
- [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false),
- [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false),
- [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false),
- [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false),
- [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false),
- [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false),
- [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
- [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false),
- [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false),
- [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false),
- [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false),
- [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false),
- [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true),
- [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false),
- [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false),
- [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false),
- [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true),
- [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false),
+ [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
+ [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
+ [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false),
+ [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false),
+ [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false),
+ [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false),
+ [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false),
+ [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false),
+ [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false),
+ [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false),
+ [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false),
+ [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false),
+ [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false),
+ [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
+ [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false),
+ [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
+ [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
+ [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
+ [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
+ [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false),
+ [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false),
+ [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false),
+ [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false),
+ [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true),
+ [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false),
+ [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false),
+ [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false),
+ [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true),
+ [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false),
};
static const struct rockchip_pmu_info px30_pmu = {
@@ -1207,6 +1294,9 @@ static const struct rockchip_pmu_info rk3588_pmu = {
.req_offset = 0x10c,
.idle_offset = 0x120,
.ack_offset = 0x118,
+ .mem_pwr_offset = 0x1a0,
+ .chain_status_offset = 0x1f0,
+ .mem_status_offset = 0x1f8,
.repair_status_offset = 0x290,
.num_domains = ARRAY_SIZE(rk3588_pm_domains),
--
2.39.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCHv2 2/2] soc: rockchip: power-domain: add rk3588 mem module support
@ 2023-04-03 19:32 ` Sebastian Reichel
0 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-04-03 19:32 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Peter Geis, Elaine Zhang, Finley Xiao, Jagan Teki,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, kernel, Vincent Legoll,
Sebastian Reichel
From: Boris Brezillon <boris.brezillon@collabora.com>
On RK3588 it's also possible to power down the memory used by the
particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds
support for this feature.
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Co-Developed-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++-------
1 file changed, 125 insertions(+), 35 deletions(-)
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 84bc022f9e5b..e3de49e671dc 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -43,8 +43,10 @@ struct rockchip_domain_info {
bool active_wakeup;
int pwr_w_mask;
int req_w_mask;
+ int mem_status_mask;
int repair_status_mask;
u32 pwr_offset;
+ u32 mem_offset;
u32 req_offset;
};
@@ -54,6 +56,9 @@ struct rockchip_pmu_info {
u32 req_offset;
u32 idle_offset;
u32 ack_offset;
+ u32 mem_pwr_offset;
+ u32 chain_status_offset;
+ u32 mem_status_offset;
u32 repair_status_offset;
u32 core_pwrcnt_offset;
@@ -119,13 +124,15 @@ struct rockchip_pmu {
.active_wakeup = wakeup, \
}
-#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \
+#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \
{ \
.name = _name, \
.pwr_offset = p_offset, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status), \
+ .mem_offset = m_offset, \
+ .mem_status_mask = (m_status), \
.repair_status_mask = (r_status), \
.req_offset = r_offset, \
.req_w_mask = (req) << 16, \
@@ -269,8 +276,8 @@ void rockchip_pmu_unblock(void)
}
EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
-#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \
- DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup)
+#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
+ DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup)
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
@@ -408,17 +415,92 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
return !(val & pd->info->status_mask);
}
+static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_read(pmu->regmap,
+ pmu->info->mem_status_offset + pd->info->mem_offset, &val);
+
+ /* 1'b0: power on, 1'b1: power off */
+ return !(val & pd->info->mem_status_mask);
+}
+
+static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_read(pmu->regmap,
+ pmu->info->chain_status_offset + pd->info->mem_offset, &val);
+
+ /* 1'b1: power on, 1'b0: power off */
+ return val & pd->info->mem_status_mask;
+}
+
+static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ struct generic_pm_domain *genpd = &pd->genpd;
+ bool is_on;
+ int ret = 0;
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
+ is_on == true, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get chain status '%s', target_on=1, val=%d\n",
+ genpd->name, is_on);
+ goto error;
+ }
+
+ udelay(20);
+
+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
+ (pd->info->pwr_mask | pd->info->pwr_w_mask));
+ wmb();
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
+ is_on == false, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get mem status '%s', target_on=0, val=%d\n",
+ genpd->name, is_on);
+ goto error;
+ }
+
+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
+ pd->info->pwr_w_mask);
+ wmb();
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
+ is_on == true, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get mem status '%s', target_on=1, val=%d\n",
+ genpd->name, is_on);
+ }
+
+error:
+ return ret;
+}
+
static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
bool on)
{
struct rockchip_pmu *pmu = pd->pmu;
struct generic_pm_domain *genpd = &pd->genpd;
u32 pd_pwr_offset = pd->info->pwr_offset;
- bool is_on;
+ bool is_on, is_mem_on = false;
if (pd->info->pwr_mask == 0)
return;
- else if (pd->info->pwr_w_mask)
+
+ if (on && pd->info->mem_status_mask)
+ is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
+
+ if (pd->info->pwr_w_mask)
regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
on ? pd->info->pwr_w_mask :
(pd->info->pwr_mask | pd->info->pwr_w_mask));
@@ -428,6 +510,9 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
wmb();
+ if (is_mem_on && rockchip_pmu_domain_mem_reset(pd))
+ return;
+
if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
is_on == on, 0, 10000)) {
dev_err(pmu->dev,
@@ -645,7 +730,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
pd->genpd.flags = GENPD_FLAG_PM_CLK;
if (pd_info->active_wakeup)
pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
- pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
+ pm_genpd_init(&pd->genpd, NULL,
+ !rockchip_pmu_domain_is_on(pd) ||
+ (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
pmu->genpd_data.domains[id] = &pd->genpd;
return 0;
@@ -1024,35 +1111,35 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
};
static const struct rockchip_domain_info rk3588_pm_domains[] = {
- [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false),
- [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false),
- [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false),
- [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false),
- [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false),
- [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false),
- [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false),
- [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false),
- [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false),
- [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false),
- [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false),
- [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false),
- [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false),
- [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false),
- [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false),
- [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false),
- [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false),
- [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
- [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false),
- [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false),
- [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false),
- [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false),
- [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false),
- [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true),
- [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false),
- [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false),
- [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false),
- [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true),
- [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false),
+ [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
+ [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
+ [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false),
+ [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false),
+ [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false),
+ [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false),
+ [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false),
+ [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false),
+ [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false),
+ [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false),
+ [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false),
+ [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false),
+ [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false),
+ [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
+ [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false),
+ [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
+ [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
+ [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
+ [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
+ [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false),
+ [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false),
+ [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false),
+ [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false),
+ [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true),
+ [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false),
+ [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false),
+ [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false),
+ [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true),
+ [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false),
};
static const struct rockchip_pmu_info px30_pmu = {
@@ -1207,6 +1294,9 @@ static const struct rockchip_pmu_info rk3588_pmu = {
.req_offset = 0x10c,
.idle_offset = 0x120,
.ack_offset = 0x118,
+ .mem_pwr_offset = 0x1a0,
+ .chain_status_offset = 0x1f0,
+ .mem_status_offset = 0x1f8,
.repair_status_offset = 0x290,
.num_domains = ARRAY_SIZE(rk3588_pm_domains),
--
2.39.2
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCHv2 2/2] soc: rockchip: power-domain: add rk3588 mem module support
@ 2023-04-03 19:32 ` Sebastian Reichel
0 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-04-03 19:32 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Peter Geis, Elaine Zhang, Finley Xiao, Jagan Teki,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, kernel, Vincent Legoll,
Sebastian Reichel
From: Boris Brezillon <boris.brezillon@collabora.com>
On RK3588 it's also possible to power down the memory used by the
particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds
support for this feature.
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
Co-Developed-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++-------
1 file changed, 125 insertions(+), 35 deletions(-)
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 84bc022f9e5b..e3de49e671dc 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -43,8 +43,10 @@ struct rockchip_domain_info {
bool active_wakeup;
int pwr_w_mask;
int req_w_mask;
+ int mem_status_mask;
int repair_status_mask;
u32 pwr_offset;
+ u32 mem_offset;
u32 req_offset;
};
@@ -54,6 +56,9 @@ struct rockchip_pmu_info {
u32 req_offset;
u32 idle_offset;
u32 ack_offset;
+ u32 mem_pwr_offset;
+ u32 chain_status_offset;
+ u32 mem_status_offset;
u32 repair_status_offset;
u32 core_pwrcnt_offset;
@@ -119,13 +124,15 @@ struct rockchip_pmu {
.active_wakeup = wakeup, \
}
-#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \
+#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \
{ \
.name = _name, \
.pwr_offset = p_offset, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status), \
+ .mem_offset = m_offset, \
+ .mem_status_mask = (m_status), \
.repair_status_mask = (r_status), \
.req_offset = r_offset, \
.req_w_mask = (req) << 16, \
@@ -269,8 +276,8 @@ void rockchip_pmu_unblock(void)
}
EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
-#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \
- DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup)
+#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
+ DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup)
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
@@ -408,17 +415,92 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
return !(val & pd->info->status_mask);
}
+static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_read(pmu->regmap,
+ pmu->info->mem_status_offset + pd->info->mem_offset, &val);
+
+ /* 1'b0: power on, 1'b1: power off */
+ return !(val & pd->info->mem_status_mask);
+}
+
+static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_read(pmu->regmap,
+ pmu->info->chain_status_offset + pd->info->mem_offset, &val);
+
+ /* 1'b1: power on, 1'b0: power off */
+ return val & pd->info->mem_status_mask;
+}
+
+static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ struct generic_pm_domain *genpd = &pd->genpd;
+ bool is_on;
+ int ret = 0;
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
+ is_on == true, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get chain status '%s', target_on=1, val=%d\n",
+ genpd->name, is_on);
+ goto error;
+ }
+
+ udelay(20);
+
+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
+ (pd->info->pwr_mask | pd->info->pwr_w_mask));
+ wmb();
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
+ is_on == false, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get mem status '%s', target_on=0, val=%d\n",
+ genpd->name, is_on);
+ goto error;
+ }
+
+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
+ pd->info->pwr_w_mask);
+ wmb();
+
+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
+ is_on == true, 0, 10000);
+ if (ret) {
+ dev_err(pmu->dev,
+ "failed to get mem status '%s', target_on=1, val=%d\n",
+ genpd->name, is_on);
+ }
+
+error:
+ return ret;
+}
+
static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
bool on)
{
struct rockchip_pmu *pmu = pd->pmu;
struct generic_pm_domain *genpd = &pd->genpd;
u32 pd_pwr_offset = pd->info->pwr_offset;
- bool is_on;
+ bool is_on, is_mem_on = false;
if (pd->info->pwr_mask == 0)
return;
- else if (pd->info->pwr_w_mask)
+
+ if (on && pd->info->mem_status_mask)
+ is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
+
+ if (pd->info->pwr_w_mask)
regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
on ? pd->info->pwr_w_mask :
(pd->info->pwr_mask | pd->info->pwr_w_mask));
@@ -428,6 +510,9 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
wmb();
+ if (is_mem_on && rockchip_pmu_domain_mem_reset(pd))
+ return;
+
if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
is_on == on, 0, 10000)) {
dev_err(pmu->dev,
@@ -645,7 +730,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
pd->genpd.flags = GENPD_FLAG_PM_CLK;
if (pd_info->active_wakeup)
pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
- pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
+ pm_genpd_init(&pd->genpd, NULL,
+ !rockchip_pmu_domain_is_on(pd) ||
+ (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
pmu->genpd_data.domains[id] = &pd->genpd;
return 0;
@@ -1024,35 +1111,35 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
};
static const struct rockchip_domain_info rk3588_pm_domains[] = {
- [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false),
- [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false),
- [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false),
- [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false),
- [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false),
- [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false),
- [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false),
- [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false),
- [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false),
- [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false),
- [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false),
- [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false),
- [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false),
- [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false),
- [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false),
- [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false),
- [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false),
- [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
- [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false),
- [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false),
- [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false),
- [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false),
- [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false),
- [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true),
- [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false),
- [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false),
- [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false),
- [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true),
- [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false),
+ [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
+ [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
+ [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false),
+ [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false),
+ [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false),
+ [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false),
+ [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false),
+ [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false),
+ [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false),
+ [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false),
+ [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false),
+ [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false),
+ [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false),
+ [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
+ [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false),
+ [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
+ [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
+ [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
+ [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
+ [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false),
+ [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false),
+ [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false),
+ [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false),
+ [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true),
+ [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false),
+ [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false),
+ [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false),
+ [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true),
+ [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false),
};
static const struct rockchip_pmu_info px30_pmu = {
@@ -1207,6 +1294,9 @@ static const struct rockchip_pmu_info rk3588_pmu = {
.req_offset = 0x10c,
.idle_offset = 0x120,
.ack_offset = 0x118,
+ .mem_pwr_offset = 0x1a0,
+ .chain_status_offset = 0x1f0,
+ .mem_status_offset = 0x1f8,
.repair_status_offset = 0x290,
.num_domains = ARRAY_SIZE(rk3588_pm_domains),
--
2.39.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: (subset) [PATCHv2 0/2] Improve RK3588 clocks and power domains support
2023-04-03 19:32 ` Sebastian Reichel
(?)
@ 2023-04-17 23:18 ` Heiko Stuebner
-1 siblings, 0 replies; 30+ messages in thread
From: Heiko Stuebner @ 2023-04-17 23:18 UTC (permalink / raw)
To: Sebastian Reichel, linux-rockchip
Cc: Heiko Stuebner, Boris Brezillon, Elaine Zhang, linux-kernel,
linux-arm-kernel, Michael Turquette, kernel, Peter Geis,
Finley Xiao, Stephen Boyd, Jagan Teki, linux-clk
On Mon, 3 Apr 2023 21:32:48 +0200, Sebastian Reichel wrote:
> After this patchset the power-domain support for RK3588 is basically on par
> with the downstream implementation. More importantly the clock controller
> change unblocks support for any IP blocks using linked clocks. The clock
> controller change must be applied before the power-domain change to avoid
> accessing unclocked registers.
>
> Changes since PATCHv1:
> * https://lore.kernel.org/all/20230331163058.5688-1-sebastian.reichel@collabora.com/
> * Replace dsb(sy) with wmb() to fix COMPILE_TEST build on !arm64; direct replacement
> would be mb(), but write memory barrier should be enough here as far as I can tell
> * Added Tested-by from Vincent Legoll
>
> [...]
Applied, thanks!
[1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
commit: 64042c28c3bb6729df8e2fda89bc7ebbe3790907
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: (subset) [PATCHv2 0/2] Improve RK3588 clocks and power domains support
@ 2023-04-17 23:18 ` Heiko Stuebner
0 siblings, 0 replies; 30+ messages in thread
From: Heiko Stuebner @ 2023-04-17 23:18 UTC (permalink / raw)
To: Sebastian Reichel, linux-rockchip
Cc: Heiko Stuebner, Boris Brezillon, Elaine Zhang, linux-kernel,
linux-arm-kernel, Michael Turquette, kernel, Peter Geis,
Finley Xiao, Stephen Boyd, Jagan Teki, linux-clk
On Mon, 3 Apr 2023 21:32:48 +0200, Sebastian Reichel wrote:
> After this patchset the power-domain support for RK3588 is basically on par
> with the downstream implementation. More importantly the clock controller
> change unblocks support for any IP blocks using linked clocks. The clock
> controller change must be applied before the power-domain change to avoid
> accessing unclocked registers.
>
> Changes since PATCHv1:
> * https://lore.kernel.org/all/20230331163058.5688-1-sebastian.reichel@collabora.com/
> * Replace dsb(sy) with wmb() to fix COMPILE_TEST build on !arm64; direct replacement
> would be mb(), but write memory barrier should be enough here as far as I can tell
> * Added Tested-by from Vincent Legoll
>
> [...]
Applied, thanks!
[1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
commit: 64042c28c3bb6729df8e2fda89bc7ebbe3790907
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: (subset) [PATCHv2 0/2] Improve RK3588 clocks and power domains support
@ 2023-04-17 23:18 ` Heiko Stuebner
0 siblings, 0 replies; 30+ messages in thread
From: Heiko Stuebner @ 2023-04-17 23:18 UTC (permalink / raw)
To: Sebastian Reichel, linux-rockchip
Cc: Heiko Stuebner, Boris Brezillon, Elaine Zhang, linux-kernel,
linux-arm-kernel, Michael Turquette, kernel, Peter Geis,
Finley Xiao, Stephen Boyd, Jagan Teki, linux-clk
On Mon, 3 Apr 2023 21:32:48 +0200, Sebastian Reichel wrote:
> After this patchset the power-domain support for RK3588 is basically on par
> with the downstream implementation. More importantly the clock controller
> change unblocks support for any IP blocks using linked clocks. The clock
> controller change must be applied before the power-domain change to avoid
> accessing unclocked registers.
>
> Changes since PATCHv1:
> * https://lore.kernel.org/all/20230331163058.5688-1-sebastian.reichel@collabora.com/
> * Replace dsb(sy) with wmb() to fix COMPILE_TEST build on !arm64; direct replacement
> would be mb(), but write memory barrier should be enough here as far as I can tell
> * Added Tested-by from Vincent Legoll
>
> [...]
Applied, thanks!
[1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
commit: 64042c28c3bb6729df8e2fda89bc7ebbe3790907
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: (subset) [PATCHv2 0/2] Improve RK3588 clocks and power domains support
2023-04-03 19:32 ` Sebastian Reichel
(?)
@ 2023-04-21 12:56 ` Heiko Stuebner
-1 siblings, 0 replies; 30+ messages in thread
From: Heiko Stuebner @ 2023-04-21 12:56 UTC (permalink / raw)
To: Sebastian Reichel, linux-rockchip
Cc: Heiko Stuebner, Finley Xiao, Stephen Boyd, linux-kernel,
Boris Brezillon, kernel, Jagan Teki, linux-clk, Elaine Zhang,
Peter Geis, linux-arm-kernel, Michael Turquette
On Mon, 3 Apr 2023 21:32:48 +0200, Sebastian Reichel wrote:
> After this patchset the power-domain support for RK3588 is basically on par
> with the downstream implementation. More importantly the clock controller
> change unblocks support for any IP blocks using linked clocks. The clock
> controller change must be applied before the power-domain change to avoid
> accessing unclocked registers.
>
> Changes since PATCHv1:
> * https://lore.kernel.org/all/20230331163058.5688-1-sebastian.reichel@collabora.com/
> * Replace dsb(sy) with wmb() to fix COMPILE_TEST build on !arm64; direct replacement
> would be mb(), but write memory barrier should be enough here as far as I can tell
> * Added Tested-by from Vincent Legoll
>
> [...]
Applied, thanks!
[2/2] soc: rockchip: power-domain: add rk3588 mem module support
commit: 632a6b6593d5bfe9932490f8483195bbf50cbbb7
For 6.5, so this will get a rebase after 6.4-rc1.
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: (subset) [PATCHv2 0/2] Improve RK3588 clocks and power domains support
@ 2023-04-21 12:56 ` Heiko Stuebner
0 siblings, 0 replies; 30+ messages in thread
From: Heiko Stuebner @ 2023-04-21 12:56 UTC (permalink / raw)
To: Sebastian Reichel, linux-rockchip
Cc: Heiko Stuebner, Finley Xiao, Stephen Boyd, linux-kernel,
Boris Brezillon, kernel, Jagan Teki, linux-clk, Elaine Zhang,
Peter Geis, linux-arm-kernel, Michael Turquette
On Mon, 3 Apr 2023 21:32:48 +0200, Sebastian Reichel wrote:
> After this patchset the power-domain support for RK3588 is basically on par
> with the downstream implementation. More importantly the clock controller
> change unblocks support for any IP blocks using linked clocks. The clock
> controller change must be applied before the power-domain change to avoid
> accessing unclocked registers.
>
> Changes since PATCHv1:
> * https://lore.kernel.org/all/20230331163058.5688-1-sebastian.reichel@collabora.com/
> * Replace dsb(sy) with wmb() to fix COMPILE_TEST build on !arm64; direct replacement
> would be mb(), but write memory barrier should be enough here as far as I can tell
> * Added Tested-by from Vincent Legoll
>
> [...]
Applied, thanks!
[2/2] soc: rockchip: power-domain: add rk3588 mem module support
commit: 632a6b6593d5bfe9932490f8483195bbf50cbbb7
For 6.5, so this will get a rebase after 6.4-rc1.
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: (subset) [PATCHv2 0/2] Improve RK3588 clocks and power domains support
@ 2023-04-21 12:56 ` Heiko Stuebner
0 siblings, 0 replies; 30+ messages in thread
From: Heiko Stuebner @ 2023-04-21 12:56 UTC (permalink / raw)
To: Sebastian Reichel, linux-rockchip
Cc: Heiko Stuebner, Finley Xiao, Stephen Boyd, linux-kernel,
Boris Brezillon, kernel, Jagan Teki, linux-clk, Elaine Zhang,
Peter Geis, linux-arm-kernel, Michael Turquette
On Mon, 3 Apr 2023 21:32:48 +0200, Sebastian Reichel wrote:
> After this patchset the power-domain support for RK3588 is basically on par
> with the downstream implementation. More importantly the clock controller
> change unblocks support for any IP blocks using linked clocks. The clock
> controller change must be applied before the power-domain change to avoid
> accessing unclocked registers.
>
> Changes since PATCHv1:
> * https://lore.kernel.org/all/20230331163058.5688-1-sebastian.reichel@collabora.com/
> * Replace dsb(sy) with wmb() to fix COMPILE_TEST build on !arm64; direct replacement
> would be mb(), but write memory barrier should be enough here as far as I can tell
> * Added Tested-by from Vincent Legoll
>
> [...]
Applied, thanks!
[2/2] soc: rockchip: power-domain: add rk3588 mem module support
commit: 632a6b6593d5bfe9932490f8483195bbf50cbbb7
For 6.5, so this will get a rebase after 6.4-rc1.
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
2023-04-03 19:32 ` Sebastian Reichel
(?)
@ 2023-07-13 14:55 ` Jagan Teki
-1 siblings, 0 replies; 30+ messages in thread
From: Jagan Teki @ 2023-07-13 14:55 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Elaine Zhang,
Finley Xiao, Michael Turquette, Stephen Boyd, Boris Brezillon,
linux-clk, linux-arm-kernel, linux-kernel, kernel,
Vincent Legoll
Hi Sebastian,
On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
<sebastian.reichel@collabora.com> wrote:
>
> RK3588 has a couple of hardware blocks called Native Interface Unit
> (NIU) that gate the clocks to devices behind them. Effectively this
> means that some clocks require two parent clocks being enabled.
> Downstream implemented this by using a separate clock driver
> ("clk-link") for them, which enables the second clock using PM
> framework.
>
> In the upstream kernel we are currently missing support for the second
> parent. The information about it is in the GATE_LINK() macro as
> linkname, but that is not used. Thus the second parent clock is not
> properly enabled. So far this did not really matter, since these clocks
> are mostly required for the more advanced IP blocks, that are not yet
> supported upstream. As this is about to change we need a fix. There
> are three options available:
>
> 1. Properly implement support for having two parent clocks in the
> clock framework.
> 2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
> disabled. This wastes some power, but keeps the hack contained
> within the clock driver. Going from this to the first solution
> is easy once that has been implemented.
> 3. Enabling the extra clock in the consumer driver. This leaks some
> implementation details into DT.
>
> This patch implements the second option as an intermediate solution
> until the first one is available. I used an alias for CLK_IS_CRITICAL,
> so that it's easy to see which clocks are not really critical once
> the clock framework supports a better way to implement this.
>
> Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> drivers/clk/rockchip/clk-rk3588.c | 42 +++++++++++++++++++------------
> 1 file changed, 26 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
> index b7ce3fbd6fa6..6994165e0395 100644
> --- a/drivers/clk/rockchip/clk-rk3588.c
> +++ b/drivers/clk/rockchip/clk-rk3588.c
> @@ -13,15 +13,25 @@
> #include "clk.h"
>
> /*
> - * GATE with additional linked clock. Downstream enables the linked clock
> - * (via runtime PM) whenever the gate is enabled. The downstream implementation
> - * does this via separate clock nodes for each of the linked gate clocks,
> - * which leaks parts of the clock tree into DT. It is unclear why this is
> - * actually needed and things work without it for simple use cases. Thus
> - * the linked clock is ignored for now.
> + * Recent Rockchip SoCs have a new hardware block called Native Interface
> + * Unit (NIU), which gates clocks to devices behind them. These effectively
> + * need two parent clocks.
> + *
> + * Downstream enables the linked clock via runtime PM whenever the gate is
> + * enabled. This implementation uses separate clock nodes for each of the
> + * linked gate clocks, which leaks parts of the clock tree into DT.
> + *
> + * The GATE_LINK macro instead takes the second parent via 'linkname', but
> + * ignores the information. Once the clock framework is ready to handle it, the
> + * information should be passed on here. But since these clocks are required to
> + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
> + * clocks critical until a better solution is available. This will waste some
> + * power, but avoids leaking implementation details into DT or hanging the
> + * system.
> */
Does it mean the clk-link topology in the downstream kernel can be
reused the same as normal clock notation?
For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
of routing to pclk_vo1_grf(done downstream)
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru HCLK_VO1>;
};
This seems breaking syscon for vo1_grf and observed a bus error while
accessing regmap. I remember in one of the RKDC discussion that the
double parenting of these clocks is mandatory while accessing
associated IP blocks. Any thoughts?
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-07-13 14:55 ` Jagan Teki
0 siblings, 0 replies; 30+ messages in thread
From: Jagan Teki @ 2023-07-13 14:55 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Elaine Zhang,
Finley Xiao, Michael Turquette, Stephen Boyd, Boris Brezillon,
linux-clk, linux-arm-kernel, linux-kernel, kernel,
Vincent Legoll
Hi Sebastian,
On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
<sebastian.reichel@collabora.com> wrote:
>
> RK3588 has a couple of hardware blocks called Native Interface Unit
> (NIU) that gate the clocks to devices behind them. Effectively this
> means that some clocks require two parent clocks being enabled.
> Downstream implemented this by using a separate clock driver
> ("clk-link") for them, which enables the second clock using PM
> framework.
>
> In the upstream kernel we are currently missing support for the second
> parent. The information about it is in the GATE_LINK() macro as
> linkname, but that is not used. Thus the second parent clock is not
> properly enabled. So far this did not really matter, since these clocks
> are mostly required for the more advanced IP blocks, that are not yet
> supported upstream. As this is about to change we need a fix. There
> are three options available:
>
> 1. Properly implement support for having two parent clocks in the
> clock framework.
> 2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
> disabled. This wastes some power, but keeps the hack contained
> within the clock driver. Going from this to the first solution
> is easy once that has been implemented.
> 3. Enabling the extra clock in the consumer driver. This leaks some
> implementation details into DT.
>
> This patch implements the second option as an intermediate solution
> until the first one is available. I used an alias for CLK_IS_CRITICAL,
> so that it's easy to see which clocks are not really critical once
> the clock framework supports a better way to implement this.
>
> Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> drivers/clk/rockchip/clk-rk3588.c | 42 +++++++++++++++++++------------
> 1 file changed, 26 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
> index b7ce3fbd6fa6..6994165e0395 100644
> --- a/drivers/clk/rockchip/clk-rk3588.c
> +++ b/drivers/clk/rockchip/clk-rk3588.c
> @@ -13,15 +13,25 @@
> #include "clk.h"
>
> /*
> - * GATE with additional linked clock. Downstream enables the linked clock
> - * (via runtime PM) whenever the gate is enabled. The downstream implementation
> - * does this via separate clock nodes for each of the linked gate clocks,
> - * which leaks parts of the clock tree into DT. It is unclear why this is
> - * actually needed and things work without it for simple use cases. Thus
> - * the linked clock is ignored for now.
> + * Recent Rockchip SoCs have a new hardware block called Native Interface
> + * Unit (NIU), which gates clocks to devices behind them. These effectively
> + * need two parent clocks.
> + *
> + * Downstream enables the linked clock via runtime PM whenever the gate is
> + * enabled. This implementation uses separate clock nodes for each of the
> + * linked gate clocks, which leaks parts of the clock tree into DT.
> + *
> + * The GATE_LINK macro instead takes the second parent via 'linkname', but
> + * ignores the information. Once the clock framework is ready to handle it, the
> + * information should be passed on here. But since these clocks are required to
> + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
> + * clocks critical until a better solution is available. This will waste some
> + * power, but avoids leaking implementation details into DT or hanging the
> + * system.
> */
Does it mean the clk-link topology in the downstream kernel can be
reused the same as normal clock notation?
For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
of routing to pclk_vo1_grf(done downstream)
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru HCLK_VO1>;
};
This seems breaking syscon for vo1_grf and observed a bus error while
accessing regmap. I remember in one of the RKDC discussion that the
double parenting of these clocks is mandatory while accessing
associated IP blocks. Any thoughts?
Thanks,
Jagan.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-07-13 14:55 ` Jagan Teki
0 siblings, 0 replies; 30+ messages in thread
From: Jagan Teki @ 2023-07-13 14:55 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Elaine Zhang,
Finley Xiao, Michael Turquette, Stephen Boyd, Boris Brezillon,
linux-clk, linux-arm-kernel, linux-kernel, kernel,
Vincent Legoll
Hi Sebastian,
On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
<sebastian.reichel@collabora.com> wrote:
>
> RK3588 has a couple of hardware blocks called Native Interface Unit
> (NIU) that gate the clocks to devices behind them. Effectively this
> means that some clocks require two parent clocks being enabled.
> Downstream implemented this by using a separate clock driver
> ("clk-link") for them, which enables the second clock using PM
> framework.
>
> In the upstream kernel we are currently missing support for the second
> parent. The information about it is in the GATE_LINK() macro as
> linkname, but that is not used. Thus the second parent clock is not
> properly enabled. So far this did not really matter, since these clocks
> are mostly required for the more advanced IP blocks, that are not yet
> supported upstream. As this is about to change we need a fix. There
> are three options available:
>
> 1. Properly implement support for having two parent clocks in the
> clock framework.
> 2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
> disabled. This wastes some power, but keeps the hack contained
> within the clock driver. Going from this to the first solution
> is easy once that has been implemented.
> 3. Enabling the extra clock in the consumer driver. This leaks some
> implementation details into DT.
>
> This patch implements the second option as an intermediate solution
> until the first one is available. I used an alias for CLK_IS_CRITICAL,
> so that it's easy to see which clocks are not really critical once
> the clock framework supports a better way to implement this.
>
> Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> drivers/clk/rockchip/clk-rk3588.c | 42 +++++++++++++++++++------------
> 1 file changed, 26 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
> index b7ce3fbd6fa6..6994165e0395 100644
> --- a/drivers/clk/rockchip/clk-rk3588.c
> +++ b/drivers/clk/rockchip/clk-rk3588.c
> @@ -13,15 +13,25 @@
> #include "clk.h"
>
> /*
> - * GATE with additional linked clock. Downstream enables the linked clock
> - * (via runtime PM) whenever the gate is enabled. The downstream implementation
> - * does this via separate clock nodes for each of the linked gate clocks,
> - * which leaks parts of the clock tree into DT. It is unclear why this is
> - * actually needed and things work without it for simple use cases. Thus
> - * the linked clock is ignored for now.
> + * Recent Rockchip SoCs have a new hardware block called Native Interface
> + * Unit (NIU), which gates clocks to devices behind them. These effectively
> + * need two parent clocks.
> + *
> + * Downstream enables the linked clock via runtime PM whenever the gate is
> + * enabled. This implementation uses separate clock nodes for each of the
> + * linked gate clocks, which leaks parts of the clock tree into DT.
> + *
> + * The GATE_LINK macro instead takes the second parent via 'linkname', but
> + * ignores the information. Once the clock framework is ready to handle it, the
> + * information should be passed on here. But since these clocks are required to
> + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
> + * clocks critical until a better solution is available. This will waste some
> + * power, but avoids leaking implementation details into DT or hanging the
> + * system.
> */
Does it mean the clk-link topology in the downstream kernel can be
reused the same as normal clock notation?
For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
of routing to pclk_vo1_grf(done downstream)
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru HCLK_VO1>;
};
This seems breaking syscon for vo1_grf and observed a bus error while
accessing regmap. I remember in one of the RKDC discussion that the
double parenting of these clocks is mandatory while accessing
associated IP blocks. Any thoughts?
Thanks,
Jagan.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
2023-07-13 14:55 ` Jagan Teki
(?)
@ 2023-07-13 19:38 ` Sebastian Reichel
-1 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-07-13 19:38 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Elaine Zhang,
Finley Xiao, Michael Turquette, Stephen Boyd, Boris Brezillon,
linux-clk, linux-arm-kernel, linux-kernel, kernel,
Vincent Legoll
[-- Attachment #1: Type: text/plain, Size: 2583 bytes --]
Hello Jagan,
On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
> On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
> <sebastian.reichel@collabora.com> wrote:
> [...]
> > + * Recent Rockchip SoCs have a new hardware block called Native Interface
> > + * Unit (NIU), which gates clocks to devices behind them. These effectively
> > + * need two parent clocks.
> > + *
> > + * Downstream enables the linked clock via runtime PM whenever the gate is
> > + * enabled. This implementation uses separate clock nodes for each of the
> > + * linked gate clocks, which leaks parts of the clock tree into DT.
> > + *
> > + * The GATE_LINK macro instead takes the second parent via 'linkname', but
> > + * ignores the information. Once the clock framework is ready to handle it, the
> > + * information should be passed on here. But since these clocks are required to
> > + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
> > + * clocks critical until a better solution is available. This will waste some
> > + * power, but avoids leaking implementation details into DT or hanging the
> > + * system.
> > */
>
> Does it mean the clk-link topology in the downstream kernel can be
> reused the same as normal clock notation?
Yes.
> For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
> of routing to pclk_vo1_grf(done downstream)
> vo1_grf: syscon@fd5a8000 {
> compatible = "rockchip,rk3588-vo-grf", "syscon";
> reg = <0x0 0xfd5a8000 0x0 0x100>;
> clocks = <&cru HCLK_VO1>;
You need PCLK_VO1 (which is currently not exposed; I somehow missed
it).
> };
>
> This seems breaking syscon for vo1_grf and observed a bus error
> while accessing regmap.
I investigated the issue you are seeing some weeks ago when my
co-workers started to work on HDMI RX and TX. You are probably
just missing this patch:
https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/ecc6415344957fa88356cec10f8b75a9da603a7b
> I remember in one of the RKDC discussion that the double parenting
> of these clocks is mandatory while accessing associated IP blocks.
Yes, it is necessary.
> Any thoughts?
The upstream workaround/hack is to have the second parent always
enabled. This obviously wastes power, but means that the hardware
description in the DT is correct. Once the clock framework supports
two parents the kernel can be updated without touching the DT,
which is considered ABI.
Greetings,
-- Sebastian
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-07-13 19:38 ` Sebastian Reichel
0 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-07-13 19:38 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Elaine Zhang,
Finley Xiao, Michael Turquette, Stephen Boyd, Boris Brezillon,
linux-clk, linux-arm-kernel, linux-kernel, kernel,
Vincent Legoll
[-- Attachment #1.1: Type: text/plain, Size: 2583 bytes --]
Hello Jagan,
On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
> On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
> <sebastian.reichel@collabora.com> wrote:
> [...]
> > + * Recent Rockchip SoCs have a new hardware block called Native Interface
> > + * Unit (NIU), which gates clocks to devices behind them. These effectively
> > + * need two parent clocks.
> > + *
> > + * Downstream enables the linked clock via runtime PM whenever the gate is
> > + * enabled. This implementation uses separate clock nodes for each of the
> > + * linked gate clocks, which leaks parts of the clock tree into DT.
> > + *
> > + * The GATE_LINK macro instead takes the second parent via 'linkname', but
> > + * ignores the information. Once the clock framework is ready to handle it, the
> > + * information should be passed on here. But since these clocks are required to
> > + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
> > + * clocks critical until a better solution is available. This will waste some
> > + * power, but avoids leaking implementation details into DT or hanging the
> > + * system.
> > */
>
> Does it mean the clk-link topology in the downstream kernel can be
> reused the same as normal clock notation?
Yes.
> For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
> of routing to pclk_vo1_grf(done downstream)
> vo1_grf: syscon@fd5a8000 {
> compatible = "rockchip,rk3588-vo-grf", "syscon";
> reg = <0x0 0xfd5a8000 0x0 0x100>;
> clocks = <&cru HCLK_VO1>;
You need PCLK_VO1 (which is currently not exposed; I somehow missed
it).
> };
>
> This seems breaking syscon for vo1_grf and observed a bus error
> while accessing regmap.
I investigated the issue you are seeing some weeks ago when my
co-workers started to work on HDMI RX and TX. You are probably
just missing this patch:
https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/ecc6415344957fa88356cec10f8b75a9da603a7b
> I remember in one of the RKDC discussion that the double parenting
> of these clocks is mandatory while accessing associated IP blocks.
Yes, it is necessary.
> Any thoughts?
The upstream workaround/hack is to have the second parent always
enabled. This obviously wastes power, but means that the hardware
description in the DT is correct. Once the clock framework supports
two parents the kernel can be updated without touching the DT,
which is considered ABI.
Greetings,
-- Sebastian
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 170 bytes --]
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-07-13 19:38 ` Sebastian Reichel
0 siblings, 0 replies; 30+ messages in thread
From: Sebastian Reichel @ 2023-07-13 19:38 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Elaine Zhang,
Finley Xiao, Michael Turquette, Stephen Boyd, Boris Brezillon,
linux-clk, linux-arm-kernel, linux-kernel, kernel,
Vincent Legoll
[-- Attachment #1.1: Type: text/plain, Size: 2583 bytes --]
Hello Jagan,
On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
> On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
> <sebastian.reichel@collabora.com> wrote:
> [...]
> > + * Recent Rockchip SoCs have a new hardware block called Native Interface
> > + * Unit (NIU), which gates clocks to devices behind them. These effectively
> > + * need two parent clocks.
> > + *
> > + * Downstream enables the linked clock via runtime PM whenever the gate is
> > + * enabled. This implementation uses separate clock nodes for each of the
> > + * linked gate clocks, which leaks parts of the clock tree into DT.
> > + *
> > + * The GATE_LINK macro instead takes the second parent via 'linkname', but
> > + * ignores the information. Once the clock framework is ready to handle it, the
> > + * information should be passed on here. But since these clocks are required to
> > + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
> > + * clocks critical until a better solution is available. This will waste some
> > + * power, but avoids leaking implementation details into DT or hanging the
> > + * system.
> > */
>
> Does it mean the clk-link topology in the downstream kernel can be
> reused the same as normal clock notation?
Yes.
> For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
> of routing to pclk_vo1_grf(done downstream)
> vo1_grf: syscon@fd5a8000 {
> compatible = "rockchip,rk3588-vo-grf", "syscon";
> reg = <0x0 0xfd5a8000 0x0 0x100>;
> clocks = <&cru HCLK_VO1>;
You need PCLK_VO1 (which is currently not exposed; I somehow missed
it).
> };
>
> This seems breaking syscon for vo1_grf and observed a bus error
> while accessing regmap.
I investigated the issue you are seeing some weeks ago when my
co-workers started to work on HDMI RX and TX. You are probably
just missing this patch:
https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/ecc6415344957fa88356cec10f8b75a9da603a7b
> I remember in one of the RKDC discussion that the double parenting
> of these clocks is mandatory while accessing associated IP blocks.
Yes, it is necessary.
> Any thoughts?
The upstream workaround/hack is to have the second parent always
enabled. This obviously wastes power, but means that the hardware
description in the DT is correct. Once the clock framework supports
two parents the kernel can be updated without touching the DT,
which is considered ABI.
Greetings,
-- Sebastian
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
[not found] ` <20230714091150883537486@rock-chips.com>
2023-07-14 5:28 ` Jagan Teki
@ 2023-07-14 5:28 ` Jagan Teki
0 siblings, 0 replies; 30+ messages in thread
From: Jagan Teki @ 2023-07-14 5:28 UTC (permalink / raw)
To: zhangqing
Cc: Sebastian Reichel, heiko, linux-rockchip, pgwipeout, finley.xiao,
mturquette, sboyd, Boris Brezillon, linux-clk, linux-arm-kernel,
linux-kernel, kernel, Vincent Legoll
Hi,
On Fri, 14 Jul 2023 at 06:44, zhangqing@rock-chips.com
<zhangqing@rock-chips.com> wrote:
>
> Hi Sebastian,
>
> The clock needs to rely on two parent clocks, which is required by design.Refer to the attachment for details.
> Our internal branch is implemented using clk-link.c. Recently, I will implement the real GATE_LINK API according to upstream, without modifying DT.
Do you have a solution to share or any pointers? I tried to use
clk-link by dropping GATE_LINK from clk-rk3588.c however the issue
remains still as double-parenting is unsupportive. Did you add
double-parenting to the mainline clk tree? Other than that, I have
used existing clk and try to attach the link clock in conventional
clock way like
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
};
This also seems similar issue.
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-07-14 5:28 ` Jagan Teki
0 siblings, 0 replies; 30+ messages in thread
From: Jagan Teki @ 2023-07-14 5:28 UTC (permalink / raw)
To: zhangqing
Cc: Sebastian Reichel, heiko, linux-rockchip, pgwipeout, finley.xiao,
mturquette, sboyd, Boris Brezillon, linux-clk, linux-arm-kernel,
linux-kernel, kernel, Vincent Legoll
Hi,
On Fri, 14 Jul 2023 at 06:44, zhangqing@rock-chips.com
<zhangqing@rock-chips.com> wrote:
>
> Hi Sebastian,
>
> The clock needs to rely on two parent clocks, which is required by design.Refer to the attachment for details.
> Our internal branch is implemented using clk-link.c. Recently, I will implement the real GATE_LINK API according to upstream, without modifying DT.
Do you have a solution to share or any pointers? I tried to use
clk-link by dropping GATE_LINK from clk-rk3588.c however the issue
remains still as double-parenting is unsupportive. Did you add
double-parenting to the mainline clk tree? Other than that, I have
used existing clk and try to attach the link clock in conventional
clock way like
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
};
This also seems similar issue.
Thanks,
Jagan.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-07-14 5:28 ` Jagan Teki
0 siblings, 0 replies; 30+ messages in thread
From: Jagan Teki @ 2023-07-14 5:28 UTC (permalink / raw)
To: zhangqing
Cc: Sebastian Reichel, heiko, linux-rockchip, pgwipeout, finley.xiao,
mturquette, sboyd, Boris Brezillon, linux-clk, linux-arm-kernel,
linux-kernel, kernel, Vincent Legoll
Hi,
On Fri, 14 Jul 2023 at 06:44, zhangqing@rock-chips.com
<zhangqing@rock-chips.com> wrote:
>
> Hi Sebastian,
>
> The clock needs to rely on two parent clocks, which is required by design.Refer to the attachment for details.
> Our internal branch is implemented using clk-link.c. Recently, I will implement the real GATE_LINK API according to upstream, without modifying DT.
Do you have a solution to share or any pointers? I tried to use
clk-link by dropping GATE_LINK from clk-rk3588.c however the issue
remains still as double-parenting is unsupportive. Did you add
double-parenting to the mainline clk tree? Other than that, I have
used existing clk and try to attach the link clock in conventional
clock way like
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
};
This also seems similar issue.
Thanks,
Jagan.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
2023-07-13 19:38 ` Sebastian Reichel
(?)
@ 2023-07-14 5:33 ` Jagan Teki
-1 siblings, 0 replies; 30+ messages in thread
From: Jagan Teki @ 2023-07-14 5:33 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Elaine Zhang,
Finley Xiao, Michael Turquette, Stephen Boyd, Boris Brezillon,
linux-clk, linux-arm-kernel, linux-kernel, kernel,
Vincent Legoll
Hi Sebastian,
On Fri, 14 Jul 2023 at 01:08, Sebastian Reichel
<sebastian.reichel@collabora.com> wrote:
>
> Hello Jagan,
>
> On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
> > On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
> > <sebastian.reichel@collabora.com> wrote:
> > [...]
> > > + * Recent Rockchip SoCs have a new hardware block called Native Interface
> > > + * Unit (NIU), which gates clocks to devices behind them. These effectively
> > > + * need two parent clocks.
> > > + *
> > > + * Downstream enables the linked clock via runtime PM whenever the gate is
> > > + * enabled. This implementation uses separate clock nodes for each of the
> > > + * linked gate clocks, which leaks parts of the clock tree into DT.
> > > + *
> > > + * The GATE_LINK macro instead takes the second parent via 'linkname', but
> > > + * ignores the information. Once the clock framework is ready to handle it, the
> > > + * information should be passed on here. But since these clocks are required to
> > > + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
> > > + * clocks critical until a better solution is available. This will waste some
> > > + * power, but avoids leaking implementation details into DT or hanging the
> > > + * system.
> > > */
> >
> > Does it mean the clk-link topology in the downstream kernel can be
> > reused the same as normal clock notation?
>
> Yes.
>
> > For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
> > of routing to pclk_vo1_grf(done downstream)
> > vo1_grf: syscon@fd5a8000 {
> > compatible = "rockchip,rk3588-vo-grf", "syscon";
> > reg = <0x0 0xfd5a8000 0x0 0x100>;
> > clocks = <&cru HCLK_VO1>;
>
> You need PCLK_VO1 (which is currently not exposed; I somehow missed
> it).
>
> > };
> >
> > This seems breaking syscon for vo1_grf and observed a bus error
> > while accessing regmap.
>
> I investigated the issue you are seeing some weeks ago when my
> co-workers started to work on HDMI RX and TX. You are probably
> just missing this patch:
>
> https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/ecc6415344957fa88356cec10f8b75a9da603a7b
In fact, I tried this solution as well, by connecting the PCLK_VO1GRF.
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
};
But the result seems the same, accessing vo1_grf triggers an abort [1]
[1] https://gist.github.com/openedev/e241da8180341ffbf4dc6a26de7efa31
Thanks,
Jagan.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-07-14 5:33 ` Jagan Teki
0 siblings, 0 replies; 30+ messages in thread
From: Jagan Teki @ 2023-07-14 5:33 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Elaine Zhang,
Finley Xiao, Michael Turquette, Stephen Boyd, Boris Brezillon,
linux-clk, linux-arm-kernel, linux-kernel, kernel,
Vincent Legoll
Hi Sebastian,
On Fri, 14 Jul 2023 at 01:08, Sebastian Reichel
<sebastian.reichel@collabora.com> wrote:
>
> Hello Jagan,
>
> On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
> > On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
> > <sebastian.reichel@collabora.com> wrote:
> > [...]
> > > + * Recent Rockchip SoCs have a new hardware block called Native Interface
> > > + * Unit (NIU), which gates clocks to devices behind them. These effectively
> > > + * need two parent clocks.
> > > + *
> > > + * Downstream enables the linked clock via runtime PM whenever the gate is
> > > + * enabled. This implementation uses separate clock nodes for each of the
> > > + * linked gate clocks, which leaks parts of the clock tree into DT.
> > > + *
> > > + * The GATE_LINK macro instead takes the second parent via 'linkname', but
> > > + * ignores the information. Once the clock framework is ready to handle it, the
> > > + * information should be passed on here. But since these clocks are required to
> > > + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
> > > + * clocks critical until a better solution is available. This will waste some
> > > + * power, but avoids leaking implementation details into DT or hanging the
> > > + * system.
> > > */
> >
> > Does it mean the clk-link topology in the downstream kernel can be
> > reused the same as normal clock notation?
>
> Yes.
>
> > For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
> > of routing to pclk_vo1_grf(done downstream)
> > vo1_grf: syscon@fd5a8000 {
> > compatible = "rockchip,rk3588-vo-grf", "syscon";
> > reg = <0x0 0xfd5a8000 0x0 0x100>;
> > clocks = <&cru HCLK_VO1>;
>
> You need PCLK_VO1 (which is currently not exposed; I somehow missed
> it).
>
> > };
> >
> > This seems breaking syscon for vo1_grf and observed a bus error
> > while accessing regmap.
>
> I investigated the issue you are seeing some weeks ago when my
> co-workers started to work on HDMI RX and TX. You are probably
> just missing this patch:
>
> https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/ecc6415344957fa88356cec10f8b75a9da603a7b
In fact, I tried this solution as well, by connecting the PCLK_VO1GRF.
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
};
But the result seems the same, accessing vo1_grf triggers an abort [1]
[1] https://gist.github.com/openedev/e241da8180341ffbf4dc6a26de7efa31
Thanks,
Jagan.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-07-14 5:33 ` Jagan Teki
0 siblings, 0 replies; 30+ messages in thread
From: Jagan Teki @ 2023-07-14 5:33 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Elaine Zhang,
Finley Xiao, Michael Turquette, Stephen Boyd, Boris Brezillon,
linux-clk, linux-arm-kernel, linux-kernel, kernel,
Vincent Legoll
Hi Sebastian,
On Fri, 14 Jul 2023 at 01:08, Sebastian Reichel
<sebastian.reichel@collabora.com> wrote:
>
> Hello Jagan,
>
> On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
> > On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
> > <sebastian.reichel@collabora.com> wrote:
> > [...]
> > > + * Recent Rockchip SoCs have a new hardware block called Native Interface
> > > + * Unit (NIU), which gates clocks to devices behind them. These effectively
> > > + * need two parent clocks.
> > > + *
> > > + * Downstream enables the linked clock via runtime PM whenever the gate is
> > > + * enabled. This implementation uses separate clock nodes for each of the
> > > + * linked gate clocks, which leaks parts of the clock tree into DT.
> > > + *
> > > + * The GATE_LINK macro instead takes the second parent via 'linkname', but
> > > + * ignores the information. Once the clock framework is ready to handle it, the
> > > + * information should be passed on here. But since these clocks are required to
> > > + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
> > > + * clocks critical until a better solution is available. This will waste some
> > > + * power, but avoids leaking implementation details into DT or hanging the
> > > + * system.
> > > */
> >
> > Does it mean the clk-link topology in the downstream kernel can be
> > reused the same as normal clock notation?
>
> Yes.
>
> > For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
> > of routing to pclk_vo1_grf(done downstream)
> > vo1_grf: syscon@fd5a8000 {
> > compatible = "rockchip,rk3588-vo-grf", "syscon";
> > reg = <0x0 0xfd5a8000 0x0 0x100>;
> > clocks = <&cru HCLK_VO1>;
>
> You need PCLK_VO1 (which is currently not exposed; I somehow missed
> it).
>
> > };
> >
> > This seems breaking syscon for vo1_grf and observed a bus error
> > while accessing regmap.
>
> I investigated the issue you are seeing some weeks ago when my
> co-workers started to work on HDMI RX and TX. You are probably
> just missing this patch:
>
> https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/ecc6415344957fa88356cec10f8b75a9da603a7b
In fact, I tried this solution as well, by connecting the PCLK_VO1GRF.
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
};
But the result seems the same, accessing vo1_grf triggers an abort [1]
[1] https://gist.github.com/openedev/e241da8180341ffbf4dc6a26de7efa31
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
2023-07-14 5:33 ` Jagan Teki
(?)
@ 2023-07-28 2:52 ` zhangqing
-1 siblings, 0 replies; 30+ messages in thread
From: zhangqing @ 2023-07-28 2:52 UTC (permalink / raw)
To: Jagan Teki, Sebastian Reichel
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Finley Xiao,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, kernel, Vincent Legoll
在 2023/7/14 13:33, Jagan Teki 写道:
> Hi Sebastian,
>
> On Fri, 14 Jul 2023 at 01:08, Sebastian Reichel
> <sebastian.reichel@collabora.com> wrote:
>> Hello Jagan,
>>
>> On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
>>> On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
>>> <sebastian.reichel@collabora.com> wrote:
>>> [...]
>>>> + * Recent Rockchip SoCs have a new hardware block called Native Interface
>>>> + * Unit (NIU), which gates clocks to devices behind them. These effectively
>>>> + * need two parent clocks.
>>>> + *
>>>> + * Downstream enables the linked clock via runtime PM whenever the gate is
>>>> + * enabled. This implementation uses separate clock nodes for each of the
>>>> + * linked gate clocks, which leaks parts of the clock tree into DT.
>>>> + *
>>>> + * The GATE_LINK macro instead takes the second parent via 'linkname', but
>>>> + * ignores the information. Once the clock framework is ready to handle it, the
>>>> + * information should be passed on here. But since these clocks are required to
>>>> + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
>>>> + * clocks critical until a better solution is available. This will waste some
>>>> + * power, but avoids leaking implementation details into DT or hanging the
>>>> + * system.
>>>> */
>>> Does it mean the clk-link topology in the downstream kernel can be
>>> reused the same as normal clock notation?
>> Yes.
>>
>>> For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
>>> of routing to pclk_vo1_grf(done downstream)
>>> vo1_grf: syscon@fd5a8000 {
>>> compatible = "rockchip,rk3588-vo-grf", "syscon";
>>> reg = <0x0 0xfd5a8000 0x0 0x100>;
>>> clocks = <&cru HCLK_VO1>;
>> You need PCLK_VO1 (which is currently not exposed; I somehow missed
>> it).
Maybe this submission is helpful
The true GATE_LINK callback is implemented.
https://patchwork.kernel.org/project/linux-clk/patch/20230728020810.29732-4-zhangqing@rock-chips.com/
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
When enable pclk_vo1grf,will enable pclk_vo1_root and hclk_vo1.
>>> };
>>>
>>> This seems breaking syscon for vo1_grf and observed a bus error
>>> while accessing regmap.
>> I investigated the issue you are seeing some weeks ago when my
>> co-workers started to work on HDMI RX and TX. You are probably
>> just missing this patch:
>>
>> https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/ecc6415344957fa88356cec10f8b75a9da603a7b
> In fact, I tried this solution as well, by connecting the PCLK_VO1GRF.
>
> vo1_grf: syscon@fd5a8000 {
> compatible = "rockchip,rk3588-vo-grf", "syscon";
> reg = <0x0 0xfd5a8000 0x0 0x100>;
> clocks = <&cru PCLK_VO1GRF>;
> };
>
> But the result seems the same, accessing vo1_grf triggers an abort [1]
>
> [1] https://gist.github.com/openedev/e241da8180341ffbf4dc6a26de7efa31
>
> Thanks,
> Jagan.
--
张晴
瑞芯微电子股份有限公司
Rockchip Electronics Co.,Ltd
地址：福建省福州市铜盘路软件大道89号软件园A区21号楼
Add:No.21 Building, A District, No.89 Software Boulevard Fuzhou, Fujian 350003, P.R.China
Tel:+86-0591-83991906-8601
邮编：350003
E-mail:elaine.zhang@rock-chips.com
****************************************************************************
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-07-28 2:52 ` zhangqing
0 siblings, 0 replies; 30+ messages in thread
From: zhangqing @ 2023-07-28 2:52 UTC (permalink / raw)
To: Jagan Teki, Sebastian Reichel
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Finley Xiao,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, kernel, Vincent Legoll
在 2023/7/14 13:33, Jagan Teki 写道:
> Hi Sebastian,
>
> On Fri, 14 Jul 2023 at 01:08, Sebastian Reichel
> <sebastian.reichel@collabora.com> wrote:
>> Hello Jagan,
>>
>> On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
>>> On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
>>> <sebastian.reichel@collabora.com> wrote:
>>> [...]
>>>> + * Recent Rockchip SoCs have a new hardware block called Native Interface
>>>> + * Unit (NIU), which gates clocks to devices behind them. These effectively
>>>> + * need two parent clocks.
>>>> + *
>>>> + * Downstream enables the linked clock via runtime PM whenever the gate is
>>>> + * enabled. This implementation uses separate clock nodes for each of the
>>>> + * linked gate clocks, which leaks parts of the clock tree into DT.
>>>> + *
>>>> + * The GATE_LINK macro instead takes the second parent via 'linkname', but
>>>> + * ignores the information. Once the clock framework is ready to handle it, the
>>>> + * information should be passed on here. But since these clocks are required to
>>>> + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
>>>> + * clocks critical until a better solution is available. This will waste some
>>>> + * power, but avoids leaking implementation details into DT or hanging the
>>>> + * system.
>>>> */
>>> Does it mean the clk-link topology in the downstream kernel can be
>>> reused the same as normal clock notation?
>> Yes.
>>
>>> For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
>>> of routing to pclk_vo1_grf(done downstream)
>>> vo1_grf: syscon@fd5a8000 {
>>> compatible = "rockchip,rk3588-vo-grf", "syscon";
>>> reg = <0x0 0xfd5a8000 0x0 0x100>;
>>> clocks = <&cru HCLK_VO1>;
>> You need PCLK_VO1 (which is currently not exposed; I somehow missed
>> it).
Maybe this submission is helpful
The true GATE_LINK callback is implemented.
https://patchwork.kernel.org/project/linux-clk/patch/20230728020810.29732-4-zhangqing@rock-chips.com/
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
When enable pclk_vo1grf,will enable pclk_vo1_root and hclk_vo1.
>>> };
>>>
>>> This seems breaking syscon for vo1_grf and observed a bus error
>>> while accessing regmap.
>> I investigated the issue you are seeing some weeks ago when my
>> co-workers started to work on HDMI RX and TX. You are probably
>> just missing this patch:
>>
>> https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/ecc6415344957fa88356cec10f8b75a9da603a7b
> In fact, I tried this solution as well, by connecting the PCLK_VO1GRF.
>
> vo1_grf: syscon@fd5a8000 {
> compatible = "rockchip,rk3588-vo-grf", "syscon";
> reg = <0x0 0xfd5a8000 0x0 0x100>;
> clocks = <&cru PCLK_VO1GRF>;
> };
>
> But the result seems the same, accessing vo1_grf triggers an abort [1]
>
> [1] https://gist.github.com/openedev/e241da8180341ffbf4dc6a26de7efa31
>
> Thanks,
> Jagan.
--
张晴
瑞芯微电子股份有限公司
Rockchip Electronics Co.,Ltd
地址：福建省福州市铜盘路软件大道89号软件园A区21号楼
Add:No.21 Building, A District, No.89 Software Boulevard Fuzhou, Fujian 350003, P.R.China
Tel:+86-0591-83991906-8601
邮编：350003
E-mail:elaine.zhang@rock-chips.com
****************************************************************************
保密提示：本邮件及其附件含有机密信息，仅发送给本邮件所指特定收件人。若非该特定收件人，请勿复制、使用或披露本邮件的任何内容。若误收本邮件，请从系统中永久性删除本邮件及所有附件，并以回复邮件或其他方式即刻告知发件人。福州瑞芯微电子有限公司拥有本邮件信息的著作权及解释权，禁止任何未经授权许可的侵权行为。
IMPORTANT NOTICE: This email is from Fuzhou Rockchip Electronics Co., Ltd .The contents of this email and any attachments may contain information that is privileged, confidential and/or exempt from disclosure under applicable law and relevant NDA. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information is STRICTLY PROHIBITED. Please immediately contact the sender as soon as possible and destroy the material in its entirety in any format. Thank you.
****************************************************************************
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused
@ 2023-07-28 2:52 ` zhangqing
0 siblings, 0 replies; 30+ messages in thread
From: zhangqing @ 2023-07-28 2:52 UTC (permalink / raw)
To: Jagan Teki, Sebastian Reichel
Cc: Heiko Stuebner, linux-rockchip, Peter Geis, Finley Xiao,
Michael Turquette, Stephen Boyd, Boris Brezillon, linux-clk,
linux-arm-kernel, linux-kernel, kernel, Vincent Legoll
在 2023/7/14 13:33, Jagan Teki 写道:
> Hi Sebastian,
>
> On Fri, 14 Jul 2023 at 01:08, Sebastian Reichel
> <sebastian.reichel@collabora.com> wrote:
>> Hello Jagan,
>>
>> On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
>>> On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
>>> <sebastian.reichel@collabora.com> wrote:
>>> [...]
>>>> + * Recent Rockchip SoCs have a new hardware block called Native Interface
>>>> + * Unit (NIU), which gates clocks to devices behind them. These effectively
>>>> + * need two parent clocks.
>>>> + *
>>>> + * Downstream enables the linked clock via runtime PM whenever the gate is
>>>> + * enabled. This implementation uses separate clock nodes for each of the
>>>> + * linked gate clocks, which leaks parts of the clock tree into DT.
>>>> + *
>>>> + * The GATE_LINK macro instead takes the second parent via 'linkname', but
>>>> + * ignores the information. Once the clock framework is ready to handle it, the
>>>> + * information should be passed on here. But since these clocks are required to
>>>> + * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
>>>> + * clocks critical until a better solution is available. This will waste some
>>>> + * power, but avoids leaking implementation details into DT or hanging the
>>>> + * system.
>>>> */
>>> Does it mean the clk-link topology in the downstream kernel can be
>>> reused the same as normal clock notation?
>> Yes.
>>
>>> For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
>>> of routing to pclk_vo1_grf(done downstream)
>>> vo1_grf: syscon@fd5a8000 {
>>> compatible = "rockchip,rk3588-vo-grf", "syscon";
>>> reg = <0x0 0xfd5a8000 0x0 0x100>;
>>> clocks = <&cru HCLK_VO1>;
>> You need PCLK_VO1 (which is currently not exposed; I somehow missed
>> it).
Maybe this submission is helpful
The true GATE_LINK callback is implemented.
https://patchwork.kernel.org/project/linux-clk/patch/20230728020810.29732-4-zhangqing@rock-chips.com/
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
When enable pclk_vo1grf,will enable pclk_vo1_root and hclk_vo1.
>>> };
>>>
>>> This seems breaking syscon for vo1_grf and observed a bus error
>>> while accessing regmap.
>> I investigated the issue you are seeing some weeks ago when my
>> co-workers started to work on HDMI RX and TX. You are probably
>> just missing this patch:
>>
>> https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/ecc6415344957fa88356cec10f8b75a9da603a7b
> In fact, I tried this solution as well, by connecting the PCLK_VO1GRF.
>
> vo1_grf: syscon@fd5a8000 {
> compatible = "rockchip,rk3588-vo-grf", "syscon";
> reg = <0x0 0xfd5a8000 0x0 0x100>;
> clocks = <&cru PCLK_VO1GRF>;
> };
>
> But the result seems the same, accessing vo1_grf triggers an abort [1]
>
> [1] https://gist.github.com/openedev/e241da8180341ffbf4dc6a26de7efa31
>
> Thanks,
> Jagan.
--
张晴
瑞芯微电子股份有限公司
Rockchip Electronics Co.,Ltd
地址：福建省福州市铜盘路软件大道89号软件园A区21号楼
Add:No.21 Building, A District, No.89 Software Boulevard Fuzhou, Fujian 350003, P.R.China
Tel:+86-0591-83991906-8601
邮编：350003
E-mail:elaine.zhang@rock-chips.com
****************************************************************************
保密提示：本邮件及其附件含有机密信息，仅发送给本邮件所指特定收件人。若非该特定收件人，请勿复制、使用或披露本邮件的任何内容。若误收本邮件，请从系统中永久性删除本邮件及所有附件，并以回复邮件或其他方式即刻告知发件人。福州瑞芯微电子有限公司拥有本邮件信息的著作权及解释权，禁止任何未经授权许可的侵权行为。
IMPORTANT NOTICE: This email is from Fuzhou Rockchip Electronics Co., Ltd .The contents of this email and any attachments may contain information that is privileged, confidential and/or exempt from disclosure under applicable law and relevant NDA. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information is STRICTLY PROHIBITED. Please immediately contact the sender as soon as possible and destroy the material in its entirety in any format. Thank you.
****************************************************************************
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2023-07-28 2:55 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-03 19:32 [PATCHv2 0/2] Improve RK3588 clocks and power domains support Sebastian Reichel
2023-04-03 19:32 ` Sebastian Reichel
2023-04-03 19:32 ` Sebastian Reichel
2023-04-03 19:32 ` [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused Sebastian Reichel
2023-04-03 19:32 ` Sebastian Reichel
2023-04-03 19:32 ` Sebastian Reichel
2023-07-13 14:55 ` Jagan Teki
2023-07-13 14:55 ` Jagan Teki
2023-07-13 14:55 ` Jagan Teki
2023-07-13 19:38 ` Sebastian Reichel
2023-07-13 19:38 ` Sebastian Reichel
2023-07-13 19:38 ` Sebastian Reichel
[not found] ` <20230714091150883537486@rock-chips.com>
2023-07-14 5:28 ` Jagan Teki
2023-07-14 5:28 ` Jagan Teki
2023-07-14 5:28 ` Jagan Teki
2023-07-14 5:33 ` Jagan Teki
2023-07-14 5:33 ` Jagan Teki
2023-07-14 5:33 ` Jagan Teki
2023-07-28 2:52 ` zhangqing
2023-07-28 2:52 ` zhangqing
2023-07-28 2:52 ` zhangqing
2023-04-03 19:32 ` [PATCHv2 2/2] soc: rockchip: power-domain: add rk3588 mem module support Sebastian Reichel
2023-04-03 19:32 ` Sebastian Reichel
2023-04-03 19:32 ` Sebastian Reichel
2023-04-17 23:18 ` (subset) [PATCHv2 0/2] Improve RK3588 clocks and power domains support Heiko Stuebner
2023-04-17 23:18 ` Heiko Stuebner
2023-04-17 23:18 ` Heiko Stuebner
2023-04-21 12:56 ` Heiko Stuebner
2023-04-21 12:56 ` Heiko Stuebner
2023-04-21 12:56 ` Heiko Stuebner
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