[PULL 0/2] target-arm queue

[PULL 0/2] target-arm queue

[Peter Maydell]

This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
we were using uninitialized data for the guarded bit when
combining stage 1 and stage 2 attrs.

thanks
-- PMM

The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:

  Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410

for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:

  target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)

----------------------------------------------------------------
target-arm: Fix bug where we weren't initializing
            guarded bit state when combining S1/S2 attrs

----------------------------------------------------------------
Richard Henderson (2):
      target/arm: PTE bit GP only applies to stage1
      target/arm: Copy guarded bit in combine_cacheattrs

 target/arm/ptw.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

[PULL 1/2] target/arm: PTE bit GP only applies to stage1

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

Only perform the extract of GP during the stage1 walk.

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index ec3f51782aa..58a6de09bc9 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1585,11 +1585,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
         result->f.attrs.secure = false;
     }
 
-    /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB.  */
-    if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
-        result->f.guarded = extract64(attrs, 50, 1); /* GP */
-    }
-
     if (regime_is_stage2(mmu_idx)) {
         result->cacheattrs.is_s2_format = true;
         result->cacheattrs.attrs = extract32(attrs, 2, 4);
@@ -1600,6 +1595,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
         assert(attrindx <= 7);
         result->cacheattrs.is_s2_format = false;
         result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
+
+        /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
+        if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
+            result->f.guarded = extract64(attrs, 50, 1); /* GP */
+        }
     }
 
     /*
-- 
2.34.1

[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

The guarded bit comes from the stage1 walk.

Fixes: Coverity CID 1507929
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 58a6de09bc9..6d72950a795 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2576,6 +2576,7 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
 
     assert(!s1.is_s2_format);
     ret.is_s2_format = false;
+    ret.guarded = s1.guarded;
 
     if (s1.attrs == 0xf0) {
         tagged = true;
-- 
2.34.1

Re: [PULL 0/2] target-arm queue

[Peter Maydell]

On Mon, 10 Apr 2023 at 15:14, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
> we were using uninitialized data for the guarded bit when
> combining stage 1 and stage 2 attrs.
>
> thanks
> -- PMM
>
> The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
>
>   Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
>
> for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
>
>   target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
>
> ----------------------------------------------------------------
> target-arm: Fix bug where we weren't initializing
>             guarded bit state when combining S1/S2 attrs
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.

-- PMM

[PULL 0/2] target-arm queue

[Peter Maydell]

Two bug fixes for 9.0...

-- PMM

The following changes since commit ce64e6224affb8b4e4b019f76d2950270b391af5:

  Merge tag 'qemu-sparc-20240404' of https://github.com/mcayland/qemu into staging (2024-04-04 15:28:06 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240408

for you to fetch changes up to 19b254e86a900dc5ee332e3ac0baf9c521301abf:

  target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3 (2024-04-08 15:38:53 +0100)

----------------------------------------------------------------
target-arm:
 * Use correct SecuritySpace for AArch64 AT ops at EL3
 * Fix CNTPOFF_EL2 trap to missing EL3

----------------------------------------------------------------
Peter Maydell (1):
      target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3

Pierre-Clément Tosi (1):
      target/arm: Fix CNTPOFF_EL2 trap to missing EL3

 target/arm/helper.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

Re: [PULL 0/2] target-arm queue

[Peter Maydell]

On Mon, 8 Apr 2024 at 16:23, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Two bug fixes for 9.0...
>
> -- PMM
>
> The following changes since commit ce64e6224affb8b4e4b019f76d2950270b391af5:
>
>   Merge tag 'qemu-sparc-20240404' of https://github.com/mcayland/qemu into staging (2024-04-04 15:28:06 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240408
>
> for you to fetch changes up to 19b254e86a900dc5ee332e3ac0baf9c521301abf:
>
>   target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3 (2024-04-08 15:38:53 +0100)
>
> ----------------------------------------------------------------
> target-arm:
>  * Use correct SecuritySpace for AArch64 AT ops at EL3
>  * Fix CNTPOFF_EL2 trap to missing EL3
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.

-- PMM

[PULL 0/2] target-arm queue

[Peter Maydell]

Hi; this pull request has a couple of fixes for bugs in
the Arm page-table-walk code, which arrived in the last
day or so.

I'm sending this out now in the hope it might just sneak
in before rc2 gets tagged, so the fixes can get more
testing time before the 7.2 release; but if they don't
make it then this should go into rc3.

thanks
-- PMM

The following changes since commit 6d71357a3b651ec9db126e4862b77e13165427f5:

  rtl8139: honor large send MSS value (2022-11-21 09:28:43 -0500)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221122

for you to fetch changes up to 15f8f4671afd22491ce99d28a296514717fead4f:

  target/arm: Use signed quantity to represent VMSAv8-64 translation level (2022-11-22 16:10:25 +0000)

----------------------------------------------------------------
target-arm:
 * Fix broken 5-level pagetable handling
 * Fix debug accesses when EL2 is present

----------------------------------------------------------------
Ard Biesheuvel (1):
      target/arm: Use signed quantity to represent VMSAv8-64 translation level

Peter Maydell (1):
      target/arm: Don't do two-stage lookup if stage 2 is disabled

 target/arm/ptw.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

Re: [PULL 0/2] target-arm queue

[Stefan Hajnoczi]

[-- Attachment #1: Type: text/plain, Size: 115 bytes --]

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 484 bytes --]

[PULL 0/2] target-arm queue

[Peter Maydell]

Couple of trivial fixes for rc3...

The following changes since commit 20661b75ea6093f5e59079d00a778a972d6732c5:

  Merge tag 'pull-ppc-20220404' of https://github.com/legoater/qemu into staging (2022-04-04 15:48:55 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220405

for you to fetch changes up to 80b952bb694a90f7e530d407b01066894e64a443:

  docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation. (2022-04-05 09:29:28 +0100)

----------------------------------------------------------------
target-arm queue:
 * docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.
 * xlnx-bbram: hw/nvram: Fix uninitialized Error *

----------------------------------------------------------------
Pavel Pisa (1):
      docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.

Tong Ho (1):
      xlnx-bbram: hw/nvram: Fix uninitialized Error *

 docs/system/devices/can.rst | 6 +++---
 hw/nvram/xlnx-bbram.c       | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

Re: [PULL 0/2] target-arm queue

[Peter Maydell]

On Tue, 5 Apr 2022 at 10:26, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Couple of trivial fixes for rc3...
>
> The following changes since commit 20661b75ea6093f5e59079d00a778a972d6732c5:
>
>   Merge tag 'pull-ppc-20220404' of https://github.com/legoater/qemu into staging (2022-04-04 15:48:55 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220405
>
> for you to fetch changes up to 80b952bb694a90f7e530d407b01066894e64a443:
>
>   docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation. (2022-04-05 09:29:28 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.
>  * xlnx-bbram: hw/nvram: Fix uninitialized Error *
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.

-- PMM

[PULL 0/2] target-arm queue

[Peter Maydell]

Just two small bug fixes for the next rc.

The following changes since commit f345abe36527a8b575482bb5a0616f43952bf1f4:

  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-03-25 10:14:47 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220325

for you to fetch changes up to c7ca3ad5e756e263daf082c315e311593ccec3d1:

  hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() logging (2022-03-25 14:41:06 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() logging
 * target/arm: Fix sve_ld1_z and sve_st1_z vs MMIO

----------------------------------------------------------------
Peter Maydell (1):
      hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() logging

Richard Henderson (1):
      target/arm: Fix sve_ld1_z and sve_st1_z vs MMIO

 hw/intc/arm_gicv3_its.c |  4 ++--
 target/arm/sve_helper.c | 10 ++++++++--
 2 files changed, 10 insertions(+), 4 deletions(-)

Re: [PULL 0/2] target-arm queue

[Peter Maydell]

On Fri, 25 Mar 2022 at 14:57, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Just two small bug fixes for the next rc.
>
> The following changes since commit f345abe36527a8b575482bb5a0616f43952bf1f4:
>
>   Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-03-25 10:14:47 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220325
>
> for you to fetch changes up to c7ca3ad5e756e263daf082c315e311593ccec3d1:
>
>   hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() logging (2022-03-25 14:41:06 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() logging
>  * target/arm: Fix sve_ld1_z and sve_st1_z vs MMIO
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.

-- PMM

[PULL 0/2] target-arm queue

[Peter Maydell]

Couple of last-minute things for rc3...

-- PMM

The following changes since commit d15532d91be177e7528310e0110e39f915779a99:

  Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into staging (2020-08-04 11:53:20 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200804

for you to fetch changes up to d250bb19ced3b702c7c37731855f6876d0cc7995:

  target/arm: Fix decode of LDRA[AB] instructions (2020-08-04 16:40:19 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix decode of LDRA[AB] instructions
 * docs/devel: Document decodetree no-overlap groups

----------------------------------------------------------------
Peter Collingbourne (1):
      target/arm: Fix decode of LDRA[AB] instructions

Richard Henderson (1):
      docs/devel: Document decodetree no-overlap groups

 docs/devel/decodetree.rst  | 29 ++++++++++++++++++-----------
 target/arm/translate-a64.c |  6 ++++--
 2 files changed, 22 insertions(+), 13 deletions(-)

Re: [PULL 0/2] target-arm queue

[Peter Maydell]

On Tue, 4 Aug 2020 at 17:08, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Couple of last-minute things for rc3...
>
> -- PMM
>
> The following changes since commit d15532d91be177e7528310e0110e39f915779a99:
>
>   Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into staging (2020-08-04 11:53:20 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200804
>
> for you to fetch changes up to d250bb19ced3b702c7c37731855f6876d0cc7995:
>
>   target/arm: Fix decode of LDRA[AB] instructions (2020-08-04 16:40:19 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * Fix decode of LDRA[AB] instructions
>  * docs/devel: Document decodetree no-overlap groups
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.

-- PMM