* [PATCH v2 00/13] SM63(50|75) DPU support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Rob Herring, Konrad Dybcio
v1 -> v2:
- Rebase on the DPU catalog rework and INTF_TE
- Fix QSEED(3L/4) discrepancies
- Fixed DMA/cursor discrepancies for 6350
- No deduplication, that's gonna be handled in catalogrework 2:
"the return of the catalogrework"
- Split MDSS & DPU binding additions
- Drop "Allow variable SSPP/INTF_BLK size", that got in w/ the rework
- Split MDSS and DPU additions
- Pick up Rob's acks
Depends on (and based on): https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v2-0-ef76c877eb97@somainline.org/T/#t
v1: https://lore.kernel.org/linux-arm-msm/20230211122656.1479141-1-konrad.dybcio@linaro.org/
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (13):
dt-bindings: display/msm: dsi-controller-main: Add SM6350
dt-bindings: display/msm: dsi-controller-main: Add SM6375
dt-bindings: display/msm: Add SM6350 DPU
dt-bindings: display/msm: Add SM6350 MDSS
dt-bindings: display/msm: Add SM6375 DPU
dt-bindings: display/msm: Add SM6375 MDSS
drm/msm/dpu: Add SM6350 support
drm/msm: mdss: Add SM6350 support
drm/msm/dpu: Add SM6375 support
drm/msm: mdss: Add SM6375 support
iommu/arm-smmu-qcom: Add SM6375 DPU compatible
iommu/arm-smmu-qcom: Add SM6350 DPU compatible
iommu/arm-smmu-qcom: Sort the compatible list alphabetically
.../bindings/display/msm/dsi-controller-main.yaml | 4 +
.../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 +++++++++
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 ++++++++++++++++++++
.../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 ++++++++++
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 186 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +
drivers/gpu/drm/msm/msm_mdss.c | 19 ++
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 +-
12 files changed, 1016 insertions(+), 2 deletions(-)
---
base-commit: eaf6956f6dfdbba2c53a668248f8213b9e01bc51
change-id: 20230411-topic-straitlagoon_mdss-8f34cacd5e26
Best regards,
--
Konrad Dybcio <konrad.dybcio@linaro.org>
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH v2 00/13] SM63(50|75) DPU support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, Konrad Dybcio, linux-kernel,
dri-devel, Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
v1 -> v2:
- Rebase on the DPU catalog rework and INTF_TE
- Fix QSEED(3L/4) discrepancies
- Fixed DMA/cursor discrepancies for 6350
- No deduplication, that's gonna be handled in catalogrework 2:
"the return of the catalogrework"
- Split MDSS & DPU binding additions
- Drop "Allow variable SSPP/INTF_BLK size", that got in w/ the rework
- Split MDSS and DPU additions
- Pick up Rob's acks
Depends on (and based on): https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v2-0-ef76c877eb97@somainline.org/T/#t
v1: https://lore.kernel.org/linux-arm-msm/20230211122656.1479141-1-konrad.dybcio@linaro.org/
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (13):
dt-bindings: display/msm: dsi-controller-main: Add SM6350
dt-bindings: display/msm: dsi-controller-main: Add SM6375
dt-bindings: display/msm: Add SM6350 DPU
dt-bindings: display/msm: Add SM6350 MDSS
dt-bindings: display/msm: Add SM6375 DPU
dt-bindings: display/msm: Add SM6375 MDSS
drm/msm/dpu: Add SM6350 support
drm/msm: mdss: Add SM6350 support
drm/msm/dpu: Add SM6375 support
drm/msm: mdss: Add SM6375 support
iommu/arm-smmu-qcom: Add SM6375 DPU compatible
iommu/arm-smmu-qcom: Add SM6350 DPU compatible
iommu/arm-smmu-qcom: Sort the compatible list alphabetically
.../bindings/display/msm/dsi-controller-main.yaml | 4 +
.../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 +++++++++
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 ++++++++++++++++++++
.../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 ++++++++++
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 186 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +
drivers/gpu/drm/msm/msm_mdss.c | 19 ++
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 +-
12 files changed, 1016 insertions(+), 2 deletions(-)
---
base-commit: eaf6956f6dfdbba2c53a668248f8213b9e01bc51
change-id: 20230411-topic-straitlagoon_mdss-8f34cacd5e26
Best regards,
--
Konrad Dybcio <konrad.dybcio@linaro.org>
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH v2 00/13] SM63(50|75) DPU support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Rob Herring, Konrad Dybcio
v1 -> v2:
- Rebase on the DPU catalog rework and INTF_TE
- Fix QSEED(3L/4) discrepancies
- Fixed DMA/cursor discrepancies for 6350
- No deduplication, that's gonna be handled in catalogrework 2:
"the return of the catalogrework"
- Split MDSS & DPU binding additions
- Drop "Allow variable SSPP/INTF_BLK size", that got in w/ the rework
- Split MDSS and DPU additions
- Pick up Rob's acks
Depends on (and based on): https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v2-0-ef76c877eb97@somainline.org/T/#t
v1: https://lore.kernel.org/linux-arm-msm/20230211122656.1479141-1-konrad.dybcio@linaro.org/
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (13):
dt-bindings: display/msm: dsi-controller-main: Add SM6350
dt-bindings: display/msm: dsi-controller-main: Add SM6375
dt-bindings: display/msm: Add SM6350 DPU
dt-bindings: display/msm: Add SM6350 MDSS
dt-bindings: display/msm: Add SM6375 DPU
dt-bindings: display/msm: Add SM6375 MDSS
drm/msm/dpu: Add SM6350 support
drm/msm: mdss: Add SM6350 support
drm/msm/dpu: Add SM6375 support
drm/msm: mdss: Add SM6375 support
iommu/arm-smmu-qcom: Add SM6375 DPU compatible
iommu/arm-smmu-qcom: Add SM6350 DPU compatible
iommu/arm-smmu-qcom: Sort the compatible list alphabetically
.../bindings/display/msm/dsi-controller-main.yaml | 4 +
.../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 +++++++++
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 ++++++++++++++++++++
.../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 ++++++++++
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 186 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +
drivers/gpu/drm/msm/msm_mdss.c | 19 ++
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 +-
12 files changed, 1016 insertions(+), 2 deletions(-)
---
base-commit: eaf6956f6dfdbba2c53a668248f8213b9e01bc51
change-id: 20230411-topic-straitlagoon_mdss-8f34cacd5e26
Best regards,
--
Konrad Dybcio <konrad.dybcio@linaro.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* [PATCH v2 01/13] dt-bindings: display/msm: dsi-controller-main: Add SM6350
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Rob Herring
Add the DSI host found on SM6350.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index e6c1ebfe8a32..6f367a1fabf8 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,sdm660-dsi-ctrl
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6350-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -285,6 +286,7 @@ allOf:
contains:
enum:
- qcom,msm8998-dsi-ctrl
+ - qcom,sm6350-dsi-ctrl
then:
properties:
clocks:
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 01/13] dt-bindings: display/msm: dsi-controller-main: Add SM6350
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Rob Herring
Add the DSI host found on SM6350.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index e6c1ebfe8a32..6f367a1fabf8 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,sdm660-dsi-ctrl
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6350-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -285,6 +286,7 @@ allOf:
contains:
enum:
- qcom,msm8998-dsi-ctrl
+ - qcom,sm6350-dsi-ctrl
then:
properties:
clocks:
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 01/13] dt-bindings: display/msm: dsi-controller-main: Add SM6350
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Add the DSI host found on SM6350.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index e6c1ebfe8a32..6f367a1fabf8 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,sdm660-dsi-ctrl
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6350-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -285,6 +286,7 @@ allOf:
contains:
enum:
- qcom,msm8998-dsi-ctrl
+ - qcom,sm6350-dsi-ctrl
then:
properties:
clocks:
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 02/13] dt-bindings: display/msm: dsi-controller-main: Add SM6375
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Rob Herring
Add the DSI host found on SM6375.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index 6f367a1fabf8..f7dc05a65420 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6350-dsi-ctrl
+ - qcom,sm6375-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -354,6 +355,7 @@ allOf:
enum:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6375-dsi-ctrl
then:
properties:
clocks:
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 02/13] dt-bindings: display/msm: dsi-controller-main: Add SM6375
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Add the DSI host found on SM6375.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index 6f367a1fabf8..f7dc05a65420 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6350-dsi-ctrl
+ - qcom,sm6375-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -354,6 +355,7 @@ allOf:
enum:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6375-dsi-ctrl
then:
properties:
clocks:
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 02/13] dt-bindings: display/msm: dsi-controller-main: Add SM6375
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Rob Herring
Add the DSI host found on SM6375.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index 6f367a1fabf8..f7dc05a65420 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6350-dsi-ctrl
+ - qcom,sm6375-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -354,6 +355,7 @@ allOf:
enum:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6375-dsi-ctrl
then:
properties:
clocks:
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Document the SM6350 DPU.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
new file mode 100644
index 000000000000..979fcf81afc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SM6350 target
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display axi clock
+ - description: Display ahb clock
+ - description: Display rot clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+ - const: rot
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ power-domains = <&rpmhpd SM6350_CX>;
+ operating-points-v2 = <&mdp_opp_table>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+...
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Document the SM6350 DPU.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
new file mode 100644
index 000000000000..979fcf81afc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SM6350 target
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display axi clock
+ - description: Display ahb clock
+ - description: Display rot clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+ - const: rot
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ power-domains = <&rpmhpd SM6350_CX>;
+ operating-points-v2 = <&mdp_opp_table>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+...
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Document the SM6350 DPU.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
new file mode 100644
index 000000000000..979fcf81afc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SM6350 target
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display axi clock
+ - description: Display ahb clock
+ - description: Display rot clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+ - const: rot
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ power-domains = <&rpmhpd SM6350_CX>;
+ operating-points-v2 = <&mdp_opp_table>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+...
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 04/13] dt-bindings: display/msm: Add SM6350 MDSS
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Document the SM6350 MDSS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++++++
1 file changed, 214 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
new file mode 100644
index 000000000000..6674040d2172
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
@@ -0,0 +1,214 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6350 Display MDSS
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+
+description:
+ SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AXI clock from gcc
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6350-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,dsi-phy-10nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sm6350-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x800 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ assigned-clock-rates = <300000000>,
+ <19200000>,
+ <19200000>,
+ <19200000>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM6350_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM6350_MX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 04/13] dt-bindings: display/msm: Add SM6350 MDSS
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Document the SM6350 MDSS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++++++
1 file changed, 214 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
new file mode 100644
index 000000000000..6674040d2172
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
@@ -0,0 +1,214 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6350 Display MDSS
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+
+description:
+ SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AXI clock from gcc
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6350-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,dsi-phy-10nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sm6350-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x800 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ assigned-clock-rates = <300000000>,
+ <19200000>,
+ <19200000>,
+ <19200000>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM6350_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM6350_MX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 04/13] dt-bindings: display/msm: Add SM6350 MDSS
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Document the SM6350 MDSS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++++++
1 file changed, 214 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
new file mode 100644
index 000000000000..6674040d2172
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
@@ -0,0 +1,214 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6350 Display MDSS
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+
+description:
+ SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AXI clock from gcc
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6350-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,dsi-phy-10nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sm6350-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x800 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ assigned-clock-rates = <300000000>,
+ <19200000>,
+ <19200000>,
+ <19200000>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM6350_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM6350_MX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 05/13] dt-bindings: display/msm: Add SM6375 DPU
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Document SM6375 DPU.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 +++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
new file mode 100644
index 000000000000..76dc5a7efebf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SM6375 target
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display iface clock
+ - description: Display bus clock
+ - description: Display core clock
+ - description: Display lut clock
+ - description: Display rot clock
+ - description: Display vsync clock
+ - description: Display throttle clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+ - const: lut
+ - const: rot
+ - const: vsync
+ - const: throttle
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6375-dpu";
+ reg = <0x05e01000 0x8e030>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "lut",
+ "rot",
+ "vsync",
+ "throttle";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+...
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 05/13] dt-bindings: display/msm: Add SM6375 DPU
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Document SM6375 DPU.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 +++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
new file mode 100644
index 000000000000..76dc5a7efebf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SM6375 target
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display iface clock
+ - description: Display bus clock
+ - description: Display core clock
+ - description: Display lut clock
+ - description: Display rot clock
+ - description: Display vsync clock
+ - description: Display throttle clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+ - const: lut
+ - const: rot
+ - const: vsync
+ - const: throttle
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6375-dpu";
+ reg = <0x05e01000 0x8e030>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "lut",
+ "rot",
+ "vsync",
+ "throttle";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+...
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 05/13] dt-bindings: display/msm: Add SM6375 DPU
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Document SM6375 DPU.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 +++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
new file mode 100644
index 000000000000..76dc5a7efebf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SM6375 target
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display iface clock
+ - description: Display bus clock
+ - description: Display core clock
+ - description: Display lut clock
+ - description: Display rot clock
+ - description: Display vsync clock
+ - description: Display throttle clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+ - const: lut
+ - const: rot
+ - const: vsync
+ - const: throttle
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6375-dpu";
+ reg = <0x05e01000 0x8e030>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "lut",
+ "rot",
+ "vsync",
+ "throttle";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+...
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 06/13] dt-bindings: display/msm: Add SM6375 MDSS
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
1 file changed, 216 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
new file mode 100644
index 000000000000..fb56971ea2a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6375 Display MDSS
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description:
+ SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dsi-phy-7nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@5e00000 {
+ compatible = "qcom,sm6375-mdss";
+ reg = <0x05e00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "ahb", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@5e01000 {
+ compatible = "qcom,sm6375-dpu";
+ reg = <0x05e01000 0x8e030>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "lut",
+ "rot",
+ "vsync",
+ "throttle";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@5e94000 {
+ compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x05e94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDMX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@5e94400 {
+ compatible = "qcom,sm6375-dsi-phy-7nm";
+ reg = <0x05e94400 0x200>,
+ <0x05e94600 0x280>,
+ <0x05e94900 0x264>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 06/13] dt-bindings: display/msm: Add SM6375 MDSS
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
1 file changed, 216 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
new file mode 100644
index 000000000000..fb56971ea2a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6375 Display MDSS
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description:
+ SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dsi-phy-7nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@5e00000 {
+ compatible = "qcom,sm6375-mdss";
+ reg = <0x05e00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "ahb", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@5e01000 {
+ compatible = "qcom,sm6375-dpu";
+ reg = <0x05e01000 0x8e030>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "lut",
+ "rot",
+ "vsync",
+ "throttle";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@5e94000 {
+ compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x05e94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDMX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@5e94400 {
+ compatible = "qcom,sm6375-dsi-phy-7nm";
+ reg = <0x05e94400 0x200>,
+ <0x05e94600 0x280>,
+ <0x05e94900 0x264>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 06/13] dt-bindings: display/msm: Add SM6375 MDSS
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
1 file changed, 216 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
new file mode 100644
index 000000000000..fb56971ea2a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6375 Display MDSS
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description:
+ SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dsi-phy-7nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@5e00000 {
+ compatible = "qcom,sm6375-mdss";
+ reg = <0x05e00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "ahb", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@5e01000 {
+ compatible = "qcom,sm6375-dpu";
+ reg = <0x05e01000 0x8e030>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "lut",
+ "rot",
+ "vsync",
+ "throttle";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@5e94000 {
+ compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x05e94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDMX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@5e94400 {
+ compatible = "qcom,sm6375-dsi-phy-7nm";
+ reg = <0x05e94400 0x200>,
+ <0x05e94600 0x280>,
+ <0x05e94900 0x264>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Konrad Dybcio
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 196 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
new file mode 100644
index 000000000000..687a508cbaa6
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_4_SM6350_H
+#define _DPU_6_4_SM6350_H
+
+static const struct dpu_caps sm6350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6350_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
+};
+
+static const struct dpu_lm_cfg sm6350_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
+};
+
+static const struct dpu_dspp_cfg sm6350_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+static struct dpu_pingpong_cfg sm6350_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ -1),
+};
+
+static const struct dpu_intf_cfg sm6350_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_vbif_cfg sm6350_vbif[] = {
+ {
+ .name = "vbif_0", .id = VBIF_RT,
+ .base = 0, .len = 0x1044,
+ .features = BIT(DPU_VBIF_QOS_REMAP),
+ .xin_halt_timeout = 0x4000,
+ .qos_rt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
+ .priority_lvl = sdm845_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 14,
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+ },
+};
+
+static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
+ {.fl = 0, .lut = 0x0011223344556677 },
+ {.fl = 0, .lut = 0x0011223445566777 },
+};
+
+static const struct dpu_perf_cfg sm6350_perf_data = {
+ .max_bw_low = 4200000,
+ .max_bw_high = 5100000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 35,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6350_cfg = {
+ .caps = &sm6350_dpu_caps,
+ .ubwc = &sm6350_ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6350_mdp),
+ .mdp = sm6350_mdp,
+ .ctl_count = ARRAY_SIZE(sm6350_ctl),
+ .ctl = sm6350_ctl,
+ .sspp_count = ARRAY_SIZE(sm6350_sspp),
+ .sspp = sm6350_sspp,
+ .mixer_count = ARRAY_SIZE(sm6350_lm),
+ .mixer = sm6350_lm,
+ .dspp_count = ARRAY_SIZE(sm6350_dspp),
+ .dspp = sm6350_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6350_pp),
+ .pingpong = sm6350_pp,
+ .intf_count = ARRAY_SIZE(sm6350_intf),
+ .intf = sm6350_intf,
+ .vbif_count = ARRAY_SIZE(sm6350_vbif),
+ .vbif = sm6350_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = &sm8250_regdma,
+ .perf = &sm6350_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR)
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index db558a9ae36e..52750b592b36 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_6_0_sm8250.h"
#include "catalog/dpu_6_2_sc7180.h"
#include "catalog/dpu_6_3_sm6115.h"
+#include "catalog/dpu_6_4_sm6350.h"
#include "catalog/dpu_6_5_qcm2290.h"
#include "catalog/dpu_7_0_sm8350.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 756bff1d2185..f9611bd75e02 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
DPU_QOS_LUT_USAGE_LINEAR,
DPU_QOS_LUT_USAGE_MACROTILE,
DPU_QOS_LUT_USAGE_NRT,
+ DPU_QOS_LUT_USAGE_CWB,
+ DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
DPU_QOS_LUT_USAGE_MAX,
};
@@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 0e7a68714e9e..46be7ad8d615 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
+ { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Konrad Dybcio
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 196 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
new file mode 100644
index 000000000000..687a508cbaa6
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_4_SM6350_H
+#define _DPU_6_4_SM6350_H
+
+static const struct dpu_caps sm6350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6350_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
+};
+
+static const struct dpu_lm_cfg sm6350_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
+};
+
+static const struct dpu_dspp_cfg sm6350_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+static struct dpu_pingpong_cfg sm6350_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ -1),
+};
+
+static const struct dpu_intf_cfg sm6350_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_vbif_cfg sm6350_vbif[] = {
+ {
+ .name = "vbif_0", .id = VBIF_RT,
+ .base = 0, .len = 0x1044,
+ .features = BIT(DPU_VBIF_QOS_REMAP),
+ .xin_halt_timeout = 0x4000,
+ .qos_rt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
+ .priority_lvl = sdm845_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 14,
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+ },
+};
+
+static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
+ {.fl = 0, .lut = 0x0011223344556677 },
+ {.fl = 0, .lut = 0x0011223445566777 },
+};
+
+static const struct dpu_perf_cfg sm6350_perf_data = {
+ .max_bw_low = 4200000,
+ .max_bw_high = 5100000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 35,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6350_cfg = {
+ .caps = &sm6350_dpu_caps,
+ .ubwc = &sm6350_ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6350_mdp),
+ .mdp = sm6350_mdp,
+ .ctl_count = ARRAY_SIZE(sm6350_ctl),
+ .ctl = sm6350_ctl,
+ .sspp_count = ARRAY_SIZE(sm6350_sspp),
+ .sspp = sm6350_sspp,
+ .mixer_count = ARRAY_SIZE(sm6350_lm),
+ .mixer = sm6350_lm,
+ .dspp_count = ARRAY_SIZE(sm6350_dspp),
+ .dspp = sm6350_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6350_pp),
+ .pingpong = sm6350_pp,
+ .intf_count = ARRAY_SIZE(sm6350_intf),
+ .intf = sm6350_intf,
+ .vbif_count = ARRAY_SIZE(sm6350_vbif),
+ .vbif = sm6350_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = &sm8250_regdma,
+ .perf = &sm6350_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR)
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index db558a9ae36e..52750b592b36 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_6_0_sm8250.h"
#include "catalog/dpu_6_2_sc7180.h"
#include "catalog/dpu_6_3_sm6115.h"
+#include "catalog/dpu_6_4_sm6350.h"
#include "catalog/dpu_6_5_qcm2290.h"
#include "catalog/dpu_7_0_sm8350.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 756bff1d2185..f9611bd75e02 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
DPU_QOS_LUT_USAGE_LINEAR,
DPU_QOS_LUT_USAGE_MACROTILE,
DPU_QOS_LUT_USAGE_NRT,
+ DPU_QOS_LUT_USAGE_CWB,
+ DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
DPU_QOS_LUT_USAGE_MAX,
};
@@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 0e7a68714e9e..46be7ad8d615 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
+ { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, Konrad Dybcio, linux-kernel,
dri-devel, Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 196 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
new file mode 100644
index 000000000000..687a508cbaa6
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_4_SM6350_H
+#define _DPU_6_4_SM6350_H
+
+static const struct dpu_caps sm6350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6350_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
+};
+
+static const struct dpu_lm_cfg sm6350_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
+};
+
+static const struct dpu_dspp_cfg sm6350_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+static struct dpu_pingpong_cfg sm6350_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ -1),
+};
+
+static const struct dpu_intf_cfg sm6350_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_vbif_cfg sm6350_vbif[] = {
+ {
+ .name = "vbif_0", .id = VBIF_RT,
+ .base = 0, .len = 0x1044,
+ .features = BIT(DPU_VBIF_QOS_REMAP),
+ .xin_halt_timeout = 0x4000,
+ .qos_rt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
+ .priority_lvl = sdm845_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 14,
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+ },
+};
+
+static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
+ {.fl = 0, .lut = 0x0011223344556677 },
+ {.fl = 0, .lut = 0x0011223445566777 },
+};
+
+static const struct dpu_perf_cfg sm6350_perf_data = {
+ .max_bw_low = 4200000,
+ .max_bw_high = 5100000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 35,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6350_cfg = {
+ .caps = &sm6350_dpu_caps,
+ .ubwc = &sm6350_ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6350_mdp),
+ .mdp = sm6350_mdp,
+ .ctl_count = ARRAY_SIZE(sm6350_ctl),
+ .ctl = sm6350_ctl,
+ .sspp_count = ARRAY_SIZE(sm6350_sspp),
+ .sspp = sm6350_sspp,
+ .mixer_count = ARRAY_SIZE(sm6350_lm),
+ .mixer = sm6350_lm,
+ .dspp_count = ARRAY_SIZE(sm6350_dspp),
+ .dspp = sm6350_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6350_pp),
+ .pingpong = sm6350_pp,
+ .intf_count = ARRAY_SIZE(sm6350_intf),
+ .intf = sm6350_intf,
+ .vbif_count = ARRAY_SIZE(sm6350_vbif),
+ .vbif = sm6350_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = &sm8250_regdma,
+ .perf = &sm6350_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR)
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index db558a9ae36e..52750b592b36 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_6_0_sm8250.h"
#include "catalog/dpu_6_2_sc7180.h"
#include "catalog/dpu_6_3_sm6115.h"
+#include "catalog/dpu_6_4_sm6350.h"
#include "catalog/dpu_6_5_qcm2290.h"
#include "catalog/dpu_7_0_sm8350.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 756bff1d2185..f9611bd75e02 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
DPU_QOS_LUT_USAGE_LINEAR,
DPU_QOS_LUT_USAGE_MACROTILE,
DPU_QOS_LUT_USAGE_NRT,
+ DPU_QOS_LUT_USAGE_CWB,
+ DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
DPU_QOS_LUT_USAGE_MAX,
};
@@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 0e7a68714e9e..46be7ad8d615 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
+ { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add support for MDSS on SM6350.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e8c93731aaa1..4e3a5f0c303c 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data = {
.highest_bank_bit = 2,
};
+static const struct msm_mdss_data sm6350_data = {
+ .ubwc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 6,
+ .ubwc_static = 0x1e,
+ .highest_bank_bit = 1,
+};
+
static const struct msm_mdss_data sm8150_data = {
.ubwc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
@@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
+ { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
{ .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add support for MDSS on SM6350.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e8c93731aaa1..4e3a5f0c303c 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data = {
.highest_bank_bit = 2,
};
+static const struct msm_mdss_data sm6350_data = {
+ .ubwc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 6,
+ .ubwc_static = 0x1e,
+ .highest_bank_bit = 1,
+};
+
static const struct msm_mdss_data sm8150_data = {
.ubwc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
@@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
+ { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
{ .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Add support for MDSS on SM6350.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e8c93731aaa1..4e3a5f0c303c 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data = {
.highest_bank_bit = 2,
};
+static const struct msm_mdss_data sm6350_data = {
+ .ubwc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 6,
+ .ubwc_static = 0x1e,
+ .highest_bank_bit = 1,
+};
+
static const struct msm_mdss_data sm8150_data = {
.ubwc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
@@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
+ { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
{ .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
5 files changed, 168 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 687a508cbaa6..d46b43964be6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
},
};
-static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
- {.fl = 0, .lut = 0x0011223344556677 },
- {.fl = 0, .lut = 0x0011223445566777 },
-};
-
static const struct dpu_perf_cfg sm6350_perf_data = {
.max_bw_low = 4200000,
.max_bw_high = 5100000,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
new file mode 100644
index 000000000000..19ca0051e072
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_9_SM6375_H
+#define _DPU_6_9_SM6375_H
+
+static const struct dpu_caps sm6375_dpu_caps = {
+ .max_mixer_width = 2048,
+ .max_mixer_blendstages = 0x4,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6375_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6375_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6375_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+};
+
+static const struct dpu_lm_cfg sm6375_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
+ &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
+};
+
+static const struct dpu_dspp_cfg sm6375_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg sm6375_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+};
+
+static const struct dpu_intf_cfg sm6375_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_vbif_cfg sm6375_vbif[] = {
+ {
+ .name = "vbif_0", .id = VBIF_RT,
+ .base = 0, .len = 0x2008,
+ .features = BIT(DPU_VBIF_QOS_REMAP),
+ .xin_halt_timeout = 0x4000,
+ .qos_rp_remap_size = 0x40,
+ .qos_rt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
+ .priority_lvl = sdm845_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 14,
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+ },
+};
+
+static const struct dpu_perf_cfg sm6375_perf_data = {
+ .max_bw_low = 5200000,
+ .max_bw_high = 6200000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0, /* No LLCC on this SoC */
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 24,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6375_cfg = {
+ .caps = &sm6375_dpu_caps,
+ .ubwc = &sm6375_ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6375_mdp),
+ .mdp = sm6375_mdp,
+ .ctl_count = ARRAY_SIZE(sm6375_ctl),
+ .ctl = sm6375_ctl,
+ .sspp_count = ARRAY_SIZE(sm6375_sspp),
+ .sspp = sm6375_sspp,
+ .mixer_count = ARRAY_SIZE(sm6375_lm),
+ .mixer = sm6375_lm,
+ .dspp_count = ARRAY_SIZE(sm6375_dspp),
+ .dspp = sm6375_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6375_pp),
+ .pingpong = sm6375_pp,
+ .intf_count = ARRAY_SIZE(sm6375_intf),
+ .intf = sm6375_intf,
+ .vbif_count = ARRAY_SIZE(sm6375_vbif),
+ .vbif = sm6375_vbif,
+ .perf = &sm6375_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR)
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 52750b592b36..29516273dd6b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
},
};
+static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
+ .maxwidth = 2048,
+ .maxblendstages = 4, /* excluding base layer */
+ .blendstage_base = { /* offsets relative to mixer base */
+ 0x20, 0x38, 0x50, 0x68
+ },
+};
+
/* QCM2290 */
static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
@@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222335777},
};
+static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
+ {.fl = 0, .lut = 0x0011223344556677 },
+ {.fl = 0, .lut = 0x0011223445566777 },
+};
+
static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222223357 },
};
@@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_6_3_sm6115.h"
#include "catalog/dpu_6_4_sm6350.h"
#include "catalog/dpu_6_5_qcm2290.h"
+#include "catalog/dpu_6_9_sm6375.h"
#include "catalog/dpu_7_0_sm8350.h"
#include "catalog/dpu_7_2_sc7280.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f9611bd75e02..b4f193037869 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 46be7ad8d615..980c3c8f8269 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
+ { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
5 files changed, 168 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 687a508cbaa6..d46b43964be6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
},
};
-static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
- {.fl = 0, .lut = 0x0011223344556677 },
- {.fl = 0, .lut = 0x0011223445566777 },
-};
-
static const struct dpu_perf_cfg sm6350_perf_data = {
.max_bw_low = 4200000,
.max_bw_high = 5100000,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
new file mode 100644
index 000000000000..19ca0051e072
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_9_SM6375_H
+#define _DPU_6_9_SM6375_H
+
+static const struct dpu_caps sm6375_dpu_caps = {
+ .max_mixer_width = 2048,
+ .max_mixer_blendstages = 0x4,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6375_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6375_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6375_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+};
+
+static const struct dpu_lm_cfg sm6375_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
+ &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
+};
+
+static const struct dpu_dspp_cfg sm6375_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg sm6375_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+};
+
+static const struct dpu_intf_cfg sm6375_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_vbif_cfg sm6375_vbif[] = {
+ {
+ .name = "vbif_0", .id = VBIF_RT,
+ .base = 0, .len = 0x2008,
+ .features = BIT(DPU_VBIF_QOS_REMAP),
+ .xin_halt_timeout = 0x4000,
+ .qos_rp_remap_size = 0x40,
+ .qos_rt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
+ .priority_lvl = sdm845_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 14,
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+ },
+};
+
+static const struct dpu_perf_cfg sm6375_perf_data = {
+ .max_bw_low = 5200000,
+ .max_bw_high = 6200000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0, /* No LLCC on this SoC */
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 24,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6375_cfg = {
+ .caps = &sm6375_dpu_caps,
+ .ubwc = &sm6375_ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6375_mdp),
+ .mdp = sm6375_mdp,
+ .ctl_count = ARRAY_SIZE(sm6375_ctl),
+ .ctl = sm6375_ctl,
+ .sspp_count = ARRAY_SIZE(sm6375_sspp),
+ .sspp = sm6375_sspp,
+ .mixer_count = ARRAY_SIZE(sm6375_lm),
+ .mixer = sm6375_lm,
+ .dspp_count = ARRAY_SIZE(sm6375_dspp),
+ .dspp = sm6375_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6375_pp),
+ .pingpong = sm6375_pp,
+ .intf_count = ARRAY_SIZE(sm6375_intf),
+ .intf = sm6375_intf,
+ .vbif_count = ARRAY_SIZE(sm6375_vbif),
+ .vbif = sm6375_vbif,
+ .perf = &sm6375_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR)
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 52750b592b36..29516273dd6b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
},
};
+static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
+ .maxwidth = 2048,
+ .maxblendstages = 4, /* excluding base layer */
+ .blendstage_base = { /* offsets relative to mixer base */
+ 0x20, 0x38, 0x50, 0x68
+ },
+};
+
/* QCM2290 */
static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
@@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222335777},
};
+static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
+ {.fl = 0, .lut = 0x0011223344556677 },
+ {.fl = 0, .lut = 0x0011223445566777 },
+};
+
static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222223357 },
};
@@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_6_3_sm6115.h"
#include "catalog/dpu_6_4_sm6350.h"
#include "catalog/dpu_6_5_qcm2290.h"
+#include "catalog/dpu_6_9_sm6375.h"
#include "catalog/dpu_7_0_sm8350.h"
#include "catalog/dpu_7_2_sc7280.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f9611bd75e02..b4f193037869 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 46be7ad8d615..980c3c8f8269 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
+ { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
5 files changed, 168 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 687a508cbaa6..d46b43964be6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
},
};
-static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
- {.fl = 0, .lut = 0x0011223344556677 },
- {.fl = 0, .lut = 0x0011223445566777 },
-};
-
static const struct dpu_perf_cfg sm6350_perf_data = {
.max_bw_low = 4200000,
.max_bw_high = 5100000,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
new file mode 100644
index 000000000000..19ca0051e072
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_9_SM6375_H
+#define _DPU_6_9_SM6375_H
+
+static const struct dpu_caps sm6375_dpu_caps = {
+ .max_mixer_width = 2048,
+ .max_mixer_blendstages = 0x4,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6375_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6375_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6375_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+};
+
+static const struct dpu_lm_cfg sm6375_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
+ &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
+};
+
+static const struct dpu_dspp_cfg sm6375_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg sm6375_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+};
+
+static const struct dpu_intf_cfg sm6375_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_vbif_cfg sm6375_vbif[] = {
+ {
+ .name = "vbif_0", .id = VBIF_RT,
+ .base = 0, .len = 0x2008,
+ .features = BIT(DPU_VBIF_QOS_REMAP),
+ .xin_halt_timeout = 0x4000,
+ .qos_rp_remap_size = 0x40,
+ .qos_rt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
+ .priority_lvl = sdm845_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 14,
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+ },
+};
+
+static const struct dpu_perf_cfg sm6375_perf_data = {
+ .max_bw_low = 5200000,
+ .max_bw_high = 6200000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0, /* No LLCC on this SoC */
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 24,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6375_cfg = {
+ .caps = &sm6375_dpu_caps,
+ .ubwc = &sm6375_ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6375_mdp),
+ .mdp = sm6375_mdp,
+ .ctl_count = ARRAY_SIZE(sm6375_ctl),
+ .ctl = sm6375_ctl,
+ .sspp_count = ARRAY_SIZE(sm6375_sspp),
+ .sspp = sm6375_sspp,
+ .mixer_count = ARRAY_SIZE(sm6375_lm),
+ .mixer = sm6375_lm,
+ .dspp_count = ARRAY_SIZE(sm6375_dspp),
+ .dspp = sm6375_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6375_pp),
+ .pingpong = sm6375_pp,
+ .intf_count = ARRAY_SIZE(sm6375_intf),
+ .intf = sm6375_intf,
+ .vbif_count = ARRAY_SIZE(sm6375_vbif),
+ .vbif = sm6375_vbif,
+ .perf = &sm6375_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR)
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 52750b592b36..29516273dd6b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
},
};
+static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
+ .maxwidth = 2048,
+ .maxblendstages = 4, /* excluding base layer */
+ .blendstage_base = { /* offsets relative to mixer base */
+ 0x20, 0x38, 0x50, 0x68
+ },
+};
+
/* QCM2290 */
static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
@@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222335777},
};
+static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
+ {.fl = 0, .lut = 0x0011223344556677 },
+ {.fl = 0, .lut = 0x0011223445566777 },
+};
+
static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222223357 },
};
@@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_6_3_sm6115.h"
#include "catalog/dpu_6_4_sm6350.h"
#include "catalog/dpu_6_5_qcm2290.h"
+#include "catalog/dpu_6_9_sm6375.h"
#include "catalog/dpu_7_0_sm8350.h"
#include "catalog/dpu_7_2_sc7280.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f9611bd75e02..b4f193037869 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 46be7ad8d615..980c3c8f8269 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
+ { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add support for MDSS on SM6375.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 4e3a5f0c303c..f2470ce699f7 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
.highest_bank_bit = 1,
};
+static const struct msm_mdss_data sm6375_data = {
+ .ubwc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 6,
+ .ubwc_static = 0x1e,
+ /* Possibly 0 for LPDDR3 */
+ .highest_bank_bit = 1,
+};
+
static const struct msm_mdss_data sm8150_data = {
.ubwc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
@@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
+ { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
{ .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Add support for MDSS on SM6375.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 4e3a5f0c303c..f2470ce699f7 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
.highest_bank_bit = 1,
};
+static const struct msm_mdss_data sm6375_data = {
+ .ubwc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 6,
+ .ubwc_static = 0x1e,
+ /* Possibly 0 for LPDDR3 */
+ .highest_bank_bit = 1,
+};
+
static const struct msm_mdss_data sm8150_data = {
.ubwc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
@@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
+ { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
{ .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add support for MDSS on SM6375.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 4e3a5f0c303c..f2470ce699f7 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
.highest_bank_bit = 1,
};
+static const struct msm_mdss_data sm6375_data = {
+ .ubwc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 6,
+ .ubwc_static = 0x1e,
+ /* Possibly 0 for LPDDR3 */
+ .highest_bank_bit = 1,
+};
+
static const struct msm_mdss_data sm8150_data = {
.ubwc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
@@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
+ { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
{ .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 11/13] iommu/arm-smmu-qcom: Add SM6375 DPU compatible
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index ae09c627bc84..995ab5172883 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6375-mdss" },
{ }
};
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 11/13] iommu/arm-smmu-qcom: Add SM6375 DPU compatible
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index ae09c627bc84..995ab5172883 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6375-mdss" },
{ }
};
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 11/13] iommu/arm-smmu-qcom: Add SM6375 DPU compatible
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index ae09c627bc84..995ab5172883 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6375-mdss" },
{ }
};
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 12/13] iommu/arm-smmu-qcom: Add SM6350 DPU compatible
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 995ab5172883..2daaa600ac75 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm6375-mdss" },
{ }
};
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 12/13] iommu/arm-smmu-qcom: Add SM6350 DPU compatible
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, Konrad Dybcio, linux-kernel,
dri-devel, Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 995ab5172883..2daaa600ac75 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm6375-mdss" },
{ }
};
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 12/13] iommu/arm-smmu-qcom: Add SM6350 DPU compatible
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 995ab5172883..2daaa600ac75 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm6375-mdss" },
{ }
};
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 13/13] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:31 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 2daaa600ac75..e64c737724c4 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -251,12 +251,12 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc7280-mss-pil" },
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sc8280xp-mdss" },
- { .compatible = "qcom,sm8150-mdss" },
- { .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
{ .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm6375-mdss" },
+ { .compatible = "qcom,sm8150-mdss" },
+ { .compatible = "qcom,sm8250-mdss" },
{ }
};
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 13/13] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel,
Konrad Dybcio, iommu, Marijn Suijten, freedreno,
linux-arm-kernel
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 2daaa600ac75..e64c737724c4 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -251,12 +251,12 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc7280-mss-pil" },
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sc8280xp-mdss" },
- { .compatible = "qcom,sm8150-mdss" },
- { .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
{ .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm6375-mdss" },
+ { .compatible = "qcom,sm8150-mdss" },
+ { .compatible = "qcom,sm8250-mdss" },
{ }
};
--
2.40.0
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [PATCH v2 13/13] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
@ 2023-04-20 22:31 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 22:31 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 2daaa600ac75..e64c737724c4 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -251,12 +251,12 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc7280-mss-pil" },
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sc8280xp-mdss" },
- { .compatible = "qcom,sm8150-mdss" },
- { .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
{ .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm6375-mdss" },
+ { .compatible = "qcom,sm8150-mdss" },
+ { .compatible = "qcom,sm8250-mdss" },
{ }
};
--
2.40.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:41 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:41 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add SM6350 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 196 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> new file mode 100644
> index 000000000000..687a508cbaa6
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -0,0 +1,191 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_4_SM6350_H
> +#define _DPU_6_4_SM6350_H
> +
> +static const struct dpu_caps sm6350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0x7,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
DPU_CLK_CTRL_DMA0
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
DPU_CLK_CTRL_DMA2
> +};
> +
> +static const struct dpu_lm_cfg sm6350_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> +};
> +
> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static struct dpu_pingpong_cfg sm6350_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + -1),
> +};
> +
> +static const struct dpu_intf_cfg sm6350_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x1044,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
Do we need two equal entries here?
Also please push the qos to the dpu_hw_catalog.c, I want to take another
look at these structures and it is easier if all of them are beneath
one's eyes.
> +};
> +
> +static const struct dpu_perf_cfg sm6350_perf_data = {
> + .max_bw_low = 4200000,
> + .max_bw_high = 5100000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 35,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> + .caps = &sm6350_dpu_caps,
> + .ubwc = &sm6350_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
> + .mdp = sm6350_mdp,
> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
> + .ctl = sm6350_ctl,
> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
> + .sspp = sm6350_sspp,
> + .mixer_count = ARRAY_SIZE(sm6350_lm),
> + .mixer = sm6350_lm,
> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
> + .dspp = sm6350_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
> + .pingpong = sm6350_pp,
> + .intf_count = ARRAY_SIZE(sm6350_intf),
> + .intf = sm6350_intf,
> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
> + .vbif = sm6350_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8250_regdma,
> + .perf = &sm6350_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR)
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index db558a9ae36e..52750b592b36 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_0_sm8250.h"
> #include "catalog/dpu_6_2_sc7180.h"
> #include "catalog/dpu_6_3_sm6115.h"
> +#include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 756bff1d2185..f9611bd75e02 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
> DPU_QOS_LUT_USAGE_LINEAR,
> DPU_QOS_LUT_USAGE_MACROTILE,
> DPU_QOS_LUT_USAGE_NRT,
> + DPU_QOS_LUT_USAGE_CWB,
> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
This should probably be removed. It would be nice to clean these things
up, but not as a part of sm6350.
> DPU_QOS_LUT_USAGE_MAX,
> };
>
> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 0e7a68714e9e..46be7ad8d615 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-20 22:41 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:41 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, Konrad Dybcio, linux-kernel,
dri-devel, iommu, Marijn Suijten, freedreno, linux-arm-kernel
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add SM6350 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 196 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> new file mode 100644
> index 000000000000..687a508cbaa6
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -0,0 +1,191 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_4_SM6350_H
> +#define _DPU_6_4_SM6350_H
> +
> +static const struct dpu_caps sm6350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0x7,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
DPU_CLK_CTRL_DMA0
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
DPU_CLK_CTRL_DMA2
> +};
> +
> +static const struct dpu_lm_cfg sm6350_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> +};
> +
> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static struct dpu_pingpong_cfg sm6350_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + -1),
> +};
> +
> +static const struct dpu_intf_cfg sm6350_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x1044,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
Do we need two equal entries here?
Also please push the qos to the dpu_hw_catalog.c, I want to take another
look at these structures and it is easier if all of them are beneath
one's eyes.
> +};
> +
> +static const struct dpu_perf_cfg sm6350_perf_data = {
> + .max_bw_low = 4200000,
> + .max_bw_high = 5100000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 35,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> + .caps = &sm6350_dpu_caps,
> + .ubwc = &sm6350_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
> + .mdp = sm6350_mdp,
> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
> + .ctl = sm6350_ctl,
> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
> + .sspp = sm6350_sspp,
> + .mixer_count = ARRAY_SIZE(sm6350_lm),
> + .mixer = sm6350_lm,
> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
> + .dspp = sm6350_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
> + .pingpong = sm6350_pp,
> + .intf_count = ARRAY_SIZE(sm6350_intf),
> + .intf = sm6350_intf,
> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
> + .vbif = sm6350_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8250_regdma,
> + .perf = &sm6350_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR)
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index db558a9ae36e..52750b592b36 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_0_sm8250.h"
> #include "catalog/dpu_6_2_sc7180.h"
> #include "catalog/dpu_6_3_sm6115.h"
> +#include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 756bff1d2185..f9611bd75e02 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
> DPU_QOS_LUT_USAGE_LINEAR,
> DPU_QOS_LUT_USAGE_MACROTILE,
> DPU_QOS_LUT_USAGE_NRT,
> + DPU_QOS_LUT_USAGE_CWB,
> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
This should probably be removed. It would be nice to clean these things
up, but not as a part of sm6350.
> DPU_QOS_LUT_USAGE_MAX,
> };
>
> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 0e7a68714e9e..46be7ad8d615 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-20 22:41 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:41 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add SM6350 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 196 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> new file mode 100644
> index 000000000000..687a508cbaa6
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -0,0 +1,191 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_4_SM6350_H
> +#define _DPU_6_4_SM6350_H
> +
> +static const struct dpu_caps sm6350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0x7,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
DPU_CLK_CTRL_DMA0
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
DPU_CLK_CTRL_DMA2
> +};
> +
> +static const struct dpu_lm_cfg sm6350_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> +};
> +
> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static struct dpu_pingpong_cfg sm6350_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + -1),
> +};
> +
> +static const struct dpu_intf_cfg sm6350_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x1044,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
Do we need two equal entries here?
Also please push the qos to the dpu_hw_catalog.c, I want to take another
look at these structures and it is easier if all of them are beneath
one's eyes.
> +};
> +
> +static const struct dpu_perf_cfg sm6350_perf_data = {
> + .max_bw_low = 4200000,
> + .max_bw_high = 5100000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 35,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> + .caps = &sm6350_dpu_caps,
> + .ubwc = &sm6350_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
> + .mdp = sm6350_mdp,
> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
> + .ctl = sm6350_ctl,
> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
> + .sspp = sm6350_sspp,
> + .mixer_count = ARRAY_SIZE(sm6350_lm),
> + .mixer = sm6350_lm,
> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
> + .dspp = sm6350_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
> + .pingpong = sm6350_pp,
> + .intf_count = ARRAY_SIZE(sm6350_intf),
> + .intf = sm6350_intf,
> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
> + .vbif = sm6350_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8250_regdma,
> + .perf = &sm6350_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR)
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index db558a9ae36e..52750b592b36 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_0_sm8250.h"
> #include "catalog/dpu_6_2_sc7180.h"
> #include "catalog/dpu_6_3_sm6115.h"
> +#include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 756bff1d2185..f9611bd75e02 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
> DPU_QOS_LUT_USAGE_LINEAR,
> DPU_QOS_LUT_USAGE_MACROTILE,
> DPU_QOS_LUT_USAGE_NRT,
> + DPU_QOS_LUT_USAGE_CWB,
> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
This should probably be removed. It would be nice to clean these things
up, but not as a part of sm6350.
> DPU_QOS_LUT_USAGE_MAX,
> };
>
> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 0e7a68714e9e..46be7ad8d615 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:43 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:43 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add support for MDSS on SM6350.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support
@ 2023-04-20 22:43 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:43 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel, iommu,
Marijn Suijten, freedreno, linux-arm-kernel
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add support for MDSS on SM6350.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support
@ 2023-04-20 22:43 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:43 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add support for MDSS on SM6350.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:48 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:48 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add basic SM6375 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 5 files changed, 168 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 687a508cbaa6..d46b43964be6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
> },
> };
>
> -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> - {.fl = 0, .lut = 0x0011223344556677 },
> - {.fl = 0, .lut = 0x0011223445566777 },
> -};
> -
Probably this should be squashed into the patch 7.
> static const struct dpu_perf_cfg sm6350_perf_data = {
> .max_bw_low = 4200000,
> .max_bw_high = 5100000,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> new file mode 100644
> index 000000000000..19ca0051e072
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -0,0 +1,152 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_9_SM6375_H
> +#define _DPU_6_9_SM6375_H
> +
> +static const struct dpu_caps sm6375_dpu_caps = {
> + .max_mixer_width = 2048,
DEFAULT_DPU_LINE_WIDTH,
> + .max_mixer_blendstages = 0x4,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = 2160,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6375_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6375_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> +};
> +
> +static const struct dpu_lm_cfg sm6375_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
> +};
> +
> +static const struct dpu_dspp_cfg sm6375_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static const struct dpu_pingpong_cfg sm6375_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> +};
> +
> +static const struct dpu_intf_cfg sm6375_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x2008,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rp_remap_size = 0x40,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_perf_cfg sm6375_perf_data = {
> + .max_bw_low = 5200000,
> + .max_bw_high = 6200000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0, /* No LLCC on this SoC */
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 24,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6375_cfg = {
> + .caps = &sm6375_dpu_caps,
> + .ubwc = &sm6375_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
> + .mdp = sm6375_mdp,
> + .ctl_count = ARRAY_SIZE(sm6375_ctl),
> + .ctl = sm6375_ctl,
> + .sspp_count = ARRAY_SIZE(sm6375_sspp),
> + .sspp = sm6375_sspp,
> + .mixer_count = ARRAY_SIZE(sm6375_lm),
> + .mixer = sm6375_lm,
> + .dspp_count = ARRAY_SIZE(sm6375_dspp),
> + .dspp = sm6375_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6375_pp),
> + .pingpong = sm6375_pp,
> + .intf_count = ARRAY_SIZE(sm6375_intf),
> + .intf = sm6375_intf,
> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
> + .vbif = sm6375_vbif,
> + .perf = &sm6375_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR)
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 52750b592b36..29516273dd6b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
> },
> };
>
> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
Same as qcm2290
> + .maxwidth = 2048,
DEFAULT_DPU_LINE_WIDTH,
> + .maxblendstages = 4, /* excluding base layer */
> + .blendstage_base = { /* offsets relative to mixer base */
> + 0x20, 0x38, 0x50, 0x68
> + },
> +};
> +
> /* QCM2290 */
>
> static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
> @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222335777},
> };
>
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222223357 },
> };
> @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_3_sm6115.h"
> #include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
> +#include "catalog/dpu_6_9_sm6375.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> #include "catalog/dpu_7_2_sc7280.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index f9611bd75e02..b4f193037869 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 46be7ad8d615..980c3c8f8269 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> + { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
@ 2023-04-20 22:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:48 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel, iommu,
Marijn Suijten, freedreno, linux-arm-kernel
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add basic SM6375 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 5 files changed, 168 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 687a508cbaa6..d46b43964be6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
> },
> };
>
> -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> - {.fl = 0, .lut = 0x0011223344556677 },
> - {.fl = 0, .lut = 0x0011223445566777 },
> -};
> -
Probably this should be squashed into the patch 7.
> static const struct dpu_perf_cfg sm6350_perf_data = {
> .max_bw_low = 4200000,
> .max_bw_high = 5100000,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> new file mode 100644
> index 000000000000..19ca0051e072
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -0,0 +1,152 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_9_SM6375_H
> +#define _DPU_6_9_SM6375_H
> +
> +static const struct dpu_caps sm6375_dpu_caps = {
> + .max_mixer_width = 2048,
DEFAULT_DPU_LINE_WIDTH,
> + .max_mixer_blendstages = 0x4,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = 2160,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6375_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6375_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> +};
> +
> +static const struct dpu_lm_cfg sm6375_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
> +};
> +
> +static const struct dpu_dspp_cfg sm6375_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static const struct dpu_pingpong_cfg sm6375_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> +};
> +
> +static const struct dpu_intf_cfg sm6375_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x2008,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rp_remap_size = 0x40,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_perf_cfg sm6375_perf_data = {
> + .max_bw_low = 5200000,
> + .max_bw_high = 6200000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0, /* No LLCC on this SoC */
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 24,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6375_cfg = {
> + .caps = &sm6375_dpu_caps,
> + .ubwc = &sm6375_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
> + .mdp = sm6375_mdp,
> + .ctl_count = ARRAY_SIZE(sm6375_ctl),
> + .ctl = sm6375_ctl,
> + .sspp_count = ARRAY_SIZE(sm6375_sspp),
> + .sspp = sm6375_sspp,
> + .mixer_count = ARRAY_SIZE(sm6375_lm),
> + .mixer = sm6375_lm,
> + .dspp_count = ARRAY_SIZE(sm6375_dspp),
> + .dspp = sm6375_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6375_pp),
> + .pingpong = sm6375_pp,
> + .intf_count = ARRAY_SIZE(sm6375_intf),
> + .intf = sm6375_intf,
> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
> + .vbif = sm6375_vbif,
> + .perf = &sm6375_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR)
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 52750b592b36..29516273dd6b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
> },
> };
>
> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
Same as qcm2290
> + .maxwidth = 2048,
DEFAULT_DPU_LINE_WIDTH,
> + .maxblendstages = 4, /* excluding base layer */
> + .blendstage_base = { /* offsets relative to mixer base */
> + 0x20, 0x38, 0x50, 0x68
> + },
> +};
> +
> /* QCM2290 */
>
> static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
> @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222335777},
> };
>
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222223357 },
> };
> @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_3_sm6115.h"
> #include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
> +#include "catalog/dpu_6_9_sm6375.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> #include "catalog/dpu_7_2_sc7280.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index f9611bd75e02..b4f193037869 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 46be7ad8d615..980c3c8f8269 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> + { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
@ 2023-04-20 22:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:48 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add basic SM6375 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 5 files changed, 168 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 687a508cbaa6..d46b43964be6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
> },
> };
>
> -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> - {.fl = 0, .lut = 0x0011223344556677 },
> - {.fl = 0, .lut = 0x0011223445566777 },
> -};
> -
Probably this should be squashed into the patch 7.
> static const struct dpu_perf_cfg sm6350_perf_data = {
> .max_bw_low = 4200000,
> .max_bw_high = 5100000,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> new file mode 100644
> index 000000000000..19ca0051e072
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -0,0 +1,152 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_9_SM6375_H
> +#define _DPU_6_9_SM6375_H
> +
> +static const struct dpu_caps sm6375_dpu_caps = {
> + .max_mixer_width = 2048,
DEFAULT_DPU_LINE_WIDTH,
> + .max_mixer_blendstages = 0x4,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = 2160,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6375_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6375_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> +};
> +
> +static const struct dpu_lm_cfg sm6375_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
> +};
> +
> +static const struct dpu_dspp_cfg sm6375_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static const struct dpu_pingpong_cfg sm6375_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> +};
> +
> +static const struct dpu_intf_cfg sm6375_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x2008,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rp_remap_size = 0x40,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_perf_cfg sm6375_perf_data = {
> + .max_bw_low = 5200000,
> + .max_bw_high = 6200000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0, /* No LLCC on this SoC */
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 24,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6375_cfg = {
> + .caps = &sm6375_dpu_caps,
> + .ubwc = &sm6375_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
> + .mdp = sm6375_mdp,
> + .ctl_count = ARRAY_SIZE(sm6375_ctl),
> + .ctl = sm6375_ctl,
> + .sspp_count = ARRAY_SIZE(sm6375_sspp),
> + .sspp = sm6375_sspp,
> + .mixer_count = ARRAY_SIZE(sm6375_lm),
> + .mixer = sm6375_lm,
> + .dspp_count = ARRAY_SIZE(sm6375_dspp),
> + .dspp = sm6375_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6375_pp),
> + .pingpong = sm6375_pp,
> + .intf_count = ARRAY_SIZE(sm6375_intf),
> + .intf = sm6375_intf,
> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
> + .vbif = sm6375_vbif,
> + .perf = &sm6375_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR)
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 52750b592b36..29516273dd6b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
> },
> };
>
> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
Same as qcm2290
> + .maxwidth = 2048,
DEFAULT_DPU_LINE_WIDTH,
> + .maxblendstages = 4, /* excluding base layer */
> + .blendstage_base = { /* offsets relative to mixer base */
> + 0x20, 0x38, 0x50, 0x68
> + },
> +};
> +
> /* QCM2290 */
>
> static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
> @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222335777},
> };
>
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222223357 },
> };
> @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_3_sm6115.h"
> #include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
> +#include "catalog/dpu_6_9_sm6375.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> #include "catalog/dpu_7_2_sc7280.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index f9611bd75e02..b4f193037869 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 46be7ad8d615..980c3c8f8269 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> + { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:49 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:49 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add support for MDSS on SM6375.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
@ 2023-04-20 22:49 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:49 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel, iommu,
Marijn Suijten, freedreno, linux-arm-kernel
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add support for MDSS on SM6375.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
@ 2023-04-20 22:49 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:49 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add support for MDSS on SM6375.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:50 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:50 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add support for MDSS on SM6375.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 4e3a5f0c303c..f2470ce699f7 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
> .highest_bank_bit = 1,
> };
>
> +static const struct msm_mdss_data sm6375_data = {
> + .ubwc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_static = 0x1e,
> + /* Possibly 0 for LPDDR3 */
> + .highest_bank_bit = 1,
> +};
Nit: we can use sm6350 data here, can't we?
> +
> static const struct msm_mdss_data sm8150_data = {
> .ubwc_version = UBWC_3_0,
> .ubwc_dec_version = UBWC_3_0,
> @@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
> { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
> + { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
@ 2023-04-20 22:50 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:50 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel, iommu,
Marijn Suijten, freedreno, linux-arm-kernel
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add support for MDSS on SM6375.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 4e3a5f0c303c..f2470ce699f7 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
> .highest_bank_bit = 1,
> };
>
> +static const struct msm_mdss_data sm6375_data = {
> + .ubwc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_static = 0x1e,
> + /* Possibly 0 for LPDDR3 */
> + .highest_bank_bit = 1,
> +};
Nit: we can use sm6350 data here, can't we?
> +
> static const struct msm_mdss_data sm8150_data = {
> .ubwc_version = UBWC_3_0,
> .ubwc_dec_version = UBWC_3_0,
> @@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
> { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
> + { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
@ 2023-04-20 22:50 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:50 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add support for MDSS on SM6375.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 4e3a5f0c303c..f2470ce699f7 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
> .highest_bank_bit = 1,
> };
>
> +static const struct msm_mdss_data sm6375_data = {
> + .ubwc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_static = 0x1e,
> + /* Possibly 0 for LPDDR3 */
> + .highest_bank_bit = 1,
> +};
Nit: we can use sm6350 data here, can't we?
> +
> static const struct msm_mdss_data sm8150_data = {
> .ubwc_version = UBWC_3_0,
> .ubwc_dec_version = UBWC_3_0,
> @@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
> { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
> + { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 12/13] iommu/arm-smmu-qcom: Add SM6350 DPU compatible
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:51 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:51 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On 21/04/2023 01:31, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> Add the SM6350 DPU compatible to clients compatible list, as it also
> needs the workarounds.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 12/13] iommu/arm-smmu-qcom: Add SM6350 DPU compatible
@ 2023-04-20 22:51 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:51 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, Konrad Dybcio, linux-kernel,
dri-devel, iommu, Marijn Suijten, freedreno, linux-arm-kernel
On 21/04/2023 01:31, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> Add the SM6350 DPU compatible to clients compatible list, as it also
> needs the workarounds.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 12/13] iommu/arm-smmu-qcom: Add SM6350 DPU compatible
@ 2023-04-20 22:51 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:51 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On 21/04/2023 01:31, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> Add the SM6350 DPU compatible to clients compatible list, as it also
> needs the workarounds.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 11/13] iommu/arm-smmu-qcom: Add SM6375 DPU compatible
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:52 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:52 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add the SM6375 DPU compatible to clients compatible list, as it also
> needs the workarounds.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 11/13] iommu/arm-smmu-qcom: Add SM6375 DPU compatible
@ 2023-04-20 22:52 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:52 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel, iommu,
Marijn Suijten, freedreno, linux-arm-kernel
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add the SM6375 DPU compatible to clients compatible list, as it also
> needs the workarounds.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 11/13] iommu/arm-smmu-qcom: Add SM6375 DPU compatible
@ 2023-04-20 22:52 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:52 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> Add the SM6375 DPU compatible to clients compatible list, as it also
> needs the workarounds.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 13/13] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-20 22:53 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:53 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel, iommu,
Marijn Suijten, freedreno, linux-arm-kernel
On 21/04/2023 01:31, Konrad Dybcio wrote:
> It got broken at some point, fix it up.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
This should probably come before patches 11 and 12.
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 2daaa600ac75..e64c737724c4 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -251,12 +251,12 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
> { .compatible = "qcom,sc7280-mss-pil" },
> { .compatible = "qcom,sc8180x-mdss" },
> { .compatible = "qcom,sc8280xp-mdss" },
> - { .compatible = "qcom,sm8150-mdss" },
> - { .compatible = "qcom,sm8250-mdss" },
> { .compatible = "qcom,sdm845-mdss" },
> { .compatible = "qcom,sdm845-mss-pil" },
> { .compatible = "qcom,sm6350-mdss" },
> { .compatible = "qcom,sm6375-mdss" },
> + { .compatible = "qcom,sm8150-mdss" },
> + { .compatible = "qcom,sm8250-mdss" },
> { }
> };
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 13/13] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
@ 2023-04-20 22:53 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:53 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> It got broken at some point, fix it up.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
This should probably come before patches 11 and 12.
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 2daaa600ac75..e64c737724c4 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -251,12 +251,12 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
> { .compatible = "qcom,sc7280-mss-pil" },
> { .compatible = "qcom,sc8180x-mdss" },
> { .compatible = "qcom,sc8280xp-mdss" },
> - { .compatible = "qcom,sm8150-mdss" },
> - { .compatible = "qcom,sm8250-mdss" },
> { .compatible = "qcom,sdm845-mdss" },
> { .compatible = "qcom,sdm845-mss-pil" },
> { .compatible = "qcom,sm6350-mdss" },
> { .compatible = "qcom,sm6375-mdss" },
> + { .compatible = "qcom,sm8150-mdss" },
> + { .compatible = "qcom,sm8250-mdss" },
> { }
> };
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 13/13] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
@ 2023-04-20 22:53 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 22:53 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21/04/2023 01:31, Konrad Dybcio wrote:
> It got broken at some point, fix it up.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
This should probably come before patches 11 and 12.
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 2daaa600ac75..e64c737724c4 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -251,12 +251,12 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
> { .compatible = "qcom,sc7280-mss-pil" },
> { .compatible = "qcom,sc8180x-mdss" },
> { .compatible = "qcom,sc8280xp-mdss" },
> - { .compatible = "qcom,sm8150-mdss" },
> - { .compatible = "qcom,sm8250-mdss" },
> { .compatible = "qcom,sdm845-mdss" },
> { .compatible = "qcom,sdm845-mss-pil" },
> { .compatible = "qcom,sm6350-mdss" },
> { .compatible = "qcom,sm6375-mdss" },
> + { .compatible = "qcom,sm8150-mdss" },
> + { .compatible = "qcom,sm8250-mdss" },
> { }
> };
>
>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-20 22:41 ` Dmitry Baryshkov
(?)
@ 2023-04-20 23:05 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 23:05 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On 21.04.2023 00:41, Dmitry Baryshkov wrote:
> On 21/04/2023 01:31, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
[...]
>> +
>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>
> DPU_CLK_CTRL_DMA0
>
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>
> DPU_CLK_CTRL_DMA2
_DMA1?
>
>
>> +};
>> +
>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>
> Do we need two equal entries here?
Hmm.. looks like the SDE driver dropped the fill level
logic in 4.19 times and that might have thrown me off
when porting this Since the [0] entry has what looks
like a lower LUT value, should I give it .fl=1?
>
> Also please push the qos to the dpu_hw_catalog.c, I want to take another look at these structures and it is easier if all of them are beneath one's eyes.
Will do.
>
>> +};
>> +
>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>> + .max_bw_low = 4200000,
>> + .max_bw_high = 5100000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0,
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 35,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
[...]
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>> DPU_QOS_LUT_USAGE_LINEAR,
>> DPU_QOS_LUT_USAGE_MACROTILE,
>> DPU_QOS_LUT_USAGE_NRT,
>> + DPU_QOS_LUT_USAGE_CWB,
>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>
> This should probably be removed. It would be nice to clean these things up, but not as a part of sm6350.
Well, I won't be able to fill in the danger LUT table otherwise!
Konrad
>
>> DPU_QOS_LUT_USAGE_MAX,
>> };
>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 0e7a68714e9e..46be7ad8d615 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-20 23:05 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 23:05 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, Konrad Dybcio, linux-kernel,
dri-devel, iommu, Marijn Suijten, freedreno, linux-arm-kernel
On 21.04.2023 00:41, Dmitry Baryshkov wrote:
> On 21/04/2023 01:31, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
[...]
>> +
>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>
> DPU_CLK_CTRL_DMA0
>
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>
> DPU_CLK_CTRL_DMA2
_DMA1?
>
>
>> +};
>> +
>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>
> Do we need two equal entries here?
Hmm.. looks like the SDE driver dropped the fill level
logic in 4.19 times and that might have thrown me off
when porting this Since the [0] entry has what looks
like a lower LUT value, should I give it .fl=1?
>
> Also please push the qos to the dpu_hw_catalog.c, I want to take another look at these structures and it is easier if all of them are beneath one's eyes.
Will do.
>
>> +};
>> +
>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>> + .max_bw_low = 4200000,
>> + .max_bw_high = 5100000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0,
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 35,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
[...]
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>> DPU_QOS_LUT_USAGE_LINEAR,
>> DPU_QOS_LUT_USAGE_MACROTILE,
>> DPU_QOS_LUT_USAGE_NRT,
>> + DPU_QOS_LUT_USAGE_CWB,
>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>
> This should probably be removed. It would be nice to clean these things up, but not as a part of sm6350.
Well, I won't be able to fill in the danger LUT table otherwise!
Konrad
>
>> DPU_QOS_LUT_USAGE_MAX,
>> };
>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 0e7a68714e9e..46be7ad8d615 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-20 23:05 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 23:05 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On 21.04.2023 00:41, Dmitry Baryshkov wrote:
> On 21/04/2023 01:31, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
[...]
>> +
>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>
> DPU_CLK_CTRL_DMA0
>
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>
> DPU_CLK_CTRL_DMA2
_DMA1?
>
>
>> +};
>> +
>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>
> Do we need two equal entries here?
Hmm.. looks like the SDE driver dropped the fill level
logic in 4.19 times and that might have thrown me off
when porting this Since the [0] entry has what looks
like a lower LUT value, should I give it .fl=1?
>
> Also please push the qos to the dpu_hw_catalog.c, I want to take another look at these structures and it is easier if all of them are beneath one's eyes.
Will do.
>
>> +};
>> +
>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>> + .max_bw_low = 4200000,
>> + .max_bw_high = 5100000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0,
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 35,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
[...]
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>> DPU_QOS_LUT_USAGE_LINEAR,
>> DPU_QOS_LUT_USAGE_MACROTILE,
>> DPU_QOS_LUT_USAGE_NRT,
>> + DPU_QOS_LUT_USAGE_CWB,
>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>
> This should probably be removed. It would be nice to clean these things up, but not as a part of sm6350.
Well, I won't be able to fill in the danger LUT table otherwise!
Konrad
>
>> DPU_QOS_LUT_USAGE_MAX,
>> };
>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 0e7a68714e9e..46be7ad8d615 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-20 23:05 ` Konrad Dybcio
(?)
@ 2023-04-20 23:06 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 23:06 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On 21/04/2023 02:05, Konrad Dybcio wrote:
>
>
> On 21.04.2023 00:41, Dmitry Baryshkov wrote:
>> On 21/04/2023 01:31, Konrad Dybcio wrote:
>>> Add SM6350 support to the DPU1 driver to enable display output.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
> [...]
>
>>> +
>>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>>
>> DPU_CLK_CTRL_DMA0
This is DPU_CLK_CTRL_DMA1, I made a typo
>>
>>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>>
>> DPU_CLK_CTRL_DMA2
> _DMA1?
>
And this is DMA2, I was correct.
>
>>
>>
>>> +};
>>> +
>
>>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>>> + {.fl = 0, .lut = 0x0011223344556677 },
>>> + {.fl = 0, .lut = 0x0011223445566777 },
>>
>> Do we need two equal entries here?
> Hmm.. looks like the SDE driver dropped the fill level
> logic in 4.19 times and that might have thrown me off
> when porting this Since the [0] entry has what looks
> like a lower LUT value, should I give it .fl=1?
>
>
>>
>> Also please push the qos to the dpu_hw_catalog.c, I want to take another look at these structures and it is easier if all of them are beneath one's eyes.
> Will do.
>
>>
>>> +};
>>> +
>>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>>> + .max_bw_low = 4200000,
>>> + .max_bw_high = 5100000,
>>> + .min_core_ib = 2500000,
>>> + .min_llcc_ib = 0,
>>> + .min_dram_ib = 1600000,
>>> + .min_prefill_lines = 35,
>>> + /* TODO: confirm danger_lut_tbl */
>>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> [...]
>
>
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>>> DPU_QOS_LUT_USAGE_LINEAR,
>>> DPU_QOS_LUT_USAGE_MACROTILE,
>>> DPU_QOS_LUT_USAGE_NRT,
>>> + DPU_QOS_LUT_USAGE_CWB,
>>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>>
>> This should probably be removed. It would be nice to clean these things up, but not as a part of sm6350.
> Well, I won't be able to fill in the danger LUT table otherwise!
>
> Konrad
>>
>>> DPU_QOS_LUT_USAGE_MAX,
>>> };
>>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> index 0e7a68714e9e..46be7ad8d615 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>>
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-20 23:06 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 23:06 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, Konrad Dybcio, linux-kernel,
dri-devel, iommu, Marijn Suijten, freedreno, linux-arm-kernel
On 21/04/2023 02:05, Konrad Dybcio wrote:
>
>
> On 21.04.2023 00:41, Dmitry Baryshkov wrote:
>> On 21/04/2023 01:31, Konrad Dybcio wrote:
>>> Add SM6350 support to the DPU1 driver to enable display output.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
> [...]
>
>>> +
>>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>>
>> DPU_CLK_CTRL_DMA0
This is DPU_CLK_CTRL_DMA1, I made a typo
>>
>>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>>
>> DPU_CLK_CTRL_DMA2
> _DMA1?
>
And this is DMA2, I was correct.
>
>>
>>
>>> +};
>>> +
>
>>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>>> + {.fl = 0, .lut = 0x0011223344556677 },
>>> + {.fl = 0, .lut = 0x0011223445566777 },
>>
>> Do we need two equal entries here?
> Hmm.. looks like the SDE driver dropped the fill level
> logic in 4.19 times and that might have thrown me off
> when porting this Since the [0] entry has what looks
> like a lower LUT value, should I give it .fl=1?
>
>
>>
>> Also please push the qos to the dpu_hw_catalog.c, I want to take another look at these structures and it is easier if all of them are beneath one's eyes.
> Will do.
>
>>
>>> +};
>>> +
>>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>>> + .max_bw_low = 4200000,
>>> + .max_bw_high = 5100000,
>>> + .min_core_ib = 2500000,
>>> + .min_llcc_ib = 0,
>>> + .min_dram_ib = 1600000,
>>> + .min_prefill_lines = 35,
>>> + /* TODO: confirm danger_lut_tbl */
>>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> [...]
>
>
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>>> DPU_QOS_LUT_USAGE_LINEAR,
>>> DPU_QOS_LUT_USAGE_MACROTILE,
>>> DPU_QOS_LUT_USAGE_NRT,
>>> + DPU_QOS_LUT_USAGE_CWB,
>>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>>
>> This should probably be removed. It would be nice to clean these things up, but not as a part of sm6350.
> Well, I won't be able to fill in the danger LUT table otherwise!
>
> Konrad
>>
>>> DPU_QOS_LUT_USAGE_MAX,
>>> };
>>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> index 0e7a68714e9e..46be7ad8d615 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>>
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-20 23:06 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-20 23:06 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On 21/04/2023 02:05, Konrad Dybcio wrote:
>
>
> On 21.04.2023 00:41, Dmitry Baryshkov wrote:
>> On 21/04/2023 01:31, Konrad Dybcio wrote:
>>> Add SM6350 support to the DPU1 driver to enable display output.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
> [...]
>
>>> +
>>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>>
>> DPU_CLK_CTRL_DMA0
This is DPU_CLK_CTRL_DMA1, I made a typo
>>
>>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>>
>> DPU_CLK_CTRL_DMA2
> _DMA1?
>
And this is DMA2, I was correct.
>
>>
>>
>>> +};
>>> +
>
>>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>>> + {.fl = 0, .lut = 0x0011223344556677 },
>>> + {.fl = 0, .lut = 0x0011223445566777 },
>>
>> Do we need two equal entries here?
> Hmm.. looks like the SDE driver dropped the fill level
> logic in 4.19 times and that might have thrown me off
> when porting this Since the [0] entry has what looks
> like a lower LUT value, should I give it .fl=1?
>
>
>>
>> Also please push the qos to the dpu_hw_catalog.c, I want to take another look at these structures and it is easier if all of them are beneath one's eyes.
> Will do.
>
>>
>>> +};
>>> +
>>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>>> + .max_bw_low = 4200000,
>>> + .max_bw_high = 5100000,
>>> + .min_core_ib = 2500000,
>>> + .min_llcc_ib = 0,
>>> + .min_dram_ib = 1600000,
>>> + .min_prefill_lines = 35,
>>> + /* TODO: confirm danger_lut_tbl */
>>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> [...]
>
>
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>>> DPU_QOS_LUT_USAGE_LINEAR,
>>> DPU_QOS_LUT_USAGE_MACROTILE,
>>> DPU_QOS_LUT_USAGE_NRT,
>>> + DPU_QOS_LUT_USAGE_CWB,
>>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>>
>> This should probably be removed. It would be nice to clean these things up, but not as a part of sm6350.
> Well, I won't be able to fill in the danger LUT table otherwise!
>
> Konrad
>>
>>> DPU_QOS_LUT_USAGE_MAX,
>>> };
>>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> index 0e7a68714e9e..46be7ad8d615 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>>
>>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
2023-04-20 22:50 ` Dmitry Baryshkov
(?)
@ 2023-04-20 23:06 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 23:06 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21.04.2023 00:50, Dmitry Baryshkov wrote:
> On 21/04/2023 01:31, Konrad Dybcio wrote:
>> Add support for MDSS on SM6375.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
>> index 4e3a5f0c303c..f2470ce699f7 100644
>> --- a/drivers/gpu/drm/msm/msm_mdss.c
>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
>> @@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
>> .highest_bank_bit = 1,
>> };
>> +static const struct msm_mdss_data sm6375_data = {
>> + .ubwc_version = UBWC_2_0,
>> + .ubwc_dec_version = UBWC_2_0,
>> + .ubwc_swizzle = 6,
>> + .ubwc_static = 0x1e,
>> + /* Possibly 0 for LPDDR3 */
>> + .highest_bank_bit = 1,
>> +};
>
> Nit: we can use sm6350 data here, can't we?
Nice catch!
Konrad
>
>> +
>> static const struct msm_mdss_data sm8150_data = {
>> .ubwc_version = UBWC_3_0,
>> .ubwc_dec_version = UBWC_3_0,
>> @@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
>> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
>> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
>> { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
>> + { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
>> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
>> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
>> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>>
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
@ 2023-04-20 23:06 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 23:06 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 21.04.2023 00:50, Dmitry Baryshkov wrote:
> On 21/04/2023 01:31, Konrad Dybcio wrote:
>> Add support for MDSS on SM6375.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
>> index 4e3a5f0c303c..f2470ce699f7 100644
>> --- a/drivers/gpu/drm/msm/msm_mdss.c
>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
>> @@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
>> .highest_bank_bit = 1,
>> };
>> +static const struct msm_mdss_data sm6375_data = {
>> + .ubwc_version = UBWC_2_0,
>> + .ubwc_dec_version = UBWC_2_0,
>> + .ubwc_swizzle = 6,
>> + .ubwc_static = 0x1e,
>> + /* Possibly 0 for LPDDR3 */
>> + .highest_bank_bit = 1,
>> +};
>
> Nit: we can use sm6350 data here, can't we?
Nice catch!
Konrad
>
>> +
>> static const struct msm_mdss_data sm8150_data = {
>> .ubwc_version = UBWC_3_0,
>> .ubwc_dec_version = UBWC_3_0,
>> @@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
>> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
>> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
>> { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
>> + { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
>> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
>> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
>> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
@ 2023-04-20 23:06 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-20 23:06 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, linux-kernel, dri-devel, iommu,
Marijn Suijten, freedreno, linux-arm-kernel
On 21.04.2023 00:50, Dmitry Baryshkov wrote:
> On 21/04/2023 01:31, Konrad Dybcio wrote:
>> Add support for MDSS on SM6375.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
>> index 4e3a5f0c303c..f2470ce699f7 100644
>> --- a/drivers/gpu/drm/msm/msm_mdss.c
>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
>> @@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
>> .highest_bank_bit = 1,
>> };
>> +static const struct msm_mdss_data sm6375_data = {
>> + .ubwc_version = UBWC_2_0,
>> + .ubwc_dec_version = UBWC_2_0,
>> + .ubwc_swizzle = 6,
>> + .ubwc_static = 0x1e,
>> + /* Possibly 0 for LPDDR3 */
>> + .highest_bank_bit = 1,
>> +};
>
> Nit: we can use sm6350 data here, can't we?
Nice catch!
Konrad
>
>> +
>> static const struct msm_mdss_data sm8150_data = {
>> .ubwc_version = UBWC_3_0,
>> .ubwc_dec_version = UBWC_3_0,
>> @@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
>> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
>> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
>> { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
>> + { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
>> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
>> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
>> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>>
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 04/13] dt-bindings: display/msm: Add SM6350 MDSS
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-21 12:56 ` Rob Herring
-1 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-21 12:56 UTC (permalink / raw)
To: Konrad Dybcio
Cc: linux-arm-kernel, dri-devel, Abhinav Kumar, Krzysztof Kozlowski,
linux-arm-msm, Will Deacon, Rob Herring, David Airlie,
Marijn Suijten, devicetree, Dmitry Baryshkov, Daniel Vetter,
Joerg Roedel, Sean Paul, Rob Clark, Robin Murphy, iommu,
Krishna Manikandan, linux-kernel, freedreno
On Fri, 21 Apr 2023 00:31:13 +0200, Konrad Dybcio wrote:
> Document the SM6350 MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++++++
> 1 file changed, 214 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.example.dtb: dsi@ae94000: compatible: 'oneOf' conditional failed, one must be fixed:
'qcom,sm6350-dsi-ctrl' is not one of ['qcom,apq8064-dsi-ctrl', 'qcom,msm8916-dsi-ctrl', 'qcom,msm8953-dsi-ctrl', 'qcom,msm8974-dsi-ctrl', 'qcom,msm8996-dsi-ctrl', 'qcom,msm8998-dsi-ctrl', 'qcom,qcm2290-dsi-ctrl', 'qcom,sc7180-dsi-ctrl', 'qcom,sc7280-dsi-ctrl', 'qcom,sdm660-dsi-ctrl', 'qcom,sdm845-dsi-ctrl', 'qcom,sm8150-dsi-ctrl', 'qcom,sm8250-dsi-ctrl', 'qcom,sm8350-dsi-ctrl', 'qcom,sm8450-dsi-ctrl', 'qcom,sm8550-dsi-ctrl']
'qcom,sm6350-dsi-ctrl' is not one of ['dsi-ctrl-6g-qcm2290']
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.example.dtb: dsi@ae94000: Unevaluated properties are not allowed ('compatible' was unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230411-topic-straitlagoon_mdss-v2-4-5def73f50980@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 06/13] dt-bindings: display/msm: Add SM6375 MDSS
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-21 12:56 ` Rob Herring
-1 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-21 12:56 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Robin Murphy, Rob Clark, Sean Paul, Dmitry Baryshkov,
Will Deacon, linux-arm-kernel, Krzysztof Kozlowski, Rob Herring,
Daniel Vetter, Joerg Roedel, iommu, freedreno,
Krishna Manikandan, devicetree, David Airlie, dri-devel,
Marijn Suijten, linux-arm-msm, linux-kernel, Abhinav Kumar
On Fri, 21 Apr 2023 00:31:15 +0200, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
> 1 file changed, 216 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: dsi@5e94000: compatible: 'oneOf' conditional failed, one must be fixed:
'qcom,sm6375-dsi-ctrl' is not one of ['qcom,apq8064-dsi-ctrl', 'qcom,msm8916-dsi-ctrl', 'qcom,msm8953-dsi-ctrl', 'qcom,msm8974-dsi-ctrl', 'qcom,msm8996-dsi-ctrl', 'qcom,msm8998-dsi-ctrl', 'qcom,qcm2290-dsi-ctrl', 'qcom,sc7180-dsi-ctrl', 'qcom,sc7280-dsi-ctrl', 'qcom,sdm660-dsi-ctrl', 'qcom,sdm845-dsi-ctrl', 'qcom,sm8150-dsi-ctrl', 'qcom,sm8250-dsi-ctrl', 'qcom,sm8350-dsi-ctrl', 'qcom,sm8450-dsi-ctrl', 'qcom,sm8550-dsi-ctrl']
'qcom,sm6375-dsi-ctrl' is not one of ['dsi-ctrl-6g-qcm2290']
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: dsi@5e94000: Unevaluated properties are not allowed ('compatible' was unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230411-topic-straitlagoon_mdss-v2-6-5def73f50980@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 04/13] dt-bindings: display/msm: Add SM6350 MDSS
@ 2023-04-21 12:56 ` Rob Herring
0 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-21 12:56 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Sean Paul, devicetree, iommu, linux-arm-msm, Joerg Roedel,
Abhinav Kumar, dri-devel, linux-kernel, Rob Herring,
Krishna Manikandan, Krzysztof Kozlowski, Dmitry Baryshkov,
Marijn Suijten, freedreno, Will Deacon, linux-arm-kernel,
Robin Murphy
On Fri, 21 Apr 2023 00:31:13 +0200, Konrad Dybcio wrote:
> Document the SM6350 MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++++++
> 1 file changed, 214 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.example.dtb: dsi@ae94000: compatible: 'oneOf' conditional failed, one must be fixed:
'qcom,sm6350-dsi-ctrl' is not one of ['qcom,apq8064-dsi-ctrl', 'qcom,msm8916-dsi-ctrl', 'qcom,msm8953-dsi-ctrl', 'qcom,msm8974-dsi-ctrl', 'qcom,msm8996-dsi-ctrl', 'qcom,msm8998-dsi-ctrl', 'qcom,qcm2290-dsi-ctrl', 'qcom,sc7180-dsi-ctrl', 'qcom,sc7280-dsi-ctrl', 'qcom,sdm660-dsi-ctrl', 'qcom,sdm845-dsi-ctrl', 'qcom,sm8150-dsi-ctrl', 'qcom,sm8250-dsi-ctrl', 'qcom,sm8350-dsi-ctrl', 'qcom,sm8450-dsi-ctrl', 'qcom,sm8550-dsi-ctrl']
'qcom,sm6350-dsi-ctrl' is not one of ['dsi-ctrl-6g-qcm2290']
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.example.dtb: dsi@ae94000: Unevaluated properties are not allowed ('compatible' was unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230411-topic-straitlagoon_mdss-v2-4-5def73f50980@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 06/13] dt-bindings: display/msm: Add SM6375 MDSS
@ 2023-04-21 12:56 ` Rob Herring
0 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-21 12:56 UTC (permalink / raw)
To: Konrad Dybcio
Cc: freedreno, Will Deacon, devicetree, Robin Murphy, Joerg Roedel,
iommu, dri-devel, linux-kernel, Abhinav Kumar, Rob Herring,
Krishna Manikandan, Krzysztof Kozlowski, linux-arm-msm,
Dmitry Baryshkov, Marijn Suijten, Sean Paul, linux-arm-kernel
On Fri, 21 Apr 2023 00:31:15 +0200, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
> 1 file changed, 216 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: dsi@5e94000: compatible: 'oneOf' conditional failed, one must be fixed:
'qcom,sm6375-dsi-ctrl' is not one of ['qcom,apq8064-dsi-ctrl', 'qcom,msm8916-dsi-ctrl', 'qcom,msm8953-dsi-ctrl', 'qcom,msm8974-dsi-ctrl', 'qcom,msm8996-dsi-ctrl', 'qcom,msm8998-dsi-ctrl', 'qcom,qcm2290-dsi-ctrl', 'qcom,sc7180-dsi-ctrl', 'qcom,sc7280-dsi-ctrl', 'qcom,sdm660-dsi-ctrl', 'qcom,sdm845-dsi-ctrl', 'qcom,sm8150-dsi-ctrl', 'qcom,sm8250-dsi-ctrl', 'qcom,sm8350-dsi-ctrl', 'qcom,sm8450-dsi-ctrl', 'qcom,sm8550-dsi-ctrl']
'qcom,sm6375-dsi-ctrl' is not one of ['dsi-ctrl-6g-qcm2290']
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: dsi@5e94000: Unevaluated properties are not allowed ('compatible' was unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230411-topic-straitlagoon_mdss-v2-6-5def73f50980@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 04/13] dt-bindings: display/msm: Add SM6350 MDSS
@ 2023-04-21 12:56 ` Rob Herring
0 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-21 12:56 UTC (permalink / raw)
To: Konrad Dybcio
Cc: linux-arm-kernel, dri-devel, Abhinav Kumar, Krzysztof Kozlowski,
linux-arm-msm, Will Deacon, Rob Herring, David Airlie,
Marijn Suijten, devicetree, Dmitry Baryshkov, Daniel Vetter,
Joerg Roedel, Sean Paul, Rob Clark, Robin Murphy, iommu,
Krishna Manikandan, linux-kernel, freedreno
On Fri, 21 Apr 2023 00:31:13 +0200, Konrad Dybcio wrote:
> Document the SM6350 MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++++++
> 1 file changed, 214 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.example.dtb: dsi@ae94000: compatible: 'oneOf' conditional failed, one must be fixed:
'qcom,sm6350-dsi-ctrl' is not one of ['qcom,apq8064-dsi-ctrl', 'qcom,msm8916-dsi-ctrl', 'qcom,msm8953-dsi-ctrl', 'qcom,msm8974-dsi-ctrl', 'qcom,msm8996-dsi-ctrl', 'qcom,msm8998-dsi-ctrl', 'qcom,qcm2290-dsi-ctrl', 'qcom,sc7180-dsi-ctrl', 'qcom,sc7280-dsi-ctrl', 'qcom,sdm660-dsi-ctrl', 'qcom,sdm845-dsi-ctrl', 'qcom,sm8150-dsi-ctrl', 'qcom,sm8250-dsi-ctrl', 'qcom,sm8350-dsi-ctrl', 'qcom,sm8450-dsi-ctrl', 'qcom,sm8550-dsi-ctrl']
'qcom,sm6350-dsi-ctrl' is not one of ['dsi-ctrl-6g-qcm2290']
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.example.dtb: dsi@ae94000: Unevaluated properties are not allowed ('compatible' was unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230411-topic-straitlagoon_mdss-v2-4-5def73f50980@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 06/13] dt-bindings: display/msm: Add SM6375 MDSS
@ 2023-04-21 12:56 ` Rob Herring
0 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-21 12:56 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Robin Murphy, Rob Clark, Sean Paul, Dmitry Baryshkov,
Will Deacon, linux-arm-kernel, Krzysztof Kozlowski, Rob Herring,
Daniel Vetter, Joerg Roedel, iommu, freedreno,
Krishna Manikandan, devicetree, David Airlie, dri-devel,
Marijn Suijten, linux-arm-msm, linux-kernel, Abhinav Kumar
On Fri, 21 Apr 2023 00:31:15 +0200, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
> 1 file changed, 216 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: dsi@5e94000: compatible: 'oneOf' conditional failed, one must be fixed:
'qcom,sm6375-dsi-ctrl' is not one of ['qcom,apq8064-dsi-ctrl', 'qcom,msm8916-dsi-ctrl', 'qcom,msm8953-dsi-ctrl', 'qcom,msm8974-dsi-ctrl', 'qcom,msm8996-dsi-ctrl', 'qcom,msm8998-dsi-ctrl', 'qcom,qcm2290-dsi-ctrl', 'qcom,sc7180-dsi-ctrl', 'qcom,sc7280-dsi-ctrl', 'qcom,sdm660-dsi-ctrl', 'qcom,sdm845-dsi-ctrl', 'qcom,sm8150-dsi-ctrl', 'qcom,sm8250-dsi-ctrl', 'qcom,sm8350-dsi-ctrl', 'qcom,sm8450-dsi-ctrl', 'qcom,sm8550-dsi-ctrl']
'qcom,sm6375-dsi-ctrl' is not one of ['dsi-ctrl-6g-qcm2290']
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: dsi@5e94000: Unevaluated properties are not allowed ('compatible' was unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230411-topic-straitlagoon_mdss-v2-6-5def73f50980@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-25 16:53 ` Rob Herring
-1 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-25 16:53 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On Fri, Apr 21, 2023 at 12:31:12AM +0200, Konrad Dybcio wrote:
> Document the SM6350 DPU.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> new file mode 100644
> index 000000000000..979fcf81afc9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DPU dt properties for SM6350 target
> +
> +maintainers:
> + - Konrad Dybcio <konrad.dybcio@linaro.org>
> +
> +$ref: /schemas/display/msm/dpu-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sm6350-dpu
> +
> + reg:
> + items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
Drop 'Address offset and size for '
With that,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
@ 2023-04-25 16:53 ` Rob Herring
0 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-25 16:53 UTC (permalink / raw)
To: Konrad Dybcio
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Abhinav Kumar, dri-devel, linux-kernel,
Krishna Manikandan, linux-arm-msm, Dmitry Baryshkov,
Marijn Suijten, linux-arm-kernel, Robin Murphy
On Fri, Apr 21, 2023 at 12:31:12AM +0200, Konrad Dybcio wrote:
> Document the SM6350 DPU.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> new file mode 100644
> index 000000000000..979fcf81afc9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DPU dt properties for SM6350 target
> +
> +maintainers:
> + - Konrad Dybcio <konrad.dybcio@linaro.org>
> +
> +$ref: /schemas/display/msm/dpu-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sm6350-dpu
> +
> + reg:
> + items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
Drop 'Address offset and size for '
With that,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
@ 2023-04-25 16:53 ` Rob Herring
0 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-25 16:53 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On Fri, Apr 21, 2023 at 12:31:12AM +0200, Konrad Dybcio wrote:
> Document the SM6350 DPU.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> new file mode 100644
> index 000000000000..979fcf81afc9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DPU dt properties for SM6350 target
> +
> +maintainers:
> + - Konrad Dybcio <konrad.dybcio@linaro.org>
> +
> +$ref: /schemas/display/msm/dpu-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sm6350-dpu
> +
> + reg:
> + items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
Drop 'Address offset and size for '
With that,
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-25 17:03 ` Rob Herring
-1 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-25 17:03 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On Fri, Apr 21, 2023 at 12:31:12AM +0200, Konrad Dybcio wrote:
> Document the SM6350 DPU.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> new file mode 100644
> index 000000000000..979fcf81afc9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DPU dt properties for SM6350 target
> +
> +maintainers:
> + - Konrad Dybcio <konrad.dybcio@linaro.org>
> +
> +$ref: /schemas/display/msm/dpu-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sm6350-dpu
> +
> + reg:
> + items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
> +
> + reg-names:
> + items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> + items:
> + - description: Display axi clock
> + - description: Display ahb clock
> + - description: Display rot clock
> + - description: Display lut clock
> + - description: Display core clock
> + - description: Display vsync clock
> +
> + clock-names:
> + items:
> + - const: bus
> + - const: iface
> + - const: rot
> + - const: lut
> + - const: core
> + - const: vsync
Is there some reason the clocks are in different order? They appear to
be the same minus the 'throttle' clock. Is there really no 'throttle'
clock? Maybe this platform just tied it to one of the same clocks in the
above?
I really hate the mess that is clocks. We have the same or related
blocks with just totally different names and order. The result is
if/then schemas or separate schemas like this. Neither option is great,
but at least the if/then schemas provides some motivation to not have
pointless variations like this. </rant>
As it seems the only difference between these 2 bindings is 1 extra
clock, can't they be shared?
Rob
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
@ 2023-04-25 17:03 ` Rob Herring
0 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-25 17:03 UTC (permalink / raw)
To: Konrad Dybcio
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Abhinav Kumar, dri-devel, linux-kernel,
Krishna Manikandan, linux-arm-msm, Dmitry Baryshkov,
Marijn Suijten, linux-arm-kernel, Robin Murphy
On Fri, Apr 21, 2023 at 12:31:12AM +0200, Konrad Dybcio wrote:
> Document the SM6350 DPU.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> new file mode 100644
> index 000000000000..979fcf81afc9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DPU dt properties for SM6350 target
> +
> +maintainers:
> + - Konrad Dybcio <konrad.dybcio@linaro.org>
> +
> +$ref: /schemas/display/msm/dpu-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sm6350-dpu
> +
> + reg:
> + items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
> +
> + reg-names:
> + items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> + items:
> + - description: Display axi clock
> + - description: Display ahb clock
> + - description: Display rot clock
> + - description: Display lut clock
> + - description: Display core clock
> + - description: Display vsync clock
> +
> + clock-names:
> + items:
> + - const: bus
> + - const: iface
> + - const: rot
> + - const: lut
> + - const: core
> + - const: vsync
Is there some reason the clocks are in different order? They appear to
be the same minus the 'throttle' clock. Is there really no 'throttle'
clock? Maybe this platform just tied it to one of the same clocks in the
above?
I really hate the mess that is clocks. We have the same or related
blocks with just totally different names and order. The result is
if/then schemas or separate schemas like this. Neither option is great,
but at least the if/then schemas provides some motivation to not have
pointless variations like this. </rant>
As it seems the only difference between these 2 bindings is 1 extra
clock, can't they be shared?
Rob
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
@ 2023-04-25 17:03 ` Rob Herring
0 siblings, 0 replies; 127+ messages in thread
From: Rob Herring @ 2023-04-25 17:03 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On Fri, Apr 21, 2023 at 12:31:12AM +0200, Konrad Dybcio wrote:
> Document the SM6350 DPU.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> new file mode 100644
> index 000000000000..979fcf81afc9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DPU dt properties for SM6350 target
> +
> +maintainers:
> + - Konrad Dybcio <konrad.dybcio@linaro.org>
> +
> +$ref: /schemas/display/msm/dpu-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sm6350-dpu
> +
> + reg:
> + items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
> +
> + reg-names:
> + items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> + items:
> + - description: Display axi clock
> + - description: Display ahb clock
> + - description: Display rot clock
> + - description: Display lut clock
> + - description: Display core clock
> + - description: Display vsync clock
> +
> + clock-names:
> + items:
> + - const: bus
> + - const: iface
> + - const: rot
> + - const: lut
> + - const: core
> + - const: vsync
Is there some reason the clocks are in different order? They appear to
be the same minus the 'throttle' clock. Is there really no 'throttle'
clock? Maybe this platform just tied it to one of the same clocks in the
above?
I really hate the mess that is clocks. We have the same or related
blocks with just totally different names and order. The result is
if/then schemas or separate schemas like this. Neither option is great,
but at least the if/then schemas provides some motivation to not have
pointless variations like this. </rant>
As it seems the only difference between these 2 bindings is 1 extra
clock, can't they be shared?
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-27 15:37 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 15:37 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu, Konrad Dybcio
On 2023-04-21 00:31:16, Konrad Dybcio wrote:
> Add SM6350 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
After addressing the comments from Dmitry (CURSOR0->DMA1 and
CURSOR1->DMA2), this is:
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
See below for some nits.
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 196 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> new file mode 100644
> index 000000000000..687a508cbaa6
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -0,0 +1,191 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_4_SM6350_H
> +#define _DPU_6_4_SM6350_H
> +
> +static const struct dpu_caps sm6350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0x7,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
I thought it was QSEED3LITE, but doesn't really matter as both are
handled similarly. It'll anyway change when I resubmit:
https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
which should hardcode the register value directly, making this field
superfluous.
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> +};
> +
> +static const struct dpu_lm_cfg sm6350_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
These two entries are indented with two tabs and have one character too
many to align with the opening parenthesis on the previous line. Can we
please settle on a single style, as this commit mostly uses tabs+spaces
to align with the opening parenthesis?
Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
line with zero extra characters to the opening parenthesis), but I find
double tabs more convenient as it doesn't require reindenting when
changing the name of the macro (which happened too often in my INTF TE
series).
> +};
> +
> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static struct dpu_pingpong_cfg sm6350_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + -1),
Glad to see no TE2 here, we just removed it from all of DPU >= 5.0.0
instead of >= 7.0.0 in [1] as downstream DTS turned out to be wrong.
[1]: https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-2-27ce1a5ab5c6@somainline.org/
- Marijn
> +};
> +
> +static const struct dpu_intf_cfg sm6350_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x1044,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> +static const struct dpu_perf_cfg sm6350_perf_data = {
> + .max_bw_low = 4200000,
> + .max_bw_high = 5100000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 35,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> + .caps = &sm6350_dpu_caps,
> + .ubwc = &sm6350_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
> + .mdp = sm6350_mdp,
> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
> + .ctl = sm6350_ctl,
> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
> + .sspp = sm6350_sspp,
> + .mixer_count = ARRAY_SIZE(sm6350_lm),
> + .mixer = sm6350_lm,
> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
> + .dspp = sm6350_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
> + .pingpong = sm6350_pp,
> + .intf_count = ARRAY_SIZE(sm6350_intf),
> + .intf = sm6350_intf,
> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
> + .vbif = sm6350_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8250_regdma,
> + .perf = &sm6350_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR)
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index db558a9ae36e..52750b592b36 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_0_sm8250.h"
> #include "catalog/dpu_6_2_sc7180.h"
> #include "catalog/dpu_6_3_sm6115.h"
> +#include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 756bff1d2185..f9611bd75e02 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
> DPU_QOS_LUT_USAGE_LINEAR,
> DPU_QOS_LUT_USAGE_MACROTILE,
> DPU_QOS_LUT_USAGE_NRT,
> + DPU_QOS_LUT_USAGE_CWB,
> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
> DPU_QOS_LUT_USAGE_MAX,
> };
>
> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 0e7a68714e9e..46be7ad8d615 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-27 15:37 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 15:37 UTC (permalink / raw)
To: Konrad Dybcio
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Konrad Dybcio, Abhinav Kumar, dri-devel,
linux-kernel, Rob Herring, Krishna Manikandan, linux-arm-msm,
Dmitry Baryshkov, linux-arm-kernel, Robin Murphy
On 2023-04-21 00:31:16, Konrad Dybcio wrote:
> Add SM6350 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
After addressing the comments from Dmitry (CURSOR0->DMA1 and
CURSOR1->DMA2), this is:
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
See below for some nits.
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 196 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> new file mode 100644
> index 000000000000..687a508cbaa6
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -0,0 +1,191 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_4_SM6350_H
> +#define _DPU_6_4_SM6350_H
> +
> +static const struct dpu_caps sm6350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0x7,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
I thought it was QSEED3LITE, but doesn't really matter as both are
handled similarly. It'll anyway change when I resubmit:
https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
which should hardcode the register value directly, making this field
superfluous.
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> +};
> +
> +static const struct dpu_lm_cfg sm6350_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
These two entries are indented with two tabs and have one character too
many to align with the opening parenthesis on the previous line. Can we
please settle on a single style, as this commit mostly uses tabs+spaces
to align with the opening parenthesis?
Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
line with zero extra characters to the opening parenthesis), but I find
double tabs more convenient as it doesn't require reindenting when
changing the name of the macro (which happened too often in my INTF TE
series).
> +};
> +
> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static struct dpu_pingpong_cfg sm6350_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + -1),
Glad to see no TE2 here, we just removed it from all of DPU >= 5.0.0
instead of >= 7.0.0 in [1] as downstream DTS turned out to be wrong.
[1]: https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-2-27ce1a5ab5c6@somainline.org/
- Marijn
> +};
> +
> +static const struct dpu_intf_cfg sm6350_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x1044,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> +static const struct dpu_perf_cfg sm6350_perf_data = {
> + .max_bw_low = 4200000,
> + .max_bw_high = 5100000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 35,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> + .caps = &sm6350_dpu_caps,
> + .ubwc = &sm6350_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
> + .mdp = sm6350_mdp,
> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
> + .ctl = sm6350_ctl,
> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
> + .sspp = sm6350_sspp,
> + .mixer_count = ARRAY_SIZE(sm6350_lm),
> + .mixer = sm6350_lm,
> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
> + .dspp = sm6350_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
> + .pingpong = sm6350_pp,
> + .intf_count = ARRAY_SIZE(sm6350_intf),
> + .intf = sm6350_intf,
> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
> + .vbif = sm6350_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8250_regdma,
> + .perf = &sm6350_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR)
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index db558a9ae36e..52750b592b36 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_0_sm8250.h"
> #include "catalog/dpu_6_2_sc7180.h"
> #include "catalog/dpu_6_3_sm6115.h"
> +#include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 756bff1d2185..f9611bd75e02 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
> DPU_QOS_LUT_USAGE_LINEAR,
> DPU_QOS_LUT_USAGE_MACROTILE,
> DPU_QOS_LUT_USAGE_NRT,
> + DPU_QOS_LUT_USAGE_CWB,
> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
> DPU_QOS_LUT_USAGE_MAX,
> };
>
> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 0e7a68714e9e..46be7ad8d615 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-27 15:37 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 15:37 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu, Konrad Dybcio
On 2023-04-21 00:31:16, Konrad Dybcio wrote:
> Add SM6350 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
After addressing the comments from Dmitry (CURSOR0->DMA1 and
CURSOR1->DMA2), this is:
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
See below for some nits.
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 196 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> new file mode 100644
> index 000000000000..687a508cbaa6
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -0,0 +1,191 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_4_SM6350_H
> +#define _DPU_6_4_SM6350_H
> +
> +static const struct dpu_caps sm6350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0x7,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
I thought it was QSEED3LITE, but doesn't really matter as both are
handled similarly. It'll anyway change when I resubmit:
https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
which should hardcode the register value directly, making this field
superfluous.
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> +};
> +
> +static const struct dpu_lm_cfg sm6350_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
These two entries are indented with two tabs and have one character too
many to align with the opening parenthesis on the previous line. Can we
please settle on a single style, as this commit mostly uses tabs+spaces
to align with the opening parenthesis?
Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
line with zero extra characters to the opening parenthesis), but I find
double tabs more convenient as it doesn't require reindenting when
changing the name of the macro (which happened too often in my INTF TE
series).
> +};
> +
> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static struct dpu_pingpong_cfg sm6350_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + -1),
Glad to see no TE2 here, we just removed it from all of DPU >= 5.0.0
instead of >= 7.0.0 in [1] as downstream DTS turned out to be wrong.
[1]: https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-2-27ce1a5ab5c6@somainline.org/
- Marijn
> +};
> +
> +static const struct dpu_intf_cfg sm6350_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x1044,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> +static const struct dpu_perf_cfg sm6350_perf_data = {
> + .max_bw_low = 4200000,
> + .max_bw_high = 5100000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 35,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> + .caps = &sm6350_dpu_caps,
> + .ubwc = &sm6350_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
> + .mdp = sm6350_mdp,
> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
> + .ctl = sm6350_ctl,
> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
> + .sspp = sm6350_sspp,
> + .mixer_count = ARRAY_SIZE(sm6350_lm),
> + .mixer = sm6350_lm,
> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
> + .dspp = sm6350_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
> + .pingpong = sm6350_pp,
> + .intf_count = ARRAY_SIZE(sm6350_intf),
> + .intf = sm6350_intf,
> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
> + .vbif = sm6350_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8250_regdma,
> + .perf = &sm6350_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR)
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index db558a9ae36e..52750b592b36 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_0_sm8250.h"
> #include "catalog/dpu_6_2_sc7180.h"
> #include "catalog/dpu_6_3_sm6115.h"
> +#include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 756bff1d2185..f9611bd75e02 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
> DPU_QOS_LUT_USAGE_LINEAR,
> DPU_QOS_LUT_USAGE_MACROTILE,
> DPU_QOS_LUT_USAGE_NRT,
> + DPU_QOS_LUT_USAGE_CWB,
> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
> DPU_QOS_LUT_USAGE_MAX,
> };
>
> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 0e7a68714e9e..46be7ad8d615 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
> --
> 2.40.0
>
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-27 15:46 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 15:46 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu
On 2023-04-21 00:31:18, Konrad Dybcio wrote:
> Add basic SM6375 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 5 files changed, 168 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 687a508cbaa6..d46b43964be6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
> },
> };
>
> -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> - {.fl = 0, .lut = 0x0011223344556677 },
> - {.fl = 0, .lut = 0x0011223445566777 },
> -};
> -
> static const struct dpu_perf_cfg sm6350_perf_data = {
> .max_bw_low = 4200000,
> .max_bw_high = 5100000,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> new file mode 100644
> index 000000000000..19ca0051e072
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -0,0 +1,152 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_9_SM6375_H
> +#define _DPU_6_9_SM6375_H
> +
> +static const struct dpu_caps sm6375_dpu_caps = {
> + .max_mixer_width = 2048,
> + .max_mixer_blendstages = 0x4,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = 2160,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6375_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6375_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> +};
> +
> +static const struct dpu_lm_cfg sm6375_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
Same indentation nit here as in SM6350.
> +};
> +
> +static const struct dpu_dspp_cfg sm6375_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static const struct dpu_pingpong_cfg sm6375_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> +};
> +
> +static const struct dpu_intf_cfg sm6375_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x2008,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rp_remap_size = 0x40,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_perf_cfg sm6375_perf_data = {
> + .max_bw_low = 5200000,
> + .max_bw_high = 6200000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0, /* No LLCC on this SoC */
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 24,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6375_cfg = {
> + .caps = &sm6375_dpu_caps,
> + .ubwc = &sm6375_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
> + .mdp = sm6375_mdp,
> + .ctl_count = ARRAY_SIZE(sm6375_ctl),
> + .ctl = sm6375_ctl,
> + .sspp_count = ARRAY_SIZE(sm6375_sspp),
> + .sspp = sm6375_sspp,
> + .mixer_count = ARRAY_SIZE(sm6375_lm),
> + .mixer = sm6375_lm,
> + .dspp_count = ARRAY_SIZE(sm6375_dspp),
> + .dspp = sm6375_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6375_pp),
> + .pingpong = sm6375_pp,
> + .intf_count = ARRAY_SIZE(sm6375_intf),
> + .intf = sm6375_intf,
> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
> + .vbif = sm6375_vbif,
> + .perf = &sm6375_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
INTF0 is set to INTF_NONE, no point in turning on the interrupt for it.
https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-1-27ce1a5ab5c6@somainline.org/
> + BIT(MDP_INTF1_INTR)
And you might want to turn on MDP_INTF1_TEAR_INTR (same on SM6350), that
could explain why INTF TE wasn't working on these SoCs yet.
- Marijn
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 52750b592b36..29516273dd6b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
> },
> };
>
> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
> + .maxwidth = 2048,
> + .maxblendstages = 4, /* excluding base layer */
> + .blendstage_base = { /* offsets relative to mixer base */
> + 0x20, 0x38, 0x50, 0x68
> + },
> +};
> +
> /* QCM2290 */
>
> static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
> @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222335777},
> };
>
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222223357 },
> };
> @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_3_sm6115.h"
> #include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
> +#include "catalog/dpu_6_9_sm6375.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> #include "catalog/dpu_7_2_sc7280.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index f9611bd75e02..b4f193037869 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 46be7ad8d615..980c3c8f8269 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> + { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
@ 2023-04-27 15:46 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 15:46 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu
On 2023-04-21 00:31:18, Konrad Dybcio wrote:
> Add basic SM6375 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 5 files changed, 168 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 687a508cbaa6..d46b43964be6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
> },
> };
>
> -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> - {.fl = 0, .lut = 0x0011223344556677 },
> - {.fl = 0, .lut = 0x0011223445566777 },
> -};
> -
> static const struct dpu_perf_cfg sm6350_perf_data = {
> .max_bw_low = 4200000,
> .max_bw_high = 5100000,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> new file mode 100644
> index 000000000000..19ca0051e072
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -0,0 +1,152 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_9_SM6375_H
> +#define _DPU_6_9_SM6375_H
> +
> +static const struct dpu_caps sm6375_dpu_caps = {
> + .max_mixer_width = 2048,
> + .max_mixer_blendstages = 0x4,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = 2160,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6375_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6375_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> +};
> +
> +static const struct dpu_lm_cfg sm6375_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
Same indentation nit here as in SM6350.
> +};
> +
> +static const struct dpu_dspp_cfg sm6375_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static const struct dpu_pingpong_cfg sm6375_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> +};
> +
> +static const struct dpu_intf_cfg sm6375_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x2008,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rp_remap_size = 0x40,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_perf_cfg sm6375_perf_data = {
> + .max_bw_low = 5200000,
> + .max_bw_high = 6200000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0, /* No LLCC on this SoC */
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 24,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6375_cfg = {
> + .caps = &sm6375_dpu_caps,
> + .ubwc = &sm6375_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
> + .mdp = sm6375_mdp,
> + .ctl_count = ARRAY_SIZE(sm6375_ctl),
> + .ctl = sm6375_ctl,
> + .sspp_count = ARRAY_SIZE(sm6375_sspp),
> + .sspp = sm6375_sspp,
> + .mixer_count = ARRAY_SIZE(sm6375_lm),
> + .mixer = sm6375_lm,
> + .dspp_count = ARRAY_SIZE(sm6375_dspp),
> + .dspp = sm6375_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6375_pp),
> + .pingpong = sm6375_pp,
> + .intf_count = ARRAY_SIZE(sm6375_intf),
> + .intf = sm6375_intf,
> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
> + .vbif = sm6375_vbif,
> + .perf = &sm6375_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
INTF0 is set to INTF_NONE, no point in turning on the interrupt for it.
https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-1-27ce1a5ab5c6@somainline.org/
> + BIT(MDP_INTF1_INTR)
And you might want to turn on MDP_INTF1_TEAR_INTR (same on SM6350), that
could explain why INTF TE wasn't working on these SoCs yet.
- Marijn
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 52750b592b36..29516273dd6b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
> },
> };
>
> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
> + .maxwidth = 2048,
> + .maxblendstages = 4, /* excluding base layer */
> + .blendstage_base = { /* offsets relative to mixer base */
> + 0x20, 0x38, 0x50, 0x68
> + },
> +};
> +
> /* QCM2290 */
>
> static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
> @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222335777},
> };
>
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222223357 },
> };
> @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_3_sm6115.h"
> #include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
> +#include "catalog/dpu_6_9_sm6375.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> #include "catalog/dpu_7_2_sc7280.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index f9611bd75e02..b4f193037869 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 46be7ad8d615..980c3c8f8269 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> + { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
> --
> 2.40.0
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
@ 2023-04-27 15:46 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 15:46 UTC (permalink / raw)
To: Konrad Dybcio
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Abhinav Kumar, dri-devel, linux-kernel,
Rob Herring, Krishna Manikandan, linux-arm-msm, Dmitry Baryshkov,
linux-arm-kernel, Robin Murphy
On 2023-04-21 00:31:18, Konrad Dybcio wrote:
> Add basic SM6375 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 5 files changed, 168 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 687a508cbaa6..d46b43964be6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
> },
> };
>
> -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> - {.fl = 0, .lut = 0x0011223344556677 },
> - {.fl = 0, .lut = 0x0011223445566777 },
> -};
> -
> static const struct dpu_perf_cfg sm6350_perf_data = {
> .max_bw_low = 4200000,
> .max_bw_high = 5100000,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> new file mode 100644
> index 000000000000..19ca0051e072
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -0,0 +1,152 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef _DPU_6_9_SM6375_H
> +#define _DPU_6_9_SM6375_H
> +
> +static const struct dpu_caps sm6375_dpu_caps = {
> + .max_mixer_width = 2048,
> + .max_mixer_blendstages = 0x4,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = 2160,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_swizzle = 6,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + },
> +};
> +
> +static const struct dpu_ctl_cfg sm6375_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6375_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> +};
> +
> +static const struct dpu_lm_cfg sm6375_lm[] = {
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
Same indentation nit here as in SM6350.
> +};
> +
> +static const struct dpu_dspp_cfg sm6375_dspp[] = {
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> +static const struct dpu_pingpong_cfg sm6375_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> +};
> +
> +static const struct dpu_intf_cfg sm6375_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> +};
> +
> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x2008,
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rp_remap_size = 0x40,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> +static const struct dpu_perf_cfg sm6375_perf_data = {
> + .max_bw_low = 5200000,
> + .max_bw_high = 6200000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0, /* No LLCC on this SoC */
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 24,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> + .entries = sm6350_qos_linear_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm6375_cfg = {
> + .caps = &sm6375_dpu_caps,
> + .ubwc = &sm6375_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
> + .mdp = sm6375_mdp,
> + .ctl_count = ARRAY_SIZE(sm6375_ctl),
> + .ctl = sm6375_ctl,
> + .sspp_count = ARRAY_SIZE(sm6375_sspp),
> + .sspp = sm6375_sspp,
> + .mixer_count = ARRAY_SIZE(sm6375_lm),
> + .mixer = sm6375_lm,
> + .dspp_count = ARRAY_SIZE(sm6375_dspp),
> + .dspp = sm6375_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6375_pp),
> + .pingpong = sm6375_pp,
> + .intf_count = ARRAY_SIZE(sm6375_intf),
> + .intf = sm6375_intf,
> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
> + .vbif = sm6375_vbif,
> + .perf = &sm6375_perf_data,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
INTF0 is set to INTF_NONE, no point in turning on the interrupt for it.
https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-1-27ce1a5ab5c6@somainline.org/
> + BIT(MDP_INTF1_INTR)
And you might want to turn on MDP_INTF1_TEAR_INTR (same on SM6350), that
could explain why INTF TE wasn't working on these SoCs yet.
- Marijn
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 52750b592b36..29516273dd6b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
> },
> };
>
> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
> + .maxwidth = 2048,
> + .maxblendstages = 4, /* excluding base layer */
> + .blendstage_base = { /* offsets relative to mixer base */
> + 0x20, 0x38, 0x50, 0x68
> + },
> +};
> +
> /* QCM2290 */
>
> static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
> @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222335777},
> };
>
> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222223357 },
> };
> @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_6_3_sm6115.h"
> #include "catalog/dpu_6_4_sm6350.h"
> #include "catalog/dpu_6_5_qcm2290.h"
> +#include "catalog/dpu_6_9_sm6375.h"
>
> #include "catalog/dpu_7_0_sm8350.h"
> #include "catalog/dpu_7_2_sc7280.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index f9611bd75e02..b4f193037869 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
> extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 46be7ad8d615..980c3c8f8269 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
> + { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-27 15:37 ` Marijn Suijten
(?)
@ 2023-04-27 15:48 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 15:48 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu, Konrad Dybcio
On 2023-04-27 17:37:42, Marijn Suijten wrote:
> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
> > Add SM6350 support to the DPU1 driver to enable display output.
> >
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> After addressing the comments from Dmitry (CURSOR0->DMA1 and
> CURSOR1->DMA2), this is:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> See below for some nits.
Actually found one glaring issue that might explain why INTF TE wasn't
working for you the other day!
> > ---
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> > 4 files changed, 196 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> > new file mode 100644
> > index 000000000000..687a508cbaa6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> > @@ -0,0 +1,191 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> > + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> > + * Copyright (c) 2023, Linaro Limited
> > + */
> > +
> > +#ifndef _DPU_6_4_SM6350_H
> > +#define _DPU_6_4_SM6350_H
> > +
> > +static const struct dpu_caps sm6350_dpu_caps = {
> > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .max_mixer_blendstages = 0x7,
> > + .qseed_type = DPU_SSPP_SCALER_QSEED4,
>
> I thought it was QSEED3LITE, but doesn't really matter as both are
> handled similarly. It'll anyway change when I resubmit:
>
> https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
>
> which should hardcode the register value directly, making this field
> superfluous.
>
> > + .has_src_split = true,
> > + .has_dim_layer = true,
> > + .has_idle_pc = true,
> > + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > +};
> > +
> > +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
> > + .ubwc_version = DPU_HW_UBWC_VER_20,
> > + .ubwc_swizzle = 6,
> > + .highest_bank_bit = 1,
> > +};
> > +
> > +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + .base = 0x0, .len = 0x494,
> > + .features = 0,
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> > + },
> > +};
> > +
> > +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> > + {
> > + .name = "ctl_0", .id = CTL_0,
> > + .base = 0x1000, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> > + },
> > + {
> > + .name = "ctl_1", .id = CTL_1,
> > + .base = 0x1200, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> > + },
> > + {
> > + .name = "ctl_2", .id = CTL_2,
> > + .base = 0x1400, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> > + },
> > + {
> > + .name = "ctl_3", .id = CTL_3,
> > + .base = 0x1600, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> > + },
> > +};
> > +
> > +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> > + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> > + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> > + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> > + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> > +};
> > +
> > +static const struct dpu_lm_cfg sm6350_lm[] = {
> > + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> > + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> > + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> > + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
>
> These two entries are indented with two tabs and have one character too
> many to align with the opening parenthesis on the previous line. Can we
> please settle on a single style, as this commit mostly uses tabs+spaces
> to align with the opening parenthesis?
>
> Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> line with zero extra characters to the opening parenthesis), but I find
> double tabs more convenient as it doesn't require reindenting when
> changing the name of the macro (which happened too often in my INTF TE
> series).
>
> > +};
> > +
> > +static const struct dpu_dspp_cfg sm6350_dspp[] = {
> > + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> > + &sm8150_dspp_sblk),
> > +};
> > +
> > +static struct dpu_pingpong_cfg sm6350_pp[] = {
> > + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> > + -1),
> > + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> > + -1),
>
> Glad to see no TE2 here, we just removed it from all of DPU >= 5.0.0
> instead of >= 7.0.0 in [1] as downstream DTS turned out to be wrong.
>
> [1]: https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-2-27ce1a5ab5c6@somainline.org/
>
> - Marijn
>
> > +};
> > +
> > +static const struct dpu_intf_cfg sm6350_intf[] = {
> > + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> > + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> > + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> > +};
> > +
> > +static const struct dpu_vbif_cfg sm6350_vbif[] = {
> > + {
> > + .name = "vbif_0", .id = VBIF_RT,
> > + .base = 0, .len = 0x1044,
> > + .features = BIT(DPU_VBIF_QOS_REMAP),
> > + .xin_halt_timeout = 0x4000,
> > + .qos_rt_tbl = {
> > + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> > + .priority_lvl = sdm845_rt_pri_lvl,
> > + },
> > + .qos_nrt_tbl = {
> > + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> > + .priority_lvl = sdm845_nrt_pri_lvl,
> > + },
> > + .memtype_count = 14,
> > + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> > + },
> > +};
> > +
> > +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> > + {.fl = 0, .lut = 0x0011223344556677 },
> > + {.fl = 0, .lut = 0x0011223445566777 },
> > +};
> > +
> > +static const struct dpu_perf_cfg sm6350_perf_data = {
> > + .max_bw_low = 4200000,
> > + .max_bw_high = 5100000,
> > + .min_core_ib = 2500000,
> > + .min_llcc_ib = 0,
> > + .min_dram_ib = 1600000,
> > + .min_prefill_lines = 35,
> > + /* TODO: confirm danger_lut_tbl */
> > + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> > + .qos_lut_tbl = {
> > + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> > + .entries = sm6350_qos_linear_macrotile
> > + },
> > + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> > + .entries = sm6350_qos_linear_macrotile
> > + },
> > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> > + .entries = sc7180_qos_nrt
> > + },
> > + },
> > + .cdp_cfg = {
> > + {.rd_enable = 1, .wr_enable = 1},
> > + {.rd_enable = 1, .wr_enable = 0}
> > + },
> > + .clk_inefficiency_factor = 105,
> > + .bw_inefficiency_factor = 120,
> > +};
> > +
> > +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> > + .caps = &sm6350_dpu_caps,
> > + .ubwc = &sm6350_ubwc_cfg,
> > + .mdp_count = ARRAY_SIZE(sm6350_mdp),
> > + .mdp = sm6350_mdp,
> > + .ctl_count = ARRAY_SIZE(sm6350_ctl),
> > + .ctl = sm6350_ctl,
> > + .sspp_count = ARRAY_SIZE(sm6350_sspp),
> > + .sspp = sm6350_sspp,
> > + .mixer_count = ARRAY_SIZE(sm6350_lm),
> > + .mixer = sm6350_lm,
> > + .dspp_count = ARRAY_SIZE(sm6350_dspp),
> > + .dspp = sm6350_dspp,
> > + .pingpong_count = ARRAY_SIZE(sm6350_pp),
> > + .pingpong = sm6350_pp,
> > + .intf_count = ARRAY_SIZE(sm6350_intf),
> > + .intf = sm6350_intf,
> > + .vbif_count = ARRAY_SIZE(sm6350_vbif),
> > + .vbif = sm6350_vbif,
> > + .reg_dma_count = 1,
> > + .dma_cfg = &sm8250_regdma,
> > + .perf = &sm6350_perf_data,
> > + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > + BIT(MDP_SSPP_TOP0_INTR2) | \
> > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > + BIT(MDP_INTF0_INTR) | \
> > + BIT(MDP_INTF1_INTR)
For completeness I should've pointed out that you're missing
MDP_INTF1_TEAR_INTR here, likely resulting in INTF TE not working.
- Marijn
<snip>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-27 15:48 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 15:48 UTC (permalink / raw)
To: Konrad Dybcio
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Konrad Dybcio, Abhinav Kumar, dri-devel,
linux-kernel, Rob Herring, Krishna Manikandan, linux-arm-msm,
Dmitry Baryshkov, linux-arm-kernel, Robin Murphy
On 2023-04-27 17:37:42, Marijn Suijten wrote:
> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
> > Add SM6350 support to the DPU1 driver to enable display output.
> >
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> After addressing the comments from Dmitry (CURSOR0->DMA1 and
> CURSOR1->DMA2), this is:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> See below for some nits.
Actually found one glaring issue that might explain why INTF TE wasn't
working for you the other day!
> > ---
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> > 4 files changed, 196 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> > new file mode 100644
> > index 000000000000..687a508cbaa6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> > @@ -0,0 +1,191 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> > + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> > + * Copyright (c) 2023, Linaro Limited
> > + */
> > +
> > +#ifndef _DPU_6_4_SM6350_H
> > +#define _DPU_6_4_SM6350_H
> > +
> > +static const struct dpu_caps sm6350_dpu_caps = {
> > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .max_mixer_blendstages = 0x7,
> > + .qseed_type = DPU_SSPP_SCALER_QSEED4,
>
> I thought it was QSEED3LITE, but doesn't really matter as both are
> handled similarly. It'll anyway change when I resubmit:
>
> https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
>
> which should hardcode the register value directly, making this field
> superfluous.
>
> > + .has_src_split = true,
> > + .has_dim_layer = true,
> > + .has_idle_pc = true,
> > + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > +};
> > +
> > +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
> > + .ubwc_version = DPU_HW_UBWC_VER_20,
> > + .ubwc_swizzle = 6,
> > + .highest_bank_bit = 1,
> > +};
> > +
> > +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + .base = 0x0, .len = 0x494,
> > + .features = 0,
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> > + },
> > +};
> > +
> > +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> > + {
> > + .name = "ctl_0", .id = CTL_0,
> > + .base = 0x1000, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> > + },
> > + {
> > + .name = "ctl_1", .id = CTL_1,
> > + .base = 0x1200, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> > + },
> > + {
> > + .name = "ctl_2", .id = CTL_2,
> > + .base = 0x1400, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> > + },
> > + {
> > + .name = "ctl_3", .id = CTL_3,
> > + .base = 0x1600, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> > + },
> > +};
> > +
> > +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> > + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> > + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> > + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> > + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> > +};
> > +
> > +static const struct dpu_lm_cfg sm6350_lm[] = {
> > + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> > + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> > + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> > + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
>
> These two entries are indented with two tabs and have one character too
> many to align with the opening parenthesis on the previous line. Can we
> please settle on a single style, as this commit mostly uses tabs+spaces
> to align with the opening parenthesis?
>
> Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> line with zero extra characters to the opening parenthesis), but I find
> double tabs more convenient as it doesn't require reindenting when
> changing the name of the macro (which happened too often in my INTF TE
> series).
>
> > +};
> > +
> > +static const struct dpu_dspp_cfg sm6350_dspp[] = {
> > + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> > + &sm8150_dspp_sblk),
> > +};
> > +
> > +static struct dpu_pingpong_cfg sm6350_pp[] = {
> > + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> > + -1),
> > + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> > + -1),
>
> Glad to see no TE2 here, we just removed it from all of DPU >= 5.0.0
> instead of >= 7.0.0 in [1] as downstream DTS turned out to be wrong.
>
> [1]: https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-2-27ce1a5ab5c6@somainline.org/
>
> - Marijn
>
> > +};
> > +
> > +static const struct dpu_intf_cfg sm6350_intf[] = {
> > + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> > + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> > + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> > +};
> > +
> > +static const struct dpu_vbif_cfg sm6350_vbif[] = {
> > + {
> > + .name = "vbif_0", .id = VBIF_RT,
> > + .base = 0, .len = 0x1044,
> > + .features = BIT(DPU_VBIF_QOS_REMAP),
> > + .xin_halt_timeout = 0x4000,
> > + .qos_rt_tbl = {
> > + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> > + .priority_lvl = sdm845_rt_pri_lvl,
> > + },
> > + .qos_nrt_tbl = {
> > + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> > + .priority_lvl = sdm845_nrt_pri_lvl,
> > + },
> > + .memtype_count = 14,
> > + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> > + },
> > +};
> > +
> > +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> > + {.fl = 0, .lut = 0x0011223344556677 },
> > + {.fl = 0, .lut = 0x0011223445566777 },
> > +};
> > +
> > +static const struct dpu_perf_cfg sm6350_perf_data = {
> > + .max_bw_low = 4200000,
> > + .max_bw_high = 5100000,
> > + .min_core_ib = 2500000,
> > + .min_llcc_ib = 0,
> > + .min_dram_ib = 1600000,
> > + .min_prefill_lines = 35,
> > + /* TODO: confirm danger_lut_tbl */
> > + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> > + .qos_lut_tbl = {
> > + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> > + .entries = sm6350_qos_linear_macrotile
> > + },
> > + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> > + .entries = sm6350_qos_linear_macrotile
> > + },
> > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> > + .entries = sc7180_qos_nrt
> > + },
> > + },
> > + .cdp_cfg = {
> > + {.rd_enable = 1, .wr_enable = 1},
> > + {.rd_enable = 1, .wr_enable = 0}
> > + },
> > + .clk_inefficiency_factor = 105,
> > + .bw_inefficiency_factor = 120,
> > +};
> > +
> > +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> > + .caps = &sm6350_dpu_caps,
> > + .ubwc = &sm6350_ubwc_cfg,
> > + .mdp_count = ARRAY_SIZE(sm6350_mdp),
> > + .mdp = sm6350_mdp,
> > + .ctl_count = ARRAY_SIZE(sm6350_ctl),
> > + .ctl = sm6350_ctl,
> > + .sspp_count = ARRAY_SIZE(sm6350_sspp),
> > + .sspp = sm6350_sspp,
> > + .mixer_count = ARRAY_SIZE(sm6350_lm),
> > + .mixer = sm6350_lm,
> > + .dspp_count = ARRAY_SIZE(sm6350_dspp),
> > + .dspp = sm6350_dspp,
> > + .pingpong_count = ARRAY_SIZE(sm6350_pp),
> > + .pingpong = sm6350_pp,
> > + .intf_count = ARRAY_SIZE(sm6350_intf),
> > + .intf = sm6350_intf,
> > + .vbif_count = ARRAY_SIZE(sm6350_vbif),
> > + .vbif = sm6350_vbif,
> > + .reg_dma_count = 1,
> > + .dma_cfg = &sm8250_regdma,
> > + .perf = &sm6350_perf_data,
> > + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > + BIT(MDP_SSPP_TOP0_INTR2) | \
> > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > + BIT(MDP_INTF0_INTR) | \
> > + BIT(MDP_INTF1_INTR)
For completeness I should've pointed out that you're missing
MDP_INTF1_TEAR_INTR here, likely resulting in INTF TE not working.
- Marijn
<snip>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-27 15:48 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 15:48 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu, Konrad Dybcio
On 2023-04-27 17:37:42, Marijn Suijten wrote:
> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
> > Add SM6350 support to the DPU1 driver to enable display output.
> >
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> After addressing the comments from Dmitry (CURSOR0->DMA1 and
> CURSOR1->DMA2), this is:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> See below for some nits.
Actually found one glaring issue that might explain why INTF TE wasn't
working for you the other day!
> > ---
> > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> > 4 files changed, 196 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> > new file mode 100644
> > index 000000000000..687a508cbaa6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> > @@ -0,0 +1,191 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> > + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> > + * Copyright (c) 2023, Linaro Limited
> > + */
> > +
> > +#ifndef _DPU_6_4_SM6350_H
> > +#define _DPU_6_4_SM6350_H
> > +
> > +static const struct dpu_caps sm6350_dpu_caps = {
> > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .max_mixer_blendstages = 0x7,
> > + .qseed_type = DPU_SSPP_SCALER_QSEED4,
>
> I thought it was QSEED3LITE, but doesn't really matter as both are
> handled similarly. It'll anyway change when I resubmit:
>
> https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
>
> which should hardcode the register value directly, making this field
> superfluous.
>
> > + .has_src_split = true,
> > + .has_dim_layer = true,
> > + .has_idle_pc = true,
> > + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > +};
> > +
> > +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
> > + .ubwc_version = DPU_HW_UBWC_VER_20,
> > + .ubwc_swizzle = 6,
> > + .highest_bank_bit = 1,
> > +};
> > +
> > +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + .base = 0x0, .len = 0x494,
> > + .features = 0,
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> > + },
> > +};
> > +
> > +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> > + {
> > + .name = "ctl_0", .id = CTL_0,
> > + .base = 0x1000, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> > + },
> > + {
> > + .name = "ctl_1", .id = CTL_1,
> > + .base = 0x1200, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> > + },
> > + {
> > + .name = "ctl_2", .id = CTL_2,
> > + .base = 0x1400, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> > + },
> > + {
> > + .name = "ctl_3", .id = CTL_3,
> > + .base = 0x1600, .len = 0x1dc,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> > + },
> > +};
> > +
> > +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> > + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> > + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> > + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> > + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> > +};
> > +
> > +static const struct dpu_lm_cfg sm6350_lm[] = {
> > + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> > + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> > + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> > + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
>
> These two entries are indented with two tabs and have one character too
> many to align with the opening parenthesis on the previous line. Can we
> please settle on a single style, as this commit mostly uses tabs+spaces
> to align with the opening parenthesis?
>
> Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> line with zero extra characters to the opening parenthesis), but I find
> double tabs more convenient as it doesn't require reindenting when
> changing the name of the macro (which happened too often in my INTF TE
> series).
>
> > +};
> > +
> > +static const struct dpu_dspp_cfg sm6350_dspp[] = {
> > + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> > + &sm8150_dspp_sblk),
> > +};
> > +
> > +static struct dpu_pingpong_cfg sm6350_pp[] = {
> > + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> > + -1),
> > + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> > + -1),
>
> Glad to see no TE2 here, we just removed it from all of DPU >= 5.0.0
> instead of >= 7.0.0 in [1] as downstream DTS turned out to be wrong.
>
> [1]: https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-2-27ce1a5ab5c6@somainline.org/
>
> - Marijn
>
> > +};
> > +
> > +static const struct dpu_intf_cfg sm6350_intf[] = {
> > + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> > + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> > + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> > +};
> > +
> > +static const struct dpu_vbif_cfg sm6350_vbif[] = {
> > + {
> > + .name = "vbif_0", .id = VBIF_RT,
> > + .base = 0, .len = 0x1044,
> > + .features = BIT(DPU_VBIF_QOS_REMAP),
> > + .xin_halt_timeout = 0x4000,
> > + .qos_rt_tbl = {
> > + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> > + .priority_lvl = sdm845_rt_pri_lvl,
> > + },
> > + .qos_nrt_tbl = {
> > + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> > + .priority_lvl = sdm845_nrt_pri_lvl,
> > + },
> > + .memtype_count = 14,
> > + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> > + },
> > +};
> > +
> > +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
> > + {.fl = 0, .lut = 0x0011223344556677 },
> > + {.fl = 0, .lut = 0x0011223445566777 },
> > +};
> > +
> > +static const struct dpu_perf_cfg sm6350_perf_data = {
> > + .max_bw_low = 4200000,
> > + .max_bw_high = 5100000,
> > + .min_core_ib = 2500000,
> > + .min_llcc_ib = 0,
> > + .min_dram_ib = 1600000,
> > + .min_prefill_lines = 35,
> > + /* TODO: confirm danger_lut_tbl */
> > + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> > + .qos_lut_tbl = {
> > + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> > + .entries = sm6350_qos_linear_macrotile
> > + },
> > + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
> > + .entries = sm6350_qos_linear_macrotile
> > + },
> > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> > + .entries = sc7180_qos_nrt
> > + },
> > + },
> > + .cdp_cfg = {
> > + {.rd_enable = 1, .wr_enable = 1},
> > + {.rd_enable = 1, .wr_enable = 0}
> > + },
> > + .clk_inefficiency_factor = 105,
> > + .bw_inefficiency_factor = 120,
> > +};
> > +
> > +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> > + .caps = &sm6350_dpu_caps,
> > + .ubwc = &sm6350_ubwc_cfg,
> > + .mdp_count = ARRAY_SIZE(sm6350_mdp),
> > + .mdp = sm6350_mdp,
> > + .ctl_count = ARRAY_SIZE(sm6350_ctl),
> > + .ctl = sm6350_ctl,
> > + .sspp_count = ARRAY_SIZE(sm6350_sspp),
> > + .sspp = sm6350_sspp,
> > + .mixer_count = ARRAY_SIZE(sm6350_lm),
> > + .mixer = sm6350_lm,
> > + .dspp_count = ARRAY_SIZE(sm6350_dspp),
> > + .dspp = sm6350_dspp,
> > + .pingpong_count = ARRAY_SIZE(sm6350_pp),
> > + .pingpong = sm6350_pp,
> > + .intf_count = ARRAY_SIZE(sm6350_intf),
> > + .intf = sm6350_intf,
> > + .vbif_count = ARRAY_SIZE(sm6350_vbif),
> > + .vbif = sm6350_vbif,
> > + .reg_dma_count = 1,
> > + .dma_cfg = &sm8250_regdma,
> > + .perf = &sm6350_perf_data,
> > + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > + BIT(MDP_SSPP_TOP0_INTR2) | \
> > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > + BIT(MDP_INTF0_INTR) | \
> > + BIT(MDP_INTF1_INTR)
For completeness I should've pointed out that you're missing
MDP_INTF1_TEAR_INTR here, likely resulting in INTF TE not working.
- Marijn
<snip>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-27 21:03 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 21:03 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu
On 2023-04-21 00:31:17, Konrad Dybcio wrote:
> Add support for MDSS on SM6350.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index e8c93731aaa1..4e3a5f0c303c 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data = {
> .highest_bank_bit = 2,
> };
>
> +static const struct msm_mdss_data sm6350_data = {
> + .ubwc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_static = 0x1e,
> + .highest_bank_bit = 1,
> +};
> +
> static const struct msm_mdss_data sm8150_data = {
> .ubwc_version = UBWC_3_0,
> .ubwc_dec_version = UBWC_3_0,
> @@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
> + { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support
@ 2023-04-27 21:03 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 21:03 UTC (permalink / raw)
To: Konrad Dybcio
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Abhinav Kumar, dri-devel, linux-kernel,
Rob Herring, Krishna Manikandan, linux-arm-msm, Dmitry Baryshkov,
linux-arm-kernel, Robin Murphy
On 2023-04-21 00:31:17, Konrad Dybcio wrote:
> Add support for MDSS on SM6350.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index e8c93731aaa1..4e3a5f0c303c 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data = {
> .highest_bank_bit = 2,
> };
>
> +static const struct msm_mdss_data sm6350_data = {
> + .ubwc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_static = 0x1e,
> + .highest_bank_bit = 1,
> +};
> +
> static const struct msm_mdss_data sm8150_data = {
> .ubwc_version = UBWC_3_0,
> .ubwc_dec_version = UBWC_3_0,
> @@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
> + { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support
@ 2023-04-27 21:03 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 21:03 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu
On 2023-04-21 00:31:17, Konrad Dybcio wrote:
> Add support for MDSS on SM6350.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index e8c93731aaa1..4e3a5f0c303c 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data = {
> .highest_bank_bit = 2,
> };
>
> +static const struct msm_mdss_data sm6350_data = {
> + .ubwc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_static = 0x1e,
> + .highest_bank_bit = 1,
> +};
> +
> static const struct msm_mdss_data sm8150_data = {
> .ubwc_version = UBWC_3_0,
> .ubwc_dec_version = UBWC_3_0,
> @@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
> + { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>
> --
> 2.40.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
2023-04-20 22:31 ` Konrad Dybcio
(?)
@ 2023-04-27 21:04 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 21:04 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu
On 2023-04-21 00:31:19, Konrad Dybcio wrote:
> Add support for MDSS on SM6375.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
(After reusing sm6350 data, as suggested by Dmitry)
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 4e3a5f0c303c..f2470ce699f7 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
> .highest_bank_bit = 1,
> };
>
> +static const struct msm_mdss_data sm6375_data = {
> + .ubwc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_static = 0x1e,
> + /* Possibly 0 for LPDDR3 */
> + .highest_bank_bit = 1,
> +};
> +
> static const struct msm_mdss_data sm8150_data = {
> .ubwc_version = UBWC_3_0,
> .ubwc_dec_version = UBWC_3_0,
> @@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
> { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
> + { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
@ 2023-04-27 21:04 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 21:04 UTC (permalink / raw)
To: Konrad Dybcio
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Abhinav Kumar, dri-devel, linux-kernel,
Rob Herring, Krishna Manikandan, linux-arm-msm, Dmitry Baryshkov,
linux-arm-kernel, Robin Murphy
On 2023-04-21 00:31:19, Konrad Dybcio wrote:
> Add support for MDSS on SM6375.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
(After reusing sm6350 data, as suggested by Dmitry)
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 4e3a5f0c303c..f2470ce699f7 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
> .highest_bank_bit = 1,
> };
>
> +static const struct msm_mdss_data sm6375_data = {
> + .ubwc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_static = 0x1e,
> + /* Possibly 0 for LPDDR3 */
> + .highest_bank_bit = 1,
> +};
> +
> static const struct msm_mdss_data sm8150_data = {
> .ubwc_version = UBWC_3_0,
> .ubwc_dec_version = UBWC_3_0,
> @@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
> { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
> + { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support
@ 2023-04-27 21:04 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-04-27 21:04 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu
On 2023-04-21 00:31:19, Konrad Dybcio wrote:
> Add support for MDSS on SM6375.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
(After reusing sm6350 data, as suggested by Dmitry)
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 4e3a5f0c303c..f2470ce699f7 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data = {
> .highest_bank_bit = 1,
> };
>
> +static const struct msm_mdss_data sm6375_data = {
> + .ubwc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_static = 0x1e,
> + /* Possibly 0 for LPDDR3 */
> + .highest_bank_bit = 1,
> +};
> +
> static const struct msm_mdss_data sm8150_data = {
> .ubwc_version = UBWC_3_0,
> .ubwc_dec_version = UBWC_3_0,
> @@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
> { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
> { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
> + { .compatible = "qcom,sm6375-mdss", .data = &sm6375_data },
> { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
> { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
> { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>
> --
> 2.40.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-27 15:37 ` Marijn Suijten
(?)
@ 2023-04-28 12:24 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-28 12:24 UTC (permalink / raw)
To: Marijn Suijten
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu, Konrad Dybcio
[...]
>> +
>> +static const struct dpu_caps sm6350_dpu_caps = {
>> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .max_mixer_blendstages = 0x7,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> I thought it was QSEED3LITE, but doesn't really matter as both are
> handled similarly. It'll anyway change when I resubmit:
>
> https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
>
> which should hardcode the register value directly, making this field
> superfluous.
Okay, so I'll just resubmit as-is, I suppose?
[...]
>> +static const struct dpu_lm_cfg sm6350_lm[] = {
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
>> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> These two entries are indented with two tabs and have one character too
> many to align with the opening parenthesis on the previous line. Can we
> please settle on a single style, as this commit mostly uses tabs+spaces
> to align with the opening parenthesis?
>
> Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> line with zero extra characters to the opening parenthesis), but I find
> double tabs more convenient as it doesn't require reindenting when
> changing the name of the macro (which happened too often in my INTF TE
> series).
sure, let's go with that Dmitry suggested!
Konrad
>
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
>> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> + &sm8150_dspp_sblk),
>> +};
>> +
>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> + -1),
>> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> + -1),
> Glad to see no TE2 here, we just removed it from all of DPU >= 5.0.0
> instead of >= 7.0.0 in [1] as downstream DTS turned out to be wrong.
>
> [1]: https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-2-27ce1a5ab5c6@somainline.org/
>
> - Marijn
>
>> +};
>> +
>> +static const struct dpu_intf_cfg sm6350_intf[] = {
>> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
>> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
>> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>> +};
>> +
>> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
>> + {
>> + .name = "vbif_0", .id = VBIF_RT,
>> + .base = 0, .len = 0x1044,
>> + .features = BIT(DPU_VBIF_QOS_REMAP),
>> + .xin_halt_timeout = 0x4000,
>> + .qos_rt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
>> + .priority_lvl = sdm845_rt_pri_lvl,
>> + },
>> + .qos_nrt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
>> + .priority_lvl = sdm845_nrt_pri_lvl,
>> + },
>> + .memtype_count = 14,
>> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
>> + },
>> +};
>> +
>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>> +};
>> +
>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>> + .max_bw_low = 4200000,
>> + .max_bw_high = 5100000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0,
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 35,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
>> + .qos_lut_tbl = {
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> + .entries = sc7180_qos_nrt
>> + },
>> + },
>> + .cdp_cfg = {
>> + {.rd_enable = 1, .wr_enable = 1},
>> + {.rd_enable = 1, .wr_enable = 0}
>> + },
>> + .clk_inefficiency_factor = 105,
>> + .bw_inefficiency_factor = 120,
>> +};
>> +
>> +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
>> + .caps = &sm6350_dpu_caps,
>> + .ubwc = &sm6350_ubwc_cfg,
>> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
>> + .mdp = sm6350_mdp,
>> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
>> + .ctl = sm6350_ctl,
>> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
>> + .sspp = sm6350_sspp,
>> + .mixer_count = ARRAY_SIZE(sm6350_lm),
>> + .mixer = sm6350_lm,
>> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
>> + .dspp = sm6350_dspp,
>> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
>> + .pingpong = sm6350_pp,
>> + .intf_count = ARRAY_SIZE(sm6350_intf),
>> + .intf = sm6350_intf,
>> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
>> + .vbif = sm6350_vbif,
>> + .reg_dma_count = 1,
>> + .dma_cfg = &sm8250_regdma,
>> + .perf = &sm6350_perf_data,
>> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
>> + BIT(MDP_SSPP_TOP0_INTR2) | \
>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
>> + BIT(MDP_INTF0_INTR) | \
>> + BIT(MDP_INTF1_INTR)
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index db558a9ae36e..52750b592b36 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>> #include "catalog/dpu_6_0_sm8250.h"
>> #include "catalog/dpu_6_2_sc7180.h"
>> #include "catalog/dpu_6_3_sm6115.h"
>> +#include "catalog/dpu_6_4_sm6350.h"
>> #include "catalog/dpu_6_5_qcm2290.h"
>>
>> #include "catalog/dpu_7_0_sm8350.h"
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 756bff1d2185..f9611bd75e02 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>> DPU_QOS_LUT_USAGE_LINEAR,
>> DPU_QOS_LUT_USAGE_MACROTILE,
>> DPU_QOS_LUT_USAGE_NRT,
>> + DPU_QOS_LUT_USAGE_CWB,
>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>> DPU_QOS_LUT_USAGE_MAX,
>> };
>>
>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 0e7a68714e9e..46be7ad8d615 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>
>> --
>> 2.40.0
>>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-28 12:24 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-28 12:24 UTC (permalink / raw)
To: Marijn Suijten
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu, Konrad Dybcio
[...]
>> +
>> +static const struct dpu_caps sm6350_dpu_caps = {
>> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .max_mixer_blendstages = 0x7,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> I thought it was QSEED3LITE, but doesn't really matter as both are
> handled similarly. It'll anyway change when I resubmit:
>
> https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
>
> which should hardcode the register value directly, making this field
> superfluous.
Okay, so I'll just resubmit as-is, I suppose?
[...]
>> +static const struct dpu_lm_cfg sm6350_lm[] = {
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
>> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> These two entries are indented with two tabs and have one character too
> many to align with the opening parenthesis on the previous line. Can we
> please settle on a single style, as this commit mostly uses tabs+spaces
> to align with the opening parenthesis?
>
> Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> line with zero extra characters to the opening parenthesis), but I find
> double tabs more convenient as it doesn't require reindenting when
> changing the name of the macro (which happened too often in my INTF TE
> series).
sure, let's go with that Dmitry suggested!
Konrad
>
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
>> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> + &sm8150_dspp_sblk),
>> +};
>> +
>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> + -1),
>> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> + -1),
> Glad to see no TE2 here, we just removed it from all of DPU >= 5.0.0
> instead of >= 7.0.0 in [1] as downstream DTS turned out to be wrong.
>
> [1]: https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-2-27ce1a5ab5c6@somainline.org/
>
> - Marijn
>
>> +};
>> +
>> +static const struct dpu_intf_cfg sm6350_intf[] = {
>> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
>> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
>> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>> +};
>> +
>> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
>> + {
>> + .name = "vbif_0", .id = VBIF_RT,
>> + .base = 0, .len = 0x1044,
>> + .features = BIT(DPU_VBIF_QOS_REMAP),
>> + .xin_halt_timeout = 0x4000,
>> + .qos_rt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
>> + .priority_lvl = sdm845_rt_pri_lvl,
>> + },
>> + .qos_nrt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
>> + .priority_lvl = sdm845_nrt_pri_lvl,
>> + },
>> + .memtype_count = 14,
>> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
>> + },
>> +};
>> +
>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>> +};
>> +
>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>> + .max_bw_low = 4200000,
>> + .max_bw_high = 5100000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0,
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 35,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
>> + .qos_lut_tbl = {
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> + .entries = sc7180_qos_nrt
>> + },
>> + },
>> + .cdp_cfg = {
>> + {.rd_enable = 1, .wr_enable = 1},
>> + {.rd_enable = 1, .wr_enable = 0}
>> + },
>> + .clk_inefficiency_factor = 105,
>> + .bw_inefficiency_factor = 120,
>> +};
>> +
>> +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
>> + .caps = &sm6350_dpu_caps,
>> + .ubwc = &sm6350_ubwc_cfg,
>> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
>> + .mdp = sm6350_mdp,
>> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
>> + .ctl = sm6350_ctl,
>> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
>> + .sspp = sm6350_sspp,
>> + .mixer_count = ARRAY_SIZE(sm6350_lm),
>> + .mixer = sm6350_lm,
>> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
>> + .dspp = sm6350_dspp,
>> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
>> + .pingpong = sm6350_pp,
>> + .intf_count = ARRAY_SIZE(sm6350_intf),
>> + .intf = sm6350_intf,
>> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
>> + .vbif = sm6350_vbif,
>> + .reg_dma_count = 1,
>> + .dma_cfg = &sm8250_regdma,
>> + .perf = &sm6350_perf_data,
>> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
>> + BIT(MDP_SSPP_TOP0_INTR2) | \
>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
>> + BIT(MDP_INTF0_INTR) | \
>> + BIT(MDP_INTF1_INTR)
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index db558a9ae36e..52750b592b36 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>> #include "catalog/dpu_6_0_sm8250.h"
>> #include "catalog/dpu_6_2_sc7180.h"
>> #include "catalog/dpu_6_3_sm6115.h"
>> +#include "catalog/dpu_6_4_sm6350.h"
>> #include "catalog/dpu_6_5_qcm2290.h"
>>
>> #include "catalog/dpu_7_0_sm8350.h"
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 756bff1d2185..f9611bd75e02 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>> DPU_QOS_LUT_USAGE_LINEAR,
>> DPU_QOS_LUT_USAGE_MACROTILE,
>> DPU_QOS_LUT_USAGE_NRT,
>> + DPU_QOS_LUT_USAGE_CWB,
>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>> DPU_QOS_LUT_USAGE_MAX,
>> };
>>
>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 0e7a68714e9e..46be7ad8d615 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>
>> --
>> 2.40.0
>>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-28 12:24 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-28 12:24 UTC (permalink / raw)
To: Marijn Suijten
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Konrad Dybcio, Abhinav Kumar, dri-devel,
linux-kernel, Rob Herring, Krishna Manikandan, linux-arm-msm,
Dmitry Baryshkov, linux-arm-kernel, Robin Murphy
[...]
>> +
>> +static const struct dpu_caps sm6350_dpu_caps = {
>> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .max_mixer_blendstages = 0x7,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> I thought it was QSEED3LITE, but doesn't really matter as both are
> handled similarly. It'll anyway change when I resubmit:
>
> https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
>
> which should hardcode the register value directly, making this field
> superfluous.
Okay, so I'll just resubmit as-is, I suppose?
[...]
>> +static const struct dpu_lm_cfg sm6350_lm[] = {
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
>> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> These two entries are indented with two tabs and have one character too
> many to align with the opening parenthesis on the previous line. Can we
> please settle on a single style, as this commit mostly uses tabs+spaces
> to align with the opening parenthesis?
>
> Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> line with zero extra characters to the opening parenthesis), but I find
> double tabs more convenient as it doesn't require reindenting when
> changing the name of the macro (which happened too often in my INTF TE
> series).
sure, let's go with that Dmitry suggested!
Konrad
>
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
>> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> + &sm8150_dspp_sblk),
>> +};
>> +
>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> + -1),
>> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> + -1),
> Glad to see no TE2 here, we just removed it from all of DPU >= 5.0.0
> instead of >= 7.0.0 in [1] as downstream DTS turned out to be wrong.
>
> [1]: https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-2-27ce1a5ab5c6@somainline.org/
>
> - Marijn
>
>> +};
>> +
>> +static const struct dpu_intf_cfg sm6350_intf[] = {
>> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
>> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
>> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>> +};
>> +
>> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
>> + {
>> + .name = "vbif_0", .id = VBIF_RT,
>> + .base = 0, .len = 0x1044,
>> + .features = BIT(DPU_VBIF_QOS_REMAP),
>> + .xin_halt_timeout = 0x4000,
>> + .qos_rt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
>> + .priority_lvl = sdm845_rt_pri_lvl,
>> + },
>> + .qos_nrt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
>> + .priority_lvl = sdm845_nrt_pri_lvl,
>> + },
>> + .memtype_count = 14,
>> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
>> + },
>> +};
>> +
>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>> +};
>> +
>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>> + .max_bw_low = 4200000,
>> + .max_bw_high = 5100000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0,
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 35,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
>> + .qos_lut_tbl = {
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> + .entries = sc7180_qos_nrt
>> + },
>> + },
>> + .cdp_cfg = {
>> + {.rd_enable = 1, .wr_enable = 1},
>> + {.rd_enable = 1, .wr_enable = 0}
>> + },
>> + .clk_inefficiency_factor = 105,
>> + .bw_inefficiency_factor = 120,
>> +};
>> +
>> +const struct dpu_mdss_cfg dpu_sm6350_cfg = {
>> + .caps = &sm6350_dpu_caps,
>> + .ubwc = &sm6350_ubwc_cfg,
>> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
>> + .mdp = sm6350_mdp,
>> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
>> + .ctl = sm6350_ctl,
>> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
>> + .sspp = sm6350_sspp,
>> + .mixer_count = ARRAY_SIZE(sm6350_lm),
>> + .mixer = sm6350_lm,
>> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
>> + .dspp = sm6350_dspp,
>> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
>> + .pingpong = sm6350_pp,
>> + .intf_count = ARRAY_SIZE(sm6350_intf),
>> + .intf = sm6350_intf,
>> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
>> + .vbif = sm6350_vbif,
>> + .reg_dma_count = 1,
>> + .dma_cfg = &sm8250_regdma,
>> + .perf = &sm6350_perf_data,
>> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
>> + BIT(MDP_SSPP_TOP0_INTR2) | \
>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
>> + BIT(MDP_INTF0_INTR) | \
>> + BIT(MDP_INTF1_INTR)
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index db558a9ae36e..52750b592b36 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>> #include "catalog/dpu_6_0_sm8250.h"
>> #include "catalog/dpu_6_2_sc7180.h"
>> #include "catalog/dpu_6_3_sm6115.h"
>> +#include "catalog/dpu_6_4_sm6350.h"
>> #include "catalog/dpu_6_5_qcm2290.h"
>>
>> #include "catalog/dpu_7_0_sm8350.h"
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 756bff1d2185..f9611bd75e02 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>> DPU_QOS_LUT_USAGE_LINEAR,
>> DPU_QOS_LUT_USAGE_MACROTILE,
>> DPU_QOS_LUT_USAGE_NRT,
>> + DPU_QOS_LUT_USAGE_CWB,
>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>> DPU_QOS_LUT_USAGE_MAX,
>> };
>>
>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 0e7a68714e9e..46be7ad8d615 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>
>> --
>> 2.40.0
>>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-27 15:48 ` Marijn Suijten
(?)
@ 2023-04-28 12:25 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-28 12:25 UTC (permalink / raw)
To: Marijn Suijten
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu, Konrad Dybcio
On 4/27/23 16:48, Marijn Suijten wrote:
> On 2023-04-27 17:37:42, Marijn Suijten wrote:
>> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
>>> Add SM6350 support to the DPU1 driver to enable display output.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> After addressing the comments from Dmitry (CURSOR0->DMA1 and
>> CURSOR1->DMA2), this is:
>>
>> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>>
>> See below for some nits.
> Actually found one glaring issue that might explain why INTF TE wasn't
> working for you the other day!
[...]
>>> + .vbif = sm6350_vbif,
>>> + .reg_dma_count = 1,
>>> + .dma_cfg = &sm8250_regdma,
>>> + .perf = &sm6350_perf_data,
>>> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
>>> + BIT(MDP_SSPP_TOP0_INTR2) | \
>>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
>>> + BIT(MDP_INTF0_INTR) | \
>>> + BIT(MDP_INTF1_INTR)
> For completeness I should've pointed out that you're missing
> MDP_INTF1_TEAR_INTR here, likely resulting in INTF TE not working.
>
> - Marijn
<annoyed noises>
so it might have been this.. I'll retest, thanks!
Konrad
>
> <snip>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-28 12:25 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-28 12:25 UTC (permalink / raw)
To: Marijn Suijten
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Konrad Dybcio, Abhinav Kumar, dri-devel,
linux-kernel, Rob Herring, Krishna Manikandan, linux-arm-msm,
Dmitry Baryshkov, linux-arm-kernel, Robin Murphy
On 4/27/23 16:48, Marijn Suijten wrote:
> On 2023-04-27 17:37:42, Marijn Suijten wrote:
>> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
>>> Add SM6350 support to the DPU1 driver to enable display output.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> After addressing the comments from Dmitry (CURSOR0->DMA1 and
>> CURSOR1->DMA2), this is:
>>
>> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>>
>> See below for some nits.
> Actually found one glaring issue that might explain why INTF TE wasn't
> working for you the other day!
[...]
>>> + .vbif = sm6350_vbif,
>>> + .reg_dma_count = 1,
>>> + .dma_cfg = &sm8250_regdma,
>>> + .perf = &sm6350_perf_data,
>>> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
>>> + BIT(MDP_SSPP_TOP0_INTR2) | \
>>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
>>> + BIT(MDP_INTF0_INTR) | \
>>> + BIT(MDP_INTF1_INTR)
> For completeness I should've pointed out that you're missing
> MDP_INTF1_TEAR_INTR here, likely resulting in INTF TE not working.
>
> - Marijn
<annoyed noises>
so it might have been this.. I'll retest, thanks!
Konrad
>
> <snip>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-28 12:25 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-28 12:25 UTC (permalink / raw)
To: Marijn Suijten
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu, Konrad Dybcio
On 4/27/23 16:48, Marijn Suijten wrote:
> On 2023-04-27 17:37:42, Marijn Suijten wrote:
>> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
>>> Add SM6350 support to the DPU1 driver to enable display output.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> After addressing the comments from Dmitry (CURSOR0->DMA1 and
>> CURSOR1->DMA2), this is:
>>
>> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>>
>> See below for some nits.
> Actually found one glaring issue that might explain why INTF TE wasn't
> working for you the other day!
[...]
>>> + .vbif = sm6350_vbif,
>>> + .reg_dma_count = 1,
>>> + .dma_cfg = &sm8250_regdma,
>>> + .perf = &sm6350_perf_data,
>>> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
>>> + BIT(MDP_SSPP_TOP0_INTR2) | \
>>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
>>> + BIT(MDP_INTF0_INTR) | \
>>> + BIT(MDP_INTF1_INTR)
> For completeness I should've pointed out that you're missing
> MDP_INTF1_TEAR_INTR here, likely resulting in INTF TE not working.
>
> - Marijn
<annoyed noises>
so it might have been this.. I'll retest, thanks!
Konrad
>
> <snip>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
2023-04-27 15:46 ` Marijn Suijten
(?)
@ 2023-04-28 12:32 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-28 12:32 UTC (permalink / raw)
To: Marijn Suijten
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu
On 4/27/23 16:46, Marijn Suijten wrote:
> On 2023-04-21 00:31:18, Konrad Dybcio wrote:
>> Add basic SM6375 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> 5 files changed, 168 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> index 687a508cbaa6..d46b43964be6 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
>> },
>> };
>>
>> -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> - {.fl = 0, .lut = 0x0011223344556677 },
>> - {.fl = 0, .lut = 0x0011223445566777 },
>> -};
>> -
>> static const struct dpu_perf_cfg sm6350_perf_data = {
>> .max_bw_low = 4200000,
>> .max_bw_high = 5100000,
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
>> new file mode 100644
>> index 000000000000..19ca0051e072
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
>> @@ -0,0 +1,152 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023, Linaro Limited
>> + */
>> +
>> +#ifndef _DPU_6_9_SM6375_H
>> +#define _DPU_6_9_SM6375_H
>> +
>> +static const struct dpu_caps sm6375_dpu_caps = {
>> + .max_mixer_width = 2048,
>> + .max_mixer_blendstages = 0x4,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
>> + .has_dim_layer = true,
>> + .has_idle_pc = true,
>> + .max_linewidth = 2160,
>> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +};
>> +
>> +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
>> + .ubwc_version = DPU_HW_UBWC_VER_20,
>> + .ubwc_swizzle = 6,
>> + .highest_bank_bit = 1,
>> +};
>> +
>> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
>> + {
>> + .name = "top_0", .id = MDP_TOP,
>> + .base = 0x0, .len = 0x494,
>> + .features = 0,
>> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
>> + },
>> +};
>> +
>> +static const struct dpu_ctl_cfg sm6375_ctl[] = {
>> + {
>> + .name = "ctl_0", .id = CTL_0,
>> + .base = 0x1000, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> + },
>> +};
>> +
>> +static const struct dpu_sspp_cfg sm6375_sspp[] = {
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>> + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> +};
>> +
>> +static const struct dpu_lm_cfg sm6375_lm[] = {
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
>> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
> Same indentation nit here as in SM6350.
Ack
>
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm6375_dspp[] = {
>> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> + &sm8150_dspp_sblk),
>> +};
>> +
>> +static const struct dpu_pingpong_cfg sm6375_pp[] = {
>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> + -1),
>> +};
>> +
>> +static const struct dpu_intf_cfg sm6375_intf[] = {
>> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
>> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
>> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>> +};
>> +
>> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
>> + {
>> + .name = "vbif_0", .id = VBIF_RT,
>> + .base = 0, .len = 0x2008,
>> + .features = BIT(DPU_VBIF_QOS_REMAP),
>> + .xin_halt_timeout = 0x4000,
>> + .qos_rp_remap_size = 0x40,
>> + .qos_rt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
>> + .priority_lvl = sdm845_rt_pri_lvl,
>> + },
>> + .qos_nrt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
>> + .priority_lvl = sdm845_nrt_pri_lvl,
>> + },
>> + .memtype_count = 14,
>> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
>> + },
>> +};
>> +
>> +static const struct dpu_perf_cfg sm6375_perf_data = {
>> + .max_bw_low = 5200000,
>> + .max_bw_high = 6200000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0, /* No LLCC on this SoC */
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 24,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
>> + .qos_lut_tbl = {
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> + .entries = sc7180_qos_nrt
>> + },
>> + },
>> + .cdp_cfg = {
>> + {.rd_enable = 1, .wr_enable = 1},
>> + {.rd_enable = 1, .wr_enable = 0}
>> + },
>> + .clk_inefficiency_factor = 105,
>> + .bw_inefficiency_factor = 120,
>> +};
>> +
>> +const struct dpu_mdss_cfg dpu_sm6375_cfg = {
>> + .caps = &sm6375_dpu_caps,
>> + .ubwc = &sm6375_ubwc_cfg,
>> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
>> + .mdp = sm6375_mdp,
>> + .ctl_count = ARRAY_SIZE(sm6375_ctl),
>> + .ctl = sm6375_ctl,
>> + .sspp_count = ARRAY_SIZE(sm6375_sspp),
>> + .sspp = sm6375_sspp,
>> + .mixer_count = ARRAY_SIZE(sm6375_lm),
>> + .mixer = sm6375_lm,
>> + .dspp_count = ARRAY_SIZE(sm6375_dspp),
>> + .dspp = sm6375_dspp,
>> + .pingpong_count = ARRAY_SIZE(sm6375_pp),
>> + .pingpong = sm6375_pp,
>> + .intf_count = ARRAY_SIZE(sm6375_intf),
>> + .intf = sm6375_intf,
>> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
>> + .vbif = sm6375_vbif,
>> + .perf = &sm6375_perf_data,
>> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
>> + BIT(MDP_SSPP_TOP0_INTR2) | \
>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
>> + BIT(MDP_INTF0_INTR) | \
> INTF0 is set to INTF_NONE, no point in turning on the interrupt for it.
>
> https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-1-27ce1a5ab5c6@somainline.org/
>
>> + BIT(MDP_INTF1_INTR)
> And you might want to turn on MDP_INTF1_TEAR_INTR (same on SM6350), that
> could explain why INTF TE wasn't working on these SoCs yet.
>
> - Marijn
*sigh*
thanks!
Konrad
>
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 52750b592b36..29516273dd6b 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
>> },
>> };
>>
>> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
>> + .maxwidth = 2048,
>> + .maxblendstages = 4, /* excluding base layer */
>> + .blendstage_base = { /* offsets relative to mixer base */
>> + 0x20, 0x38, 0x50, 0x68
>> + },
>> +};
>> +
>> /* QCM2290 */
>>
>> static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
>> @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
>> {.fl = 0, .lut = 0x0011222222335777},
>> };
>>
>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>> +};
>> +
>> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
>> {.fl = 0, .lut = 0x0011222222223357 },
>> };
>> @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>> #include "catalog/dpu_6_3_sm6115.h"
>> #include "catalog/dpu_6_4_sm6350.h"
>> #include "catalog/dpu_6_5_qcm2290.h"
>> +#include "catalog/dpu_6_9_sm6375.h"
>>
>> #include "catalog/dpu_7_0_sm8350.h"
>> #include "catalog/dpu_7_2_sc7280.h"
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index f9611bd75e02..b4f193037869 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 46be7ad8d615..980c3c8f8269 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>> + { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>
>> --
>> 2.40.0
>>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
@ 2023-04-28 12:32 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-28 12:32 UTC (permalink / raw)
To: Marijn Suijten
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Abhinav Kumar, dri-devel, linux-kernel,
Rob Herring, Krishna Manikandan, linux-arm-msm, Dmitry Baryshkov,
linux-arm-kernel, Robin Murphy
On 4/27/23 16:46, Marijn Suijten wrote:
> On 2023-04-21 00:31:18, Konrad Dybcio wrote:
>> Add basic SM6375 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> 5 files changed, 168 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> index 687a508cbaa6..d46b43964be6 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
>> },
>> };
>>
>> -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> - {.fl = 0, .lut = 0x0011223344556677 },
>> - {.fl = 0, .lut = 0x0011223445566777 },
>> -};
>> -
>> static const struct dpu_perf_cfg sm6350_perf_data = {
>> .max_bw_low = 4200000,
>> .max_bw_high = 5100000,
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
>> new file mode 100644
>> index 000000000000..19ca0051e072
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
>> @@ -0,0 +1,152 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023, Linaro Limited
>> + */
>> +
>> +#ifndef _DPU_6_9_SM6375_H
>> +#define _DPU_6_9_SM6375_H
>> +
>> +static const struct dpu_caps sm6375_dpu_caps = {
>> + .max_mixer_width = 2048,
>> + .max_mixer_blendstages = 0x4,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
>> + .has_dim_layer = true,
>> + .has_idle_pc = true,
>> + .max_linewidth = 2160,
>> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +};
>> +
>> +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
>> + .ubwc_version = DPU_HW_UBWC_VER_20,
>> + .ubwc_swizzle = 6,
>> + .highest_bank_bit = 1,
>> +};
>> +
>> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
>> + {
>> + .name = "top_0", .id = MDP_TOP,
>> + .base = 0x0, .len = 0x494,
>> + .features = 0,
>> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
>> + },
>> +};
>> +
>> +static const struct dpu_ctl_cfg sm6375_ctl[] = {
>> + {
>> + .name = "ctl_0", .id = CTL_0,
>> + .base = 0x1000, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> + },
>> +};
>> +
>> +static const struct dpu_sspp_cfg sm6375_sspp[] = {
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>> + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> +};
>> +
>> +static const struct dpu_lm_cfg sm6375_lm[] = {
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
>> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
> Same indentation nit here as in SM6350.
Ack
>
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm6375_dspp[] = {
>> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> + &sm8150_dspp_sblk),
>> +};
>> +
>> +static const struct dpu_pingpong_cfg sm6375_pp[] = {
>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> + -1),
>> +};
>> +
>> +static const struct dpu_intf_cfg sm6375_intf[] = {
>> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
>> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
>> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>> +};
>> +
>> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
>> + {
>> + .name = "vbif_0", .id = VBIF_RT,
>> + .base = 0, .len = 0x2008,
>> + .features = BIT(DPU_VBIF_QOS_REMAP),
>> + .xin_halt_timeout = 0x4000,
>> + .qos_rp_remap_size = 0x40,
>> + .qos_rt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
>> + .priority_lvl = sdm845_rt_pri_lvl,
>> + },
>> + .qos_nrt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
>> + .priority_lvl = sdm845_nrt_pri_lvl,
>> + },
>> + .memtype_count = 14,
>> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
>> + },
>> +};
>> +
>> +static const struct dpu_perf_cfg sm6375_perf_data = {
>> + .max_bw_low = 5200000,
>> + .max_bw_high = 6200000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0, /* No LLCC on this SoC */
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 24,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
>> + .qos_lut_tbl = {
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> + .entries = sc7180_qos_nrt
>> + },
>> + },
>> + .cdp_cfg = {
>> + {.rd_enable = 1, .wr_enable = 1},
>> + {.rd_enable = 1, .wr_enable = 0}
>> + },
>> + .clk_inefficiency_factor = 105,
>> + .bw_inefficiency_factor = 120,
>> +};
>> +
>> +const struct dpu_mdss_cfg dpu_sm6375_cfg = {
>> + .caps = &sm6375_dpu_caps,
>> + .ubwc = &sm6375_ubwc_cfg,
>> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
>> + .mdp = sm6375_mdp,
>> + .ctl_count = ARRAY_SIZE(sm6375_ctl),
>> + .ctl = sm6375_ctl,
>> + .sspp_count = ARRAY_SIZE(sm6375_sspp),
>> + .sspp = sm6375_sspp,
>> + .mixer_count = ARRAY_SIZE(sm6375_lm),
>> + .mixer = sm6375_lm,
>> + .dspp_count = ARRAY_SIZE(sm6375_dspp),
>> + .dspp = sm6375_dspp,
>> + .pingpong_count = ARRAY_SIZE(sm6375_pp),
>> + .pingpong = sm6375_pp,
>> + .intf_count = ARRAY_SIZE(sm6375_intf),
>> + .intf = sm6375_intf,
>> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
>> + .vbif = sm6375_vbif,
>> + .perf = &sm6375_perf_data,
>> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
>> + BIT(MDP_SSPP_TOP0_INTR2) | \
>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
>> + BIT(MDP_INTF0_INTR) | \
> INTF0 is set to INTF_NONE, no point in turning on the interrupt for it.
>
> https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-1-27ce1a5ab5c6@somainline.org/
>
>> + BIT(MDP_INTF1_INTR)
> And you might want to turn on MDP_INTF1_TEAR_INTR (same on SM6350), that
> could explain why INTF TE wasn't working on these SoCs yet.
>
> - Marijn
*sigh*
thanks!
Konrad
>
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 52750b592b36..29516273dd6b 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
>> },
>> };
>>
>> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
>> + .maxwidth = 2048,
>> + .maxblendstages = 4, /* excluding base layer */
>> + .blendstage_base = { /* offsets relative to mixer base */
>> + 0x20, 0x38, 0x50, 0x68
>> + },
>> +};
>> +
>> /* QCM2290 */
>>
>> static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
>> @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
>> {.fl = 0, .lut = 0x0011222222335777},
>> };
>>
>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>> +};
>> +
>> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
>> {.fl = 0, .lut = 0x0011222222223357 },
>> };
>> @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>> #include "catalog/dpu_6_3_sm6115.h"
>> #include "catalog/dpu_6_4_sm6350.h"
>> #include "catalog/dpu_6_5_qcm2290.h"
>> +#include "catalog/dpu_6_9_sm6375.h"
>>
>> #include "catalog/dpu_7_0_sm8350.h"
>> #include "catalog/dpu_7_2_sc7280.h"
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index f9611bd75e02..b4f193037869 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 46be7ad8d615..980c3c8f8269 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>> + { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>
>> --
>> 2.40.0
>>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support
@ 2023-04-28 12:32 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-04-28 12:32 UTC (permalink / raw)
To: Marijn Suijten
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu
On 4/27/23 16:46, Marijn Suijten wrote:
> On 2023-04-21 00:31:18, Konrad Dybcio wrote:
>> Add basic SM6375 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> 5 files changed, 168 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> index 687a508cbaa6..d46b43964be6 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = {
>> },
>> };
>>
>> -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> - {.fl = 0, .lut = 0x0011223344556677 },
>> - {.fl = 0, .lut = 0x0011223445566777 },
>> -};
>> -
>> static const struct dpu_perf_cfg sm6350_perf_data = {
>> .max_bw_low = 4200000,
>> .max_bw_high = 5100000,
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
>> new file mode 100644
>> index 000000000000..19ca0051e072
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
>> @@ -0,0 +1,152 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023, Linaro Limited
>> + */
>> +
>> +#ifndef _DPU_6_9_SM6375_H
>> +#define _DPU_6_9_SM6375_H
>> +
>> +static const struct dpu_caps sm6375_dpu_caps = {
>> + .max_mixer_width = 2048,
>> + .max_mixer_blendstages = 0x4,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
>> + .has_dim_layer = true,
>> + .has_idle_pc = true,
>> + .max_linewidth = 2160,
>> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +};
>> +
>> +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
>> + .ubwc_version = DPU_HW_UBWC_VER_20,
>> + .ubwc_swizzle = 6,
>> + .highest_bank_bit = 1,
>> +};
>> +
>> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
>> + {
>> + .name = "top_0", .id = MDP_TOP,
>> + .base = 0x0, .len = 0x494,
>> + .features = 0,
>> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
>> + },
>> +};
>> +
>> +static const struct dpu_ctl_cfg sm6375_ctl[] = {
>> + {
>> + .name = "ctl_0", .id = CTL_0,
>> + .base = 0x1000, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> + },
>> +};
>> +
>> +static const struct dpu_sspp_cfg sm6375_sspp[] = {
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>> + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> +};
>> +
>> +static const struct dpu_lm_cfg sm6375_lm[] = {
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
>> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
> Same indentation nit here as in SM6350.
Ack
>
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm6375_dspp[] = {
>> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> + &sm8150_dspp_sblk),
>> +};
>> +
>> +static const struct dpu_pingpong_cfg sm6375_pp[] = {
>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> + -1),
>> +};
>> +
>> +static const struct dpu_intf_cfg sm6375_intf[] = {
>> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
>> + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
>> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>> +};
>> +
>> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
>> + {
>> + .name = "vbif_0", .id = VBIF_RT,
>> + .base = 0, .len = 0x2008,
>> + .features = BIT(DPU_VBIF_QOS_REMAP),
>> + .xin_halt_timeout = 0x4000,
>> + .qos_rp_remap_size = 0x40,
>> + .qos_rt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
>> + .priority_lvl = sdm845_rt_pri_lvl,
>> + },
>> + .qos_nrt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
>> + .priority_lvl = sdm845_nrt_pri_lvl,
>> + },
>> + .memtype_count = 14,
>> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
>> + },
>> +};
>> +
>> +static const struct dpu_perf_cfg sm6375_perf_data = {
>> + .max_bw_low = 5200000,
>> + .max_bw_high = 6200000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0, /* No LLCC on this SoC */
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 24,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
>> + .qos_lut_tbl = {
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
>> + .entries = sm6350_qos_linear_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> + .entries = sc7180_qos_nrt
>> + },
>> + },
>> + .cdp_cfg = {
>> + {.rd_enable = 1, .wr_enable = 1},
>> + {.rd_enable = 1, .wr_enable = 0}
>> + },
>> + .clk_inefficiency_factor = 105,
>> + .bw_inefficiency_factor = 120,
>> +};
>> +
>> +const struct dpu_mdss_cfg dpu_sm6375_cfg = {
>> + .caps = &sm6375_dpu_caps,
>> + .ubwc = &sm6375_ubwc_cfg,
>> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
>> + .mdp = sm6375_mdp,
>> + .ctl_count = ARRAY_SIZE(sm6375_ctl),
>> + .ctl = sm6375_ctl,
>> + .sspp_count = ARRAY_SIZE(sm6375_sspp),
>> + .sspp = sm6375_sspp,
>> + .mixer_count = ARRAY_SIZE(sm6375_lm),
>> + .mixer = sm6375_lm,
>> + .dspp_count = ARRAY_SIZE(sm6375_dspp),
>> + .dspp = sm6375_dspp,
>> + .pingpong_count = ARRAY_SIZE(sm6375_pp),
>> + .pingpong = sm6375_pp,
>> + .intf_count = ARRAY_SIZE(sm6375_intf),
>> + .intf = sm6375_intf,
>> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
>> + .vbif = sm6375_vbif,
>> + .perf = &sm6375_perf_data,
>> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
>> + BIT(MDP_SSPP_TOP0_INTR2) | \
>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
>> + BIT(MDP_INTF0_INTR) | \
> INTF0 is set to INTF_NONE, no point in turning on the interrupt for it.
>
> https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-1-27ce1a5ab5c6@somainline.org/
>
>> + BIT(MDP_INTF1_INTR)
> And you might want to turn on MDP_INTF1_TEAR_INTR (same on SM6350), that
> could explain why INTF TE wasn't working on these SoCs yet.
>
> - Marijn
*sigh*
thanks!
Konrad
>
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 52750b592b36..29516273dd6b 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
>> },
>> };
>>
>> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
>> + .maxwidth = 2048,
>> + .maxblendstages = 4, /* excluding base layer */
>> + .blendstage_base = { /* offsets relative to mixer base */
>> + 0x20, 0x38, 0x50, 0x68
>> + },
>> +};
>> +
>> /* QCM2290 */
>>
>> static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
>> @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
>> {.fl = 0, .lut = 0x0011222222335777},
>> };
>>
>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>> +};
>> +
>> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
>> {.fl = 0, .lut = 0x0011222222223357 },
>> };
>> @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>> #include "catalog/dpu_6_3_sm6115.h"
>> #include "catalog/dpu_6_4_sm6350.h"
>> #include "catalog/dpu_6_5_qcm2290.h"
>> +#include "catalog/dpu_6_9_sm6375.h"
>>
>> #include "catalog/dpu_7_0_sm8350.h"
>> #include "catalog/dpu_7_2_sc7280.h"
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index f9611bd75e02..b4f193037869 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>> extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 46be7ad8d615..980c3c8f8269 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>> { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>> + { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>
>> --
>> 2.40.0
>>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-27 15:37 ` Marijn Suijten
(?)
@ 2023-04-28 13:03 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-28 13:03 UTC (permalink / raw)
To: Marijn Suijten, Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Krishna Manikandan,
Will Deacon, Robin Murphy, Joerg Roedel, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel,
iommu, Konrad Dybcio
On 27/04/2023 18:37, Marijn Suijten wrote:
> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> After addressing the comments from Dmitry (CURSOR0->DMA1 and
> CURSOR1->DMA2), this is:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> See below for some nits.
>
>> ---
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> 4 files changed, 196 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> new file mode 100644
>> index 000000000000..687a508cbaa6
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> @@ -0,0 +1,191 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023, Linaro Limited
>> + */
>> +
>> +#ifndef _DPU_6_4_SM6350_H
>> +#define _DPU_6_4_SM6350_H
>> +
>> +static const struct dpu_caps sm6350_dpu_caps = {
>> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .max_mixer_blendstages = 0x7,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
>
> I thought it was QSEED3LITE, but doesn't really matter as both are
> handled similarly. It'll anyway change when I resubmit:
If I understood correctly, we mixed two things: hw stuff and the
userspace library. QSEEDv2 was a hardware scaler. "qseedv3/v3lite/v4"
are software library names that are used with the scalers newer than
QSEED2. From the driver point we can ignore that and use scaler's hw
version (which mostly but not always corresponds to the 3/3lite/4).
>
> https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
>
> which should hardcode the register value directly, making this field
> superfluous.
>
>> + .has_src_split = true,
>> + .has_dim_layer = true,
>> + .has_idle_pc = true,
>> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +};
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-28 13:03 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-28 13:03 UTC (permalink / raw)
To: Marijn Suijten, Konrad Dybcio
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Konrad Dybcio, Abhinav Kumar, dri-devel,
linux-kernel, Rob Herring, Krishna Manikandan, linux-arm-msm,
linux-arm-kernel, Robin Murphy
On 27/04/2023 18:37, Marijn Suijten wrote:
> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> After addressing the comments from Dmitry (CURSOR0->DMA1 and
> CURSOR1->DMA2), this is:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> See below for some nits.
>
>> ---
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> 4 files changed, 196 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> new file mode 100644
>> index 000000000000..687a508cbaa6
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> @@ -0,0 +1,191 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023, Linaro Limited
>> + */
>> +
>> +#ifndef _DPU_6_4_SM6350_H
>> +#define _DPU_6_4_SM6350_H
>> +
>> +static const struct dpu_caps sm6350_dpu_caps = {
>> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .max_mixer_blendstages = 0x7,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
>
> I thought it was QSEED3LITE, but doesn't really matter as both are
> handled similarly. It'll anyway change when I resubmit:
If I understood correctly, we mixed two things: hw stuff and the
userspace library. QSEEDv2 was a hardware scaler. "qseedv3/v3lite/v4"
are software library names that are used with the scalers newer than
QSEED2. From the driver point we can ignore that and use scaler's hw
version (which mostly but not always corresponds to the 3/3lite/4).
>
> https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
>
> which should hardcode the register value directly, making this field
> superfluous.
>
>> + .has_src_split = true,
>> + .has_dim_layer = true,
>> + .has_idle_pc = true,
>> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +};
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-04-28 13:03 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-04-28 13:03 UTC (permalink / raw)
To: Marijn Suijten, Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Krishna Manikandan,
Will Deacon, Robin Murphy, Joerg Roedel, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel,
iommu, Konrad Dybcio
On 27/04/2023 18:37, Marijn Suijten wrote:
> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> After addressing the comments from Dmitry (CURSOR0->DMA1 and
> CURSOR1->DMA2), this is:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> See below for some nits.
>
>> ---
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> 4 files changed, 196 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> new file mode 100644
>> index 000000000000..687a508cbaa6
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> @@ -0,0 +1,191 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023, Linaro Limited
>> + */
>> +
>> +#ifndef _DPU_6_4_SM6350_H
>> +#define _DPU_6_4_SM6350_H
>> +
>> +static const struct dpu_caps sm6350_dpu_caps = {
>> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .max_mixer_blendstages = 0x7,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
>
> I thought it was QSEED3LITE, but doesn't really matter as both are
> handled similarly. It'll anyway change when I resubmit:
If I understood correctly, we mixed two things: hw stuff and the
userspace library. QSEEDv2 was a hardware scaler. "qseedv3/v3lite/v4"
are software library names that are used with the scalers newer than
QSEED2. From the driver point we can ignore that and use scaler's hw
version (which mostly but not always corresponds to the 3/3lite/4).
>
> https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
>
> which should hardcode the register value directly, making this field
> superfluous.
>
>> + .has_src_split = true,
>> + .has_dim_layer = true,
>> + .has_idle_pc = true,
>> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +};
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-27 15:37 ` Marijn Suijten
(?)
@ 2023-05-05 12:11 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-05-05 12:11 UTC (permalink / raw)
To: Marijn Suijten, Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Krishna Manikandan,
Will Deacon, Robin Murphy, Joerg Roedel, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel,
iommu, Konrad Dybcio
On 27/04/2023 18:37, Marijn Suijten wrote:
> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> After addressing the comments from Dmitry (CURSOR0->DMA1 and
> CURSOR1->DMA2), this is:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> See below for some nits.
[...]
>> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
>> + {
>> + .name = "top_0", .id = MDP_TOP,
>> + .base = 0x0, .len = 0x494,
>> + .features = 0,
>> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
>> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
>> + },
>> +};
>> +
>> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
>> + {
>> + .name = "ctl_0", .id = CTL_0,
>> + .base = 0x1000, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> + },
>> + {
>> + .name = "ctl_1", .id = CTL_1,
>> + .base = 0x1200, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> + },
>> + {
>> + .name = "ctl_2", .id = CTL_2,
>> + .base = 0x1400, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> + },
>> + {
>> + .name = "ctl_3", .id = CTL_3,
>> + .base = 0x1600, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> + },
>> +};
>> +
>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> +};
>> +
>> +static const struct dpu_lm_cfg sm6350_lm[] = {
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
>> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
>
> These two entries are indented with two tabs and have one character too
> many to align with the opening parenthesis on the previous line. Can we
> please settle on a single style, as this commit mostly uses tabs+spaces
> to align with the opening parenthesis?
>
> Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> line with zero extra characters to the opening parenthesis), but I find
> double tabs more convenient as it doesn't require reindenting when
> changing the name of the macro (which happened too often in my INTF TE
> series).
I mainly vote for 'cino=(0' for indenting conditions (where double tab
is confusing) and for function calls. I do not have a strong opinion
about macros expansions. We have been using double-tab there, which is
fine with me.
Another option (which I personally find more appealing, but it doesn't
play well with the current guidelines) is to have all macro arguments in
a single line. It makes it easier to compare things.
And another option would be to expand these macros up to some point.
Previous experience with clock and interconnect drivers showed that
expanding such multi-arg acros makes it _easier_ to handle the data.
Counterintuitive, but true.
>
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
>> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> + &sm8150_dspp_sblk),
>> +};
>> +
>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> + -1),
>> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> + -1),
[skipped the rest]
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-05-05 12:11 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-05-05 12:11 UTC (permalink / raw)
To: Marijn Suijten, Konrad Dybcio
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Konrad Dybcio, Abhinav Kumar, dri-devel,
linux-kernel, Rob Herring, Krishna Manikandan, linux-arm-msm,
linux-arm-kernel, Robin Murphy
On 27/04/2023 18:37, Marijn Suijten wrote:
> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> After addressing the comments from Dmitry (CURSOR0->DMA1 and
> CURSOR1->DMA2), this is:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> See below for some nits.
[...]
>> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
>> + {
>> + .name = "top_0", .id = MDP_TOP,
>> + .base = 0x0, .len = 0x494,
>> + .features = 0,
>> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
>> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
>> + },
>> +};
>> +
>> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
>> + {
>> + .name = "ctl_0", .id = CTL_0,
>> + .base = 0x1000, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> + },
>> + {
>> + .name = "ctl_1", .id = CTL_1,
>> + .base = 0x1200, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> + },
>> + {
>> + .name = "ctl_2", .id = CTL_2,
>> + .base = 0x1400, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> + },
>> + {
>> + .name = "ctl_3", .id = CTL_3,
>> + .base = 0x1600, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> + },
>> +};
>> +
>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> +};
>> +
>> +static const struct dpu_lm_cfg sm6350_lm[] = {
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
>> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
>
> These two entries are indented with two tabs and have one character too
> many to align with the opening parenthesis on the previous line. Can we
> please settle on a single style, as this commit mostly uses tabs+spaces
> to align with the opening parenthesis?
>
> Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> line with zero extra characters to the opening parenthesis), but I find
> double tabs more convenient as it doesn't require reindenting when
> changing the name of the macro (which happened too often in my INTF TE
> series).
I mainly vote for 'cino=(0' for indenting conditions (where double tab
is confusing) and for function calls. I do not have a strong opinion
about macros expansions. We have been using double-tab there, which is
fine with me.
Another option (which I personally find more appealing, but it doesn't
play well with the current guidelines) is to have all macro arguments in
a single line. It makes it easier to compare things.
And another option would be to expand these macros up to some point.
Previous experience with clock and interconnect drivers showed that
expanding such multi-arg acros makes it _easier_ to handle the data.
Counterintuitive, but true.
>
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
>> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> + &sm8150_dspp_sblk),
>> +};
>> +
>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> + -1),
>> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> + -1),
[skipped the rest]
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-05-05 12:11 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-05-05 12:11 UTC (permalink / raw)
To: Marijn Suijten, Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Krishna Manikandan,
Will Deacon, Robin Murphy, Joerg Roedel, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, linux-arm-kernel,
iommu, Konrad Dybcio
On 27/04/2023 18:37, Marijn Suijten wrote:
> On 2023-04-21 00:31:16, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> After addressing the comments from Dmitry (CURSOR0->DMA1 and
> CURSOR1->DMA2), this is:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> See below for some nits.
[...]
>> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
>> + {
>> + .name = "top_0", .id = MDP_TOP,
>> + .base = 0x0, .len = 0x494,
>> + .features = 0,
>> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
>> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
>> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
>> + },
>> +};
>> +
>> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
>> + {
>> + .name = "ctl_0", .id = CTL_0,
>> + .base = 0x1000, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> + },
>> + {
>> + .name = "ctl_1", .id = CTL_1,
>> + .base = 0x1200, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> + },
>> + {
>> + .name = "ctl_2", .id = CTL_2,
>> + .base = 0x1400, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> + },
>> + {
>> + .name = "ctl_3", .id = CTL_3,
>> + .base = 0x1600, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> + },
>> +};
>> +
>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> +};
>> +
>> +static const struct dpu_lm_cfg sm6350_lm[] = {
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
>> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
>
> These two entries are indented with two tabs and have one character too
> many to align with the opening parenthesis on the previous line. Can we
> please settle on a single style, as this commit mostly uses tabs+spaces
> to align with the opening parenthesis?
>
> Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> line with zero extra characters to the opening parenthesis), but I find
> double tabs more convenient as it doesn't require reindenting when
> changing the name of the macro (which happened too often in my INTF TE
> series).
I mainly vote for 'cino=(0' for indenting conditions (where double tab
is confusing) and for function calls. I do not have a strong opinion
about macros expansions. We have been using double-tab there, which is
fine with me.
Another option (which I personally find more appealing, but it doesn't
play well with the current guidelines) is to have all macro arguments in
a single line. It makes it easier to compare things.
And another option would be to expand these macros up to some point.
Previous experience with clock and interconnect drivers showed that
expanding such multi-arg acros makes it _easier_ to handle the data.
Counterintuitive, but true.
>
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
>> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> + &sm8150_dspp_sblk),
>> +};
>> +
>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> + -1),
>> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> + -1),
[skipped the rest]
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
2023-04-25 17:03 ` Rob Herring
(?)
@ 2023-05-05 12:38 ` Konrad Dybcio
-1 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-05-05 12:38 UTC (permalink / raw)
To: Rob Herring
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 25.04.2023 19:03, Rob Herring wrote:
> On Fri, Apr 21, 2023 at 12:31:12AM +0200, Konrad Dybcio wrote:
>> Document the SM6350 DPU.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
>> 1 file changed, 94 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
>> new file mode 100644
>> index 000000000000..979fcf81afc9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
>> @@ -0,0 +1,94 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Display DPU dt properties for SM6350 target
>> +
>> +maintainers:
>> + - Konrad Dybcio <konrad.dybcio@linaro.org>
>> +
>> +$ref: /schemas/display/msm/dpu-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - const: qcom,sm6350-dpu
>> +
>> + reg:
>> + items:
>> + - description: Address offset and size for mdp register set
>> + - description: Address offset and size for vbif register set
>> +
>> + reg-names:
>> + items:
>> + - const: mdp
>> + - const: vbif
>> +
>> + clocks:
>> + items:
>> + - description: Display axi clock
>> + - description: Display ahb clock
>> + - description: Display rot clock
>> + - description: Display lut clock
>> + - description: Display core clock
>> + - description: Display vsync clock
>> +
>> + clock-names:
>> + items:
>> + - const: bus
>> + - const: iface
>> + - const: rot
>> + - const: lut
>> + - const: core
>> + - const: vsync
>
> Is there some reason the clocks are in different order?
Nope, I'll sort this out
They appear to
> be the same minus the 'throttle' clock. Is there really no 'throttle'
> clock?
Looks like GCC_DISP_THROTTLE_AXI_CLK does exist on sm6350 as well, no
idea how/if it's used though.. Perhaps I can just remove it from sm6375
and if it turns out necessary we can reintroduce it another day.
Maybe this platform just tied it to one of the same clocks in the
> above?
Unlikely, most likely it's for some dire deep power saving stuff that
does not seem to be used/exposed, even on the bsp kernel
>
> I really hate the mess that is clocks. We have the same or related
> blocks with just totally different names and order. The result is
> if/then schemas or separate schemas like this. Neither option is great,
> but at least the if/then schemas provides some motivation to not have
> pointless variations like this. </rant>
It's a totally valid rant..
>
> As it seems the only difference between these 2 bindings is 1 extra
> clock, can't they be shared?
Sounds like a plan!
Konrad
>
> Rob
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
@ 2023-05-05 12:38 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-05-05 12:38 UTC (permalink / raw)
To: Rob Herring
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Abhinav Kumar, dri-devel, linux-kernel,
Krishna Manikandan, linux-arm-msm, Dmitry Baryshkov,
Marijn Suijten, linux-arm-kernel, Robin Murphy
On 25.04.2023 19:03, Rob Herring wrote:
> On Fri, Apr 21, 2023 at 12:31:12AM +0200, Konrad Dybcio wrote:
>> Document the SM6350 DPU.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
>> 1 file changed, 94 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
>> new file mode 100644
>> index 000000000000..979fcf81afc9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
>> @@ -0,0 +1,94 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Display DPU dt properties for SM6350 target
>> +
>> +maintainers:
>> + - Konrad Dybcio <konrad.dybcio@linaro.org>
>> +
>> +$ref: /schemas/display/msm/dpu-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - const: qcom,sm6350-dpu
>> +
>> + reg:
>> + items:
>> + - description: Address offset and size for mdp register set
>> + - description: Address offset and size for vbif register set
>> +
>> + reg-names:
>> + items:
>> + - const: mdp
>> + - const: vbif
>> +
>> + clocks:
>> + items:
>> + - description: Display axi clock
>> + - description: Display ahb clock
>> + - description: Display rot clock
>> + - description: Display lut clock
>> + - description: Display core clock
>> + - description: Display vsync clock
>> +
>> + clock-names:
>> + items:
>> + - const: bus
>> + - const: iface
>> + - const: rot
>> + - const: lut
>> + - const: core
>> + - const: vsync
>
> Is there some reason the clocks are in different order?
Nope, I'll sort this out
They appear to
> be the same minus the 'throttle' clock. Is there really no 'throttle'
> clock?
Looks like GCC_DISP_THROTTLE_AXI_CLK does exist on sm6350 as well, no
idea how/if it's used though.. Perhaps I can just remove it from sm6375
and if it turns out necessary we can reintroduce it another day.
Maybe this platform just tied it to one of the same clocks in the
> above?
Unlikely, most likely it's for some dire deep power saving stuff that
does not seem to be used/exposed, even on the bsp kernel
>
> I really hate the mess that is clocks. We have the same or related
> blocks with just totally different names and order. The result is
> if/then schemas or separate schemas like this. Neither option is great,
> but at least the if/then schemas provides some motivation to not have
> pointless variations like this. </rant>
It's a totally valid rant..
>
> As it seems the only difference between these 2 bindings is 1 extra
> clock, can't they be shared?
Sounds like a plan!
Konrad
>
> Rob
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU
@ 2023-05-05 12:38 ` Konrad Dybcio
0 siblings, 0 replies; 127+ messages in thread
From: Konrad Dybcio @ 2023-05-05 12:38 UTC (permalink / raw)
To: Rob Herring
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 25.04.2023 19:03, Rob Herring wrote:
> On Fri, Apr 21, 2023 at 12:31:12AM +0200, Konrad Dybcio wrote:
>> Document the SM6350 DPU.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++
>> 1 file changed, 94 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
>> new file mode 100644
>> index 000000000000..979fcf81afc9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
>> @@ -0,0 +1,94 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Display DPU dt properties for SM6350 target
>> +
>> +maintainers:
>> + - Konrad Dybcio <konrad.dybcio@linaro.org>
>> +
>> +$ref: /schemas/display/msm/dpu-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - const: qcom,sm6350-dpu
>> +
>> + reg:
>> + items:
>> + - description: Address offset and size for mdp register set
>> + - description: Address offset and size for vbif register set
>> +
>> + reg-names:
>> + items:
>> + - const: mdp
>> + - const: vbif
>> +
>> + clocks:
>> + items:
>> + - description: Display axi clock
>> + - description: Display ahb clock
>> + - description: Display rot clock
>> + - description: Display lut clock
>> + - description: Display core clock
>> + - description: Display vsync clock
>> +
>> + clock-names:
>> + items:
>> + - const: bus
>> + - const: iface
>> + - const: rot
>> + - const: lut
>> + - const: core
>> + - const: vsync
>
> Is there some reason the clocks are in different order?
Nope, I'll sort this out
They appear to
> be the same minus the 'throttle' clock. Is there really no 'throttle'
> clock?
Looks like GCC_DISP_THROTTLE_AXI_CLK does exist on sm6350 as well, no
idea how/if it's used though.. Perhaps I can just remove it from sm6375
and if it turns out necessary we can reintroduce it another day.
Maybe this platform just tied it to one of the same clocks in the
> above?
Unlikely, most likely it's for some dire deep power saving stuff that
does not seem to be used/exposed, even on the bsp kernel
>
> I really hate the mess that is clocks. We have the same or related
> blocks with just totally different names and order. The result is
> if/then schemas or separate schemas like this. Neither option is great,
> but at least the if/then schemas provides some motivation to not have
> pointless variations like this. </rant>
It's a totally valid rant..
>
> As it seems the only difference between these 2 bindings is 1 extra
> clock, can't they be shared?
Sounds like a plan!
Konrad
>
> Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-28 13:03 ` Dmitry Baryshkov
@ 2023-05-08 22:03 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-05-08 22:03 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Konrad Dybcio, Abhinav Kumar, dri-devel,
linux-kernel, Konrad Dybcio, Rob Herring, Krishna Manikandan,
linux-arm-msm, linux-arm-kernel, Robin Murphy
On 2023-04-28 16:03:54, Dmitry Baryshkov wrote:
<snip>
> >> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> >
> > I thought it was QSEED3LITE, but doesn't really matter as both are
> > handled similarly. It'll anyway change when I resubmit:
>
> If I understood correctly, we mixed two things: hw stuff and the
> userspace library. QSEEDv2 was a hardware scaler. "qseedv3/v3lite/v4"
> are software library names that are used with the scalers newer than
> QSEED2. From the driver point we can ignore that and use scaler's hw
> version (which mostly but not always corresponds to the 3/3lite/4).
If I remember correctly, that matches the register changes we intended
to do in the patch below. This was only available starting at qseedv3.
One of the replies in that thread clarifies which register value is used
on what hardware, and that is what downstream switches on.
I'll try and respin it once we're through the DSC series.
- Marijn
> > https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
> >
> > which should hardcode the register value directly, making this field
> > superfluous.
<snip>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-05-08 22:03 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-05-08 22:03 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu, Konrad Dybcio
On 2023-04-28 16:03:54, Dmitry Baryshkov wrote:
<snip>
> >> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> >
> > I thought it was QSEED3LITE, but doesn't really matter as both are
> > handled similarly. It'll anyway change when I resubmit:
>
> If I understood correctly, we mixed two things: hw stuff and the
> userspace library. QSEEDv2 was a hardware scaler. "qseedv3/v3lite/v4"
> are software library names that are used with the scalers newer than
> QSEED2. From the driver point we can ignore that and use scaler's hw
> version (which mostly but not always corresponds to the 3/3lite/4).
If I remember correctly, that matches the register changes we intended
to do in the patch below. This was only available starting at qseedv3.
One of the replies in that thread clarifies which register value is used
on what hardware, and that is what downstream switches on.
I'll try and respin it once we're through the DSC series.
- Marijn
> > https://lore.kernel.org/linux-arm-msm/20230215-sspp-scaler-version-v1-0-416b1500b85b@somainline.org/T/#u
> >
> > which should hardcode the register value directly, making this field
> > superfluous.
<snip>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-05-05 12:11 ` Dmitry Baryshkov
@ 2023-05-08 22:04 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-05-08 22:04 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-arm-kernel, iommu, Konrad Dybcio
On 2023-05-05 15:11:44, Dmitry Baryshkov wrote:
> On 27/04/2023 18:37, Marijn Suijten wrote:
> > On 2023-04-21 00:31:16, Konrad Dybcio wrote:
> >> Add SM6350 support to the DPU1 driver to enable display output.
> >>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> >
> > After addressing the comments from Dmitry (CURSOR0->DMA1 and
> > CURSOR1->DMA2), this is:
> >
> > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> >
> > See below for some nits.
>
> [...]
>
> >> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> >> + {
> >> + .name = "top_0", .id = MDP_TOP,
> >> + .base = 0x0, .len = 0x494,
> >> + .features = 0,
> >> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> >> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> >> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> >> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> >> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> >> + },
> >> +};
> >> +
> >> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> >> + {
> >> + .name = "ctl_0", .id = CTL_0,
> >> + .base = 0x1000, .len = 0x1dc,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> >> + },
> >> + {
> >> + .name = "ctl_1", .id = CTL_1,
> >> + .base = 0x1200, .len = 0x1dc,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> >> + },
> >> + {
> >> + .name = "ctl_2", .id = CTL_2,
> >> + .base = 0x1400, .len = 0x1dc,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> >> + },
> >> + {
> >> + .name = "ctl_3", .id = CTL_3,
> >> + .base = 0x1600, .len = 0x1dc,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> >> + },
> >> +};
> >> +
> >> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> >> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> >> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> >> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> >> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> >> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> >> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> >> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> >> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> >> +};
> >> +
> >> +static const struct dpu_lm_cfg sm6350_lm[] = {
> >> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> >> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> >> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> >> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> >
> > These two entries are indented with two tabs and have one character too
> > many to align with the opening parenthesis on the previous line. Can we
> > please settle on a single style, as this commit mostly uses tabs+spaces
> > to align with the opening parenthesis?
> >
> > Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> > line with zero extra characters to the opening parenthesis), but I find
> > double tabs more convenient as it doesn't require reindenting when
> > changing the name of the macro (which happened too often in my INTF TE
> > series).
>
> I mainly vote for 'cino=(0' for indenting conditions (where double tab
> is confusing) and for function calls. I do not have a strong opinion
> about macros expansions. We have been using double-tab there, which is
> fine with me.
Agreed on both. `cino=(0` looks nice but double-tab in the catalog has
been easier to work with.
> Another option (which I personally find more appealing, but it doesn't
> play well with the current guidelines) is to have all macro arguments in
> a single line. It makes it easier to compare things.
Single line would be superb especially for current array tables.
>
> And another option would be to expand these macros up to some point.
> Previous experience with clock and interconnect drivers showed that
> expanding such multi-arg acros makes it _easier_ to handle the data.
> Counterintuitive, but true.
Fully agree, as well as inlining some flag constants.
<snip>
- Marijn
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-05-08 22:04 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2023-05-08 22:04 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, iommu, Krzysztof Kozlowski, Will Deacon, devicetree,
Sean Paul, Joerg Roedel, Konrad Dybcio, Abhinav Kumar, dri-devel,
linux-kernel, Konrad Dybcio, Rob Herring, Krishna Manikandan,
linux-arm-msm, linux-arm-kernel, Robin Murphy
On 2023-05-05 15:11:44, Dmitry Baryshkov wrote:
> On 27/04/2023 18:37, Marijn Suijten wrote:
> > On 2023-04-21 00:31:16, Konrad Dybcio wrote:
> >> Add SM6350 support to the DPU1 driver to enable display output.
> >>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> >
> > After addressing the comments from Dmitry (CURSOR0->DMA1 and
> > CURSOR1->DMA2), this is:
> >
> > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> >
> > See below for some nits.
>
> [...]
>
> >> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> >> + {
> >> + .name = "top_0", .id = MDP_TOP,
> >> + .base = 0x0, .len = 0x494,
> >> + .features = 0,
> >> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> >> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> >> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> >> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> >> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> >> + },
> >> +};
> >> +
> >> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
> >> + {
> >> + .name = "ctl_0", .id = CTL_0,
> >> + .base = 0x1000, .len = 0x1dc,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> >> + },
> >> + {
> >> + .name = "ctl_1", .id = CTL_1,
> >> + .base = 0x1200, .len = 0x1dc,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> >> + },
> >> + {
> >> + .name = "ctl_2", .id = CTL_2,
> >> + .base = 0x1400, .len = 0x1dc,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> >> + },
> >> + {
> >> + .name = "ctl_3", .id = CTL_3,
> >> + .base = 0x1600, .len = 0x1dc,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> >> + },
> >> +};
> >> +
> >> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> >> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> >> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> >> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> >> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> >> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> >> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> >> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> >> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> >> +};
> >> +
> >> +static const struct dpu_lm_cfg sm6350_lm[] = {
> >> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> >> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> >> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> >> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> >
> > These two entries are indented with two tabs and have one character too
> > many to align with the opening parenthesis on the previous line. Can we
> > please settle on a single style, as this commit mostly uses tabs+spaces
> > to align with the opening parenthesis?
> >
> > Dmitry vouched for `cino=(0` (when in unclosed parenthesis, align next
> > line with zero extra characters to the opening parenthesis), but I find
> > double tabs more convenient as it doesn't require reindenting when
> > changing the name of the macro (which happened too often in my INTF TE
> > series).
>
> I mainly vote for 'cino=(0' for indenting conditions (where double tab
> is confusing) and for function calls. I do not have a strong opinion
> about macros expansions. We have been using double-tab there, which is
> fine with me.
Agreed on both. `cino=(0` looks nice but double-tab in the catalog has
been easier to work with.
> Another option (which I personally find more appealing, but it doesn't
> play well with the current guidelines) is to have all macro arguments in
> a single line. It makes it easier to compare things.
Single line would be superb especially for current array tables.
>
> And another option would be to expand these macros up to some point.
> Previous experience with clock and interconnect drivers showed that
> expanding such multi-arg acros makes it _easier_ to handle the data.
> Counterintuitive, but true.
Fully agree, as well as inlining some flag constants.
<snip>
- Marijn
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
2023-04-20 23:05 ` Konrad Dybcio
(?)
@ 2023-05-18 21:21 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-05-18 21:21 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On 21/04/2023 02:05, Konrad Dybcio wrote:
>
>
> On 21.04.2023 00:41, Dmitry Baryshkov wrote:
>> On 21/04/2023 01:31, Konrad Dybcio wrote:
>>> Add SM6350 support to the DPU1 driver to enable display output.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
> [...]
>
>>> +
>>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>>
>> DPU_CLK_CTRL_DMA0
>>
>>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>>
>> DPU_CLK_CTRL_DMA2
> _DMA1?
>
>
>>
>>
>>> +};
>>> +
>
>>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>>> + {.fl = 0, .lut = 0x0011223344556677 },
>>> + {.fl = 0, .lut = 0x0011223445566777 },
>>
>> Do we need two equal entries here?
> Hmm.. looks like the SDE driver dropped the fill level
> logic in 4.19 times and that might have thrown me off
> when porting this Since the [0] entry has what looks
> like a lower LUT value, should I give it .fl=1?
>
>
>>
>> Also please push the qos to the dpu_hw_catalog.c, I want to take another look at these structures and it is easier if all of them are beneath one's eyes.
> Will do.
>
>>
>>> +};
>>> +
>>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>>> + .max_bw_low = 4200000,
>>> + .max_bw_high = 5100000,
>>> + .min_core_ib = 2500000,
>>> + .min_llcc_ib = 0,
>>> + .min_dram_ib = 1600000,
>>> + .min_prefill_lines = 35,
>>> + /* TODO: confirm danger_lut_tbl */
>>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> [...]
>
>
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>>> DPU_QOS_LUT_USAGE_LINEAR,
>>> DPU_QOS_LUT_USAGE_MACROTILE,
>>> DPU_QOS_LUT_USAGE_NRT,
>>> + DPU_QOS_LUT_USAGE_CWB,
>>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>>
>> This should probably be removed. It would be nice to clean these things up, but not as a part of sm6350.
> Well, I won't be able to fill in the danger LUT table otherwise!
danger/safe LUT tables have two entries for portrait/landscape (which we
do not support). Please choose either of them for now.
These two entries should be dropped for now (it was known for some time
that MACROTILE_QSEED != MACROTILE. And CWB is not supported yet).
>
> Konrad
>>
>>> DPU_QOS_LUT_USAGE_MAX,
>>> };
>>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> index 0e7a68714e9e..46be7ad8d615 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>>
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-05-18 21:21 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-05-18 21:21 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On 21/04/2023 02:05, Konrad Dybcio wrote:
>
>
> On 21.04.2023 00:41, Dmitry Baryshkov wrote:
>> On 21/04/2023 01:31, Konrad Dybcio wrote:
>>> Add SM6350 support to the DPU1 driver to enable display output.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
> [...]
>
>>> +
>>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>>
>> DPU_CLK_CTRL_DMA0
>>
>>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>>
>> DPU_CLK_CTRL_DMA2
> _DMA1?
>
>
>>
>>
>>> +};
>>> +
>
>>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>>> + {.fl = 0, .lut = 0x0011223344556677 },
>>> + {.fl = 0, .lut = 0x0011223445566777 },
>>
>> Do we need two equal entries here?
> Hmm.. looks like the SDE driver dropped the fill level
> logic in 4.19 times and that might have thrown me off
> when porting this Since the [0] entry has what looks
> like a lower LUT value, should I give it .fl=1?
>
>
>>
>> Also please push the qos to the dpu_hw_catalog.c, I want to take another look at these structures and it is easier if all of them are beneath one's eyes.
> Will do.
>
>>
>>> +};
>>> +
>>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>>> + .max_bw_low = 4200000,
>>> + .max_bw_high = 5100000,
>>> + .min_core_ib = 2500000,
>>> + .min_llcc_ib = 0,
>>> + .min_dram_ib = 1600000,
>>> + .min_prefill_lines = 35,
>>> + /* TODO: confirm danger_lut_tbl */
>>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> [...]
>
>
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>>> DPU_QOS_LUT_USAGE_LINEAR,
>>> DPU_QOS_LUT_USAGE_MACROTILE,
>>> DPU_QOS_LUT_USAGE_NRT,
>>> + DPU_QOS_LUT_USAGE_CWB,
>>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>>
>> This should probably be removed. It would be nice to clean these things up, but not as a part of sm6350.
> Well, I won't be able to fill in the danger LUT table otherwise!
danger/safe LUT tables have two entries for portrait/landscape (which we
do not support). Please choose either of them for now.
These two entries should be dropped for now (it was known for some time
that MACROTILE_QSEED != MACROTILE. And CWB is not supported yet).
>
> Konrad
>>
>>> DPU_QOS_LUT_USAGE_MAX,
>>> };
>>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> index 0e7a68714e9e..46be7ad8d615 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>>
>>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support
@ 2023-05-18 21:21 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2023-05-18 21:21 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel
Cc: devicetree, linux-arm-msm, Konrad Dybcio, linux-kernel,
dri-devel, iommu, Marijn Suijten, freedreno, linux-arm-kernel
On 21/04/2023 02:05, Konrad Dybcio wrote:
>
>
> On 21.04.2023 00:41, Dmitry Baryshkov wrote:
>> On 21/04/2023 01:31, Konrad Dybcio wrote:
>>> Add SM6350 support to the DPU1 driver to enable display output.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
> [...]
>
>>> +
>>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
>>> + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>>
>> DPU_CLK_CTRL_DMA0
>>
>>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>>
>> DPU_CLK_CTRL_DMA2
> _DMA1?
>
>
>>
>>
>>> +};
>>> +
>
>>> +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
>>> + {.fl = 0, .lut = 0x0011223344556677 },
>>> + {.fl = 0, .lut = 0x0011223445566777 },
>>
>> Do we need two equal entries here?
> Hmm.. looks like the SDE driver dropped the fill level
> logic in 4.19 times and that might have thrown me off
> when porting this Since the [0] entry has what looks
> like a lower LUT value, should I give it .fl=1?
>
>
>>
>> Also please push the qos to the dpu_hw_catalog.c, I want to take another look at these structures and it is easier if all of them are beneath one's eyes.
> Will do.
>
>>
>>> +};
>>> +
>>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>>> + .max_bw_low = 4200000,
>>> + .max_bw_high = 5100000,
>>> + .min_core_ib = 2500000,
>>> + .min_llcc_ib = 0,
>>> + .min_dram_ib = 1600000,
>>> + .min_prefill_lines = 35,
>>> + /* TODO: confirm danger_lut_tbl */
>>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> [...]
>
>
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage {
>>> DPU_QOS_LUT_USAGE_LINEAR,
>>> DPU_QOS_LUT_USAGE_MACROTILE,
>>> DPU_QOS_LUT_USAGE_NRT,
>>> + DPU_QOS_LUT_USAGE_CWB,
>>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>>
>> This should probably be removed. It would be nice to clean these things up, but not as a part of sm6350.
> Well, I won't be able to fill in the danger LUT table otherwise!
danger/safe LUT tables have two entries for portrait/landscape (which we
do not support). Please choose either of them for now.
These two entries should be dropped for now (it was known for some time
that MACROTILE_QSEED != MACROTILE. And CWB is not supported yet).
>
> Konrad
>>
>>> DPU_QOS_LUT_USAGE_MAX,
>>> };
>>> @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
>>> +extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
>>> extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> index 0e7a68714e9e..46be7ad8d615 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] = {
>>> { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
>>> { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
>>> { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
>>> + { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
>>> { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
>>> { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
>>> { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>>
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
end of thread, other threads:[~2023-05-18 21:22 UTC | newest]
Thread overview: 127+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-20 22:31 [PATCH v2 00/13] SM63(50|75) DPU support Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` [PATCH v2 01/13] dt-bindings: display/msm: dsi-controller-main: Add SM6350 Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` [PATCH v2 02/13] dt-bindings: display/msm: dsi-controller-main: Add SM6375 Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-25 16:53 ` Rob Herring
2023-04-25 16:53 ` Rob Herring
2023-04-25 16:53 ` Rob Herring
2023-04-25 17:03 ` Rob Herring
2023-04-25 17:03 ` Rob Herring
2023-04-25 17:03 ` Rob Herring
2023-05-05 12:38 ` Konrad Dybcio
2023-05-05 12:38 ` Konrad Dybcio
2023-05-05 12:38 ` Konrad Dybcio
2023-04-20 22:31 ` [PATCH v2 04/13] dt-bindings: display/msm: Add SM6350 MDSS Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-21 12:56 ` Rob Herring
2023-04-21 12:56 ` Rob Herring
2023-04-21 12:56 ` Rob Herring
2023-04-20 22:31 ` [PATCH v2 05/13] dt-bindings: display/msm: Add SM6375 DPU Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` [PATCH v2 06/13] dt-bindings: display/msm: Add SM6375 MDSS Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-21 12:56 ` Rob Herring
2023-04-21 12:56 ` Rob Herring
2023-04-21 12:56 ` Rob Herring
2023-04-20 22:31 ` [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:41 ` Dmitry Baryshkov
2023-04-20 22:41 ` Dmitry Baryshkov
2023-04-20 22:41 ` Dmitry Baryshkov
2023-04-20 23:05 ` Konrad Dybcio
2023-04-20 23:05 ` Konrad Dybcio
2023-04-20 23:05 ` Konrad Dybcio
2023-04-20 23:06 ` Dmitry Baryshkov
2023-04-20 23:06 ` Dmitry Baryshkov
2023-04-20 23:06 ` Dmitry Baryshkov
2023-05-18 21:21 ` Dmitry Baryshkov
2023-05-18 21:21 ` Dmitry Baryshkov
2023-05-18 21:21 ` Dmitry Baryshkov
2023-04-27 15:37 ` Marijn Suijten
2023-04-27 15:37 ` Marijn Suijten
2023-04-27 15:37 ` Marijn Suijten
2023-04-27 15:48 ` Marijn Suijten
2023-04-27 15:48 ` Marijn Suijten
2023-04-27 15:48 ` Marijn Suijten
2023-04-28 12:25 ` Konrad Dybcio
2023-04-28 12:25 ` Konrad Dybcio
2023-04-28 12:25 ` Konrad Dybcio
2023-04-28 12:24 ` Konrad Dybcio
2023-04-28 12:24 ` Konrad Dybcio
2023-04-28 12:24 ` Konrad Dybcio
2023-04-28 13:03 ` Dmitry Baryshkov
2023-04-28 13:03 ` Dmitry Baryshkov
2023-04-28 13:03 ` Dmitry Baryshkov
2023-05-08 22:03 ` Marijn Suijten
2023-05-08 22:03 ` Marijn Suijten
2023-05-05 12:11 ` Dmitry Baryshkov
2023-05-05 12:11 ` Dmitry Baryshkov
2023-05-05 12:11 ` Dmitry Baryshkov
2023-05-08 22:04 ` Marijn Suijten
2023-05-08 22:04 ` Marijn Suijten
2023-04-20 22:31 ` [PATCH v2 08/13] drm/msm: mdss: " Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:43 ` Dmitry Baryshkov
2023-04-20 22:43 ` Dmitry Baryshkov
2023-04-20 22:43 ` Dmitry Baryshkov
2023-04-27 21:03 ` Marijn Suijten
2023-04-27 21:03 ` Marijn Suijten
2023-04-27 21:03 ` Marijn Suijten
2023-04-20 22:31 ` [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:48 ` Dmitry Baryshkov
2023-04-20 22:48 ` Dmitry Baryshkov
2023-04-20 22:48 ` Dmitry Baryshkov
2023-04-27 15:46 ` Marijn Suijten
2023-04-27 15:46 ` Marijn Suijten
2023-04-27 15:46 ` Marijn Suijten
2023-04-28 12:32 ` Konrad Dybcio
2023-04-28 12:32 ` Konrad Dybcio
2023-04-28 12:32 ` Konrad Dybcio
2023-04-20 22:31 ` [PATCH v2 10/13] drm/msm: mdss: " Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:49 ` Dmitry Baryshkov
2023-04-20 22:49 ` Dmitry Baryshkov
2023-04-20 22:49 ` Dmitry Baryshkov
2023-04-20 22:50 ` Dmitry Baryshkov
2023-04-20 22:50 ` Dmitry Baryshkov
2023-04-20 22:50 ` Dmitry Baryshkov
2023-04-20 23:06 ` Konrad Dybcio
2023-04-20 23:06 ` Konrad Dybcio
2023-04-20 23:06 ` Konrad Dybcio
2023-04-27 21:04 ` Marijn Suijten
2023-04-27 21:04 ` Marijn Suijten
2023-04-27 21:04 ` Marijn Suijten
2023-04-20 22:31 ` [PATCH v2 11/13] iommu/arm-smmu-qcom: Add SM6375 DPU compatible Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:52 ` Dmitry Baryshkov
2023-04-20 22:52 ` Dmitry Baryshkov
2023-04-20 22:52 ` Dmitry Baryshkov
2023-04-20 22:31 ` [PATCH v2 12/13] iommu/arm-smmu-qcom: Add SM6350 " Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:51 ` Dmitry Baryshkov
2023-04-20 22:51 ` Dmitry Baryshkov
2023-04-20 22:51 ` Dmitry Baryshkov
2023-04-20 22:31 ` [PATCH v2 13/13] iommu/arm-smmu-qcom: Sort the compatible list alphabetically Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:31 ` Konrad Dybcio
2023-04-20 22:53 ` Dmitry Baryshkov
2023-04-20 22:53 ` Dmitry Baryshkov
2023-04-20 22:53 ` Dmitry Baryshkov
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