All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v2 0/7] MIPS: LLVM toolchain support for more CPUs
@ 2023-04-14  8:06 Jiaxun Yang
  2023-04-14  8:06 ` [PATCH v2 1/7] MIPS: Move various toolchain ASE check to Kconfig Jiaxun Yang
                   ` (6 more replies)
  0 siblings, 7 replies; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-14  8:06 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

This patchset is to add toolchain feature detection for most MIPS CPUs
by adding more toolchain feature detections and fixing -march CFLAGS.

Thanks
Jiaxun

Jiaxun Yang (7):
  MIPS: Move various toolchain ASE check to Kconfig
  MIPS: Add toolchain feature dependency for microMIPS smartMIPS
  MIPS: Detect toolchain support of workarounds in Kconfig
  MIPS: Detect toolchain support of o32 ABI with 64 bit CPU
  MIPS: Remove cc-option checks for -march=octeon
  MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  MIPS: Limit MIPS_MT_SMP support by ISA reversion

 arch/mips/Kconfig                | 68 ++++++++++++++++++++++++++++---
 arch/mips/Makefile               | 70 +++++++++++---------------------
 arch/mips/cavium-octeon/Kconfig  |  1 +
 arch/mips/crypto/crc32-mips.c    |  4 +-
 arch/mips/include/asm/asmmacro.h |  8 ++--
 arch/mips/include/asm/ginvt.h    |  2 +-
 arch/mips/include/asm/mipsregs.h | 10 ++---
 arch/mips/include/asm/msa.h      |  4 +-
 8 files changed, 101 insertions(+), 66 deletions(-)

-- 
2.39.2 (Apple Git-143)


^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH v2 1/7] MIPS: Move various toolchain ASE check to Kconfig
  2023-04-14  8:06 [PATCH v2 0/7] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
@ 2023-04-14  8:06 ` Jiaxun Yang
  2023-04-14  8:06 ` [PATCH v2 2/7] MIPS: Add toolchain feature dependency for microMIPS smartMIPS Jiaxun Yang
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-14  8:06 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

Use Kconfig to perform Kconfig toolchain feature check, so we will
be able to have toolchain feature availablility information in Kconfig
to guard relevant options.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v2: Fix a typo
---
 arch/mips/Kconfig                | 27 +++++++++++++++++++++++++++
 arch/mips/Makefile               | 29 +++--------------------------
 arch/mips/crypto/crc32-mips.c    |  4 ++--
 arch/mips/include/asm/asmmacro.h |  8 ++++----
 arch/mips/include/asm/ginvt.h    |  2 +-
 arch/mips/include/asm/mipsregs.h | 10 +++++-----
 arch/mips/include/asm/msa.h      |  4 ++--
 7 files changed, 44 insertions(+), 40 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 770d098b11bf..41ac4dc5aae4 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3157,6 +3157,12 @@ config MIPS32_N32
 
 	  If unsure, say N.
 
+config CC_HAS_SMARTMIPS
+	def_bool $(cc-option,-msmartmips)
+
+config CC_HAS_MICROMIPS
+	def_bool $(cc-option,-mmicromips)
+
 config CC_HAS_MNO_BRANCH_LIKELY
 	def_bool y
 	depends on $(cc-option,-mno-branch-likely)
@@ -3165,6 +3171,27 @@ config CC_HAS_MNO_BRANCH_LIKELY
 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
 	def_bool y if CC_IS_CLANG
 
+config AS_HAS_MSA
+	def_bool $(cc-option,-Wa$(comma)-mmsa)
+
+config AS_HAS_VIRT
+	def_bool $(cc-option,-Wa$(comma)-mvirt)
+
+# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which
+# only warns
+config AS_HAS_XPA
+	def_bool $(cc-option,-Wa$(comma)-mxpa) if !CPU_MICROMIPS
+	def_bool $(cc-option,-mmicromips -Wa$(comma)-fatal-warnings -Wa$(comma)-mxpa) if CPU_MICROMIPS
+
+config AS_HAS_CRC
+	def_bool $(cc-option,-Wa$(comma)-mcrc)
+
+config AS_HAS_DSP
+	def_bool $(cc-option,-Wa$(comma)-mdsp)
+
+config AS_HAS_GINV
+	def_bool $(cc-option,-Wa$(comma)-mginv)
+
 menu "Power management options"
 
 config ARCH_HIBERNATION_POSSIBLE
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index a7a4ee66a9d3..3aa0f9d4ceb6 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -233,32 +233,9 @@ cflags-$(CONFIG_CPU_LOONGSON64)	+= $(call as-option,-Wa$(comma)-mno-fix-loongson
 # Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
 # been fixed properly.
 mips-cflags				:= $(cflags-y)
-ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y)
-smartmips-ase				:= $(call cc-option-yn,$(mips-cflags) -msmartmips)
-cflags-$(smartmips-ase)			+= -msmartmips -Wa,--no-warn
-endif
-ifeq ($(CONFIG_CPU_MICROMIPS),y)
-micromips-ase				:= $(call cc-option-yn,$(mips-cflags) -mmicromips)
-cflags-$(micromips-ase)			+= -mmicromips
-endif
-ifeq ($(CONFIG_CPU_HAS_MSA),y)
-toolchain-msa				:= $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa)
-cflags-$(toolchain-msa)			+= -DTOOLCHAIN_SUPPORTS_MSA
-endif
-toolchain-virt				:= $(call cc-option-yn,$(mips-cflags) -mvirt)
-cflags-$(toolchain-virt)		+= -DTOOLCHAIN_SUPPORTS_VIRT
-# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which
-# only warns
-xpa-cflags-y				:= $(mips-cflags)
-xpa-cflags-$(micromips-ase)		+= -mmicromips -Wa$(comma)-fatal-warnings
-toolchain-xpa				:= $(call cc-option-yn,$(xpa-cflags-y) -mxpa)
-cflags-$(toolchain-xpa)			+= -DTOOLCHAIN_SUPPORTS_XPA
-toolchain-crc				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc)
-cflags-$(toolchain-crc)			+= -DTOOLCHAIN_SUPPORTS_CRC
-toolchain-dsp				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mdsp)
-cflags-$(toolchain-dsp)			+= -DTOOLCHAIN_SUPPORTS_DSP
-toolchain-ginv				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mginv)
-cflags-$(toolchain-ginv)		+= -DTOOLCHAIN_SUPPORTS_GINV
+
+cflags-$(CONFIG_CPU_HAS_SMARTMIPS)	+= -msmartmips -Wa,--no-warn
+cflags-$(CONFIG_CPU_MICROMIPS)		+= -mmicromips
 
 #
 # Firmware support
diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c
index 3e4f5ba104f8..54bbcfae06d5 100644
--- a/arch/mips/crypto/crc32-mips.c
+++ b/arch/mips/crypto/crc32-mips.c
@@ -27,7 +27,7 @@ enum crc_type {
 	crc32c,
 };
 
-#ifndef TOOLCHAIN_SUPPORTS_CRC
+#ifndef CONFIG_AS_HAS_CRC
 #define _ASM_SET_CRC(OP, SZ, TYPE)					  \
 _ASM_MACRO_3R(OP, rt, rs, rt2,						  \
 	".ifnc	\\rt, \\rt2\n\t"					  \
@@ -38,7 +38,7 @@ _ASM_MACRO_3R(OP, rt, rs, rt2,						  \
 	_ASM_INSN32_IF_MM(0x00000030 | (__rs << 16) | (__rt << 21) |	  \
 			  ((SZ) << 14) | ((TYPE) << 3)))
 #define _ASM_UNSET_CRC(op, SZ, TYPE) ".purgem " #op "\n\t"
-#else /* !TOOLCHAIN_SUPPORTS_CRC */
+#else /* !CONFIG_AS_HAS_CRC */
 #define _ASM_SET_CRC(op, SZ, TYPE) ".set\tcrc\n\t"
 #define _ASM_UNSET_CRC(op, SZ, TYPE)
 #endif
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 067a635d3bc8..74c2dedc55b4 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -239,7 +239,7 @@
 	 .word	0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
 	.endm
 
-#ifdef TOOLCHAIN_SUPPORTS_MSA
+#ifdef CONFIG_AS_HAS_MSA
 	.macro	_cfcmsa	rd, cs
 	.set	push
 	.set	mips32r2
@@ -507,7 +507,7 @@
 	.endm
 #endif
 
-#ifdef TOOLCHAIN_SUPPORTS_MSA
+#ifdef CONFIG_AS_HAS_MSA
 #define FPR_BASE_OFFS	THREAD_FPR0
 #define FPR_BASE	$1
 #else
@@ -518,7 +518,7 @@
 	.macro	msa_save_all	thread
 	.set	push
 	.set	noat
-#ifdef TOOLCHAIN_SUPPORTS_MSA
+#ifdef CONFIG_AS_HAS_MSA
 	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
 #endif
 	st_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
@@ -565,7 +565,7 @@
 	.set	hardfloat
 	lw	$1, THREAD_MSA_CSR(\thread)
 	_ctcmsa	MSA_CSR, $1
-#ifdef TOOLCHAIN_SUPPORTS_MSA
+#ifdef CONFIG_AS_HAS_MSA
 	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
 #endif
 	ld_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
diff --git a/arch/mips/include/asm/ginvt.h b/arch/mips/include/asm/ginvt.h
index 87b2974ffc53..20244a622552 100644
--- a/arch/mips/include/asm/ginvt.h
+++ b/arch/mips/include/asm/ginvt.h
@@ -10,7 +10,7 @@ enum ginvt_type {
 	GINVT_MMID,
 };
 
-#ifdef TOOLCHAIN_SUPPORTS_GINV
+#ifdef CONFIG_AS_HAS_GINV
 # define _ASM_SET_GINV	".set	ginv\n"
 # define _ASM_UNSET_GINV
 #else
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2d53704d9f24..8f0ebc399338 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1604,7 +1604,7 @@ do {									\
 	local_irq_restore(__flags);					\
 } while (0)
 
-#ifndef TOOLCHAIN_SUPPORTS_XPA
+#ifndef CONFIG_AS_HAS_XPA
 #define _ASM_SET_MFHC0							\
 	_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,				\
 			 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)	\
@@ -1615,7 +1615,7 @@ do {									\
 			 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)	\
 			 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11))
 #define _ASM_UNSET_MTHC0 ".purgem mthc0\n\t"
-#else	/* !TOOLCHAIN_SUPPORTS_XPA */
+#else	/* !CONFIG_AS_HAS_XPA */
 #define _ASM_SET_MFHC0 ".set\txpa\n\t"
 #define _ASM_SET_MTHC0 ".set\txpa\n\t"
 #define _ASM_UNSET_MFHC0
@@ -2040,7 +2040,7 @@ do {									\
  * Macros to access the guest system control coprocessor
  */
 
-#ifndef TOOLCHAIN_SUPPORTS_VIRT
+#ifndef CONFIG_AS_HAS_VIRT
 #define _ASM_SET_MFGC0							\
 	_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,				\
 			 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)	\
@@ -2077,7 +2077,7 @@ do {									\
 #define __tlbginvf()							\
 		_ASM_INSN_IF_MIPS(0x4200000c)				\
 		_ASM_INSN32_IF_MM(0x0000517c)
-#else	/* !TOOLCHAIN_SUPPORTS_VIRT */
+#else	/* !CONFIG_AS_HAS_VIRT */
 #define _ASM_SET_VIRT ".set\tvirt\n\t"
 #define _ASM_SET_MFGC0	_ASM_SET_VIRT
 #define _ASM_SET_DMFGC0	_ASM_SET_VIRT
@@ -2395,7 +2395,7 @@ do {									\
 	: : "r" (val));							\
 } while (0)
 
-#ifdef TOOLCHAIN_SUPPORTS_DSP
+#ifdef CONFIG_AS_HAS_DSP
 #define rddsp(mask)							\
 ({									\
 	unsigned int __dspctl;						\
diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h
index 236a49ee2e3e..a9ca57e3f780 100644
--- a/arch/mips/include/asm/msa.h
+++ b/arch/mips/include/asm/msa.h
@@ -156,7 +156,7 @@ static inline void init_msa_upper(void)
 	_init_msa_upper();
 }
 
-#ifndef TOOLCHAIN_SUPPORTS_MSA
+#ifndef CONFIG_AS_HAS_MSA
 /*
  * Define assembler macros using .word for the c[ft]cmsa instructions in order
  * to allow compilation with toolchains that do not support MSA. Once all
@@ -173,7 +173,7 @@ static inline void init_msa_upper(void)
 		      _ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6)	\
 		      _ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6))
 #define _ASM_UNSET_CTCMSA ".purgem ctcmsa\n\t"
-#else /* TOOLCHAIN_SUPPORTS_MSA */
+#else /* CONFIG_AS_HAS_MSA */
 #define _ASM_SET_CFCMSA						\
 		".set\tfp=64\n\t"				\
 		".set\tmsa\n\t"
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v2 2/7] MIPS: Add toolchain feature dependency for microMIPS smartMIPS
  2023-04-14  8:06 [PATCH v2 0/7] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
  2023-04-14  8:06 ` [PATCH v2 1/7] MIPS: Move various toolchain ASE check to Kconfig Jiaxun Yang
@ 2023-04-14  8:06 ` Jiaxun Yang
  2023-04-18 13:08   ` Thomas Bogendoerfer
  2023-04-14  8:06 ` [PATCH v2 3/7] MIPS: Detect toolchain support of workarounds in Kconfig Jiaxun Yang
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-14  8:06 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

microMIPS smartMIPS kernel can only be compiled if they are supported
by toolchain.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
---
 arch/mips/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 41ac4dc5aae4..0b270562c3eb 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2360,7 +2360,7 @@ config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
 	  Select this if you want neither microMIPS nor SmartMIPS support
 
 config CPU_HAS_SMARTMIPS
-	depends on SYS_SUPPORTS_SMARTMIPS
+	depends on SYS_SUPPORTS_SMARTMIPS && CC_HAS_SMARTMIPS
 	bool "SmartMIPS"
 	help
 	  SmartMIPS is a extension of the MIPS32 architecture aimed at
@@ -2373,6 +2373,7 @@ config CPU_HAS_SMARTMIPS
 
 config CPU_MICROMIPS
 	depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
+	depends on CC_HAS_MICROMIPS
 	bool "microMIPS"
 	help
 	  When this option is enabled the kernel will be built using the
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v2 3/7] MIPS: Detect toolchain support of workarounds in Kconfig
  2023-04-14  8:06 [PATCH v2 0/7] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
  2023-04-14  8:06 ` [PATCH v2 1/7] MIPS: Move various toolchain ASE check to Kconfig Jiaxun Yang
  2023-04-14  8:06 ` [PATCH v2 2/7] MIPS: Add toolchain feature dependency for microMIPS smartMIPS Jiaxun Yang
@ 2023-04-14  8:06 ` Jiaxun Yang
  2023-04-18 13:09   ` Thomas Bogendoerfer
  2023-04-14  8:06 ` [PATCH v2 4/7] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU Jiaxun Yang
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-14  8:06 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

LLVM toolchain does not support most of workarounds, detect
those supports in Kconfig so we can hide unsupported workarounds
to user.

Link: https://github.com/ClangBuiltLinux/linux/issues/1544
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
---
 arch/mips/Kconfig               | 28 +++++++++++++++++++++++++---
 arch/mips/Makefile              |  6 +++---
 arch/mips/cavium-octeon/Kconfig |  1 +
 3 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0b270562c3eb..0cd9cd01b7ab 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -371,9 +371,9 @@ config MACH_DECSTATION
 	select CEVT_R4K if CPU_R4X00
 	select CSRC_IOASIC
 	select CSRC_R4K if CPU_R4X00
-	select CPU_DADDI_WORKAROUNDS if 64BIT
-	select CPU_R4000_WORKAROUNDS if 64BIT
-	select CPU_R4400_WORKAROUNDS if 64BIT
+	imply CPU_DADDI_WORKAROUNDS
+	imply CPU_R4000_WORKAROUNDS
+	imply CPU_R4400_WORKAROUNDS
 	select DMA_NONCOHERENT
 	select NO_IOPORT_MAP
 	select IRQ_MIPS_CPU
@@ -1723,6 +1723,7 @@ config CPU_JUMP_WORKAROUNDS
 config CPU_LOONGSON2F_WORKAROUNDS
 	bool "Loongson 2F Workarounds"
 	default y
+	depends on AS_HAS_NOP_WORKAROUNDS && AS_HAS_JUMP_WORKAROUNDS
 	select CPU_NOP_WORKAROUNDS
 	select CPU_JUMP_WORKAROUNDS
 	help
@@ -2457,6 +2458,7 @@ config CPU_HAS_SYNC
 #   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
 config CPU_DADDI_WORKAROUNDS
 	bool
+	depends on CPU_R4X00_BUGS64 && CC_HAS_DADDI_WORKAROUNDS
 
 # Work around certain R4000 CPU errata (as implemented by GCC):
 #
@@ -2478,6 +2480,7 @@ config CPU_DADDI_WORKAROUNDS
 #   erratum #52
 config CPU_R4000_WORKAROUNDS
 	bool
+	depends on CPU_R4X00_BUGS64 && CC_HAS_R4000_WORKAROUNDS
 	select CPU_R4400_WORKAROUNDS
 
 # Work around certain R4400 CPU errata (as implemented by GCC):
@@ -2488,6 +2491,7 @@ config CPU_R4000_WORKAROUNDS
 #   "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
 config CPU_R4400_WORKAROUNDS
 	bool
+	depends on CPU_R4X00_BUGS64 && CC_HAS_R4400_WORKAROUNDS
 
 config CPU_R4X00_BUGS64
 	bool
@@ -3168,6 +3172,15 @@ config CC_HAS_MNO_BRANCH_LIKELY
 	def_bool y
 	depends on $(cc-option,-mno-branch-likely)
 
+config CC_HAS_R4000_WORKAROUNDS
+	def_bool $(cc-option,-mfix-r4000)
+
+config CC_HAS_R4400_WORKAROUNDS
+	def_bool $(cc-option,-mfix-r4400)
+
+config CC_HAS_DADDI_WORKAROUNDS
+	def_bool $(cc-option,-mno-daddi)
+
 # https://github.com/llvm/llvm-project/issues/61045
 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
 	def_bool y if CC_IS_CLANG
@@ -3193,6 +3206,15 @@ config AS_HAS_DSP
 config AS_HAS_GINV
 	def_bool $(cc-option,-Wa$(comma)-mginv)
 
+config AS_HAS_CN63XXP1_WORKAROUNDS
+	def_bool $(cc-option,-Wa$(comma)-mfix-cn63xxp1)
+
+config AS_HAS_NOP_WORKAROUNDS
+	def_bool $(cc-option,-Wa$(comma)-mfix-loongson2f-nop)
+
+config AS_HAS_JUMP_WORKAROUNDS
+	def_bool $(cc-option,-Wa$(comma)-mfix-loongson2f-jump)
+
 menu "Power management options"
 
 config ARCH_HIBERNATION_POSSIBLE
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 3aa0f9d4ceb6..344fe5f00f7b 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -193,9 +193,9 @@ cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2
 endif
 cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi)
 
-cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= $(call cc-option,-mfix-r4000,)
-cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)
-cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS)	+= $(call cc-option,-mno-daddi,)
+cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= -mfix-r4000
+cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= -mfix-r4400
+cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS)	+= -mno-daddi
 ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
 cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop
 cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 450e979ef5d9..38c9dc89cd5f 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -4,6 +4,7 @@ if CPU_CAVIUM_OCTEON
 config CAVIUM_CN63XXP1
 	bool "Enable CN63XXP1 errata workarounds"
 	default "n"
+	depends on AS_HAS_CN63XXP1_WORKAROUNDS
 	help
 	  The CN63XXP1 chip requires build time workarounds to
 	  function reliably, select this option to enable them.  These
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v2 4/7] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU
  2023-04-14  8:06 [PATCH v2 0/7] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
                   ` (2 preceding siblings ...)
  2023-04-14  8:06 ` [PATCH v2 3/7] MIPS: Detect toolchain support of workarounds in Kconfig Jiaxun Yang
@ 2023-04-14  8:06 ` Jiaxun Yang
  2023-04-14  8:06 ` [PATCH v2 5/7] MIPS: Remove cc-option checks for -march=octeon Jiaxun Yang
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-14  8:06 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

LLVM is not happy with using o32 ABI on 64 bit CPU, thus build 32 bit
kernel is unsupported.

Detect this in Kconfig to prevent user select 32 bit kernel with
unsupported toolchain.

Link: https://github.com/ClangBuiltLinux/linux/issues/884
Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0cd9cd01b7ab..2374f859e001 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2016,6 +2016,7 @@ choice
 config 32BIT
 	bool "32-bit kernel"
 	depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
+	depends on CC_HAS_O32_ABI
 	select TRAD_SIGNALS
 	help
 	  Select this option if you want to build a 32-bit kernel.
@@ -3137,7 +3138,7 @@ config COMPAT
 
 config MIPS32_O32
 	bool "Kernel support for o32 binaries"
-	depends on 64BIT
+	depends on 64BIT && CC_HAS_O32_ABI
 	select ARCH_WANT_OLD_COMPAT_IPC
 	select COMPAT
 	select MIPS32_COMPAT
@@ -3185,6 +3186,10 @@ config CC_HAS_DADDI_WORKAROUNDS
 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
 	def_bool y if CC_IS_CLANG
 
+config CC_HAS_O32_ABI
+	def_bool y
+	depends on !CPU_SUPPORTS_64BIT_KERNEL || $(cc-option,-march=mips3 -mabi=32)
+
 config AS_HAS_MSA
 	def_bool $(cc-option,-Wa$(comma)-mmsa)
 
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v2 5/7] MIPS: Remove cc-option checks for -march=octeon
  2023-04-14  8:06 [PATCH v2 0/7] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
                   ` (3 preceding siblings ...)
  2023-04-14  8:06 ` [PATCH v2 4/7] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU Jiaxun Yang
@ 2023-04-14  8:06 ` Jiaxun Yang
  2023-04-14  8:07 ` [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported Jiaxun Yang
  2023-04-14  8:07 ` [PATCH v2 7/7] MIPS: Limit MIPS_MT_SMP support by ISA reversion Jiaxun Yang
  6 siblings, 0 replies; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-14  8:06 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

Nowadays our minimal supported GCC/Clang all support -march=octeon.
Remove cc-option checks to simplify code.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Makefile | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 344fe5f00f7b..af3d17ec35d3 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -174,10 +174,7 @@ cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mdmx)
 cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mips3d)
 cflags-$(CONFIG_CPU_R10000)	+= $(call cc-option,-march=r10000,-march=r8000) \
 			-Wa,--trap
-cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
-ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
-cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
-endif
+cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -march=octeon -Wa,--trap
 cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
 cflags-$(CONFIG_CPU_BMIPS)	+= -march=mips32 -Wa,-mips32 -Wa,--trap
 
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-14  8:06 [PATCH v2 0/7] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
                   ` (4 preceding siblings ...)
  2023-04-14  8:06 ` [PATCH v2 5/7] MIPS: Remove cc-option checks for -march=octeon Jiaxun Yang
@ 2023-04-14  8:07 ` Jiaxun Yang
  2023-04-18 20:07   ` Nick Desaulniers
  2023-04-14  8:07 ` [PATCH v2 7/7] MIPS: Limit MIPS_MT_SMP support by ISA reversion Jiaxun Yang
  6 siblings, 1 reply; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-14  8:07 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

LLVM does not implement some of -march options. However those options
are not mandatory for kernel to build for those CPUs.

Fallback -march CFLAG to ISA level if unsupported by toolchain so
we can get those kernel to build with LLVM.

Link: https://github.com/ClangBuiltLinux/linux/issues/1544
Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v2: Reword commit message
---
 arch/mips/Makefile | 30 +++++++++++++++++-------------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index af3d17ec35d3..0fa84fc395c9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -148,10 +148,10 @@ cflags-y += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
 #
 # CPU-dependent compiler/assembler options for optimization.
 #
-cflags-$(CONFIG_CPU_R3000)	+= -march=r3000
-cflags-$(CONFIG_CPU_R4300)	+= -march=r4300 -Wa,--trap
-cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap
-cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap
+cflags-$(CONFIG_CPU_R3000)	+= $(call cc-option,-march=r3000,-march=mips1)
+cflags-$(CONFIG_CPU_R4300)	+= $(call cc-option,-march=r4300,-march=mips3) -Wa,--trap
+cflags-$(CONFIG_CPU_R4X00)	+= $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
+cflags-$(CONFIG_CPU_TX49XX)	+= $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R1)	+= -march=mips32 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R2)	+= -march=mips32r2 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R5)	+= -march=mips32r5 -Wa,--trap -modd-spreg
@@ -160,26 +160,30 @@ cflags-$(CONFIG_CPU_MIPS64_R1)	+= -march=mips64 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R2)	+= -march=mips64r2 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R5)	+= -march=mips64r5 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R6)	+= -march=mips64r6 -Wa,--trap
-cflags-$(CONFIG_CPU_P5600)	+= -march=p5600 -Wa,--trap -modd-spreg
-cflags-$(CONFIG_CPU_R5000)	+= -march=r5000 -Wa,--trap
-cflags-$(CONFIG_CPU_R5500)	+= $(call cc-option,-march=r5500,-march=r5000) \
+cflags-$(CONFIG_CPU_P5600)	+= $(call cc-option,-march=p5600,-march=mips32r5) \
+			-Wa,--trap -modd-spreg
+cflags-$(CONFIG_CPU_R5000)	+= $(call cc-option,-march=r5000,-march=mips4) \
 			-Wa,--trap
-cflags-$(CONFIG_CPU_NEVADA)	+= $(call cc-option,-march=rm5200,-march=r5000) \
+cflags-$(CONFIG_CPU_R5500)	+= $(call cc-option,-march=r5500,-march=mips4) \
 			-Wa,--trap
-cflags-$(CONFIG_CPU_RM7000)	+= $(call cc-option,-march=rm7000,-march=r5000) \
+cflags-$(CONFIG_CPU_NEVADA)	+= $(call cc-option,-march=rm5200,-march=mips4) \
 			-Wa,--trap
-cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-march=sb1,-march=r5000) \
+cflags-$(CONFIG_CPU_RM7000)	+= $(call cc-option,-march=rm7000,-march=mips4) \
+			-Wa,--trap
+cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-march=sb1,-march=mips4) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mdmx)
 cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mips3d)
-cflags-$(CONFIG_CPU_R10000)	+= $(call cc-option,-march=r10000,-march=r8000) \
+cflags-$(CONFIG_CPU_R10000)	+= $(call cc-option,-march=r10000,-march=mips4) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -march=octeon -Wa,--trap
 cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
 cflags-$(CONFIG_CPU_BMIPS)	+= -march=mips32 -Wa,-mips32 -Wa,--trap
 
-cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap
-cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2E) += \
+			$(call cc-option,-march=loongson2e,-march=mips3) -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2F) += \
+			$(call cc-option,-march=loongson2f,-march=mips3) -Wa,--trap
 # Some -march= flags enable MMI instructions, and GCC complains about that
 # support being enabled alongside -msoft-float. Thus explicitly disable MMI.
 cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi)
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v2 7/7] MIPS: Limit MIPS_MT_SMP support by ISA reversion
  2023-04-14  8:06 [PATCH v2 0/7] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
                   ` (5 preceding siblings ...)
  2023-04-14  8:07 ` [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported Jiaxun Yang
@ 2023-04-14  8:07 ` Jiaxun Yang
  6 siblings, 0 replies; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-14  8:07 UTC (permalink / raw)
  To: linux-mips
  Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang, Guenter Roeck

MIPS MT ASE is only available on ISA between Release 1 and Release 5.
Add ISA level dependency to Kconfig to fix build.

Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2374f859e001..a61f860771e2 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2194,7 +2194,8 @@ config CPU_R4K_CACHE_TLB
 config MIPS_MT_SMP
 	bool "MIPS MT SMP support (1 TC on each available VPE)"
 	default y
-	depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
+	depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
+	depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
 	select CPU_MIPSR2_IRQ_VI
 	select CPU_MIPSR2_IRQ_EI
 	select SYNC_R4K
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/7] MIPS: Add toolchain feature dependency for microMIPS smartMIPS
  2023-04-14  8:06 ` [PATCH v2 2/7] MIPS: Add toolchain feature dependency for microMIPS smartMIPS Jiaxun Yang
@ 2023-04-18 13:08   ` Thomas Bogendoerfer
  2023-04-19 23:01     ` Nick Desaulniers
  0 siblings, 1 reply; 24+ messages in thread
From: Thomas Bogendoerfer @ 2023-04-18 13:08 UTC (permalink / raw)
  To: Jiaxun Yang; +Cc: linux-mips, llvm, ndesaulniers, nathan

On Fri, Apr 14, 2023 at 09:06:56AM +0100, Jiaxun Yang wrote:
> microMIPS smartMIPS kernel can only be compiled if they are supported
> by toolchain.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
> ---
>  arch/mips/Kconfig | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 41ac4dc5aae4..0b270562c3eb 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2360,7 +2360,7 @@ config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
>  	  Select this if you want neither microMIPS nor SmartMIPS support
>  
>  config CPU_HAS_SMARTMIPS
> -	depends on SYS_SUPPORTS_SMARTMIPS
> +	depends on SYS_SUPPORTS_SMARTMIPS && CC_HAS_SMARTMIPS
>  	bool "SmartMIPS"
>  	help
>  	  SmartMIPS is a extension of the MIPS32 architecture aimed at
> @@ -2373,6 +2373,7 @@ config CPU_HAS_SMARTMIPS
>  
>  config CPU_MICROMIPS
>  	depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
> +	depends on CC_HAS_MICROMIPS
>  	bool "microMIPS"
>  	help
>  	  When this option is enabled the kernel will be built using the

hmm, with this change the options will silently be dropped. I prefer
the error message, that the compiler doesn't support what is configured.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 3/7] MIPS: Detect toolchain support of workarounds in Kconfig
  2023-04-14  8:06 ` [PATCH v2 3/7] MIPS: Detect toolchain support of workarounds in Kconfig Jiaxun Yang
@ 2023-04-18 13:09   ` Thomas Bogendoerfer
  2023-04-18 17:14     ` Jiaxun Yang
  0 siblings, 1 reply; 24+ messages in thread
From: Thomas Bogendoerfer @ 2023-04-18 13:09 UTC (permalink / raw)
  To: Jiaxun Yang; +Cc: linux-mips, llvm, ndesaulniers, nathan

On Fri, Apr 14, 2023 at 09:06:57AM +0100, Jiaxun Yang wrote:
> LLVM toolchain does not support most of workarounds, detect
> those supports in Kconfig so we can hide unsupported workarounds
> to user.

again hiding something, which then needs to be digged out is IMHO not
a good way.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 3/7] MIPS: Detect toolchain support of workarounds in Kconfig
  2023-04-18 13:09   ` Thomas Bogendoerfer
@ 2023-04-18 17:14     ` Jiaxun Yang
  0 siblings, 0 replies; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-18 17:14 UTC (permalink / raw)
  To: Thomas Bogendoerfer; +Cc: linux-mips, llvm, Nick Desaulniers, Nathan Chancellor



> 2023年4月18日 14:09，Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写道：
> 
> On Fri, Apr 14, 2023 at 09:06:57AM +0100, Jiaxun Yang wrote:
>> LLVM toolchain does not support most of workarounds, detect
>> those supports in Kconfig so we can hide unsupported workarounds
>> to user.
> 
> again hiding something, which then needs to be digged out is IMHO not
> a good way.

Agreed, my universal target is to make every defconfig build against clang so we
can leverage clang’s warning to find any potential problems, and possibly use clang
built kernel on machines that don't need those workaround. Seems like better option
Is to let user to drop those configs manually.

Will drop this two patch.

Thanks
Jiaxun


> 
> Thomas.
> 
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]


^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-14  8:07 ` [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported Jiaxun Yang
@ 2023-04-18 20:07   ` Nick Desaulniers
  2023-04-19 16:50     ` Jiaxun Yang
  0 siblings, 1 reply; 24+ messages in thread
From: Nick Desaulniers @ 2023-04-18 20:07 UTC (permalink / raw)
  To: Jiaxun Yang; +Cc: linux-mips, llvm, tsbogend, nathan

On Fri, Apr 14, 2023 at 1:07 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> LLVM does not implement some of -march options. However those options
> are not mandatory for kernel to build for those CPUs.
>
> Fallback -march CFLAG to ISA level if unsupported by toolchain so
> we can get those kernel to build with LLVM.
>
> Link: https://github.com/ClangBuiltLinux/linux/issues/1544
> Reported-by: Nathan Chancellor <nathan@kernel.org>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Thanks for the patch! Maybe it's more obvious to folks who work on
mips, but how did you determine that say `p5600` is `mips32r5` or
`r10000` is `mips4`?

Is there a table somewhere you used as a reference? Including such
info in the commit message would help reviewers such as myself verify
the patch.

Also, in v1, you mentioned that -mtune is not a substitute. It would
be good to record that info in the commit message as well.

> ---
> v2: Reword commit message
> ---
>  arch/mips/Makefile | 30 +++++++++++++++++-------------
>  1 file changed, 17 insertions(+), 13 deletions(-)
>
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index af3d17ec35d3..0fa84fc395c9 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -148,10 +148,10 @@ cflags-y += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
>  #
>  # CPU-dependent compiler/assembler options for optimization.
>  #
> -cflags-$(CONFIG_CPU_R3000)     += -march=r3000
> -cflags-$(CONFIG_CPU_R4300)     += -march=r4300 -Wa,--trap
> -cflags-$(CONFIG_CPU_R4X00)     += -march=r4600 -Wa,--trap
> -cflags-$(CONFIG_CPU_TX49XX)    += -march=r4600 -Wa,--trap
> +cflags-$(CONFIG_CPU_R3000)     += $(call cc-option,-march=r3000,-march=mips1)
> +cflags-$(CONFIG_CPU_R4300)     += $(call cc-option,-march=r4300,-march=mips3) -Wa,--trap
> +cflags-$(CONFIG_CPU_R4X00)     += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
> +cflags-$(CONFIG_CPU_TX49XX)    += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg
> @@ -160,26 +160,30 @@ cflags-$(CONFIG_CPU_MIPS64_R1)    += -march=mips64 -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS64_R5) += -march=mips64r5 -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap
> -cflags-$(CONFIG_CPU_P5600)     += -march=p5600 -Wa,--trap -modd-spreg
> -cflags-$(CONFIG_CPU_R5000)     += -march=r5000 -Wa,--trap
> -cflags-$(CONFIG_CPU_R5500)     += $(call cc-option,-march=r5500,-march=r5000) \
> +cflags-$(CONFIG_CPU_P5600)     += $(call cc-option,-march=p5600,-march=mips32r5) \
> +                       -Wa,--trap -modd-spreg
> +cflags-$(CONFIG_CPU_R5000)     += $(call cc-option,-march=r5000,-march=mips4) \
>                         -Wa,--trap
> -cflags-$(CONFIG_CPU_NEVADA)    += $(call cc-option,-march=rm5200,-march=r5000) \
> +cflags-$(CONFIG_CPU_R5500)     += $(call cc-option,-march=r5500,-march=mips4) \
>                         -Wa,--trap
> -cflags-$(CONFIG_CPU_RM7000)    += $(call cc-option,-march=rm7000,-march=r5000) \
> +cflags-$(CONFIG_CPU_NEVADA)    += $(call cc-option,-march=rm5200,-march=mips4) \
>                         -Wa,--trap
> -cflags-$(CONFIG_CPU_SB1)       += $(call cc-option,-march=sb1,-march=r5000) \
> +cflags-$(CONFIG_CPU_RM7000)    += $(call cc-option,-march=rm7000,-march=mips4) \
> +                       -Wa,--trap
> +cflags-$(CONFIG_CPU_SB1)       += $(call cc-option,-march=sb1,-march=mips4) \
>                         -Wa,--trap
>  cflags-$(CONFIG_CPU_SB1)       += $(call cc-option,-mno-mdmx)
>  cflags-$(CONFIG_CPU_SB1)       += $(call cc-option,-mno-mips3d)
> -cflags-$(CONFIG_CPU_R10000)    += $(call cc-option,-march=r10000,-march=r8000) \
> +cflags-$(CONFIG_CPU_R10000)    += $(call cc-option,-march=r10000,-march=mips4) \
>                         -Wa,--trap
>  cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -march=octeon -Wa,--trap
>  cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
>  cflags-$(CONFIG_CPU_BMIPS)     += -march=mips32 -Wa,-mips32 -Wa,--trap
>
> -cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap
> -cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap
> +cflags-$(CONFIG_CPU_LOONGSON2E) += \
> +                       $(call cc-option,-march=loongson2e,-march=mips3) -Wa,--trap
> +cflags-$(CONFIG_CPU_LOONGSON2F) += \
> +                       $(call cc-option,-march=loongson2f,-march=mips3) -Wa,--trap
>  # Some -march= flags enable MMI instructions, and GCC complains about that
>  # support being enabled alongside -msoft-float. Thus explicitly disable MMI.
>  cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi)
> --
> 2.39.2 (Apple Git-143)
>


-- 
Thanks,
~Nick Desaulniers

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-18 20:07   ` Nick Desaulniers
@ 2023-04-19 16:50     ` Jiaxun Yang
  2023-04-19 21:35       ` Nick Desaulniers
  0 siblings, 1 reply; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-19 16:50 UTC (permalink / raw)
  To: Nick Desaulniers; +Cc: linux-mips, llvm, Thomas Bogendoerfer, Nathan Chancellor



> 2023年4月18日 21:07，Nick Desaulniers <ndesaulniers@google.com> 写道：
> 
> On Fri, Apr 14, 2023 at 1:07 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>> 
>> LLVM does not implement some of -march options. However those options
>> are not mandatory for kernel to build for those CPUs.
>> 
>> Fallback -march CFLAG to ISA level if unsupported by toolchain so
>> we can get those kernel to build with LLVM.
>> 
>> Link: https://github.com/ClangBuiltLinux/linux/issues/1544
>> Reported-by: Nathan Chancellor <nathan@kernel.org>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> 
> Thanks for the patch! Maybe it's more obvious to folks who work on
> mips, but how did you determine that say `p5600` is `mips32r5` or
> `r10000` is `mips4`?

Wikipedia [1] should fit the purpose.

> 
> Is there a table somewhere you used as a reference? Including such
> info in the commit message would help reviewers such as myself verify
> the patch.
> 
> Also, in v1, you mentioned that -mtune is not a substitute. It would
> be good to record that info in the commit message as well.

Thanks for the input! Will reword in next rev.

> 


[1]: https://en.wikipedia.org/wiki/List_of_MIPS_architecture_processors

Thanks
- Jiaxun

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-19 16:50     ` Jiaxun Yang
@ 2023-04-19 21:35       ` Nick Desaulniers
  2023-04-19 22:15         ` Thomas Bogendoerfer
  0 siblings, 1 reply; 24+ messages in thread
From: Nick Desaulniers @ 2023-04-19 21:35 UTC (permalink / raw)
  To: Jiaxun Yang, Thomas Bogendoerfer; +Cc: linux-mips, llvm, Nathan Chancellor

On Wed, Apr 19, 2023 at 9:50 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
>
>
> > 2023年4月18日 21:07，Nick Desaulniers <ndesaulniers@google.com> 写道：
> >
> > On Fri, Apr 14, 2023 at 1:07 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> >>
> >> LLVM does not implement some of -march options. However those options
> >> are not mandatory for kernel to build for those CPUs.
> >>
> >> Fallback -march CFLAG to ISA level if unsupported by toolchain so
> >> we can get those kernel to build with LLVM.
> >>
> >> Link: https://github.com/ClangBuiltLinux/linux/issues/1544
> >> Reported-by: Nathan Chancellor <nathan@kernel.org>
> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >
> > Thanks for the patch! Maybe it's more obvious to folks who work on
> > mips, but how did you determine that say `p5600` is `mips32r5` or
> > `r10000` is `mips4`?
>
> Wikipedia [1] should fit the purpose.
>
> [1]: https://en.wikipedia.org/wiki/List_of_MIPS_architecture_processors

Mostly! Though I was not able to verify:
- p5600
- r5500
- rm5200
- sb1
- loongson*

The rest LGTM, but maybe these families are better understood by Thomas?
-- 
Thanks,
~Nick Desaulniers

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-19 21:35       ` Nick Desaulniers
@ 2023-04-19 22:15         ` Thomas Bogendoerfer
  2023-04-19 23:36           ` Jiaxun Yang
  2023-04-20 16:32           ` Nick Desaulniers
  0 siblings, 2 replies; 24+ messages in thread
From: Thomas Bogendoerfer @ 2023-04-19 22:15 UTC (permalink / raw)
  To: Nick Desaulniers; +Cc: Jiaxun Yang, linux-mips, llvm, Nathan Chancellor

On Wed, Apr 19, 2023 at 02:35:02PM -0700, Nick Desaulniers wrote:
> On Wed, Apr 19, 2023 at 9:50 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> >
> >
> >
> > > 2023年4月18日 21:07，Nick Desaulniers <ndesaulniers@google.com> 写道：
> > >
> > > On Fri, Apr 14, 2023 at 1:07 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> > >>
> > >> LLVM does not implement some of -march options. However those options
> > >> are not mandatory for kernel to build for those CPUs.
> > >>
> > >> Fallback -march CFLAG to ISA level if unsupported by toolchain so
> > >> we can get those kernel to build with LLVM.
> > >>
> > >> Link: https://github.com/ClangBuiltLinux/linux/issues/1544
> > >> Reported-by: Nathan Chancellor <nathan@kernel.org>
> > >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > >
> > > Thanks for the patch! Maybe it's more obvious to folks who work on
> > > mips, but how did you determine that say `p5600` is `mips32r5` or
> > > `r10000` is `mips4`?
> >
> > Wikipedia [1] should fit the purpose.
> >
> > [1]: https://en.wikipedia.org/wiki/List_of_MIPS_architecture_processors
> 
> Mostly! Though I was not able to verify:
> - p5600

mips32r5

> - r5500

mips4

> - rm5200

mips4

> - sb1

mips64r1

all information taken from datasheets.

> - loongson*

probably depends on the exact type, but as I don't have datasheets
I can't say what it is exactly, probaly mips32r2/mips64r2.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/7] MIPS: Add toolchain feature dependency for microMIPS smartMIPS
  2023-04-18 13:08   ` Thomas Bogendoerfer
@ 2023-04-19 23:01     ` Nick Desaulniers
  2023-04-20 19:41       ` Jiaxun Yang
  0 siblings, 1 reply; 24+ messages in thread
From: Nick Desaulniers @ 2023-04-19 23:01 UTC (permalink / raw)
  To: Thomas Bogendoerfer
  Cc: Jiaxun Yang, linux-mips, llvm, nathan, Borislav Petkov,
	Linux Kbuild mailing list, Masahiro Yamada

On Tue, Apr 18, 2023 at 6:13 AM Thomas Bogendoerfer
<tsbogend@alpha.franken.de> wrote:
>
> On Fri, Apr 14, 2023 at 09:06:56AM +0100, Jiaxun Yang wrote:
> > microMIPS smartMIPS kernel can only be compiled if they are supported
> > by toolchain.
> >
> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>

Question: won't the lack of this (patch and rest of the series) hurt
our ability to test randconfig builds of ARCH=mips with clang? See
also the 0day report from Boris:
https://lore.kernel.org/llvm/202304170748.Fg9VIgGd-lkp@intel.com/

i.e. randconfig will continue to select options that can't be built yet.

> > ---
> >  arch/mips/Kconfig | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> > index 41ac4dc5aae4..0b270562c3eb 100644
> > --- a/arch/mips/Kconfig
> > +++ b/arch/mips/Kconfig
> > @@ -2360,7 +2360,7 @@ config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
> >         Select this if you want neither microMIPS nor SmartMIPS support
> >
> >  config CPU_HAS_SMARTMIPS
> > -     depends on SYS_SUPPORTS_SMARTMIPS
> > +     depends on SYS_SUPPORTS_SMARTMIPS && CC_HAS_SMARTMIPS
> >       bool "SmartMIPS"
> >       help
> >         SmartMIPS is a extension of the MIPS32 architecture aimed at
> > @@ -2373,6 +2373,7 @@ config CPU_HAS_SMARTMIPS
> >
> >  config CPU_MICROMIPS
> >       depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
> > +     depends on CC_HAS_MICROMIPS
> >       bool "microMIPS"
> >       help
> >         When this option is enabled the kernel will be built using the
>
> hmm, with this change the options will silently be dropped. I prefer
> the error message, that the compiler doesn't support what is configured.
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]



-- 
Thanks,
~Nick Desaulniers

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-19 22:15         ` Thomas Bogendoerfer
@ 2023-04-19 23:36           ` Jiaxun Yang
  2023-04-20  8:06             ` Thomas Bogendoerfer
  2023-04-20 16:32           ` Nick Desaulniers
  1 sibling, 1 reply; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-19 23:36 UTC (permalink / raw)
  To: Thomas Bogendoerfer; +Cc: Nick Desaulniers, linux-mips, llvm, Nathan Chancellor



> 2023年4月19日 23:15，Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写道：
> 
> On Wed, Apr 19, 2023 at 02:35:02PM -0700, Nick Desaulniers wrote:
>> On Wed, Apr 19, 2023 at 9:50 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>>> 
>>> 
>>> 
>>>> 2023年4月18日 21:07，Nick Desaulniers <ndesaulniers@google.com> 写道：
>>>> 
>>>> On Fri, Apr 14, 2023 at 1:07 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>>>>> 
>>>>> LLVM does not implement some of -march options. However those options
>>>>> are not mandatory for kernel to build for those CPUs.
>>>>> 
>>>>> Fallback -march CFLAG to ISA level if unsupported by toolchain so
>>>>> we can get those kernel to build with LLVM.
>>>>> 
>>>>> Link: https://github.com/ClangBuiltLinux/linux/issues/1544
>>>>> Reported-by: Nathan Chancellor <nathan@kernel.org>
>>>>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>>> 
>>>> Thanks for the patch! Maybe it's more obvious to folks who work on
>>>> mips, but how did you determine that say `p5600` is `mips32r5` or
>>>> `r10000` is `mips4`?
>>> 
>>> Wikipedia [1] should fit the purpose.
>>> 
>>> [1]: https://en.wikipedia.org/wiki/List_of_MIPS_architecture_processors
>> 
>> Mostly! Though I was not able to verify:
>> - p5600
> 
> mips32r5

On wikipedia’s “Imagination Technologies” section.

> 
>> - r5500
> 
> mips4
> 
>> - rm5200
> 
> mips4

I think those are all R5000 derivatives?

> 
>> - sb1
> 
> mips64r1

On wikipedia’s "Other designers” section.

> 
> all information taken from datasheets.
> 
>> - loongson*

Loongson-1A/1B/1C: Claims to be MIPS32R2 but lacks FP64 and DIEI, so I’d say they are R1.
Loongson2e/Loongson2f: MIPS-III
Loongson64: MIPS64R2

Thanks.
- Jiaxu

> 
> probably depends on the exact type, but as I don't have datasheets
> I can't say what it is exactly, probaly mips32r2/mips64r2.
> 
> Thomas.
> 
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]



^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-19 23:36           ` Jiaxun Yang
@ 2023-04-20  8:06             ` Thomas Bogendoerfer
  0 siblings, 0 replies; 24+ messages in thread
From: Thomas Bogendoerfer @ 2023-04-20  8:06 UTC (permalink / raw)
  To: Jiaxun Yang; +Cc: Nick Desaulniers, linux-mips, llvm, Nathan Chancellor

On Thu, Apr 20, 2023 at 12:36:41AM +0100, Jiaxun Yang wrote:
> >>> Wikipedia [1] should fit the purpose.
> >>> 
> >>> [1]: https://en.wikipedia.org/wiki/List_of_MIPS_architecture_processors
> >> 
> >> Mostly! Though I was not able to verify:
> >> - p5600
> > 
> > mips32r5
> 
> On wikipedia’s “Imagination Technologies” section.
> 
> > 
> >> - r5500
> > 
> > mips4
> > 
> >> - rm5200
> > 
> > mips4
> 
> I think those are all R5000 derivatives?

yes, which makes them mips4. Vr5500 is special as it supports out-of-order
execution.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-19 22:15         ` Thomas Bogendoerfer
  2023-04-19 23:36           ` Jiaxun Yang
@ 2023-04-20 16:32           ` Nick Desaulniers
  2023-04-20 18:42             ` Xi Ruoyao
  2023-04-20 19:16             ` Jiaxun Yang
  1 sibling, 2 replies; 24+ messages in thread
From: Nick Desaulniers @ 2023-04-20 16:32 UTC (permalink / raw)
  To: Thomas Bogendoerfer, Jiaxun Yang
  Cc: linux-mips, llvm, Nathan Chancellor, Huacai Chen, kernel, loongarch

On Wed, Apr 19, 2023 at 3:15 PM Thomas Bogendoerfer
<tsbogend@alpha.franken.de> wrote:
>
> On Wed, Apr 19, 2023 at 02:35:02PM -0700, Nick Desaulniers wrote:
> > On Wed, Apr 19, 2023 at 9:50 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> > >
> > >
> > >
> > > > 2023年4月18日 21:07，Nick Desaulniers <ndesaulniers@google.com> 写道：
> > > >
> > > > On Fri, Apr 14, 2023 at 1:07 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> > > >>
> > > >> LLVM does not implement some of -march options. However those options
> > > >> are not mandatory for kernel to build for those CPUs.
> > > >>
> > > >> Fallback -march CFLAG to ISA level if unsupported by toolchain so
> > > >> we can get those kernel to build with LLVM.
> > > >>
> > > >> Link: https://github.com/ClangBuiltLinux/linux/issues/1544
> > > >> Reported-by: Nathan Chancellor <nathan@kernel.org>
> > > >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > > >
> > > > Thanks for the patch! Maybe it's more obvious to folks who work on
> > > > mips, but how did you determine that say `p5600` is `mips32r5` or
> > > > `r10000` is `mips4`?
> > >
> > > Wikipedia [1] should fit the purpose.
> > >
> > > [1]: https://en.wikipedia.org/wiki/List_of_MIPS_architecture_processors
> >
> > Mostly! Though I was not able to verify:
> > - p5600
>
> mips32r5
>
> > - r5500
>
> mips4
>
> > - rm5200
>
> mips4
>
> > - sb1
>
> mips64r1

Thomas, thanks for reviewing datasheets to verify this.

Jiaxun, for SB1, you have cc-option fall back to -march=mips4, does
that need to be -march=mips64r1?

(With that last question resolved, I'm happy to sign off on this patch)

>
> all information taken from datasheets.
>
> > - loongson*
>
> probably depends on the exact type, but as I don't have datasheets
> I can't say what it is exactly, probaly mips32r2/mips64r2.

Oh look Jiaxun, you are the maintainer for
"MIPS/LOONGSON64 ARCHITECTURE"
ok then I will trust your knowledge of this architecture!

---
Separate question to Huacai, Wang, and the loongarch list; I know LLVM
landed the Loongarch backend recently; any idea what's the status of
building arch=loongarch with LLVM=1 (linux kernel)?

-- 
Thanks,
~Nick Desaulniers

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-20 16:32           ` Nick Desaulniers
@ 2023-04-20 18:42             ` Xi Ruoyao
  2023-04-20 18:50               ` Xi Ruoyao
  2023-04-20 19:16             ` Jiaxun Yang
  1 sibling, 1 reply; 24+ messages in thread
From: Xi Ruoyao @ 2023-04-20 18:42 UTC (permalink / raw)
  To: Nick Desaulniers, Thomas Bogendoerfer, Jiaxun Yang
  Cc: linux-mips, llvm, Nathan Chancellor, Huacai Chen, kernel, loongarch

Hi Nick,

On Thu, 2023-04-20 at 09:32 -0700, Nick Desaulniers wrote:
> Separate question to Huacai, Wang, and the loongarch list; I know LLVM
> landed the Loongarch backend recently; any idea what's the status of
> building arch=loongarch with LLVM=1 (linux kernel)?

AFAIK there are some issues not resolved yet:
https://github.com/ClangBuiltLinux/linux/issues/1787
-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-20 18:42             ` Xi Ruoyao
@ 2023-04-20 18:50               ` Xi Ruoyao
  0 siblings, 0 replies; 24+ messages in thread
From: Xi Ruoyao @ 2023-04-20 18:50 UTC (permalink / raw)
  To: Nick Desaulniers, Thomas Bogendoerfer, Jiaxun Yang
  Cc: linux-mips, llvm, Nathan Chancellor, Huacai Chen, kernel, loongarch

On Fri, 2023-04-21 at 02:42 +0800, Xi Ruoyao wrote:
> Hi Nick,
> 
> On Thu, 2023-04-20 at 09:32 -0700, Nick Desaulniers wrote:
> > Separate question to Huacai, Wang, and the loongarch list; I know
> > LLVM
> > landed the Loongarch backend recently; any idea what's the status of
> > building arch=loongarch with LLVM=1 (linux kernel)?
> 
> AFAIK there are some issues not resolved yet:
> https://github.com/ClangBuiltLinux/linux/issues/1787

I must be completely stupid: I didn't see you are the one raised the
ticket :).

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-20 16:32           ` Nick Desaulniers
  2023-04-20 18:42             ` Xi Ruoyao
@ 2023-04-20 19:16             ` Jiaxun Yang
  1 sibling, 0 replies; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-20 19:16 UTC (permalink / raw)
  To: Nick Desaulniers
  Cc: Thomas Bogendoerfer, linux-mips, llvm, Nathan Chancellor,
	Huacai Chen, Xuerui Wang, loongarch



> 2023年4月20日 17:32，Nick Desaulniers <ndesaulniers@google.com> 写道：
> 
> On Wed, Apr 19, 2023 at 3:15 PM Thomas Bogendoerfer
> <tsbogend@alpha.franken.de> wrote:
>> 
>> On Wed, Apr 19, 2023 at 02:35:02PM -0700, Nick Desaulniers wrote:
>>> On Wed, Apr 19, 2023 at 9:50 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>>>> 
>>>> 
>>>> 
>>>>> 2023年4月18日 21:07，Nick Desaulniers <ndesaulniers@google.com> 写道：
>>>>> 
>>>>> On Fri, Apr 14, 2023 at 1:07 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>>>>>> 
>>>>>> LLVM does not implement some of -march options. However those options
>>>>>> are not mandatory for kernel to build for those CPUs.
>>>>>> 
>>>>>> Fallback -march CFLAG to ISA level if unsupported by toolchain so
>>>>>> we can get those kernel to build with LLVM.
>>>>>> 
>>>>>> Link: https://github.com/ClangBuiltLinux/linux/issues/1544
>>>>>> Reported-by: Nathan Chancellor <nathan@kernel.org>
>>>>>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>>>> 
>>>>> Thanks for the patch! Maybe it's more obvious to folks who work on
>>>>> mips, but how did you determine that say `p5600` is `mips32r5` or
>>>>> `r10000` is `mips4`?
>>>> 
>>>> Wikipedia [1] should fit the purpose.
>>>> 
>>>> [1]: https://en.wikipedia.org/wiki/List_of_MIPS_architecture_processors
>>> 
>>> Mostly! Though I was not able to verify:
>>> - p5600
>> 
>> mips32r5
>> 
>>> - r5500
>> 
>> mips4
>> 
>>> - rm5200
>> 
>> mips4
>> 
>>> - sb1
>> 
>> mips64r1
> 
> Thomas, thanks for reviewing datasheets to verify this.
> 
> Jiaxun, for SB1, you have cc-option fall back to -march=mips4, does
> that need to be -march=mips64r1?

Yep, my bad, was reading the manual wrong.

Will fix in next rev.

Thanks.
- Jiaxun

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/7] MIPS: Add toolchain feature dependency for microMIPS smartMIPS
  2023-04-19 23:01     ` Nick Desaulniers
@ 2023-04-20 19:41       ` Jiaxun Yang
  2023-04-24 17:03         ` Nathan Chancellor
  0 siblings, 1 reply; 24+ messages in thread
From: Jiaxun Yang @ 2023-04-20 19:41 UTC (permalink / raw)
  To: Nick Desaulniers
  Cc: Thomas Bogendoerfer, linux-mips, llvm, Nathan Chancellor,
	Borislav Petkov, Linux Kbuild mailing list, Masahiro Yamada



> 2023年4月20日 00:01，Nick Desaulniers <ndesaulniers@google.com> 写道：
> 
> On Tue, Apr 18, 2023 at 6:13 AM Thomas Bogendoerfer
> <tsbogend@alpha.franken.de> wrote:
>> 
>> On Fri, Apr 14, 2023 at 09:06:56AM +0100, Jiaxun Yang wrote:
>>> microMIPS smartMIPS kernel can only be compiled if they are supported
>>> by toolchain.
>>> 
>>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
> 
> Question: won't the lack of this (patch and rest of the series) hurt
> our ability to test randconfig builds of ARCH=mips with clang? See
> also the 0day report from Boris:
> https://lore.kernel.org/llvm/202304170748.Fg9VIgGd-lkp@intel.com/

Kconfig experts, Is there any way to generate warning based on Kconfig options?
So we can let users know there are something went wrong but still allow build to happen.

Thanks
- Jiaxun 

> 
> i.e. randconfig will continue to select options that can't be built yet.
> 
> -- 
> Thanks,
> ~Nick Desaulniers



^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/7] MIPS: Add toolchain feature dependency for microMIPS smartMIPS
  2023-04-20 19:41       ` Jiaxun Yang
@ 2023-04-24 17:03         ` Nathan Chancellor
  0 siblings, 0 replies; 24+ messages in thread
From: Nathan Chancellor @ 2023-04-24 17:03 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: Nick Desaulniers, Thomas Bogendoerfer, linux-mips, llvm,
	Borislav Petkov, Linux Kbuild mailing list, Masahiro Yamada

On Thu, Apr 20, 2023 at 08:41:07PM +0100, Jiaxun Yang wrote:
> 
> 
> > 2023年4月20日 00:01，Nick Desaulniers <ndesaulniers@google.com> 写道：
> > 
> > On Tue, Apr 18, 2023 at 6:13 AM Thomas Bogendoerfer
> > <tsbogend@alpha.franken.de> wrote:
> >> 
> >> On Fri, Apr 14, 2023 at 09:06:56AM +0100, Jiaxun Yang wrote:
> >>> microMIPS smartMIPS kernel can only be compiled if they are supported
> >>> by toolchain.
> >>> 
> >>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >>> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
> > 
> > Question: won't the lack of this (patch and rest of the series) hurt
> > our ability to test randconfig builds of ARCH=mips with clang? See
> > also the 0day report from Boris:
> > https://lore.kernel.org/llvm/202304170748.Fg9VIgGd-lkp@intel.com/
> 
> Kconfig experts, Is there any way to generate warning based on Kconfig options?
> So we can let users know there are something went wrong but still allow build to happen.

I do not think there is a way that this can be done within Kconfig
itself but you could do something like arch/x86/Makefile does for
RETPOLINE during archprepare and warn when an option is selected without
a dependency. I envision something like the following but it has not
even been compile tested:

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 04e46ec24319..2c3be65ce3cc 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -399,6 +399,11 @@ ifdef CONFIG_MIPS32_O32
 	@$(kecho) '  Checking missing-syscalls for O32'
 	$(Q)$(MAKE) $(build)=. missing-syscalls missing_syscalls_flags="-mabi=32"
 endif
+ifdef CONFIG_CPU_HAS_SMARTMIPS
+ifndef CC_HAS_SMARTMIPS
+	$(warning CONFIG_CPU_HAS_SMARTMIPS selected without supported compiler, build may not work)
+endif
+endif
 
 install:
 	$(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)

You could also make that depend on !CONFIG_COMPILE_TEST, as that is a
signal that the user does not intend to run this kernel.

Masahiro might have other comments.

Cheers,
Nathan

^ permalink raw reply related	[flat|nested] 24+ messages in thread
end of thread, other threads:[~2023-04-24 17:03 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-14  8:06 [PATCH v2 0/7] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
2023-04-14  8:06 ` [PATCH v2 1/7] MIPS: Move various toolchain ASE check to Kconfig Jiaxun Yang
2023-04-14  8:06 ` [PATCH v2 2/7] MIPS: Add toolchain feature dependency for microMIPS smartMIPS Jiaxun Yang
2023-04-18 13:08   ` Thomas Bogendoerfer
2023-04-19 23:01     ` Nick Desaulniers
2023-04-20 19:41       ` Jiaxun Yang
2023-04-24 17:03         ` Nathan Chancellor
2023-04-14  8:06 ` [PATCH v2 3/7] MIPS: Detect toolchain support of workarounds in Kconfig Jiaxun Yang
2023-04-18 13:09   ` Thomas Bogendoerfer
2023-04-18 17:14     ` Jiaxun Yang
2023-04-14  8:06 ` [PATCH v2 4/7] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU Jiaxun Yang
2023-04-14  8:06 ` [PATCH v2 5/7] MIPS: Remove cc-option checks for -march=octeon Jiaxun Yang
2023-04-14  8:07 ` [PATCH v2 6/7] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported Jiaxun Yang
2023-04-18 20:07   ` Nick Desaulniers
2023-04-19 16:50     ` Jiaxun Yang
2023-04-19 21:35       ` Nick Desaulniers
2023-04-19 22:15         ` Thomas Bogendoerfer
2023-04-19 23:36           ` Jiaxun Yang
2023-04-20  8:06             ` Thomas Bogendoerfer
2023-04-20 16:32           ` Nick Desaulniers
2023-04-20 18:42             ` Xi Ruoyao
2023-04-20 18:50               ` Xi Ruoyao
2023-04-20 19:16             ` Jiaxun Yang
2023-04-14  8:07 ` [PATCH v2 7/7] MIPS: Limit MIPS_MT_SMP support by ISA reversion Jiaxun Yang

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.