* [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe
@ 2023-04-17 15:35 Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 01/10] lib/xe_ioctl: Add missing header for direct resolving Zbigniew Kempczyński
` (11 more replies)
0 siblings, 12 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:35 UTC (permalink / raw)
To: igt-dev
Series touches intel-bb + intel-buf which are rendercopy, gpgpu fill and
media fill facilities. Exercise both paths on CI (i915 and xe) to check
there's no regression in common part.
Zbigniew Kempczyński (10):
lib/xe_ioctl: Add missing header for direct resolving
lib/xe_query: Add region helpers and missing doc
lib/xe_query: Remove commented out function prototype
lib/intel_allocator: Add allocator support for Xe
lib/intel_bufops: Add Xe support in bufops
lib/intel_batchbuffer: Add Xe support in intel-bb
tests/xe_intel_bb: Check if intel-bb Xe support correctness
tests/xe-fast-feedback: Add xe_intel_bb test to BAT
lib/gpgpu_fill: Use RENDER engine flag to work on Xe
tests/xe_gpgpu_fill: Exercise gpgpu fill on Xe
lib/gpgpu_fill.c | 4 +-
lib/gpu_cmds.c | 2 +-
lib/intel_allocator.c | 51 +-
lib/intel_aux_pgtable.c | 2 +-
lib/intel_batchbuffer.c | 430 ++++++--
lib/intel_batchbuffer.h | 28 +-
lib/intel_bufops.c | 73 +-
lib/intel_bufops.h | 13 +-
lib/xe/xe_ioctl.h | 1 +
lib/xe/xe_query.c | 45 +
lib/xe/xe_query.h | 3 +-
tests/i915/gem_caching.c | 4 +-
tests/i915/gem_pxp.c | 2 +-
tests/intel-ci/xe-fast-feedback.testlist | 19 +
tests/meson.build | 2 +
tests/xe/xe_gpgpu_fill.c | 133 +++
tests/xe/xe_intel_bb.c | 1181 ++++++++++++++++++++++
17 files changed, 1851 insertions(+), 142 deletions(-)
create mode 100644 tests/xe/xe_gpgpu_fill.c
create mode 100644 tests/xe/xe_intel_bb.c
--
2.34.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 01/10] lib/xe_ioctl: Add missing header for direct resolving
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
@ 2023-04-17 15:35 ` Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 02/10] lib/xe_query: Add region helpers and missing doc Zbigniew Kempczyński
` (10 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:35 UTC (permalink / raw)
To: igt-dev
xe_ioctl.h user expects all types resolving. Add missing stddef.h
header which contains size_t definition.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
lib/xe/xe_ioctl.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index d8c40eda01..049cd183d6 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -11,6 +11,7 @@
#ifndef XE_IOCTL_H
#define XE_IOCTL_H
+#include <stddef.h>
#include <stdint.h>
#include <xe_drm.h>
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 02/10] lib/xe_query: Add region helpers and missing doc
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 01/10] lib/xe_ioctl: Add missing header for direct resolving Zbigniew Kempczyński
@ 2023-04-17 15:35 ` Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 03/10] lib/xe_query: Remove commented out function prototype Zbigniew Kempczyński
` (9 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:35 UTC (permalink / raw)
To: igt-dev
For easier iterate over memory regions and produce dynamic subtests
add xe_region_name() helper.
As Xe requires buffer size alignment during creating bo add
xe_min_page_size() helper.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
lib/xe/xe_query.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
lib/xe/xe_query.h | 2 ++
2 files changed, 47 insertions(+)
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 2b627a78ac..bd5eb1d189 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -422,6 +422,13 @@ struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx)
return &xe_dev->hw_engines[idx];
}
+/**
+ * xe_mem_region:
+ * @fd: xe device fd
+ * @region: region mask
+ *
+ * Returns memory region structure for @region mask.
+ */
struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region)
{
struct xe_device *xe_dev;
@@ -434,6 +441,44 @@ struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region)
return &xe_dev->mem_usage->regions[region_idx];
}
+/**
+ * xe_region_name:
+ * @region: region mask
+ *
+ * Returns region string like "system" or "vram-n" where n=0...62.
+ */
+const char *xe_region_name(uint64_t region)
+{
+ static char **vrams;
+ int region_idx = ffs(region) - 1;
+
+ /* Populate the array */
+ if (!vrams) {
+ vrams = calloc(64, sizeof(char *));
+ for (int i = 0; i < 64; i++) {
+ if (i != 0)
+ asprintf(&vrams[i], "vram-%d", i - 1);
+ else
+ asprintf(&vrams[i], "system");
+ igt_assert(vrams[i]);
+ }
+ }
+
+ return vrams[region_idx];
+}
+
+/**
+ * xe_min_page_size:
+ * @fd: xe device fd
+ * @region: region mask
+ *
+ * Returns minimum page size for @region.
+ */
+uint32_t xe_min_page_size(int fd, uint64_t region)
+{
+ return xe_mem_region(fd, region)->min_page_size;
+}
+
/**
* xe_number_hw_engine:
* @fd: xe device fd
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 0d4b810a10..f49acb1d7b 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -84,6 +84,8 @@ uint64_t vram_if_possible(int fd, int gt);
struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);
+const char *xe_region_name(uint64_t region);
+uint32_t xe_min_page_size(int fd, uint64_t region);
unsigned int xe_number_hw_engines(int fd);
bool xe_has_vram(int fd);
//uint64_t xe_vram_size(int fd);
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 03/10] lib/xe_query: Remove commented out function prototype
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 01/10] lib/xe_ioctl: Add missing header for direct resolving Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 02/10] lib/xe_query: Add region helpers and missing doc Zbigniew Kempczyński
@ 2023-04-17 15:35 ` Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 04/10] lib/intel_allocator: Add allocator support for Xe Zbigniew Kempczyński
` (8 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:35 UTC (permalink / raw)
To: igt-dev
Remove unnecessary commented out code.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
lib/xe/xe_query.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index f49acb1d7b..cc6e7cefdc 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -88,7 +88,6 @@ const char *xe_region_name(uint64_t region);
uint32_t xe_min_page_size(int fd, uint64_t region);
unsigned int xe_number_hw_engines(int fd);
bool xe_has_vram(int fd);
-//uint64_t xe_vram_size(int fd);
uint64_t xe_vram_size(int fd, int gt);
uint32_t xe_get_default_alignment(int fd);
uint32_t xe_va_bits(int fd);
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 04/10] lib/intel_allocator: Add allocator support for Xe
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
` (2 preceding siblings ...)
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 03/10] lib/xe_query: Remove commented out function prototype Zbigniew Kempczyński
@ 2023-04-17 15:35 ` Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 05/10] lib/intel_bufops: Add Xe support in bufops Zbigniew Kempczyński
` (7 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:35 UTC (permalink / raw)
To: igt-dev
Start supporting va range configuration for xe allocator.
During opening allocator has to be aware of vm range (start and end).
i915 driver doesn't expose vm range information so those variables
have to be detected. In xe driver we get information of va size from
the kernel query so va end can be directly configured. At the moment
there's no autodetection of va start for xe what might need to be
address in the future if due some reason lower offsets might not be
in use.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
lib/intel_allocator.c | 51 ++++++++++++++++++++++++++-----------------
1 file changed, 31 insertions(+), 20 deletions(-)
diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c
index 2b08dd5996..50d4819a2e 100644
--- a/lib/intel_allocator.c
+++ b/lib/intel_allocator.c
@@ -16,6 +16,7 @@
#include "igt_map.h"
#include "intel_allocator.h"
#include "intel_allocator_msgchannel.h"
+#include "xe/xe_query.h"
//#define ALLOCDBG
#ifdef ALLOCDBG
@@ -597,7 +598,7 @@ static int handle_request(struct alloc_req *req, struct alloc_resp *resp)
break;
case REQ_ALLOC:
- if (!req->alloc.alignment)
+ if (!req->alloc.alignment || req->alloc.alignment < ial->default_alignment)
req->alloc.alignment = ial->default_alignment;
resp->response_type = RESP_ALLOC;
@@ -910,24 +911,33 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx,
struct alloc_resp resp;
uint64_t gtt_size;
- if (!start)
- req.open.start = gem_detect_safe_start_offset(fd);
+ if (is_i915_device(fd)) {
+ if (!start)
+ req.open.start = gem_detect_safe_start_offset(fd);
- if (!end) {
- igt_assert_f(can_report_gtt_size(fd), "Invalid fd\n");
- gtt_size = gem_aperture_size(fd);
- if (!gem_uses_full_ppgtt(fd))
- gtt_size /= 2;
- else
- gtt_size -= RESERVED;
+ if (!end) {
+ igt_assert_f(can_report_gtt_size(fd), "Invalid fd\n");
+ gtt_size = gem_aperture_size(fd);
+ if (!gem_uses_full_ppgtt(fd))
+ gtt_size /= 2;
+ else
+ gtt_size -= RESERVED;
- req.open.end = gtt_size;
- }
+ req.open.end = gtt_size;
+ }
+
+ if (!default_alignment)
+ req.open.default_alignment = gem_detect_safe_alignment(fd);
+
+ req.open.start = ALIGN(req.open.start, req.open.default_alignment);
+ } else {
+ struct xe_device *xe_dev = xe_device_get(fd);
- if (!default_alignment)
- req.open.default_alignment = gem_detect_safe_alignment(fd);
+ igt_assert(xe_dev);
- req.open.start = ALIGN(req.open.start, req.open.default_alignment);
+ if (!end)
+ req.open.end = 1ull << xe_dev->va_bits;
+ }
/* Get child_tid only once at open() */
if (child_tid == -1)
@@ -991,6 +1001,7 @@ uint64_t intel_allocator_open_vm_full(int fd, uint32_t vm,
uint64_t default_alignment)
{
igt_assert(vm != 0);
+
return __intel_allocator_open_full(fd, 0, vm, start, end,
allocator_type, strategy,
default_alignment);
@@ -998,7 +1009,7 @@ uint64_t intel_allocator_open_vm_full(int fd, uint32_t vm,
/**
* intel_allocator_open:
- * @fd: i915 descriptor
+ * @fd: i915 or xe descriptor
* @ctx: context
* @allocator_type: one of INTEL_ALLOCATOR_* define
*
@@ -1014,14 +1025,14 @@ uint64_t intel_allocator_open_vm_full(int fd, uint32_t vm,
*/
uint64_t intel_allocator_open(int fd, uint32_t ctx, uint8_t allocator_type)
{
- return intel_allocator_open_full(fd, ctx, 0, 0, allocator_type,
- ALLOC_STRATEGY_HIGH_TO_LOW, 0);
+ return __intel_allocator_open_full(fd, ctx, 0, 0, 0, allocator_type,
+ ALLOC_STRATEGY_HIGH_TO_LOW, 0);
}
uint64_t intel_allocator_open_vm(int fd, uint32_t vm, uint8_t allocator_type)
{
- return intel_allocator_open_vm_full(fd, vm, 0, 0, allocator_type,
- ALLOC_STRATEGY_HIGH_TO_LOW, 0);
+ return __intel_allocator_open_full(fd, 0, vm, 0, 0, allocator_type,
+ ALLOC_STRATEGY_HIGH_TO_LOW, 0);
}
uint64_t intel_allocator_open_vm_as(uint64_t allocator_handle, uint32_t new_vm)
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 05/10] lib/intel_bufops: Add Xe support in bufops
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
` (3 preceding siblings ...)
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 04/10] lib/intel_allocator: Add allocator support for Xe Zbigniew Kempczyński
@ 2023-04-17 15:35 ` Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 06/10] lib/intel_batchbuffer: Add Xe support in intel-bb Zbigniew Kempczyński
` (6 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:35 UTC (permalink / raw)
To: igt-dev
Extend bufops to support Xe:
- change region to 64bit region mask,
- add initialization helper (full) which allows passing handle,
size and region,
- mapping functions (read + write) selects driver specific mapping
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
lib/intel_bufops.c | 73 ++++++++++++++++++++++++++++++++++++++++++----
lib/intel_bufops.h | 13 ++++++++-
2 files changed, 80 insertions(+), 6 deletions(-)
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index cdc7a1698b..3307f30ee3 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -26,6 +26,8 @@
#include <cairo.h>
#include "i915/gem_create.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
#include "igt.h"
#include "igt_x86.h"
#include "intel_bufops.h"
@@ -488,6 +490,9 @@ static void *mmap_write(int fd, struct intel_buf *buf)
{
void *map = NULL;
+ if (is_xe_device(fd))
+ return xe_bo_map(fd, buf->handle, buf->surface[0].size);
+
if (gem_has_lmem(fd)) {
/*
* set/get_caching and set_domain are no longer supported on
@@ -530,6 +535,9 @@ static void *mmap_read(int fd, struct intel_buf *buf)
{
void *map = NULL;
+ if (is_xe_device(fd))
+ return xe_bo_map(fd, buf->handle, buf->surface[0].size);
+
if (gem_has_lmem(fd)) {
/*
* set/get_caching and set_domain are no longer supported on
@@ -809,7 +817,7 @@ static void __intel_buf_init(struct buf_ops *bops,
int width, int height, int bpp, int alignment,
uint32_t req_tiling, uint32_t compression,
uint64_t bo_size, int bo_stride,
- uint32_t region)
+ uint64_t region)
{
uint32_t tiling = req_tiling;
uint64_t size;
@@ -899,9 +907,17 @@ static void __intel_buf_init(struct buf_ops *bops,
buf->size = size;
buf->handle = handle;
- if (!handle)
- if (__gem_create_in_memory_regions(bops->fd, &buf->handle, &size, region))
- igt_assert_eq(__gem_create(bops->fd, &size, &buf->handle), 0);
+ if (!handle) {
+ if (is_i915_device(bops->fd)) {
+ if (__gem_create_in_memory_regions(bops->fd, &buf->handle, &size, region))
+ igt_assert_eq(__gem_create(bops->fd, &size, &buf->handle), 0);
+ } else {
+ region = vram_if_possible(bops->fd, 0);
+ size = ALIGN(size, xe_get_default_alignment(bops->fd));
+ buf->handle = xe_bo_create_flags(bops->fd, 0, size, region);
+ }
+ }
+ buf->region = region;
/* Store gem bo size */
buf->bo_size = size;
@@ -945,7 +961,7 @@ void intel_buf_init_in_region(struct buf_ops *bops,
struct intel_buf *buf,
int width, int height, int bpp, int alignment,
uint32_t tiling, uint32_t compression,
- uint32_t region)
+ uint64_t region)
{
__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
tiling, compression, 0, 0, region);
@@ -1010,6 +1026,41 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
req_tiling, compression, 0, 0, -1);
}
+/**
+ * intel_buf_init_full
+ * @bops: pointer to buf_ops
+ * @handle: BO handle created by the caller
+ * @buf: pointer to intel_buf structure to be filled
+ * @width: surface width
+ * @height: surface height
+ * @bpp: bits-per-pixel (8 / 16 / 32 / 64)
+ * @alignment: alignment of the stride for linear surfaces
+ * @req_tiling: surface tiling
+ * @compression: surface compression type
+ * @size: size
+ * @region: region
+ *
+ * Function configures BO handle within intel_buf structure passed by the caller
+ * (with all its metadata - width, height, ...). Useful if BO was created
+ * outside. Allows passing real size which caller is aware of.
+ *
+ * Note: intel_buf_close() can be used because intel_buf is aware it is not
+ * buffer owner so it won't close it underneath.
+ */
+void intel_buf_init_full(struct buf_ops *bops,
+ uint32_t handle,
+ struct intel_buf *buf,
+ int width, int height,
+ int bpp, int alignment,
+ uint32_t req_tiling,
+ uint32_t compression,
+ uint64_t size,
+ uint64_t region)
+{
+ __intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
+ req_tiling, compression, size, 0, region);
+}
+
/**
* intel_buf_create
* @bops: pointer to buf_ops
@@ -1423,6 +1474,18 @@ static struct buf_ops *__buf_ops_create(int fd, bool check_idempotency)
igt_debug("generation: %d, supported tiles: 0x%02x\n",
bops->intel_gen, bops->supported_tiles);
+ /* No tiling support in XE. */
+ if (is_xe_device(fd)) {
+ bops->supported_hw_tiles = TILE_NONE;
+
+ bops->linear_to_x = copy_linear_to_x;
+ bops->x_to_linear = copy_x_to_linear;
+ bops->linear_to_y = copy_linear_to_y;
+ bops->y_to_linear = copy_y_to_linear;
+
+ return bops;
+ }
+
/*
* Warning!
*
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 25b4307399..0b6e025ca3 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -43,6 +43,7 @@ struct intel_buf {
} addr;
uint64_t bo_size;
+ uint64_t region;
/* Tracking */
struct intel_bb *ibb;
@@ -135,7 +136,7 @@ void intel_buf_init_in_region(struct buf_ops *bops,
struct intel_buf *buf,
int width, int height, int bpp, int alignment,
uint32_t tiling, uint32_t compression,
- uint32_t region);
+ uint64_t region);
void intel_buf_close(struct buf_ops *bops, struct intel_buf *buf);
void intel_buf_init_using_handle(struct buf_ops *bops,
@@ -143,6 +144,15 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
struct intel_buf *buf,
int width, int height, int bpp, int alignment,
uint32_t req_tiling, uint32_t compression);
+void intel_buf_init_full(struct buf_ops *bops,
+ uint32_t handle,
+ struct intel_buf *buf,
+ int width, int height,
+ int bpp, int alignment,
+ uint32_t req_tiling,
+ uint32_t compression,
+ uint64_t size,
+ uint64_t region);
struct intel_buf *intel_buf_create(struct buf_ops *bops,
int width, int height,
@@ -164,6 +174,7 @@ struct intel_buf *intel_buf_create_using_handle_and_size(struct buf_ops *bops,
uint32_t compression,
uint64_t size,
int stride);
+
void intel_buf_destroy(struct intel_buf *buf);
static inline void intel_buf_set_pxp(struct intel_buf *buf, bool new_pxp_state)
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 06/10] lib/intel_batchbuffer: Add Xe support in intel-bb
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
` (4 preceding siblings ...)
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 05/10] lib/intel_bufops: Add Xe support in bufops Zbigniew Kempczyński
@ 2023-04-17 15:35 ` Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 07/10] tests/xe_intel_bb: Check if intel-bb Xe support correctness Zbigniew Kempczyński
` (5 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:35 UTC (permalink / raw)
To: igt-dev
Intention of creating intel-bb was to replace libdrm for i915.
Due to many code relies on it (kms for example) most rational way
is to extend and add Xe path to it.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
lib/gpu_cmds.c | 2 +-
lib/intel_aux_pgtable.c | 2 +-
lib/intel_batchbuffer.c | 430 ++++++++++++++++++++++++++++++---------
lib/intel_batchbuffer.h | 28 ++-
tests/i915/gem_caching.c | 4 +-
tests/i915/gem_pxp.c | 2 +-
6 files changed, 355 insertions(+), 113 deletions(-)
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index cee81555d8..afb26d2990 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -251,7 +251,7 @@ gen7_fill_binding_table(struct intel_bb *ibb,
{
uint32_t binding_table_offset;
uint32_t *binding_table;
- uint32_t devid = intel_get_drm_devid(ibb->i915);
+ uint32_t devid = intel_get_drm_devid(ibb->fd);
intel_bb_ptr_align(ibb, 64);
binding_table_offset = intel_bb_offset(ibb);
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index 5205687080..946ca60b97 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -481,7 +481,7 @@ intel_aux_pgtable_create(struct intel_bb *ibb,
intel_bb_add_intel_buf_with_alignment(ibb, pgt->buf,
pgt->max_align, false);
- pgt_map(ibb->i915, pgt);
+ pgt_map(ibb->fd, pgt);
pgt_populate_entries(pgt, bufs, buf_count);
pgt_unmap(pgt);
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index a4eb4c2bbc..47ab579daa 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -29,6 +29,8 @@
#include <glib.h>
#include "i915/gem_create.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
#include "intel_batchbuffer.h"
#include "intel_bufops.h"
#include "intel_chipset.h"
@@ -38,6 +40,9 @@
#include "veboxcopy.h"
#include "sw_sync.h"
#include "gpgpu_fill.h"
+#include "igt_aux.h"
+#include "igt_syncobj.h"
+#include "i830_reg.h"
#include "huc_copy.h"
#include "i915/i915_blt.h"
@@ -828,21 +833,22 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
/**
* __intel_bb_create:
- * @i915: drm fd
+ * @fd: drm fd - i915 or xe
* @ctx: context id
- * @cfg: intel_ctx configuration, NULL for default context or legacy mode
+ * @cfg: for i915 intel_ctx configuration, NULL for default context or legacy mode,
+ * unused for xe
* @size: size of the batchbuffer
* @do_relocs: use relocations or allocator
* @allocator_type: allocator type, must be INTEL_ALLOCATOR_NONE for relocations
*
* intel-bb assumes it will work in one of two modes - with relocations or
- * with using allocator (currently RANDOM and SIMPLE are implemented).
+ * with using allocator (currently RELOC and SIMPLE are implemented).
* Some description is required to describe how they maintain the addresses.
*
* Before entering into each scenarios generic rule is intel-bb keeps objects
* and their offsets in the internal cache and reuses in subsequent execs.
*
- * 1. intel-bb with relocations
+ * 1. intel-bb with relocations (i915 only)
*
* Creating new intel-bb adds handle to cache implicitly and sets its address
* to 0. Objects added to intel-bb later also have address 0 set for first run.
@@ -850,14 +856,15 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
* works in reloc mode addresses are only suggestion to the driver and we
* cannot be sure they won't change at next exec.
*
- * 2. with allocator
+ * 2. with allocator (i915 or xe)
*
* This mode is valid only for ppgtt. Addresses are acquired from allocator
- * and softpinned. intel-bb cache must be then coherent with allocator
- * (simple is coherent, random is not due to fact we don't keep its state).
+ * and softpinned (i915) or vm-binded (xe). intel-bb cache must be then
+ * coherent with allocator (simple is coherent, reloc partially [doesn't
+ * support address reservation]).
* When we do intel-bb reset with purging cache it has to reacquire addresses
* from allocator (allocator should return same address - what is true for
- * simple allocator and false for random as mentioned before).
+ * simple and reloc allocators).
*
* If we do reset without purging caches we use addresses from intel-bb cache
* during execbuf objects construction.
@@ -873,7 +880,7 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
* Pointer the intel_bb, asserts on failure.
*/
static struct intel_bb *
-__intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
+__intel_bb_create(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
uint32_t size, bool do_relocs,
uint64_t start, uint64_t end,
uint8_t allocator_type, enum allocator_strategy strategy)
@@ -883,48 +890,86 @@ __intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
igt_assert(ibb);
- ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
- ibb->devid = intel_get_drm_devid(i915);
+ ibb->devid = intel_get_drm_devid(fd);
ibb->gen = intel_gen(ibb->devid);
+ ibb->ctx = ctx;
+
+ ibb->fd = fd;
+ ibb->driver = is_i915_device(fd) ? INTEL_DRIVER_I915 :
+ is_xe_device(fd) ? INTEL_DRIVER_XE : 0;
+ igt_assert(ibb->driver);
/*
* If we don't have full ppgtt driver can change our addresses
* so allocator is useless in this case. Just enforce relocations
* for such gens and don't use allocator at all.
*/
- if (!ibb->uses_full_ppgtt)
- do_relocs = true;
+ if (ibb->driver == INTEL_DRIVER_I915) {
+ ibb->uses_full_ppgtt = gem_uses_full_ppgtt(fd);
- /*
- * For softpin mode allocator has full control over offsets allocation
- * so we want kernel to not interfere with this.
- */
- if (do_relocs)
- ibb->allows_obj_alignment = gem_allows_obj_alignment(i915);
+ if (!ibb->uses_full_ppgtt)
+ do_relocs = true;
- /* Use safe start offset instead assuming 0x0 is safe */
- start = max_t(uint64_t, start, gem_detect_safe_start_offset(i915));
+ /*
+ * For softpin mode allocator has full control over offsets allocation
+ * so we want kernel to not interfere with this.
+ */
+ if (do_relocs) {
+ ibb->allows_obj_alignment = gem_allows_obj_alignment(fd);
+ allocator_type = INTEL_ALLOCATOR_NONE;
+ } else {
+ /* if relocs are set we won't use an allocator */
+ ibb->allocator_handle =
+ intel_allocator_open_full(fd, ctx,
+ start, end,
+ allocator_type,
+ strategy, 0);
+ }
+
+ /* Use safe start offset instead assuming 0x0 is safe */
+ start = max_t(uint64_t, start, gem_detect_safe_start_offset(fd));
+
+ ibb->vm_id = 0;
+ } else {
+ igt_assert(!do_relocs);
+
+ if (!ctx)
+ ctx = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+
+ ibb->uses_full_ppgtt = 1;
+ ibb->allocator_handle =
+ intel_allocator_open_full(fd, ctx, start, end,
+ allocator_type,
+ strategy,
+ xe_get_default_alignment(fd));
+ ibb->vm_id = ctx;
+ ibb->last_engine = ~0U;
+ }
- /* if relocs are set we won't use an allocator */
- if (do_relocs)
- allocator_type = INTEL_ALLOCATOR_NONE;
- else
- ibb->allocator_handle = intel_allocator_open_full(i915, ctx,
- start, end,
- allocator_type,
- strategy, 0);
ibb->allocator_type = allocator_type;
ibb->allocator_strategy = strategy;
ibb->allocator_start = start;
ibb->allocator_end = end;
- ibb->i915 = i915;
ibb->enforce_relocs = do_relocs;
- ibb->handle = gem_create(i915, size);
+ igt_assert(ibb->driver == INTEL_DRIVER_I915 ||
+ (ibb->driver == INTEL_DRIVER_XE && !do_relocs));
+
+ if (ibb->driver == INTEL_DRIVER_I915) {
+ ibb->handle = gem_create(fd, size);
+ ibb->alignment = gem_detect_safe_alignment(fd);
+ ibb->gtt_size = gem_aperture_size(fd);
+ } else {
+ ibb->alignment = xe_get_default_alignment(fd);
+ size = ALIGN(size, ibb->alignment);
+ ibb->handle = xe_bo_create_flags(fd, 0, size,
+ xe_has_vram(fd) ?
+ vram_memory(fd, 0) :
+ system_memory(fd));
+ ibb->gtt_size = 1ull << xe_va_bits(fd);
+ }
+
ibb->size = size;
- ibb->alignment = gem_detect_safe_alignment(i915);
- ibb->ctx = ctx;
- ibb->vm_id = 0;
ibb->batch = calloc(1, size);
igt_assert(ibb->batch);
ibb->ptr = ibb->batch;
@@ -937,7 +982,6 @@ __intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
memcpy(ibb->cfg, cfg, sizeof(*cfg));
}
- ibb->gtt_size = gem_aperture_size(i915);
if ((ibb->gtt_size - 1) >> 32)
ibb->supports_48b_address = true;
@@ -961,13 +1005,13 @@ __intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
/**
* intel_bb_create_full:
- * @i915: drm fd
+ * @fd: drm fd - i915 or xe
* @ctx: context
* @cfg: intel_ctx configuration, NULL for default context or legacy mode
* @size: size of the batchbuffer
* @start: allocator vm start address
* @end: allocator vm start address
- * @allocator_type: allocator type, SIMPLE, RANDOM, ...
+ * @allocator_type: allocator type, SIMPLE, RELOC, ...
* @strategy: allocation strategy
*
* Creates bb with context passed in @ctx, size in @size and allocator type
@@ -980,19 +1024,19 @@ __intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
*
* Pointer the intel_bb, asserts on failure.
*/
-struct intel_bb *intel_bb_create_full(int i915, uint32_t ctx,
+struct intel_bb *intel_bb_create_full(int fd, uint32_t ctx,
const intel_ctx_cfg_t *cfg, uint32_t size,
uint64_t start, uint64_t end,
uint8_t allocator_type,
enum allocator_strategy strategy)
{
- return __intel_bb_create(i915, ctx, cfg, size, false, start, end,
+ return __intel_bb_create(fd, ctx, cfg, size, false, start, end,
allocator_type, strategy);
}
/**
* intel_bb_create_with_allocator:
- * @i915: drm fd
+ * @fd: drm fd - i915 or xe
* @ctx: context
* @cfg: intel_ctx configuration, NULL for default context or legacy mode
* @size: size of the batchbuffer
@@ -1006,18 +1050,18 @@ struct intel_bb *intel_bb_create_full(int i915, uint32_t ctx,
*
* Pointer the intel_bb, asserts on failure.
*/
-struct intel_bb *intel_bb_create_with_allocator(int i915, uint32_t ctx,
+struct intel_bb *intel_bb_create_with_allocator(int fd, uint32_t ctx,
const intel_ctx_cfg_t *cfg,
uint32_t size,
uint8_t allocator_type)
{
- return __intel_bb_create(i915, ctx, cfg, size, false, 0, 0,
+ return __intel_bb_create(fd, ctx, cfg, size, false, 0, 0,
allocator_type, ALLOC_STRATEGY_HIGH_TO_LOW);
}
-static bool aux_needs_softpin(int i915)
+static bool aux_needs_softpin(int fd)
{
- return intel_gen(intel_get_drm_devid(i915)) >= 12;
+ return intel_gen(intel_get_drm_devid(fd)) >= 12;
}
static bool has_ctx_cfg(struct intel_bb *ibb)
@@ -1027,7 +1071,7 @@ static bool has_ctx_cfg(struct intel_bb *ibb)
/**
* intel_bb_create:
- * @i915: drm fd
+ * @fd: drm fd - i915 or xe
* @size: size of the batchbuffer
*
* Creates bb with default context.
@@ -1045,19 +1089,19 @@ static bool has_ctx_cfg(struct intel_bb *ibb)
* connection to it inside intel_bb is not valid anymore.
* Trying to use it leads to catastrofic errors.
*/
-struct intel_bb *intel_bb_create(int i915, uint32_t size)
+struct intel_bb *intel_bb_create(int fd, uint32_t size)
{
- bool relocs = gem_has_relocations(i915);
+ bool relocs = is_i915_device(fd) && gem_has_relocations(fd);
- return __intel_bb_create(i915, 0, NULL, size,
- relocs && !aux_needs_softpin(i915), 0, 0,
+ return __intel_bb_create(fd, 0, NULL, size,
+ relocs && !aux_needs_softpin(fd), 0, 0,
INTEL_ALLOCATOR_SIMPLE,
ALLOC_STRATEGY_HIGH_TO_LOW);
}
/**
* intel_bb_create_with_context:
- * @i915: drm fd
+ * @fd: drm fd - i915 or xe
* @ctx: context id
* @cfg: intel_ctx configuration, NULL for default context or legacy mode
* @size: size of the batchbuffer
@@ -1070,20 +1114,20 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
* Pointer the intel_bb, asserts on failure.
*/
struct intel_bb *
-intel_bb_create_with_context(int i915, uint32_t ctx,
+intel_bb_create_with_context(int fd, uint32_t ctx,
const intel_ctx_cfg_t *cfg, uint32_t size)
{
- bool relocs = gem_has_relocations(i915);
+ bool relocs = is_i915_device(fd) && gem_has_relocations(fd);
- return __intel_bb_create(i915, ctx, cfg, size,
- relocs && !aux_needs_softpin(i915), 0, 0,
+ return __intel_bb_create(fd, ctx, cfg, size,
+ relocs && !aux_needs_softpin(fd), 0, 0,
INTEL_ALLOCATOR_SIMPLE,
ALLOC_STRATEGY_HIGH_TO_LOW);
}
/**
* intel_bb_create_with_relocs:
- * @i915: drm fd
+ * @fd: drm fd - i915
* @size: size of the batchbuffer
*
* Creates bb which will disable passing addresses.
@@ -1093,17 +1137,17 @@ intel_bb_create_with_context(int i915, uint32_t ctx,
*
* Pointer the intel_bb, asserts on failure.
*/
-struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
+struct intel_bb *intel_bb_create_with_relocs(int fd, uint32_t size)
{
- igt_require(gem_has_relocations(i915));
+ igt_require(is_i915_device(fd) && gem_has_relocations(fd));
- return __intel_bb_create(i915, 0, NULL, size, true, 0, 0,
+ return __intel_bb_create(fd, 0, NULL, size, true, 0, 0,
INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
}
/**
* intel_bb_create_with_relocs_and_context:
- * @i915: drm fd
+ * @fd: drm fd - i915
* @ctx: context
* @cfg: intel_ctx configuration, NULL for default context or legacy mode
* @size: size of the batchbuffer
@@ -1116,19 +1160,19 @@ struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
* Pointer the intel_bb, asserts on failure.
*/
struct intel_bb *
-intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx,
+intel_bb_create_with_relocs_and_context(int fd, uint32_t ctx,
const intel_ctx_cfg_t *cfg,
uint32_t size)
{
- igt_require(gem_has_relocations(i915));
+ igt_require(is_i915_device(fd) && gem_has_relocations(fd));
- return __intel_bb_create(i915, ctx, cfg, size, true, 0, 0,
+ return __intel_bb_create(fd, ctx, cfg, size, true, 0, 0,
INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
}
/**
* intel_bb_create_no_relocs:
- * @i915: drm fd
+ * @fd: drm fd - i915 or xe
* @size: size of the batchbuffer
*
* Creates bb with disabled relocations.
@@ -1138,11 +1182,12 @@ intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx,
*
* Pointer the intel_bb, asserts on failure.
*/
-struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size)
+struct intel_bb *intel_bb_create_no_relocs(int fd, uint32_t size)
{
- igt_require(gem_uses_full_ppgtt(i915));
+ igt_require(is_xe_device(fd) ||
+ (is_i915_device(fd) && gem_uses_full_ppgtt(fd)));
- return __intel_bb_create(i915, 0, NULL, size, false, 0, 0,
+ return __intel_bb_create(fd, 0, NULL, size, false, 0, 0,
INTEL_ALLOCATOR_SIMPLE,
ALLOC_STRATEGY_HIGH_TO_LOW);
}
@@ -1217,16 +1262,80 @@ void intel_bb_destroy(struct intel_bb *ibb)
intel_allocator_free(ibb->allocator_handle, ibb->handle);
intel_allocator_close(ibb->allocator_handle);
}
- gem_close(ibb->i915, ibb->handle);
+ gem_close(ibb->fd, ibb->handle);
if (ibb->fence >= 0)
close(ibb->fence);
+ if (ibb->engine_syncobj)
+ syncobj_destroy(ibb->fd, ibb->engine_syncobj);
+ if (ibb->vm_id && !ibb->ctx)
+ xe_vm_destroy(ibb->fd, ibb->vm_id);
free(ibb->batch);
free(ibb->cfg);
free(ibb);
}
+static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(struct intel_bb *ibb,
+ uint32_t op, uint32_t region)
+{
+ struct drm_i915_gem_exec_object2 **objects = ibb->objects;
+ struct drm_xe_vm_bind_op *bind_ops, *ops;
+ bool set_obj = (op & 0xffff) == XE_VM_BIND_OP_MAP;
+
+ bind_ops = calloc(ibb->num_objects, sizeof(*bind_ops));
+ igt_assert(bind_ops);
+
+ igt_debug("bind_ops: %s\n", set_obj ? "MAP" : "UNMAP");
+ for (int i = 0; i < ibb->num_objects; i++) {
+ ops = &bind_ops[i];
+
+ if (set_obj)
+ ops->obj = objects[i]->handle;
+
+ ops->op = op;
+ ops->obj_offset = 0;
+ ops->addr = objects[i]->offset;
+ ops->range = objects[i]->rsvd1;
+ ops->region = region;
+
+ igt_debug(" [%d]: handle: %u, offset: %llx, size: %llx\n",
+ i, ops->obj, (long long)ops->addr, (long long)ops->range);
+ }
+
+ return bind_ops;
+}
+
+static void __unbind_xe_objects(struct intel_bb *ibb)
+{
+ struct drm_xe_sync syncs[2] = {
+ { .flags = DRM_XE_SYNC_SYNCOBJ },
+ { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ };
+ int ret;
+
+ syncs[0].handle = ibb->engine_syncobj;
+ syncs[1].handle = syncobj_create(ibb->fd, 0);
+
+ if (ibb->num_objects > 1) {
+ struct drm_xe_vm_bind_op *bind_ops;
+ uint32_t op = XE_VM_BIND_OP_UNMAP | XE_VM_BIND_FLAG_ASYNC;
+
+ bind_ops = xe_alloc_bind_ops(ibb, op, 0);
+ xe_vm_bind_array(ibb->fd, ibb->vm_id, 0, bind_ops,
+ ibb->num_objects, syncs, 2);
+ free(bind_ops);
+ } else {
+ xe_vm_unbind_async(ibb->fd, ibb->vm_id, 0, 0,
+ ibb->batch_offset, ibb->size, syncs, 2);
+ }
+ ret = syncobj_wait_err(ibb->fd, &syncs[1].handle, 1, INT64_MAX, 0);
+ igt_assert_eq(ret, 0);
+ syncobj_destroy(ibb->fd, syncs[1].handle);
+
+ ibb->xe_bound = false;
+}
+
/*
* intel_bb_reset:
* @ibb: pointer to intel_bb
@@ -1238,7 +1347,6 @@ void intel_bb_destroy(struct intel_bb *ibb)
* from intel-bb tracking list. Removing intel_bufs releases their addresses
* in the allocator.
*/
-
void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
{
uint32_t i;
@@ -1258,6 +1366,9 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
for (i = 0; i < ibb->num_objects; i++)
ibb->objects[i]->flags &= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ if (is_xe_device(ibb->fd) && ibb->xe_bound)
+ __unbind_xe_objects(ibb);
+
__intel_bb_destroy_relocations(ibb);
__intel_bb_destroy_objects(ibb);
__reallocate_objects(ibb);
@@ -1277,11 +1388,16 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
intel_bb_remove_object(ibb, ibb->handle, ibb->batch_offset,
ibb->size);
- gem_close(ibb->i915, ibb->handle);
- ibb->handle = gem_create(ibb->i915, ibb->size);
+ gem_close(ibb->fd, ibb->handle);
+ if (is_i915_device(ibb->fd))
+ ibb->handle = gem_create(ibb->fd, ibb->size);
+ else
+ ibb->handle = xe_bo_create_flags(ibb->fd, 0, ibb->size,
+ vram_if_possible(ibb->fd, 0));
- /* Keep address for bb in reloc mode and RANDOM allocator */
- if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE)
+ /* Reacquire offset for RELOC and SIMPLE */
+ if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE ||
+ ibb->allocator_type == INTEL_ALLOCATOR_RELOC)
ibb->batch_offset = __intel_bb_get_offset(ibb,
ibb->handle,
ibb->size,
@@ -1304,13 +1420,19 @@ int intel_bb_sync(struct intel_bb *ibb)
{
int ret;
- if (ibb->fence < 0)
+ if (ibb->fence < 0 && !ibb->engine_syncobj)
return 0;
- ret = sync_fence_wait(ibb->fence, -1);
- if (ret == 0) {
- close(ibb->fence);
- ibb->fence = -1;
+ if (ibb->fence >= 0) {
+ ret = sync_fence_wait(ibb->fence, -1);
+ if (ret == 0) {
+ close(ibb->fence);
+ ibb->fence = -1;
+ }
+ } else {
+ igt_assert_neq(ibb->engine_syncobj, 0);
+ ret = syncobj_wait_err(ibb->fd, &ibb->engine_syncobj,
+ 1, INT64_MAX, 0);
}
return ret;
@@ -1325,7 +1447,7 @@ int intel_bb_sync(struct intel_bb *ibb)
void intel_bb_print(struct intel_bb *ibb)
{
igt_info("drm fd: %d, gen: %d, devid: %u, debug: %d\n",
- ibb->i915, ibb->gen, ibb->devid, ibb->debug);
+ ibb->fd, ibb->gen, ibb->devid, ibb->debug);
igt_info("handle: %u, size: %u, batch: %p, ptr: %p\n",
ibb->handle, ibb->size, ibb->batch, ibb->ptr);
igt_info("gtt_size: %" PRIu64 ", supports 48bit: %d\n",
@@ -1350,7 +1472,7 @@ void intel_bb_dump(struct intel_bb *ibb, const char *filename)
FILE *out;
void *ptr;
- ptr = gem_mmap__device_coherent(ibb->i915, ibb->handle, 0, ibb->size,
+ ptr = gem_mmap__device_coherent(ibb->fd, ibb->handle, 0, ibb->size,
PROT_READ);
out = fopen(filename, "wb");
igt_assert(out);
@@ -1501,7 +1623,7 @@ static void __remove_from_objects(struct intel_bb *ibb,
}
/**
- * intel_bb_add_object:
+ * __intel_bb_add_object:
* @ibb: pointer to intel_bb
* @handle: which handle to add to objects array
* @size: object size
@@ -1513,9 +1635,9 @@ static void __remove_from_objects(struct intel_bb *ibb,
* in the object tree. When object is a render target it has to
* be marked with EXEC_OBJECT_WRITE flag.
*/
-struct drm_i915_gem_exec_object2 *
-intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
- uint64_t offset, uint64_t alignment, bool write)
+static struct drm_i915_gem_exec_object2 *
+__intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
+ uint64_t offset, uint64_t alignment, bool write)
{
struct drm_i915_gem_exec_object2 *object;
@@ -1523,8 +1645,12 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
|| ALIGN(offset, alignment) == offset);
igt_assert(is_power_of_two(alignment));
+ if (ibb->driver == INTEL_DRIVER_I915)
+ alignment = max_t(uint64_t, alignment, gem_detect_safe_alignment(ibb->fd));
+ else if (ibb->driver == INTEL_DRIVER_XE)
+ alignment = max_t(uint64_t, ibb->alignment, alignment);
+
object = __add_to_cache(ibb, handle);
- alignment = max_t(uint64_t, alignment, gem_detect_safe_alignment(ibb->i915));
__add_to_objects(ibb, object);
/*
@@ -1584,9 +1710,27 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
if (ibb->allows_obj_alignment)
object->alignment = alignment;
+ if (ibb->driver == INTEL_DRIVER_XE) {
+ object->alignment = alignment;
+ object->rsvd1 = size;
+ }
+
return object;
}
+struct drm_i915_gem_exec_object2 *
+intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
+ uint64_t offset, uint64_t alignment, bool write)
+{
+ struct drm_i915_gem_exec_object2 *obj = NULL;
+
+ obj = __intel_bb_add_object(ibb, handle, size, offset,
+ alignment, write);
+ igt_assert(obj);
+
+ return obj;
+}
+
bool intel_bb_remove_object(struct intel_bb *ibb, uint32_t handle,
uint64_t offset, uint64_t size)
{
@@ -1999,7 +2143,7 @@ static void intel_bb_dump_execbuf(struct intel_bb *ibb,
uint64_t address;
igt_debug("execbuf [pid: %ld, fd: %d, ctx: %u]\n",
- (long) getpid(), ibb->i915, ibb->ctx);
+ (long) getpid(), ibb->fd, ibb->ctx);
igt_debug("execbuf batch len: %u, start offset: 0x%x, "
"DR1: 0x%x, DR4: 0x%x, "
"num clip: %u, clipptr: 0x%llx, "
@@ -2135,6 +2279,83 @@ static void update_offsets(struct intel_bb *ibb,
}
#define LINELEN 76
+
+static int
+__xe_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+ uint64_t flags, bool sync)
+{
+ uint32_t engine = flags & (I915_EXEC_BSD_MASK | I915_EXEC_RING_MASK);
+ uint32_t engine_id;
+ struct drm_xe_sync syncs[2] = {
+ { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ };
+ struct drm_xe_vm_bind_op *bind_ops;
+ void *map;
+
+ igt_assert_eq(ibb->num_relocs, 0);
+ igt_assert_eq(ibb->xe_bound, false);
+
+ if (ibb->last_engine != engine) {
+ struct drm_xe_engine_class_instance inst = { };
+
+ inst.engine_instance =
+ (flags & I915_EXEC_BSD_MASK) >> I915_EXEC_BSD_SHIFT;
+
+ switch (flags & I915_EXEC_RING_MASK) {
+ case I915_EXEC_DEFAULT:
+ case I915_EXEC_BLT:
+ inst.engine_class = DRM_XE_ENGINE_CLASS_COPY;
+ break;
+ case I915_EXEC_BSD:
+ inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
+ break;
+ case I915_EXEC_RENDER:
+ inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
+ break;
+ case I915_EXEC_VEBOX:
+ inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;
+ break;
+ default:
+ igt_assert(false);
+ }
+ igt_debug("Run on %s\n", xe_engine_class_string(inst.engine_class));
+
+ ibb->engine_id = engine_id =
+ xe_engine_create(ibb->fd, ibb->vm_id, &inst, 0);
+ } else {
+ engine_id = ibb->engine_id;
+ }
+ ibb->last_engine = engine;
+
+ map = xe_bo_map(ibb->fd, ibb->handle, ibb->size);
+ memcpy(map, ibb->batch, ibb->size);
+ gem_munmap(map, ibb->size);
+
+ syncs[0].handle = syncobj_create(ibb->fd, 0);
+ if (ibb->num_objects > 1) {
+ bind_ops = xe_alloc_bind_ops(ibb, XE_VM_BIND_OP_MAP | XE_VM_BIND_FLAG_ASYNC, 0);
+ xe_vm_bind_array(ibb->fd, ibb->vm_id, 0, bind_ops,
+ ibb->num_objects, syncs, 1);
+ ibb->xe_bound = true;
+ free(bind_ops);
+ } else {
+ xe_vm_bind_async(ibb->fd, ibb->vm_id, 0, ibb->handle, 0,
+ ibb->batch_offset, ibb->size, syncs, 1);
+ }
+
+ syncs[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ ibb->engine_syncobj = syncobj_create(ibb->fd, 0);
+ syncs[1].handle = ibb->engine_syncobj;
+
+ xe_exec_sync(ibb->fd, engine_id, ibb->batch_offset, syncs, 2);
+
+ if (sync)
+ intel_bb_sync(ibb);
+
+ return 0;
+}
+
/*
* __intel_bb_exec:
* @ibb: pointer to intel_bb
@@ -2160,7 +2381,7 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
ibb->objects[0]->handle = ibb->handle;
ibb->objects[0]->offset = ibb->batch_offset;
- gem_write(ibb->i915, ibb->handle, 0, ibb->batch, ibb->size);
+ gem_write(ibb->fd, ibb->handle, 0, ibb->batch, ibb->size);
memset(&execbuf, 0, sizeof(execbuf));
objects = create_objects_array(ibb);
@@ -2173,13 +2394,10 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
execbuf.flags &= ~I915_EXEC_NO_RELOC;
execbuf.rsvd2 = 0;
- if (ibb->dump_base64)
- intel_bb_dump_base64(ibb, LINELEN);
-
/* For debugging on CI, remove in final series */
intel_bb_dump_execbuf(ibb, &execbuf);
- ret = __gem_execbuf_wr(ibb->i915, &execbuf);
+ ret = __gem_execbuf_wr(ibb->fd, &execbuf);
if (ret) {
intel_bb_dump_execbuf(ibb, &execbuf);
free(objects);
@@ -2230,7 +2448,13 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
uint64_t flags, bool sync)
{
- igt_assert_eq(__intel_bb_exec(ibb, end_offset, flags, sync), 0);
+ if (ibb->dump_base64)
+ intel_bb_dump_base64(ibb, LINELEN);
+
+ if (ibb->driver == INTEL_DRIVER_I915)
+ igt_assert_eq(__intel_bb_exec(ibb, end_offset, flags, sync), 0);
+ else
+ igt_assert_eq(__xe_bb_exec(ibb, end_offset, flags, sync), 0);
}
/**
@@ -2409,13 +2633,13 @@ uint32_t intel_bb_copy_data(struct intel_bb *ibb,
*/
void intel_bb_blit_start(struct intel_bb *ibb, uint32_t flags)
{
- if (blt_has_xy_src_copy(ibb->i915))
+ if (blt_has_xy_src_copy(ibb->fd))
intel_bb_out(ibb, XY_SRC_COPY_BLT_CMD |
XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB |
flags |
(6 + 2 * (ibb->gen >= 8)));
- else if (blt_has_fast_copy(ibb->i915))
+ else if (blt_has_fast_copy(ibb->fd))
intel_bb_out(ibb, XY_FAST_COPY_BLT | flags);
else
igt_assert_f(0, "No supported blit command found\n");
@@ -2456,9 +2680,9 @@ void intel_bb_emit_blt_copy(struct intel_bb *ibb,
if (gen >= 4 && src->tiling != I915_TILING_NONE) {
src_pitch /= 4;
- if (blt_has_xy_src_copy(ibb->i915))
+ if (blt_has_xy_src_copy(ibb->fd))
cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
- else if (blt_has_fast_copy(ibb->i915))
+ else if (blt_has_fast_copy(ibb->fd))
cmd_bits |= fast_copy_dword0(src->tiling, dst->tiling);
else
igt_assert_f(0, "No supported blit command found\n");
@@ -2466,7 +2690,7 @@ void intel_bb_emit_blt_copy(struct intel_bb *ibb,
if (gen >= 4 && dst->tiling != I915_TILING_NONE) {
dst_pitch /= 4;
- if (blt_has_xy_src_copy(ibb->i915))
+ if (blt_has_xy_src_copy(ibb->fd))
cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
else
cmd_bits |= fast_copy_dword0(src->tiling, dst->tiling);
@@ -2480,7 +2704,7 @@ void intel_bb_emit_blt_copy(struct intel_bb *ibb,
CHECK_RANGE(src_pitch); CHECK_RANGE(dst_pitch);
br13_bits = 0;
- if (blt_has_xy_src_copy(ibb->i915)) {
+ if (blt_has_xy_src_copy(ibb->fd)) {
switch (bpp) {
case 8:
break;
@@ -2496,7 +2720,7 @@ void intel_bb_emit_blt_copy(struct intel_bb *ibb,
igt_fail(IGT_EXIT_FAILURE);
}
} else {
- br13_bits = fast_copy_dword1(ibb->i915, src->tiling, dst->tiling, bpp);
+ br13_bits = fast_copy_dword1(ibb->fd, src->tiling, dst->tiling, bpp);
}
if ((src->tiling | dst->tiling) >= I915_TILING_Y) {
@@ -2628,14 +2852,20 @@ void intel_bb_track(bool do_tracking)
static void __intel_bb_reinit_alloc(struct intel_bb *ibb)
{
+ uint64_t alignment = 0;
+
if (ibb->allocator_type == INTEL_ALLOCATOR_NONE)
return;
- ibb->allocator_handle = intel_allocator_open_full(ibb->i915, ibb->ctx,
+ if (ibb->driver == INTEL_DRIVER_XE)
+ alignment = xe_get_default_alignment(ibb->fd);
+
+ ibb->allocator_handle = intel_allocator_open_full(ibb->fd, ibb->ctx,
ibb->allocator_start, ibb->allocator_end,
ibb->allocator_type,
ibb->allocator_strategy,
- 0);
+ alignment);
+
intel_bb_reset(ibb, true);
}
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 10e4126606..e2566d8223 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -235,6 +235,11 @@ struct igt_pxp {
uint32_t appid;
};
+enum intel_driver {
+ INTEL_DRIVER_I915 = 1,
+ INTEL_DRIVER_XE,
+};
+
/*
* Batchbuffer without libdrm dependency
*/
@@ -246,7 +251,9 @@ struct intel_bb {
uint8_t allocator_type;
enum allocator_strategy allocator_strategy;
- int i915;
+ enum intel_driver driver;
+ int fd;
+
unsigned int gen;
bool debug;
bool dump_base64;
@@ -268,6 +275,11 @@ struct intel_bb {
uint32_t ctx;
uint32_t vm_id;
+ bool xe_bound;
+ uint32_t engine_syncobj;
+ uint32_t engine_id;
+ uint32_t last_engine;
+
/* Context configuration */
intel_ctx_cfg_t *cfg;
@@ -299,21 +311,21 @@ struct intel_bb {
};
struct intel_bb *
-intel_bb_create_full(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
+intel_bb_create_full(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
uint32_t size, uint64_t start, uint64_t end,
uint8_t allocator_type, enum allocator_strategy strategy);
struct intel_bb *
-intel_bb_create_with_allocator(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
+intel_bb_create_with_allocator(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
uint32_t size, uint8_t allocator_type);
-struct intel_bb *intel_bb_create(int i915, uint32_t size);
+struct intel_bb *intel_bb_create(int fd, uint32_t size);
struct intel_bb *
-intel_bb_create_with_context(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
+intel_bb_create_with_context(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
uint32_t size);
-struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
+struct intel_bb *intel_bb_create_with_relocs(int fd, uint32_t size);
struct intel_bb *
-intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx,
+intel_bb_create_with_relocs_and_context(int fd, uint32_t ctx,
const intel_ctx_cfg_t *cfg, uint32_t size);
-struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size);
+struct intel_bb *intel_bb_create_no_relocs(int fd, uint32_t size);
void intel_bb_destroy(struct intel_bb *ibb);
/* make it safe to use intel_allocator after failed test */
diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
index b6ecd8346c..6e944f0acb 100644
--- a/tests/i915/gem_caching.c
+++ b/tests/i915/gem_caching.c
@@ -83,7 +83,7 @@ copy_bo(struct intel_bb *ibb, struct intel_buf *src, struct intel_buf *dst)
intel_bb_add_intel_buf(ibb, src, false);
intel_bb_add_intel_buf(ibb, dst, true);
- if (blt_has_xy_src_copy(ibb->i915)) {
+ if (blt_has_xy_src_copy(ibb->fd)) {
intel_bb_out(ibb,
XY_SRC_COPY_BLT_CMD |
XY_SRC_COPY_BLT_WRITE_ALPHA |
@@ -93,7 +93,7 @@ copy_bo(struct intel_bb *ibb, struct intel_buf *src, struct intel_buf *dst)
intel_bb_out(ibb, (3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
4096);
- } else if (blt_has_fast_copy(ibb->i915)) {
+ } else if (blt_has_fast_copy(ibb->fd)) {
intel_bb_out(ibb, XY_FAST_COPY_BLT);
intel_bb_out(ibb, XY_FAST_COPY_COLOR_DEPTH_32 | 4096);
} else {
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index af657d0e1b..2f27abd582 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -809,7 +809,7 @@ static int gem_execbuf_flush_store_dw(int i915, struct intel_bb *ibb, uint32_t c
ret = __intel_bb_exec(ibb, intel_bb_offset(ibb),
I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
if (ret == 0) {
- gem_sync(ibb->i915, fence->handle);
+ gem_sync(ibb->fd, fence->handle);
assert_pipectl_storedw_done(i915, fence->handle);
}
return ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 07/10] tests/xe_intel_bb: Check if intel-bb Xe support correctness
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
` (5 preceding siblings ...)
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 06/10] lib/intel_batchbuffer: Add Xe support in intel-bb Zbigniew Kempczyński
@ 2023-04-17 15:35 ` Zbigniew Kempczyński
2023-04-17 15:36 ` [igt-dev] [PATCH i-g-t 08/10] tests/xe-fast-feedback: Add xe_intel_bb test to BAT Zbigniew Kempczyński
` (4 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:35 UTC (permalink / raw)
To: igt-dev
As we're reusing intel-bb for Xe we need to check it behaves correctly
for buffer handling and submission.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_intel_bb.c | 1181 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 1182 insertions(+)
create mode 100644 tests/xe/xe_intel_bb.c
diff --git a/tests/meson.build b/tests/meson.build
index da31e7824b..3ec440710e 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -255,6 +255,7 @@ xe_progs = [
'xe_exec_threads',
'xe_guc_pc',
'xe_huc_copy',
+ 'xe_intel_bb',
'xe_mmap',
'xe_mmio',
'xe_module_load',
diff --git a/tests/xe/xe_intel_bb.c b/tests/xe/xe_intel_bb.c
new file mode 100644
index 0000000000..42ba09f37d
--- /dev/null
+++ b/tests/xe/xe_intel_bb.c
@@ -0,0 +1,1181 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "igt.h"
+#include "igt_crc.h"
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <cairo.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <glib.h>
+#include <zlib.h>
+#include "intel_bufops.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+/**
+ * TEST: Basic tests for intel-bb xe functionality
+ * Category: Software building block
+ * Sub-category: xe
+ * Test category: functionality test
+ */
+
+#define PAGE_SIZE 4096
+
+#define WIDTH 64
+#define HEIGHT 64
+#define STRIDE (WIDTH * 4)
+#define SIZE (HEIGHT * STRIDE)
+
+#define COLOR_00 0x00
+#define COLOR_33 0x33
+#define COLOR_77 0x77
+#define COLOR_CC 0xcc
+
+IGT_TEST_DESCRIPTION("xe_intel_bb API check.");
+
+static bool debug_bb;
+static bool write_png;
+static bool buf_info;
+static bool print_base64;
+
+static void *alloc_aligned(uint64_t size)
+{
+ void *p;
+
+ igt_assert_eq(posix_memalign(&p, 16, size), 0);
+
+ return p;
+}
+
+static void fill_buf(struct intel_buf *buf, uint8_t color)
+{
+ uint8_t *ptr;
+ int xe = buf_ops_get_fd(buf->bops);
+ int i;
+
+ ptr = xe_bo_map(xe, buf->handle, buf->surface[0].size);
+
+ for (i = 0; i < buf->surface[0].size; i++)
+ ptr[i] = color;
+
+ munmap(ptr, buf->surface[0].size);
+}
+
+static void check_buf(struct intel_buf *buf, uint8_t color)
+{
+ uint8_t *ptr;
+ int xe = buf_ops_get_fd(buf->bops);
+ int i;
+
+ ptr = xe_bo_map(xe, buf->handle, buf->surface[0].size);
+
+ for (i = 0; i < buf->surface[0].size; i++)
+ igt_assert(ptr[i] == color);
+
+ munmap(ptr, buf->surface[0].size);
+}
+
+static struct intel_buf *
+create_buf(struct buf_ops *bops, int width, int height, uint8_t color)
+{
+ struct intel_buf *buf;
+
+ buf = calloc(1, sizeof(*buf));
+ igt_assert(buf);
+
+ intel_buf_init(bops, buf, width/4, height, 32, 0, I915_TILING_NONE, 0);
+ fill_buf(buf, color);
+
+ return buf;
+}
+
+static void print_buf(struct intel_buf *buf, const char *name)
+{
+ uint8_t *ptr;
+ int xe = buf_ops_get_fd(buf->bops);
+
+ ptr = xe_bo_map(xe, buf->handle, buf->surface[0].size);
+
+ igt_debug("[%s] Buf handle: %d, size: %" PRIu64
+ ", v: 0x%02x, presumed_addr: %p\n",
+ name, buf->handle, buf->surface[0].size, ptr[0],
+ from_user_pointer(buf->addr.offset));
+ munmap(ptr, buf->surface[0].size);
+}
+
+/**
+ * SUBTEST: reset-bb
+ * Description: check bb reset
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void reset_bb(struct buf_ops *bops)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+
+ ibb = intel_bb_create(xe, PAGE_SIZE);
+ intel_bb_reset(ibb, false);
+ intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: purge-bb
+ * Description: check bb reset == full (purge)
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void purge_bb(struct buf_ops *bops)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_buf *buf;
+ struct intel_bb *ibb;
+ uint64_t offset0, offset1;
+
+ buf = intel_buf_create(bops, 512, 512, 32, 0, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+ ibb = intel_bb_create(xe, 4096);
+ intel_bb_set_debug(ibb, true);
+
+ intel_bb_add_intel_buf(ibb, buf, false);
+ offset0 = buf->addr.offset;
+
+ intel_bb_reset(ibb, true);
+ buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
+
+ intel_bb_add_intel_buf(ibb, buf, false);
+ offset1 = buf->addr.offset;
+
+ igt_assert(offset0 == offset1);
+
+ intel_buf_destroy(buf);
+ intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: simple-%s
+ * Description: Run simple bb xe %arg[1] test
+ * Run type: BAT
+ *
+ * arg[1]:
+ *
+ * @bb: bb
+ * @bb-ctx: bb-ctx
+ */
+static void simple_bb(struct buf_ops *bops, bool new_context)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ uint32_t ctx = 0;
+
+ ibb = intel_bb_create_with_allocator(xe, ctx, NULL, PAGE_SIZE,
+ INTEL_ALLOCATOR_SIMPLE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+ /* Check we're safe with reset and no double-free will occur */
+ intel_bb_reset(ibb, true);
+ intel_bb_reset(ibb, false);
+ intel_bb_reset(ibb, true);
+
+ if (new_context) {
+ ctx = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ intel_bb_destroy(ibb);
+ ibb = intel_bb_create_with_context(xe, ctx, NULL, PAGE_SIZE);
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
+ true);
+ xe_vm_destroy(xe, ctx);
+ }
+
+ intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: bb-with-allocator
+ * Description: check bb with passed allocator
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void bb_with_allocator(struct buf_ops *bops)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *dst;
+ uint32_t ctx = 0;
+
+ ibb = intel_bb_create_with_allocator(xe, ctx, NULL, PAGE_SIZE,
+ INTEL_ALLOCATOR_SIMPLE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ src = intel_buf_create(bops, 4096/32, 32, 8, 0, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+ dst = intel_buf_create(bops, 4096/32, 32, 8, 0, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+
+ intel_bb_add_intel_buf(ibb, src, false);
+ intel_bb_add_intel_buf(ibb, dst, true);
+ intel_bb_copy_intel_buf(ibb, dst, src, 4096);
+ intel_bb_remove_intel_buf(ibb, src);
+ intel_bb_remove_intel_buf(ibb, dst);
+
+ intel_buf_destroy(src);
+ intel_buf_destroy(dst);
+ intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: lot-of-buffers
+ * Description: check running bb with many buffers
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+#define NUM_BUFS 500
+static void lot_of_buffers(struct buf_ops *bops)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *buf[NUM_BUFS];
+ int i;
+
+ ibb = intel_bb_create(xe, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ for (i = 0; i < NUM_BUFS; i++) {
+ buf[i] = intel_buf_create(bops, 4096, 1, 8, 0, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+ if (i % 2)
+ intel_bb_add_intel_buf(ibb, buf[i], false);
+ else
+ intel_bb_add_intel_buf_with_alignment(ibb, buf[i],
+ 0x4000, false);
+ }
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ intel_bb_reset(ibb, false);
+
+ for (i = 0; i < NUM_BUFS; i++)
+ intel_buf_destroy(buf[i]);
+
+ intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: add-remove-objects
+ * Description: check bb object manipulation (add + remove)
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void add_remove_objects(struct buf_ops *bops)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *mid, *dst;
+ uint32_t offset;
+ const uint32_t width = 512;
+ const uint32_t height = 512;
+
+ ibb = intel_bb_create(xe, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ src = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+ mid = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+ dst = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+
+ intel_bb_add_intel_buf(ibb, src, false);
+ intel_bb_add_intel_buf(ibb, mid, true);
+ intel_bb_remove_intel_buf(ibb, mid);
+ intel_bb_remove_intel_buf(ibb, mid);
+ intel_bb_remove_intel_buf(ibb, mid);
+ intel_bb_add_intel_buf(ibb, dst, true);
+
+ offset = intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, offset,
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ intel_bb_reset(ibb, false);
+
+ intel_buf_destroy(src);
+ intel_buf_destroy(mid);
+ intel_buf_destroy(dst);
+ intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: destroy-bb
+ * Description: check bb destroy/create
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void destroy_bb(struct buf_ops *bops)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *mid, *dst;
+ uint32_t offset;
+ const uint32_t width = 512;
+ const uint32_t height = 512;
+
+ ibb = intel_bb_create(xe, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ src = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+ mid = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+ dst = intel_buf_create(bops, width, height, 32, 0,
+ I915_TILING_NONE, I915_COMPRESSION_NONE);
+
+ intel_bb_add_intel_buf(ibb, src, false);
+ intel_bb_add_intel_buf(ibb, mid, true);
+ intel_bb_add_intel_buf(ibb, dst, true);
+
+ offset = intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, offset,
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ intel_bb_reset(ibb, false);
+
+ /* Check destroy will detach intel_bufs */
+ intel_bb_destroy(ibb);
+ igt_assert(src->addr.offset == INTEL_BUF_INVALID_ADDRESS);
+ igt_assert(src->ibb == NULL);
+ igt_assert(mid->addr.offset == INTEL_BUF_INVALID_ADDRESS);
+ igt_assert(mid->ibb == NULL);
+ igt_assert(dst->addr.offset == INTEL_BUF_INVALID_ADDRESS);
+ igt_assert(dst->ibb == NULL);
+
+ ibb = intel_bb_create(xe, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ intel_bb_add_intel_buf(ibb, src, false);
+ offset = intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, offset,
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ intel_bb_reset(ibb, false);
+
+ intel_bb_destroy(ibb);
+ intel_buf_destroy(src);
+ intel_buf_destroy(mid);
+ intel_buf_destroy(dst);
+}
+
+/**
+ * SUBTEST: create-in-region
+ * Description: check size validation on available regions
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void create_in_region(struct buf_ops *bops, uint64_t region)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf buf = {};
+ uint32_t handle, offset;
+ uint64_t size;
+ int width = 64;
+ int height = 64;
+
+ ibb = intel_bb_create(xe, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ size = xe_min_page_size(xe, system_memory(xe));
+ handle = xe_bo_create_flags(xe, 0, size, system_memory(xe));
+ intel_buf_init_full(bops, handle, &buf,
+ width/4, height, 32, 0,
+ I915_TILING_NONE, 0,
+ size, region);
+ intel_buf_set_ownership(&buf, true);
+
+ intel_bb_add_intel_buf(ibb, &buf, false);
+ offset = intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, offset,
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ intel_bb_reset(ibb, false);
+
+ intel_buf_close(bops, &buf);
+ intel_bb_destroy(ibb);
+}
+
+static void __emit_blit(struct intel_bb *ibb,
+ struct intel_buf *src, struct intel_buf *dst)
+{
+ intel_bb_emit_blt_copy(ibb,
+ src, 0, 0, src->surface[0].stride,
+ dst, 0, 0, dst->surface[0].stride,
+ intel_buf_width(dst),
+ intel_buf_height(dst),
+ dst->bpp);
+}
+
+/**
+ * SUBTEST: blit-%s
+ * Description: Run blit on %arg[1] allocator
+ * Run type: BAT
+ *
+ * arg[1]:
+ *
+ * @simple: simple
+ * @reloc: reloc
+ */
+static void blit(struct buf_ops *bops, uint8_t allocator_type)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *dst;
+ uint64_t poff_src, poff_dst;
+ uint64_t flags = 0;
+
+ ibb = intel_bb_create_with_allocator(xe, 0, NULL, PAGE_SIZE,
+ allocator_type);
+ flags |= I915_EXEC_NO_RELOC;
+
+ src = create_buf(bops, WIDTH, HEIGHT, COLOR_CC);
+ dst = create_buf(bops, WIDTH, HEIGHT, COLOR_00);
+
+ if (buf_info) {
+ print_buf(src, "src");
+ print_buf(dst, "dst");
+ }
+
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ __emit_blit(ibb, src, dst);
+ intel_bb_emit_bbe(ibb);
+ intel_bb_flush_blit(ibb);
+ intel_bb_sync(ibb);
+ intel_bb_reset(ibb, false);
+ check_buf(dst, COLOR_CC);
+
+ poff_src = intel_bb_get_object_offset(ibb, src->handle);
+ poff_dst = intel_bb_get_object_offset(ibb, dst->handle);
+
+ /* Add buffers again */
+ intel_bb_add_intel_buf(ibb, src, false);
+ intel_bb_add_intel_buf(ibb, dst, true);
+
+ igt_assert_f(poff_src == src->addr.offset,
+ "prev src addr: %" PRIx64 " <> src addr %" PRIx64 "\n",
+ poff_src, src->addr.offset);
+ igt_assert_f(poff_dst == dst->addr.offset,
+ "prev dst addr: %" PRIx64 " <> dst addr %" PRIx64 "\n",
+ poff_dst, dst->addr.offset);
+
+ fill_buf(src, COLOR_77);
+ fill_buf(dst, COLOR_00);
+
+ __emit_blit(ibb, src, dst);
+ intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ intel_bb_reset(ibb, false);
+ check_buf(dst, COLOR_77);
+
+ intel_bb_emit_bbe(ibb);
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ intel_bb_reset(ibb, false);
+ check_buf(dst, COLOR_77);
+
+ intel_buf_destroy(src);
+ intel_buf_destroy(dst);
+ intel_bb_destroy(ibb);
+}
+
+static void scratch_buf_init(struct buf_ops *bops,
+ struct intel_buf *buf,
+ int width, int height,
+ uint32_t req_tiling,
+ enum i915_compression compression)
+{
+ int bpp = 32;
+
+ intel_buf_init(bops, buf, width, height, bpp, 0,
+ req_tiling, compression);
+
+ igt_assert(intel_buf_width(buf) == width);
+ igt_assert(intel_buf_height(buf) == height);
+}
+
+static void scratch_buf_draw_pattern(struct buf_ops *bops,
+ struct intel_buf *buf,
+ int x, int y, int w, int h,
+ int cx, int cy, int cw, int ch,
+ bool use_alternate_colors)
+{
+ cairo_surface_t *surface;
+ cairo_pattern_t *pat;
+ cairo_t *cr;
+ void *linear;
+
+ linear = alloc_aligned(buf->surface[0].size);
+
+ surface = cairo_image_surface_create_for_data(linear,
+ CAIRO_FORMAT_RGB24,
+ intel_buf_width(buf),
+ intel_buf_height(buf),
+ buf->surface[0].stride);
+
+ cr = cairo_create(surface);
+
+ cairo_rectangle(cr, cx, cy, cw, ch);
+ cairo_clip(cr);
+
+ pat = cairo_pattern_create_mesh();
+ cairo_mesh_pattern_begin_patch(pat);
+ cairo_mesh_pattern_move_to(pat, x, y);
+ cairo_mesh_pattern_line_to(pat, x+w, y);
+ cairo_mesh_pattern_line_to(pat, x+w, y+h);
+ cairo_mesh_pattern_line_to(pat, x, y+h);
+ if (use_alternate_colors) {
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 0.0, 1.0, 1.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 1.0, 0.0, 1.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 1.0, 1.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 0.0, 0.0, 0.0);
+ } else {
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 1.0, 0.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 0.0, 1.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 0.0, 0.0, 1.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 1.0, 1.0, 1.0);
+ }
+ cairo_mesh_pattern_end_patch(pat);
+
+ cairo_rectangle(cr, x, y, w, h);
+ cairo_set_source(cr, pat);
+ cairo_fill(cr);
+ cairo_pattern_destroy(pat);
+
+ cairo_destroy(cr);
+
+ cairo_surface_destroy(surface);
+
+ linear_to_intel_buf(bops, buf, linear);
+
+ free(linear);
+}
+
+#define GROUP_SIZE 4096
+static int compare_detail(const uint32_t *ptr1, uint32_t *ptr2,
+ uint32_t size)
+{
+ int i, ok = 0, fail = 0;
+ int groups = size / GROUP_SIZE;
+ int *hist = calloc(GROUP_SIZE, groups);
+
+ igt_debug("size: %d, group_size: %d, groups: %d\n",
+ size, GROUP_SIZE, groups);
+
+ for (i = 0; i < size / sizeof(uint32_t); i++) {
+ if (ptr1[i] == ptr2[i]) {
+ ok++;
+ } else {
+ fail++;
+ hist[i * sizeof(uint32_t) / GROUP_SIZE]++;
+ }
+ }
+
+ for (i = 0; i < groups; i++) {
+ if (hist[i])
+ igt_debug("[group %4x]: %d\n", i, hist[i]);
+ }
+ free(hist);
+
+ igt_debug("ok: %d, fail: %d\n", ok, fail);
+
+ return fail;
+}
+
+static int compare_bufs(struct intel_buf *buf1, struct intel_buf *buf2,
+ bool detail_compare)
+{
+ void *ptr1, *ptr2;
+ int fd1, fd2, ret;
+
+ igt_assert(buf1->surface[0].size == buf2->surface[0].size);
+
+ fd1 = buf_ops_get_fd(buf1->bops);
+ fd2 = buf_ops_get_fd(buf2->bops);
+
+ ptr1 = xe_bo_map(fd1, buf1->handle, buf1->surface[0].size);
+ ptr2 = xe_bo_map(fd2, buf2->handle, buf2->surface[0].size);
+ ret = memcmp(ptr1, ptr2, buf1->surface[0].size);
+ if (detail_compare)
+ ret = compare_detail(ptr1, ptr2, buf1->surface[0].size);
+
+ munmap(ptr1, buf1->surface[0].size);
+ munmap(ptr2, buf2->surface[0].size);
+
+ return ret;
+}
+
+#define LINELEN 76ul
+static int dump_base64(const char *name, struct intel_buf *buf)
+{
+ void *ptr;
+ int fd, ret;
+ uLongf outsize = buf->surface[0].size * 3 / 2;
+ Bytef *destbuf = malloc(outsize);
+ gchar *str, *pos;
+
+ fd = buf_ops_get_fd(buf->bops);
+
+ ptr = gem_mmap__device_coherent(fd, buf->handle, 0,
+ buf->surface[0].size, PROT_READ);
+
+ ret = compress2(destbuf, &outsize, ptr, buf->surface[0].size,
+ Z_BEST_COMPRESSION);
+ if (ret != Z_OK) {
+ igt_warn("error compressing, ret: %d\n", ret);
+ } else {
+ igt_info("compressed %" PRIu64 " -> %lu\n",
+ buf->surface[0].size, outsize);
+
+ igt_info("--- %s ---\n", name);
+ pos = str = g_base64_encode(destbuf, outsize);
+ outsize = strlen(str);
+ while (pos) {
+ char line[LINELEN + 1];
+ int to_copy = min(LINELEN, outsize);
+
+ memcpy(line, pos, to_copy);
+ line[to_copy] = 0;
+ igt_info("%s\n", line);
+ pos += LINELEN;
+ outsize -= to_copy;
+
+ if (outsize == 0)
+ break;
+ }
+ free(str);
+ }
+
+ munmap(ptr, buf->surface[0].size);
+ free(destbuf);
+
+ return ret;
+}
+
+static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling)
+{
+ struct intel_bb *ibb;
+ const int width = 1024;
+ const int height = 1024;
+ struct intel_buf src, dst, final;
+ char name[128];
+ int xe = buf_ops_get_fd(bops), fails;
+
+ ibb = intel_bb_create(xe, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ scratch_buf_init(bops, &src, width, height, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+ scratch_buf_init(bops, &dst, width, height, tiling,
+ I915_COMPRESSION_NONE);
+ scratch_buf_init(bops, &final, width, height, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+
+ if (buf_info) {
+ intel_buf_print(&src);
+ intel_buf_print(&dst);
+ }
+
+ scratch_buf_draw_pattern(bops, &src,
+ 0, 0, width, height,
+ 0, 0, width, height, 0);
+
+ intel_bb_blt_copy(ibb,
+ &src, 0, 0, src.surface[0].stride,
+ &dst, 0, 0, dst.surface[0].stride,
+ intel_buf_width(&dst),
+ intel_buf_height(&dst),
+ dst.bpp);
+
+ intel_bb_blt_copy(ibb,
+ &dst, 0, 0, dst.surface[0].stride,
+ &final, 0, 0, final.surface[0].stride,
+ intel_buf_width(&dst),
+ intel_buf_height(&dst),
+ dst.bpp);
+
+ igt_assert(intel_bb_sync(ibb) == 0);
+ intel_bb_destroy(ibb);
+
+ if (write_png) {
+ snprintf(name, sizeof(name) - 1,
+ "bb_blit_dst_tiling_%d.png", tiling);
+ intel_buf_write_to_png(&src, "bb_blit_src_tiling_none.png");
+ intel_buf_write_to_png(&dst, name);
+ intel_buf_write_to_png(&final, "bb_blit_final_tiling_none.png");
+ }
+
+ /* We'll fail on src <-> final compare so just warn */
+ if (tiling == I915_TILING_NONE) {
+ if (compare_bufs(&src, &dst, false) > 0)
+ igt_warn("none->none blit failed!");
+ } else {
+ if (compare_bufs(&src, &dst, false) == 0)
+ igt_warn("none->tiled blit failed!");
+ }
+
+ fails = compare_bufs(&src, &final, true);
+
+ intel_buf_close(bops, &src);
+ intel_buf_close(bops, &dst);
+ intel_buf_close(bops, &final);
+
+ return fails;
+}
+
+/**
+ * SUBTEST: intel-bb-blit-%s
+ * Description: Run simple bb xe %arg[1] test
+ * Run type: BAT
+ *
+ * arg[1]:
+ *
+ * @none: none
+ * @x: x
+ * @y: y
+ */
+static void do_intel_bb_blit(struct buf_ops *bops, int loops, uint32_t tiling)
+{
+ int i, fails = 0, xe = buf_ops_get_fd(bops);
+
+ /* We'll fix it for gen2/3 later. */
+ igt_require(intel_gen(intel_get_drm_devid(xe)) > 3);
+
+ for (i = 0; i < loops; i++)
+ fails += __do_intel_bb_blit(bops, tiling);
+
+ igt_assert_f(fails == 0, "intel-bb-blit (tiling: %d) fails: %d\n",
+ tiling, fails);
+}
+
+/**
+ * SUBTEST: offset-control
+ * Description: check offset is kept on default simple allocator
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void offset_control(struct buf_ops *bops)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ struct intel_buf *src, *dst1, *dst2, *dst3;
+ uint64_t poff_src, poff_dst1, poff_dst2;
+
+ ibb = intel_bb_create(xe, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ src = create_buf(bops, WIDTH, HEIGHT, COLOR_CC);
+ dst1 = create_buf(bops, WIDTH, HEIGHT, COLOR_00);
+ dst2 = create_buf(bops, WIDTH, HEIGHT, COLOR_77);
+
+ intel_bb_add_object(ibb, src->handle, intel_buf_bo_size(src),
+ src->addr.offset, 0, false);
+ intel_bb_add_object(ibb, dst1->handle, intel_buf_bo_size(dst1),
+ dst1->addr.offset, 0, true);
+ intel_bb_add_object(ibb, dst2->handle, intel_buf_bo_size(dst2),
+ dst2->addr.offset, 0, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
+
+ if (buf_info) {
+ print_buf(src, "src ");
+ print_buf(dst1, "dst1");
+ print_buf(dst2, "dst2");
+ }
+
+ poff_src = src->addr.offset;
+ poff_dst1 = dst1->addr.offset;
+ poff_dst2 = dst2->addr.offset;
+ intel_bb_reset(ibb, true);
+
+ dst3 = create_buf(bops, WIDTH, HEIGHT, COLOR_33);
+ intel_bb_add_object(ibb, dst3->handle, intel_buf_bo_size(dst3),
+ dst3->addr.offset, 0, true);
+ intel_bb_add_object(ibb, src->handle, intel_buf_bo_size(src),
+ src->addr.offset, 0, false);
+ intel_bb_add_object(ibb, dst1->handle, intel_buf_bo_size(dst1),
+ dst1->addr.offset, 0, true);
+ intel_bb_add_object(ibb, dst2->handle, intel_buf_bo_size(dst2),
+ dst2->addr.offset, 0, true);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
+ intel_bb_sync(ibb);
+ intel_bb_reset(ibb, true);
+
+ igt_assert(poff_src == src->addr.offset);
+ igt_assert(poff_dst1 == dst1->addr.offset);
+ igt_assert(poff_dst2 == dst2->addr.offset);
+
+ if (buf_info) {
+ print_buf(src, "src ");
+ print_buf(dst1, "dst1");
+ print_buf(dst2, "dst2");
+ }
+
+ intel_buf_destroy(src);
+ intel_buf_destroy(dst1);
+ intel_buf_destroy(dst2);
+ intel_buf_destroy(dst3);
+ intel_bb_destroy(ibb);
+}
+
+/*
+ * Idea of the test is to verify delta is properly added to address
+ * when emit_reloc() is called.
+ */
+
+/**
+ * SUBTEST: delta-check
+ * Description: check delta is honoured in intel-bb pipelines
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+#define DELTA_BUFFERS 3
+static void delta_check(struct buf_ops *bops)
+{
+ const uint32_t expected = 0x1234abcd;
+ int xe = buf_ops_get_fd(bops);
+ uint32_t *ptr, hi, lo, val;
+ struct intel_buf *buf;
+ struct intel_bb *ibb;
+ uint64_t offset;
+ uint64_t obj_size = xe_get_default_alignment(xe) + 0x2000;
+ uint64_t obj_offset = (1ULL << 32) - xe_get_default_alignment(xe);
+ uint64_t delta = xe_get_default_alignment(xe) + 0x1000;
+
+ ibb = intel_bb_create_with_allocator(xe, 0, NULL, PAGE_SIZE,
+ INTEL_ALLOCATOR_SIMPLE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ buf = create_buf(bops, obj_size, 0x1, COLOR_CC);
+ buf->addr.offset = obj_offset;
+ intel_bb_add_object(ibb, buf->handle, intel_buf_bo_size(buf),
+ buf->addr.offset, 0, false);
+
+ intel_bb_out(ibb, MI_STORE_DWORD_IMM_GEN4);
+ intel_bb_emit_reloc(ibb, buf->handle,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER,
+ delta, buf->addr.offset);
+ intel_bb_out(ibb, expected);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 8);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb), I915_EXEC_DEFAULT, false);
+ intel_bb_sync(ibb);
+
+ /* Buffer should be @ obj_offset */
+ offset = intel_bb_get_object_offset(ibb, buf->handle);
+ igt_assert_eq_u64(offset, obj_offset);
+
+ ptr = xe_bo_map(xe, ibb->handle, ibb->size);
+ lo = ptr[1];
+ hi = ptr[2];
+ gem_munmap(ptr, ibb->size);
+
+ ptr = xe_bo_map(xe, buf->handle, intel_buf_size(buf));
+ val = ptr[delta / sizeof(uint32_t)];
+ gem_munmap(ptr, intel_buf_size(buf));
+
+ intel_buf_destroy(buf);
+ intel_bb_destroy(ibb);
+
+ /* Assert after all resources are freed */
+ igt_assert_f(lo == 0x1000 && hi == 0x1,
+ "intel-bb doesn't properly handle delta in emit relocation\n");
+ igt_assert_f(val == expected,
+ "Address doesn't contain expected [%x] value [%x]\n",
+ expected, val);
+}
+
+/**
+ * SUBTEST: full-batch
+ * Description: check bb totally filled is executing correct
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void full_batch(struct buf_ops *bops)
+{
+ int xe = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+ int i;
+
+ ibb = intel_bb_create(xe, PAGE_SIZE);
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ for (i = 0; i < PAGE_SIZE / sizeof(uint32_t) - 1; i++)
+ intel_bb_out(ibb, 0);
+ intel_bb_emit_bbe(ibb);
+
+ igt_assert(intel_bb_offset(ibb) == PAGE_SIZE);
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ intel_bb_reset(ibb, false);
+
+ intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: render
+ * Description: check intel-bb render pipeline
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static int render(struct buf_ops *bops, uint32_t tiling,
+ uint32_t width, uint32_t height)
+{
+ struct intel_bb *ibb;
+ struct intel_buf src, dst, final;
+ int xe = buf_ops_get_fd(bops);
+ uint32_t fails = 0;
+ char name[128];
+ uint32_t devid = intel_get_drm_devid(xe);
+ igt_render_copyfunc_t render_copy = NULL;
+
+ igt_debug("%s() gen: %d\n", __func__, intel_gen(devid));
+
+ ibb = intel_bb_create(xe, PAGE_SIZE);
+
+ if (debug_bb)
+ intel_bb_set_debug(ibb, true);
+
+ if (print_base64)
+ intel_bb_set_dump_base64(ibb, true);
+
+ scratch_buf_init(bops, &src, width, height, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+ scratch_buf_init(bops, &dst, width, height, tiling,
+ I915_COMPRESSION_NONE);
+ scratch_buf_init(bops, &final, width, height, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
+
+ scratch_buf_draw_pattern(bops, &src,
+ 0, 0, width, height,
+ 0, 0, width, height, 0);
+
+ render_copy = igt_get_render_copyfunc(devid);
+ igt_assert(render_copy);
+
+ render_copy(ibb,
+ &src,
+ 0, 0, width, height,
+ &dst,
+ 0, 0);
+
+ render_copy(ibb,
+ &dst,
+ 0, 0, width, height,
+ &final,
+ 0, 0);
+
+ intel_bb_sync(ibb);
+ intel_bb_destroy(ibb);
+
+ if (write_png) {
+ snprintf(name, sizeof(name) - 1,
+ "render_dst_tiling_%d.png", tiling);
+ intel_buf_write_to_png(&src, "render_src_tiling_none.png");
+ intel_buf_write_to_png(&dst, name);
+ intel_buf_write_to_png(&final, "render_final_tiling_none.png");
+ }
+
+ /* We'll fail on src <-> final compare so just warn */
+ if (tiling == I915_TILING_NONE) {
+ if (compare_bufs(&src, &dst, false) > 0)
+ igt_warn("%s: none->none failed!\n", __func__);
+ } else {
+ if (compare_bufs(&src, &dst, false) == 0)
+ igt_warn("%s: none->tiled failed!\n", __func__);
+ }
+
+ fails = compare_bufs(&src, &final, true);
+
+ if (fails && print_base64) {
+ dump_base64("src", &src);
+ dump_base64("dst", &dst);
+ dump_base64("final", &final);
+ }
+
+ intel_buf_close(bops, &src);
+ intel_buf_close(bops, &dst);
+ intel_buf_close(bops, &final);
+
+ igt_assert_f(fails == 0, "%s: (tiling: %d) fails: %d\n",
+ __func__, tiling, fails);
+
+ return fails;
+}
+
+static int opt_handler(int opt, int opt_index, void *data)
+{
+ switch (opt) {
+ case 'd':
+ debug_bb = true;
+ break;
+ case 'p':
+ write_png = true;
+ break;
+ case 'i':
+ buf_info = true;
+ break;
+ case 'b':
+ print_base64 = true;
+ break;
+ default:
+ return IGT_OPT_HANDLER_ERROR;
+ }
+
+ return IGT_OPT_HANDLER_SUCCESS;
+}
+
+const char *help_str =
+ " -d\tDebug bb\n"
+ " -p\tWrite surfaces to png\n"
+ " -i\tPrint buffer info\n"
+ " -b\tDump to base64 (bb and images)\n"
+ " -c n\tCalculate crc up to (1 << n)\n"
+ ;
+
+igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
+{
+ int xe, i;
+ struct buf_ops *bops;
+ uint32_t width;
+
+ struct test {
+ uint32_t tiling;
+ const char *tiling_name;
+ } tests[] = {
+ { I915_TILING_NONE, "none" },
+ { I915_TILING_X, "x" },
+ { I915_TILING_Y, "y" },
+ };
+
+ igt_fixture {
+ xe = drm_open_driver(DRIVER_XE);
+ bops = buf_ops_create(xe);
+ xe_device_get(xe);
+ }
+
+ igt_describe("Ensure reset is possible on fresh bb");
+ igt_subtest("reset-bb")
+ reset_bb(bops);
+
+ igt_subtest_f("purge-bb")
+ purge_bb(bops);
+
+ igt_subtest("simple-bb")
+ simple_bb(bops, false);
+
+ igt_subtest("simple-bb-ctx")
+ simple_bb(bops, true);
+
+ igt_subtest("bb-with-allocator")
+ bb_with_allocator(bops);
+
+ igt_subtest("lot-of-buffers")
+ lot_of_buffers(bops);
+
+ igt_subtest("add-remove-objects")
+ add_remove_objects(bops);
+
+ igt_subtest("destroy-bb")
+ destroy_bb(bops);
+
+ igt_subtest_with_dynamic("create-in-region") {
+ uint64_t memreg = all_memory_regions(xe), region;
+
+ xe_for_each_mem_region(fd, memreg, region)
+ igt_dynamic_f("region-%s", xe_region_name(region))
+ create_in_region(bops, region);
+ }
+
+ igt_subtest("blit-simple")
+ blit(bops, INTEL_ALLOCATOR_SIMPLE);
+
+ igt_subtest("blit-reloc")
+ blit(bops, INTEL_ALLOCATOR_RELOC);
+
+ igt_subtest("intel-bb-blit-none")
+ do_intel_bb_blit(bops, 3, I915_TILING_NONE);
+
+ igt_subtest("intel-bb-blit-x")
+ do_intel_bb_blit(bops, 3, I915_TILING_X);
+
+ igt_subtest("intel-bb-blit-y") {
+ igt_require(intel_gen(intel_get_drm_devid(xe)) >= 6);
+ do_intel_bb_blit(bops, 3, I915_TILING_Y);
+ }
+
+ igt_subtest("offset-control")
+ offset_control(bops);
+
+ igt_subtest("delta-check")
+ delta_check(bops);
+
+ igt_subtest("full-batch")
+ full_batch(bops);
+
+ igt_subtest_with_dynamic("render") {
+ for (i = 0; i < ARRAY_SIZE(tests); i++) {
+ const struct test *t = &tests[i];
+
+ for (width = 512; width <= 1024; width += 512) {
+ igt_dynamic_f("render-%s-%u", t->tiling_name, width) {
+ render(bops, t->tiling, width, width);
+ }
+ }
+ }
+ }
+
+ igt_fixture {
+ xe_device_put(xe);
+ buf_ops_destroy(bops);
+ close(xe);
+ }
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 08/10] tests/xe-fast-feedback: Add xe_intel_bb test to BAT
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
` (6 preceding siblings ...)
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 07/10] tests/xe_intel_bb: Check if intel-bb Xe support correctness Zbigniew Kempczyński
@ 2023-04-17 15:36 ` Zbigniew Kempczyński
2023-04-17 15:36 ` [igt-dev] [PATCH i-g-t 09/10] lib/gpgpu_fill: Use RENDER engine flag to work on Xe Zbigniew Kempczyński
` (3 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:36 UTC (permalink / raw)
To: igt-dev
Verifies intel-bb integration with xe.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/intel-ci/xe-fast-feedback.testlist | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/tests/intel-ci/xe-fast-feedback.testlist b/tests/intel-ci/xe-fast-feedback.testlist
index 5db27c6345..019804b579 100644
--- a/tests/intel-ci/xe-fast-feedback.testlist
+++ b/tests/intel-ci/xe-fast-feedback.testlist
@@ -1,6 +1,24 @@
# Should be the first test
igt@xe_module_load@load
+igt@xe_intel_bb@reset-bb
+igt@xe_intel_bb@purge-bb
+igt@xe_intel_bb@simple-bb
+igt@xe_intel_bb@simple-bb-ctx
+igt@xe_intel_bb@bb-with-allocator
+igt@xe_intel_bb@lot-of-buffers
+igt@xe_intel_bb@add-remove-objects
+igt@xe_intel_bb@destroy-bb
+igt@xe_intel_bb@create-in-region
+igt@xe_intel_bb@blit-simple
+igt@xe_intel_bb@blit-reloc
+igt@xe_intel_bb@intel-bb-blit-none
+igt@xe_intel_bb@intel-bb-blit-x
+igt@xe_intel_bb@intel-bb-blit-y
+igt@xe_intel_bb@offset-control
+igt@xe_intel_bb@delta-check
+igt@xe_intel_bb@full-batch
+igt@xe_intel_bb@render
igt@xe_compute@compute-square
igt@xe_debugfs@base
igt@xe_debugfs@gt
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 09/10] lib/gpgpu_fill: Use RENDER engine flag to work on Xe
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
` (7 preceding siblings ...)
2023-04-17 15:36 ` [igt-dev] [PATCH i-g-t 08/10] tests/xe-fast-feedback: Add xe_intel_bb test to BAT Zbigniew Kempczyński
@ 2023-04-17 15:36 ` Zbigniew Kempczyński
2023-04-17 15:36 ` [igt-dev] [PATCH i-g-t 10/10] tests/xe_gpgpu_fill: Exercise gpgpu fill " Zbigniew Kempczyński
` (2 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:36 UTC (permalink / raw)
To: igt-dev
Using I915_EXEC_DEFAULT works fine for i915 selecting appropriate
command streamer. Unfortunately this cannot be used on Xe as it
requires explicit engine selection. Submitting gpgpu work on
render is fine so change to I915_EXEC_RENDER doesn't break i915
and allows run on valid engine on Xe.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
lib/gpgpu_fill.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
index 4f7bab68f2..4db8775145 100644
--- a/lib/gpgpu_fill.c
+++ b/lib/gpgpu_fill.c
@@ -288,7 +288,7 @@ __gen9_gpgpu_fillfunc(int i915,
intel_bb_ptr_align(ibb, 32);
intel_bb_exec(ibb, intel_bb_offset(ibb),
- I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ I915_EXEC_RENDER | I915_EXEC_NO_RELOC, true);
intel_bb_destroy(ibb);
}
@@ -329,7 +329,7 @@ __xehp_gpgpu_fillfunc(int i915,
intel_bb_ptr_align(ibb, 32);
intel_bb_exec(ibb, intel_bb_offset(ibb),
- I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+ I915_EXEC_RENDER | I915_EXEC_NO_RELOC, true);
intel_bb_destroy(ibb);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 10/10] tests/xe_gpgpu_fill: Exercise gpgpu fill on Xe
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
` (8 preceding siblings ...)
2023-04-17 15:36 ` [igt-dev] [PATCH i-g-t 09/10] lib/gpgpu_fill: Use RENDER engine flag to work on Xe Zbigniew Kempczyński
@ 2023-04-17 15:36 ` Zbigniew Kempczyński
2023-04-17 16:46 ` [igt-dev] ✓ Fi.CI.BAT: success for Integrate intel-bb with Xe Patchwork
2023-04-18 2:03 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 13+ messages in thread
From: Zbigniew Kempczyński @ 2023-04-17 15:36 UTC (permalink / raw)
To: igt-dev
Reuse gpgpu fill already exercised on i915 on Xe.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/intel-ci/xe-fast-feedback.testlist | 1 +
tests/meson.build | 1 +
tests/xe/xe_gpgpu_fill.c | 133 +++++++++++++++++++++++
3 files changed, 135 insertions(+)
create mode 100644 tests/xe/xe_gpgpu_fill.c
diff --git a/tests/intel-ci/xe-fast-feedback.testlist b/tests/intel-ci/xe-fast-feedback.testlist
index 019804b579..e3ebce70b6 100644
--- a/tests/intel-ci/xe-fast-feedback.testlist
+++ b/tests/intel-ci/xe-fast-feedback.testlist
@@ -118,6 +118,7 @@ igt@xe_exec_threads@threads-mixed-fd-basic
igt@xe_exec_threads@threads-bal-mixed-basic
igt@xe_exec_threads@threads-bal-mixed-shared-vm-basic
igt@xe_exec_threads@threads-bal-mixed-fd-basic
+igt@xe_gpgpu_fill@basic
igt@xe_guc_pc@freq_basic_api
igt@xe_guc_pc@freq_fixed_idle
igt@xe_guc_pc@freq_range_idle
diff --git a/tests/meson.build b/tests/meson.build
index 3ec440710e..a6642b9dc1 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -253,6 +253,7 @@ xe_progs = [
'xe_exec_fault_mode',
'xe_exec_reset',
'xe_exec_threads',
+ 'xe_gpgpu_fill',
'xe_guc_pc',
'xe_huc_copy',
'xe_intel_bb',
diff --git a/tests/xe/xe_gpgpu_fill.c b/tests/xe/xe_gpgpu_fill.c
new file mode 100644
index 0000000000..d9a932fde3
--- /dev/null
+++ b/tests/xe/xe_gpgpu_fill.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+/**
+ * TEST: Basic tests for gpgpu functionality
+ * Category: Software building block
+ * Sub-category: gpgpu
+ * Test category: functionality test
+ */
+
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+
+#include "drm.h"
+#include "i915/gem.h"
+#include "igt.h"
+#include "igt_collection.h"
+#include "intel_bufops.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define WIDTH 64
+#define HEIGHT 64
+#define STRIDE (WIDTH)
+#define SIZE (HEIGHT*STRIDE)
+#define COLOR_C4 0xc4
+#define COLOR_4C 0x4c
+
+typedef struct {
+ int drm_fd;
+ uint32_t devid;
+ struct buf_ops *bops;
+} data_t;
+
+static struct intel_buf *
+create_buf(data_t *data, int width, int height, uint8_t color, uint64_t region)
+{
+ struct intel_buf *buf;
+ uint8_t *ptr;
+ int i;
+
+ buf = calloc(1, sizeof(*buf));
+ igt_assert(buf);
+
+ buf = intel_buf_create(data->bops, width/4, height, 32, 0,
+ I915_TILING_NONE, 0);
+
+ ptr = xe_bo_map(data->drm_fd, buf->handle, buf->surface[0].size);
+
+ for (i = 0; i < buf->surface[0].size; i++)
+ ptr[i] = color;
+
+ munmap(ptr, buf->surface[0].size);
+
+ return buf;
+}
+
+static void buf_check(uint8_t *ptr, int x, int y, uint8_t color)
+{
+ uint8_t val;
+
+ val = ptr[y * WIDTH + x];
+ igt_assert_f(val == color,
+ "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
+ color, val, x, y);
+}
+
+/**
+ * SUBTEST: basic
+ * Description: run gpgpu fill
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+
+static void gpgpu_fill(data_t *data, igt_fillfunc_t fill, uint32_t region)
+{
+ struct intel_buf *buf;
+ uint8_t *ptr;
+ int i, j;
+
+ buf = create_buf(data, WIDTH, HEIGHT, COLOR_C4, region);
+ ptr = xe_bo_map(data->drm_fd, buf->handle, buf->surface[0].size);
+
+ for (i = 0; i < WIDTH; i++)
+ for (j = 0; j < HEIGHT; j++)
+ buf_check(ptr, i, j, COLOR_C4);
+
+ fill(data->drm_fd, buf, 0, 0, WIDTH / 2, HEIGHT / 2, COLOR_4C);
+
+ for (i = 0; i < WIDTH; i++)
+ for (j = 0; j < HEIGHT; j++)
+ if (i < WIDTH / 2 && j < HEIGHT / 2)
+ buf_check(ptr, i, j, COLOR_4C);
+ else
+ buf_check(ptr, i, j, COLOR_C4);
+
+ munmap(ptr, buf->surface[0].size);
+}
+
+igt_main
+{
+ data_t data = {0, };
+ igt_fillfunc_t fill_fn = NULL;
+
+ igt_fixture {
+ data.drm_fd = drm_open_driver_render(DRIVER_XE);
+ data.devid = intel_get_drm_devid(data.drm_fd);
+ data.bops = buf_ops_create(data.drm_fd);
+
+ fill_fn = igt_get_gpgpu_fillfunc(data.devid);
+ xe_device_get(data.drm_fd);
+ }
+
+ igt_subtest("basic") {
+ gpgpu_fill(&data, fill_fn, 0);
+ }
+
+ igt_fixture {
+ xe_device_put(data.drm_fd);
+ buf_ops_destroy(data.bops);
+ }
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Integrate intel-bb with Xe
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
` (9 preceding siblings ...)
2023-04-17 15:36 ` [igt-dev] [PATCH i-g-t 10/10] tests/xe_gpgpu_fill: Exercise gpgpu fill " Zbigniew Kempczyński
@ 2023-04-17 16:46 ` Patchwork
2023-04-18 2:03 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2023-04-17 16:46 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 4866 bytes --]
== Series Details ==
Series: Integrate intel-bb with Xe
URL : https://patchwork.freedesktop.org/series/116578/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13021 -> IGTPW_8811
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/index.html
Participating hosts (38 -> 36)
------------------------------
Missing (2): bat-mtlp-8 fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_8811 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_pm:
- bat-adln-1: [PASS][1] -> [DMESG-FAIL][2] ([i915#4258])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/bat-adln-1/igt@i915_selftest@live@gt_pm.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/bat-adln-1/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: NOTRUN -> [ABORT][3] ([i915#4983] / [i915#7913])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/bat-rpls-2/igt@i915_selftest@live@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#5354])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
#### Possible fixes ####
* igt@i915_pm_rps@basic-api:
- bat-dg2-11: [FAIL][5] ([i915#8308]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/bat-dg2-11/igt@i915_pm_rps@basic-api.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/bat-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@migrate:
- bat-atsm-1: [DMESG-FAIL][7] ([i915#7699]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/bat-atsm-1/igt@i915_selftest@live@migrate.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/bat-atsm-1/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [ABORT][9] ([i915#4983] / [i915#7913]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/bat-rpls-2/igt@i915_selftest@live@requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-b-dp-1:
- bat-dg2-8: [DMESG-WARN][11] ([i915#62]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/bat-dg2-8/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-b-dp-1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/bat-dg2-8/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-b-dp-1.html
* igt@kms_pipe_crc_basic@read-crc@pipe-b-dp-1:
- bat-dg2-8: [DMESG-WARN][13] ([i915#7507]) -> [PASS][14] +5 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/bat-dg2-8/igt@kms_pipe_crc_basic@read-crc@pipe-b-dp-1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/bat-dg2-8/igt@kms_pipe_crc_basic@read-crc@pipe-b-dp-1.html
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#7507]: https://gitlab.freedesktop.org/drm/intel/issues/7507
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7258 -> IGTPW_8811
CI-20190529: 20190529
CI_DRM_13021: 495482f485451a5a0612de80df7de7309f0a12da @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8811: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/index.html
IGT_7258: ad2eb276eda849b7a7985229009a816c7608186c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@xe_gpgpu_fill@basic
+igt@xe_intel_bb@add-remove-objects
+igt@xe_intel_bb@bb-with-allocator
+igt@xe_intel_bb@blit-reloc
+igt@xe_intel_bb@blit-simple
+igt@xe_intel_bb@create-in-region
+igt@xe_intel_bb@delta-check
+igt@xe_intel_bb@destroy-bb
+igt@xe_intel_bb@full-batch
+igt@xe_intel_bb@intel-bb-blit-none
+igt@xe_intel_bb@intel-bb-blit-x
+igt@xe_intel_bb@intel-bb-blit-y
+igt@xe_intel_bb@lot-of-buffers
+igt@xe_intel_bb@offset-control
+igt@xe_intel_bb@purge-bb
+igt@xe_intel_bb@render
+igt@xe_intel_bb@reset-bb
+igt@xe_intel_bb@simple-bb
+igt@xe_intel_bb@simple-bb-ctx
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/index.html
[-- Attachment #2: Type: text/html, Size: 5894 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Integrate intel-bb with Xe
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
` (10 preceding siblings ...)
2023-04-17 16:46 ` [igt-dev] ✓ Fi.CI.BAT: success for Integrate intel-bb with Xe Patchwork
@ 2023-04-18 2:03 ` Patchwork
11 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2023-04-18 2:03 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 19713 bytes --]
== Series Details ==
Series: Integrate intel-bb with Xe
URL : https://patchwork.freedesktop.org/series/116578/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13021_full -> IGTPW_8811_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_8811_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_8811_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/index.html
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_8811_full:
### IGT changes ###
#### Possible regressions ####
* igt@api_intel_allocator@default-alignment:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-snb4/igt@api_intel_allocator@default-alignment.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-snb7/igt@api_intel_allocator@default-alignment.html
- shard-glk: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-glk6/igt@api_intel_allocator@default-alignment.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-glk8/igt@api_intel_allocator@default-alignment.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@api_intel_allocator@default-alignment:
- {shard-rkl}: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-rkl-7/igt@api_intel_allocator@default-alignment.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-rkl-3/igt@api_intel_allocator@default-alignment.html
- {shard-tglu}: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-tglu-7/igt@api_intel_allocator@default-alignment.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-tglu-8/igt@api_intel_allocator@default-alignment.html
* igt@api_intel_bb@blit-reloc-purge-cache:
- {shard-dg1}: NOTRUN -> [SKIP][9] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-dg1-17/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@api_intel_bb@object-reloc-keep-cache:
- {shard-rkl}: [SKIP][10] ([i915#3281]) -> [SKIP][11] +6 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-rkl-6/igt@api_intel_bb@object-reloc-keep-cache.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-rkl-7/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@api_intel_bb@object-reloc-purge-cache:
- {shard-dg1}: [SKIP][12] ([i915#3281]) -> [SKIP][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-dg1-18/igt@api_intel_bb@object-reloc-purge-cache.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-dg1-14/igt@api_intel_bb@object-reloc-purge-cache.html
Known issues
------------
Here are the changes found in IGTPW_8811_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-apl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-glk1/igt@gem_exec_fair@basic-pace@vcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-glk9/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-glk2/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs:
- shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271]) +32 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-glk9/igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][20] -> [FAIL][21] ([i915#2346])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-glk: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-glk8/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
#### Possible fixes ####
* igt@drm_fdinfo@idle@rcs0:
- {shard-rkl}: [FAIL][23] ([i915#7742]) -> [PASS][24] +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-rkl-1/igt@drm_fdinfo@idle@rcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-rkl-1/igt@drm_fdinfo@idle@rcs0.html
* igt@gem_barrier_race@remote-request@rcs0:
- {shard-tglu}: [ABORT][25] ([i915#8211]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-tglu-9/igt@gem_barrier_race@remote-request@rcs0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-tglu-3/igt@gem_barrier_race@remote-request@rcs0.html
- shard-glk: [ABORT][27] ([i915#8211]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-glk2/igt@gem_barrier_race@remote-request@rcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-glk1/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][29] ([i915#6268]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-tglu-2/igt@gem_ctx_exec@basic-nohangcheck.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-tglu-8/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][31] ([i915#2846]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-glk6/igt@gem_exec_fair@basic-deadline.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][33] ([i915#2842]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- {shard-rkl}: [FAIL][35] ([i915#2842]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-rkl-1/igt@gem_exec_fair@basic-none@vecs0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-rkl-6/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][37] ([i915#2842]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu}: [SKIP][39] ([i915#4281]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-tglu-5/igt@i915_pm_dc@dc9-dpms.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-tglu-9/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-rkl}: [SKIP][41] ([i915#1397]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-rkl-1/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_selftest@live@dmabuf:
- shard-apl: [DMESG-FAIL][43] ([i915#7562]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-apl4/igt@i915_selftest@live@dmabuf.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-apl1/igt@i915_selftest@live@dmabuf.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][45] ([i915#2346]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@forked-bo@pipe-b:
- {shard-rkl}: [INCOMPLETE][47] ([i915#8011]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-rkl-7/igt@kms_cursor_legacy@forked-bo@pipe-b.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-rkl-3/igt@kms_cursor_legacy@forked-bo@pipe-b.html
* igt@kms_plane_scaling@i915-max-src-size@pipe-a-hdmi-a-1:
- {shard-tglu}: [FAIL][49] ([i915#8292]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-tglu-10/igt@kms_plane_scaling@i915-max-src-size@pipe-a-hdmi-a-1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-tglu-10/igt@kms_plane_scaling@i915-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- {shard-rkl}: [ABORT][51] ([i915#8311]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13021/shard-rkl-6/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/shard-rkl-7/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7562]: https://gitlab.freedesktop.org/drm/intel/issues/7562
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7967]: https://gitlab.freedesktop.org/drm/intel/issues/7967
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8155]: https://gitlab.freedesktop.org/drm/intel/issues/8155
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8311]: https://gitlab.freedesktop.org/drm/intel/issues/8311
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7258 -> IGTPW_8811
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13021: 495482f485451a5a0612de80df7de7309f0a12da @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8811: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/index.html
IGT_7258: ad2eb276eda849b7a7985229009a816c7608186c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8811/index.html
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^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-04-18 2:03 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-17 15:35 [igt-dev] [PATCH i-g-t 00/10] Integrate intel-bb with Xe Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 01/10] lib/xe_ioctl: Add missing header for direct resolving Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 02/10] lib/xe_query: Add region helpers and missing doc Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 03/10] lib/xe_query: Remove commented out function prototype Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 04/10] lib/intel_allocator: Add allocator support for Xe Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 05/10] lib/intel_bufops: Add Xe support in bufops Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 06/10] lib/intel_batchbuffer: Add Xe support in intel-bb Zbigniew Kempczyński
2023-04-17 15:35 ` [igt-dev] [PATCH i-g-t 07/10] tests/xe_intel_bb: Check if intel-bb Xe support correctness Zbigniew Kempczyński
2023-04-17 15:36 ` [igt-dev] [PATCH i-g-t 08/10] tests/xe-fast-feedback: Add xe_intel_bb test to BAT Zbigniew Kempczyński
2023-04-17 15:36 ` [igt-dev] [PATCH i-g-t 09/10] lib/gpgpu_fill: Use RENDER engine flag to work on Xe Zbigniew Kempczyński
2023-04-17 15:36 ` [igt-dev] [PATCH i-g-t 10/10] tests/xe_gpgpu_fill: Exercise gpgpu fill " Zbigniew Kempczyński
2023-04-17 16:46 ` [igt-dev] ✓ Fi.CI.BAT: success for Integrate intel-bb with Xe Patchwork
2023-04-18 2:03 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
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