[Intel-gfx] [PATCH v3 0/8] mtl: add support for pmdemand

[Intel-gfx] [PATCH v3 0/8] mtl: add support for pmdemand

[Vinod Govindapillai]

pmdemand support patches for MTL

SAGV configuration support for MTL

v2: added one missing patch in the previous version

v3: chekcpatch warning fixes
    update index handling for the icl/tgl QGV point handling
    program pmdemand code simplified

v4: update to debufs and pipe values pmdemand regiters
    removed the macro usage in update_pmdemand_values

Mika Kahola (1):
  drm/i915/mtl: Add support for PM DEMAND

Vinod Govindapillai (7):
  drm/i915: fix the derating percentage for MTL
  drm/i915: update the QGV point frequency calculations
  drm/i915: store the peak bw per QGV point
  drm/i915: extract intel_bw_check_qgv_points()
  drm/i915: modify max_bw to return index to intel_bw_info
  drm/i915/mtl: find best QGV point and configure sagv
  drm/i915/display: provision to suppress drm_warn in
    intel_get_crtc_new_encoder

 drivers/gpu/drm/i915/Makefile                 |   3 +-
 drivers/gpu/drm/i915/display/intel_bw.c       | 350 +++++++++-----
 drivers/gpu/drm/i915/display/intel_bw.h       |   6 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  17 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   3 +-
 .../gpu/drm/i915/display/intel_display_core.h |   8 +
 .../drm/i915/display/intel_display_driver.c   |   7 +
 .../drm/i915/display/intel_display_power.c    |   8 +
 drivers/gpu/drm/i915/display/intel_dpll.c     |   8 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c | 455 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_pmdemand.h |  24 +
 drivers/gpu/drm/i915/display/intel_snps_phy.c |   2 +-
 drivers/gpu/drm/i915/i915_irq.c               |  21 +-
 drivers/gpu/drm/i915/i915_reg.h               |  36 +-
 16 files changed, 819 insertions(+), 133 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h

-- 
2.34.1

[Intel-gfx] [PATCH v3 1/8] drm/i915: fix the derating percentage for MTL

[Vinod Govindapillai]

Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.

Bspec: 64631

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 597d5816ad1b..ab405c48ca3a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -379,7 +379,7 @@ static const struct intel_sa_info mtl_sa_info = {
 	.deburst = 32,
 	.deprogbwlimit = 38, /* GB/s */
 	.displayrtids = 256,
-	.derating = 20,
+	.derating = 10,
 };
 
 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
-- 
2.34.1

[Intel-gfx] [PATCH v3 2/8] drm/i915: update the QGV point frequency calculations

[Vinod Govindapillai]

From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.

Bspec: 64636

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index ab405c48ca3a..25ae4e5834d3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	val2 = intel_uncore_read(&dev_priv->uncore,
 				 MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
 	dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
-	sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
+	sp->dclk = (16667 * dclk + 500) / 1000;
 	sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
 	sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
 
-- 
2.34.1

[Intel-gfx] [PATCH v3 3/8] drm/i915: store the peak bw per QGV point

[Vinod Govindapillai]

In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.

Bspec: 64636

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c           | 7 +++++--
 drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 25ae4e5834d3..f5b6cd7f83b8 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -534,10 +534,13 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
 
 			bi->deratedbw[j] = min(maxdebw,
 					       bw * (100 - sa->derating) / 100);
+			bi->peakbw[j] = sp->dclk * num_channels *
+					qi.channel_width / 8;
 
 			drm_dbg_kms(&dev_priv->drm,
-				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
-				    i, j, bi->num_planes, bi->deratedbw[j]);
+				    "BW%d / QGV %d: num_planes=%d deratedbw=%u peakbw: %u\n",
+				    i, j, bi->num_planes, bi->deratedbw[j],
+				    bi->peakbw[j]);
 		}
 
 		for (j = 0; j < qi.num_psf_points; j++) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index e36f88a39b86..9f66d734edf6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -314,6 +314,8 @@ struct intel_display {
 			unsigned int deratedbw[I915_NUM_QGV_POINTS];
 			/* for each PSF GV point */
 			unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
+			/* Peak BW for each QGV point */
+			unsigned int peakbw[I915_NUM_QGV_POINTS];
 			u8 num_qgv_points;
 			u8 num_psf_gv_points;
 			u8 num_planes;
-- 
2.34.1

[Intel-gfx] [PATCH v3 4/8] drm/i915: extract intel_bw_check_qgv_points()

[Vinod Govindapillai]

Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 235 +++++++++++++-----------
 1 file changed, 130 insertions(+), 105 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index f5b6cd7f83b8..a3b8512ebe8a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -802,6 +802,128 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
 	return to_intel_bw_state(bw_state);
 }
 
+static int icl_find_qgv_points(struct drm_i915_private *i915,
+			       unsigned int data_rate,
+			       unsigned int num_active_planes,
+			       const struct intel_bw_state *old_bw_state,
+			       struct intel_bw_state *new_bw_state)
+{
+	unsigned int max_bw_point = 0;
+	unsigned int max_bw = 0;
+	unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
+	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+	u16 psf_points = 0;
+	u16 qgv_points = 0;
+	int i;
+	int ret;
+
+	ret = intel_atomic_lock_global_state(&new_bw_state->base);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < num_qgv_points; i++) {
+		unsigned int max_data_rate;
+
+		if (DISPLAY_VER(i915) > 11)
+			max_data_rate = tgl_max_bw(i915, num_active_planes, i);
+		else
+			max_data_rate = icl_max_bw(i915, num_active_planes, i);
+		/*
+		 * We need to know which qgv point gives us
+		 * maximum bandwidth in order to disable SAGV
+		 * if we find that we exceed SAGV block time
+		 * with watermarks. By that moment we already
+		 * have those, as it is calculated earlier in
+		 * intel_atomic_check,
+		 */
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+		if (max_data_rate >= data_rate)
+			qgv_points |= BIT(i);
+
+		drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d\n",
+			    i, max_data_rate, data_rate);
+	}
+
+	for (i = 0; i < num_psf_gv_points; i++) {
+		unsigned int max_data_rate = adl_psf_bw(i915, i);
+
+		if (max_data_rate >= data_rate)
+			psf_points |= BIT(i);
+
+		drm_dbg_kms(&i915->drm, "PSF GV point %d: max bw %d"
+			    " required %d\n",
+			    i, max_data_rate, data_rate);
+	}
+
+	/*
+	 * BSpec states that we always should have at least one allowed point
+	 * left, so if we couldn't - simply reject the configuration for obvious
+	 * reasons.
+	 */
+	if (qgv_points == 0) {
+		drm_dbg_kms(&i915->drm, "No QGV points provide sufficient memory"
+			    " bandwidth %d for display configuration(%d active planes).\n",
+			    data_rate, num_active_planes);
+		return -EINVAL;
+	}
+
+	if (num_psf_gv_points > 0 && psf_points == 0) {
+		drm_dbg_kms(&i915->drm, "No PSF GV points provide sufficient memory"
+			    " bandwidth %d for display configuration(%d active planes).\n",
+			    data_rate, num_active_planes);
+		return -EINVAL;
+	}
+
+	/*
+	 * Leave only single point with highest bandwidth, if
+	 * we can't enable SAGV due to the increased memory latency it may
+	 * cause.
+	 */
+	if (!intel_can_enable_sagv(i915, new_bw_state)) {
+		qgv_points = BIT(max_bw_point);
+		drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
+			    max_bw_point);
+	}
+
+	/*
+	 * We store the ones which need to be masked as that is what PCode
+	 * actually accepts as a parameter.
+	 */
+	new_bw_state->qgv_points_mask =
+		~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
+		  ADLS_PCODE_REQ_PSF_PT(psf_points)) &
+		icl_qgv_points_mask(i915);
+
+	/*
+	 * If the actual mask had changed we need to make sure that
+	 * the commits are serialized(in case this is a nomodeset, nonblocking)
+	 */
+	if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int intel_bw_check_qgv_points(struct drm_i915_private *i915,
+				     const struct intel_bw_state *old_bw_state,
+				     struct intel_bw_state *new_bw_state)
+{
+	unsigned int data_rate = intel_bw_data_rate(i915, new_bw_state);
+	unsigned int num_active_planes =
+			intel_bw_num_active_planes(i915, new_bw_state);
+
+	data_rate = DIV_ROUND_UP(data_rate, 1000);
+
+	return icl_find_qgv_points(i915, data_rate, num_active_planes,
+				   old_bw_state, new_bw_state);
+}
+
 static bool intel_bw_state_changed(struct drm_i915_private *i915,
 				   const struct intel_bw_state *old_bw_state,
 				   const struct intel_bw_state *new_bw_state)
@@ -1048,20 +1170,14 @@ static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *chan
 
 int intel_bw_atomic_check(struct intel_atomic_state *state)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	const struct intel_bw_state *old_bw_state;
-	struct intel_bw_state *new_bw_state;
-	unsigned int data_rate;
-	unsigned int num_active_planes;
-	int i, ret;
-	u16 qgv_points = 0, psf_points = 0;
-	unsigned int max_bw_point = 0, max_bw = 0;
-	unsigned int num_qgv_points = dev_priv->display.bw.max[0].num_qgv_points;
-	unsigned int num_psf_gv_points = dev_priv->display.bw.max[0].num_psf_gv_points;
 	bool changed = false;
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_bw_state *new_bw_state;
+	const struct intel_bw_state *old_bw_state;
+	int ret;
 
 	/* FIXME earlier gens need some checks too */
-	if (DISPLAY_VER(dev_priv) < 11)
+	if (DISPLAY_VER(i915) < 11)
 		return 0;
 
 	ret = intel_bw_check_data_rate(state, &changed);
@@ -1072,8 +1188,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	new_bw_state = intel_atomic_get_new_bw_state(state);
 
 	if (new_bw_state &&
-	    intel_can_enable_sagv(dev_priv, old_bw_state) !=
-	    intel_can_enable_sagv(dev_priv, new_bw_state))
+	    intel_can_enable_sagv(i915, old_bw_state) !=
+	    intel_can_enable_sagv(i915, new_bw_state))
 		changed = true;
 
 	/*
@@ -1083,101 +1199,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	if (!changed)
 		return 0;
 
-	ret = intel_atomic_lock_global_state(&new_bw_state->base);
+	ret = intel_bw_check_qgv_points(i915, old_bw_state, new_bw_state);
 	if (ret)
 		return ret;
 
-	data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
-	data_rate = DIV_ROUND_UP(data_rate, 1000);
-
-	num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
-
-	for (i = 0; i < num_qgv_points; i++) {
-		unsigned int max_data_rate;
-
-		if (DISPLAY_VER(dev_priv) > 11)
-			max_data_rate = tgl_max_bw(dev_priv, num_active_planes, i);
-		else
-			max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
-		/*
-		 * We need to know which qgv point gives us
-		 * maximum bandwidth in order to disable SAGV
-		 * if we find that we exceed SAGV block time
-		 * with watermarks. By that moment we already
-		 * have those, as it is calculated earlier in
-		 * intel_atomic_check,
-		 */
-		if (max_data_rate > max_bw) {
-			max_bw_point = i;
-			max_bw = max_data_rate;
-		}
-		if (max_data_rate >= data_rate)
-			qgv_points |= BIT(i);
-
-		drm_dbg_kms(&dev_priv->drm, "QGV point %d: max bw %d required %d\n",
-			    i, max_data_rate, data_rate);
-	}
-
-	for (i = 0; i < num_psf_gv_points; i++) {
-		unsigned int max_data_rate = adl_psf_bw(dev_priv, i);
-
-		if (max_data_rate >= data_rate)
-			psf_points |= BIT(i);
-
-		drm_dbg_kms(&dev_priv->drm, "PSF GV point %d: max bw %d"
-			    " required %d\n",
-			    i, max_data_rate, data_rate);
-	}
-
-	/*
-	 * BSpec states that we always should have at least one allowed point
-	 * left, so if we couldn't - simply reject the configuration for obvious
-	 * reasons.
-	 */
-	if (qgv_points == 0) {
-		drm_dbg_kms(&dev_priv->drm, "No QGV points provide sufficient memory"
-			    " bandwidth %d for display configuration(%d active planes).\n",
-			    data_rate, num_active_planes);
-		return -EINVAL;
-	}
-
-	if (num_psf_gv_points > 0 && psf_points == 0) {
-		drm_dbg_kms(&dev_priv->drm, "No PSF GV points provide sufficient memory"
-			    " bandwidth %d for display configuration(%d active planes).\n",
-			    data_rate, num_active_planes);
-		return -EINVAL;
-	}
-
-	/*
-	 * Leave only single point with highest bandwidth, if
-	 * we can't enable SAGV due to the increased memory latency it may
-	 * cause.
-	 */
-	if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
-		qgv_points = BIT(max_bw_point);
-		drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
-			    max_bw_point);
-	}
-
-	/*
-	 * We store the ones which need to be masked as that is what PCode
-	 * actually accepts as a parameter.
-	 */
-	new_bw_state->qgv_points_mask =
-		~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
-		  ADLS_PCODE_REQ_PSF_PT(psf_points)) &
-		icl_qgv_points_mask(dev_priv);
-
-	/*
-	 * If the actual mask had changed we need to make sure that
-	 * the commits are serialized(in case this is a nomodeset, nonblocking)
-	 */
-	if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
-		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
-		if (ret)
-			return ret;
-	}
-
 	return 0;
 }
 
-- 
2.34.1

[Intel-gfx] [PATCH v3 5/8] drm/i915: modify max_bw to return index to intel_bw_info

[Vinod Govindapillai]

MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.

v2: use idx to store index returned by max_bw_index functions

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index a3b8512ebe8a..a7f501131bb6 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -592,8 +592,8 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
 	i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
 }
 
-static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
-			       int num_planes, int qgv_point)
+static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv,
+				     int num_planes, int qgv_point)
 {
 	int i;
 
@@ -614,14 +614,14 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
 			return UINT_MAX;
 
 		if (num_planes >= bi->num_planes)
-			return bi->deratedbw[qgv_point];
+			return i;
 	}
 
 	return 0;
 }
 
-static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
-			       int num_planes, int qgv_point)
+static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
+				     int num_planes, int qgv_point)
 {
 	int i;
 
@@ -642,10 +642,10 @@ static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
 			return UINT_MAX;
 
 		if (num_planes <= bi->num_planes)
-			return bi->deratedbw[qgv_point];
+			return i;
 	}
 
-	return dev_priv->display.bw.max[0].deratedbw[qgv_point];
+	return 0;
 }
 
 static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
@@ -822,12 +822,19 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
 		return ret;
 
 	for (i = 0; i < num_qgv_points; i++) {
+		unsigned int idx;
 		unsigned int max_data_rate;
 
 		if (DISPLAY_VER(i915) > 11)
-			max_data_rate = tgl_max_bw(i915, num_active_planes, i);
+			idx = tgl_max_bw_index(i915, num_active_planes, i);
 		else
-			max_data_rate = icl_max_bw(i915, num_active_planes, i);
+			idx = icl_max_bw_index(i915, num_active_planes, i);
+
+		if (idx > ARRAY_SIZE(i915->display.bw.max))
+			continue;
+
+		max_data_rate = i915->display.bw.max[idx].deratedbw[i];
+
 		/*
 		 * We need to know which qgv point gives us
 		 * maximum bandwidth in order to disable SAGV
-- 
2.34.1

[Intel-gfx] [PATCH v3 6/8] drm/i915/mtl: find best QGV point and configure sagv

[Vinod Govindapillai]

From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.

Bspec: 64636

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 87 ++++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bw.h |  6 ++
 2 files changed, 91 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index a7f501131bb6..70fa469c3c20 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -802,6 +802,85 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
 	return to_intel_bw_state(bw_state);
 }
 
+static int mtl_find_qgv_points(struct drm_i915_private *i915,
+			       unsigned int data_rate,
+			       unsigned int num_active_planes,
+			       const struct intel_bw_state *old_bw_state,
+			       struct intel_bw_state *new_bw_state)
+{
+	unsigned int best_rate = UINT_MAX;
+	unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+	unsigned int qgv_peak_bw  = 0;
+	int i;
+	int ret;
+
+	ret = intel_atomic_lock_global_state(&new_bw_state->base);
+	if (ret)
+		return ret;
+
+	/*
+	 * If SAGV cannot be enabled, disable the pcode SAGV by passing all 1's
+	 * for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
+	 * not enabled. PM Demand code will clamp the value for the register
+	 */
+	if (!intel_can_enable_sagv(i915, new_bw_state)) {
+		new_bw_state->qgv_point_peakbw = UINT_MAX;
+		drm_dbg_kms(&i915->drm, "No SAGV, use UINT_MAX as peak bw.");
+		goto out;
+	}
+
+	/*
+	 * Find the best QGV point by comparing the data_rate with max data rate
+	 * offered per plane group
+	 */
+	for (i = 0; i < num_qgv_points; i++) {
+		unsigned int bw_index =
+			tgl_max_bw_index(i915, num_active_planes, i);
+		unsigned int max_data_rate;
+
+		if (bw_index > ARRAY_SIZE(i915->display.bw.max))
+			continue;
+
+		max_data_rate = i915->display.bw.max[bw_index].deratedbw[i];
+
+		if (max_data_rate < data_rate)
+			continue;
+
+		if (max_data_rate - data_rate < best_rate) {
+			best_rate = max_data_rate - data_rate;
+			qgv_peak_bw = i915->display.bw.max[bw_index].peakbw[i];
+		}
+
+		drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n",
+			    i, max_data_rate, data_rate, qgv_peak_bw);
+	}
+
+	drm_dbg_kms(&i915->drm, "Matching peaks QGV bw: %d for required data rate: %d\n",
+		    qgv_peak_bw, data_rate);
+
+	/*
+	 * The display configuration cannot be supported if no QGV point
+	 * satisfying the require data rate is found
+	 */
+	if (qgv_peak_bw == 0) {
+		drm_dbg_kms(&i915->drm, "No QGV points for bw %d for display configuration(%d active planes).\n",
+			    data_rate, num_active_planes);
+		return -EINVAL;
+	}
+
+	/* MTL PM DEMAND expects QGV BW parameter in multiples of 100 mbps */
+	new_bw_state->qgv_point_peakbw = qgv_peak_bw / 100;
+
+out:
+	if (new_bw_state->qgv_point_peakbw != old_bw_state->qgv_point_peakbw)  {
+		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 static int icl_find_qgv_points(struct drm_i915_private *i915,
 			       unsigned int data_rate,
 			       unsigned int num_active_planes,
@@ -927,8 +1006,12 @@ static int intel_bw_check_qgv_points(struct drm_i915_private *i915,
 
 	data_rate = DIV_ROUND_UP(data_rate, 1000);
 
-	return icl_find_qgv_points(i915, data_rate, num_active_planes,
-				   old_bw_state, new_bw_state);
+	if (DISPLAY_VER(i915) >= 14)
+		return mtl_find_qgv_points(i915, data_rate, num_active_planes,
+					   old_bw_state, new_bw_state);
+	else
+		return icl_find_qgv_points(i915, data_rate, num_active_planes,
+					   old_bw_state, new_bw_state);
 }
 
 static bool intel_bw_state_changed(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index f20292143745..fc32f1eace85 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -34,6 +34,12 @@ struct intel_bw_state {
 	/* bitmask of active pipes */
 	u8 active_pipes;
 
+	/*
+	 * From MTL onwards, to lock a QGV point, punit expects the peak BW of
+	 * the selected QGV point as the parameter
+	 */
+	unsigned int qgv_point_peakbw;
+
 	/*
 	 * Current QGV points mask, which restricts
 	 * some particular SAGV states, not to confuse
-- 
2.34.1

[Intel-gfx] [PATCH v3 7/8] drm/i915/mtl: Add support for PM DEMAND

[Vinod Govindapillai]

From: Mika Kahola <mika.kahola@intel.com>

Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to use REG_BIT
for a register that we touched(GEN8_DE_MISC_IER _MMIO).

Wa_14016740474 is added which applies to Xe_LPD+ display

v2: checkpatch warning fixes, simplify program pmdemand part

v3: update to dbufs and pipes values to pmdemand register(stan)
    Removed the macro usage in update_pmdemand_values()

Bspec: 66451, 64636, 64602, 64603
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   3 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   7 +
 .../gpu/drm/i915/display/intel_display_core.h |   6 +
 .../drm/i915/display/intel_display_driver.c   |   7 +
 .../drm/i915/display/intel_display_power.c    |   8 +
 drivers/gpu/drm/i915/display/intel_pmdemand.c | 455 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_pmdemand.h |  24 +
 drivers/gpu/drm/i915/i915_irq.c               |  21 +-
 drivers/gpu/drm/i915/i915_reg.h               |  36 +-
 9 files changed, 562 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9af76e376ca9..eb899fa86e51 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -281,7 +281,8 @@ i915-y += \
 	display/i9xx_wm.o \
 	display/skl_scaler.o \
 	display/skl_universal_plane.o \
-	display/skl_watermark.o
+	display/skl_watermark.o \
+	display/intel_pmdemand.o
 i915-$(CONFIG_ACPI) += \
 	display/intel_acpi.o \
 	display/intel_opregion.o
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bf391a6cd8d6..f98e235fadc6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -99,6 +99,7 @@
 #include "intel_pcode.h"
 #include "intel_pipe_crc.h"
 #include "intel_plane_initial.h"
+#include "intel_pmdemand.h"
 #include "intel_pps.h"
 #include "intel_psr.h"
 #include "intel_sdvo.h"
@@ -6306,6 +6307,10 @@ int intel_atomic_check(struct drm_device *dev,
 			return ret;
 	}
 
+	ret = intel_pmdemand_atomic_check(state);
+	if (ret)
+		goto fail;
+
 	ret = intel_atomic_check_crtcs(state);
 	if (ret)
 		goto fail;
@@ -6960,6 +6965,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	}
 
 	intel_sagv_pre_plane_update(state);
+	intel_pmdemand_pre_plane_update(state);
 
 	/* Complete the events for pipes that have now been disabled */
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
@@ -7070,6 +7076,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		intel_verify_planes(state);
 
 	intel_sagv_post_plane_update(state);
+	intel_pmdemand_post_plane_update(state);
 
 	drm_atomic_helper_commit_hw_done(&state->base);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 9f66d734edf6..9471a052aa57 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -345,6 +345,12 @@ struct intel_display {
 		struct intel_global_obj obj;
 	} dbuf;
 
+	struct {
+		wait_queue_head_t waitqueue;
+		struct mutex lock;
+		struct intel_global_obj obj;
+	} pmdemand;
+
 	struct {
 		/*
 		 * dkl.phy_lock protects against concurrent access of the
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 60ce10fc7205..79853d8c3240 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -47,6 +47,7 @@
 #include "intel_opregion.h"
 #include "intel_overlay.h"
 #include "intel_plane_initial.h"
+#include "intel_pmdemand.h"
 #include "intel_pps.h"
 #include "intel_quirks.h"
 #include "intel_vga.h"
@@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
 	if (ret < 0)
 		goto cleanup_vga;
 
+	intel_pmdemand_init(i915);
+
 	intel_power_domains_init_hw(i915, false);
 
 	if (!HAS_DISPLAY(i915))
@@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
 	if (ret)
 		goto cleanup_vga_client_pw_domain_dmc;
 
+	ret = intel_pmdemand_state_init(i915);
+	if (ret)
+		goto cleanup_vga_client_pw_domain_dmc;
+
 	init_llist_head(&i915->display.atomic_helper.free_list);
 	INIT_WORK(&i915->display.atomic_helper.free_work,
 		  intel_atomic_helper_free_state_worker);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 5150069f3f82..f5c5a486efbc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -20,6 +20,7 @@
 #include "intel_mchbar_regs.h"
 #include "intel_pch_refclk.h"
 #include "intel_pcode.h"
+#include "intel_pmdemand.h"
 #include "intel_pps_regs.h"
 #include "intel_snps_phy.h"
 #include "skl_watermark.h"
@@ -1085,6 +1086,10 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
 	dev_priv->display.dbuf.enabled_slices =
 		intel_enabled_dbuf_slices_mask(dev_priv);
 
+	if (DISPLAY_VER(dev_priv) >= 14)
+		intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
+					    dev_priv->display.dbuf.enabled_slices);
+
 	/*
 	 * Just power up at least 1 slice, we will
 	 * figure out later which slices we have and what we need.
@@ -1096,6 +1101,9 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
 {
 	gen9_dbuf_slices_update(dev_priv, 0);
+
+	if (DISPLAY_VER(dev_priv) >= 14)
+		intel_program_dbuf_pmdemand(dev_priv, 0);
 }
 
 static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
new file mode 100644
index 000000000000..df6429e7059d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include <linux/bitops.h>
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "intel_bw.h"
+#include "intel_cdclk.h"
+#include "intel_cx0_phy.h"
+#include "intel_de.h"
+#include "intel_display.h"
+#include "intel_display_trace.h"
+#include "intel_pmdemand.h"
+#include "skl_watermark.h"
+
+struct intel_pmdemand_state {
+	struct intel_global_state base;
+
+	u16 qclk_gv_bw;
+	u8 voltage_index;
+	u8 qclk_gv_index;
+	u8 active_pipes;
+	u8 dbufs;
+	u8 active_phys_plls_mask;
+	u16 cdclk_freq_mhz;
+	u16 ddiclk_freq_mhz;
+	u8 scalers;
+};
+
+#define to_intel_pmdemand_state(x) container_of((x), struct intel_pmdemand_state, base)
+
+static struct intel_global_state *
+intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
+{
+	struct intel_pmdemand_state *pmdmnd_state;
+
+	pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state), GFP_KERNEL);
+	if (!pmdmnd_state)
+		return NULL;
+
+	return &pmdmnd_state->base;
+}
+
+static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
+					 struct intel_global_state *state)
+{
+	kfree(state);
+}
+
+static const struct intel_global_state_funcs intel_pmdemand_funcs = {
+	.atomic_duplicate_state = intel_pmdemand_duplicate_state,
+	.atomic_destroy_state = intel_pmdemand_destroy_state,
+};
+
+static struct intel_pmdemand_state *
+intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_global_state *pmdemand_state;
+
+	pmdemand_state =
+		intel_atomic_get_global_obj_state(state,
+						  &i915->display.pmdemand.obj);
+	if (IS_ERR(pmdemand_state))
+		return ERR_CAST(pmdemand_state);
+
+	return to_intel_pmdemand_state(pmdemand_state);
+}
+
+static struct intel_pmdemand_state *
+intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_global_state *pmdemand_state;
+
+	pmdemand_state = intel_atomic_get_old_global_obj_state(state, &i915->display.pmdemand.obj);
+
+	return to_intel_pmdemand_state(pmdemand_state);
+}
+
+static struct intel_pmdemand_state *
+intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_global_state *pmdemand_state;
+
+	pmdemand_state = intel_atomic_get_new_global_obj_state(state, &i915->display.pmdemand.obj);
+
+	return to_intel_pmdemand_state(pmdemand_state);
+}
+
+int intel_pmdemand_state_init(struct drm_i915_private *i915)
+{
+	struct intel_pmdemand_state *pmdemand_state;
+
+	pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
+	if (!pmdemand_state)
+		return -ENOMEM;
+
+	intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
+				     &pmdemand_state->base,
+				     &intel_pmdemand_funcs);
+
+
+	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+		/* Wa_14016740474 */
+		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
+
+	return 0;
+}
+
+void intel_pmdemand_init(struct drm_i915_private *i915)
+{
+	mutex_init(&i915->display.pmdemand.lock);
+	init_waitqueue_head(&i915->display.pmdemand.waitqueue);
+}
+
+static bool pmdemand_needs_update(struct intel_atomic_state *state)
+{
+	bool changed = false;
+	struct intel_crtc *crtc;
+	int i;
+	const struct intel_bw_state *new_bw_state, *old_bw_state;
+	const struct intel_cdclk_state *new_cdclk_state;
+	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		new_bw_state = intel_atomic_get_new_bw_state(state);
+		old_bw_state = intel_atomic_get_old_bw_state(state);
+
+		new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+		old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+
+		new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+
+		if ((new_bw_state && new_bw_state->qgv_point_peakbw !=
+		     old_bw_state->qgv_point_peakbw) ||
+		    (new_dbuf_state && new_dbuf_state->active_pipes !=
+		     old_dbuf_state->active_pipes) || new_cdclk_state)
+			changed = true;
+
+		/*
+		 * break needs to be removed, if some crtc_state dependent
+		 * parameters are added here
+		 */
+		break;
+	}
+
+	return changed;
+}
+
+int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	int port_clock = 0;
+	struct intel_crtc *crtc;
+	struct intel_encoder *encoder;
+	const struct intel_bw_state *new_bw_state;
+	const struct intel_cdclk_state *new_cdclk_state;
+	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+	const struct intel_dbuf_state *new_dbuf_state;
+	struct intel_pmdemand_state *new_pmdemand_state;
+	enum phy phy;
+	int i, ret;
+
+	if (DISPLAY_VER(i915) < 14)
+		return 0;
+
+	if (!pmdemand_needs_update(state))
+		return 0;
+
+	new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
+	if (IS_ERR(new_pmdemand_state))
+		return PTR_ERR(new_pmdemand_state);
+
+	ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
+	if (ret)
+		return ret;
+
+	/* Punit figures out the voltage index based on bandwidth*/
+	new_bw_state = intel_atomic_get_bw_state(state);
+	if (IS_ERR(new_bw_state))
+		return PTR_ERR(new_bw_state);
+
+	/* firmware will calculate the qclck_gc_index, requirement is set to 0 */
+	new_pmdemand_state->qclk_gv_index = 0;
+	new_pmdemand_state->qclk_gv_bw =
+		min_t(u16, new_bw_state->qgv_point_peakbw, 0xffff);
+
+	new_dbuf_state = intel_atomic_get_dbuf_state(state);
+	if (IS_ERR(new_dbuf_state))
+		return PTR_ERR(new_dbuf_state);
+
+	i = hweight8(new_dbuf_state->active_pipes);
+	new_pmdemand_state->active_pipes = min(i, 3);
+
+	new_cdclk_state = intel_atomic_get_cdclk_state(state);
+	if (IS_ERR(new_cdclk_state))
+		return PTR_ERR(new_cdclk_state);
+
+	new_pmdemand_state->voltage_index =
+		new_cdclk_state->logical.voltage_level;
+	/* KHz to MHz */
+	new_pmdemand_state->cdclk_freq_mhz =
+		DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
+
+	new_pmdemand_state->active_phys_plls_mask = 0;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		if (!new_crtc_state->hw.active)
+			continue;
+
+		encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+		if (!encoder)
+			continue;
+
+		phy = intel_port_to_phy(i915, encoder->port);
+
+		if (intel_is_c10phy(i915, phy))
+			new_pmdemand_state->active_phys_plls_mask |= BIT(phy);
+
+		port_clock = max(port_clock, new_crtc_state->port_clock);
+	}
+
+	/* To MHz */
+	new_pmdemand_state->ddiclk_freq_mhz = DIV_ROUND_UP(port_clock, 1000);
+
+	/*
+	 * Setting scalers to max as it can not be calculated during flips and
+	 * fastsets without taking global states locks.
+	 */
+	new_pmdemand_state->scalers = 7;
+
+	ret = intel_atomic_serialize_global_state(&new_pmdemand_state->base);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
+{
+	return !((intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
+		  XELPDP_PMDEMAND_REQ_ENABLE) ||
+		(intel_de_read(i915, GEN12_DCPR_STATUS_1) &
+		 XELPDP_PMDEMAND_INFLIGHT_STATUS));
+}
+
+static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
+{
+	return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
+		 XELPDP_PMDEMAND_REQ_ENABLE);
+}
+
+static int intel_pmdemand_wait(struct drm_i915_private *i915)
+{
+	DEFINE_WAIT(wait);
+	int ret;
+	const unsigned int timeout_ms = 10;
+
+	ret = wait_event_timeout(i915->display.pmdemand.waitqueue,
+				 intel_pmdemand_req_complete(i915),
+				 msecs_to_jiffies_timeout(timeout_ms));
+	if (ret == 0)
+		drm_err(&i915->drm,
+			"timed out waiting for Punit PM Demand Response\n");
+
+	return ret;
+}
+
+/* Required to be programmed during Display Init Sequences. */
+void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
+				 u8 dbuf_slices)
+{
+	u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
+
+	mutex_lock(&i915->display.pmdemand.lock);
+	if (drm_WARN_ON(&i915->drm,
+			!intel_pmdemand_check_prev_transaction(i915)))
+		goto unlock;
+
+	intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
+		     XELPDP_PMDEMAND_DBUFS_MASK, XELPDP_PMDEMAND_DBUFS(dbufs));
+	intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
+		     XELPDP_PMDEMAND_REQ_ENABLE);
+
+	intel_pmdemand_wait(i915);
+
+unlock:
+	mutex_unlock(&i915->display.pmdemand.lock);
+}
+
+static void update_pmdemand_values(const struct intel_pmdemand_state *new,
+				   const struct intel_pmdemand_state *old,
+				   u32 *reg1, u32 *reg2)
+{
+	u32 plls, tmp;
+
+	/*
+	 * The pmdemand parameter updates happens in two steps. Pre plane and
+	 * post plane updates. During the pre plane, as DE might still be
+	 * handling with some old operations, to avoid unwanted performance
+	 * issues, program the pmdemand parameters with higher of old and new
+	 * values. And then after once settled, use the new parameter values
+	 * as part of the post plane update.
+	 */
+
+	/* Set 1*/
+	*reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_BW_MASK;
+	tmp = old ? max(old->qclk_gv_bw, new->qclk_gv_bw) : new->qclk_gv_bw;
+	*reg1 |= XELPDP_PMDEMAND_QCLK_GV_BW(tmp);
+
+	*reg1 &= ~XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK;
+	tmp = old ? max(old->voltage_index, new->voltage_index) :
+		    new->voltage_index;
+	*reg1 |= XELPDP_PMDEMAND_VOLTAGE_INDEX(tmp);
+
+	*reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK;
+	tmp = old ? max(old->qclk_gv_index, new->qclk_gv_index) :
+		    new->qclk_gv_index;
+	*reg1 |= XELPDP_PMDEMAND_QCLK_GV_INDEX(tmp);
+
+	*reg1 &= ~XELPDP_PMDEMAND_PIPES_MASK;
+	tmp = old ? max(old->active_pipes, new->active_pipes) :
+		    new->active_pipes;
+	*reg1 |= XELPDP_PMDEMAND_PIPES(tmp);
+
+	*reg1 &= ~XELPDP_PMDEMAND_PHYS_MASK;
+	plls = hweight32(new->active_phys_plls_mask);
+	if (old)
+		plls = max(plls, hweight32(old->active_phys_plls_mask));
+	*reg1 |= XELPDP_PMDEMAND_PHYS(plls);
+
+	/* Set 2*/
+	*reg2 &= ~XELPDP_PMDEMAND_CDCLK_FREQ_MASK;
+	tmp = old ? max(old->cdclk_freq_mhz, new->cdclk_freq_mhz) :
+		    new->cdclk_freq_mhz;
+	*reg2 |= XELPDP_PMDEMAND_CDCLK_FREQ(tmp);
+
+	*reg2 &= ~XELPDP_PMDEMAND_DDICLK_FREQ_MASK;
+	tmp = old ? max(old->ddiclk_freq_mhz, new->ddiclk_freq_mhz) :
+		    new->ddiclk_freq_mhz;
+	*reg2 |= XELPDP_PMDEMAND_DDICLK_FREQ(tmp);
+
+	/* Hard code scalers to 7*/
+	*reg2 &= ~XELPDP_PMDEMAND_SCALERS_MASK;
+	tmp = old ? max(old->scalers, new->scalers) : new->scalers;
+	*reg2 |= XELPDP_PMDEMAND_SCALERS(tmp);
+
+	/*
+	 * Active_PLLs starts with 1 because of CDCLK PLL.
+	 * TODO: Missing to account genlock filter when it gets used.
+	 */
+	*reg2 &= ~XELPDP_PMDEMAND_PLLS_MASK;
+	*reg2 |= XELPDP_PMDEMAND_PLLS(plls + 1);
+}
+
+static void intel_program_pmdemand(struct drm_i915_private *i915,
+				   const struct intel_pmdemand_state *new,
+				   const struct intel_pmdemand_state *old)
+{
+	bool changed = false;
+	u32 reg1, mod_reg1;
+	u32 reg2, mod_reg2;
+
+	mutex_lock(&i915->display.pmdemand.lock);
+	if (drm_WARN_ON(&i915->drm,
+			!intel_pmdemand_check_prev_transaction(i915)))
+		goto unlock;
+
+	reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
+	mod_reg1 = reg1;
+
+	reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
+	mod_reg2 = reg2;
+
+	update_pmdemand_values(new, old, &mod_reg1, &mod_reg2);
+
+	if (reg1 != mod_reg1) {
+		intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
+			       mod_reg1);
+		changed = true;
+	}
+
+	if (reg2 != mod_reg2) {
+		intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
+			       mod_reg2);
+		changed = true;
+	}
+
+	/* Initiate pm demand request only if register values are changed */
+	if (changed) {
+		drm_dbg_kms(&i915->drm,
+			    "initate pmdemand request values: (0x%x 0x%x)\n",
+			    mod_reg1, mod_reg2);
+
+		intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
+			     XELPDP_PMDEMAND_REQ_ENABLE);
+
+		intel_pmdemand_wait(i915);
+	}
+
+unlock:
+	mutex_unlock(&i915->display.pmdemand.lock);
+}
+
+static bool
+intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
+			     const struct intel_pmdemand_state *old)
+{
+	return memcmp(&new->qclk_gv_bw, &old->qclk_gv_bw,
+		      sizeof(*new) - offsetof(typeof(*new), qclk_gv_bw)) != 0;
+}
+
+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_pmdemand_state *new_pmdmnd_state =
+		intel_atomic_get_new_pmdemand_state(state);
+	const struct intel_pmdemand_state *old_pmdmnd_state =
+		intel_atomic_get_old_pmdemand_state(state);
+
+	if (DISPLAY_VER(i915) < 14)
+		return;
+
+	if (!new_pmdmnd_state ||
+	    !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
+		return;
+
+	intel_program_pmdemand(i915, new_pmdmnd_state, old_pmdmnd_state);
+}
+
+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_pmdemand_state *new_pmdmnd_state =
+		intel_atomic_get_new_pmdemand_state(state);
+	const struct intel_pmdemand_state *old_pmdmnd_state =
+		intel_atomic_get_old_pmdemand_state(state);
+
+	if (DISPLAY_VER(i915) < 14)
+		return;
+
+	if (!new_pmdmnd_state ||
+	    !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
+		return;
+
+	intel_program_pmdemand(i915, new_pmdmnd_state, NULL);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h b/drivers/gpu/drm/i915/display/intel_pmdemand.h
new file mode 100644
index 000000000000..0114f4e0225a
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_PMDEMAND_H__
+#define __INTEL_PMDEMAND_H__
+
+#include <linux/types.h>
+
+struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_crtc_state;
+struct intel_plane_state;
+
+void intel_pmdemand_init(struct drm_i915_private *i915);
+int intel_pmdemand_state_init(struct drm_i915_private *i915);
+void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
+				 u8 dbuf_slices);
+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
+int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
+
+#endif /* __INTEL_PMDEMAND_H__ */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2b94b8ca8ec9..907fa3aee179 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -41,6 +41,7 @@
 #include "display/intel_fifo_underrun.h"
 #include "display/intel_hotplug.h"
 #include "display/intel_lpe_audio.h"
+#include "display/intel_pmdemand.h"
 #include "display/intel_psr.h"
 #include "display/intel_psr_regs.h"
 
@@ -1986,12 +1987,25 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
 		return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
 }
 
+static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
+{
+	wake_up_all(&dev_priv->display.pmdemand.waitqueue);
+}
+
 static void
 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 {
 	bool found = false;
 
-	if (iir & GEN8_DE_MISC_GSE) {
+	if (DISPLAY_VER(dev_priv) >= 14 &&
+	    (iir & (XELPDP_PMDEMAND_RSP | XELPDP_PMDEMAND_RSPTOUT_ERR))) {
+		if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
+			drm_dbg(&dev_priv->drm,
+				"Error waiting for Punit PM Demand Response\n");
+
+		intel_pmdemand_irq_handler(dev_priv);
+		found = true;
+	} else if (iir & GEN8_DE_MISC_GSE) {
 		intel_opregion_asle_intr(dev_priv);
 		found = true;
 	}
@@ -3742,7 +3756,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 		de_port_masked |= BXT_DE_PORT_GMBUS;
 
-	if (DISPLAY_VER(dev_priv) >= 11) {
+	if (DISPLAY_VER(dev_priv) >= 14)
+		de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
+				  XELPDP_PMDEMAND_RSP;
+	else if (DISPLAY_VER(dev_priv) >= 11) {
 		enum port port;
 
 		if (intel_bios_is_dsi_present(dev_priv, &port))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dde6e91055bd..60c007aea1ce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4426,8 +4426,10 @@
 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
-#define  GEN8_DE_MISC_GSE		(1 << 27)
-#define  GEN8_DE_EDP_PSR		(1 << 19)
+#define  XELPDP_PMDEMAND_RSPTOUT_ERR	REG_BIT(27)
+#define  GEN8_DE_MISC_GSE		REG_BIT(27)
+#define  GEN8_DE_EDP_PSR		REG_BIT(19)
+#define  XELPDP_PMDEMAND_RSP		REG_BIT(3)
 
 #define GEN8_PCU_ISR _MMIO(0x444e0)
 #define GEN8_PCU_IMR _MMIO(0x444e4)
@@ -4512,6 +4514,33 @@
 #define  XELPDP_DP_ALT_HPD_LONG_DETECT		REG_BIT(1)
 #define  XELPDP_DP_ALT_HPD_SHORT_DETECT		REG_BIT(0)
 
+#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)		_MMIO(0x45230 + 4 * (dword))
+#define  XELPDP_PMDEMAND_QCLK_GV_BW_MASK		REG_GENMASK(31, 16)
+#define  XELPDP_PMDEMAND_QCLK_GV_BW(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
+#define  XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK		REG_GENMASK(14, 12)
+#define  XELPDP_PMDEMAND_VOLTAGE_INDEX(x)		REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
+#define  XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK		REG_GENMASK(11, 8)
+#define  XELPDP_PMDEMAND_QCLK_GV_INDEX(x)		REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
+#define  XELPDP_PMDEMAND_PIPES_MASK			REG_GENMASK(7, 6)
+#define  XELPDP_PMDEMAND_PIPES(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
+#define  XELPDP_PMDEMAND_DBUFS_MASK			REG_GENMASK(5, 4)
+#define  XELPDP_PMDEMAND_DBUFS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
+#define  XELPDP_PMDEMAND_PHYS_MASK			REG_GENMASK(2, 0)
+#define  XELPDP_PMDEMAND_PHYS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
+
+#define  XELPDP_PMDEMAND_REQ_ENABLE			REG_BIT(31)
+#define  XELPDP_PMDEMAND_CDCLK_FREQ_MASK		REG_GENMASK(30, 20)
+#define  XELPDP_PMDEMAND_CDCLK_FREQ(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
+#define  XELPDP_PMDEMAND_DDICLK_FREQ_MASK		REG_GENMASK(18, 8)
+#define  XELPDP_PMDEMAND_DDICLK_FREQ(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
+#define  XELPDP_PMDEMAND_SCALERS_MASK			REG_GENMASK(6, 4)
+#define  XELPDP_PMDEMAND_SCALERS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
+#define  XELPDP_PMDEMAND_PLLS_MASK			REG_GENMASK(2, 0)
+#define  XELPDP_PMDEMAND_PLLS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
+
+#define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
+#define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
+
 #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
 #define   ILK_ELPIN_409_SELECT	REG_BIT(25)
@@ -4671,6 +4700,9 @@
 #define   DCPR_SEND_RESP_IMM			REG_BIT(25)
 #define   DCPR_CLEAR_MEMSTAT_DIS		REG_BIT(24)
 
+#define XELPD_CHICKEN_DCPR_3			_MMIO(0x46438)
+#define   DMD_RSP_TIMEOUT_DISABLE		REG_BIT(19)
+
 #define SKL_DFSM			_MMIO(0x51000)
 #define   SKL_DFSM_DISPLAY_PM_DISABLE	(1 << 27)
 #define   SKL_DFSM_DISPLAY_HDCP_DISABLE	(1 << 25)
-- 
2.34.1

[Intel-gfx] [PATCH v3 8/8] drm/i915/display: provision to suppress drm_warn in intel_get_crtc_new_encoder

[Vinod Govindapillai]

While configuring pmdemand parameters, there could be
intel_get_crtc_new_encoder call where encoders could be 0. To avoid
invoking drm_warn in such cases, use a parameter to indicate drm_warn
should be suppressed.

v2: checkpatch warning fixes

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c     | 10 ++++++----
 drivers/gpu/drm/i915/display/intel_display.h     |  3 ++-
 drivers/gpu/drm/i915/display/intel_dpll.c        |  8 ++++----
 drivers/gpu/drm/i915/display/intel_pch_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_snps_phy.c    |  2 +-
 7 files changed, 16 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 83180074b512..e91fdd5a26c3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1879,7 +1879,7 @@ void intel_c10pll_state_verify(struct intel_atomic_state *state,
 	    !intel_crtc_needs_fastset(new_crtc_state))
 		return;
 
-	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+	encoder = intel_get_crtc_new_encoder(state, new_crtc_state, true);
 	phy = intel_port_to_phy(i915, encoder->port);
 
 	if (!intel_is_c10phy(i915, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f98e235fadc6..4cadda4acce4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -763,7 +763,8 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
  */
 struct intel_encoder *
 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
-			   const struct intel_crtc_state *crtc_state)
+			   const struct intel_crtc_state *crtc_state,
+			   bool warn)
 {
 	const struct drm_connector_state *connector_state;
 	const struct drm_connector *connector;
@@ -782,9 +783,10 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 		num_encoders++;
 	}
 
-	drm_WARN(state->base.dev, num_encoders != 1,
-		 "%d encoders for pipe %c\n",
-		 num_encoders, pipe_name(master_crtc->pipe));
+	if (warn)
+		drm_WARN(state->base.dev, num_encoders != 1,
+			 "%d encoders for pipe %c\n",
+			 num_encoders, pipe_name(master_crtc->pipe));
 
 	return encoder;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ac95961f68ba..4620ed991ff0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -501,7 +501,8 @@ bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
 
 struct intel_encoder *
 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
-			   const struct intel_crtc_state *crtc_state);
+			   const struct intel_crtc_state *crtc_state,
+			   bool warn);
 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 				  struct intel_plane *plane);
 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index a9fbef0fa817..9d30f273130e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -940,7 +940,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder =
-		intel_get_crtc_new_encoder(state, crtc_state);
+		intel_get_crtc_new_encoder(state, crtc_state, true);
 	int ret;
 
 	if (DISPLAY_VER(dev_priv) < 11 &&
@@ -969,7 +969,7 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder =
-		intel_get_crtc_new_encoder(state, crtc_state);
+		intel_get_crtc_new_encoder(state, crtc_state, true);
 
 	if (DISPLAY_VER(dev_priv) < 11 &&
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
@@ -984,7 +984,7 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder =
-		intel_get_crtc_new_encoder(state, crtc_state);
+		intel_get_crtc_new_encoder(state, crtc_state, true);
 	int ret;
 
 	ret = intel_mpllb_calc_state(crtc_state, encoder);
@@ -1003,7 +1003,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder =
-		intel_get_crtc_new_encoder(state, crtc_state);
+		intel_get_crtc_new_encoder(state, crtc_state, true);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 	int ret;
 
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 2411fe4dee8b..fa91a9f66422 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -427,7 +427,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 
-		port = intel_get_crtc_new_encoder(state, crtc_state)->port;
+		port = intel_get_crtc_new_encoder(state, crtc_state, true)->port;
 		drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
 		temp |= TRANS_DP_PORT_SEL(port);
 
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index df6429e7059d..046bf3b7d208 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -216,7 +216,7 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
 		if (!new_crtc_state->hw.active)
 			continue;
 
-		encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+		encoder = intel_get_crtc_new_encoder(state, new_crtc_state, false);
 		if (!encoder)
 			continue;
 
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index a72677bf617b..a4d56a2a670a 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -2012,7 +2012,7 @@ void intel_mpllb_state_verify(struct intel_atomic_state *state,
 	    !intel_crtc_needs_fastset(new_crtc_state))
 		return;
 
-	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+	encoder = intel_get_crtc_new_encoder(state, new_crtc_state, true);
 	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
 
 #define MPLLB_CHECK(__name)						\
-- 
2.34.1

Re: [Intel-gfx] [PATCH v3 2/8] drm/i915: update the QGV point frequency calculations

[Ville Syrjälä]

On Thu, Apr 27, 2023 at 06:00:10PM +0300, Vinod Govindapillai wrote:
> >From MTL onwwards, pcode locks the QGV point based on peak BW of
> the intended QGV point passed by the driver. So the peak BW
> calculation must match the value expected by the pcode. Update
> the calculations as per the Bspec.
> 
> Bspec: 64636
> 
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index ab405c48ca3a..25ae4e5834d3 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
>  	val2 = intel_uncore_read(&dev_priv->uncore,
>  				 MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
>  	dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
> -	sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
> +	sp->dclk = (16667 * dclk + 500) / 1000;

Don't hand roll rounding.

>  	sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
>  	sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
>  
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev4)

[Patchwork]

== Series Details ==

Series: mtl: add support for pmdemand (rev4)
URL   : https://patchwork.freedesktop.org/series/116949/
State : warning

== Summary ==

Error: dim checkpatch failed
874300201d54 drm/i915: fix the derating percentage for MTL
0351498e12a8 drm/i915: update the QGV point frequency calculations
a19eee5cbb59 drm/i915: store the peak bw per QGV point
7165b8529aef drm/i915: extract intel_bw_check_qgv_points()
08a7346302d0 drm/i915: modify max_bw to return index to intel_bw_info
0f2930d76473 drm/i915/mtl: find best QGV point and configure sagv
5bd2838f8dfc drm/i915/mtl: Add support for PM DEMAND
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:97: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#97: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:350:
+		struct mutex lock;

-:170: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#170: 
new file mode 100644

-:281: CHECK:LINE_SPACING: Please don't use multiple blank lines
#281: FILE: drivers/gpu/drm/i915/display/intel_pmdemand.c:107:
+
+

-:734: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#734: FILE: drivers/gpu/drm/i915/i915_reg.h:4519:
+#define  XELPDP_PMDEMAND_QCLK_GV_BW(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)

-:736: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#736: FILE: drivers/gpu/drm/i915/i915_reg.h:4521:
+#define  XELPDP_PMDEMAND_VOLTAGE_INDEX(x)		REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)

-:738: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#738: FILE: drivers/gpu/drm/i915/i915_reg.h:4523:
+#define  XELPDP_PMDEMAND_QCLK_GV_INDEX(x)		REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)

-:740: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#740: FILE: drivers/gpu/drm/i915/i915_reg.h:4525:
+#define  XELPDP_PMDEMAND_PIPES(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)

-:742: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#742: FILE: drivers/gpu/drm/i915/i915_reg.h:4527:
+#define  XELPDP_PMDEMAND_DBUFS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)

-:748: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#748: FILE: drivers/gpu/drm/i915/i915_reg.h:4533:
+#define  XELPDP_PMDEMAND_CDCLK_FREQ(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)

-:750: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#750: FILE: drivers/gpu/drm/i915/i915_reg.h:4535:
+#define  XELPDP_PMDEMAND_DDICLK_FREQ(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)

-:752: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#752: FILE: drivers/gpu/drm/i915/i915_reg.h:4537:
+#define  XELPDP_PMDEMAND_SCALERS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)

total: 0 errors, 9 warnings, 2 checks, 680 lines checked
0f22628358d0 drm/i915/display: provision to suppress drm_warn in intel_get_crtc_new_encoder

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for mtl: add support for pmdemand (rev4)

[Patchwork]

== Series Details ==

Series: mtl: add support for pmdemand (rev4)
URL   : https://patchwork.freedesktop.org/series/116949/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for mtl: add support for pmdemand (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4282 bytes --]

== Series Details ==

Series: mtl: add support for pmdemand (rev4)
URL   : https://patchwork.freedesktop.org/series/116949/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13071 -> Patchwork_116949v4
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/index.html

Participating hosts (38 -> 36)
------------------------------

  Missing    (2): bat-mtlp-8 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_116949v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
    - bat-dg2-8:          [PASS][1] -> [FAIL][2] ([i915#7932]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-glk-j4005:       [FAIL][3] ([i915#7916]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@requests:
    - {bat-mtlp-6}:       [ABORT][5] ([i915#7920]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/bat-mtlp-6/igt@i915_selftest@live@requests.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/bat-mtlp-6/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@slpc:
    - bat-rpls-1:         [FAIL][7] ([i915#6997]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/bat-rpls-1/igt@i915_selftest@live@slpc.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/bat-rpls-1/igt@i915_selftest@live@slpc.html

  
#### Warnings ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-kbl-8809g:       [ABORT][9] -> [ABORT][10] ([i915#8397])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/fi-kbl-8809g/igt@core_hotunplug@unbind-rebind.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/fi-kbl-8809g/igt@core_hotunplug@unbind-rebind.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7916]: https://gitlab.freedesktop.org/drm/intel/issues/7916
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
  [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
  [i915#8397]: https://gitlab.freedesktop.org/drm/intel/issues/8397


Build changes
-------------

  * Linux: CI_DRM_13071 -> Patchwork_116949v4

  CI-20190529: 20190529
  CI_DRM_13071: b9458e7075652669ec0e04abe039a5ed001701fe @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7273: f40ef4b058466219968b7792d22ff0648b82396b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_116949v4: b9458e7075652669ec0e04abe039a5ed001701fe @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

72ff61a5f452 drm/i915/display: provision to suppress drm_warn in intel_get_crtc_new_encoder
c5df808bc840 drm/i915/mtl: Add support for PM DEMAND
ca6f9668a8ee drm/i915/mtl: find best QGV point and configure sagv
b5d9b3816438 drm/i915: modify max_bw to return index to intel_bw_info
80e5807febdc drm/i915: extract intel_bw_check_qgv_points()
1f73baa912be drm/i915: store the peak bw per QGV point
9866a15853f6 drm/i915: update the QGV point frequency calculations
1cff5f944d75 drm/i915: fix the derating percentage for MTL

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/index.html

[-- Attachment #2: Type: text/html, Size: 4774 bytes --]

Re: [Intel-gfx] [PATCH v3 7/8] drm/i915/mtl: Add support for PM DEMAND

[Gustavo Sousa]

Quoting Vinod Govindapillai (2023-04-27 12:00:15)
>From: Mika Kahola <mika.kahola@intel.com>
>
>Display14 introduces a new way to instruct the PUnit with
>power and bandwidth requirements of DE. Add the functionality
>to program the registers and handle waits using interrupts.
>The current wait time for timeouts is programmed for 10 msecs to
>factor in the worst case scenarios. Changes made to use REG_BIT
>for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
>Wa_14016740474 is added which applies to Xe_LPD+ display
>
>v2: checkpatch warning fixes, simplify program pmdemand part
>
>v3: update to dbufs and pipes values to pmdemand register(stan)
>    Removed the macro usage in update_pmdemand_values()
>
>Bspec: 66451, 64636, 64602, 64603
>Cc: Matt Atwood <matthew.s.atwood@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>---
> drivers/gpu/drm/i915/Makefile                 |   3 +-
> drivers/gpu/drm/i915/display/intel_display.c  |   7 +
> .../gpu/drm/i915/display/intel_display_core.h |   6 +
> .../drm/i915/display/intel_display_driver.c   |   7 +
> .../drm/i915/display/intel_display_power.c    |   8 +
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 455 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_pmdemand.h |  24 +
> drivers/gpu/drm/i915/i915_irq.c               |  21 +-
> drivers/gpu/drm/i915/i915_reg.h               |  36 +-
> 9 files changed, 562 insertions(+), 5 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>
>diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>index 9af76e376ca9..eb899fa86e51 100644
>--- a/drivers/gpu/drm/i915/Makefile
>+++ b/drivers/gpu/drm/i915/Makefile
>@@ -281,7 +281,8 @@ i915-y += \
>        display/i9xx_wm.o \
>        display/skl_scaler.o \
>        display/skl_universal_plane.o \
>-  display/skl_watermark.o
>+  display/skl_watermark.o \
>+  display/intel_pmdemand.o
> i915-$(CONFIG_ACPI) += \
>        display/intel_acpi.o \
>        display/intel_opregion.o
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index bf391a6cd8d6..f98e235fadc6 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -99,6 +99,7 @@
> #include "intel_pcode.h"
> #include "intel_pipe_crc.h"
> #include "intel_plane_initial.h"
>+#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_sdvo.h"
>@@ -6306,6 +6307,10 @@ int intel_atomic_check(struct drm_device *dev,
>                        return ret;
>        }
> 
>+  ret = intel_pmdemand_atomic_check(state);
>+  if (ret)
>+          goto fail;
>+
>        ret = intel_atomic_check_crtcs(state);
>        if (ret)
>                goto fail;
>@@ -6960,6 +6965,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>        }
> 
>        intel_sagv_pre_plane_update(state);
>+  intel_pmdemand_pre_plane_update(state);
> 
>        /* Complete the events for pipes that have now been disabled */
>        for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>@@ -7070,6 +7076,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>                intel_verify_planes(state);
> 
>        intel_sagv_post_plane_update(state);
>+  intel_pmdemand_post_plane_update(state);
> 
>        drm_atomic_helper_commit_hw_done(&state->base);
> 
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>index 9f66d734edf6..9471a052aa57 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -345,6 +345,12 @@ struct intel_display {
>                struct intel_global_obj obj;
>        } dbuf;
> 
>+  struct {
>+          wait_queue_head_t waitqueue;
>+          struct mutex lock;
>+          struct intel_global_obj obj;
>+  } pmdemand;
>+
>        struct {
>                /*
>                 * dkl.phy_lock protects against concurrent access of the
>diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
>index 60ce10fc7205..79853d8c3240 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
>@@ -47,6 +47,7 @@
> #include "intel_opregion.h"
> #include "intel_overlay.h"
> #include "intel_plane_initial.h"
>+#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_quirks.h"
> #include "intel_vga.h"
>@@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
>        if (ret < 0)
>                goto cleanup_vga;
> 
>+  intel_pmdemand_init(i915);
>+
>        intel_power_domains_init_hw(i915, false);
> 
>        if (!HAS_DISPLAY(i915))
>@@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
>        if (ret)
>                goto cleanup_vga_client_pw_domain_dmc;
> 
>+  ret = intel_pmdemand_state_init(i915);
>+  if (ret)
>+          goto cleanup_vga_client_pw_domain_dmc;
>+
>        init_llist_head(&i915->display.atomic_helper.free_list);
>        INIT_WORK(&i915->display.atomic_helper.free_work,
>                  intel_atomic_helper_free_state_worker);
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index 5150069f3f82..f5c5a486efbc 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -20,6 +20,7 @@
> #include "intel_mchbar_regs.h"
> #include "intel_pch_refclk.h"
> #include "intel_pcode.h"
>+#include "intel_pmdemand.h"
> #include "intel_pps_regs.h"
> #include "intel_snps_phy.h"
> #include "skl_watermark.h"
>@@ -1085,6 +1086,10 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
>        dev_priv->display.dbuf.enabled_slices =
>                intel_enabled_dbuf_slices_mask(dev_priv);
> 
>+  if (DISPLAY_VER(dev_priv) >= 14)
>+          intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
>+                                      dev_priv->display.dbuf.enabled_slices);
>+
>        /*
>         * Just power up at least 1 slice, we will
>         * figure out later which slices we have and what we need.
>@@ -1096,6 +1101,9 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
> static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
> {
>        gen9_dbuf_slices_update(dev_priv, 0);
>+
>+  if (DISPLAY_VER(dev_priv) >= 14)
>+          intel_program_dbuf_pmdemand(dev_priv, 0);
> }
> 
> static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
>diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>new file mode 100644
>index 000000000000..df6429e7059d
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>@@ -0,0 +1,455 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2024 Intel Corporation
>+ */
>+
>+#include <linux/bitops.h>
>+
>+#include "i915_drv.h"
>+#include "i915_reg.h"
>+#include "intel_bw.h"
>+#include "intel_cdclk.h"
>+#include "intel_cx0_phy.h"
>+#include "intel_de.h"
>+#include "intel_display.h"
>+#include "intel_display_trace.h"
>+#include "intel_pmdemand.h"
>+#include "skl_watermark.h"
>+
>+struct intel_pmdemand_state {
>+  struct intel_global_state base;
>+
>+  u16 qclk_gv_bw;
>+  u8 voltage_index;
>+  u8 qclk_gv_index;
>+  u8 active_pipes;
>+  u8 dbufs;
>+  u8 active_phys_plls_mask;

Is u8 enough for the mask? The enum phy shows 9 possible PHY_* members.
Also, I think having BUILD_BUG_ON() somewhere in this file to make sure
we have enough bits would be nice.

>+  u16 cdclk_freq_mhz;
>+  u16 ddiclk_freq_mhz;
>+  u8 scalers;
>+};
>+
>+#define to_intel_pmdemand_state(x) container_of((x), struct intel_pmdemand_state, base)
>+
>+static struct intel_global_state *
>+intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
>+{
>+  struct intel_pmdemand_state *pmdmnd_state;
>+
>+  pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state), GFP_KERNEL);
>+  if (!pmdmnd_state)
>+          return NULL;
>+
>+  return &pmdmnd_state->base;
>+}
>+
>+static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
>+                                   struct intel_global_state *state)
>+{
>+  kfree(state);
>+}
>+
>+static const struct intel_global_state_funcs intel_pmdemand_funcs = {
>+  .atomic_duplicate_state = intel_pmdemand_duplicate_state,
>+  .atomic_destroy_state = intel_pmdemand_destroy_state,
>+};
>+
>+static struct intel_pmdemand_state *
>+intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
>+{
>+  struct drm_i915_private *i915 = to_i915(state->base.dev);
>+  struct intel_global_state *pmdemand_state;
>+
>+  pmdemand_state =
>+          intel_atomic_get_global_obj_state(state,
>+                                            &i915->display.pmdemand.obj);
>+  if (IS_ERR(pmdemand_state))
>+          return ERR_CAST(pmdemand_state);
>+
>+  return to_intel_pmdemand_state(pmdemand_state);
>+}
>+
>+static struct intel_pmdemand_state *
>+intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
>+{
>+  struct drm_i915_private *i915 = to_i915(state->base.dev);
>+  struct intel_global_state *pmdemand_state;
>+
>+  pmdemand_state = intel_atomic_get_old_global_obj_state(state, &i915->display.pmdemand.obj);

Wouldn't it be safer if we returned early here when pmdemand_state is
NULL?

I think to_intel_pmdemand_state(NULL) pmdemand_state just happens to
work (i.e. still returns NULL) because the "base" member is at the
beginning of the struct. However, we shouldn't rely on that IMO.

>+
>+  return to_intel_pmdemand_state(pmdemand_state);
>+}
>+
>+static struct intel_pmdemand_state *
>+intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
>+{
>+  struct drm_i915_private *i915 = to_i915(state->base.dev);
>+  struct intel_global_state *pmdemand_state;
>+
>+  pmdemand_state = intel_atomic_get_new_global_obj_state(state, &i915->display.pmdemand.obj);

Just as with intel_atomic_get_old_pmdemand_state(), shouldn't we return
early if pmdemand_state is NULL here?

>+
>+  return to_intel_pmdemand_state(pmdemand_state);
>+}
>+
>+int intel_pmdemand_state_init(struct drm_i915_private *i915)
>+{
>+  struct intel_pmdemand_state *pmdemand_state;
>+
>+  pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
>+  if (!pmdemand_state)
>+          return -ENOMEM;
>+
>+  intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
>+                               &pmdemand_state->base,
>+                               &intel_pmdemand_funcs);
>+
>+
>+  if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>+          /* Wa_14016740474 */
>+          intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
>+
>+  return 0;
>+}
>+
>+void intel_pmdemand_init(struct drm_i915_private *i915)
>+{
>+  mutex_init(&i915->display.pmdemand.lock);
>+  init_waitqueue_head(&i915->display.pmdemand.waitqueue);
>+}

The functions intel_pmdemand_state_init() and intel_pmdemand_init() are
both called from the same place. Furthermore,
intel_pmdemand_state_init() isn't only initializing the state, as the
Wa_14016740474 workaround is programmed there. Could we have only the
function intel_pmdemand_init() and incorporate what
intel_pmdemand_state_init() does in it?

>+
>+static bool pmdemand_needs_update(struct intel_atomic_state *state)
>+{
>+  bool changed = false;
>+  struct intel_crtc *crtc;
>+  int i;
>+  const struct intel_bw_state *new_bw_state, *old_bw_state;
>+  const struct intel_cdclk_state *new_cdclk_state;
>+  const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
>+  const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
>+
>+  for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>+                                      new_crtc_state, i) {
>+          new_bw_state = intel_atomic_get_new_bw_state(state);
>+          old_bw_state = intel_atomic_get_old_bw_state(state);
>+
>+          new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
>+          old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
>+
>+          new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
>+
>+          if ((new_bw_state && new_bw_state->qgv_point_peakbw !=
>+               old_bw_state->qgv_point_peakbw) ||
>+              (new_dbuf_state && new_dbuf_state->active_pipes !=
>+               old_dbuf_state->active_pipes) || new_cdclk_state)
>+                  changed = true;
>+
>+          /*
>+           * break needs to be removed, if some crtc_state dependent
>+           * parameters are added here
>+           */
>+          break;
>+  }
>+
>+  return changed;
>+}
>+
>+int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
>+{
>+  struct drm_i915_private *i915 = to_i915(state->base.dev);
>+  int port_clock = 0;
>+  struct intel_crtc *crtc;
>+  struct intel_encoder *encoder;
>+  const struct intel_bw_state *new_bw_state;
>+  const struct intel_cdclk_state *new_cdclk_state;
>+  const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
>+  const struct intel_dbuf_state *new_dbuf_state;
>+  struct intel_pmdemand_state *new_pmdemand_state;
>+  enum phy phy;
>+  int i, ret;
>+
>+  if (DISPLAY_VER(i915) < 14)
>+          return 0;
>+
>+  if (!pmdemand_needs_update(state))
>+          return 0;
>+
>+  new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
>+  if (IS_ERR(new_pmdemand_state))
>+          return PTR_ERR(new_pmdemand_state);
>+
>+  ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
>+  if (ret)
>+          return ret;
>+
>+  /* Punit figures out the voltage index based on bandwidth*/
>+  new_bw_state = intel_atomic_get_bw_state(state);
>+  if (IS_ERR(new_bw_state))
>+          return PTR_ERR(new_bw_state);
>+
>+  /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
>+  new_pmdemand_state->qclk_gv_index = 0;
>+  new_pmdemand_state->qclk_gv_bw =
>+          min_t(u16, new_bw_state->qgv_point_peakbw, 0xffff);
>+
>+  new_dbuf_state = intel_atomic_get_dbuf_state(state);
>+  if (IS_ERR(new_dbuf_state))
>+          return PTR_ERR(new_dbuf_state);
>+
>+  i = hweight8(new_dbuf_state->active_pipes);
>+  new_pmdemand_state->active_pipes = min(i, 3);
>+
>+  new_cdclk_state = intel_atomic_get_cdclk_state(state);
>+  if (IS_ERR(new_cdclk_state))
>+          return PTR_ERR(new_cdclk_state);
>+
>+  new_pmdemand_state->voltage_index =
>+          new_cdclk_state->logical.voltage_level;
>+  /* KHz to MHz */
>+  new_pmdemand_state->cdclk_freq_mhz =
>+          DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
>+
>+  new_pmdemand_state->active_phys_plls_mask = 0;
>+
>+  for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>+                                      new_crtc_state, i) {
>+          if (!new_crtc_state->hw.active)
>+                  continue;
>+
>+          encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
>+          if (!encoder)
>+                  continue;
>+
>+          phy = intel_port_to_phy(i915, encoder->port);
>+
>+          if (intel_is_c10phy(i915, phy))
>+                  new_pmdemand_state->active_phys_plls_mask |= BIT(phy);
>+
>+          port_clock = max(port_clock, new_crtc_state->port_clock);
>+  }

As previously noted in https://patchwork.freedesktop.org/patch/530495 ,
I'm under the impression that this loop would not let us account for al
active crtcs, only those currently being touched by this atomic
transaction. Am I wrong to assume that
for_each_oldnew_intel_crtc_in_state() would only iterate over crtcs
touched by the atomic update?

>+
>+  /* To MHz */
>+  new_pmdemand_state->ddiclk_freq_mhz = DIV_ROUND_UP(port_clock, 1000);
>+
>+  /*
>+   * Setting scalers to max as it can not be calculated during flips and
>+   * fastsets without taking global states locks.
>+   */
>+  new_pmdemand_state->scalers = 7;
>+
>+  ret = intel_atomic_serialize_global_state(&new_pmdemand_state->base);
>+  if (ret)
>+          return ret;
>+
>+  return 0;
>+}
>+
>+static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
>+{
>+  return !((intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
>+            XELPDP_PMDEMAND_REQ_ENABLE) ||
>+          (intel_de_read(i915, GEN12_DCPR_STATUS_1) &
>+           XELPDP_PMDEMAND_INFLIGHT_STATUS));
>+}
>+
>+static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
>+{
>+  return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
>+           XELPDP_PMDEMAND_REQ_ENABLE);
>+}
>+
>+static int intel_pmdemand_wait(struct drm_i915_private *i915)
>+{
>+  DEFINE_WAIT(wait);
>+  int ret;
>+  const unsigned int timeout_ms = 10;
>+
>+  ret = wait_event_timeout(i915->display.pmdemand.waitqueue,
>+                           intel_pmdemand_req_complete(i915),
>+                           msecs_to_jiffies_timeout(timeout_ms));
>+  if (ret == 0)
>+          drm_err(&i915->drm,
>+                  "timed out waiting for Punit PM Demand Response\n");
>+
>+  return ret;
>+}
>+
>+/* Required to be programmed during Display Init Sequences. */
>+void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
>+                           u8 dbuf_slices)
>+{
>+  u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
>+
>+  mutex_lock(&i915->display.pmdemand.lock);
>+  if (drm_WARN_ON(&i915->drm,
>+                  !intel_pmdemand_check_prev_transaction(i915)))
>+          goto unlock;
>+
>+  intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
>+               XELPDP_PMDEMAND_DBUFS_MASK, XELPDP_PMDEMAND_DBUFS(dbufs));
>+  intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
>+               XELPDP_PMDEMAND_REQ_ENABLE);
>+
>+  intel_pmdemand_wait(i915);
>+
>+unlock:
>+  mutex_unlock(&i915->display.pmdemand.lock);
>+}
>+
>+static void update_pmdemand_values(const struct intel_pmdemand_state *new,
>+                             const struct intel_pmdemand_state *old,
>+                             u32 *reg1, u32 *reg2)
>+{
>+  u32 plls, tmp;
>+
>+  /*
>+   * The pmdemand parameter updates happens in two steps. Pre plane and
>+   * post plane updates. During the pre plane, as DE might still be
>+   * handling with some old operations, to avoid unwanted performance
>+   * issues, program the pmdemand parameters with higher of old and new
>+   * values. And then after once settled, use the new parameter values
>+   * as part of the post plane update.
>+   */
>+
>+  /* Set 1*/
>+  *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_BW_MASK;
>+  tmp = old ? max(old->qclk_gv_bw, new->qclk_gv_bw) : new->qclk_gv_bw;
>+  *reg1 |= XELPDP_PMDEMAND_QCLK_GV_BW(tmp);
>+
>+  *reg1 &= ~XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK;
>+  tmp = old ? max(old->voltage_index, new->voltage_index) :
>+              new->voltage_index;
>+  *reg1 |= XELPDP_PMDEMAND_VOLTAGE_INDEX(tmp);
>+
>+  *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK;
>+  tmp = old ? max(old->qclk_gv_index, new->qclk_gv_index) :
>+              new->qclk_gv_index;
>+  *reg1 |= XELPDP_PMDEMAND_QCLK_GV_INDEX(tmp);
>+
>+  *reg1 &= ~XELPDP_PMDEMAND_PIPES_MASK;
>+  tmp = old ? max(old->active_pipes, new->active_pipes) :
>+              new->active_pipes;
>+  *reg1 |= XELPDP_PMDEMAND_PIPES(tmp);
>+
>+  *reg1 &= ~XELPDP_PMDEMAND_PHYS_MASK;
>+  plls = hweight32(new->active_phys_plls_mask);
>+  if (old)
>+          plls = max(plls, hweight32(old->active_phys_plls_mask));
>+  *reg1 |= XELPDP_PMDEMAND_PHYS(plls);

If plls > 7, we would be potentially programming this wrong (e.g. for
plls=8, we would setting the field to 0).

>+
>+  /* Set 2*/
>+  *reg2 &= ~XELPDP_PMDEMAND_CDCLK_FREQ_MASK;
>+  tmp = old ? max(old->cdclk_freq_mhz, new->cdclk_freq_mhz) :
>+              new->cdclk_freq_mhz;
>+  *reg2 |= XELPDP_PMDEMAND_CDCLK_FREQ(tmp);
>+
>+  *reg2 &= ~XELPDP_PMDEMAND_DDICLK_FREQ_MASK;
>+  tmp = old ? max(old->ddiclk_freq_mhz, new->ddiclk_freq_mhz) :
>+              new->ddiclk_freq_mhz;
>+  *reg2 |= XELPDP_PMDEMAND_DDICLK_FREQ(tmp);
>+
>+  /* Hard code scalers to 7*/

I think this comment can be dropped: the hardcoding happens in
intel_pmdemand_atomic_check().

>+  *reg2 &= ~XELPDP_PMDEMAND_SCALERS_MASK;
>+  tmp = old ? max(old->scalers, new->scalers) : new->scalers;
>+  *reg2 |= XELPDP_PMDEMAND_SCALERS(tmp);
>+
>+  /*
>+   * Active_PLLs starts with 1 because of CDCLK PLL.
>+   * TODO: Missing to account genlock filter when it gets used.
>+   */
>+  *reg2 &= ~XELPDP_PMDEMAND_PLLS_MASK;

I think we are missing the ternary operator here to select the maximum
value for the pre-plane case.

>+  *reg2 |= XELPDP_PMDEMAND_PLLS(plls + 1);
>+}
>+
>+static void intel_program_pmdemand(struct drm_i915_private *i915,
>+                             const struct intel_pmdemand_state *new,
>+                             const struct intel_pmdemand_state *old)
>+{
>+  bool changed = false;
>+  u32 reg1, mod_reg1;
>+  u32 reg2, mod_reg2;
>+
>+  mutex_lock(&i915->display.pmdemand.lock);
>+  if (drm_WARN_ON(&i915->drm,
>+                  !intel_pmdemand_check_prev_transaction(i915)))
>+          goto unlock;

According to the spec, we should wait and timeout after 10ms here.

>+
>+  reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
>+  mod_reg1 = reg1;
>+
>+  reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
>+  mod_reg2 = reg2;
>+
>+  update_pmdemand_values(new, old, &mod_reg1, &mod_reg2);
>+
>+  if (reg1 != mod_reg1) {
>+          intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
>+                         mod_reg1);
>+          changed = true;
>+  }
>+
>+  if (reg2 != mod_reg2) {
>+          intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
>+                         mod_reg2);
>+          changed = true;
>+  }
>+
>+  /* Initiate pm demand request only if register values are changed */
>+  if (changed) {

Nitpick: we could have

    if (!changed)
            goto unlock;

and dedent the block below.

>+          drm_dbg_kms(&i915->drm,
>+                      "initate pmdemand request values: (0x%x 0x%x)\n",
>+                      mod_reg1, mod_reg2);
>+
>+          intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
>+                       XELPDP_PMDEMAND_REQ_ENABLE);
>+
>+          intel_pmdemand_wait(i915);
>+  }
>+
>+unlock:
>+  mutex_unlock(&i915->display.pmdemand.lock);
>+}
>+
>+static bool
>+intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
>+                       const struct intel_pmdemand_state *old)
>+{
>+  return memcmp(&new->qclk_gv_bw, &old->qclk_gv_bw,
>+                sizeof(*new) - offsetof(typeof(*new), qclk_gv_bw)) != 0;
>+}
>+
>+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
>+{
>+  struct drm_i915_private *i915 = to_i915(state->base.dev);
>+  const struct intel_pmdemand_state *new_pmdmnd_state =
>+          intel_atomic_get_new_pmdemand_state(state);
>+  const struct intel_pmdemand_state *old_pmdmnd_state =
>+          intel_atomic_get_old_pmdemand_state(state);
>+
>+  if (DISPLAY_VER(i915) < 14)
>+          return;
>+
>+  if (!new_pmdmnd_state ||
>+      !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
>+          return;
>+
>+  intel_program_pmdemand(i915, new_pmdmnd_state, old_pmdmnd_state);
>+}
>+
>+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
>+{
>+  struct drm_i915_private *i915 = to_i915(state->base.dev);
>+  const struct intel_pmdemand_state *new_pmdmnd_state =
>+          intel_atomic_get_new_pmdemand_state(state);
>+  const struct intel_pmdemand_state *old_pmdmnd_state =
>+          intel_atomic_get_old_pmdemand_state(state);
>+
>+  if (DISPLAY_VER(i915) < 14)
>+          return;
>+
>+  if (!new_pmdmnd_state ||
>+      !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
>+          return;
>+
>+  intel_program_pmdemand(i915, new_pmdmnd_state, NULL);
>+}
>diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h b/drivers/gpu/drm/i915/display/intel_pmdemand.h
>new file mode 100644
>index 000000000000..0114f4e0225a
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
>@@ -0,0 +1,24 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2023 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_PMDEMAND_H__
>+#define __INTEL_PMDEMAND_H__
>+
>+#include <linux/types.h>
>+
>+struct drm_i915_private;
>+struct intel_atomic_state;
>+struct intel_crtc_state;
>+struct intel_plane_state;
>+
>+void intel_pmdemand_init(struct drm_i915_private *i915);
>+int intel_pmdemand_state_init(struct drm_i915_private *i915);
>+void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
>+                           u8 dbuf_slices);
>+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
>+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
>+int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
>+
>+#endif /* __INTEL_PMDEMAND_H__ */
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 2b94b8ca8ec9..907fa3aee179 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -41,6 +41,7 @@
> #include "display/intel_fifo_underrun.h"
> #include "display/intel_hotplug.h"
> #include "display/intel_lpe_audio.h"
>+#include "display/intel_pmdemand.h"
> #include "display/intel_psr.h"
> #include "display/intel_psr_regs.h"
> 
>@@ -1986,12 +1987,25 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
>                return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> }
> 
>+static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
>+{
>+  wake_up_all(&dev_priv->display.pmdemand.waitqueue);
>+}
>+
> static void
> gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> {
>        bool found = false;
> 
>-  if (iir & GEN8_DE_MISC_GSE) {
>+  if (DISPLAY_VER(dev_priv) >= 14 &&
>+      (iir & (XELPDP_PMDEMAND_RSP | XELPDP_PMDEMAND_RSPTOUT_ERR))) {
>+          if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)

I think we should have the (iir & (XELPDP_PMDEMAND_RSP |
XELPDP_PMDEMAND_RSPTOUT_ERR)) part as nested if statement here.
Otherwise, when the interrupt did not happen, we could endup checking
for the GEN8_DE_MISC_GSE even when DISPLAY_VER(dev_priv) >= 14.

Even though we know that iir & GEN8_DE_MISC_GSE would be false in this
situation (because both XELPDP_PMDEMAND_RSPTOUT_ERR and GEN8_DE_MISC_GSE
map to the same bit), I think having that one checked only for previous
display engines would sound more correct semantically speaking.

>+                  drm_dbg(&dev_priv->drm,
>+                          "Error waiting for Punit PM Demand Response\n");
>+
>+          intel_pmdemand_irq_handler(dev_priv);
>+          found = true;
>+  } else if (iir & GEN8_DE_MISC_GSE) {
>                intel_opregion_asle_intr(dev_priv);
>                found = true;
>        }
>@@ -3742,7 +3756,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>        if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>                de_port_masked |= BXT_DE_PORT_GMBUS;
> 
>-  if (DISPLAY_VER(dev_priv) >= 11) {
>+  if (DISPLAY_VER(dev_priv) >= 14)
>+          de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
>+                            XELPDP_PMDEMAND_RSP;
>+  else if (DISPLAY_VER(dev_priv) >= 11) {
>                enum port port;
> 
>                if (intel_bios_is_dsi_present(dev_priv, &port))
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index dde6e91055bd..60c007aea1ce 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -4426,8 +4426,10 @@
> #define GEN8_DE_MISC_IMR _MMIO(0x44464)
> #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> #define GEN8_DE_MISC_IER _MMIO(0x4446c)
>-#define  GEN8_DE_MISC_GSE         (1 << 27)
>-#define  GEN8_DE_EDP_PSR          (1 << 19)
>+#define  XELPDP_PMDEMAND_RSPTOUT_ERR      REG_BIT(27)
>+#define  GEN8_DE_MISC_GSE         REG_BIT(27)
>+#define  GEN8_DE_EDP_PSR          REG_BIT(19)
>+#define  XELPDP_PMDEMAND_RSP              REG_BIT(3)
> 
> #define GEN8_PCU_ISR _MMIO(0x444e0)
> #define GEN8_PCU_IMR _MMIO(0x444e4)
>@@ -4512,6 +4514,33 @@
> #define  XELPDP_DP_ALT_HPD_LONG_DETECT         REG_BIT(1)
> #define  XELPDP_DP_ALT_HPD_SHORT_DETECT                REG_BIT(0)
> 
>+#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)           _MMIO(0x45230 + 4 * (dword))
>+#define  XELPDP_PMDEMAND_QCLK_GV_BW_MASK          REG_GENMASK(31, 16)
>+#define  XELPDP_PMDEMAND_QCLK_GV_BW(x)                    REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
>+#define  XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK               REG_GENMASK(14, 12)
>+#define  XELPDP_PMDEMAND_VOLTAGE_INDEX(x)         REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
>+#define  XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK               REG_GENMASK(11, 8)
>+#define  XELPDP_PMDEMAND_QCLK_GV_INDEX(x)         REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
>+#define  XELPDP_PMDEMAND_PIPES_MASK                       REG_GENMASK(7, 6)
>+#define  XELPDP_PMDEMAND_PIPES(x)                 REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
>+#define  XELPDP_PMDEMAND_DBUFS_MASK                       REG_GENMASK(5, 4)
>+#define  XELPDP_PMDEMAND_DBUFS(x)                 REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
>+#define  XELPDP_PMDEMAND_PHYS_MASK                        REG_GENMASK(2, 0)
>+#define  XELPDP_PMDEMAND_PHYS(x)                  REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
>+
>+#define  XELPDP_PMDEMAND_REQ_ENABLE                       REG_BIT(31)
>+#define  XELPDP_PMDEMAND_CDCLK_FREQ_MASK          REG_GENMASK(30, 20)
>+#define  XELPDP_PMDEMAND_CDCLK_FREQ(x)                    REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
>+#define  XELPDP_PMDEMAND_DDICLK_FREQ_MASK         REG_GENMASK(18, 8)
>+#define  XELPDP_PMDEMAND_DDICLK_FREQ(x)                   REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
>+#define  XELPDP_PMDEMAND_SCALERS_MASK                     REG_GENMASK(6, 4)
>+#define  XELPDP_PMDEMAND_SCALERS(x)                       REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
>+#define  XELPDP_PMDEMAND_PLLS_MASK                        REG_GENMASK(2, 0)
>+#define  XELPDP_PMDEMAND_PLLS(x)                  REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
>+
>+#define GEN12_DCPR_STATUS_1                               _MMIO(0x46440)
>+#define  XELPDP_PMDEMAND_INFLIGHT_STATUS          REG_BIT(26)
>+
> #define ILK_DISPLAY_CHICKEN2   _MMIO(0x42004)
> /* Required on all Ironlake and Sandybridge according to the B-Spec. */
> #define   ILK_ELPIN_409_SELECT REG_BIT(25)
>@@ -4671,6 +4700,9 @@
> #define   DCPR_SEND_RESP_IMM                   REG_BIT(25)
> #define   DCPR_CLEAR_MEMSTAT_DIS               REG_BIT(24)
> 
>+#define XELPD_CHICKEN_DCPR_3                      _MMIO(0x46438)
>+#define   DMD_RSP_TIMEOUT_DISABLE         REG_BIT(19)
>+
> #define SKL_DFSM                       _MMIO(0x51000)
> #define   SKL_DFSM_DISPLAY_PM_DISABLE  (1 << 27)
> #define   SKL_DFSM_DISPLAY_HDCP_DISABLE        (1 << 25)
>-- 
>2.34.1
>

[Intel-gfx] ✗ Fi.CI.IGT: failure for mtl: add support for pmdemand (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 11282 bytes --]

== Series Details ==

Series: mtl: add support for pmdemand (rev4)
URL   : https://patchwork.freedesktop.org/series/116949/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13071_full -> Patchwork_116949v4_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_116949v4_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_116949v4_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_116949v4_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
    - shard-glk:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-glk8/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-glk7/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s4-devices@smem:
    - {shard-tglu}:       [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-tglu-7/igt@gem_exec_suspend@basic-s4-devices@smem.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html

  * igt@i915_selftest@live@workarounds:
    - {shard-dg1}:        [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-16/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-dg1-13/igt@i915_selftest@live@workarounds.html

  
Known issues
------------

  Here are the changes found in Patchwork_116949v4_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][7] -> [FAIL][8] ([i915#2846])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-glk9/igt@gem_exec_fair@basic-deadline.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-glk3/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-apl:          [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-apl3/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-apl7/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-apl3/igt@gem_huc_copy@huc-copy.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-apl:          NOTRUN -> [SKIP][12] ([fdo#109271]) +25 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-apl3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_content_protection@atomic@pipe-a-dp-1:
    - shard-apl:          NOTRUN -> [TIMEOUT][13] ([i915#7173])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-apl3/igt@kms_content_protection@atomic@pipe-a-dp-1.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-hdmi-a-1:
    - shard-snb:          NOTRUN -> [SKIP][14] ([fdo#109271]) +21 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-snb1/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-hdmi-a-1.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
    - {shard-rkl}:        [FAIL][15] ([i915#7742]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-rkl-3/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html

  * igt@gem_barrier_race@remote-request@rcs0:
    - {shard-dg1}:        [ABORT][17] ([i915#7461] / [i915#8234]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-16/igt@gem_barrier_race@remote-request@rcs0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-dg1-12/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_eio@hibernate:
    - shard-apl:          [ABORT][19] -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-apl3/igt@gem_eio@hibernate.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-apl3/igt@gem_eio@hibernate.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - {shard-dg1}:        [TIMEOUT][21] ([i915#5493]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@i915_pm_dc@dc6-dpms:
    - {shard-tglu}:       [FAIL][23] ([i915#3989] / [i915#454]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-tglu-8/igt@i915_pm_dc@dc6-dpms.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-tglu-4/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - {shard-dg1}:        [FAIL][25] ([i915#3591]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [FAIL][27] ([i915#2346]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
    - shard-glk:          [FAIL][29] ([i915#2346]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_plane@pixel-format@pipe-a-planes:
    - shard-glk:          [FAIL][31] ([i915#1623]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-glk9/igt@kms_plane@pixel-format@pipe-a-planes.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-glk1/igt@kms_plane@pixel-format@pipe-a-planes.html

  * igt@perf_pmu@idle@rcs0:
    - {shard-rkl}:        [FAIL][33] ([i915#4349]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-rkl-6/igt@perf_pmu@idle@rcs0.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/shard-rkl-3/igt@perf_pmu@idle@rcs0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1623]: https://gitlab.freedesktop.org/drm/intel/issues/1623
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#8102]: https://gitlab.freedesktop.org/drm/intel/issues/8102
  [i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381


Build changes
-------------

  * Linux: CI_DRM_13071 -> Patchwork_116949v4

  CI-20190529: 20190529
  CI_DRM_13071: b9458e7075652669ec0e04abe039a5ed001701fe @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7273: f40ef4b058466219968b7792d22ff0648b82396b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_116949v4: b9458e7075652669ec0e04abe039a5ed001701fe @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v4/index.html

[-- Attachment #2: Type: text/html, Size: 10747 bytes --]

Re: [Intel-gfx] [PATCH v3 2/8] drm/i915: update the QGV point frequency calculations

[Govindapillai, Vinod]

On Thu, 2023-04-27 at 18:04 +0300, Ville Syrjälä wrote:
> On Thu, Apr 27, 2023 at 06:00:10PM +0300, Vinod Govindapillai wrote:
> > > From MTL onwwards, pcode locks the QGV point based on peak BW of
> > the intended QGV point passed by the driver. So the peak BW
> > calculation must match the value expected by the pcode. Update
> > the calculations as per the Bspec.
> > 
> > Bspec: 64636
> > 
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> > index ab405c48ca3a..25ae4e5834d3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
> >         val2 = intel_uncore_read(&dev_priv->uncore,
> >                                  MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
> >         dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
> > -       sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
> > +       sp->dclk = (16667 * dclk + 500) / 1000;
> 
> Don't hand roll rounding.

Hi Ville,

I did not understand what you meant by this.

This is as per the Bspec 64636. I am assuming, probably this is what pcode expects to get it
compared with its internal reference qclk peak Bw. I will clarify with Art.

And there is another requirement to get rid of div_round_up() of these BW calculations. Will address
them separately.

BR
Vinod
> 
> >         sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
> >         sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
> >  
> > -- 
> > 2.34.1
> 

Re: [Intel-gfx] [PATCH v3 2/8] drm/i915: update the QGV point frequency calculations

[Jani Nikula]

On Fri, 28 Apr 2023, "Govindapillai, Vinod" <vinod.govindapillai@intel.com> wrote:
> On Thu, 2023-04-27 at 18:04 +0300, Ville Syrjälä wrote:
>> On Thu, Apr 27, 2023 at 06:00:10PM +0300, Vinod Govindapillai wrote:
>> > > From MTL onwwards, pcode locks the QGV point based on peak BW of
>> > the intended QGV point passed by the driver. So the peak BW
>> > calculation must match the value expected by the pcode. Update
>> > the calculations as per the Bspec.
>> > 
>> > Bspec: 64636
>> > 
>> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> > index ab405c48ca3a..25ae4e5834d3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> > @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
>> >         val2 = intel_uncore_read(&dev_priv->uncore,
>> >                                  MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
>> >         dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
>> > -       sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
>> > +       sp->dclk = (16667 * dclk + 500) / 1000;
>> 
>> Don't hand roll rounding.
>
> Hi Ville,
>
> I did not understand what you meant by this.
>
> This is as per the Bspec 64636. I am assuming, probably this is what pcode expects to get it
> compared with its internal reference qclk peak Bw. I will clarify with Art.
>
> And there is another requirement to get rid of div_round_up() of these BW calculations. Will address
> them separately.

The point is, no matter whether you need to round up or down or nearest,
you need to use the DIV_ROUND_* helpers for that, not duplicate the
logic here. No matter what bspec says.

BR,
Jani.


>
> BR
> Vinod
>> 
>> >         sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
>> >         sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
>> >  
>> > -- 
>> > 2.34.1
>> 
>

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v3 7/8] drm/i915/mtl: Add support for PM DEMAND

[Jani Nikula]

On Thu, 27 Apr 2023, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> From: Mika Kahola <mika.kahola@intel.com>
>
> Display14 introduces a new way to instruct the PUnit with
> power and bandwidth requirements of DE. Add the functionality
> to program the registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to
> factor in the worst case scenarios. Changes made to use REG_BIT
> for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
> Wa_14016740474 is added which applies to Xe_LPD+ display
>
> v2: checkpatch warning fixes, simplify program pmdemand part
>
> v3: update to dbufs and pipes values to pmdemand register(stan)
>     Removed the macro usage in update_pmdemand_values()
>
> Bspec: 66451, 64636, 64602, 64603
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                 |   3 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |   7 +
>  .../gpu/drm/i915/display/intel_display_core.h |   6 +
>  .../drm/i915/display/intel_display_driver.c   |   7 +
>  .../drm/i915/display/intel_display_power.c    |   8 +
>  drivers/gpu/drm/i915/display/intel_pmdemand.c | 455 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_pmdemand.h |  24 +
>  drivers/gpu/drm/i915/i915_irq.c               |  21 +-
>  drivers/gpu/drm/i915/i915_reg.h               |  36 +-
>  9 files changed, 562 insertions(+), 5 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 9af76e376ca9..eb899fa86e51 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -281,7 +281,8 @@ i915-y += \
>  	display/i9xx_wm.o \
>  	display/skl_scaler.o \
>  	display/skl_universal_plane.o \
> -	display/skl_watermark.o
> +	display/skl_watermark.o \
> +	display/intel_pmdemand.o

Comment near the top of the file:

# Please keep these build lists sorted!


BR,
Jani.


>  i915-$(CONFIG_ACPI) += \
>  	display/intel_acpi.o \
>  	display/intel_opregion.o
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bf391a6cd8d6..f98e235fadc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -99,6 +99,7 @@
>  #include "intel_pcode.h"
>  #include "intel_pipe_crc.h"
>  #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
>  #include "intel_pps.h"
>  #include "intel_psr.h"
>  #include "intel_sdvo.h"
> @@ -6306,6 +6307,10 @@ int intel_atomic_check(struct drm_device *dev,
>  			return ret;
>  	}
>  
> +	ret = intel_pmdemand_atomic_check(state);
> +	if (ret)
> +		goto fail;
> +
>  	ret = intel_atomic_check_crtcs(state);
>  	if (ret)
>  		goto fail;
> @@ -6960,6 +6965,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	}
>  
>  	intel_sagv_pre_plane_update(state);
> +	intel_pmdemand_pre_plane_update(state);
>  
>  	/* Complete the events for pipes that have now been disabled */
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> @@ -7070,6 +7076,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		intel_verify_planes(state);
>  
>  	intel_sagv_post_plane_update(state);
> +	intel_pmdemand_post_plane_update(state);
>  
>  	drm_atomic_helper_commit_hw_done(&state->base);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 9f66d734edf6..9471a052aa57 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -345,6 +345,12 @@ struct intel_display {
>  		struct intel_global_obj obj;
>  	} dbuf;
>  
> +	struct {
> +		wait_queue_head_t waitqueue;
> +		struct mutex lock;
> +		struct intel_global_obj obj;
> +	} pmdemand;
> +
>  	struct {
>  		/*
>  		 * dkl.phy_lock protects against concurrent access of the
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 60ce10fc7205..79853d8c3240 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -47,6 +47,7 @@
>  #include "intel_opregion.h"
>  #include "intel_overlay.h"
>  #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
>  #include "intel_pps.h"
>  #include "intel_quirks.h"
>  #include "intel_vga.h"
> @@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
>  	if (ret < 0)
>  		goto cleanup_vga;
>  
> +	intel_pmdemand_init(i915);
> +
>  	intel_power_domains_init_hw(i915, false);
>  
>  	if (!HAS_DISPLAY(i915))
> @@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
>  	if (ret)
>  		goto cleanup_vga_client_pw_domain_dmc;
>  
> +	ret = intel_pmdemand_state_init(i915);
> +	if (ret)
> +		goto cleanup_vga_client_pw_domain_dmc;
> +
>  	init_llist_head(&i915->display.atomic_helper.free_list);
>  	INIT_WORK(&i915->display.atomic_helper.free_work,
>  		  intel_atomic_helper_free_state_worker);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 5150069f3f82..f5c5a486efbc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -20,6 +20,7 @@
>  #include "intel_mchbar_regs.h"
>  #include "intel_pch_refclk.h"
>  #include "intel_pcode.h"
> +#include "intel_pmdemand.h"
>  #include "intel_pps_regs.h"
>  #include "intel_snps_phy.h"
>  #include "skl_watermark.h"
> @@ -1085,6 +1086,10 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
>  	dev_priv->display.dbuf.enabled_slices =
>  		intel_enabled_dbuf_slices_mask(dev_priv);
>  
> +	if (DISPLAY_VER(dev_priv) >= 14)
> +		intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
> +					    dev_priv->display.dbuf.enabled_slices);
> +
>  	/*
>  	 * Just power up at least 1 slice, we will
>  	 * figure out later which slices we have and what we need.
> @@ -1096,6 +1101,9 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
>  static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
>  {
>  	gen9_dbuf_slices_update(dev_priv, 0);
> +
> +	if (DISPLAY_VER(dev_priv) >= 14)
> +		intel_program_dbuf_pmdemand(dev_priv, 0);
>  }
>  
>  static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> new file mode 100644
> index 000000000000..df6429e7059d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -0,0 +1,455 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#include <linux/bitops.h>
> +
> +#include "i915_drv.h"
> +#include "i915_reg.h"
> +#include "intel_bw.h"
> +#include "intel_cdclk.h"
> +#include "intel_cx0_phy.h"
> +#include "intel_de.h"
> +#include "intel_display.h"
> +#include "intel_display_trace.h"
> +#include "intel_pmdemand.h"
> +#include "skl_watermark.h"
> +
> +struct intel_pmdemand_state {
> +	struct intel_global_state base;
> +
> +	u16 qclk_gv_bw;
> +	u8 voltage_index;
> +	u8 qclk_gv_index;
> +	u8 active_pipes;
> +	u8 dbufs;
> +	u8 active_phys_plls_mask;
> +	u16 cdclk_freq_mhz;
> +	u16 ddiclk_freq_mhz;
> +	u8 scalers;
> +};
> +
> +#define to_intel_pmdemand_state(x) container_of((x), struct intel_pmdemand_state, base)
> +
> +static struct intel_global_state *
> +intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
> +{
> +	struct intel_pmdemand_state *pmdmnd_state;
> +
> +	pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state), GFP_KERNEL);
> +	if (!pmdmnd_state)
> +		return NULL;
> +
> +	return &pmdmnd_state->base;
> +}
> +
> +static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
> +					 struct intel_global_state *state)
> +{
> +	kfree(state);
> +}
> +
> +static const struct intel_global_state_funcs intel_pmdemand_funcs = {
> +	.atomic_duplicate_state = intel_pmdemand_duplicate_state,
> +	.atomic_destroy_state = intel_pmdemand_destroy_state,
> +};
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_global_state *pmdemand_state;
> +
> +	pmdemand_state =
> +		intel_atomic_get_global_obj_state(state,
> +						  &i915->display.pmdemand.obj);
> +	if (IS_ERR(pmdemand_state))
> +		return ERR_CAST(pmdemand_state);
> +
> +	return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_global_state *pmdemand_state;
> +
> +	pmdemand_state = intel_atomic_get_old_global_obj_state(state, &i915->display.pmdemand.obj);
> +
> +	return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_global_state *pmdemand_state;
> +
> +	pmdemand_state = intel_atomic_get_new_global_obj_state(state, &i915->display.pmdemand.obj);
> +
> +	return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +int intel_pmdemand_state_init(struct drm_i915_private *i915)
> +{
> +	struct intel_pmdemand_state *pmdemand_state;
> +
> +	pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
> +	if (!pmdemand_state)
> +		return -ENOMEM;
> +
> +	intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
> +				     &pmdemand_state->base,
> +				     &intel_pmdemand_funcs);
> +
> +
> +	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> +		/* Wa_14016740474 */
> +		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
> +
> +	return 0;
> +}
> +
> +void intel_pmdemand_init(struct drm_i915_private *i915)
> +{
> +	mutex_init(&i915->display.pmdemand.lock);
> +	init_waitqueue_head(&i915->display.pmdemand.waitqueue);
> +}
> +
> +static bool pmdemand_needs_update(struct intel_atomic_state *state)
> +{
> +	bool changed = false;
> +	struct intel_crtc *crtc;
> +	int i;
> +	const struct intel_bw_state *new_bw_state, *old_bw_state;
> +	const struct intel_cdclk_state *new_cdclk_state;
> +	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> +	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> +
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		new_bw_state = intel_atomic_get_new_bw_state(state);
> +		old_bw_state = intel_atomic_get_old_bw_state(state);
> +
> +		new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> +		old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> +
> +		new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> +
> +		if ((new_bw_state && new_bw_state->qgv_point_peakbw !=
> +		     old_bw_state->qgv_point_peakbw) ||
> +		    (new_dbuf_state && new_dbuf_state->active_pipes !=
> +		     old_dbuf_state->active_pipes) || new_cdclk_state)
> +			changed = true;
> +
> +		/*
> +		 * break needs to be removed, if some crtc_state dependent
> +		 * parameters are added here
> +		 */
> +		break;
> +	}
> +
> +	return changed;
> +}
> +
> +int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	int port_clock = 0;
> +	struct intel_crtc *crtc;
> +	struct intel_encoder *encoder;
> +	const struct intel_bw_state *new_bw_state;
> +	const struct intel_cdclk_state *new_cdclk_state;
> +	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> +	const struct intel_dbuf_state *new_dbuf_state;
> +	struct intel_pmdemand_state *new_pmdemand_state;
> +	enum phy phy;
> +	int i, ret;
> +
> +	if (DISPLAY_VER(i915) < 14)
> +		return 0;
> +
> +	if (!pmdemand_needs_update(state))
> +		return 0;
> +
> +	new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
> +	if (IS_ERR(new_pmdemand_state))
> +		return PTR_ERR(new_pmdemand_state);
> +
> +	ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
> +	if (ret)
> +		return ret;
> +
> +	/* Punit figures out the voltage index based on bandwidth*/
> +	new_bw_state = intel_atomic_get_bw_state(state);
> +	if (IS_ERR(new_bw_state))
> +		return PTR_ERR(new_bw_state);
> +
> +	/* firmware will calculate the qclck_gc_index, requirement is set to 0 */
> +	new_pmdemand_state->qclk_gv_index = 0;
> +	new_pmdemand_state->qclk_gv_bw =
> +		min_t(u16, new_bw_state->qgv_point_peakbw, 0xffff);
> +
> +	new_dbuf_state = intel_atomic_get_dbuf_state(state);
> +	if (IS_ERR(new_dbuf_state))
> +		return PTR_ERR(new_dbuf_state);
> +
> +	i = hweight8(new_dbuf_state->active_pipes);
> +	new_pmdemand_state->active_pipes = min(i, 3);
> +
> +	new_cdclk_state = intel_atomic_get_cdclk_state(state);
> +	if (IS_ERR(new_cdclk_state))
> +		return PTR_ERR(new_cdclk_state);
> +
> +	new_pmdemand_state->voltage_index =
> +		new_cdclk_state->logical.voltage_level;
> +	/* KHz to MHz */
> +	new_pmdemand_state->cdclk_freq_mhz =
> +		DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
> +
> +	new_pmdemand_state->active_phys_plls_mask = 0;
> +
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		if (!new_crtc_state->hw.active)
> +			continue;
> +
> +		encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> +		if (!encoder)
> +			continue;
> +
> +		phy = intel_port_to_phy(i915, encoder->port);
> +
> +		if (intel_is_c10phy(i915, phy))
> +			new_pmdemand_state->active_phys_plls_mask |= BIT(phy);
> +
> +		port_clock = max(port_clock, new_crtc_state->port_clock);
> +	}
> +
> +	/* To MHz */
> +	new_pmdemand_state->ddiclk_freq_mhz = DIV_ROUND_UP(port_clock, 1000);
> +
> +	/*
> +	 * Setting scalers to max as it can not be calculated during flips and
> +	 * fastsets without taking global states locks.
> +	 */
> +	new_pmdemand_state->scalers = 7;
> +
> +	ret = intel_atomic_serialize_global_state(&new_pmdemand_state->base);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
> +{
> +	return !((intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> +		  XELPDP_PMDEMAND_REQ_ENABLE) ||
> +		(intel_de_read(i915, GEN12_DCPR_STATUS_1) &
> +		 XELPDP_PMDEMAND_INFLIGHT_STATUS));
> +}
> +
> +static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
> +{
> +	return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> +		 XELPDP_PMDEMAND_REQ_ENABLE);
> +}
> +
> +static int intel_pmdemand_wait(struct drm_i915_private *i915)
> +{
> +	DEFINE_WAIT(wait);
> +	int ret;
> +	const unsigned int timeout_ms = 10;
> +
> +	ret = wait_event_timeout(i915->display.pmdemand.waitqueue,
> +				 intel_pmdemand_req_complete(i915),
> +				 msecs_to_jiffies_timeout(timeout_ms));
> +	if (ret == 0)
> +		drm_err(&i915->drm,
> +			"timed out waiting for Punit PM Demand Response\n");
> +
> +	return ret;
> +}
> +
> +/* Required to be programmed during Display Init Sequences. */
> +void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
> +				 u8 dbuf_slices)
> +{
> +	u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
> +
> +	mutex_lock(&i915->display.pmdemand.lock);
> +	if (drm_WARN_ON(&i915->drm,
> +			!intel_pmdemand_check_prev_transaction(i915)))
> +		goto unlock;
> +
> +	intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> +		     XELPDP_PMDEMAND_DBUFS_MASK, XELPDP_PMDEMAND_DBUFS(dbufs));
> +	intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> +		     XELPDP_PMDEMAND_REQ_ENABLE);
> +
> +	intel_pmdemand_wait(i915);
> +
> +unlock:
> +	mutex_unlock(&i915->display.pmdemand.lock);
> +}
> +
> +static void update_pmdemand_values(const struct intel_pmdemand_state *new,
> +				   const struct intel_pmdemand_state *old,
> +				   u32 *reg1, u32 *reg2)
> +{
> +	u32 plls, tmp;
> +
> +	/*
> +	 * The pmdemand parameter updates happens in two steps. Pre plane and
> +	 * post plane updates. During the pre plane, as DE might still be
> +	 * handling with some old operations, to avoid unwanted performance
> +	 * issues, program the pmdemand parameters with higher of old and new
> +	 * values. And then after once settled, use the new parameter values
> +	 * as part of the post plane update.
> +	 */
> +
> +	/* Set 1*/
> +	*reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_BW_MASK;
> +	tmp = old ? max(old->qclk_gv_bw, new->qclk_gv_bw) : new->qclk_gv_bw;
> +	*reg1 |= XELPDP_PMDEMAND_QCLK_GV_BW(tmp);
> +
> +	*reg1 &= ~XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK;
> +	tmp = old ? max(old->voltage_index, new->voltage_index) :
> +		    new->voltage_index;
> +	*reg1 |= XELPDP_PMDEMAND_VOLTAGE_INDEX(tmp);
> +
> +	*reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK;
> +	tmp = old ? max(old->qclk_gv_index, new->qclk_gv_index) :
> +		    new->qclk_gv_index;
> +	*reg1 |= XELPDP_PMDEMAND_QCLK_GV_INDEX(tmp);
> +
> +	*reg1 &= ~XELPDP_PMDEMAND_PIPES_MASK;
> +	tmp = old ? max(old->active_pipes, new->active_pipes) :
> +		    new->active_pipes;
> +	*reg1 |= XELPDP_PMDEMAND_PIPES(tmp);
> +
> +	*reg1 &= ~XELPDP_PMDEMAND_PHYS_MASK;
> +	plls = hweight32(new->active_phys_plls_mask);
> +	if (old)
> +		plls = max(plls, hweight32(old->active_phys_plls_mask));
> +	*reg1 |= XELPDP_PMDEMAND_PHYS(plls);
> +
> +	/* Set 2*/
> +	*reg2 &= ~XELPDP_PMDEMAND_CDCLK_FREQ_MASK;
> +	tmp = old ? max(old->cdclk_freq_mhz, new->cdclk_freq_mhz) :
> +		    new->cdclk_freq_mhz;
> +	*reg2 |= XELPDP_PMDEMAND_CDCLK_FREQ(tmp);
> +
> +	*reg2 &= ~XELPDP_PMDEMAND_DDICLK_FREQ_MASK;
> +	tmp = old ? max(old->ddiclk_freq_mhz, new->ddiclk_freq_mhz) :
> +		    new->ddiclk_freq_mhz;
> +	*reg2 |= XELPDP_PMDEMAND_DDICLK_FREQ(tmp);
> +
> +	/* Hard code scalers to 7*/
> +	*reg2 &= ~XELPDP_PMDEMAND_SCALERS_MASK;
> +	tmp = old ? max(old->scalers, new->scalers) : new->scalers;
> +	*reg2 |= XELPDP_PMDEMAND_SCALERS(tmp);
> +
> +	/*
> +	 * Active_PLLs starts with 1 because of CDCLK PLL.
> +	 * TODO: Missing to account genlock filter when it gets used.
> +	 */
> +	*reg2 &= ~XELPDP_PMDEMAND_PLLS_MASK;
> +	*reg2 |= XELPDP_PMDEMAND_PLLS(plls + 1);
> +}
> +
> +static void intel_program_pmdemand(struct drm_i915_private *i915,
> +				   const struct intel_pmdemand_state *new,
> +				   const struct intel_pmdemand_state *old)
> +{
> +	bool changed = false;
> +	u32 reg1, mod_reg1;
> +	u32 reg2, mod_reg2;
> +
> +	mutex_lock(&i915->display.pmdemand.lock);
> +	if (drm_WARN_ON(&i915->drm,
> +			!intel_pmdemand_check_prev_transaction(i915)))
> +		goto unlock;
> +
> +	reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
> +	mod_reg1 = reg1;
> +
> +	reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
> +	mod_reg2 = reg2;
> +
> +	update_pmdemand_values(new, old, &mod_reg1, &mod_reg2);
> +
> +	if (reg1 != mod_reg1) {
> +		intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> +			       mod_reg1);
> +		changed = true;
> +	}
> +
> +	if (reg2 != mod_reg2) {
> +		intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> +			       mod_reg2);
> +		changed = true;
> +	}
> +
> +	/* Initiate pm demand request only if register values are changed */
> +	if (changed) {
> +		drm_dbg_kms(&i915->drm,
> +			    "initate pmdemand request values: (0x%x 0x%x)\n",
> +			    mod_reg1, mod_reg2);
> +
> +		intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> +			     XELPDP_PMDEMAND_REQ_ENABLE);
> +
> +		intel_pmdemand_wait(i915);
> +	}
> +
> +unlock:
> +	mutex_unlock(&i915->display.pmdemand.lock);
> +}
> +
> +static bool
> +intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
> +			     const struct intel_pmdemand_state *old)
> +{
> +	return memcmp(&new->qclk_gv_bw, &old->qclk_gv_bw,
> +		      sizeof(*new) - offsetof(typeof(*new), qclk_gv_bw)) != 0;
> +}
> +
> +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_pmdemand_state *new_pmdmnd_state =
> +		intel_atomic_get_new_pmdemand_state(state);
> +	const struct intel_pmdemand_state *old_pmdmnd_state =
> +		intel_atomic_get_old_pmdemand_state(state);
> +
> +	if (DISPLAY_VER(i915) < 14)
> +		return;
> +
> +	if (!new_pmdmnd_state ||
> +	    !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
> +		return;
> +
> +	intel_program_pmdemand(i915, new_pmdmnd_state, old_pmdmnd_state);
> +}
> +
> +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_pmdemand_state *new_pmdmnd_state =
> +		intel_atomic_get_new_pmdemand_state(state);
> +	const struct intel_pmdemand_state *old_pmdmnd_state =
> +		intel_atomic_get_old_pmdemand_state(state);
> +
> +	if (DISPLAY_VER(i915) < 14)
> +		return;
> +
> +	if (!new_pmdmnd_state ||
> +	    !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
> +		return;
> +
> +	intel_program_pmdemand(i915, new_pmdmnd_state, NULL);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> new file mode 100644
> index 000000000000..0114f4e0225a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef __INTEL_PMDEMAND_H__
> +#define __INTEL_PMDEMAND_H__
> +
> +#include <linux/types.h>
> +
> +struct drm_i915_private;
> +struct intel_atomic_state;
> +struct intel_crtc_state;
> +struct intel_plane_state;
> +
> +void intel_pmdemand_init(struct drm_i915_private *i915);
> +int intel_pmdemand_state_init(struct drm_i915_private *i915);
> +void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
> +				 u8 dbuf_slices);
> +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
> +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
> +int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
> +
> +#endif /* __INTEL_PMDEMAND_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2b94b8ca8ec9..907fa3aee179 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -41,6 +41,7 @@
>  #include "display/intel_fifo_underrun.h"
>  #include "display/intel_hotplug.h"
>  #include "display/intel_lpe_audio.h"
> +#include "display/intel_pmdemand.h"
>  #include "display/intel_psr.h"
>  #include "display/intel_psr_regs.h"
>  
> @@ -1986,12 +1987,25 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
>  		return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
>  }
>  
> +static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
> +{
> +	wake_up_all(&dev_priv->display.pmdemand.waitqueue);
> +}
> +
>  static void
>  gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>  {
>  	bool found = false;
>  
> -	if (iir & GEN8_DE_MISC_GSE) {
> +	if (DISPLAY_VER(dev_priv) >= 14 &&
> +	    (iir & (XELPDP_PMDEMAND_RSP | XELPDP_PMDEMAND_RSPTOUT_ERR))) {
> +		if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
> +			drm_dbg(&dev_priv->drm,
> +				"Error waiting for Punit PM Demand Response\n");
> +
> +		intel_pmdemand_irq_handler(dev_priv);
> +		found = true;
> +	} else if (iir & GEN8_DE_MISC_GSE) {
>  		intel_opregion_asle_intr(dev_priv);
>  		found = true;
>  	}
> @@ -3742,7 +3756,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>  		de_port_masked |= BXT_DE_PORT_GMBUS;
>  
> -	if (DISPLAY_VER(dev_priv) >= 11) {
> +	if (DISPLAY_VER(dev_priv) >= 14)
> +		de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
> +				  XELPDP_PMDEMAND_RSP;
> +	else if (DISPLAY_VER(dev_priv) >= 11) {
>  		enum port port;
>  
>  		if (intel_bios_is_dsi_present(dev_priv, &port))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dde6e91055bd..60c007aea1ce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4426,8 +4426,10 @@
>  #define GEN8_DE_MISC_IMR _MMIO(0x44464)
>  #define GEN8_DE_MISC_IIR _MMIO(0x44468)
>  #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> -#define  GEN8_DE_MISC_GSE		(1 << 27)
> -#define  GEN8_DE_EDP_PSR		(1 << 19)
> +#define  XELPDP_PMDEMAND_RSPTOUT_ERR	REG_BIT(27)
> +#define  GEN8_DE_MISC_GSE		REG_BIT(27)
> +#define  GEN8_DE_EDP_PSR		REG_BIT(19)
> +#define  XELPDP_PMDEMAND_RSP		REG_BIT(3)
>  
>  #define GEN8_PCU_ISR _MMIO(0x444e0)
>  #define GEN8_PCU_IMR _MMIO(0x444e4)
> @@ -4512,6 +4514,33 @@
>  #define  XELPDP_DP_ALT_HPD_LONG_DETECT		REG_BIT(1)
>  #define  XELPDP_DP_ALT_HPD_SHORT_DETECT		REG_BIT(0)
>  
> +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)		_MMIO(0x45230 + 4 * (dword))
> +#define  XELPDP_PMDEMAND_QCLK_GV_BW_MASK		REG_GENMASK(31, 16)
> +#define  XELPDP_PMDEMAND_QCLK_GV_BW(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
> +#define  XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK		REG_GENMASK(14, 12)
> +#define  XELPDP_PMDEMAND_VOLTAGE_INDEX(x)		REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
> +#define  XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK		REG_GENMASK(11, 8)
> +#define  XELPDP_PMDEMAND_QCLK_GV_INDEX(x)		REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
> +#define  XELPDP_PMDEMAND_PIPES_MASK			REG_GENMASK(7, 6)
> +#define  XELPDP_PMDEMAND_PIPES(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
> +#define  XELPDP_PMDEMAND_DBUFS_MASK			REG_GENMASK(5, 4)
> +#define  XELPDP_PMDEMAND_DBUFS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
> +#define  XELPDP_PMDEMAND_PHYS_MASK			REG_GENMASK(2, 0)
> +#define  XELPDP_PMDEMAND_PHYS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
> +
> +#define  XELPDP_PMDEMAND_REQ_ENABLE			REG_BIT(31)
> +#define  XELPDP_PMDEMAND_CDCLK_FREQ_MASK		REG_GENMASK(30, 20)
> +#define  XELPDP_PMDEMAND_CDCLK_FREQ(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
> +#define  XELPDP_PMDEMAND_DDICLK_FREQ_MASK		REG_GENMASK(18, 8)
> +#define  XELPDP_PMDEMAND_DDICLK_FREQ(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
> +#define  XELPDP_PMDEMAND_SCALERS_MASK			REG_GENMASK(6, 4)
> +#define  XELPDP_PMDEMAND_SCALERS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
> +#define  XELPDP_PMDEMAND_PLLS_MASK			REG_GENMASK(2, 0)
> +#define  XELPDP_PMDEMAND_PLLS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
> +
> +#define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
> +#define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
> +
>  #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
>  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
>  #define   ILK_ELPIN_409_SELECT	REG_BIT(25)
> @@ -4671,6 +4700,9 @@
>  #define   DCPR_SEND_RESP_IMM			REG_BIT(25)
>  #define   DCPR_CLEAR_MEMSTAT_DIS		REG_BIT(24)
>  
> +#define XELPD_CHICKEN_DCPR_3			_MMIO(0x46438)
> +#define   DMD_RSP_TIMEOUT_DISABLE		REG_BIT(19)
> +
>  #define SKL_DFSM			_MMIO(0x51000)
>  #define   SKL_DFSM_DISPLAY_PM_DISABLE	(1 << 27)
>  #define   SKL_DFSM_DISPLAY_HDCP_DISABLE	(1 << 25)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v3 1/8] drm/i915: fix the derating percentage for MTL

[Matt Roper]

On Thu, Apr 27, 2023 at 06:00:09PM +0300, Vinod Govindapillai wrote:
> Follow the values from bspec for the percentage overhead for
> efficiency in MTL BW calculations.
> 
> Bspec: 64631
> 
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

Looks like the bspec was updated with this new value on March 30th.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 597d5816ad1b..ab405c48ca3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -379,7 +379,7 @@ static const struct intel_sa_info mtl_sa_info = {
>  	.deburst = 32,
>  	.deprogbwlimit = 38, /* GB/s */
>  	.displayrtids = 256,
> -	.derating = 20,
> +	.derating = 10,
>  };
>  
>  static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v3 7/8] drm/i915/mtl: Add support for PM DEMAND

[Govindapillai, Vinod]

Hello

Thanks for the comments. Pls see some inline replies..

On Thu, 2023-04-27 at 17:24 -0300, Gustavo Sousa wrote:
> Quoting Vinod Govindapillai (2023-04-27 12:00:15)
> > From: Mika Kahola <mika.kahola@intel.com>
> > 
> > Display14 introduces a new way to instruct the PUnit with
> > power and bandwidth requirements of DE. Add the functionality
> > to program the registers and handle waits using interrupts.
> > The current wait time for timeouts is programmed for 10 msecs to
> > factor in the worst case scenarios. Changes made to use REG_BIT
> > for a register that we touched(GEN8_DE_MISC_IER _MMIO).
> > 
> > Wa_14016740474 is added which applies to Xe_LPD+ display
> > 
> > v2: checkpatch warning fixes, simplify program pmdemand part
> > 
> > v3: update to dbufs and pipes values to pmdemand register(stan)
> >    Removed the macro usage in update_pmdemand_values()
> > 
> > Bspec: 66451, 64636, 64602, 64603
> > Cc: Matt Atwood <matthew.s.atwood@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> > drivers/gpu/drm/i915/Makefile                 |   3 +-
> > drivers/gpu/drm/i915/display/intel_display.c  |   7 +
> > .../gpu/drm/i915/display/intel_display_core.h |   6 +
> > .../drm/i915/display/intel_display_driver.c   |   7 +
> > .../drm/i915/display/intel_display_power.c    |   8 +
> > drivers/gpu/drm/i915/display/intel_pmdemand.c | 455 ++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_pmdemand.h |  24 +
> > drivers/gpu/drm/i915/i915_irq.c               |  21 +-
> > drivers/gpu/drm/i915/i915_reg.h               |  36 +-
> > 9 files changed, 562 insertions(+), 5 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
> > 
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 9af76e376ca9..eb899fa86e51 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -281,7 +281,8 @@ i915-y += \
> >        display/i9xx_wm.o \
> >        display/skl_scaler.o \
> >        display/skl_universal_plane.o \
> > -  display/skl_watermark.o
> > +  display/skl_watermark.o \
> > +  display/intel_pmdemand.o
> > i915-$(CONFIG_ACPI) += \
> >        display/intel_acpi.o \
> >        display/intel_opregion.o
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index bf391a6cd8d6..f98e235fadc6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -99,6 +99,7 @@
> > #include "intel_pcode.h"
> > #include "intel_pipe_crc.h"
> > #include "intel_plane_initial.h"
> > +#include "intel_pmdemand.h"
> > #include "intel_pps.h"
> > #include "intel_psr.h"
> > #include "intel_sdvo.h"
> > @@ -6306,6 +6307,10 @@ int intel_atomic_check(struct drm_device *dev,
> >                        return ret;
> >        }
> > 
> > +  ret = intel_pmdemand_atomic_check(state);
> > +  if (ret)
> > +          goto fail;
> > +
> >        ret = intel_atomic_check_crtcs(state);
> >        if (ret)
> >                goto fail;
> > @@ -6960,6 +6965,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> >        }
> > 
> >        intel_sagv_pre_plane_update(state);
> > +  intel_pmdemand_pre_plane_update(state);
> > 
> >        /* Complete the events for pipes that have now been disabled */
> >        for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > @@ -7070,6 +7076,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> >                intel_verify_planes(state);
> > 
> >        intel_sagv_post_plane_update(state);
> > +  intel_pmdemand_post_plane_update(state);
> > 
> >        drm_atomic_helper_commit_hw_done(&state->base);
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> > b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 9f66d734edf6..9471a052aa57 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -345,6 +345,12 @@ struct intel_display {
> >                struct intel_global_obj obj;
> >        } dbuf;
> > 
> > +  struct {
> > +          wait_queue_head_t waitqueue;
> > +          struct mutex lock;
> > +          struct intel_global_obj obj;
> > +  } pmdemand;
> > +
> >        struct {
> >                /*
> >                 * dkl.phy_lock protects against concurrent access of the
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > index 60ce10fc7205..79853d8c3240 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > @@ -47,6 +47,7 @@
> > #include "intel_opregion.h"
> > #include "intel_overlay.h"
> > #include "intel_plane_initial.h"
> > +#include "intel_pmdemand.h"
> > #include "intel_pps.h"
> > #include "intel_quirks.h"
> > #include "intel_vga.h"
> > @@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
> >        if (ret < 0)
> >                goto cleanup_vga;
> > 
> > +  intel_pmdemand_init(i915);
> > +
> >        intel_power_domains_init_hw(i915, false);
> > 
> >        if (!HAS_DISPLAY(i915))
> > @@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
> >        if (ret)
> >                goto cleanup_vga_client_pw_domain_dmc;
> > 
> > +  ret = intel_pmdemand_state_init(i915);
> > +  if (ret)
> > +          goto cleanup_vga_client_pw_domain_dmc;
> > +
> >        init_llist_head(&i915->display.atomic_helper.free_list);
> >        INIT_WORK(&i915->display.atomic_helper.free_work,
> >                  intel_atomic_helper_free_state_worker);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 5150069f3f82..f5c5a486efbc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -20,6 +20,7 @@
> > #include "intel_mchbar_regs.h"
> > #include "intel_pch_refclk.h"
> > #include "intel_pcode.h"
> > +#include "intel_pmdemand.h"
> > #include "intel_pps_regs.h"
> > #include "intel_snps_phy.h"
> > #include "skl_watermark.h"
> > @@ -1085,6 +1086,10 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
> >        dev_priv->display.dbuf.enabled_slices =
> >                intel_enabled_dbuf_slices_mask(dev_priv);
> > 
> > +  if (DISPLAY_VER(dev_priv) >= 14)
> > +          intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
> > +                                      dev_priv->display.dbuf.enabled_slices);
> > +
> >        /*
> >         * Just power up at least 1 slice, we will
> >         * figure out later which slices we have and what we need.
> > @@ -1096,6 +1101,9 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
> > static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
> > {
> >        gen9_dbuf_slices_update(dev_priv, 0);
> > +
> > +  if (DISPLAY_VER(dev_priv) >= 14)
> > +          intel_program_dbuf_pmdemand(dev_priv, 0);
> > }
> > 
> > static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
> > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > new file mode 100644
> > index 000000000000..df6429e7059d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > @@ -0,0 +1,455 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2024 Intel Corporation
> > + */
> > +
> > +#include <linux/bitops.h>
> > +
> > +#include "i915_drv.h"
> > +#include "i915_reg.h"
> > +#include "intel_bw.h"
> > +#include "intel_cdclk.h"
> > +#include "intel_cx0_phy.h"
> > +#include "intel_de.h"
> > +#include "intel_display.h"
> > +#include "intel_display_trace.h"
> > +#include "intel_pmdemand.h"
> > +#include "skl_watermark.h"
> > +
> > +struct intel_pmdemand_state {
> > +  struct intel_global_state base;
> > +
> > +  u16 qclk_gv_bw;
> > +  u8 voltage_index;
> > +  u8 qclk_gv_index;
> > +  u8 active_pipes;
> > +  u8 dbufs;
> > +  u8 active_phys_plls_mask;
> 
> Is u8 enough for the mask? The enum phy shows 9 possible PHY_* members.
> Also, I think having BUILD_BUG_ON() somewhere in this file to make sure
> we have enough bits would be nice.
Thanks. updated.
> 
> > +  u16 cdclk_freq_mhz;
> > +  u16 ddiclk_freq_mhz;
> > +  u8 scalers;
> > +};
> > +
> > +#define to_intel_pmdemand_state(x) container_of((x), struct intel_pmdemand_state, base)
> > +
> > +static struct intel_global_state *
> > +intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
> > +{
> > +  struct intel_pmdemand_state *pmdmnd_state;
> > +
> > +  pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state), GFP_KERNEL);
> > +  if (!pmdmnd_state)
> > +          return NULL;
> > +
> > +  return &pmdmnd_state->base;
> > +}
> > +
> > +static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
> > +                                   struct intel_global_state *state)
> > +{
> > +  kfree(state);
> > +}
> > +
> > +static const struct intel_global_state_funcs intel_pmdemand_funcs = {
> > +  .atomic_duplicate_state = intel_pmdemand_duplicate_state,
> > +  .atomic_destroy_state = intel_pmdemand_destroy_state,
> > +};
> > +
> > +static struct intel_pmdemand_state *
> > +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
> > +{
> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > +  struct intel_global_state *pmdemand_state;
> > +
> > +  pmdemand_state =
> > +          intel_atomic_get_global_obj_state(state,
> > +                                            &i915->display.pmdemand.obj);
> > +  if (IS_ERR(pmdemand_state))
> > +          return ERR_CAST(pmdemand_state);
> > +
> > +  return to_intel_pmdemand_state(pmdemand_state);
> > +}
> > +
> > +static struct intel_pmdemand_state *
> > +intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
> > +{
> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > +  struct intel_global_state *pmdemand_state;
> > +
> > +  pmdemand_state = intel_atomic_get_old_global_obj_state(state, &i915->display.pmdemand.obj);
> 
> Wouldn't it be safer if we returned early here when pmdemand_state is
> NULL?
> 
> I think to_intel_pmdemand_state(NULL) pmdemand_state just happens to
> work (i.e. still returns NULL) because the "base" member is at the
> beginning of the struct. However, we shouldn't rely on that IMO.

Well. It is a valid point. But the base pointer is the first member for exaclty the reason you
pointed out. So  to prevent someone from accidentally move that "base" from that position, I added a
BUILD_BUG_ON() check. There are few other state objects which lack such a check. I will address that
as a separate patch.

> 
> > +
> > +  return to_intel_pmdemand_state(pmdemand_state);
> > +}
> > +
> > +static struct intel_pmdemand_state *
> > +intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
> > +{
> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > +  struct intel_global_state *pmdemand_state;
> > +
> > +  pmdemand_state = intel_atomic_get_new_global_obj_state(state, &i915->display.pmdemand.obj);
> 
> Just as with intel_atomic_get_old_pmdemand_state(), shouldn't we return
> early if pmdemand_state is NULL here?
> 
> > +
> > +  return to_intel_pmdemand_state(pmdemand_state);
> > +}
> > +
> > +int intel_pmdemand_state_init(struct drm_i915_private *i915)
> > +{
> > +  struct intel_pmdemand_state *pmdemand_state;
> > +
> > +  pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
> > +  if (!pmdemand_state)
> > +          return -ENOMEM;
> > +
> > +  intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
> > +                               &pmdemand_state->base,
> > +                               &intel_pmdemand_funcs);
> > +
> > +
> > +  if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> > +          /* Wa_14016740474 */
> > +          intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
> > +
> > +  return 0;
> > +}
> > +
> > +void intel_pmdemand_init(struct drm_i915_private *i915)
> > +{
> > +  mutex_init(&i915->display.pmdemand.lock);
> > +  init_waitqueue_head(&i915->display.pmdemand.waitqueue);
> > +}
> 
> The functions intel_pmdemand_state_init() and intel_pmdemand_init() are
> both called from the same place. Furthermore,
> intel_pmdemand_state_init() isn't only initializing the state, as the
> Wa_14016740474 workaround is programmed there. Could we have only the
> function intel_pmdemand_init() and incorporate what
> intel_pmdemand_state_init() does in it?

I tried that earlier and wasn't possible. Because the intel_power_domains_init_hw() will call the
pmdemand debuf config. And I can't recall the other issue. But I will confirm this again and update
as I am not able to try this locally.
> 
> > +
> > +static bool pmdemand_needs_update(struct intel_atomic_state *state)
> > +{
> > +  bool changed = false;
> > +  struct intel_crtc *crtc;
> > +  int i;
> > +  const struct intel_bw_state *new_bw_state, *old_bw_state;
> > +  const struct intel_cdclk_state *new_cdclk_state;
> > +  const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > +  const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> > +
> > +  for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > +                                      new_crtc_state, i) {
> > +          new_bw_state = intel_atomic_get_new_bw_state(state);
> > +          old_bw_state = intel_atomic_get_old_bw_state(state);
> > +
> > +          new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> > +          old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> > +
> > +          new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> > +
> > +          if ((new_bw_state && new_bw_state->qgv_point_peakbw !=
> > +               old_bw_state->qgv_point_peakbw) ||
> > +              (new_dbuf_state && new_dbuf_state->active_pipes !=
> > +               old_dbuf_state->active_pipes) || new_cdclk_state)
> > +                  changed = true;
> > +
> > +          /*
> > +           * break needs to be removed, if some crtc_state dependent
> > +           * parameters are added here
> > +           */
> > +          break;
> > +  }
> > +
> > +  return changed;
> > +}
> > +
> > +int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
> > +{
> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > +  int port_clock = 0;
> > +  struct intel_crtc *crtc;
> > +  struct intel_encoder *encoder;
> > +  const struct intel_bw_state *new_bw_state;
> > +  const struct intel_cdclk_state *new_cdclk_state;
> > +  const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > +  const struct intel_dbuf_state *new_dbuf_state;
> > +  struct intel_pmdemand_state *new_pmdemand_state;
> > +  enum phy phy;
> > +  int i, ret;
> > +
> > +  if (DISPLAY_VER(i915) < 14)
> > +          return 0;
> > +
> > +  if (!pmdemand_needs_update(state))
> > +          return 0;
> > +
> > +  new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
> > +  if (IS_ERR(new_pmdemand_state))
> > +          return PTR_ERR(new_pmdemand_state);
> > +
> > +  ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
> > +  if (ret)
> > +          return ret;
> > +
> > +  /* Punit figures out the voltage index based on bandwidth*/
> > +  new_bw_state = intel_atomic_get_bw_state(state);
> > +  if (IS_ERR(new_bw_state))
> > +          return PTR_ERR(new_bw_state);
> > +
> > +  /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
> > +  new_pmdemand_state->qclk_gv_index = 0;
> > +  new_pmdemand_state->qclk_gv_bw =
> > +          min_t(u16, new_bw_state->qgv_point_peakbw, 0xffff);
> > +
> > +  new_dbuf_state = intel_atomic_get_dbuf_state(state);
> > +  if (IS_ERR(new_dbuf_state))
> > +          return PTR_ERR(new_dbuf_state);
> > +
> > +  i = hweight8(new_dbuf_state->active_pipes);
> > +  new_pmdemand_state->active_pipes = min(i, 3);
> > +
> > +  new_cdclk_state = intel_atomic_get_cdclk_state(state);
> > +  if (IS_ERR(new_cdclk_state))
> > +          return PTR_ERR(new_cdclk_state);
> > +
> > +  new_pmdemand_state->voltage_index =
> > +          new_cdclk_state->logical.voltage_level;
> > +  /* KHz to MHz */
> > +  new_pmdemand_state->cdclk_freq_mhz =
> > +          DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
> > +
> > +  new_pmdemand_state->active_phys_plls_mask = 0;
> > +
> > +  for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > +                                      new_crtc_state, i) {
> > +          if (!new_crtc_state->hw.active)
> > +                  continue;
> > +
> > +          encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> > +          if (!encoder)
> > +                  continue;
> > +
> > +          phy = intel_port_to_phy(i915, encoder->port);
> > +
> > +          if (intel_is_c10phy(i915, phy))
> > +                  new_pmdemand_state->active_phys_plls_mask |= BIT(phy);
> > +
> > +          port_clock = max(port_clock, new_crtc_state->port_clock);
> > +  }
> 
> As previously noted in https://patchwork.freedesktop.org/patch/530495 ,
> I'm under the impression that this loop would not let us account for al
> active crtcs, only those currently being touched by this atomic
> transaction. Am I wrong to assume that
> for_each_oldnew_intel_crtc_in_state() would only iterate over crtcs
> touched by the atomic update?

I checked the intel_bw_check_data_rate() which should be doing something similar to find out about
the datarate from eachi pipe and figure out the total data rate. So I thought this should be
sufficient. 

> 
> > +
> > +  /* To MHz */
> > +  new_pmdemand_state->ddiclk_freq_mhz = DIV_ROUND_UP(port_clock, 1000);
> > +
> > +  /*
> > +   * Setting scalers to max as it can not be calculated during flips and
> > +   * fastsets without taking global states locks.
> > +   */
> > +  new_pmdemand_state->scalers = 7;
> > +
> > +  ret = intel_atomic_serialize_global_state(&new_pmdemand_state->base);
> > +  if (ret)
> > +          return ret;
> > +
> > +  return 0;
> > +}
> > +
> > +static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
> > +{
> > +  return !((intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> > +            XELPDP_PMDEMAND_REQ_ENABLE) ||
> > +          (intel_de_read(i915, GEN12_DCPR_STATUS_1) &
> > +           XELPDP_PMDEMAND_INFLIGHT_STATUS));
> > +}
> > +
> > +static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
> > +{
> > +  return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> > +           XELPDP_PMDEMAND_REQ_ENABLE);
> > +}
> > +
> > +static int intel_pmdemand_wait(struct drm_i915_private *i915)
> > +{
> > +  DEFINE_WAIT(wait);
> > +  int ret;
> > +  const unsigned int timeout_ms = 10;
> > +
> > +  ret = wait_event_timeout(i915->display.pmdemand.waitqueue,
> > +                           intel_pmdemand_req_complete(i915),
> > +                           msecs_to_jiffies_timeout(timeout_ms));
> > +  if (ret == 0)
> > +          drm_err(&i915->drm,
> > +                  "timed out waiting for Punit PM Demand Response\n");
> > +
> > +  return ret;
> > +}
> > +
> > +/* Required to be programmed during Display Init Sequences. */
> > +void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
> > +                           u8 dbuf_slices)
> > +{
> > +  u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
> > +
> > +  mutex_lock(&i915->display.pmdemand.lock);
> > +  if (drm_WARN_ON(&i915->drm,
> > +                  !intel_pmdemand_check_prev_transaction(i915)))
> > +          goto unlock;
> > +
> > +  intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> > +               XELPDP_PMDEMAND_DBUFS_MASK, XELPDP_PMDEMAND_DBUFS(dbufs));
> > +  intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> > +               XELPDP_PMDEMAND_REQ_ENABLE);
> > +
> > +  intel_pmdemand_wait(i915);
> > +
> > +unlock:
> > +  mutex_unlock(&i915->display.pmdemand.lock);
> > +}
> > +
> > +static void update_pmdemand_values(const struct intel_pmdemand_state *new,
> > +                             const struct intel_pmdemand_state *old,
> > +                             u32 *reg1, u32 *reg2)
> > +{
> > +  u32 plls, tmp;
> > +
> > +  /*
> > +   * The pmdemand parameter updates happens in two steps. Pre plane and
> > +   * post plane updates. During the pre plane, as DE might still be
> > +   * handling with some old operations, to avoid unwanted performance
> > +   * issues, program the pmdemand parameters with higher of old and new
> > +   * values. And then after once settled, use the new parameter values
> > +   * as part of the post plane update.
> > +   */
> > +
> > +  /* Set 1*/
> > +  *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_BW_MASK;
> > +  tmp = old ? max(old->qclk_gv_bw, new->qclk_gv_bw) : new->qclk_gv_bw;
> > +  *reg1 |= XELPDP_PMDEMAND_QCLK_GV_BW(tmp);
> > +
> > +  *reg1 &= ~XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK;
> > +  tmp = old ? max(old->voltage_index, new->voltage_index) :
> > +              new->voltage_index;
> > +  *reg1 |= XELPDP_PMDEMAND_VOLTAGE_INDEX(tmp);
> > +
> > +  *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK;
> > +  tmp = old ? max(old->qclk_gv_index, new->qclk_gv_index) :
> > +              new->qclk_gv_index;
> > +  *reg1 |= XELPDP_PMDEMAND_QCLK_GV_INDEX(tmp);
> > +
> > +  *reg1 &= ~XELPDP_PMDEMAND_PIPES_MASK;
> > +  tmp = old ? max(old->active_pipes, new->active_pipes) :
> > +              new->active_pipes;
> > +  *reg1 |= XELPDP_PMDEMAND_PIPES(tmp);
> > +
> > +  *reg1 &= ~XELPDP_PMDEMAND_PHYS_MASK;
> > +  plls = hweight32(new->active_phys_plls_mask);
> > +  if (old)
> > +          plls = max(plls, hweight32(old->active_phys_plls_mask));
> > +  *reg1 |= XELPDP_PMDEMAND_PHYS(plls);
> 
> If plls > 7, we would be potentially programming this wrong (e.g. for
> plls=8, we would setting the field to 0).

Thanks for pointing that out. Fixed.

> 
> > +
> > +  /* Set 2*/
> > +  *reg2 &= ~XELPDP_PMDEMAND_CDCLK_FREQ_MASK;
> > +  tmp = old ? max(old->cdclk_freq_mhz, new->cdclk_freq_mhz) :
> > +              new->cdclk_freq_mhz;
> > +  *reg2 |= XELPDP_PMDEMAND_CDCLK_FREQ(tmp);
> > +
> > +  *reg2 &= ~XELPDP_PMDEMAND_DDICLK_FREQ_MASK;
> > +  tmp = old ? max(old->ddiclk_freq_mhz, new->ddiclk_freq_mhz) :
> > +              new->ddiclk_freq_mhz;
> > +  *reg2 |= XELPDP_PMDEMAND_DDICLK_FREQ(tmp);
> > +
> > +  /* Hard code scalers to 7*/
> 
> I think this comment can be dropped: the hardcoding happens in
> intel_pmdemand_atomic_check().

Done
> 
> > +  *reg2 &= ~XELPDP_PMDEMAND_SCALERS_MASK;
> > +  tmp = old ? max(old->scalers, new->scalers) : new->scalers;
> > +  *reg2 |= XELPDP_PMDEMAND_SCALERS(tmp);
> > +
> > +  /*
> > +   * Active_PLLs starts with 1 because of CDCLK PLL.
> > +   * TODO: Missing to account genlock filter when it gets used.
> > +   */
> > +  *reg2 &= ~XELPDP_PMDEMAND_PLLS_MASK;
> 
> I think we are missing the ternary operator here to select the maximum
> value for the pre-plane case.
As pet the above comments, it is just the plls from step earlier + 1

> 
> > +  *reg2 |= XELPDP_PMDEMAND_PLLS(plls + 1);
> > +}
> > +
> > +static void intel_program_pmdemand(struct drm_i915_private *i915,
> > +                             const struct intel_pmdemand_state *new,
> > +                             const struct intel_pmdemand_state *old)
> > +{
> > +  bool changed = false;
> > +  u32 reg1, mod_reg1;
> > +  u32 reg2, mod_reg2;
> > +
> > +  mutex_lock(&i915->display.pmdemand.lock);
> > +  if (drm_WARN_ON(&i915->drm,
> > +                  !intel_pmdemand_check_prev_transaction(i915)))
> > +          goto unlock;
> 
> According to the spec, we should wait and timeout after 10ms here.
> 
> > +
> > +  reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
> > +  mod_reg1 = reg1;
> > +
> > +  reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
> > +  mod_reg2 = reg2;
> > +
> > +  update_pmdemand_values(new, old, &mod_reg1, &mod_reg2);
> > +
> > +  if (reg1 != mod_reg1) {
> > +          intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> > +                         mod_reg1);
> > +          changed = true;
> > +  }
> > +
> > +  if (reg2 != mod_reg2) {
> > +          intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> > +                         mod_reg2);
> > +          changed = true;
> > +  }
> > +
> > +  /* Initiate pm demand request only if register values are changed */
> > +  if (changed) {
> 
> Nitpick: we could have
> 
>     if (!changed)
>             goto unlock;
> 
> and dedent the block below.

Done.
> 
> > +          drm_dbg_kms(&i915->drm,
> > +                      "initate pmdemand request values: (0x%x 0x%x)\n",
> > +                      mod_reg1, mod_reg2);
> > +
> > +          intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> > +                       XELPDP_PMDEMAND_REQ_ENABLE);
> > +
> > +          intel_pmdemand_wait(i915);
> > +  }
> > +
> > +unlock:
> > +  mutex_unlock(&i915->display.pmdemand.lock);
> > +}
> > +
> > +static bool
> > +intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
> > +                       const struct intel_pmdemand_state *old)
> > +{
> > +  return memcmp(&new->qclk_gv_bw, &old->qclk_gv_bw,
> > +                sizeof(*new) - offsetof(typeof(*new), qclk_gv_bw)) != 0;
> > +}
> > +
> > +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
> > +{
> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > +  const struct intel_pmdemand_state *new_pmdmnd_state =
> > +          intel_atomic_get_new_pmdemand_state(state);
> > +  const struct intel_pmdemand_state *old_pmdmnd_state =
> > +          intel_atomic_get_old_pmdemand_state(state);
> > +
> > +  if (DISPLAY_VER(i915) < 14)
> > +          return;
> > +
> > +  if (!new_pmdmnd_state ||
> > +      !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
> > +          return;
> > +
> > +  intel_program_pmdemand(i915, new_pmdmnd_state, old_pmdmnd_state);
> > +}
> > +
> > +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
> > +{
> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > +  const struct intel_pmdemand_state *new_pmdmnd_state =
> > +          intel_atomic_get_new_pmdemand_state(state);
> > +  const struct intel_pmdemand_state *old_pmdmnd_state =
> > +          intel_atomic_get_old_pmdemand_state(state);
> > +
> > +  if (DISPLAY_VER(i915) < 14)
> > +          return;
> > +
> > +  if (!new_pmdmnd_state ||
> > +      !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
> > +          return;
> > +
> > +  intel_program_pmdemand(i915, new_pmdmnd_state, NULL);
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h
> > b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> > new file mode 100644
> > index 000000000000..0114f4e0225a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> > @@ -0,0 +1,24 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2023 Intel Corporation
> > + */
> > +
> > +#ifndef __INTEL_PMDEMAND_H__
> > +#define __INTEL_PMDEMAND_H__
> > +
> > +#include <linux/types.h>
> > +
> > +struct drm_i915_private;
> > +struct intel_atomic_state;
> > +struct intel_crtc_state;
> > +struct intel_plane_state;
> > +
> > +void intel_pmdemand_init(struct drm_i915_private *i915);
> > +int intel_pmdemand_state_init(struct drm_i915_private *i915);
> > +void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
> > +                           u8 dbuf_slices);
> > +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
> > +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
> > +int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
> > +
> > +#endif /* __INTEL_PMDEMAND_H__ */
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 2b94b8ca8ec9..907fa3aee179 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -41,6 +41,7 @@
> > #include "display/intel_fifo_underrun.h"
> > #include "display/intel_hotplug.h"
> > #include "display/intel_lpe_audio.h"
> > +#include "display/intel_pmdemand.h"
> > #include "display/intel_psr.h"
> > #include "display/intel_psr_regs.h"
> > 
> > @@ -1986,12 +1987,25 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
> >                return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> > }
> > 
> > +static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
> > +{
> > +  wake_up_all(&dev_priv->display.pmdemand.waitqueue);
> > +}
> > +
> > static void
> > gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> > {
> >        bool found = false;
> > 
> > -  if (iir & GEN8_DE_MISC_GSE) {
> > +  if (DISPLAY_VER(dev_priv) >= 14 &&
> > +      (iir & (XELPDP_PMDEMAND_RSP | XELPDP_PMDEMAND_RSPTOUT_ERR))) {
> > +          if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
> 
> I think we should have the (iir & (XELPDP_PMDEMAND_RSP |
> XELPDP_PMDEMAND_RSPTOUT_ERR)) part as nested if statement here.
> Otherwise, when the interrupt did not happen, we could endup checking
> for the GEN8_DE_MISC_GSE even when DISPLAY_VER(dev_priv) >= 14.
> 
> Even though we know that iir & GEN8_DE_MISC_GSE would be false in this
> situation (because both XELPDP_PMDEMAND_RSPTOUT_ERR and GEN8_DE_MISC_GSE
> map to the same bit), I think having that one checked only for previous
> display engines would sound more correct semantically speaking.

Thanks. updated.

> 
> > +                  drm_dbg(&dev_priv->drm,
> > +                          "Error waiting for Punit PM Demand Response\n");
> > +
> > +          intel_pmdemand_irq_handler(dev_priv);
> > +          found = true;
> > +  } else if (iir & GEN8_DE_MISC_GSE) {
> >                intel_opregion_asle_intr(dev_priv);
> >                found = true;
> >        }
> > @@ -3742,7 +3756,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> >        if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> >                de_port_masked |= BXT_DE_PORT_GMBUS;
> > 
> > -  if (DISPLAY_VER(dev_priv) >= 11) {
> > +  if (DISPLAY_VER(dev_priv) >= 14)
> > +          de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
> > +                            XELPDP_PMDEMAND_RSP;
> > +  else if (DISPLAY_VER(dev_priv) >= 11) {
> >                enum port port;
> > 
> >                if (intel_bios_is_dsi_present(dev_priv, &port))
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index dde6e91055bd..60c007aea1ce 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4426,8 +4426,10 @@
> > #define GEN8_DE_MISC_IMR _MMIO(0x44464)
> > #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> > #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> > -#define  GEN8_DE_MISC_GSE         (1 << 27)
> > -#define  GEN8_DE_EDP_PSR          (1 << 19)
> > +#define  XELPDP_PMDEMAND_RSPTOUT_ERR      REG_BIT(27)
> > +#define  GEN8_DE_MISC_GSE         REG_BIT(27)
> > +#define  GEN8_DE_EDP_PSR          REG_BIT(19)
> > +#define  XELPDP_PMDEMAND_RSP              REG_BIT(3)
> > 
> > #define GEN8_PCU_ISR _MMIO(0x444e0)
> > #define GEN8_PCU_IMR _MMIO(0x444e4)
> > @@ -4512,6 +4514,33 @@
> > #define  XELPDP_DP_ALT_HPD_LONG_DETECT         REG_BIT(1)
> > #define  XELPDP_DP_ALT_HPD_SHORT_DETECT                REG_BIT(0)
> > 
> > +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)           _MMIO(0x45230 + 4 * (dword))
> > +#define  XELPDP_PMDEMAND_QCLK_GV_BW_MASK          REG_GENMASK(31, 16)
> > +#define  XELPDP_PMDEMAND_QCLK_GV_BW(x)                   
> > REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
> > +#define  XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK               REG_GENMASK(14, 12)
> > +#define  XELPDP_PMDEMAND_VOLTAGE_INDEX(x)        
> > REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
> > +#define  XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK               REG_GENMASK(11, 8)
> > +#define  XELPDP_PMDEMAND_QCLK_GV_INDEX(x)        
> > REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
> > +#define  XELPDP_PMDEMAND_PIPES_MASK                       REG_GENMASK(7, 6)
> > +#define  XELPDP_PMDEMAND_PIPES(x)                 REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
> > +#define  XELPDP_PMDEMAND_DBUFS_MASK                       REG_GENMASK(5, 4)
> > +#define  XELPDP_PMDEMAND_DBUFS(x)                 REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
> > +#define  XELPDP_PMDEMAND_PHYS_MASK                        REG_GENMASK(2, 0)
> > +#define  XELPDP_PMDEMAND_PHYS(x)                  REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
> > +
> > +#define  XELPDP_PMDEMAND_REQ_ENABLE                       REG_BIT(31)
> > +#define  XELPDP_PMDEMAND_CDCLK_FREQ_MASK          REG_GENMASK(30, 20)
> > +#define  XELPDP_PMDEMAND_CDCLK_FREQ(x)                   
> > REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
> > +#define  XELPDP_PMDEMAND_DDICLK_FREQ_MASK         REG_GENMASK(18, 8)
> > +#define  XELPDP_PMDEMAND_DDICLK_FREQ(x)                  
> > REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
> > +#define  XELPDP_PMDEMAND_SCALERS_MASK                     REG_GENMASK(6, 4)
> > +#define  XELPDP_PMDEMAND_SCALERS(x)                      
> > REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
> > +#define  XELPDP_PMDEMAND_PLLS_MASK                        REG_GENMASK(2, 0)
> > +#define  XELPDP_PMDEMAND_PLLS(x)                  REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
> > +
> > +#define GEN12_DCPR_STATUS_1                               _MMIO(0x46440)
> > +#define  XELPDP_PMDEMAND_INFLIGHT_STATUS          REG_BIT(26)
> > +
> > #define ILK_DISPLAY_CHICKEN2   _MMIO(0x42004)
> > /* Required on all Ironlake and Sandybridge according to the B-Spec. */
> > #define   ILK_ELPIN_409_SELECT REG_BIT(25)
> > @@ -4671,6 +4700,9 @@
> > #define   DCPR_SEND_RESP_IMM                   REG_BIT(25)
> > #define   DCPR_CLEAR_MEMSTAT_DIS               REG_BIT(24)
> > 
> > +#define XELPD_CHICKEN_DCPR_3                      _MMIO(0x46438)
> > +#define   DMD_RSP_TIMEOUT_DISABLE         REG_BIT(19)
> > +
> > #define SKL_DFSM                       _MMIO(0x51000)
> > #define   SKL_DFSM_DISPLAY_PM_DISABLE  (1 << 27)
> > #define   SKL_DFSM_DISPLAY_HDCP_DISABLE        (1 << 25)
> > -- 
> > 2.34.1
> > 

Re: [Intel-gfx] [PATCH v3 7/8] drm/i915/mtl: Add support for PM DEMAND

[Gustavo Sousa]

Quoting Govindapillai, Vinod (2023-05-11 20:24:55)
>Hello
>
>Thanks for the comments. Pls see some inline replies..
>
>On Thu, 2023-04-27 at 17:24 -0300, Gustavo Sousa wrote:
>> Quoting Vinod Govindapillai (2023-04-27 12:00:15)
>> > From: Mika Kahola <mika.kahola@intel.com>
>> > 
>> > Display14 introduces a new way to instruct the PUnit with
>> > power and bandwidth requirements of DE. Add the functionality
>> > to program the registers and handle waits using interrupts.
>> > The current wait time for timeouts is programmed for 10 msecs to
>> > factor in the worst case scenarios. Changes made to use REG_BIT
>> > for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>> > 
>> > Wa_14016740474 is added which applies to Xe_LPD+ display
>> > 
>> > v2: checkpatch warning fixes, simplify program pmdemand part
>> > 
>> > v3: update to dbufs and pipes values to pmdemand register(stan)
>> >    Removed the macro usage in update_pmdemand_values()
>> > 
>> > Bspec: 66451, 64636, 64602, 64603
>> > Cc: Matt Atwood <matthew.s.atwood@intel.com>
>> > Cc: Matt Roper <matthew.d.roper@intel.com>
>> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/Makefile                 |   3 +-
>> > drivers/gpu/drm/i915/display/intel_display.c  |   7 +
>> > .../gpu/drm/i915/display/intel_display_core.h |   6 +
>> > .../drm/i915/display/intel_display_driver.c   |   7 +
>> > .../drm/i915/display/intel_display_power.c    |   8 +
>> > drivers/gpu/drm/i915/display/intel_pmdemand.c | 455 ++++++++++++++++++
>> > drivers/gpu/drm/i915/display/intel_pmdemand.h |  24 +
>> > drivers/gpu/drm/i915/i915_irq.c               |  21 +-
>> > drivers/gpu/drm/i915/i915_reg.h               |  36 +-
>> > 9 files changed, 562 insertions(+), 5 deletions(-)
>> > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
>> > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>> > 
>> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> > index 9af76e376ca9..eb899fa86e51 100644
>> > --- a/drivers/gpu/drm/i915/Makefile
>> > +++ b/drivers/gpu/drm/i915/Makefile
>> > @@ -281,7 +281,8 @@ i915-y += \
>> >        display/i9xx_wm.o \
>> >        display/skl_scaler.o \
>> >        display/skl_universal_plane.o \
>> > -  display/skl_watermark.o
>> > +  display/skl_watermark.o \
>> > +  display/intel_pmdemand.o
>> > i915-$(CONFIG_ACPI) += \
>> >        display/intel_acpi.o \
>> >        display/intel_opregion.o
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > b/drivers/gpu/drm/i915/display/intel_display.c
>> > index bf391a6cd8d6..f98e235fadc6 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -99,6 +99,7 @@
>> > #include "intel_pcode.h"
>> > #include "intel_pipe_crc.h"
>> > #include "intel_plane_initial.h"
>> > +#include "intel_pmdemand.h"
>> > #include "intel_pps.h"
>> > #include "intel_psr.h"
>> > #include "intel_sdvo.h"
>> > @@ -6306,6 +6307,10 @@ int intel_atomic_check(struct drm_device *dev,
>> >                        return ret;
>> >        }
>> > 
>> > +  ret = intel_pmdemand_atomic_check(state);
>> > +  if (ret)
>> > +          goto fail;
>> > +
>> >        ret = intel_atomic_check_crtcs(state);
>> >        if (ret)
>> >                goto fail;
>> > @@ -6960,6 +6965,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>> >        }
>> > 
>> >        intel_sagv_pre_plane_update(state);
>> > +  intel_pmdemand_pre_plane_update(state);
>> > 
>> >        /* Complete the events for pipes that have now been disabled */
>> >        for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> > @@ -7070,6 +7076,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>> >                intel_verify_planes(state);
>> > 
>> >        intel_sagv_post_plane_update(state);
>> > +  intel_pmdemand_post_plane_update(state);
>> > 
>> >        drm_atomic_helper_commit_hw_done(&state->base);
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> > b/drivers/gpu/drm/i915/display/intel_display_core.h
>> > index 9f66d734edf6..9471a052aa57 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> > @@ -345,6 +345,12 @@ struct intel_display {
>> >                struct intel_global_obj obj;
>> >        } dbuf;
>> > 
>> > +  struct {
>> > +          wait_queue_head_t waitqueue;
>> > +          struct mutex lock;
>> > +          struct intel_global_obj obj;
>> > +  } pmdemand;
>> > +
>> >        struct {
>> >                /*
>> >                 * dkl.phy_lock protects against concurrent access of the
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > index 60ce10fc7205..79853d8c3240 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > @@ -47,6 +47,7 @@
>> > #include "intel_opregion.h"
>> > #include "intel_overlay.h"
>> > #include "intel_plane_initial.h"
>> > +#include "intel_pmdemand.h"
>> > #include "intel_pps.h"
>> > #include "intel_quirks.h"
>> > #include "intel_vga.h"
>> > @@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
>> >        if (ret < 0)
>> >                goto cleanup_vga;
>> > 
>> > +  intel_pmdemand_init(i915);
>> > +
>> >        intel_power_domains_init_hw(i915, false);
>> > 
>> >        if (!HAS_DISPLAY(i915))
>> > @@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
>> >        if (ret)
>> >                goto cleanup_vga_client_pw_domain_dmc;
>> > 
>> > +  ret = intel_pmdemand_state_init(i915);
>> > +  if (ret)
>> > +          goto cleanup_vga_client_pw_domain_dmc;
>> > +
>> >        init_llist_head(&i915->display.atomic_helper.free_list);
>> >        INIT_WORK(&i915->display.atomic_helper.free_work,
>> >                  intel_atomic_helper_free_state_worker);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> > b/drivers/gpu/drm/i915/display/intel_display_power.c
>> > index 5150069f3f82..f5c5a486efbc 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> > @@ -20,6 +20,7 @@
>> > #include "intel_mchbar_regs.h"
>> > #include "intel_pch_refclk.h"
>> > #include "intel_pcode.h"
>> > +#include "intel_pmdemand.h"
>> > #include "intel_pps_regs.h"
>> > #include "intel_snps_phy.h"
>> > #include "skl_watermark.h"
>> > @@ -1085,6 +1086,10 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
>> >        dev_priv->display.dbuf.enabled_slices =
>> >                intel_enabled_dbuf_slices_mask(dev_priv);
>> > 
>> > +  if (DISPLAY_VER(dev_priv) >= 14)
>> > +          intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
>> > +                                      dev_priv->display.dbuf.enabled_slices);
>> > +
>> >        /*
>> >         * Just power up at least 1 slice, we will
>> >         * figure out later which slices we have and what we need.
>> > @@ -1096,6 +1101,9 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
>> > static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
>> > {
>> >        gen9_dbuf_slices_update(dev_priv, 0);
>> > +
>> > +  if (DISPLAY_VER(dev_priv) >= 14)
>> > +          intel_program_dbuf_pmdemand(dev_priv, 0);
>> > }
>> > 
>> > static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
>> > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> > b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> > new file mode 100644
>> > index 000000000000..df6429e7059d
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> > @@ -0,0 +1,455 @@
>> > +// SPDX-License-Identifier: MIT
>> > +/*
>> > + * Copyright © 2024 Intel Corporation
>> > + */
>> > +
>> > +#include <linux/bitops.h>
>> > +
>> > +#include "i915_drv.h"
>> > +#include "i915_reg.h"
>> > +#include "intel_bw.h"
>> > +#include "intel_cdclk.h"
>> > +#include "intel_cx0_phy.h"
>> > +#include "intel_de.h"
>> > +#include "intel_display.h"
>> > +#include "intel_display_trace.h"
>> > +#include "intel_pmdemand.h"
>> > +#include "skl_watermark.h"
>> > +
>> > +struct intel_pmdemand_state {
>> > +  struct intel_global_state base;
>> > +
>> > +  u16 qclk_gv_bw;
>> > +  u8 voltage_index;
>> > +  u8 qclk_gv_index;
>> > +  u8 active_pipes;
>> > +  u8 dbufs;
>> > +  u8 active_phys_plls_mask;
>> 
>> Is u8 enough for the mask? The enum phy shows 9 possible PHY_* members.
>> Also, I think having BUILD_BUG_ON() somewhere in this file to make sure
>> we have enough bits would be nice.
>Thanks. updated.
>> 
>> > +  u16 cdclk_freq_mhz;
>> > +  u16 ddiclk_freq_mhz;
>> > +  u8 scalers;
>> > +};
>> > +
>> > +#define to_intel_pmdemand_state(x) container_of((x), struct intel_pmdemand_state, base)
>> > +
>> > +static struct intel_global_state *
>> > +intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
>> > +{
>> > +  struct intel_pmdemand_state *pmdmnd_state;
>> > +
>> > +  pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state), GFP_KERNEL);
>> > +  if (!pmdmnd_state)
>> > +          return NULL;
>> > +
>> > +  return &pmdmnd_state->base;
>> > +}
>> > +
>> > +static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
>> > +                                   struct intel_global_state *state)
>> > +{
>> > +  kfree(state);
>> > +}
>> > +
>> > +static const struct intel_global_state_funcs intel_pmdemand_funcs = {
>> > +  .atomic_duplicate_state = intel_pmdemand_duplicate_state,
>> > +  .atomic_destroy_state = intel_pmdemand_destroy_state,
>> > +};
>> > +
>> > +static struct intel_pmdemand_state *
>> > +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
>> > +{
>> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
>> > +  struct intel_global_state *pmdemand_state;
>> > +
>> > +  pmdemand_state =
>> > +          intel_atomic_get_global_obj_state(state,
>> > +                                            &i915->display.pmdemand.obj);
>> > +  if (IS_ERR(pmdemand_state))
>> > +          return ERR_CAST(pmdemand_state);
>> > +
>> > +  return to_intel_pmdemand_state(pmdemand_state);
>> > +}
>> > +
>> > +static struct intel_pmdemand_state *
>> > +intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
>> > +{
>> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
>> > +  struct intel_global_state *pmdemand_state;
>> > +
>> > +  pmdemand_state = intel_atomic_get_old_global_obj_state(state, &i915->display.pmdemand.obj);
>> 
>> Wouldn't it be safer if we returned early here when pmdemand_state is
>> NULL?
>> 
>> I think to_intel_pmdemand_state(NULL) pmdemand_state just happens to
>> work (i.e. still returns NULL) because the "base" member is at the
>> beginning of the struct. However, we shouldn't rely on that IMO.
>
>Well. It is a valid point. But the base pointer is the first member for exaclty the reason you
>pointed out. So  to prevent someone from accidentally move that "base" from that position, I added a
>BUILD_BUG_ON() check. There are few other state objects which lack such a check. I will address that
>as a separate patch.

Hm... Not sure I am totally convinced here. If we are enforcing (with
BUILD_BUG_ON()) the base to be the first member, then what is the point in using
container_of() instead of just a simple cast?

I believe one of the points of using container_of() is that it alows we *not* to
enforce a strict layout of the containing struct for things to work.

Now, if for some (yet unkown) reason we need to move the "base" member in the
future, it would be difficult to find all places where the pointer could be NULL
but we relied one the assumption that "base" would always be at offset 0.

>
>> 
>> > +
>> > +  return to_intel_pmdemand_state(pmdemand_state);
>> > +}
>> > +
>> > +static struct intel_pmdemand_state *
>> > +intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
>> > +{
>> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
>> > +  struct intel_global_state *pmdemand_state;
>> > +
>> > +  pmdemand_state = intel_atomic_get_new_global_obj_state(state, &i915->display.pmdemand.obj);
>> 
>> Just as with intel_atomic_get_old_pmdemand_state(), shouldn't we return
>> early if pmdemand_state is NULL here?
>> 
>> > +
>> > +  return to_intel_pmdemand_state(pmdemand_state);
>> > +}
>> > +
>> > +int intel_pmdemand_state_init(struct drm_i915_private *i915)
>> > +{
>> > +  struct intel_pmdemand_state *pmdemand_state;
>> > +
>> > +  pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
>> > +  if (!pmdemand_state)
>> > +          return -ENOMEM;
>> > +
>> > +  intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
>> > +                               &pmdemand_state->base,
>> > +                               &intel_pmdemand_funcs);
>> > +
>> > +
>> > +  if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>> > +          /* Wa_14016740474 */
>> > +          intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
>> > +
>> > +  return 0;
>> > +}
>> > +
>> > +void intel_pmdemand_init(struct drm_i915_private *i915)
>> > +{
>> > +  mutex_init(&i915->display.pmdemand.lock);
>> > +  init_waitqueue_head(&i915->display.pmdemand.waitqueue);
>> > +}
>> 
>> The functions intel_pmdemand_state_init() and intel_pmdemand_init() are
>> both called from the same place. Furthermore,
>> intel_pmdemand_state_init() isn't only initializing the state, as the
>> Wa_14016740474 workaround is programmed there. Could we have only the
>> function intel_pmdemand_init() and incorporate what
>> intel_pmdemand_state_init() does in it?
>
>I tried that earlier and wasn't possible. Because the intel_power_domains_init_hw() will call the
>pmdemand debuf config. And I can't recall the other issue. But I will confirm this again and update
>as I am not able to try this locally.

Well, regarding intel_power_domains_init_hw(), wouldn't the solution be to call
the single init function for PM Demand before that one is called? Am I missing
something?

>> 
>> > +
>> > +static bool pmdemand_needs_update(struct intel_atomic_state *state)
>> > +{
>> > +  bool changed = false;
>> > +  struct intel_crtc *crtc;
>> > +  int i;
>> > +  const struct intel_bw_state *new_bw_state, *old_bw_state;
>> > +  const struct intel_cdclk_state *new_cdclk_state;
>> > +  const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
>> > +  const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
>> > +
>> > +  for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>> > +                                      new_crtc_state, i) {
>> > +          new_bw_state = intel_atomic_get_new_bw_state(state);
>> > +          old_bw_state = intel_atomic_get_old_bw_state(state);
>> > +
>> > +          new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
>> > +          old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
>> > +
>> > +          new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
>> > +
>> > +          if ((new_bw_state && new_bw_state->qgv_point_peakbw !=
>> > +               old_bw_state->qgv_point_peakbw) ||
>> > +              (new_dbuf_state && new_dbuf_state->active_pipes !=
>> > +               old_dbuf_state->active_pipes) || new_cdclk_state)
>> > +                  changed = true;
>> > +
>> > +          /*
>> > +           * break needs to be removed, if some crtc_state dependent
>> > +           * parameters are added here
>> > +           */
>> > +          break;
>> > +  }
>> > +
>> > +  return changed;
>> > +}
>> > +
>> > +int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
>> > +{
>> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
>> > +  int port_clock = 0;
>> > +  struct intel_crtc *crtc;
>> > +  struct intel_encoder *encoder;
>> > +  const struct intel_bw_state *new_bw_state;
>> > +  const struct intel_cdclk_state *new_cdclk_state;
>> > +  const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
>> > +  const struct intel_dbuf_state *new_dbuf_state;
>> > +  struct intel_pmdemand_state *new_pmdemand_state;
>> > +  enum phy phy;
>> > +  int i, ret;
>> > +
>> > +  if (DISPLAY_VER(i915) < 14)
>> > +          return 0;
>> > +
>> > +  if (!pmdemand_needs_update(state))
>> > +          return 0;
>> > +
>> > +  new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
>> > +  if (IS_ERR(new_pmdemand_state))
>> > +          return PTR_ERR(new_pmdemand_state);
>> > +
>> > +  ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
>> > +  if (ret)
>> > +          return ret;
>> > +
>> > +  /* Punit figures out the voltage index based on bandwidth*/
>> > +  new_bw_state = intel_atomic_get_bw_state(state);
>> > +  if (IS_ERR(new_bw_state))
>> > +          return PTR_ERR(new_bw_state);
>> > +
>> > +  /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
>> > +  new_pmdemand_state->qclk_gv_index = 0;
>> > +  new_pmdemand_state->qclk_gv_bw =
>> > +          min_t(u16, new_bw_state->qgv_point_peakbw, 0xffff);
>> > +
>> > +  new_dbuf_state = intel_atomic_get_dbuf_state(state);
>> > +  if (IS_ERR(new_dbuf_state))
>> > +          return PTR_ERR(new_dbuf_state);
>> > +
>> > +  i = hweight8(new_dbuf_state->active_pipes);
>> > +  new_pmdemand_state->active_pipes = min(i, 3);
>> > +
>> > +  new_cdclk_state = intel_atomic_get_cdclk_state(state);
>> > +  if (IS_ERR(new_cdclk_state))
>> > +          return PTR_ERR(new_cdclk_state);
>> > +
>> > +  new_pmdemand_state->voltage_index =
>> > +          new_cdclk_state->logical.voltage_level;
>> > +  /* KHz to MHz */
>> > +  new_pmdemand_state->cdclk_freq_mhz =
>> > +          DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
>> > +
>> > +  new_pmdemand_state->active_phys_plls_mask = 0;
>> > +
>> > +  for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>> > +                                      new_crtc_state, i) {
>> > +          if (!new_crtc_state->hw.active)
>> > +                  continue;
>> > +
>> > +          encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
>> > +          if (!encoder)
>> > +                  continue;
>> > +
>> > +          phy = intel_port_to_phy(i915, encoder->port);
>> > +
>> > +          if (intel_is_c10phy(i915, phy))
>> > +                  new_pmdemand_state->active_phys_plls_mask |= BIT(phy);
>> > +
>> > +          port_clock = max(port_clock, new_crtc_state->port_clock);
>> > +  }
>> 
>> As previously noted in https://patchwork.freedesktop.org/patch/530495 ,
>> I'm under the impression that this loop would not let us account for al
>> active crtcs, only those currently being touched by this atomic
>> transaction. Am I wrong to assume that
>> for_each_oldnew_intel_crtc_in_state() would only iterate over crtcs
>> touched by the atomic update?
>
>I checked the intel_bw_check_data_rate() which should be doing something similar to find out about
>the datarate from eachi pipe and figure out the total data rate. So I thought this should be
>sufficient. 

I took a quick look at intel_bw_check_data_rate()'s implementation and I think
it works there because struct intel_bw_state has arrays containing values for
each pipe, meaning that those not included in the atomic update would already
contain the current values from previous transactions.

For the number of active phy PLLs, I believe we can handle it similarly to how
it is done by intel_calc_active_pipes().

Now, for the maximum port_clock, maybe we could use the array approach like done
with intel_bw_check_data_rate(). So we can always have all port_clock values
here.

>
>> 
>> > +
>> > +  /* To MHz */
>> > +  new_pmdemand_state->ddiclk_freq_mhz = DIV_ROUND_UP(port_clock, 1000);
>> > +
>> > +  /*
>> > +   * Setting scalers to max as it can not be calculated during flips and
>> > +   * fastsets without taking global states locks.
>> > +   */
>> > +  new_pmdemand_state->scalers = 7;
>> > +
>> > +  ret = intel_atomic_serialize_global_state(&new_pmdemand_state->base);
>> > +  if (ret)
>> > +          return ret;
>> > +
>> > +  return 0;
>> > +}
>> > +
>> > +static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
>> > +{
>> > +  return !((intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
>> > +            XELPDP_PMDEMAND_REQ_ENABLE) ||
>> > +          (intel_de_read(i915, GEN12_DCPR_STATUS_1) &
>> > +           XELPDP_PMDEMAND_INFLIGHT_STATUS));
>> > +}
>> > +
>> > +static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
>> > +{
>> > +  return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
>> > +           XELPDP_PMDEMAND_REQ_ENABLE);
>> > +}
>> > +
>> > +static int intel_pmdemand_wait(struct drm_i915_private *i915)
>> > +{
>> > +  DEFINE_WAIT(wait);
>> > +  int ret;
>> > +  const unsigned int timeout_ms = 10;
>> > +
>> > +  ret = wait_event_timeout(i915->display.pmdemand.waitqueue,
>> > +                           intel_pmdemand_req_complete(i915),
>> > +                           msecs_to_jiffies_timeout(timeout_ms));
>> > +  if (ret == 0)
>> > +          drm_err(&i915->drm,
>> > +                  "timed out waiting for Punit PM Demand Response\n");
>> > +
>> > +  return ret;
>> > +}
>> > +
>> > +/* Required to be programmed during Display Init Sequences. */
>> > +void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
>> > +                           u8 dbuf_slices)
>> > +{
>> > +  u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
>> > +
>> > +  mutex_lock(&i915->display.pmdemand.lock);
>> > +  if (drm_WARN_ON(&i915->drm,
>> > +                  !intel_pmdemand_check_prev_transaction(i915)))
>> > +          goto unlock;
>> > +
>> > +  intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
>> > +               XELPDP_PMDEMAND_DBUFS_MASK, XELPDP_PMDEMAND_DBUFS(dbufs));
>> > +  intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
>> > +               XELPDP_PMDEMAND_REQ_ENABLE);
>> > +
>> > +  intel_pmdemand_wait(i915);
>> > +
>> > +unlock:
>> > +  mutex_unlock(&i915->display.pmdemand.lock);
>> > +}
>> > +
>> > +static void update_pmdemand_values(const struct intel_pmdemand_state *new,
>> > +                             const struct intel_pmdemand_state *old,
>> > +                             u32 *reg1, u32 *reg2)
>> > +{
>> > +  u32 plls, tmp;
>> > +
>> > +  /*
>> > +   * The pmdemand parameter updates happens in two steps. Pre plane and
>> > +   * post plane updates. During the pre plane, as DE might still be
>> > +   * handling with some old operations, to avoid unwanted performance
>> > +   * issues, program the pmdemand parameters with higher of old and new
>> > +   * values. And then after once settled, use the new parameter values
>> > +   * as part of the post plane update.
>> > +   */
>> > +
>> > +  /* Set 1*/
>> > +  *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_BW_MASK;
>> > +  tmp = old ? max(old->qclk_gv_bw, new->qclk_gv_bw) : new->qclk_gv_bw;
>> > +  *reg1 |= XELPDP_PMDEMAND_QCLK_GV_BW(tmp);
>> > +
>> > +  *reg1 &= ~XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK;
>> > +  tmp = old ? max(old->voltage_index, new->voltage_index) :
>> > +              new->voltage_index;
>> > +  *reg1 |= XELPDP_PMDEMAND_VOLTAGE_INDEX(tmp);
>> > +
>> > +  *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK;
>> > +  tmp = old ? max(old->qclk_gv_index, new->qclk_gv_index) :
>> > +              new->qclk_gv_index;
>> > +  *reg1 |= XELPDP_PMDEMAND_QCLK_GV_INDEX(tmp);
>> > +
>> > +  *reg1 &= ~XELPDP_PMDEMAND_PIPES_MASK;
>> > +  tmp = old ? max(old->active_pipes, new->active_pipes) :
>> > +              new->active_pipes;
>> > +  *reg1 |= XELPDP_PMDEMAND_PIPES(tmp);
>> > +
>> > +  *reg1 &= ~XELPDP_PMDEMAND_PHYS_MASK;
>> > +  plls = hweight32(new->active_phys_plls_mask);
>> > +  if (old)
>> > +          plls = max(plls, hweight32(old->active_phys_plls_mask));
>> > +  *reg1 |= XELPDP_PMDEMAND_PHYS(plls);
>> 
>> If plls > 7, we would be potentially programming this wrong (e.g. for
>> plls=8, we would setting the field to 0).
>
>Thanks for pointing that out. Fixed.
>
>> 
>> > +
>> > +  /* Set 2*/
>> > +  *reg2 &= ~XELPDP_PMDEMAND_CDCLK_FREQ_MASK;
>> > +  tmp = old ? max(old->cdclk_freq_mhz, new->cdclk_freq_mhz) :
>> > +              new->cdclk_freq_mhz;
>> > +  *reg2 |= XELPDP_PMDEMAND_CDCLK_FREQ(tmp);
>> > +
>> > +  *reg2 &= ~XELPDP_PMDEMAND_DDICLK_FREQ_MASK;
>> > +  tmp = old ? max(old->ddiclk_freq_mhz, new->ddiclk_freq_mhz) :
>> > +              new->ddiclk_freq_mhz;
>> > +  *reg2 |= XELPDP_PMDEMAND_DDICLK_FREQ(tmp);
>> > +
>> > +  /* Hard code scalers to 7*/
>> 
>> I think this comment can be dropped: the hardcoding happens in
>> intel_pmdemand_atomic_check().
>
>Done
>> 
>> > +  *reg2 &= ~XELPDP_PMDEMAND_SCALERS_MASK;
>> > +  tmp = old ? max(old->scalers, new->scalers) : new->scalers;
>> > +  *reg2 |= XELPDP_PMDEMAND_SCALERS(tmp);
>> > +
>> > +  /*
>> > +   * Active_PLLs starts with 1 because of CDCLK PLL.
>> > +   * TODO: Missing to account genlock filter when it gets used.
>> > +   */
>> > +  *reg2 &= ~XELPDP_PMDEMAND_PLLS_MASK;
>> 
>> I think we are missing the ternary operator here to select the maximum
>> value for the pre-plane case.
>As pet the above comments, it is just the plls from step earlier + 1

Ah, got it. Thanks.

>
>> 
>> > +  *reg2 |= XELPDP_PMDEMAND_PLLS(plls + 1);
>> > +}
>> > +
>> > +static void intel_program_pmdemand(struct drm_i915_private *i915,
>> > +                             const struct intel_pmdemand_state *new,
>> > +                             const struct intel_pmdemand_state *old)
>> > +{
>> > +  bool changed = false;
>> > +  u32 reg1, mod_reg1;
>> > +  u32 reg2, mod_reg2;
>> > +
>> > +  mutex_lock(&i915->display.pmdemand.lock);
>> > +  if (drm_WARN_ON(&i915->drm,
>> > +                  !intel_pmdemand_check_prev_transaction(i915)))
>> > +          goto unlock;
>> 
>> According to the spec, we should wait and timeout after 10ms here.
>> 
>> > +
>> > +  reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
>> > +  mod_reg1 = reg1;
>> > +
>> > +  reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
>> > +  mod_reg2 = reg2;
>> > +
>> > +  update_pmdemand_values(new, old, &mod_reg1, &mod_reg2);
>> > +
>> > +  if (reg1 != mod_reg1) {
>> > +          intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
>> > +                         mod_reg1);
>> > +          changed = true;
>> > +  }
>> > +
>> > +  if (reg2 != mod_reg2) {
>> > +          intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
>> > +                         mod_reg2);
>> > +          changed = true;
>> > +  }
>> > +
>> > +  /* Initiate pm demand request only if register values are changed */
>> > +  if (changed) {
>> 
>> Nitpick: we could have
>> 
>>     if (!changed)
>>             goto unlock;
>> 
>> and dedent the block below.
>
>Done.
>> 
>> > +          drm_dbg_kms(&i915->drm,
>> > +                      "initate pmdemand request values: (0x%x 0x%x)\n",
>> > +                      mod_reg1, mod_reg2);
>> > +
>> > +          intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
>> > +                       XELPDP_PMDEMAND_REQ_ENABLE);
>> > +
>> > +          intel_pmdemand_wait(i915);
>> > +  }
>> > +
>> > +unlock:
>> > +  mutex_unlock(&i915->display.pmdemand.lock);
>> > +}
>> > +
>> > +static bool
>> > +intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
>> > +                       const struct intel_pmdemand_state *old)
>> > +{
>> > +  return memcmp(&new->qclk_gv_bw, &old->qclk_gv_bw,
>> > +                sizeof(*new) - offsetof(typeof(*new), qclk_gv_bw)) != 0;
>> > +}
>> > +
>> > +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
>> > +{
>> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
>> > +  const struct intel_pmdemand_state *new_pmdmnd_state =
>> > +          intel_atomic_get_new_pmdemand_state(state);
>> > +  const struct intel_pmdemand_state *old_pmdmnd_state =
>> > +          intel_atomic_get_old_pmdemand_state(state);
>> > +
>> > +  if (DISPLAY_VER(i915) < 14)
>> > +          return;
>> > +
>> > +  if (!new_pmdmnd_state ||
>> > +      !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
>> > +          return;
>> > +
>> > +  intel_program_pmdemand(i915, new_pmdmnd_state, old_pmdmnd_state);
>> > +}
>> > +
>> > +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
>> > +{
>> > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
>> > +  const struct intel_pmdemand_state *new_pmdmnd_state =
>> > +          intel_atomic_get_new_pmdemand_state(state);
>> > +  const struct intel_pmdemand_state *old_pmdmnd_state =
>> > +          intel_atomic_get_old_pmdemand_state(state);
>> > +
>> > +  if (DISPLAY_VER(i915) < 14)
>> > +          return;
>> > +
>> > +  if (!new_pmdmnd_state ||
>> > +      !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
>> > +          return;
>> > +
>> > +  intel_program_pmdemand(i915, new_pmdmnd_state, NULL);
>> > +}
>> > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h
>> > b/drivers/gpu/drm/i915/display/intel_pmdemand.h
>> > new file mode 100644
>> > index 000000000000..0114f4e0225a
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
>> > @@ -0,0 +1,24 @@
>> > +/* SPDX-License-Identifier: MIT */
>> > +/*
>> > + * Copyright © 2023 Intel Corporation
>> > + */
>> > +
>> > +#ifndef __INTEL_PMDEMAND_H__
>> > +#define __INTEL_PMDEMAND_H__
>> > +
>> > +#include <linux/types.h>
>> > +
>> > +struct drm_i915_private;
>> > +struct intel_atomic_state;
>> > +struct intel_crtc_state;
>> > +struct intel_plane_state;
>> > +
>> > +void intel_pmdemand_init(struct drm_i915_private *i915);
>> > +int intel_pmdemand_state_init(struct drm_i915_private *i915);
>> > +void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
>> > +                           u8 dbuf_slices);
>> > +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
>> > +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
>> > +int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
>> > +
>> > +#endif /* __INTEL_PMDEMAND_H__ */
>> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> > index 2b94b8ca8ec9..907fa3aee179 100644
>> > --- a/drivers/gpu/drm/i915/i915_irq.c
>> > +++ b/drivers/gpu/drm/i915/i915_irq.c
>> > @@ -41,6 +41,7 @@
>> > #include "display/intel_fifo_underrun.h"
>> > #include "display/intel_hotplug.h"
>> > #include "display/intel_lpe_audio.h"
>> > +#include "display/intel_pmdemand.h"
>> > #include "display/intel_psr.h"
>> > #include "display/intel_psr_regs.h"
>> > 
>> > @@ -1986,12 +1987,25 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
>> >                return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
>> > }
>> > 
>> > +static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
>> > +{
>> > +  wake_up_all(&dev_priv->display.pmdemand.waitqueue);
>> > +}
>> > +
>> > static void
>> > gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>> > {
>> >        bool found = false;
>> > 
>> > -  if (iir & GEN8_DE_MISC_GSE) {
>> > +  if (DISPLAY_VER(dev_priv) >= 14 &&
>> > +      (iir & (XELPDP_PMDEMAND_RSP | XELPDP_PMDEMAND_RSPTOUT_ERR))) {
>> > +          if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
>> 
>> I think we should have the (iir & (XELPDP_PMDEMAND_RSP |
>> XELPDP_PMDEMAND_RSPTOUT_ERR)) part as nested if statement here.
>> Otherwise, when the interrupt did not happen, we could endup checking
>> for the GEN8_DE_MISC_GSE even when DISPLAY_VER(dev_priv) >= 14.
>> 
>> Even though we know that iir & GEN8_DE_MISC_GSE would be false in this
>> situation (because both XELPDP_PMDEMAND_RSPTOUT_ERR and GEN8_DE_MISC_GSE
>> map to the same bit), I think having that one checked only for previous
>> display engines would sound more correct semantically speaking.
>
>Thanks. updated.
>
>> 
>> > +                  drm_dbg(&dev_priv->drm,
>> > +                          "Error waiting for Punit PM Demand Response\n");
>> > +
>> > +          intel_pmdemand_irq_handler(dev_priv);
>> > +          found = true;
>> > +  } else if (iir & GEN8_DE_MISC_GSE) {
>> >                intel_opregion_asle_intr(dev_priv);
>> >                found = true;
>> >        }
>> > @@ -3742,7 +3756,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>> >        if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>> >                de_port_masked |= BXT_DE_PORT_GMBUS;
>> > 
>> > -  if (DISPLAY_VER(dev_priv) >= 11) {
>> > +  if (DISPLAY_VER(dev_priv) >= 14)
>> > +          de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
>> > +                            XELPDP_PMDEMAND_RSP;
>> > +  else if (DISPLAY_VER(dev_priv) >= 11) {
>> >                enum port port;
>> > 
>> >                if (intel_bios_is_dsi_present(dev_priv, &port))
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index dde6e91055bd..60c007aea1ce 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -4426,8 +4426,10 @@
>> > #define GEN8_DE_MISC_IMR _MMIO(0x44464)
>> > #define GEN8_DE_MISC_IIR _MMIO(0x44468)
>> > #define GEN8_DE_MISC_IER _MMIO(0x4446c)
>> > -#define  GEN8_DE_MISC_GSE         (1 << 27)
>> > -#define  GEN8_DE_EDP_PSR          (1 << 19)
>> > +#define  XELPDP_PMDEMAND_RSPTOUT_ERR      REG_BIT(27)
>> > +#define  GEN8_DE_MISC_GSE         REG_BIT(27)
>> > +#define  GEN8_DE_EDP_PSR          REG_BIT(19)
>> > +#define  XELPDP_PMDEMAND_RSP              REG_BIT(3)
>> > 
>> > #define GEN8_PCU_ISR _MMIO(0x444e0)
>> > #define GEN8_PCU_IMR _MMIO(0x444e4)
>> > @@ -4512,6 +4514,33 @@
>> > #define  XELPDP_DP_ALT_HPD_LONG_DETECT         REG_BIT(1)
>> > #define  XELPDP_DP_ALT_HPD_SHORT_DETECT                REG_BIT(0)
>> > 
>> > +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)           _MMIO(0x45230 + 4 * (dword))
>> > +#define  XELPDP_PMDEMAND_QCLK_GV_BW_MASK          REG_GENMASK(31, 16)
>> > +#define  XELPDP_PMDEMAND_QCLK_GV_BW(x)                   
>> > REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
>> > +#define  XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK               REG_GENMASK(14, 12)
>> > +#define  XELPDP_PMDEMAND_VOLTAGE_INDEX(x)        
>> > REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
>> > +#define  XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK               REG_GENMASK(11, 8)
>> > +#define  XELPDP_PMDEMAND_QCLK_GV_INDEX(x)        
>> > REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
>> > +#define  XELPDP_PMDEMAND_PIPES_MASK                       REG_GENMASK(7, 6)
>> > +#define  XELPDP_PMDEMAND_PIPES(x)                 REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
>> > +#define  XELPDP_PMDEMAND_DBUFS_MASK                       REG_GENMASK(5, 4)
>> > +#define  XELPDP_PMDEMAND_DBUFS(x)                 REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
>> > +#define  XELPDP_PMDEMAND_PHYS_MASK                        REG_GENMASK(2, 0)
>> > +#define  XELPDP_PMDEMAND_PHYS(x)                  REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
>> > +
>> > +#define  XELPDP_PMDEMAND_REQ_ENABLE                       REG_BIT(31)
>> > +#define  XELPDP_PMDEMAND_CDCLK_FREQ_MASK          REG_GENMASK(30, 20)
>> > +#define  XELPDP_PMDEMAND_CDCLK_FREQ(x)                   
>> > REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
>> > +#define  XELPDP_PMDEMAND_DDICLK_FREQ_MASK         REG_GENMASK(18, 8)
>> > +#define  XELPDP_PMDEMAND_DDICLK_FREQ(x)                  
>> > REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
>> > +#define  XELPDP_PMDEMAND_SCALERS_MASK                     REG_GENMASK(6, 4)
>> > +#define  XELPDP_PMDEMAND_SCALERS(x)                      
>> > REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
>> > +#define  XELPDP_PMDEMAND_PLLS_MASK                        REG_GENMASK(2, 0)
>> > +#define  XELPDP_PMDEMAND_PLLS(x)                  REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
>> > +
>> > +#define GEN12_DCPR_STATUS_1                               _MMIO(0x46440)
>> > +#define  XELPDP_PMDEMAND_INFLIGHT_STATUS          REG_BIT(26)
>> > +
>> > #define ILK_DISPLAY_CHICKEN2   _MMIO(0x42004)
>> > /* Required on all Ironlake and Sandybridge according to the B-Spec. */
>> > #define   ILK_ELPIN_409_SELECT REG_BIT(25)
>> > @@ -4671,6 +4700,9 @@
>> > #define   DCPR_SEND_RESP_IMM                   REG_BIT(25)
>> > #define   DCPR_CLEAR_MEMSTAT_DIS               REG_BIT(24)
>> > 
>> > +#define XELPD_CHICKEN_DCPR_3                      _MMIO(0x46438)
>> > +#define   DMD_RSP_TIMEOUT_DISABLE         REG_BIT(19)
>> > +
>> > #define SKL_DFSM                       _MMIO(0x51000)
>> > #define   SKL_DFSM_DISPLAY_PM_DISABLE  (1 << 27)
>> > #define   SKL_DFSM_DISPLAY_HDCP_DISABLE        (1 << 25)
>> > -- 
>> > 2.34.1
>> > 
>

Re: [Intel-gfx] [PATCH v3 7/8] drm/i915/mtl: Add support for PM DEMAND

[Jani Nikula]

On Thu, 27 Apr 2023, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> From: Mika Kahola <mika.kahola@intel.com>
>
> Display14 introduces a new way to instruct the PUnit with
> power and bandwidth requirements of DE. Add the functionality
> to program the registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to
> factor in the worst case scenarios. Changes made to use REG_BIT
> for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
> Wa_14016740474 is added which applies to Xe_LPD+ display
>
> v2: checkpatch warning fixes, simplify program pmdemand part
>
> v3: update to dbufs and pipes values to pmdemand register(stan)
>     Removed the macro usage in update_pmdemand_values()
>
> Bspec: 66451, 64636, 64602, 64603
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                 |   3 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |   7 +
>  .../gpu/drm/i915/display/intel_display_core.h |   6 +
>  .../drm/i915/display/intel_display_driver.c   |   7 +
>  .../drm/i915/display/intel_display_power.c    |   8 +
>  drivers/gpu/drm/i915/display/intel_pmdemand.c | 455 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_pmdemand.h |  24 +
>  drivers/gpu/drm/i915/i915_irq.c               |  21 +-
>  drivers/gpu/drm/i915/i915_reg.h               |  36 +-
>  9 files changed, 562 insertions(+), 5 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 9af76e376ca9..eb899fa86e51 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -281,7 +281,8 @@ i915-y += \
>  	display/i9xx_wm.o \
>  	display/skl_scaler.o \
>  	display/skl_universal_plane.o \
> -	display/skl_watermark.o
> +	display/skl_watermark.o \
> +	display/intel_pmdemand.o
>  i915-$(CONFIG_ACPI) += \
>  	display/intel_acpi.o \
>  	display/intel_opregion.o
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bf391a6cd8d6..f98e235fadc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -99,6 +99,7 @@
>  #include "intel_pcode.h"
>  #include "intel_pipe_crc.h"
>  #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
>  #include "intel_pps.h"
>  #include "intel_psr.h"
>  #include "intel_sdvo.h"
> @@ -6306,6 +6307,10 @@ int intel_atomic_check(struct drm_device *dev,
>  			return ret;
>  	}
>  
> +	ret = intel_pmdemand_atomic_check(state);
> +	if (ret)
> +		goto fail;
> +
>  	ret = intel_atomic_check_crtcs(state);
>  	if (ret)
>  		goto fail;
> @@ -6960,6 +6965,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	}
>  
>  	intel_sagv_pre_plane_update(state);
> +	intel_pmdemand_pre_plane_update(state);
>  
>  	/* Complete the events for pipes that have now been disabled */
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> @@ -7070,6 +7076,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		intel_verify_planes(state);
>  
>  	intel_sagv_post_plane_update(state);
> +	intel_pmdemand_post_plane_update(state);
>  
>  	drm_atomic_helper_commit_hw_done(&state->base);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 9f66d734edf6..9471a052aa57 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -345,6 +345,12 @@ struct intel_display {
>  		struct intel_global_obj obj;
>  	} dbuf;
>  
> +	struct {
> +		wait_queue_head_t waitqueue;
> +		struct mutex lock;
> +		struct intel_global_obj obj;
> +	} pmdemand;
> +

See the comment a little higher up:

	/* Grouping using anonymous structs. Keep sorted. */


>  	struct {
>  		/*
>  		 * dkl.phy_lock protects against concurrent access of the
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 60ce10fc7205..79853d8c3240 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -47,6 +47,7 @@
>  #include "intel_opregion.h"
>  #include "intel_overlay.h"
>  #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
>  #include "intel_pps.h"
>  #include "intel_quirks.h"
>  #include "intel_vga.h"
> @@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
>  	if (ret < 0)
>  		goto cleanup_vga;
>  
> +	intel_pmdemand_init(i915);
> +
>  	intel_power_domains_init_hw(i915, false);
>  
>  	if (!HAS_DISPLAY(i915))
> @@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
>  	if (ret)
>  		goto cleanup_vga_client_pw_domain_dmc;
>  
> +	ret = intel_pmdemand_state_init(i915);
> +	if (ret)
> +		goto cleanup_vga_client_pw_domain_dmc;
> +
>  	init_llist_head(&i915->display.atomic_helper.free_list);
>  	INIT_WORK(&i915->display.atomic_helper.free_work,
>  		  intel_atomic_helper_free_state_worker);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 5150069f3f82..f5c5a486efbc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -20,6 +20,7 @@
>  #include "intel_mchbar_regs.h"
>  #include "intel_pch_refclk.h"
>  #include "intel_pcode.h"
> +#include "intel_pmdemand.h"
>  #include "intel_pps_regs.h"
>  #include "intel_snps_phy.h"
>  #include "skl_watermark.h"
> @@ -1085,6 +1086,10 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
>  	dev_priv->display.dbuf.enabled_slices =
>  		intel_enabled_dbuf_slices_mask(dev_priv);
>  
> +	if (DISPLAY_VER(dev_priv) >= 14)
> +		intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
> +					    dev_priv->display.dbuf.enabled_slices);
> +
>  	/*
>  	 * Just power up at least 1 slice, we will
>  	 * figure out later which slices we have and what we need.
> @@ -1096,6 +1101,9 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
>  static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
>  {
>  	gen9_dbuf_slices_update(dev_priv, 0);
> +
> +	if (DISPLAY_VER(dev_priv) >= 14)
> +		intel_program_dbuf_pmdemand(dev_priv, 0);
>  }
>  
>  static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> new file mode 100644
> index 000000000000..df6429e7059d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -0,0 +1,455 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#include <linux/bitops.h>
> +
> +#include "i915_drv.h"
> +#include "i915_reg.h"
> +#include "intel_bw.h"
> +#include "intel_cdclk.h"
> +#include "intel_cx0_phy.h"
> +#include "intel_de.h"
> +#include "intel_display.h"
> +#include "intel_display_trace.h"
> +#include "intel_pmdemand.h"
> +#include "skl_watermark.h"
> +
> +struct intel_pmdemand_state {
> +	struct intel_global_state base;
> +
> +	u16 qclk_gv_bw;
> +	u8 voltage_index;
> +	u8 qclk_gv_index;
> +	u8 active_pipes;
> +	u8 dbufs;
> +	u8 active_phys_plls_mask;
> +	u16 cdclk_freq_mhz;
> +	u16 ddiclk_freq_mhz;
> +	u8 scalers;
> +};
> +
> +#define to_intel_pmdemand_state(x) container_of((x), struct intel_pmdemand_state, base)
> +
> +static struct intel_global_state *
> +intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
> +{
> +	struct intel_pmdemand_state *pmdmnd_state;
> +
> +	pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state), GFP_KERNEL);
> +	if (!pmdmnd_state)
> +		return NULL;
> +
> +	return &pmdmnd_state->base;
> +}
> +
> +static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
> +					 struct intel_global_state *state)
> +{
> +	kfree(state);
> +}
> +
> +static const struct intel_global_state_funcs intel_pmdemand_funcs = {
> +	.atomic_duplicate_state = intel_pmdemand_duplicate_state,
> +	.atomic_destroy_state = intel_pmdemand_destroy_state,
> +};
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_global_state *pmdemand_state;
> +
> +	pmdemand_state =
> +		intel_atomic_get_global_obj_state(state,
> +						  &i915->display.pmdemand.obj);
> +	if (IS_ERR(pmdemand_state))
> +		return ERR_CAST(pmdemand_state);
> +
> +	return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_global_state *pmdemand_state;
> +
> +	pmdemand_state = intel_atomic_get_old_global_obj_state(state, &i915->display.pmdemand.obj);
> +
> +	return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_global_state *pmdemand_state;
> +
> +	pmdemand_state = intel_atomic_get_new_global_obj_state(state, &i915->display.pmdemand.obj);
> +
> +	return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +int intel_pmdemand_state_init(struct drm_i915_private *i915)
> +{
> +	struct intel_pmdemand_state *pmdemand_state;
> +
> +	pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
> +	if (!pmdemand_state)
> +		return -ENOMEM;
> +
> +	intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
> +				     &pmdemand_state->base,
> +				     &intel_pmdemand_funcs);
> +
> +
> +	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> +		/* Wa_14016740474 */
> +		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
> +
> +	return 0;
> +}
> +
> +void intel_pmdemand_init(struct drm_i915_private *i915)
> +{
> +	mutex_init(&i915->display.pmdemand.lock);
> +	init_waitqueue_head(&i915->display.pmdemand.waitqueue);
> +}
> +
> +static bool pmdemand_needs_update(struct intel_atomic_state *state)
> +{
> +	bool changed = false;
> +	struct intel_crtc *crtc;
> +	int i;
> +	const struct intel_bw_state *new_bw_state, *old_bw_state;
> +	const struct intel_cdclk_state *new_cdclk_state;
> +	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> +	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> +
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		new_bw_state = intel_atomic_get_new_bw_state(state);
> +		old_bw_state = intel_atomic_get_old_bw_state(state);
> +
> +		new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> +		old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> +
> +		new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> +
> +		if ((new_bw_state && new_bw_state->qgv_point_peakbw !=
> +		     old_bw_state->qgv_point_peakbw) ||
> +		    (new_dbuf_state && new_dbuf_state->active_pipes !=
> +		     old_dbuf_state->active_pipes) || new_cdclk_state)
> +			changed = true;
> +
> +		/*
> +		 * break needs to be removed, if some crtc_state dependent
> +		 * parameters are added here
> +		 */
> +		break;
> +	}
> +
> +	return changed;
> +}
> +
> +int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	int port_clock = 0;
> +	struct intel_crtc *crtc;
> +	struct intel_encoder *encoder;
> +	const struct intel_bw_state *new_bw_state;
> +	const struct intel_cdclk_state *new_cdclk_state;
> +	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> +	const struct intel_dbuf_state *new_dbuf_state;
> +	struct intel_pmdemand_state *new_pmdemand_state;
> +	enum phy phy;
> +	int i, ret;
> +
> +	if (DISPLAY_VER(i915) < 14)
> +		return 0;
> +
> +	if (!pmdemand_needs_update(state))
> +		return 0;
> +
> +	new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
> +	if (IS_ERR(new_pmdemand_state))
> +		return PTR_ERR(new_pmdemand_state);
> +
> +	ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
> +	if (ret)
> +		return ret;
> +
> +	/* Punit figures out the voltage index based on bandwidth*/
> +	new_bw_state = intel_atomic_get_bw_state(state);
> +	if (IS_ERR(new_bw_state))
> +		return PTR_ERR(new_bw_state);
> +
> +	/* firmware will calculate the qclck_gc_index, requirement is set to 0 */
> +	new_pmdemand_state->qclk_gv_index = 0;
> +	new_pmdemand_state->qclk_gv_bw =
> +		min_t(u16, new_bw_state->qgv_point_peakbw, 0xffff);
> +
> +	new_dbuf_state = intel_atomic_get_dbuf_state(state);
> +	if (IS_ERR(new_dbuf_state))
> +		return PTR_ERR(new_dbuf_state);
> +
> +	i = hweight8(new_dbuf_state->active_pipes);
> +	new_pmdemand_state->active_pipes = min(i, 3);
> +
> +	new_cdclk_state = intel_atomic_get_cdclk_state(state);
> +	if (IS_ERR(new_cdclk_state))
> +		return PTR_ERR(new_cdclk_state);
> +
> +	new_pmdemand_state->voltage_index =
> +		new_cdclk_state->logical.voltage_level;
> +	/* KHz to MHz */
> +	new_pmdemand_state->cdclk_freq_mhz =
> +		DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
> +
> +	new_pmdemand_state->active_phys_plls_mask = 0;
> +
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		if (!new_crtc_state->hw.active)
> +			continue;
> +
> +		encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> +		if (!encoder)
> +			continue;
> +
> +		phy = intel_port_to_phy(i915, encoder->port);
> +
> +		if (intel_is_c10phy(i915, phy))
> +			new_pmdemand_state->active_phys_plls_mask |= BIT(phy);
> +
> +		port_clock = max(port_clock, new_crtc_state->port_clock);
> +	}
> +
> +	/* To MHz */
> +	new_pmdemand_state->ddiclk_freq_mhz = DIV_ROUND_UP(port_clock, 1000);
> +
> +	/*
> +	 * Setting scalers to max as it can not be calculated during flips and
> +	 * fastsets without taking global states locks.
> +	 */
> +	new_pmdemand_state->scalers = 7;
> +
> +	ret = intel_atomic_serialize_global_state(&new_pmdemand_state->base);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
> +{
> +	return !((intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> +		  XELPDP_PMDEMAND_REQ_ENABLE) ||
> +		(intel_de_read(i915, GEN12_DCPR_STATUS_1) &
> +		 XELPDP_PMDEMAND_INFLIGHT_STATUS));
> +}
> +
> +static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
> +{
> +	return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> +		 XELPDP_PMDEMAND_REQ_ENABLE);
> +}
> +
> +static int intel_pmdemand_wait(struct drm_i915_private *i915)
> +{
> +	DEFINE_WAIT(wait);
> +	int ret;
> +	const unsigned int timeout_ms = 10;
> +
> +	ret = wait_event_timeout(i915->display.pmdemand.waitqueue,
> +				 intel_pmdemand_req_complete(i915),
> +				 msecs_to_jiffies_timeout(timeout_ms));
> +	if (ret == 0)
> +		drm_err(&i915->drm,
> +			"timed out waiting for Punit PM Demand Response\n");
> +
> +	return ret;
> +}
> +
> +/* Required to be programmed during Display Init Sequences. */
> +void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
> +				 u8 dbuf_slices)
> +{
> +	u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
> +
> +	mutex_lock(&i915->display.pmdemand.lock);
> +	if (drm_WARN_ON(&i915->drm,
> +			!intel_pmdemand_check_prev_transaction(i915)))
> +		goto unlock;
> +
> +	intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> +		     XELPDP_PMDEMAND_DBUFS_MASK, XELPDP_PMDEMAND_DBUFS(dbufs));
> +	intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> +		     XELPDP_PMDEMAND_REQ_ENABLE);
> +
> +	intel_pmdemand_wait(i915);
> +
> +unlock:
> +	mutex_unlock(&i915->display.pmdemand.lock);
> +}
> +
> +static void update_pmdemand_values(const struct intel_pmdemand_state *new,
> +				   const struct intel_pmdemand_state *old,
> +				   u32 *reg1, u32 *reg2)
> +{
> +	u32 plls, tmp;
> +
> +	/*
> +	 * The pmdemand parameter updates happens in two steps. Pre plane and
> +	 * post plane updates. During the pre plane, as DE might still be
> +	 * handling with some old operations, to avoid unwanted performance
> +	 * issues, program the pmdemand parameters with higher of old and new
> +	 * values. And then after once settled, use the new parameter values
> +	 * as part of the post plane update.
> +	 */
> +
> +	/* Set 1*/
> +	*reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_BW_MASK;
> +	tmp = old ? max(old->qclk_gv_bw, new->qclk_gv_bw) : new->qclk_gv_bw;
> +	*reg1 |= XELPDP_PMDEMAND_QCLK_GV_BW(tmp);
> +
> +	*reg1 &= ~XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK;
> +	tmp = old ? max(old->voltage_index, new->voltage_index) :
> +		    new->voltage_index;
> +	*reg1 |= XELPDP_PMDEMAND_VOLTAGE_INDEX(tmp);
> +
> +	*reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK;
> +	tmp = old ? max(old->qclk_gv_index, new->qclk_gv_index) :
> +		    new->qclk_gv_index;
> +	*reg1 |= XELPDP_PMDEMAND_QCLK_GV_INDEX(tmp);
> +
> +	*reg1 &= ~XELPDP_PMDEMAND_PIPES_MASK;
> +	tmp = old ? max(old->active_pipes, new->active_pipes) :
> +		    new->active_pipes;
> +	*reg1 |= XELPDP_PMDEMAND_PIPES(tmp);
> +
> +	*reg1 &= ~XELPDP_PMDEMAND_PHYS_MASK;
> +	plls = hweight32(new->active_phys_plls_mask);
> +	if (old)
> +		plls = max(plls, hweight32(old->active_phys_plls_mask));
> +	*reg1 |= XELPDP_PMDEMAND_PHYS(plls);
> +
> +	/* Set 2*/
> +	*reg2 &= ~XELPDP_PMDEMAND_CDCLK_FREQ_MASK;
> +	tmp = old ? max(old->cdclk_freq_mhz, new->cdclk_freq_mhz) :
> +		    new->cdclk_freq_mhz;
> +	*reg2 |= XELPDP_PMDEMAND_CDCLK_FREQ(tmp);
> +
> +	*reg2 &= ~XELPDP_PMDEMAND_DDICLK_FREQ_MASK;
> +	tmp = old ? max(old->ddiclk_freq_mhz, new->ddiclk_freq_mhz) :
> +		    new->ddiclk_freq_mhz;
> +	*reg2 |= XELPDP_PMDEMAND_DDICLK_FREQ(tmp);
> +
> +	/* Hard code scalers to 7*/
> +	*reg2 &= ~XELPDP_PMDEMAND_SCALERS_MASK;
> +	tmp = old ? max(old->scalers, new->scalers) : new->scalers;
> +	*reg2 |= XELPDP_PMDEMAND_SCALERS(tmp);
> +
> +	/*
> +	 * Active_PLLs starts with 1 because of CDCLK PLL.
> +	 * TODO: Missing to account genlock filter when it gets used.
> +	 */
> +	*reg2 &= ~XELPDP_PMDEMAND_PLLS_MASK;
> +	*reg2 |= XELPDP_PMDEMAND_PLLS(plls + 1);
> +}
> +
> +static void intel_program_pmdemand(struct drm_i915_private *i915,
> +				   const struct intel_pmdemand_state *new,
> +				   const struct intel_pmdemand_state *old)
> +{
> +	bool changed = false;
> +	u32 reg1, mod_reg1;
> +	u32 reg2, mod_reg2;
> +
> +	mutex_lock(&i915->display.pmdemand.lock);
> +	if (drm_WARN_ON(&i915->drm,
> +			!intel_pmdemand_check_prev_transaction(i915)))
> +		goto unlock;
> +
> +	reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
> +	mod_reg1 = reg1;
> +
> +	reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
> +	mod_reg2 = reg2;
> +
> +	update_pmdemand_values(new, old, &mod_reg1, &mod_reg2);
> +
> +	if (reg1 != mod_reg1) {
> +		intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> +			       mod_reg1);
> +		changed = true;
> +	}
> +
> +	if (reg2 != mod_reg2) {
> +		intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> +			       mod_reg2);
> +		changed = true;
> +	}
> +
> +	/* Initiate pm demand request only if register values are changed */
> +	if (changed) {
> +		drm_dbg_kms(&i915->drm,
> +			    "initate pmdemand request values: (0x%x 0x%x)\n",
> +			    mod_reg1, mod_reg2);
> +
> +		intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> +			     XELPDP_PMDEMAND_REQ_ENABLE);
> +
> +		intel_pmdemand_wait(i915);
> +	}
> +
> +unlock:
> +	mutex_unlock(&i915->display.pmdemand.lock);
> +}
> +
> +static bool
> +intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
> +			     const struct intel_pmdemand_state *old)
> +{
> +	return memcmp(&new->qclk_gv_bw, &old->qclk_gv_bw,
> +		      sizeof(*new) - offsetof(typeof(*new), qclk_gv_bw)) != 0;
> +}
> +
> +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_pmdemand_state *new_pmdmnd_state =
> +		intel_atomic_get_new_pmdemand_state(state);
> +	const struct intel_pmdemand_state *old_pmdmnd_state =
> +		intel_atomic_get_old_pmdemand_state(state);
> +
> +	if (DISPLAY_VER(i915) < 14)
> +		return;
> +
> +	if (!new_pmdmnd_state ||
> +	    !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
> +		return;
> +
> +	intel_program_pmdemand(i915, new_pmdmnd_state, old_pmdmnd_state);
> +}
> +
> +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_pmdemand_state *new_pmdmnd_state =
> +		intel_atomic_get_new_pmdemand_state(state);
> +	const struct intel_pmdemand_state *old_pmdmnd_state =
> +		intel_atomic_get_old_pmdemand_state(state);
> +
> +	if (DISPLAY_VER(i915) < 14)
> +		return;
> +
> +	if (!new_pmdmnd_state ||
> +	    !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
> +		return;
> +
> +	intel_program_pmdemand(i915, new_pmdmnd_state, NULL);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> new file mode 100644
> index 000000000000..0114f4e0225a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef __INTEL_PMDEMAND_H__
> +#define __INTEL_PMDEMAND_H__
> +
> +#include <linux/types.h>
> +
> +struct drm_i915_private;
> +struct intel_atomic_state;
> +struct intel_crtc_state;
> +struct intel_plane_state;
> +
> +void intel_pmdemand_init(struct drm_i915_private *i915);
> +int intel_pmdemand_state_init(struct drm_i915_private *i915);
> +void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
> +				 u8 dbuf_slices);
> +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
> +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
> +int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
> +
> +#endif /* __INTEL_PMDEMAND_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2b94b8ca8ec9..907fa3aee179 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -41,6 +41,7 @@
>  #include "display/intel_fifo_underrun.h"
>  #include "display/intel_hotplug.h"
>  #include "display/intel_lpe_audio.h"
> +#include "display/intel_pmdemand.h"
>  #include "display/intel_psr.h"
>  #include "display/intel_psr_regs.h"
>  
> @@ -1986,12 +1987,25 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
>  		return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
>  }
>  
> +static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
> +{
> +	wake_up_all(&dev_priv->display.pmdemand.waitqueue);
> +}
> +
>  static void
>  gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>  {
>  	bool found = false;
>  
> -	if (iir & GEN8_DE_MISC_GSE) {
> +	if (DISPLAY_VER(dev_priv) >= 14 &&
> +	    (iir & (XELPDP_PMDEMAND_RSP | XELPDP_PMDEMAND_RSPTOUT_ERR))) {
> +		if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
> +			drm_dbg(&dev_priv->drm,
> +				"Error waiting for Punit PM Demand Response\n");
> +
> +		intel_pmdemand_irq_handler(dev_priv);
> +		found = true;
> +	} else if (iir & GEN8_DE_MISC_GSE) {
>  		intel_opregion_asle_intr(dev_priv);
>  		found = true;
>  	}
> @@ -3742,7 +3756,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>  		de_port_masked |= BXT_DE_PORT_GMBUS;
>  
> -	if (DISPLAY_VER(dev_priv) >= 11) {
> +	if (DISPLAY_VER(dev_priv) >= 14)
> +		de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
> +				  XELPDP_PMDEMAND_RSP;
> +	else if (DISPLAY_VER(dev_priv) >= 11) {
>  		enum port port;
>  
>  		if (intel_bios_is_dsi_present(dev_priv, &port))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dde6e91055bd..60c007aea1ce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4426,8 +4426,10 @@
>  #define GEN8_DE_MISC_IMR _MMIO(0x44464)
>  #define GEN8_DE_MISC_IIR _MMIO(0x44468)
>  #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> -#define  GEN8_DE_MISC_GSE		(1 << 27)
> -#define  GEN8_DE_EDP_PSR		(1 << 19)
> +#define  XELPDP_PMDEMAND_RSPTOUT_ERR	REG_BIT(27)
> +#define  GEN8_DE_MISC_GSE		REG_BIT(27)
> +#define  GEN8_DE_EDP_PSR		REG_BIT(19)
> +#define  XELPDP_PMDEMAND_RSP		REG_BIT(3)
>  
>  #define GEN8_PCU_ISR _MMIO(0x444e0)
>  #define GEN8_PCU_IMR _MMIO(0x444e4)
> @@ -4512,6 +4514,33 @@
>  #define  XELPDP_DP_ALT_HPD_LONG_DETECT		REG_BIT(1)
>  #define  XELPDP_DP_ALT_HPD_SHORT_DETECT		REG_BIT(0)
>  
> +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)		_MMIO(0x45230 + 4 * (dword))
> +#define  XELPDP_PMDEMAND_QCLK_GV_BW_MASK		REG_GENMASK(31, 16)
> +#define  XELPDP_PMDEMAND_QCLK_GV_BW(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
> +#define  XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK		REG_GENMASK(14, 12)
> +#define  XELPDP_PMDEMAND_VOLTAGE_INDEX(x)		REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
> +#define  XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK		REG_GENMASK(11, 8)
> +#define  XELPDP_PMDEMAND_QCLK_GV_INDEX(x)		REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
> +#define  XELPDP_PMDEMAND_PIPES_MASK			REG_GENMASK(7, 6)
> +#define  XELPDP_PMDEMAND_PIPES(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
> +#define  XELPDP_PMDEMAND_DBUFS_MASK			REG_GENMASK(5, 4)
> +#define  XELPDP_PMDEMAND_DBUFS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
> +#define  XELPDP_PMDEMAND_PHYS_MASK			REG_GENMASK(2, 0)
> +#define  XELPDP_PMDEMAND_PHYS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
> +
> +#define  XELPDP_PMDEMAND_REQ_ENABLE			REG_BIT(31)
> +#define  XELPDP_PMDEMAND_CDCLK_FREQ_MASK		REG_GENMASK(30, 20)
> +#define  XELPDP_PMDEMAND_CDCLK_FREQ(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
> +#define  XELPDP_PMDEMAND_DDICLK_FREQ_MASK		REG_GENMASK(18, 8)
> +#define  XELPDP_PMDEMAND_DDICLK_FREQ(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
> +#define  XELPDP_PMDEMAND_SCALERS_MASK			REG_GENMASK(6, 4)
> +#define  XELPDP_PMDEMAND_SCALERS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
> +#define  XELPDP_PMDEMAND_PLLS_MASK			REG_GENMASK(2, 0)
> +#define  XELPDP_PMDEMAND_PLLS(x)			REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
> +
> +#define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
> +#define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
> +
>  #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
>  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
>  #define   ILK_ELPIN_409_SELECT	REG_BIT(25)
> @@ -4671,6 +4700,9 @@
>  #define   DCPR_SEND_RESP_IMM			REG_BIT(25)
>  #define   DCPR_CLEAR_MEMSTAT_DIS		REG_BIT(24)
>  
> +#define XELPD_CHICKEN_DCPR_3			_MMIO(0x46438)
> +#define   DMD_RSP_TIMEOUT_DISABLE		REG_BIT(19)
> +
>  #define SKL_DFSM			_MMIO(0x51000)
>  #define   SKL_DFSM_DISPLAY_PM_DISABLE	(1 << 27)
>  #define   SKL_DFSM_DISPLAY_HDCP_DISABLE	(1 << 25)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v3 7/8] drm/i915/mtl: Add support for PM DEMAND

[Govindapillai, Vinod]

Hi Gustavo,

Thanks for the comments. Some inline responses are below!

On Fri, 2023-05-12 at 17:43 -0300, Gustavo Sousa wrote:
> Quoting Govindapillai, Vinod (2023-05-11 20:24:55)
> > Hello
> > 
> > Thanks for the comments. Pls see some inline replies..
> > 
> > On Thu, 2023-04-27 at 17:24 -0300, Gustavo Sousa wrote:
> > > Quoting Vinod Govindapillai (2023-04-27 12:00:15)
> > > > From: Mika Kahola <mika.kahola@intel.com>
> > > > 
> > > > Display14 introduces a new way to instruct the PUnit with
> > > > power and bandwidth requirements of DE. Add the functionality
> > > > to program the registers and handle waits using interrupts.
> > > > The current wait time for timeouts is programmed for 10 msecs to
> > > > factor in the worst case scenarios. Changes made to use REG_BIT
> > > > for a register that we touched(GEN8_DE_MISC_IER _MMIO).
> > > > 
> > > > Wa_14016740474 is added which applies to Xe_LPD+ display
> > > > 
> > > > v2: checkpatch warning fixes, simplify program pmdemand part
> > > > 
> > > > v3: update to dbufs and pipes values to pmdemand register(stan)
> > > >    Removed the macro usage in update_pmdemand_values()
> > > > 
> > > > Bspec: 66451, 64636, 64602, 64603
> > > > Cc: Matt Atwood <matthew.s.atwood@intel.com>
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/Makefile                 |   3 +-
> > > > drivers/gpu/drm/i915/display/intel_display.c  |   7 +
> > > > .../gpu/drm/i915/display/intel_display_core.h |   6 +
> > > > .../drm/i915/display/intel_display_driver.c   |   7 +
> > > > .../drm/i915/display/intel_display_power.c    |   8 +
> > > > drivers/gpu/drm/i915/display/intel_pmdemand.c | 455 ++++++++++++++++++
> > > > drivers/gpu/drm/i915/display/intel_pmdemand.h |  24 +
> > > > drivers/gpu/drm/i915/i915_irq.c               |  21 +-
> > > > drivers/gpu/drm/i915/i915_reg.h               |  36 +-
> > > > 9 files changed, 562 insertions(+), 5 deletions(-)
> > > > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> > > > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > > > index 9af76e376ca9..eb899fa86e51 100644
> > > > --- a/drivers/gpu/drm/i915/Makefile
> > > > +++ b/drivers/gpu/drm/i915/Makefile
> > > > @@ -281,7 +281,8 @@ i915-y += \
> > > >        display/i9xx_wm.o \
> > > >        display/skl_scaler.o \
> > > >        display/skl_universal_plane.o \
> > > > -  display/skl_watermark.o
> > > > +  display/skl_watermark.o \
> > > > +  display/intel_pmdemand.o
> > > > i915-$(CONFIG_ACPI) += \
> > > >        display/intel_acpi.o \
> > > >        display/intel_opregion.o
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index bf391a6cd8d6..f98e235fadc6 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -99,6 +99,7 @@
> > > > #include "intel_pcode.h"
> > > > #include "intel_pipe_crc.h"
> > > > #include "intel_plane_initial.h"
> > > > +#include "intel_pmdemand.h"
> > > > #include "intel_pps.h"
> > > > #include "intel_psr.h"
> > > > #include "intel_sdvo.h"
> > > > @@ -6306,6 +6307,10 @@ int intel_atomic_check(struct drm_device *dev,
> > > >                        return ret;
> > > >        }
> > > > 
> > > > +  ret = intel_pmdemand_atomic_check(state);
> > > > +  if (ret)
> > > > +          goto fail;
> > > > +
> > > >        ret = intel_atomic_check_crtcs(state);
> > > >        if (ret)
> > > >                goto fail;
> > > > @@ -6960,6 +6965,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > >        }
> > > > 
> > > >        intel_sagv_pre_plane_update(state);
> > > > +  intel_pmdemand_pre_plane_update(state);
> > > > 
> > > >        /* Complete the events for pipes that have now been disabled */
> > > >        for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > > > @@ -7070,6 +7076,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > >                intel_verify_planes(state);
> > > > 
> > > >        intel_sagv_post_plane_update(state);
> > > > +  intel_pmdemand_post_plane_update(state);
> > > > 
> > > >        drm_atomic_helper_commit_hw_done(&state->base);
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > index 9f66d734edf6..9471a052aa57 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > @@ -345,6 +345,12 @@ struct intel_display {
> > > >                struct intel_global_obj obj;
> > > >        } dbuf;
> > > > 
> > > > +  struct {
> > > > +          wait_queue_head_t waitqueue;
> > > > +          struct mutex lock;
> > > > +          struct intel_global_obj obj;
> > > > +  } pmdemand;
> > > > +
> > > >        struct {
> > > >                /*
> > > >                 * dkl.phy_lock protects against concurrent access of the
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > > > b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > > > index 60ce10fc7205..79853d8c3240 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > > > @@ -47,6 +47,7 @@
> > > > #include "intel_opregion.h"
> > > > #include "intel_overlay.h"
> > > > #include "intel_plane_initial.h"
> > > > +#include "intel_pmdemand.h"
> > > > #include "intel_pps.h"
> > > > #include "intel_quirks.h"
> > > > #include "intel_vga.h"
> > > > @@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
> > > >        if (ret < 0)
> > > >                goto cleanup_vga;
> > > > 
> > > > +  intel_pmdemand_init(i915);
> > > > +
> > > >        intel_power_domains_init_hw(i915, false);
> > > > 
> > > >        if (!HAS_DISPLAY(i915))
> > > > @@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
> > > >        if (ret)
> > > >                goto cleanup_vga_client_pw_domain_dmc;
> > > > 
> > > > +  ret = intel_pmdemand_state_init(i915);
> > > > +  if (ret)
> > > > +          goto cleanup_vga_client_pw_domain_dmc;
> > > > +
> > > >        init_llist_head(&i915->display.atomic_helper.free_list);
> > > >        INIT_WORK(&i915->display.atomic_helper.free_work,
> > > >                  intel_atomic_helper_free_state_worker);
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > index 5150069f3f82..f5c5a486efbc 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > @@ -20,6 +20,7 @@
> > > > #include "intel_mchbar_regs.h"
> > > > #include "intel_pch_refclk.h"
> > > > #include "intel_pcode.h"
> > > > +#include "intel_pmdemand.h"
> > > > #include "intel_pps_regs.h"
> > > > #include "intel_snps_phy.h"
> > > > #include "skl_watermark.h"
> > > > @@ -1085,6 +1086,10 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
> > > >        dev_priv->display.dbuf.enabled_slices =
> > > >                intel_enabled_dbuf_slices_mask(dev_priv);
> > > > 
> > > > +  if (DISPLAY_VER(dev_priv) >= 14)
> > > > +          intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
> > > > +                                      dev_priv->display.dbuf.enabled_slices);
> > > > +
> > > >        /*
> > > >         * Just power up at least 1 slice, we will
> > > >         * figure out later which slices we have and what we need.
> > > > @@ -1096,6 +1101,9 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
> > > > static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
> > > > {
> > > >        gen9_dbuf_slices_update(dev_priv, 0);
> > > > +
> > > > +  if (DISPLAY_VER(dev_priv) >= 14)
> > > > +          intel_program_dbuf_pmdemand(dev_priv, 0);
> > > > }
> > > > 
> > > > static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > > > b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > > > new file mode 100644
> > > > index 000000000000..df6429e7059d
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> > > > @@ -0,0 +1,455 @@
> > > > +// SPDX-License-Identifier: MIT
> > > > +/*
> > > > + * Copyright © 2024 Intel Corporation
> > > > + */
> > > > +
> > > > +#include <linux/bitops.h>
> > > > +
> > > > +#include "i915_drv.h"
> > > > +#include "i915_reg.h"
> > > > +#include "intel_bw.h"
> > > > +#include "intel_cdclk.h"
> > > > +#include "intel_cx0_phy.h"
> > > > +#include "intel_de.h"
> > > > +#include "intel_display.h"
> > > > +#include "intel_display_trace.h"
> > > > +#include "intel_pmdemand.h"
> > > > +#include "skl_watermark.h"
> > > > +
> > > > +struct intel_pmdemand_state {
> > > > +  struct intel_global_state base;
> > > > +
> > > > +  u16 qclk_gv_bw;
> > > > +  u8 voltage_index;
> > > > +  u8 qclk_gv_index;
> > > > +  u8 active_pipes;
> > > > +  u8 dbufs;
> > > > +  u8 active_phys_plls_mask;
> > > 
> > > Is u8 enough for the mask? The enum phy shows 9 possible PHY_* members.
> > > Also, I think having BUILD_BUG_ON() somewhere in this file to make sure
> > > we have enough bits would be nice.
> > Thanks. updated.
> > > 
> > > > +  u16 cdclk_freq_mhz;
> > > > +  u16 ddiclk_freq_mhz;
> > > > +  u8 scalers;
> > > > +};
> > > > +
> > > > +#define to_intel_pmdemand_state(x) container_of((x), struct intel_pmdemand_state, base)
> > > > +
> > > > +static struct intel_global_state *
> > > > +intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
> > > > +{
> > > > +  struct intel_pmdemand_state *pmdmnd_state;
> > > > +
> > > > +  pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state), GFP_KERNEL);
> > > > +  if (!pmdmnd_state)
> > > > +          return NULL;
> > > > +
> > > > +  return &pmdmnd_state->base;
> > > > +}
> > > > +
> > > > +static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
> > > > +                                   struct intel_global_state *state)
> > > > +{
> > > > +  kfree(state);
> > > > +}
> > > > +
> > > > +static const struct intel_global_state_funcs intel_pmdemand_funcs = {
> > > > +  .atomic_duplicate_state = intel_pmdemand_duplicate_state,
> > > > +  .atomic_destroy_state = intel_pmdemand_destroy_state,
> > > > +};
> > > > +
> > > > +static struct intel_pmdemand_state *
> > > > +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
> > > > +{
> > > > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > > +  struct intel_global_state *pmdemand_state;
> > > > +
> > > > +  pmdemand_state =
> > > > +          intel_atomic_get_global_obj_state(state,
> > > > +                                            &i915->display.pmdemand.obj);
> > > > +  if (IS_ERR(pmdemand_state))
> > > > +          return ERR_CAST(pmdemand_state);
> > > > +
> > > > +  return to_intel_pmdemand_state(pmdemand_state);
> > > > +}
> > > > +
> > > > +static struct intel_pmdemand_state *
> > > > +intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
> > > > +{
> > > > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > > +  struct intel_global_state *pmdemand_state;
> > > > +
> > > > +  pmdemand_state = intel_atomic_get_old_global_obj_state(state, &i915-
> > > > >display.pmdemand.obj);
> > > 
> > > Wouldn't it be safer if we returned early here when pmdemand_state is
> > > NULL?
> > > 
> > > I think to_intel_pmdemand_state(NULL) pmdemand_state just happens to
> > > work (i.e. still returns NULL) because the "base" member is at the
> > > beginning of the struct. However, we shouldn't rely on that IMO.
> > 
> > Well. It is a valid point. But the base pointer is the first member for exaclty the reason you
> > pointed out. So  to prevent someone from accidentally move that "base" from that position, I
> > added a
> > BUILD_BUG_ON() check. There are few other state objects which lack such a check. I will address
> > that
> > as a separate patch.
> 
> Hm... Not sure I am totally convinced here. If we are enforcing (with
> BUILD_BUG_ON()) the base to be the first member, then what is the point in using
> container_of() instead of just a simple cast?
> 
> I believe one of the points of using container_of() is that it alows we *not* to
> enforce a strict layout of the containing struct for things to work.
> 
> Now, if for some (yet unkown) reason we need to move the "base" member in the
> future, it would be difficult to find all places where the pointer could be NULL
> but we relied one the assumption that "base" would always be at offset 0.

I agree! But for example, bw_state, cdclk_state etc. use similar approach. So assumed the base is
the first member for that reason! 

Anyway I can check for NULL explicitly in this case!

> 
> > 
> > > 
> > > > +
> > > > +  return to_intel_pmdemand_state(pmdemand_state);
> > > > +}
> > > > +
> > > > +static struct intel_pmdemand_state *
> > > > +intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
> > > > +{
> > > > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > > +  struct intel_global_state *pmdemand_state;
> > > > +
> > > > +  pmdemand_state = intel_atomic_get_new_global_obj_state(state, &i915-
> > > > >display.pmdemand.obj);
> > > 
> > > Just as with intel_atomic_get_old_pmdemand_state(), shouldn't we return
> > > early if pmdemand_state is NULL here?
> > > 
> > > > +
> > > > +  return to_intel_pmdemand_state(pmdemand_state);
> > > > +}
> > > > +
> > > > +int intel_pmdemand_state_init(struct drm_i915_private *i915)
> > > > +{
> > > > +  struct intel_pmdemand_state *pmdemand_state;
> > > > +
> > > > +  pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
> > > > +  if (!pmdemand_state)
> > > > +          return -ENOMEM;
> > > > +
> > > > +  intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
> > > > +                               &pmdemand_state->base,
> > > > +                               &intel_pmdemand_funcs);
> > > > +
> > > > +
> > > > +  if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> > > > +          /* Wa_14016740474 */
> > > > +          intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
> > > > +
> > > > +  return 0;
> > > > +}
> > > > +
> > > > +void intel_pmdemand_init(struct drm_i915_private *i915)
> > > > +{
> > > > +  mutex_init(&i915->display.pmdemand.lock);
> > > > +  init_waitqueue_head(&i915->display.pmdemand.waitqueue);
> > > > +}
> > > 
> > > The functions intel_pmdemand_state_init() and intel_pmdemand_init() are
> > > both called from the same place. Furthermore,
> > > intel_pmdemand_state_init() isn't only initializing the state, as the
> > > Wa_14016740474 workaround is programmed there. Could we have only the
> > > function intel_pmdemand_init() and incorporate what
> > > intel_pmdemand_state_init() does in it?
> > 
> > I tried that earlier and wasn't possible. Because the intel_power_domains_init_hw() will call
> > the
> > pmdemand debuf config. And I can't recall the other issue. But I will confirm this again and
> > update
> > as I am not able to try this locally.
> 
> Well, regarding intel_power_domains_init_hw(), wouldn't the solution be to call
> the single init function for PM Demand before that one is called? Am I missing
> something?

Yeah.. the problem with that is, 
 INIT_LIST_HEAD(&i915->display.global.obj_list); happens in 228,2: intel_mode_config_init(i915);
which is called bit later!


[   17.238639] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7: 0000000000000400
[   17.238640] PKRU: 55555554
[   17.238642] Call Trace:
[   17.238643]  <TASK>
[   17.238644]  intel_atomic_global_obj_init+0x49/0x70 [i915]
[   17.238769]  intel_pmdemand_init+0x3f/0xf0 [i915]
[   17.238887]  intel_display_driver_probe_noirq+0x94/0x2d0 [i915]
[   17.239005]  i915_driver_probe+0x4ce/0xce0 [i915]
[   17.239095]  i915_pci_probe+0xc6/0x1f0 [i915]
[   17.239181]  pci_device_probe+0x9e/0x160



 

> 
> > > 
> > > > +
> > > > +static bool pmdemand_needs_update(struct intel_atomic_state *state)
> > > > +{
> > > > +  bool changed = false;
> > > > +  struct intel_crtc *crtc;
> > > > +  int i;
> > > > +  const struct intel_bw_state *new_bw_state, *old_bw_state;
> > > > +  const struct intel_cdclk_state *new_cdclk_state;
> > > > +  const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > > > +  const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> > > > +
> > > > +  for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > > > +                                      new_crtc_state, i) {
> > > > +          new_bw_state = intel_atomic_get_new_bw_state(state);
> > > > +          old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > +
> > > > +          new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> > > > +          old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> > > > +
> > > > +          new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> > > > +
> > > > +          if ((new_bw_state && new_bw_state->qgv_point_peakbw !=
> > > > +               old_bw_state->qgv_point_peakbw) ||
> > > > +              (new_dbuf_state && new_dbuf_state->active_pipes !=
> > > > +               old_dbuf_state->active_pipes) || new_cdclk_state)
> > > > +                  changed = true;
> > > > +
> > > > +          /*
> > > > +           * break needs to be removed, if some crtc_state dependent
> > > > +           * parameters are added here
> > > > +           */
> > > > +          break;
> > > > +  }
> > > > +
> > > > +  return changed;
> > > > +}
> > > > +
> > > > +int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
> > > > +{
> > > > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > > +  int port_clock = 0;
> > > > +  struct intel_crtc *crtc;
> > > > +  struct intel_encoder *encoder;
> > > > +  const struct intel_bw_state *new_bw_state;
> > > > +  const struct intel_cdclk_state *new_cdclk_state;
> > > > +  const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > > > +  const struct intel_dbuf_state *new_dbuf_state;
> > > > +  struct intel_pmdemand_state *new_pmdemand_state;
> > > > +  enum phy phy;
> > > > +  int i, ret;
> > > > +
> > > > +  if (DISPLAY_VER(i915) < 14)
> > > > +          return 0;
> > > > +
> > > > +  if (!pmdemand_needs_update(state))
> > > > +          return 0;
> > > > +
> > > > +  new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
> > > > +  if (IS_ERR(new_pmdemand_state))
> > > > +          return PTR_ERR(new_pmdemand_state);
> > > > +
> > > > +  ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
> > > > +  if (ret)
> > > > +          return ret;
> > > > +
> > > > +  /* Punit figures out the voltage index based on bandwidth*/
> > > > +  new_bw_state = intel_atomic_get_bw_state(state);
> > > > +  if (IS_ERR(new_bw_state))
> > > > +          return PTR_ERR(new_bw_state);
> > > > +
> > > > +  /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
> > > > +  new_pmdemand_state->qclk_gv_index = 0;
> > > > +  new_pmdemand_state->qclk_gv_bw =
> > > > +          min_t(u16, new_bw_state->qgv_point_peakbw, 0xffff);
> > > > +
> > > > +  new_dbuf_state = intel_atomic_get_dbuf_state(state);
> > > > +  if (IS_ERR(new_dbuf_state))
> > > > +          return PTR_ERR(new_dbuf_state);
> > > > +
> > > > +  i = hweight8(new_dbuf_state->active_pipes);
> > > > +  new_pmdemand_state->active_pipes = min(i, 3);
> > > > +
> > > > +  new_cdclk_state = intel_atomic_get_cdclk_state(state);
> > > > +  if (IS_ERR(new_cdclk_state))
> > > > +          return PTR_ERR(new_cdclk_state);
> > > > +
> > > > +  new_pmdemand_state->voltage_index =
> > > > +          new_cdclk_state->logical.voltage_level;
> > > > +  /* KHz to MHz */
> > > > +  new_pmdemand_state->cdclk_freq_mhz =
> > > > +          DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
> > > > +
> > > > +  new_pmdemand_state->active_phys_plls_mask = 0;
> > > > +
> > > > +  for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > > > +                                      new_crtc_state, i) {
> > > > +          if (!new_crtc_state->hw.active)
> > > > +                  continue;
> > > > +
> > > > +          encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> > > > +          if (!encoder)
> > > > +                  continue;
> > > > +
> > > > +          phy = intel_port_to_phy(i915, encoder->port);
> > > > +
> > > > +          if (intel_is_c10phy(i915, phy))
> > > > +                  new_pmdemand_state->active_phys_plls_mask |= BIT(phy);
> > > > +
> > > > +          port_clock = max(port_clock, new_crtc_state->port_clock);
> > > > +  }
> > > 
> > > As previously noted in https://patchwork.freedesktop.org/patch/530495 ,
> > > I'm under the impression that this loop would not let us account for al
> > > active crtcs, only those currently being touched by this atomic
> > > transaction. Am I wrong to assume that
> > > for_each_oldnew_intel_crtc_in_state() would only iterate over crtcs
> > > touched by the atomic update?
> > 
> > I checked the intel_bw_check_data_rate() which should be doing something similar to find out
> > about
> > the datarate from eachi pipe and figure out the total data rate. So I thought this should be
> > sufficient. 
> 
> I took a quick look at intel_bw_check_data_rate()'s implementation and I think
> it works there because struct intel_bw_state has arrays containing values for
> each pipe, meaning that those not included in the atomic update would already
> contain the current values from previous transactions.
> 
> For the number of active phy PLLs, I believe we can handle it similarly to how
> it is done by intel_calc_active_pipes().
> 
> Now, for the maximum port_clock, maybe we could use the array approach like done
> with intel_bw_check_data_rate(). So we can always have all port_clock values
> here.

Based on my current understanding, the iteration to calculate the max ddiclk seems okay!
for_each_ondnew_intel_crtc_state() iterate through all the crtcs and I think we can use max(max,
ddiclk[i]) here! Tried some of the tests with multiple displays and seems to find the max ddiclk
fine.

About the active phys, i changed the logic! Now i iterate through the connector_state and finds the
active connectors and update corresponding phys. As we just need the number of active phys, I got
rid of the mask for active phys.

I will confirm this approach with some experts here as well!

Thanks
Vinod

> 
> > 
> > > 
> > > > +
> > > > +  /* To MHz */
> > > > +  new_pmdemand_state->ddiclk_freq_mhz = DIV_ROUND_UP(port_clock, 1000);
> > > > +
> > > > +  /*
> > > > +   * Setting scalers to max as it can not be calculated during flips and
> > > > +   * fastsets without taking global states locks.
> > > > +   */
> > > > +  new_pmdemand_state->scalers = 7;
> > > > +
> > > > +  ret = intel_atomic_serialize_global_state(&new_pmdemand_state->base);
> > > > +  if (ret)
> > > > +          return ret;
> > > > +
> > > > +  return 0;
> > > > +}
> > > > +
> > > > +static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
> > > > +{
> > > > +  return !((intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> > > > +            XELPDP_PMDEMAND_REQ_ENABLE) ||
> > > > +          (intel_de_read(i915, GEN12_DCPR_STATUS_1) &
> > > > +           XELPDP_PMDEMAND_INFLIGHT_STATUS));
> > > > +}
> > > > +
> > > > +static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
> > > > +{
> > > > +  return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> > > > +           XELPDP_PMDEMAND_REQ_ENABLE);
> > > > +}
> > > > +
> > > > +static int intel_pmdemand_wait(struct drm_i915_private *i915)
> > > > +{
> > > > +  DEFINE_WAIT(wait);
> > > > +  int ret;
> > > > +  const unsigned int timeout_ms = 10;
> > > > +
> > > > +  ret = wait_event_timeout(i915->display.pmdemand.waitqueue,
> > > > +                           intel_pmdemand_req_complete(i915),
> > > > +                           msecs_to_jiffies_timeout(timeout_ms));
> > > > +  if (ret == 0)
> > > > +          drm_err(&i915->drm,
> > > > +                  "timed out waiting for Punit PM Demand Response\n");
> > > > +
> > > > +  return ret;
> > > > +}
> > > > +
> > > > +/* Required to be programmed during Display Init Sequences. */
> > > > +void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
> > > > +                           u8 dbuf_slices)
> > > > +{
> > > > +  u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
> > > > +
> > > > +  mutex_lock(&i915->display.pmdemand.lock);
> > > > +  if (drm_WARN_ON(&i915->drm,
> > > > +                  !intel_pmdemand_check_prev_transaction(i915)))
> > > > +          goto unlock;
> > > > +
> > > > +  intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> > > > +               XELPDP_PMDEMAND_DBUFS_MASK, XELPDP_PMDEMAND_DBUFS(dbufs));
> > > > +  intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> > > > +               XELPDP_PMDEMAND_REQ_ENABLE);
> > > > +
> > > > +  intel_pmdemand_wait(i915);
> > > > +
> > > > +unlock:
> > > > +  mutex_unlock(&i915->display.pmdemand.lock);
> > > > +}
> > > > +
> > > > +static void update_pmdemand_values(const struct intel_pmdemand_state *new,
> > > > +                             const struct intel_pmdemand_state *old,
> > > > +                             u32 *reg1, u32 *reg2)
> > > > +{
> > > > +  u32 plls, tmp;
> > > > +
> > > > +  /*
> > > > +   * The pmdemand parameter updates happens in two steps. Pre plane and
> > > > +   * post plane updates. During the pre plane, as DE might still be
> > > > +   * handling with some old operations, to avoid unwanted performance
> > > > +   * issues, program the pmdemand parameters with higher of old and new
> > > > +   * values. And then after once settled, use the new parameter values
> > > > +   * as part of the post plane update.
> > > > +   */
> > > > +
> > > > +  /* Set 1*/
> > > > +  *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_BW_MASK;
> > > > +  tmp = old ? max(old->qclk_gv_bw, new->qclk_gv_bw) : new->qclk_gv_bw;
> > > > +  *reg1 |= XELPDP_PMDEMAND_QCLK_GV_BW(tmp);
> > > > +
> > > > +  *reg1 &= ~XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK;
> > > > +  tmp = old ? max(old->voltage_index, new->voltage_index) :
> > > > +              new->voltage_index;
> > > > +  *reg1 |= XELPDP_PMDEMAND_VOLTAGE_INDEX(tmp);
> > > > +
> > > > +  *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK;
> > > > +  tmp = old ? max(old->qclk_gv_index, new->qclk_gv_index) :
> > > > +              new->qclk_gv_index;
> > > > +  *reg1 |= XELPDP_PMDEMAND_QCLK_GV_INDEX(tmp);
> > > > +
> > > > +  *reg1 &= ~XELPDP_PMDEMAND_PIPES_MASK;
> > > > +  tmp = old ? max(old->active_pipes, new->active_pipes) :
> > > > +              new->active_pipes;
> > > > +  *reg1 |= XELPDP_PMDEMAND_PIPES(tmp);
> > > > +
> > > > +  *reg1 &= ~XELPDP_PMDEMAND_PHYS_MASK;
> > > > +  plls = hweight32(new->active_phys_plls_mask);
> > > > +  if (old)
> > > > +          plls = max(plls, hweight32(old->active_phys_plls_mask));
> > > > +  *reg1 |= XELPDP_PMDEMAND_PHYS(plls);
> > > 
> > > If plls > 7, we would be potentially programming this wrong (e.g. for
> > > plls=8, we would setting the field to 0).
> > 
> > Thanks for pointing that out. Fixed.
> > 
> > > 
> > > > +
> > > > +  /* Set 2*/
> > > > +  *reg2 &= ~XELPDP_PMDEMAND_CDCLK_FREQ_MASK;
> > > > +  tmp = old ? max(old->cdclk_freq_mhz, new->cdclk_freq_mhz) :
> > > > +              new->cdclk_freq_mhz;
> > > > +  *reg2 |= XELPDP_PMDEMAND_CDCLK_FREQ(tmp);
> > > > +
> > > > +  *reg2 &= ~XELPDP_PMDEMAND_DDICLK_FREQ_MASK;
> > > > +  tmp = old ? max(old->ddiclk_freq_mhz, new->ddiclk_freq_mhz) :
> > > > +              new->ddiclk_freq_mhz;
> > > > +  *reg2 |= XELPDP_PMDEMAND_DDICLK_FREQ(tmp);
> > > > +
> > > > +  /* Hard code scalers to 7*/
> > > 
> > > I think this comment can be dropped: the hardcoding happens in
> > > intel_pmdemand_atomic_check().
> > 
> > Done
> > > 
> > > > +  *reg2 &= ~XELPDP_PMDEMAND_SCALERS_MASK;
> > > > +  tmp = old ? max(old->scalers, new->scalers) : new->scalers;
> > > > +  *reg2 |= XELPDP_PMDEMAND_SCALERS(tmp);
> > > > +
> > > > +  /*
> > > > +   * Active_PLLs starts with 1 because of CDCLK PLL.
> > > > +   * TODO: Missing to account genlock filter when it gets used.
> > > > +   */
> > > > +  *reg2 &= ~XELPDP_PMDEMAND_PLLS_MASK;
> > > 
> > > I think we are missing the ternary operator here to select the maximum
> > > value for the pre-plane case.
> > As pet the above comments, it is just the plls from step earlier + 1
> 
> Ah, got it. Thanks.
> 
> > 
> > > 
> > > > +  *reg2 |= XELPDP_PMDEMAND_PLLS(plls + 1);
> > > > +}
> > > > +
> > > > +static void intel_program_pmdemand(struct drm_i915_private *i915,
> > > > +                             const struct intel_pmdemand_state *new,
> > > > +                             const struct intel_pmdemand_state *old)
> > > > +{
> > > > +  bool changed = false;
> > > > +  u32 reg1, mod_reg1;
> > > > +  u32 reg2, mod_reg2;
> > > > +
> > > > +  mutex_lock(&i915->display.pmdemand.lock);
> > > > +  if (drm_WARN_ON(&i915->drm,
> > > > +                  !intel_pmdemand_check_prev_transaction(i915)))
> > > > +          goto unlock;
> > > 
> > > According to the spec, we should wait and timeout after 10ms here.
> > > 
> > > > +
> > > > +  reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
> > > > +  mod_reg1 = reg1;
> > > > +
> > > > +  reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
> > > > +  mod_reg2 = reg2;
> > > > +
> > > > +  update_pmdemand_values(new, old, &mod_reg1, &mod_reg2);
> > > > +
> > > > +  if (reg1 != mod_reg1) {
> > > > +          intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> > > > +                         mod_reg1);
> > > > +          changed = true;
> > > > +  }
> > > > +
> > > > +  if (reg2 != mod_reg2) {
> > > > +          intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> > > > +                         mod_reg2);
> > > > +          changed = true;
> > > > +  }
> > > > +
> > > > +  /* Initiate pm demand request only if register values are changed */
> > > > +  if (changed) {
> > > 
> > > Nitpick: we could have
> > > 
> > >     if (!changed)
> > >             goto unlock;
> > > 
> > > and dedent the block below.
> > 
> > Done.
> > > 
> > > > +          drm_dbg_kms(&i915->drm,
> > > > +                      "initate pmdemand request values: (0x%x 0x%x)\n",
> > > > +                      mod_reg1, mod_reg2);
> > > > +
> > > > +          intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> > > > +                       XELPDP_PMDEMAND_REQ_ENABLE);
> > > > +
> > > > +          intel_pmdemand_wait(i915);
> > > > +  }
> > > > +
> > > > +unlock:
> > > > +  mutex_unlock(&i915->display.pmdemand.lock);
> > > > +}
> > > > +
> > > > +static bool
> > > > +intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
> > > > +                       const struct intel_pmdemand_state *old)
> > > > +{
> > > > +  return memcmp(&new->qclk_gv_bw, &old->qclk_gv_bw,
> > > > +                sizeof(*new) - offsetof(typeof(*new), qclk_gv_bw)) != 0;
> > > > +}
> > > > +
> > > > +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
> > > > +{
> > > > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > > +  const struct intel_pmdemand_state *new_pmdmnd_state =
> > > > +          intel_atomic_get_new_pmdemand_state(state);
> > > > +  const struct intel_pmdemand_state *old_pmdmnd_state =
> > > > +          intel_atomic_get_old_pmdemand_state(state);
> > > > +
> > > > +  if (DISPLAY_VER(i915) < 14)
> > > > +          return;
> > > > +
> > > > +  if (!new_pmdmnd_state ||
> > > > +      !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
> > > > +          return;
> > > > +
> > > > +  intel_program_pmdemand(i915, new_pmdmnd_state, old_pmdmnd_state);
> > > > +}
> > > > +
> > > > +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
> > > > +{
> > > > +  struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > > +  const struct intel_pmdemand_state *new_pmdmnd_state =
> > > > +          intel_atomic_get_new_pmdemand_state(state);
> > > > +  const struct intel_pmdemand_state *old_pmdmnd_state =
> > > > +          intel_atomic_get_old_pmdemand_state(state);
> > > > +
> > > > +  if (DISPLAY_VER(i915) < 14)
> > > > +          return;
> > > > +
> > > > +  if (!new_pmdmnd_state ||
> > > > +      !intel_pmdemand_state_changed(new_pmdmnd_state, old_pmdmnd_state))
> > > > +          return;
> > > > +
> > > > +  intel_program_pmdemand(i915, new_pmdmnd_state, NULL);
> > > > +}
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h
> > > > b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> > > > new file mode 100644
> > > > index 000000000000..0114f4e0225a
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> > > > @@ -0,0 +1,24 @@
> > > > +/* SPDX-License-Identifier: MIT */
> > > > +/*
> > > > + * Copyright © 2023 Intel Corporation
> > > > + */
> > > > +
> > > > +#ifndef __INTEL_PMDEMAND_H__
> > > > +#define __INTEL_PMDEMAND_H__
> > > > +
> > > > +#include <linux/types.h>
> > > > +
> > > > +struct drm_i915_private;
> > > > +struct intel_atomic_state;
> > > > +struct intel_crtc_state;
> > > > +struct intel_plane_state;
> > > > +
> > > > +void intel_pmdemand_init(struct drm_i915_private *i915);
> > > > +int intel_pmdemand_state_init(struct drm_i915_private *i915);
> > > > +void intel_program_dbuf_pmdemand(struct drm_i915_private *i915,
> > > > +                           u8 dbuf_slices);
> > > > +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
> > > > +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
> > > > +int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
> > > > +
> > > > +#endif /* __INTEL_PMDEMAND_H__ */
> > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > > index 2b94b8ca8ec9..907fa3aee179 100644
> > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > @@ -41,6 +41,7 @@
> > > > #include "display/intel_fifo_underrun.h"
> > > > #include "display/intel_hotplug.h"
> > > > #include "display/intel_lpe_audio.h"
> > > > +#include "display/intel_pmdemand.h"
> > > > #include "display/intel_psr.h"
> > > > #include "display/intel_psr_regs.h"
> > > > 
> > > > @@ -1986,12 +1987,25 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private
> > > > *dev_priv)
> > > >                return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> > > > }
> > > > 
> > > > +static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
> > > > +{
> > > > +  wake_up_all(&dev_priv->display.pmdemand.waitqueue);
> > > > +}
> > > > +
> > > > static void
> > > > gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> > > > {
> > > >        bool found = false;
> > > > 
> > > > -  if (iir & GEN8_DE_MISC_GSE) {
> > > > +  if (DISPLAY_VER(dev_priv) >= 14 &&
> > > > +      (iir & (XELPDP_PMDEMAND_RSP | XELPDP_PMDEMAND_RSPTOUT_ERR))) {
> > > > +          if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
> > > 
> > > I think we should have the (iir & (XELPDP_PMDEMAND_RSP |
> > > XELPDP_PMDEMAND_RSPTOUT_ERR)) part as nested if statement here.
> > > Otherwise, when the interrupt did not happen, we could endup checking
> > > for the GEN8_DE_MISC_GSE even when DISPLAY_VER(dev_priv) >= 14.
> > > 
> > > Even though we know that iir & GEN8_DE_MISC_GSE would be false in this
> > > situation (because both XELPDP_PMDEMAND_RSPTOUT_ERR and GEN8_DE_MISC_GSE
> > > map to the same bit), I think having that one checked only for previous
> > > display engines would sound more correct semantically speaking.
> > 
> > Thanks. updated.
> > 
> > > 
> > > > +                  drm_dbg(&dev_priv->drm,
> > > > +                          "Error waiting for Punit PM Demand Response\n");
> > > > +
> > > > +          intel_pmdemand_irq_handler(dev_priv);
> > > > +          found = true;
> > > > +  } else if (iir & GEN8_DE_MISC_GSE) {
> > > >                intel_opregion_asle_intr(dev_priv);
> > > >                found = true;
> > > >        }
> > > > @@ -3742,7 +3756,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private
> > > > *dev_priv)
> > > >        if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> > > >                de_port_masked |= BXT_DE_PORT_GMBUS;
> > > > 
> > > > -  if (DISPLAY_VER(dev_priv) >= 11) {
> > > > +  if (DISPLAY_VER(dev_priv) >= 14)
> > > > +          de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
> > > > +                            XELPDP_PMDEMAND_RSP;
> > > > +  else if (DISPLAY_VER(dev_priv) >= 11) {
> > > >                enum port port;
> > > > 
> > > >                if (intel_bios_is_dsi_present(dev_priv, &port))
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index dde6e91055bd..60c007aea1ce 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -4426,8 +4426,10 @@
> > > > #define GEN8_DE_MISC_IMR _MMIO(0x44464)
> > > > #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> > > > #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> > > > -#define  GEN8_DE_MISC_GSE         (1 << 27)
> > > > -#define  GEN8_DE_EDP_PSR          (1 << 19)
> > > > +#define  XELPDP_PMDEMAND_RSPTOUT_ERR      REG_BIT(27)
> > > > +#define  GEN8_DE_MISC_GSE         REG_BIT(27)
> > > > +#define  GEN8_DE_EDP_PSR          REG_BIT(19)
> > > > +#define  XELPDP_PMDEMAND_RSP              REG_BIT(3)
> > > > 
> > > > #define GEN8_PCU_ISR _MMIO(0x444e0)
> > > > #define GEN8_PCU_IMR _MMIO(0x444e4)
> > > > @@ -4512,6 +4514,33 @@
> > > > #define  XELPDP_DP_ALT_HPD_LONG_DETECT         REG_BIT(1)
> > > > #define  XELPDP_DP_ALT_HPD_SHORT_DETECT                REG_BIT(0)
> > > > 
> > > > +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)           _MMIO(0x45230 + 4 * (dword))
> > > > +#define  XELPDP_PMDEMAND_QCLK_GV_BW_MASK          REG_GENMASK(31, 16)
> > > > +#define  XELPDP_PMDEMAND_QCLK_GV_BW(x)                   
> > > > REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
> > > > +#define  XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK               REG_GENMASK(14, 12)
> > > > +#define  XELPDP_PMDEMAND_VOLTAGE_INDEX(x)        
> > > > REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
> > > > +#define  XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK               REG_GENMASK(11, 8)
> > > > +#define  XELPDP_PMDEMAND_QCLK_GV_INDEX(x)        
> > > > REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
> > > > +#define  XELPDP_PMDEMAND_PIPES_MASK                       REG_GENMASK(7, 6)
> > > > +#define  XELPDP_PMDEMAND_PIPES(x)                
> > > > REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
> > > > +#define  XELPDP_PMDEMAND_DBUFS_MASK                       REG_GENMASK(5, 4)
> > > > +#define  XELPDP_PMDEMAND_DBUFS(x)                
> > > > REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
> > > > +#define  XELPDP_PMDEMAND_PHYS_MASK                        REG_GENMASK(2, 0)
> > > > +#define  XELPDP_PMDEMAND_PHYS(x)                  REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK,
> > > > x)
> > > > +
> > > > +#define  XELPDP_PMDEMAND_REQ_ENABLE                       REG_BIT(31)
> > > > +#define  XELPDP_PMDEMAND_CDCLK_FREQ_MASK          REG_GENMASK(30, 20)
> > > > +#define  XELPDP_PMDEMAND_CDCLK_FREQ(x)                   
> > > > REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
> > > > +#define  XELPDP_PMDEMAND_DDICLK_FREQ_MASK         REG_GENMASK(18, 8)
> > > > +#define  XELPDP_PMDEMAND_DDICLK_FREQ(x)                  
> > > > REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
> > > > +#define  XELPDP_PMDEMAND_SCALERS_MASK                     REG_GENMASK(6, 4)
> > > > +#define  XELPDP_PMDEMAND_SCALERS(x)                      
> > > > REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
> > > > +#define  XELPDP_PMDEMAND_PLLS_MASK                        REG_GENMASK(2, 0)
> > > > +#define  XELPDP_PMDEMAND_PLLS(x)                  REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK,
> > > > x)
> > > > +
> > > > +#define GEN12_DCPR_STATUS_1                               _MMIO(0x46440)
> > > > +#define  XELPDP_PMDEMAND_INFLIGHT_STATUS          REG_BIT(26)
> > > > +
> > > > #define ILK_DISPLAY_CHICKEN2   _MMIO(0x42004)
> > > > /* Required on all Ironlake and Sandybridge according to the B-Spec. */
> > > > #define   ILK_ELPIN_409_SELECT REG_BIT(25)
> > > > @@ -4671,6 +4700,9 @@
> > > > #define   DCPR_SEND_RESP_IMM                   REG_BIT(25)
> > > > #define   DCPR_CLEAR_MEMSTAT_DIS               REG_BIT(24)
> > > > 
> > > > +#define XELPD_CHICKEN_DCPR_3                      _MMIO(0x46438)
> > > > +#define   DMD_RSP_TIMEOUT_DISABLE         REG_BIT(19)
> > > > +
> > > > #define SKL_DFSM                       _MMIO(0x51000)
> > > > #define   SKL_DFSM_DISPLAY_PM_DISABLE  (1 << 27)
> > > > #define   SKL_DFSM_DISPLAY_HDCP_DISABLE        (1 << 25)
> > > > -- 
> > > > 2.34.1
> > > > 
> > 

[Intel-gfx] [PATCH v3 0/8] mtl: add support for pmdemand

[Vinod Govindapillai]

pmdemand support patches for MTL

SAGV configuration support for MTL

v2: added one missing patch in the previous version

v3: chekcpatch warning fixes
    update index handling for the icl/tgl QGV point handling
    program pmdemand code simplified

Mika Kahola (1):
  drm/i915/mtl: Add support for PM DEMAND

Vinod Govindapillai (7):
  drm/i915: fix the derating percentage for MTL
  drm/i915: update the QGV point frequency calculations
  drm/i915: store the peak bw per QGV point
  drm/i915: extract intel_bw_check_qgv_points()
  drm/i915: modify max_bw to return index to intel_bw_info
  drm/i915/mtl: find best QGV point and configure sagv
  drm/i915/display: provision to suppress drm_warn in
    intel_get_crtc_new_encoder

 drivers/gpu/drm/i915/Makefile                 |   3 +-
 drivers/gpu/drm/i915/display/intel_bw.c       | 350 +++++++++-----
 drivers/gpu/drm/i915/display/intel_bw.h       |   6 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  17 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   3 +-
 .../gpu/drm/i915/display/intel_display_core.h |   8 +
 .../drm/i915/display/intel_display_driver.c   |   7 +
 .../drm/i915/display/intel_display_power.c    |   8 +
 drivers/gpu/drm/i915/display/intel_dpll.c     |   8 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c | 450 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_pmdemand.h |  24 +
 drivers/gpu/drm/i915/display/intel_snps_phy.c |   2 +-
 drivers/gpu/drm/i915/i915_irq.c               |  21 +-
 drivers/gpu/drm/i915/i915_reg.h               |  36 +-
 16 files changed, 814 insertions(+), 133 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h

-- 
2.34.1