[igt-dev] [i-g-t V5 00/47] Add IGT display support for XE

[igt-dev] [i-g-t V5 00/47] Add IGT display support for XE

[Bhanuprakash Modem]

Add IGT support to work kms tests on XE driver.

TODO: Spin, BUSY & HANG related tests.

V2: - Rebase on PW 116578v5
V3: - Rebase on PW 116578v6
V4: - Rebase on PW 116578v7
V5: - Rebase on PW 116578v8

Bhanuprakash Modem (30):
  lib/igt_fb: Add copy engine support for XE
  lib/igt_draw: Add gpu draw routine support for XE
  tests/i915/kms_big_fb: Add XE support
  tests/i915/kms_big_joiner: Add XE support
  tests/i915/kms_cdclk: Add XE support
  tests/i915/kms_draw_crc: Add XE support
  tests/i915/kms_dsc: Add XE support
  tests/i915/kms_flip_scaled_crc: Add XE support
  tests/i915/kms_flip_tiling: Add XE support
  tests/i915/kms_mmap_write_crc: Add XE support
  tests/kms_3d: Add XE support
  tests/kms_async_flips: No XE support
  tests/kms_atomic_transition: Add XE support
  tests/color: Add XE support
  tests/kms_concurrent: Add XE support
  tests/kms_content_protection: Add XE support
  tests/kms_cursor_crc: Add XE support
  tests/kms_flip_event_leak: Add XE support
  tests/kms_getfb: Add XE support
  tests/kms_hdmi_inject: Add XE support
  tests/kms_hdr: Add XE support
  tests/kms_panel_fitting: Add XE support
  tests/kms_plane: Add XE support
  tests/kms_plane_lowers: Add XE support
  tests/kms_plane_scaling: Add XE support
  tests/kms_prime: Use Rendercopy instead of Blit
  tests/kms_prime: Add XE support
  tests/kms_rotation_crc: Add XE support
  tests/kms_setmode: Add XE support
  tests/kms_universal_plane: Add XE support

Zbigniew Kempczyński (17):
  lib/xe_ioctl: Add missing header for direct resolving
  lib/xe_query: Add region helpers and missing doc
  lib/xe_query: Remove commented out function prototype
  lib/intel_allocator: Add allocator support for Xe
  lib/drmtest: Add driver enum for i915/xe
  lib/intel_bufops: Add Xe support in bufops
  lib/intel_batchbuffer: Rename i915 -> fd as preparation step for xe
  lib/intel_batchbuffer: Reacquire offset for reloc allocator in reset
    path
  lib/intel_batchbuffer: Update intel-bb docs
  lib/intel_batchbuffer: Add Xe support in intel-bb
  tests/xe_intel_bb: Check if intel-bb Xe support correctness
  tests/xe-fast-feedback: Add xe_intel_bb test to BAT
  lib/gpgpu_fill: Use RENDER engine flag to work on Xe
  tests/xe_gpgpu_fill: Exercise gpgpu fill on Xe
  lib/igt_fb: For xe assume vram is used on discrete
  lib/igt_draw: Pass region while building intel_buf from flink
  tests/kms_big_fb: Deduce region for xe framebuffer

 lib/drmtest.h                            |    8 +
 lib/gpgpu_fill.c                         |    4 +-
 lib/gpu_cmds.c                           |    2 +-
 lib/igt_draw.c                           |   95 +-
 lib/igt_draw.h                           |    2 +
 lib/igt_fb.c                             |   41 +-
 lib/intel_allocator.c                    |   40 +-
 lib/intel_aux_pgtable.c                  |    2 +-
 lib/intel_batchbuffer.c                  |  421 ++++++--
 lib/intel_batchbuffer.h                  |   22 +-
 lib/intel_bufops.c                       |  123 ++-
 lib/intel_bufops.h                       |   24 +-
 lib/xe/xe_ioctl.h                        |    1 +
 lib/xe/xe_query.c                        |   45 +
 lib/xe/xe_query.h                        |    3 +-
 tests/chamelium/kms_chamelium_color.c    |    2 +-
 tests/i915/gem_caching.c                 |    4 +-
 tests/i915/gem_pxp.c                     |    2 +-
 tests/i915/kms_big_fb.c                  |   84 +-
 tests/i915/kms_big_joiner.c              |    2 +-
 tests/i915/kms_cdclk.c                   |    5 +-
 tests/i915/kms_draw_crc.c                |   24 +-
 tests/i915/kms_dsc.c                     |    2 +-
 tests/i915/kms_flip_scaled_crc.c         |    8 +-
 tests/i915/kms_flip_tiling.c             |    8 +-
 tests/i915/kms_mmap_write_crc.c          |    4 +-
 tests/intel-ci/xe-fast-feedback.testlist |   19 +
 tests/kms_3d.c                           |    8 +
 tests/kms_async_flips.c                  |    8 +-
 tests/kms_atomic_transition.c            |    8 +-
 tests/kms_color.c                        |   10 +-
 tests/kms_color_helper.c                 |    2 +-
 tests/kms_concurrent.c                   |    4 +-
 tests/kms_content_protection.c           |   12 +-
 tests/kms_cursor_crc.c                   |    4 +-
 tests/kms_flip_event_leak.c              |    5 +
 tests/kms_getfb.c                        |   22 +-
 tests/kms_hdmi_inject.c                  |   10 +-
 tests/kms_hdr.c                          |    8 +-
 tests/kms_panel_fitting.c                |   12 +-
 tests/kms_plane.c                        |   19 +-
 tests/kms_plane_lowres.c                 |    9 +-
 tests/kms_plane_scaling.c                |   41 +-
 tests/kms_prime.c                        |  230 ++++-
 tests/kms_rotation_crc.c                 |   23 +-
 tests/kms_setmode.c                      |    7 +
 tests/kms_universal_plane.c              |   15 +-
 tests/meson.build                        |    2 +
 tests/xe/xe_gpgpu_fill.c                 |  135 +++
 tests/xe/xe_intel_bb.c                   | 1185 ++++++++++++++++++++++
 50 files changed, 2447 insertions(+), 329 deletions(-)
 create mode 100644 tests/xe/xe_gpgpu_fill.c
 create mode 100644 tests/xe/xe_intel_bb.c

--
2.40.0

[igt-dev] [i-g-t V5 01/47] lib/xe_ioctl: Add missing header for direct resolving

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

xe_ioctl.h user expects all types resolving. Add missing stddef.h
header which contains size_t definition.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 lib/xe/xe_ioctl.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index d8c40eda0..049cd183d 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -11,6 +11,7 @@
 #ifndef XE_IOCTL_H
 #define XE_IOCTL_H
 
+#include <stddef.h>
 #include <stdint.h>
 #include <xe_drm.h>
 
-- 
2.40.0

[igt-dev] [i-g-t V5 02/47] lib/xe_query: Add region helpers and missing doc

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

For easier iterate over memory regions and produce dynamic subtests
add xe_region_name() helper.

As Xe requires buffer size alignment during creating bo add
xe_min_page_size() helper.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 lib/xe/xe_query.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
 lib/xe/xe_query.h |  2 ++
 2 files changed, 47 insertions(+)

diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 2b627a78a..bd5eb1d18 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -422,6 +422,13 @@ struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx)
 	return &xe_dev->hw_engines[idx];
 }
 
+/**
+ * xe_mem_region:
+ * @fd: xe device fd
+ * @region: region mask
+ *
+ * Returns memory region structure for @region mask.
+ */
 struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region)
 {
 	struct xe_device *xe_dev;
@@ -434,6 +441,44 @@ struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region)
 	return &xe_dev->mem_usage->regions[region_idx];
 }
 
+/**
+ * xe_region_name:
+ * @region: region mask
+ *
+ * Returns region string like "system" or "vram-n" where n=0...62.
+ */
+const char *xe_region_name(uint64_t region)
+{
+	static char **vrams;
+	int region_idx = ffs(region) - 1;
+
+	/* Populate the array */
+	if (!vrams) {
+		vrams = calloc(64, sizeof(char *));
+		for (int i = 0; i < 64; i++) {
+			if (i != 0)
+				asprintf(&vrams[i], "vram-%d", i - 1);
+			else
+				asprintf(&vrams[i], "system");
+			igt_assert(vrams[i]);
+		}
+	}
+
+	return vrams[region_idx];
+}
+
+/**
+ * xe_min_page_size:
+ * @fd: xe device fd
+ * @region: region mask
+ *
+ * Returns minimum page size for @region.
+ */
+uint32_t xe_min_page_size(int fd, uint64_t region)
+{
+	return xe_mem_region(fd, region)->min_page_size;
+}
+
 /**
  * xe_number_hw_engine:
  * @fd: xe device fd
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 0d4b810a1..f49acb1d7 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -84,6 +84,8 @@ uint64_t vram_if_possible(int fd, int gt);
 struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
 struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
 struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);
+const char *xe_region_name(uint64_t region);
+uint32_t xe_min_page_size(int fd, uint64_t region);
 unsigned int xe_number_hw_engines(int fd);
 bool xe_has_vram(int fd);
 //uint64_t xe_vram_size(int fd);
-- 
2.40.0

[igt-dev] [i-g-t V5 03/47] lib/xe_query: Remove commented out function prototype

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Remove unnecessary commented out code.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 lib/xe/xe_query.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index f49acb1d7..cc6e7cefd 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -88,7 +88,6 @@ const char *xe_region_name(uint64_t region);
 uint32_t xe_min_page_size(int fd, uint64_t region);
 unsigned int xe_number_hw_engines(int fd);
 bool xe_has_vram(int fd);
-//uint64_t xe_vram_size(int fd);
 uint64_t xe_vram_size(int fd, int gt);
 uint32_t xe_get_default_alignment(int fd);
 uint32_t xe_va_bits(int fd);
-- 
2.40.0

[igt-dev] [i-g-t V5 04/47] lib/intel_allocator: Add allocator support for Xe

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Start supporting va range configuration for xe allocator.

During opening allocator has to be aware of vm range (start and end).
i915 driver doesn't expose vm range information so those variables
have to be detected. In xe driver we get information of va size from
the kernel query so va end can be directly configured. At the moment
there's no autodetection of va start for xe what might need to be
address in the future if for some reason lower offsets might not be
in use.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 lib/intel_allocator.c | 40 +++++++++++++++++++++++++---------------
 1 file changed, 25 insertions(+), 15 deletions(-)

diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c
index 2b08dd599..45c1168ab 100644
--- a/lib/intel_allocator.c
+++ b/lib/intel_allocator.c
@@ -16,6 +16,7 @@
 #include "igt_map.h"
 #include "intel_allocator.h"
 #include "intel_allocator_msgchannel.h"
+#include "xe/xe_query.h"
 
 //#define ALLOCDBG
 #ifdef ALLOCDBG
@@ -910,24 +911,33 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx,
 	struct alloc_resp resp;
 	uint64_t gtt_size;
 
-	if (!start)
-		req.open.start = gem_detect_safe_start_offset(fd);
+	if (is_i915_device(fd)) {
+		if (!start)
+			req.open.start = gem_detect_safe_start_offset(fd);
 
-	if (!end) {
-		igt_assert_f(can_report_gtt_size(fd), "Invalid fd\n");
-		gtt_size = gem_aperture_size(fd);
-		if (!gem_uses_full_ppgtt(fd))
-			gtt_size /= 2;
-		else
-			gtt_size -= RESERVED;
+		if (!end) {
+			igt_assert_f(can_report_gtt_size(fd), "Invalid fd\n");
+			gtt_size = gem_aperture_size(fd);
+			if (!gem_uses_full_ppgtt(fd))
+				gtt_size /= 2;
+			else
+				gtt_size -= RESERVED;
 
-		req.open.end = gtt_size;
-	}
+			req.open.end = gtt_size;
+		}
 
-	if (!default_alignment)
-		req.open.default_alignment = gem_detect_safe_alignment(fd);
+		if (!default_alignment)
+			req.open.default_alignment = gem_detect_safe_alignment(fd);
+
+		req.open.start = ALIGN(req.open.start, req.open.default_alignment);
+	} else {
+		struct xe_device *xe_dev = xe_device_get(fd);
 
-	req.open.start = ALIGN(req.open.start, req.open.default_alignment);
+		igt_assert(xe_dev);
+
+		if (!end)
+			req.open.end = 1ull << xe_dev->va_bits;
+	}
 
 	/* Get child_tid only once at open() */
 	if (child_tid == -1)
@@ -998,7 +1008,7 @@ uint64_t intel_allocator_open_vm_full(int fd, uint32_t vm,
 
 /**
  * intel_allocator_open:
- * @fd: i915 descriptor
+ * @fd: i915 or xe descriptor
  * @ctx: context
  * @allocator_type: one of INTEL_ALLOCATOR_* define
  *
-- 
2.40.0

[igt-dev] [i-g-t V5 05/47] lib/drmtest: Add driver enum for i915/xe

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Library code like intel-bb and intel-buf which requires adoption
to handle both drivers should store driver on which fd they are
working on instead of calling costful is_i915/xe_device() helper.

Introduce intel_driver enum which will be used on library code
adoption to Xe.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
---
 lib/drmtest.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/lib/drmtest.h b/lib/drmtest.h
index 5878f6512..3c88b85c6 100644
--- a/lib/drmtest.h
+++ b/lib/drmtest.h
@@ -62,6 +62,14 @@
  */
 #define DRIVER_ANY 	~(DRIVER_VGEM)
 
+/*
+ * Compile friendly enum for i915/xe.
+ */
+enum intel_driver {
+	INTEL_DRIVER_I915 = 1,
+	INTEL_DRIVER_XE,
+};
+
 void __set_forced_driver(const char *name);
 
 /**
-- 
2.40.0

[igt-dev] [i-g-t V5 06/47] lib/intel_bufops: Add Xe support in bufops

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Extend bufops to support Xe:
 - change region to 64bit region mask,
 - add initialization helper (full) which allows passing handle,
   size and region,
 - mapping functions (read + write) selects driver specific mapping

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
---
 lib/intel_bufops.c | 123 +++++++++++++++++++++++++++++++++++++++++----
 lib/intel_bufops.h |  24 ++++++++-
 2 files changed, 136 insertions(+), 11 deletions(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index cdc7a1698..46fd981f0 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -29,6 +29,8 @@
 #include "igt.h"
 #include "igt_x86.h"
 #include "intel_bufops.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
 
 /**
  * SECTION:intel_bufops
@@ -106,6 +108,7 @@ typedef void (*bo_copy)(struct buf_ops *, struct intel_buf *, uint32_t *);
 
 struct buf_ops {
 	int fd;
+	enum intel_driver driver;
 	int gen_start;
 	int gen_end;
 	unsigned int intel_gen;
@@ -488,6 +491,9 @@ static void *mmap_write(int fd, struct intel_buf *buf)
 {
 	void *map = NULL;
 
+	if (buf->bops->driver == INTEL_DRIVER_XE)
+		return xe_bo_map(fd, buf->handle, buf->surface[0].size);
+
 	if (gem_has_lmem(fd)) {
 		/*
 		 * set/get_caching and set_domain are no longer supported on
@@ -530,6 +536,9 @@ static void *mmap_read(int fd, struct intel_buf *buf)
 {
 	void *map = NULL;
 
+	if (buf->bops->driver == INTEL_DRIVER_XE)
+		return xe_bo_map(fd, buf->handle, buf->surface[0].size);
+
 	if (gem_has_lmem(fd)) {
 		/*
 		 * set/get_caching and set_domain are no longer supported on
@@ -809,7 +818,7 @@ static void __intel_buf_init(struct buf_ops *bops,
 			     int width, int height, int bpp, int alignment,
 			     uint32_t req_tiling, uint32_t compression,
 			     uint64_t bo_size, int bo_stride,
-			     uint32_t region)
+			     uint64_t region)
 {
 	uint32_t tiling = req_tiling;
 	uint64_t size;
@@ -899,9 +908,20 @@ static void __intel_buf_init(struct buf_ops *bops,
 	buf->size = size;
 	buf->handle = handle;
 
-	if (!handle)
-		if (__gem_create_in_memory_regions(bops->fd, &buf->handle, &size, region))
-			igt_assert_eq(__gem_create(bops->fd, &size, &buf->handle), 0);
+	if (bops->driver == INTEL_DRIVER_XE)
+		igt_assert_f(region != -1, "Xe requires region awareness, "
+					   "use api which passes valid region\n");
+	buf->region = region;
+
+	if (!handle) {
+		if (bops->driver == INTEL_DRIVER_I915) {
+			if (__gem_create_in_memory_regions(bops->fd, &buf->handle, &size, region))
+				igt_assert_eq(__gem_create(bops->fd, &size, &buf->handle), 0);
+		} else {
+			size = ALIGN(size, xe_get_default_alignment(bops->fd));
+			buf->handle = xe_bo_create_flags(bops->fd, 0, size, region);
+		}
+	}
 
 	/* Store gem bo size */
 	buf->bo_size = size;
@@ -930,8 +950,12 @@ void intel_buf_init(struct buf_ops *bops,
 		    int width, int height, int bpp, int alignment,
 		    uint32_t tiling, uint32_t compression)
 {
+	uint64_t region;
+
+	region = bops->driver == INTEL_DRIVER_I915 ? I915_SYSTEM_MEMORY :
+						     system_memory(bops->fd);
 	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
-			 tiling, compression, 0, 0, I915_SYSTEM_MEMORY);
+			 tiling, compression, 0, 0, region);
 
 	intel_buf_set_ownership(buf, true);
 }
@@ -945,7 +969,7 @@ void intel_buf_init_in_region(struct buf_ops *bops,
 			      struct intel_buf *buf,
 			      int width, int height, int bpp, int alignment,
 			      uint32_t tiling, uint32_t compression,
-			      uint32_t region)
+			      uint64_t region)
 {
 	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
 			 tiling, compression, 0, 0, region);
@@ -1010,6 +1034,43 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
 			 req_tiling, compression, 0, 0, -1);
 }
 
+/**
+ * intel_buf_init_full
+ * @bops: pointer to buf_ops
+ * @handle: BO handle created by the caller
+ * @buf: pointer to intel_buf structure to be filled
+ * @width: surface width
+ * @height: surface height
+ * @bpp: bits-per-pixel (8 / 16 / 32 / 64)
+ * @alignment: alignment of the stride for linear surfaces
+ * @req_tiling: surface tiling
+ * @compression: surface compression type
+ * @size: real bo size
+ * @stride: bo stride
+ * @region: region
+ *
+ * Function configures BO handle within intel_buf structure passed by the caller
+ * (with all its metadata - width, height, ...). Useful if BO was created
+ * outside. Allows passing real size which caller is aware of.
+ *
+ * Note: intel_buf_close() can be used because intel_buf is aware it is not
+ * buffer owner so it won't close it underneath.
+ */
+void intel_buf_init_full(struct buf_ops *bops,
+			 uint32_t handle,
+			 struct intel_buf *buf,
+			 int width, int height,
+			 int bpp, int alignment,
+			 uint32_t req_tiling,
+			 uint32_t compression,
+			 uint64_t size,
+			 int stride,
+			 uint64_t region)
+{
+	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
+			 req_tiling, compression, size, stride, region);
+}
+
 /**
  * intel_buf_create
  * @bops: pointer to buf_ops
@@ -1084,6 +1145,20 @@ struct intel_buf *intel_buf_create_using_handle_and_size(struct buf_ops *bops,
 							 uint32_t compression,
 							 uint64_t size,
 							 int stride)
+{
+	return intel_buf_create_full(bops, handle, width, height, bpp, alignment,
+				     req_tiling, compression, size, stride, -1);
+}
+
+struct intel_buf *intel_buf_create_full(struct buf_ops *bops,
+					uint32_t handle,
+					int width, int height,
+					int bpp, int alignment,
+					uint32_t req_tiling,
+					uint32_t compression,
+					uint64_t size,
+					int stride,
+					uint64_t region)
 {
 	struct intel_buf *buf;
 
@@ -1093,12 +1168,11 @@ struct intel_buf *intel_buf_create_using_handle_and_size(struct buf_ops *bops,
 	igt_assert(buf);
 
 	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
-			 req_tiling, compression, size, stride, -1);
+			 req_tiling, compression, size, stride, region);
 
 	return buf;
 }
 
-
 /**
  * intel_buf_destroy
  * @buf: intel_buf
@@ -1420,8 +1494,24 @@ static struct buf_ops *__buf_ops_create(int fd, bool check_idempotency)
 
 	bops->fd = fd;
 	bops->intel_gen = generation;
-	igt_debug("generation: %d, supported tiles: 0x%02x\n",
-		  bops->intel_gen, bops->supported_tiles);
+	bops->driver = is_i915_device(fd) ? INTEL_DRIVER_I915 :
+					    is_xe_device(fd) ? INTEL_DRIVER_XE : 0;
+	igt_assert(bops->driver);
+	igt_debug("generation: %d, supported tiles: 0x%02x, driver: %s\n",
+		  bops->intel_gen, bops->supported_tiles,
+		  bops->driver == INTEL_DRIVER_I915 ? "i915" : "xe");
+
+	/* No tiling support in XE. */
+	if (bops->driver == INTEL_DRIVER_XE) {
+		bops->supported_hw_tiles = TILE_NONE;
+
+		bops->linear_to_x = copy_linear_to_x;
+		bops->x_to_linear = copy_x_to_linear;
+		bops->linear_to_y = copy_linear_to_y;
+		bops->y_to_linear = copy_y_to_linear;
+
+		return bops;
+	}
 
 	/*
 	 * Warning!
@@ -1569,6 +1659,19 @@ int buf_ops_get_fd(struct buf_ops *bops)
 	return bops->fd;
 }
 
+/**
+ * buf_ops_get_driver
+ * @bops: pointer to buf_ops
+ *
+ * Returns: intel driver enum value
+ */
+enum intel_driver buf_ops_get_driver(struct buf_ops *bops)
+{
+	igt_assert(bops);
+
+	return bops->driver;
+}
+
 /**
  * buf_ops_set_software_tiling
  * @bops: pointer to buf_ops
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 25b430739..0037548a3 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -43,6 +43,7 @@ struct intel_buf {
 	} addr;
 
 	uint64_t bo_size;
+	uint64_t region;
 
 	/* Tracking */
 	struct intel_bb *ibb;
@@ -109,6 +110,7 @@ struct buf_ops *buf_ops_create(int fd);
 struct buf_ops *buf_ops_create_with_selftest(int fd);
 void buf_ops_destroy(struct buf_ops *bops);
 int buf_ops_get_fd(struct buf_ops *bops);
+enum intel_driver buf_ops_get_driver(struct buf_ops *bops);
 
 bool buf_ops_set_software_tiling(struct buf_ops *bops,
 				 uint32_t tiling,
@@ -135,7 +137,7 @@ void intel_buf_init_in_region(struct buf_ops *bops,
 			      struct intel_buf *buf,
 			      int width, int height, int bpp, int alignment,
 			      uint32_t tiling, uint32_t compression,
-			      uint32_t region);
+			      uint64_t region);
 void intel_buf_close(struct buf_ops *bops, struct intel_buf *buf);
 
 void intel_buf_init_using_handle(struct buf_ops *bops,
@@ -143,6 +145,16 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
 				 struct intel_buf *buf,
 				 int width, int height, int bpp, int alignment,
 				 uint32_t req_tiling, uint32_t compression);
+void intel_buf_init_full(struct buf_ops *bops,
+			 uint32_t handle,
+			 struct intel_buf *buf,
+			 int width, int height,
+			 int bpp, int alignment,
+			 uint32_t req_tiling,
+			 uint32_t compression,
+			 uint64_t size,
+			 int stride,
+			 uint64_t region);
 
 struct intel_buf *intel_buf_create(struct buf_ops *bops,
 				   int width, int height,
@@ -164,6 +176,16 @@ struct intel_buf *intel_buf_create_using_handle_and_size(struct buf_ops *bops,
 							 uint32_t compression,
 							 uint64_t size,
 							 int stride);
+
+struct intel_buf *intel_buf_create_full(struct buf_ops *bops,
+					uint32_t handle,
+					int width, int height,
+					int bpp, int alignment,
+					uint32_t req_tiling,
+					uint32_t compression,
+					uint64_t size,
+					int stride,
+					uint64_t region);
 void intel_buf_destroy(struct intel_buf *buf);
 
 static inline void intel_buf_set_pxp(struct intel_buf *buf, bool new_pxp_state)
-- 
2.40.0

[igt-dev] [i-g-t V5 07/47] lib/intel_batchbuffer: Rename i915 -> fd as preparation step for xe

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Until now intel-bb was designed to handle i915 (relocations and
softpinning). We want to reuse it also for xe as softpinning
which requires allocator also unblocks this for vm_bind used
in xe.

This is preparation step which stops using i915 as internal fd
to avoid confusion.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
---
 lib/gpu_cmds.c           |   2 +-
 lib/intel_aux_pgtable.c  |   2 +-
 lib/intel_batchbuffer.c  | 116 +++++++++++++++++++--------------------
 lib/intel_batchbuffer.h  |  16 +++---
 tests/i915/gem_caching.c |   4 +-
 tests/i915/gem_pxp.c     |   2 +-
 6 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index cee81555d..afb26d299 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -251,7 +251,7 @@ gen7_fill_binding_table(struct intel_bb *ibb,
 {
 	uint32_t binding_table_offset;
 	uint32_t *binding_table;
-	uint32_t devid = intel_get_drm_devid(ibb->i915);
+	uint32_t devid = intel_get_drm_devid(ibb->fd);
 
 	intel_bb_ptr_align(ibb, 64);
 	binding_table_offset = intel_bb_offset(ibb);
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index 520568708..946ca60b9 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -481,7 +481,7 @@ intel_aux_pgtable_create(struct intel_bb *ibb,
 	intel_bb_add_intel_buf_with_alignment(ibb, pgt->buf,
 					      pgt->max_align, false);
 
-	pgt_map(ibb->i915, pgt);
+	pgt_map(ibb->fd, pgt);
 	pgt_populate_entries(pgt, bufs, buf_count);
 	pgt_unmap(pgt);
 
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index a4eb4c2bb..7dbd6dd58 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -828,7 +828,7 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
 
 /**
  * __intel_bb_create:
- * @i915: drm fd
+ * @fd: drm fd
  * @ctx: context id
  * @cfg: intel_ctx configuration, NULL for default context or legacy mode
  * @size: size of the batchbuffer
@@ -873,7 +873,7 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
  * Pointer the intel_bb, asserts on failure.
  */
 static struct intel_bb *
-__intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
+__intel_bb_create(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 		  uint32_t size, bool do_relocs,
 		  uint64_t start, uint64_t end,
 		  uint8_t allocator_type, enum allocator_strategy strategy)
@@ -883,8 +883,8 @@ __intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 
 	igt_assert(ibb);
 
-	ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
-	ibb->devid = intel_get_drm_devid(i915);
+	ibb->uses_full_ppgtt = gem_uses_full_ppgtt(fd);
+	ibb->devid = intel_get_drm_devid(fd);
 	ibb->gen = intel_gen(ibb->devid);
 
 	/*
@@ -900,16 +900,16 @@ __intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 	 * so we want kernel to not interfere with this.
 	 */
 	if (do_relocs)
-		ibb->allows_obj_alignment = gem_allows_obj_alignment(i915);
+		ibb->allows_obj_alignment = gem_allows_obj_alignment(fd);
 
 	/* Use safe start offset instead assuming 0x0 is safe */
-	start = max_t(uint64_t, start, gem_detect_safe_start_offset(i915));
+	start = max_t(uint64_t, start, gem_detect_safe_start_offset(fd));
 
 	/* if relocs are set we won't use an allocator */
 	if (do_relocs)
 		allocator_type = INTEL_ALLOCATOR_NONE;
 	else
-		ibb->allocator_handle = intel_allocator_open_full(i915, ctx,
+		ibb->allocator_handle = intel_allocator_open_full(fd, ctx,
 								  start, end,
 								  allocator_type,
 								  strategy, 0);
@@ -918,11 +918,11 @@ __intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 	ibb->allocator_start = start;
 	ibb->allocator_end = end;
 
-	ibb->i915 = i915;
+	ibb->fd = fd;
 	ibb->enforce_relocs = do_relocs;
-	ibb->handle = gem_create(i915, size);
+	ibb->handle = gem_create(fd, size);
 	ibb->size = size;
-	ibb->alignment = gem_detect_safe_alignment(i915);
+	ibb->alignment = gem_detect_safe_alignment(fd);
 	ibb->ctx = ctx;
 	ibb->vm_id = 0;
 	ibb->batch = calloc(1, size);
@@ -937,7 +937,7 @@ __intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 		memcpy(ibb->cfg, cfg, sizeof(*cfg));
 	}
 
-	ibb->gtt_size = gem_aperture_size(i915);
+	ibb->gtt_size = gem_aperture_size(fd);
 	if ((ibb->gtt_size - 1) >> 32)
 		ibb->supports_48b_address = true;
 
@@ -961,7 +961,7 @@ __intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 
 /**
  * intel_bb_create_full:
- * @i915: drm fd
+ * @fd: drm fd
  * @ctx: context
  * @cfg: intel_ctx configuration, NULL for default context or legacy mode
  * @size: size of the batchbuffer
@@ -980,19 +980,19 @@ __intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
  *
  * Pointer the intel_bb, asserts on failure.
  */
-struct intel_bb *intel_bb_create_full(int i915, uint32_t ctx,
+struct intel_bb *intel_bb_create_full(int fd, uint32_t ctx,
 				      const intel_ctx_cfg_t *cfg, uint32_t size,
 				      uint64_t start, uint64_t end,
 				      uint8_t allocator_type,
 				      enum allocator_strategy strategy)
 {
-	return __intel_bb_create(i915, ctx, cfg, size, false, start, end,
+	return __intel_bb_create(fd, ctx, cfg, size, false, start, end,
 				 allocator_type, strategy);
 }
 
 /**
  * intel_bb_create_with_allocator:
- * @i915: drm fd
+ * @fd: drm fd
  * @ctx: context
  * @cfg: intel_ctx configuration, NULL for default context or legacy mode
  * @size: size of the batchbuffer
@@ -1006,18 +1006,18 @@ struct intel_bb *intel_bb_create_full(int i915, uint32_t ctx,
  *
  * Pointer the intel_bb, asserts on failure.
  */
-struct intel_bb *intel_bb_create_with_allocator(int i915, uint32_t ctx,
+struct intel_bb *intel_bb_create_with_allocator(int fd, uint32_t ctx,
 						const intel_ctx_cfg_t *cfg,
 						uint32_t size,
 						uint8_t allocator_type)
 {
-	return __intel_bb_create(i915, ctx, cfg, size, false, 0, 0,
+	return __intel_bb_create(fd, ctx, cfg, size, false, 0, 0,
 				 allocator_type, ALLOC_STRATEGY_HIGH_TO_LOW);
 }
 
-static bool aux_needs_softpin(int i915)
+static bool aux_needs_softpin(int fd)
 {
-	return intel_gen(intel_get_drm_devid(i915)) >= 12;
+	return intel_gen(intel_get_drm_devid(fd)) >= 12;
 }
 
 static bool has_ctx_cfg(struct intel_bb *ibb)
@@ -1027,7 +1027,7 @@ static bool has_ctx_cfg(struct intel_bb *ibb)
 
 /**
  * intel_bb_create:
- * @i915: drm fd
+ * @fd: drm fd
  * @size: size of the batchbuffer
  *
  * Creates bb with default context.
@@ -1045,19 +1045,19 @@ static bool has_ctx_cfg(struct intel_bb *ibb)
  * connection to it inside intel_bb is not valid anymore.
  * Trying to use it leads to catastrofic errors.
  */
-struct intel_bb *intel_bb_create(int i915, uint32_t size)
+struct intel_bb *intel_bb_create(int fd, uint32_t size)
 {
-	bool relocs = gem_has_relocations(i915);
+	bool relocs = gem_has_relocations(fd);
 
-	return __intel_bb_create(i915, 0, NULL, size,
-				 relocs && !aux_needs_softpin(i915), 0, 0,
+	return __intel_bb_create(fd, 0, NULL, size,
+				 relocs && !aux_needs_softpin(fd), 0, 0,
 				 INTEL_ALLOCATOR_SIMPLE,
 				 ALLOC_STRATEGY_HIGH_TO_LOW);
 }
 
 /**
  * intel_bb_create_with_context:
- * @i915: drm fd
+ * @fd: drm fd
  * @ctx: context id
  * @cfg: intel_ctx configuration, NULL for default context or legacy mode
  * @size: size of the batchbuffer
@@ -1070,20 +1070,20 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
  * Pointer the intel_bb, asserts on failure.
  */
 struct intel_bb *
-intel_bb_create_with_context(int i915, uint32_t ctx,
+intel_bb_create_with_context(int fd, uint32_t ctx,
 			     const intel_ctx_cfg_t *cfg, uint32_t size)
 {
-	bool relocs = gem_has_relocations(i915);
+	bool relocs = gem_has_relocations(fd);
 
-	return __intel_bb_create(i915, ctx, cfg, size,
-				 relocs && !aux_needs_softpin(i915), 0, 0,
+	return __intel_bb_create(fd, ctx, cfg, size,
+				 relocs && !aux_needs_softpin(fd), 0, 0,
 				 INTEL_ALLOCATOR_SIMPLE,
 				 ALLOC_STRATEGY_HIGH_TO_LOW);
 }
 
 /**
  * intel_bb_create_with_relocs:
- * @i915: drm fd
+ * @fd: drm fd
  * @size: size of the batchbuffer
  *
  * Creates bb which will disable passing addresses.
@@ -1093,17 +1093,17 @@ intel_bb_create_with_context(int i915, uint32_t ctx,
  *
  * Pointer the intel_bb, asserts on failure.
  */
-struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
+struct intel_bb *intel_bb_create_with_relocs(int fd, uint32_t size)
 {
-	igt_require(gem_has_relocations(i915));
+	igt_require(gem_has_relocations(fd));
 
-	return __intel_bb_create(i915, 0, NULL, size, true, 0, 0,
+	return __intel_bb_create(fd, 0, NULL, size, true, 0, 0,
 				 INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
 }
 
 /**
  * intel_bb_create_with_relocs_and_context:
- * @i915: drm fd
+ * @fd: drm fd
  * @ctx: context
  * @cfg: intel_ctx configuration, NULL for default context or legacy mode
  * @size: size of the batchbuffer
@@ -1116,19 +1116,19 @@ struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
  * Pointer the intel_bb, asserts on failure.
  */
 struct intel_bb *
-intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx,
+intel_bb_create_with_relocs_and_context(int fd, uint32_t ctx,
 					const intel_ctx_cfg_t *cfg,
 					uint32_t size)
 {
-	igt_require(gem_has_relocations(i915));
+	igt_require(gem_has_relocations(fd));
 
-	return __intel_bb_create(i915, ctx, cfg, size, true, 0, 0,
+	return __intel_bb_create(fd, ctx, cfg, size, true, 0, 0,
 				 INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
 }
 
 /**
  * intel_bb_create_no_relocs:
- * @i915: drm fd
+ * @fd: drm fd
  * @size: size of the batchbuffer
  *
  * Creates bb with disabled relocations.
@@ -1138,11 +1138,11 @@ intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx,
  *
  * Pointer the intel_bb, asserts on failure.
  */
-struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size)
+struct intel_bb *intel_bb_create_no_relocs(int fd, uint32_t size)
 {
-	igt_require(gem_uses_full_ppgtt(i915));
+	igt_require(gem_uses_full_ppgtt(fd));
 
-	return __intel_bb_create(i915, 0, NULL, size, false, 0, 0,
+	return __intel_bb_create(fd, 0, NULL, size, false, 0, 0,
 				 INTEL_ALLOCATOR_SIMPLE,
 				 ALLOC_STRATEGY_HIGH_TO_LOW);
 }
@@ -1217,7 +1217,7 @@ void intel_bb_destroy(struct intel_bb *ibb)
 		intel_allocator_free(ibb->allocator_handle, ibb->handle);
 		intel_allocator_close(ibb->allocator_handle);
 	}
-	gem_close(ibb->i915, ibb->handle);
+	gem_close(ibb->fd, ibb->handle);
 
 	if (ibb->fence >= 0)
 		close(ibb->fence);
@@ -1277,8 +1277,8 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
 		intel_bb_remove_object(ibb, ibb->handle, ibb->batch_offset,
 				       ibb->size);
 
-	gem_close(ibb->i915, ibb->handle);
-	ibb->handle = gem_create(ibb->i915, ibb->size);
+	gem_close(ibb->fd, ibb->handle);
+	ibb->handle = gem_create(ibb->fd, ibb->size);
 
 	/* Keep address for bb in reloc mode and RANDOM allocator */
 	if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE)
@@ -1325,7 +1325,7 @@ int intel_bb_sync(struct intel_bb *ibb)
 void intel_bb_print(struct intel_bb *ibb)
 {
 	igt_info("drm fd: %d, gen: %d, devid: %u, debug: %d\n",
-		 ibb->i915, ibb->gen, ibb->devid, ibb->debug);
+		 ibb->fd, ibb->gen, ibb->devid, ibb->debug);
 	igt_info("handle: %u, size: %u, batch: %p, ptr: %p\n",
 		 ibb->handle, ibb->size, ibb->batch, ibb->ptr);
 	igt_info("gtt_size: %" PRIu64 ", supports 48bit: %d\n",
@@ -1350,7 +1350,7 @@ void intel_bb_dump(struct intel_bb *ibb, const char *filename)
 	FILE *out;
 	void *ptr;
 
-	ptr = gem_mmap__device_coherent(ibb->i915, ibb->handle, 0, ibb->size,
+	ptr = gem_mmap__device_coherent(ibb->fd, ibb->handle, 0, ibb->size,
 					PROT_READ);
 	out = fopen(filename, "wb");
 	igt_assert(out);
@@ -1524,7 +1524,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 	igt_assert(is_power_of_two(alignment));
 
 	object = __add_to_cache(ibb, handle);
-	alignment = max_t(uint64_t, alignment, gem_detect_safe_alignment(ibb->i915));
+	alignment = max_t(uint64_t, alignment, gem_detect_safe_alignment(ibb->fd));
 	__add_to_objects(ibb, object);
 
 	/*
@@ -1999,7 +1999,7 @@ static void intel_bb_dump_execbuf(struct intel_bb *ibb,
 	uint64_t address;
 
 	igt_debug("execbuf [pid: %ld, fd: %d, ctx: %u]\n",
-		  (long) getpid(), ibb->i915, ibb->ctx);
+		  (long) getpid(), ibb->fd, ibb->ctx);
 	igt_debug("execbuf batch len: %u, start offset: 0x%x, "
 		  "DR1: 0x%x, DR4: 0x%x, "
 		  "num clip: %u, clipptr: 0x%llx, "
@@ -2160,7 +2160,7 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 	ibb->objects[0]->handle = ibb->handle;
 	ibb->objects[0]->offset = ibb->batch_offset;
 
-	gem_write(ibb->i915, ibb->handle, 0, ibb->batch, ibb->size);
+	gem_write(ibb->fd, ibb->handle, 0, ibb->batch, ibb->size);
 
 	memset(&execbuf, 0, sizeof(execbuf));
 	objects = create_objects_array(ibb);
@@ -2179,7 +2179,7 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 	/* For debugging on CI, remove in final series */
 	intel_bb_dump_execbuf(ibb, &execbuf);
 
-	ret = __gem_execbuf_wr(ibb->i915, &execbuf);
+	ret = __gem_execbuf_wr(ibb->fd, &execbuf);
 	if (ret) {
 		intel_bb_dump_execbuf(ibb, &execbuf);
 		free(objects);
@@ -2409,13 +2409,13 @@ uint32_t intel_bb_copy_data(struct intel_bb *ibb,
  */
 void intel_bb_blit_start(struct intel_bb *ibb, uint32_t flags)
 {
-	if (blt_has_xy_src_copy(ibb->i915))
+	if (blt_has_xy_src_copy(ibb->fd))
 		intel_bb_out(ibb, XY_SRC_COPY_BLT_CMD |
 			     XY_SRC_COPY_BLT_WRITE_ALPHA |
 			     XY_SRC_COPY_BLT_WRITE_RGB |
 			     flags |
 			     (6 + 2 * (ibb->gen >= 8)));
-	else if (blt_has_fast_copy(ibb->i915))
+	else if (blt_has_fast_copy(ibb->fd))
 		intel_bb_out(ibb, XY_FAST_COPY_BLT | flags);
 	else
 		igt_assert_f(0, "No supported blit command found\n");
@@ -2456,9 +2456,9 @@ void intel_bb_emit_blt_copy(struct intel_bb *ibb,
 
 	if (gen >= 4 && src->tiling != I915_TILING_NONE) {
 		src_pitch /= 4;
-		if (blt_has_xy_src_copy(ibb->i915))
+		if (blt_has_xy_src_copy(ibb->fd))
 			cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
-		else if (blt_has_fast_copy(ibb->i915))
+		else if (blt_has_fast_copy(ibb->fd))
 			cmd_bits |= fast_copy_dword0(src->tiling, dst->tiling);
 		else
 			igt_assert_f(0, "No supported blit command found\n");
@@ -2466,7 +2466,7 @@ void intel_bb_emit_blt_copy(struct intel_bb *ibb,
 
 	if (gen >= 4 && dst->tiling != I915_TILING_NONE) {
 		dst_pitch /= 4;
-		if (blt_has_xy_src_copy(ibb->i915))
+		if (blt_has_xy_src_copy(ibb->fd))
 			cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
 		else
 			cmd_bits |= fast_copy_dword0(src->tiling, dst->tiling);
@@ -2480,7 +2480,7 @@ void intel_bb_emit_blt_copy(struct intel_bb *ibb,
 	CHECK_RANGE(src_pitch); CHECK_RANGE(dst_pitch);
 
 	br13_bits = 0;
-	if (blt_has_xy_src_copy(ibb->i915)) {
+	if (blt_has_xy_src_copy(ibb->fd)) {
 		switch (bpp) {
 		case 8:
 			break;
@@ -2496,7 +2496,7 @@ void intel_bb_emit_blt_copy(struct intel_bb *ibb,
 			igt_fail(IGT_EXIT_FAILURE);
 		}
 	} else {
-		br13_bits = fast_copy_dword1(ibb->i915, src->tiling, dst->tiling, bpp);
+		br13_bits = fast_copy_dword1(ibb->fd, src->tiling, dst->tiling, bpp);
 	}
 
 	if ((src->tiling | dst->tiling) >= I915_TILING_Y) {
@@ -2631,7 +2631,7 @@ static void __intel_bb_reinit_alloc(struct intel_bb *ibb)
 	if (ibb->allocator_type == INTEL_ALLOCATOR_NONE)
 		return;
 
-	ibb->allocator_handle = intel_allocator_open_full(ibb->i915, ibb->ctx,
+	ibb->allocator_handle = intel_allocator_open_full(ibb->fd, ibb->ctx,
 							  ibb->allocator_start, ibb->allocator_end,
 							  ibb->allocator_type,
 							  ibb->allocator_strategy,
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 10e412660..4978b6fb2 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -246,7 +246,7 @@ struct intel_bb {
 	uint8_t allocator_type;
 	enum allocator_strategy allocator_strategy;
 
-	int i915;
+	int fd;
 	unsigned int gen;
 	bool debug;
 	bool dump_base64;
@@ -299,21 +299,21 @@ struct intel_bb {
 };
 
 struct intel_bb *
-intel_bb_create_full(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
+intel_bb_create_full(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 		     uint32_t size, uint64_t start, uint64_t end,
 		     uint8_t allocator_type, enum allocator_strategy strategy);
 struct intel_bb *
-intel_bb_create_with_allocator(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
+intel_bb_create_with_allocator(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 			       uint32_t size, uint8_t allocator_type);
-struct intel_bb *intel_bb_create(int i915, uint32_t size);
+struct intel_bb *intel_bb_create(int fd, uint32_t size);
 struct intel_bb *
-intel_bb_create_with_context(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
+intel_bb_create_with_context(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 			     uint32_t size);
-struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
+struct intel_bb *intel_bb_create_with_relocs(int fd, uint32_t size);
 struct intel_bb *
-intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx,
+intel_bb_create_with_relocs_and_context(int fd, uint32_t ctx,
 					const intel_ctx_cfg_t *cfg, uint32_t size);
-struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size);
+struct intel_bb *intel_bb_create_no_relocs(int fd, uint32_t size);
 void intel_bb_destroy(struct intel_bb *ibb);
 
 /* make it safe to use intel_allocator after failed test */
diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
index b6ecd8346..6e944f0ac 100644
--- a/tests/i915/gem_caching.c
+++ b/tests/i915/gem_caching.c
@@ -83,7 +83,7 @@ copy_bo(struct intel_bb *ibb, struct intel_buf *src, struct intel_buf *dst)
 	intel_bb_add_intel_buf(ibb, src, false);
 	intel_bb_add_intel_buf(ibb, dst, true);
 
-	if (blt_has_xy_src_copy(ibb->i915)) {
+	if (blt_has_xy_src_copy(ibb->fd)) {
 		intel_bb_out(ibb,
 			     XY_SRC_COPY_BLT_CMD |
 			     XY_SRC_COPY_BLT_WRITE_ALPHA |
@@ -93,7 +93,7 @@ copy_bo(struct intel_bb *ibb, struct intel_buf *src, struct intel_buf *dst)
 		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 			     (0xcc << 16) | /* copy ROP */
 			     4096);
-	} else if (blt_has_fast_copy(ibb->i915)) {
+	} else if (blt_has_fast_copy(ibb->fd)) {
 		intel_bb_out(ibb, XY_FAST_COPY_BLT);
 		intel_bb_out(ibb, XY_FAST_COPY_COLOR_DEPTH_32 | 4096);
 	} else {
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index af657d0e1..2f27abd58 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -809,7 +809,7 @@ static int gem_execbuf_flush_store_dw(int i915, struct intel_bb *ibb, uint32_t c
 	ret = __intel_bb_exec(ibb, intel_bb_offset(ibb),
 				  I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
 	if (ret == 0) {
-		gem_sync(ibb->i915, fence->handle);
+		gem_sync(ibb->fd, fence->handle);
 		assert_pipectl_storedw_done(i915, fence->handle);
 	}
 	return ret;
-- 
2.40.0

[igt-dev] [i-g-t V5 08/47] lib/intel_batchbuffer: Reacquire offset for reloc allocator in reset path

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

On reset path we recreate bo for batch (to avoid stalls) so we should
reacquire the offset too. At the moment simple allocator will return
same offset (so unfortunately we'll stall), but for reloc allocator
we'll get new one (so we avoid stall).

I've noticed this is missing during xe_intel_bb test, where on reloc
I noticed unexpected result (direct consequence of using same offset
which pointed to old batch, not new one).

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_batchbuffer.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 7dbd6dd58..99b0b6158 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1280,8 +1280,9 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
 	gem_close(ibb->fd, ibb->handle);
 	ibb->handle = gem_create(ibb->fd, ibb->size);
 
-	/* Keep address for bb in reloc mode and RANDOM allocator */
-	if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE)
+	/* Reacquire offset for RELOC and SIMPLE */
+	if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE ||
+	    ibb->allocator_type == INTEL_ALLOCATOR_RELOC)
 		ibb->batch_offset = __intel_bb_get_offset(ibb,
 							  ibb->handle,
 							  ibb->size,
-- 
2.40.0

[igt-dev] [i-g-t V5 09/47] lib/intel_batchbuffer: Update intel-bb docs

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

After RANDOM pseudo-allocator was removed and RELOC allocator becomed
stateful docs stays intact and documents old code. Fix this before
adding xe code.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_batchbuffer.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 99b0b6158..306b7650e 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -836,7 +836,7 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
  * @allocator_type: allocator type, must be INTEL_ALLOCATOR_NONE for relocations
  *
  * intel-bb assumes it will work in one of two modes - with relocations or
- * with using allocator (currently RANDOM and SIMPLE are implemented).
+ * with using allocator (currently RELOC and SIMPLE are implemented).
  * Some description is required to describe how they maintain the addresses.
  *
  * Before entering into each scenarios generic rule is intel-bb keeps objects
@@ -854,10 +854,10 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
  *
  * This mode is valid only for ppgtt. Addresses are acquired from allocator
  * and softpinned. intel-bb cache must be then coherent with allocator
- * (simple is coherent, random is not due to fact we don't keep its state).
+ * (simple is coherent, reloc partially [doesn't support address reservation]).
  * When we do intel-bb reset with purging cache it has to reacquire addresses
  * from allocator (allocator should return same address - what is true for
- * simple allocator and false for random as mentioned before).
+ * simple and reloc allocators).
  *
  * If we do reset without purging caches we use addresses from intel-bb cache
  * during execbuf objects construction.
@@ -967,7 +967,7 @@ __intel_bb_create(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
  * @size: size of the batchbuffer
  * @start: allocator vm start address
  * @end: allocator vm start address
- * @allocator_type: allocator type, SIMPLE, RANDOM, ...
+ * @allocator_type: allocator type, SIMPLE, RELOC, ...
  * @strategy: allocation strategy
  *
  * Creates bb with context passed in @ctx, size in @size and allocator type
-- 
2.40.0

[igt-dev] [i-g-t V5 10/47] lib/intel_batchbuffer: Add Xe support in intel-bb

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Intention of creating intel-bb was to replace libdrm for i915.
Due to many code relies on it (kms for example) most rational way
is to extend and add Xe path to it.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
 lib/intel_batchbuffer.c | 336 ++++++++++++++++++++++++++++++++--------
 lib/intel_batchbuffer.h |   6 +
 2 files changed, 281 insertions(+), 61 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 306b7650e..38ad792e5 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -28,18 +28,22 @@
 #include <search.h>
 #include <glib.h>
 
+#include "gpgpu_fill.h"
+#include "huc_copy.h"
 #include "i915/gem_create.h"
+#include "i915/gem_mman.h"
+#include "i915/i915_blt.h"
+#include "igt_aux.h"
+#include "igt_syncobj.h"
 #include "intel_batchbuffer.h"
 #include "intel_bufops.h"
 #include "intel_chipset.h"
 #include "media_fill.h"
 #include "media_spin.h"
-#include "i915/gem_mman.h"
-#include "veboxcopy.h"
 #include "sw_sync.h"
-#include "gpgpu_fill.h"
-#include "huc_copy.h"
-#include "i915/i915_blt.h"
+#include "veboxcopy.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
 
 #define BCS_SWCTRL 0x22200
 #define BCS_SRC_Y (1 << 0)
@@ -828,9 +832,10 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
 
 /**
  * __intel_bb_create:
- * @fd: drm fd
+ * @fd: drm fd - i915 or xe
  * @ctx: context id
- * @cfg: intel_ctx configuration, NULL for default context or legacy mode
+ * @cfg: for i915 intel_ctx configuration, NULL for default context or legacy mode,
+ *       unused for xe
  * @size: size of the batchbuffer
  * @do_relocs: use relocations or allocator
  * @allocator_type: allocator type, must be INTEL_ALLOCATOR_NONE for relocations
@@ -842,7 +847,7 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
  * Before entering into each scenarios generic rule is intel-bb keeps objects
  * and their offsets in the internal cache and reuses in subsequent execs.
  *
- * 1. intel-bb with relocations
+ * 1. intel-bb with relocations (i915 only)
  *
  * Creating new intel-bb adds handle to cache implicitly and sets its address
  * to 0. Objects added to intel-bb later also have address 0 set for first run.
@@ -850,11 +855,12 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
  * works in reloc mode addresses are only suggestion to the driver and we
  * cannot be sure they won't change at next exec.
  *
- * 2. with allocator
+ * 2. with allocator (i915 or xe)
  *
  * This mode is valid only for ppgtt. Addresses are acquired from allocator
- * and softpinned. intel-bb cache must be then coherent with allocator
- * (simple is coherent, reloc partially [doesn't support address reservation]).
+ * and softpinned (i915) or vm-binded (xe). intel-bb cache must be then
+ * coherent with allocator (simple is coherent, reloc partially [doesn't
+ * support address reservation]).
  * When we do intel-bb reset with purging cache it has to reacquire addresses
  * from allocator (allocator should return same address - what is true for
  * simple and reloc allocators).
@@ -883,48 +889,75 @@ __intel_bb_create(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 
 	igt_assert(ibb);
 
-	ibb->uses_full_ppgtt = gem_uses_full_ppgtt(fd);
 	ibb->devid = intel_get_drm_devid(fd);
 	ibb->gen = intel_gen(ibb->devid);
+	ibb->ctx = ctx;
+
+	ibb->fd = fd;
+	ibb->driver = is_i915_device(fd) ? INTEL_DRIVER_I915 :
+					   is_xe_device(fd) ? INTEL_DRIVER_XE : 0;
+	igt_assert(ibb->driver);
 
 	/*
 	 * If we don't have full ppgtt driver can change our addresses
 	 * so allocator is useless in this case. Just enforce relocations
 	 * for such gens and don't use allocator at all.
 	 */
-	if (!ibb->uses_full_ppgtt)
-		do_relocs = true;
+	if (ibb->driver == INTEL_DRIVER_I915) {
+		ibb->uses_full_ppgtt = gem_uses_full_ppgtt(fd);
+		ibb->alignment = gem_detect_safe_alignment(fd);
+		ibb->gtt_size = gem_aperture_size(fd);
+		ibb->handle = gem_create(fd, size);
 
-	/*
-	 * For softpin mode allocator has full control over offsets allocation
-	 * so we want kernel to not interfere with this.
-	 */
-	if (do_relocs)
-		ibb->allows_obj_alignment = gem_allows_obj_alignment(fd);
+		if (!ibb->uses_full_ppgtt)
+			do_relocs = true;
+
+		/*
+		 * For softpin mode allocator has full control over offsets allocation
+		 * so we want kernel to not interfere with this.
+		 */
+		if (do_relocs) {
+			ibb->allows_obj_alignment = gem_allows_obj_alignment(fd);
+			allocator_type = INTEL_ALLOCATOR_NONE;
+		} else {
+			/* Use safe start offset instead assuming 0x0 is safe */
+			start = max_t(uint64_t, start, gem_detect_safe_start_offset(fd));
+
+			/* if relocs are set we won't use an allocator */
+			ibb->allocator_handle =
+				intel_allocator_open_full(fd, ctx, start, end,
+							  allocator_type,
+							  strategy, 0);
+		}
 
-	/* Use safe start offset instead assuming 0x0 is safe */
-	start = max_t(uint64_t, start, gem_detect_safe_start_offset(fd));
+		ibb->vm_id = 0;
+	} else {
+		igt_assert(!do_relocs);
+
+		ibb->alignment = xe_get_default_alignment(fd);
+		size = ALIGN(size, ibb->alignment);
+		ibb->handle = xe_bo_create_flags(fd, 0, size, vram_if_possible(fd, 0));
+		ibb->gtt_size = 1ull << xe_va_bits(fd);
+
+		if (!ctx)
+			ctx = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+
+		ibb->uses_full_ppgtt = true;
+		ibb->allocator_handle =
+			intel_allocator_open_full(fd, ctx, start, end,
+						  allocator_type, strategy,
+						  ibb->alignment);
+		ibb->vm_id = ctx;
+		ibb->last_engine = ~0U;
+	}
 
-	/* if relocs are set we won't use an allocator */
-	if (do_relocs)
-		allocator_type = INTEL_ALLOCATOR_NONE;
-	else
-		ibb->allocator_handle = intel_allocator_open_full(fd, ctx,
-								  start, end,
-								  allocator_type,
-								  strategy, 0);
 	ibb->allocator_type = allocator_type;
 	ibb->allocator_strategy = strategy;
 	ibb->allocator_start = start;
 	ibb->allocator_end = end;
-
-	ibb->fd = fd;
 	ibb->enforce_relocs = do_relocs;
-	ibb->handle = gem_create(fd, size);
+
 	ibb->size = size;
-	ibb->alignment = gem_detect_safe_alignment(fd);
-	ibb->ctx = ctx;
-	ibb->vm_id = 0;
 	ibb->batch = calloc(1, size);
 	igt_assert(ibb->batch);
 	ibb->ptr = ibb->batch;
@@ -937,7 +970,6 @@ __intel_bb_create(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 		memcpy(ibb->cfg, cfg, sizeof(*cfg));
 	}
 
-	ibb->gtt_size = gem_aperture_size(fd);
 	if ((ibb->gtt_size - 1) >> 32)
 		ibb->supports_48b_address = true;
 
@@ -961,7 +993,7 @@ __intel_bb_create(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
 
 /**
  * intel_bb_create_full:
- * @fd: drm fd
+ * @fd: drm fd - i915 or xe
  * @ctx: context
  * @cfg: intel_ctx configuration, NULL for default context or legacy mode
  * @size: size of the batchbuffer
@@ -992,7 +1024,7 @@ struct intel_bb *intel_bb_create_full(int fd, uint32_t ctx,
 
 /**
  * intel_bb_create_with_allocator:
- * @fd: drm fd
+ * @fd: drm fd - i915 or xe
  * @ctx: context
  * @cfg: intel_ctx configuration, NULL for default context or legacy mode
  * @size: size of the batchbuffer
@@ -1027,7 +1059,7 @@ static bool has_ctx_cfg(struct intel_bb *ibb)
 
 /**
  * intel_bb_create:
- * @fd: drm fd
+ * @fd: drm fd - i915 or xe
  * @size: size of the batchbuffer
  *
  * Creates bb with default context.
@@ -1047,7 +1079,7 @@ static bool has_ctx_cfg(struct intel_bb *ibb)
  */
 struct intel_bb *intel_bb_create(int fd, uint32_t size)
 {
-	bool relocs = gem_has_relocations(fd);
+	bool relocs = is_i915_device(fd) && gem_has_relocations(fd);
 
 	return __intel_bb_create(fd, 0, NULL, size,
 				 relocs && !aux_needs_softpin(fd), 0, 0,
@@ -1057,7 +1089,7 @@ struct intel_bb *intel_bb_create(int fd, uint32_t size)
 
 /**
  * intel_bb_create_with_context:
- * @fd: drm fd
+ * @fd: drm fd - i915 or xe
  * @ctx: context id
  * @cfg: intel_ctx configuration, NULL for default context or legacy mode
  * @size: size of the batchbuffer
@@ -1073,7 +1105,7 @@ struct intel_bb *
 intel_bb_create_with_context(int fd, uint32_t ctx,
 			     const intel_ctx_cfg_t *cfg, uint32_t size)
 {
-	bool relocs = gem_has_relocations(fd);
+	bool relocs = is_i915_device(fd) && gem_has_relocations(fd);
 
 	return __intel_bb_create(fd, ctx, cfg, size,
 				 relocs && !aux_needs_softpin(fd), 0, 0,
@@ -1083,7 +1115,7 @@ intel_bb_create_with_context(int fd, uint32_t ctx,
 
 /**
  * intel_bb_create_with_relocs:
- * @fd: drm fd
+ * @fd: drm fd - i915
  * @size: size of the batchbuffer
  *
  * Creates bb which will disable passing addresses.
@@ -1095,7 +1127,7 @@ intel_bb_create_with_context(int fd, uint32_t ctx,
  */
 struct intel_bb *intel_bb_create_with_relocs(int fd, uint32_t size)
 {
-	igt_require(gem_has_relocations(fd));
+	igt_require(is_i915_device(fd) && gem_has_relocations(fd));
 
 	return __intel_bb_create(fd, 0, NULL, size, true, 0, 0,
 				 INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
@@ -1103,7 +1135,7 @@ struct intel_bb *intel_bb_create_with_relocs(int fd, uint32_t size)
 
 /**
  * intel_bb_create_with_relocs_and_context:
- * @fd: drm fd
+ * @fd: drm fd - i915
  * @ctx: context
  * @cfg: intel_ctx configuration, NULL for default context or legacy mode
  * @size: size of the batchbuffer
@@ -1120,7 +1152,7 @@ intel_bb_create_with_relocs_and_context(int fd, uint32_t ctx,
 					const intel_ctx_cfg_t *cfg,
 					uint32_t size)
 {
-	igt_require(gem_has_relocations(fd));
+	igt_require(is_i915_device(fd) && gem_has_relocations(fd));
 
 	return __intel_bb_create(fd, ctx, cfg, size, true, 0, 0,
 				 INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
@@ -1221,12 +1253,76 @@ void intel_bb_destroy(struct intel_bb *ibb)
 
 	if (ibb->fence >= 0)
 		close(ibb->fence);
+	if (ibb->engine_syncobj)
+		syncobj_destroy(ibb->fd, ibb->engine_syncobj);
+	if (ibb->vm_id && !ibb->ctx)
+		xe_vm_destroy(ibb->fd, ibb->vm_id);
 
 	free(ibb->batch);
 	free(ibb->cfg);
 	free(ibb);
 }
 
+static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(struct intel_bb *ibb,
+						   uint32_t op, uint32_t region)
+{
+	struct drm_i915_gem_exec_object2 **objects = ibb->objects;
+	struct drm_xe_vm_bind_op *bind_ops, *ops;
+	bool set_obj = (op & 0xffff) == XE_VM_BIND_OP_MAP;
+
+	bind_ops = calloc(ibb->num_objects, sizeof(*bind_ops));
+	igt_assert(bind_ops);
+
+	igt_debug("bind_ops: %s\n", set_obj ? "MAP" : "UNMAP");
+	for (int i = 0; i < ibb->num_objects; i++) {
+		ops = &bind_ops[i];
+
+		if (set_obj)
+			ops->obj = objects[i]->handle;
+
+		ops->op = op;
+		ops->obj_offset = 0;
+		ops->addr = objects[i]->offset;
+		ops->range = objects[i]->rsvd1;
+		ops->region = region;
+
+		igt_debug("  [%d]: handle: %u, offset: %llx, size: %llx\n",
+			  i, ops->obj, (long long)ops->addr, (long long)ops->range);
+	}
+
+	return bind_ops;
+}
+
+static void __unbind_xe_objects(struct intel_bb *ibb)
+{
+	struct drm_xe_sync syncs[2] = {
+		{ .flags = DRM_XE_SYNC_SYNCOBJ },
+		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+	};
+	int ret;
+
+	syncs[0].handle = ibb->engine_syncobj;
+	syncs[1].handle = syncobj_create(ibb->fd, 0);
+
+	if (ibb->num_objects > 1) {
+		struct drm_xe_vm_bind_op *bind_ops;
+		uint32_t op = XE_VM_BIND_OP_UNMAP | XE_VM_BIND_FLAG_ASYNC;
+
+		bind_ops = xe_alloc_bind_ops(ibb, op, 0);
+		xe_vm_bind_array(ibb->fd, ibb->vm_id, 0, bind_ops,
+				 ibb->num_objects, syncs, 2);
+		free(bind_ops);
+	} else {
+		xe_vm_unbind_async(ibb->fd, ibb->vm_id, 0, 0,
+				   ibb->batch_offset, ibb->size, syncs, 2);
+	}
+	ret = syncobj_wait_err(ibb->fd, &syncs[1].handle, 1, INT64_MAX, 0);
+	igt_assert_eq(ret, 0);
+	syncobj_destroy(ibb->fd, syncs[1].handle);
+
+	ibb->xe_bound = false;
+}
+
 /*
  * intel_bb_reset:
  * @ibb: pointer to intel_bb
@@ -1258,6 +1354,9 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
 	for (i = 0; i < ibb->num_objects; i++)
 		ibb->objects[i]->flags &= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
 
+	if (is_xe_device(ibb->fd) && ibb->xe_bound)
+		__unbind_xe_objects(ibb);
+
 	__intel_bb_destroy_relocations(ibb);
 	__intel_bb_destroy_objects(ibb);
 	__reallocate_objects(ibb);
@@ -1278,7 +1377,11 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
 				       ibb->size);
 
 	gem_close(ibb->fd, ibb->handle);
-	ibb->handle = gem_create(ibb->fd, ibb->size);
+	if (ibb->driver == INTEL_DRIVER_I915)
+		ibb->handle = gem_create(ibb->fd, ibb->size);
+	else
+		ibb->handle = xe_bo_create_flags(ibb->fd, 0, ibb->size,
+						 vram_if_possible(ibb->fd, 0));
 
 	/* Reacquire offset for RELOC and SIMPLE */
 	if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE ||
@@ -1305,13 +1408,19 @@ int intel_bb_sync(struct intel_bb *ibb)
 {
 	int ret;
 
-	if (ibb->fence < 0)
+	if (ibb->fence < 0 && !ibb->engine_syncobj)
 		return 0;
 
-	ret = sync_fence_wait(ibb->fence, -1);
-	if (ret == 0) {
-		close(ibb->fence);
-		ibb->fence = -1;
+	if (ibb->fence >= 0) {
+		ret = sync_fence_wait(ibb->fence, -1);
+		if (ret == 0) {
+			close(ibb->fence);
+			ibb->fence = -1;
+		}
+	} else {
+		igt_assert_neq(ibb->engine_syncobj, 0);
+		ret = syncobj_wait_err(ibb->fd, &ibb->engine_syncobj,
+				       1, INT64_MAX, 0);
 	}
 
 	return ret;
@@ -1502,7 +1611,7 @@ static void __remove_from_objects(struct intel_bb *ibb,
 }
 
 /**
- * intel_bb_add_object:
+ * __intel_bb_add_object:
  * @ibb: pointer to intel_bb
  * @handle: which handle to add to objects array
  * @size: object size
@@ -1514,9 +1623,9 @@ static void __remove_from_objects(struct intel_bb *ibb,
  * in the object tree. When object is a render target it has to
  * be marked with EXEC_OBJECT_WRITE flag.
  */
-struct drm_i915_gem_exec_object2 *
-intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
-		    uint64_t offset, uint64_t alignment, bool write)
+static struct drm_i915_gem_exec_object2 *
+__intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
+		      uint64_t offset, uint64_t alignment, bool write)
 {
 	struct drm_i915_gem_exec_object2 *object;
 
@@ -1524,8 +1633,12 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 		   || ALIGN(offset, alignment) == offset);
 	igt_assert(is_power_of_two(alignment));
 
+	if (ibb->driver == INTEL_DRIVER_I915)
+		alignment = max_t(uint64_t, alignment, gem_detect_safe_alignment(ibb->fd));
+	else
+		alignment = max_t(uint64_t, ibb->alignment, alignment);
+
 	object = __add_to_cache(ibb, handle);
-	alignment = max_t(uint64_t, alignment, gem_detect_safe_alignment(ibb->fd));
 	__add_to_objects(ibb, object);
 
 	/*
@@ -1585,9 +1698,27 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 	if (ibb->allows_obj_alignment)
 		object->alignment = alignment;
 
+	if (ibb->driver == INTEL_DRIVER_XE) {
+		object->alignment = alignment;
+		object->rsvd1 = size;
+	}
+
 	return object;
 }
 
+struct drm_i915_gem_exec_object2 *
+intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
+		    uint64_t offset, uint64_t alignment, bool write)
+{
+	struct drm_i915_gem_exec_object2 *obj = NULL;
+
+	obj = __intel_bb_add_object(ibb, handle, size, offset,
+				    alignment, write);
+	igt_assert(obj);
+
+	return obj;
+}
+
 bool intel_bb_remove_object(struct intel_bb *ibb, uint32_t handle,
 			    uint64_t offset, uint64_t size)
 {
@@ -2136,6 +2267,82 @@ static void update_offsets(struct intel_bb *ibb,
 }
 
 #define LINELEN 76
+
+static int
+__xe_bb_exec(struct intel_bb *ibb, uint64_t flags, bool sync)
+{
+	uint32_t engine = flags & (I915_EXEC_BSD_MASK | I915_EXEC_RING_MASK);
+	uint32_t engine_id;
+	struct drm_xe_sync syncs[2] = {
+		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+	};
+	struct drm_xe_vm_bind_op *bind_ops;
+	void *map;
+
+	igt_assert_eq(ibb->num_relocs, 0);
+	igt_assert_eq(ibb->xe_bound, false);
+
+	if (ibb->last_engine != engine) {
+		struct drm_xe_engine_class_instance inst = { };
+
+		inst.engine_instance =
+			(flags & I915_EXEC_BSD_MASK) >> I915_EXEC_BSD_SHIFT;
+
+		switch (flags & I915_EXEC_RING_MASK) {
+		case I915_EXEC_DEFAULT:
+		case I915_EXEC_BLT:
+			inst.engine_class = DRM_XE_ENGINE_CLASS_COPY;
+			break;
+		case I915_EXEC_BSD:
+			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
+			break;
+		case I915_EXEC_RENDER:
+			inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
+			break;
+		case I915_EXEC_VEBOX:
+			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;
+			break;
+		default:
+			igt_assert_f(false, "Unknown engine: %x", (uint32_t) flags);
+		}
+		igt_debug("Run on %s\n", xe_engine_class_string(inst.engine_class));
+
+		ibb->engine_id = engine_id =
+			xe_engine_create(ibb->fd, ibb->vm_id, &inst, 0);
+	} else {
+		engine_id = ibb->engine_id;
+	}
+	ibb->last_engine = engine;
+
+	map = xe_bo_map(ibb->fd, ibb->handle, ibb->size);
+	memcpy(map, ibb->batch, ibb->size);
+	gem_munmap(map, ibb->size);
+
+	syncs[0].handle = syncobj_create(ibb->fd, 0);
+	if (ibb->num_objects > 1) {
+		bind_ops = xe_alloc_bind_ops(ibb, XE_VM_BIND_OP_MAP | XE_VM_BIND_FLAG_ASYNC, 0);
+		xe_vm_bind_array(ibb->fd, ibb->vm_id, 0, bind_ops,
+				 ibb->num_objects, syncs, 1);
+		free(bind_ops);
+	} else {
+		xe_vm_bind_async(ibb->fd, ibb->vm_id, 0, ibb->handle, 0,
+				 ibb->batch_offset, ibb->size, syncs, 1);
+	}
+	ibb->xe_bound = true;
+
+	syncs[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+	ibb->engine_syncobj = syncobj_create(ibb->fd, 0);
+	syncs[1].handle = ibb->engine_syncobj;
+
+	xe_exec_sync(ibb->fd, engine_id, ibb->batch_offset, syncs, 2);
+
+	if (sync)
+		intel_bb_sync(ibb);
+
+	return 0;
+}
+
 /*
  * __intel_bb_exec:
  * @ibb: pointer to intel_bb
@@ -2221,7 +2428,7 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 /**
  * intel_bb_exec:
  * @ibb: pointer to intel_bb
- * @end_offset: offset of the last instruction in the bb
+ * @end_offset: offset of the last instruction in the bb (for i915)
  * @flags: flags passed directly to execbuf
  * @sync: if true wait for execbuf completion, otherwise caller is responsible
  * to wait for completion
@@ -2231,7 +2438,13 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 		   uint64_t flags, bool sync)
 {
-	igt_assert_eq(__intel_bb_exec(ibb, end_offset, flags, sync), 0);
+	if (ibb->dump_base64)
+		intel_bb_dump_base64(ibb, LINELEN);
+
+	if (ibb->driver == INTEL_DRIVER_I915)
+		igt_assert_eq(__intel_bb_exec(ibb, end_offset, flags, sync), 0);
+	else
+		igt_assert_eq(__xe_bb_exec(ibb, flags, sync), 0);
 }
 
 /**
@@ -2636,7 +2849,8 @@ static void __intel_bb_reinit_alloc(struct intel_bb *ibb)
 							  ibb->allocator_start, ibb->allocator_end,
 							  ibb->allocator_type,
 							  ibb->allocator_strategy,
-							  0);
+							  ibb->alignment);
+
 	intel_bb_reset(ibb, true);
 }
 
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 4978b6fb2..9a58fb780 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -246,6 +246,7 @@ struct intel_bb {
 	uint8_t allocator_type;
 	enum allocator_strategy allocator_strategy;
 
+	enum intel_driver driver;
 	int fd;
 	unsigned int gen;
 	bool debug;
@@ -268,6 +269,11 @@ struct intel_bb {
 	uint32_t ctx;
 	uint32_t vm_id;
 
+	bool xe_bound;
+	uint32_t engine_syncobj;
+	uint32_t engine_id;
+	uint32_t last_engine;
+
 	/* Context configuration */
 	intel_ctx_cfg_t *cfg;
 
-- 
2.40.0

[igt-dev] [i-g-t V5 11/47] tests/xe_intel_bb: Check if intel-bb Xe support correctness

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

As we're reusing intel-bb for Xe we need to check it behaves correctly
for buffer handling and submission.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
---
 tests/meson.build      |    1 +
 tests/xe/xe_intel_bb.c | 1185 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 1186 insertions(+)
 create mode 100644 tests/xe/xe_intel_bb.c

diff --git a/tests/meson.build b/tests/meson.build
index 8909cfa8f..b026fac48 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -256,6 +256,7 @@ xe_progs = [
 	'xe_exec_threads',
 	'xe_guc_pc',
 	'xe_huc_copy',
+	'xe_intel_bb',
 	'xe_mmap',
 	'xe_mmio',
 	'xe_module_load',
diff --git a/tests/xe/xe_intel_bb.c b/tests/xe/xe_intel_bb.c
new file mode 100644
index 000000000..35d61608e
--- /dev/null
+++ b/tests/xe/xe_intel_bb.c
@@ -0,0 +1,1185 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <cairo.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <glib.h>
+#include <inttypes.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <zlib.h>
+
+#include "igt.h"
+#include "igt_crc.h"
+#include "intel_bufops.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+/**
+ * TEST: Basic tests for intel-bb xe functionality
+ * Category: Software building block
+ * Sub-category: xe
+ * Test category: functionality test
+ */
+
+#define PAGE_SIZE 4096
+
+#define WIDTH	64
+#define HEIGHT	64
+#define STRIDE	(WIDTH * 4)
+#define SIZE	(HEIGHT * STRIDE)
+
+#define COLOR_00	0x00
+#define COLOR_33	0x33
+#define COLOR_77	0x77
+#define COLOR_CC	0xcc
+
+IGT_TEST_DESCRIPTION("xe_intel_bb API check.");
+
+static bool debug_bb;
+static bool write_png;
+static bool buf_info;
+static bool print_base64;
+
+static void *alloc_aligned(uint64_t size)
+{
+	void *p;
+
+	igt_assert_eq(posix_memalign(&p, 16, size), 0);
+
+	return p;
+}
+
+static void fill_buf(struct intel_buf *buf, uint8_t color)
+{
+	uint8_t *ptr;
+	int xe = buf_ops_get_fd(buf->bops);
+	int i;
+
+	ptr = xe_bo_map(xe, buf->handle, buf->surface[0].size);
+
+	for (i = 0; i < buf->surface[0].size; i++)
+		ptr[i] = color;
+
+	munmap(ptr, buf->surface[0].size);
+}
+
+static void check_buf(struct intel_buf *buf, uint8_t color)
+{
+	uint8_t *ptr;
+	int xe = buf_ops_get_fd(buf->bops);
+	int i;
+
+	ptr = xe_bo_map(xe, buf->handle, buf->surface[0].size);
+
+	for (i = 0; i < buf->surface[0].size; i++)
+		igt_assert(ptr[i] == color);
+
+	munmap(ptr, buf->surface[0].size);
+}
+
+static struct intel_buf *
+create_buf(struct buf_ops *bops, int width, int height, uint8_t color)
+{
+	struct intel_buf *buf;
+
+	buf = calloc(1, sizeof(*buf));
+	igt_assert(buf);
+
+	intel_buf_init(bops, buf, width/4, height, 32, 0, I915_TILING_NONE, 0);
+	fill_buf(buf, color);
+
+	return buf;
+}
+
+static void print_buf(struct intel_buf *buf, const char *name)
+{
+	uint8_t *ptr;
+	int xe = buf_ops_get_fd(buf->bops);
+
+	ptr = xe_bo_map(xe, buf->handle, buf->surface[0].size);
+
+	igt_debug("[%s] Buf handle: %d, size: %" PRIu64
+		  ", v: 0x%02x, presumed_addr: %p\n",
+		  name, buf->handle, buf->surface[0].size, ptr[0],
+		  from_user_pointer(buf->addr.offset));
+	munmap(ptr, buf->surface[0].size);
+}
+
+/**
+ * SUBTEST: reset-bb
+ * Description: check bb reset
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void reset_bb(struct buf_ops *bops)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_bb *ibb;
+
+	ibb = intel_bb_create(xe, PAGE_SIZE);
+	intel_bb_reset(ibb, false);
+	intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: purge-bb
+ * Description: check bb reset == full (purge)
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void purge_bb(struct buf_ops *bops)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_buf *buf;
+	struct intel_bb *ibb;
+	uint64_t offset0, offset1;
+
+	buf = intel_buf_create(bops, 512, 512, 32, 0, I915_TILING_NONE,
+			       I915_COMPRESSION_NONE);
+	ibb = intel_bb_create(xe, 4096);
+	intel_bb_set_debug(ibb, true);
+
+	intel_bb_add_intel_buf(ibb, buf, false);
+	offset0 = buf->addr.offset;
+
+	intel_bb_reset(ibb, true);
+	buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
+
+	intel_bb_add_intel_buf(ibb, buf, false);
+	offset1 = buf->addr.offset;
+
+	igt_assert(offset0 == offset1);
+
+	intel_buf_destroy(buf);
+	intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: simple-%s
+ * Description: Run simple bb xe %arg[1] test
+ * Run type: BAT
+ *
+ * arg[1]:
+ *
+ * @bb:     bb
+ * @bb-ctx: bb-ctx
+ */
+static void simple_bb(struct buf_ops *bops, bool new_context)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_bb *ibb;
+	uint32_t ctx = 0;
+
+	ibb = intel_bb_create_with_allocator(xe, ctx, NULL, PAGE_SIZE,
+					     INTEL_ALLOCATOR_SIMPLE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 8);
+
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+	/* Check we're safe with reset and no double-free will occur */
+	intel_bb_reset(ibb, true);
+	intel_bb_reset(ibb, false);
+	intel_bb_reset(ibb, true);
+
+	if (new_context) {
+		ctx = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+		intel_bb_destroy(ibb);
+		ibb = intel_bb_create_with_context(xe, ctx, NULL, PAGE_SIZE);
+		intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+		intel_bb_ptr_align(ibb, 8);
+		intel_bb_exec(ibb, intel_bb_offset(ibb),
+			      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
+			      true);
+		xe_vm_destroy(xe, ctx);
+	}
+
+	intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: bb-with-allocator
+ * Description: check bb with passed allocator
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void bb_with_allocator(struct buf_ops *bops)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_bb *ibb;
+	struct intel_buf *src, *dst;
+	uint32_t ctx = 0;
+
+	ibb = intel_bb_create_with_allocator(xe, ctx, NULL, PAGE_SIZE,
+					     INTEL_ALLOCATOR_SIMPLE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	src = intel_buf_create(bops, 4096/32, 32, 8, 0, I915_TILING_NONE,
+			       I915_COMPRESSION_NONE);
+	dst = intel_buf_create(bops, 4096/32, 32, 8, 0, I915_TILING_NONE,
+			       I915_COMPRESSION_NONE);
+
+	intel_bb_add_intel_buf(ibb, src, false);
+	intel_bb_add_intel_buf(ibb, dst, true);
+	intel_bb_copy_intel_buf(ibb, dst, src, 4096);
+	intel_bb_remove_intel_buf(ibb, src);
+	intel_bb_remove_intel_buf(ibb, dst);
+
+	intel_buf_destroy(src);
+	intel_buf_destroy(dst);
+	intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: lot-of-buffers
+ * Description: check running bb with many buffers
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+#define NUM_BUFS 500
+static void lot_of_buffers(struct buf_ops *bops)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_bb *ibb;
+	struct intel_buf *buf[NUM_BUFS];
+	int i;
+
+	ibb = intel_bb_create(xe, PAGE_SIZE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 8);
+
+	for (i = 0; i < NUM_BUFS; i++) {
+		buf[i] = intel_buf_create(bops, 4096, 1, 8, 0, I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
+		if (i % 2)
+			intel_bb_add_intel_buf(ibb, buf[i], false);
+		else
+			intel_bb_add_intel_buf_with_alignment(ibb, buf[i],
+							      0x4000, false);
+	}
+
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+	intel_bb_reset(ibb, false);
+
+	for (i = 0; i < NUM_BUFS; i++)
+		intel_buf_destroy(buf[i]);
+
+	intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: add-remove-objects
+ * Description: check bb object manipulation (add + remove)
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void add_remove_objects(struct buf_ops *bops)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_bb *ibb;
+	struct intel_buf *src, *mid, *dst;
+	uint32_t offset;
+	const uint32_t width = 512;
+	const uint32_t height = 512;
+
+	ibb = intel_bb_create(xe, PAGE_SIZE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	src = intel_buf_create(bops, width, height, 32, 0,
+			       I915_TILING_NONE, I915_COMPRESSION_NONE);
+	mid = intel_buf_create(bops, width, height, 32, 0,
+			       I915_TILING_NONE, I915_COMPRESSION_NONE);
+	dst = intel_buf_create(bops, width, height, 32, 0,
+			       I915_TILING_NONE, I915_COMPRESSION_NONE);
+
+	intel_bb_add_intel_buf(ibb, src, false);
+	intel_bb_add_intel_buf(ibb, mid, true);
+	intel_bb_remove_intel_buf(ibb, mid);
+	intel_bb_remove_intel_buf(ibb, mid);
+	intel_bb_remove_intel_buf(ibb, mid);
+	intel_bb_add_intel_buf(ibb, dst, true);
+
+	offset = intel_bb_emit_bbe(ibb);
+	intel_bb_exec(ibb, offset,
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+	intel_bb_reset(ibb, false);
+
+	intel_buf_destroy(src);
+	intel_buf_destroy(mid);
+	intel_buf_destroy(dst);
+	intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: destroy-bb
+ * Description: check bb destroy/create
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void destroy_bb(struct buf_ops *bops)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_bb *ibb;
+	struct intel_buf *src, *mid, *dst;
+	uint32_t offset;
+	const uint32_t width = 512;
+	const uint32_t height = 512;
+
+	ibb = intel_bb_create(xe, PAGE_SIZE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	src = intel_buf_create(bops, width, height, 32, 0,
+			       I915_TILING_NONE, I915_COMPRESSION_NONE);
+	mid = intel_buf_create(bops, width, height, 32, 0,
+			       I915_TILING_NONE, I915_COMPRESSION_NONE);
+	dst = intel_buf_create(bops, width, height, 32, 0,
+			       I915_TILING_NONE, I915_COMPRESSION_NONE);
+
+	intel_bb_add_intel_buf(ibb, src, false);
+	intel_bb_add_intel_buf(ibb, mid, true);
+	intel_bb_add_intel_buf(ibb, dst, true);
+
+	offset = intel_bb_emit_bbe(ibb);
+	intel_bb_exec(ibb, offset,
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+	intel_bb_reset(ibb, false);
+
+	/* Check destroy will detach intel_bufs */
+	intel_bb_destroy(ibb);
+	igt_assert(src->addr.offset == INTEL_BUF_INVALID_ADDRESS);
+	igt_assert(src->ibb == NULL);
+	igt_assert(mid->addr.offset == INTEL_BUF_INVALID_ADDRESS);
+	igt_assert(mid->ibb == NULL);
+	igt_assert(dst->addr.offset == INTEL_BUF_INVALID_ADDRESS);
+	igt_assert(dst->ibb == NULL);
+
+	ibb = intel_bb_create(xe, PAGE_SIZE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	intel_bb_add_intel_buf(ibb, src, false);
+	offset = intel_bb_emit_bbe(ibb);
+	intel_bb_exec(ibb, offset,
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+	intel_bb_reset(ibb, false);
+
+	intel_bb_destroy(ibb);
+	intel_buf_destroy(src);
+	intel_buf_destroy(mid);
+	intel_buf_destroy(dst);
+}
+
+/**
+ * SUBTEST: create-in-region
+ * Description: check size validation on available regions
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void create_in_region(struct buf_ops *bops, uint64_t region)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_bb *ibb;
+	struct intel_buf buf = {};
+	uint32_t handle, offset;
+	uint64_t size;
+	int width = 64;
+	int height = 64;
+
+	ibb = intel_bb_create(xe, PAGE_SIZE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	size = xe_min_page_size(xe, system_memory(xe));
+	handle = xe_bo_create_flags(xe, 0, size, system_memory(xe));
+	intel_buf_init_full(bops, handle, &buf,
+			    width/4, height, 32, 0,
+			    I915_TILING_NONE, 0,
+			    size, 0, region);
+	intel_buf_set_ownership(&buf, true);
+
+	intel_bb_add_intel_buf(ibb, &buf, false);
+	offset = intel_bb_emit_bbe(ibb);
+	intel_bb_exec(ibb, offset,
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+	intel_bb_reset(ibb, false);
+
+	intel_buf_close(bops, &buf);
+	intel_bb_destroy(ibb);
+}
+
+static void __emit_blit(struct intel_bb *ibb,
+			 struct intel_buf *src, struct intel_buf *dst)
+{
+	intel_bb_emit_blt_copy(ibb,
+			       src, 0, 0, src->surface[0].stride,
+			       dst, 0, 0, dst->surface[0].stride,
+			       intel_buf_width(dst),
+			       intel_buf_height(dst),
+			       dst->bpp);
+}
+
+/**
+ * SUBTEST: blit-%s
+ * Description: Run blit on %arg[1] allocator
+ * Run type: BAT
+ *
+ * arg[1]:
+ *
+ * @simple:				simple
+ * @reloc:				reloc
+ */
+static void blit(struct buf_ops *bops, uint8_t allocator_type)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_bb *ibb;
+	struct intel_buf *src, *dst;
+	uint64_t poff_src, poff_dst;
+	uint64_t flags = 0;
+
+	ibb = intel_bb_create_with_allocator(xe, 0, NULL, PAGE_SIZE,
+					     allocator_type);
+	flags |= I915_EXEC_NO_RELOC;
+
+	src = create_buf(bops, WIDTH, HEIGHT, COLOR_CC);
+	dst = create_buf(bops, WIDTH, HEIGHT, COLOR_00);
+
+	if (buf_info) {
+		print_buf(src, "src");
+		print_buf(dst, "dst");
+	}
+
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	__emit_blit(ibb, src, dst);
+	intel_bb_emit_bbe(ibb);
+	intel_bb_flush_blit(ibb);
+	intel_bb_sync(ibb);
+	intel_bb_reset(ibb, false);
+	check_buf(dst, COLOR_CC);
+
+	poff_src = intel_bb_get_object_offset(ibb, src->handle);
+	poff_dst = intel_bb_get_object_offset(ibb, dst->handle);
+
+	/* Add buffers again */
+	intel_bb_add_intel_buf(ibb, src, false);
+	intel_bb_add_intel_buf(ibb, dst, true);
+
+	igt_assert_f(poff_src == src->addr.offset,
+		     "prev src addr: %" PRIx64 " <> src addr %" PRIx64 "\n",
+		     poff_src, src->addr.offset);
+	igt_assert_f(poff_dst == dst->addr.offset,
+		     "prev dst addr: %" PRIx64 " <> dst addr %" PRIx64 "\n",
+		     poff_dst, dst->addr.offset);
+
+	fill_buf(src, COLOR_77);
+	fill_buf(dst, COLOR_00);
+
+	__emit_blit(ibb, src, dst);
+	intel_bb_emit_bbe(ibb);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+	intel_bb_reset(ibb, false);
+	check_buf(dst, COLOR_77);
+
+	intel_bb_emit_bbe(ibb);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+	intel_bb_reset(ibb, false);
+	check_buf(dst, COLOR_77);
+
+	intel_buf_destroy(src);
+	intel_buf_destroy(dst);
+	intel_bb_destroy(ibb);
+}
+
+static void scratch_buf_init(struct buf_ops *bops,
+			     struct intel_buf *buf,
+			     int width, int height,
+			     uint32_t req_tiling,
+			     enum i915_compression compression)
+{
+	int fd = buf_ops_get_fd(bops);
+	int bpp = 32;
+
+	/*
+	 * We use system memory even if vram is possible because wc mapping
+	 * is extremely slow.
+	 */
+	intel_buf_init_in_region(bops, buf, width, height, bpp, 0,
+				 req_tiling, compression,
+				 system_memory(fd));
+
+	igt_assert(intel_buf_width(buf) == width);
+	igt_assert(intel_buf_height(buf) == height);
+}
+
+static void scratch_buf_draw_pattern(struct buf_ops *bops,
+				     struct intel_buf *buf,
+				     int x, int y, int w, int h,
+				     int cx, int cy, int cw, int ch,
+				     bool use_alternate_colors)
+{
+	cairo_surface_t *surface;
+	cairo_pattern_t *pat;
+	cairo_t *cr;
+	void *linear;
+
+	linear = alloc_aligned(buf->surface[0].size);
+
+	surface = cairo_image_surface_create_for_data(linear,
+						      CAIRO_FORMAT_RGB24,
+						      intel_buf_width(buf),
+						      intel_buf_height(buf),
+						      buf->surface[0].stride);
+
+	cr = cairo_create(surface);
+
+	cairo_rectangle(cr, cx, cy, cw, ch);
+	cairo_clip(cr);
+
+	pat = cairo_pattern_create_mesh();
+	cairo_mesh_pattern_begin_patch(pat);
+	cairo_mesh_pattern_move_to(pat, x,   y);
+	cairo_mesh_pattern_line_to(pat, x+w, y);
+	cairo_mesh_pattern_line_to(pat, x+w, y+h);
+	cairo_mesh_pattern_line_to(pat, x,   y+h);
+	if (use_alternate_colors) {
+		cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 0.0, 1.0, 1.0);
+		cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 1.0, 0.0, 1.0);
+		cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 1.0, 1.0, 0.0);
+		cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 0.0, 0.0, 0.0);
+	} else {
+		cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 1.0, 0.0, 0.0);
+		cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 0.0, 1.0, 0.0);
+		cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 0.0, 0.0, 1.0);
+		cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 1.0, 1.0, 1.0);
+	}
+	cairo_mesh_pattern_end_patch(pat);
+
+	cairo_rectangle(cr, x, y, w, h);
+	cairo_set_source(cr, pat);
+	cairo_fill(cr);
+	cairo_pattern_destroy(pat);
+
+	cairo_destroy(cr);
+
+	cairo_surface_destroy(surface);
+
+	linear_to_intel_buf(bops, buf, linear);
+
+	free(linear);
+}
+
+#define GROUP_SIZE 4096
+static int compare_detail(const uint32_t *ptr1, uint32_t *ptr2,
+			  uint32_t size)
+{
+	int i, ok = 0, fail = 0;
+	int groups = size / GROUP_SIZE;
+	int *hist = calloc(GROUP_SIZE, groups);
+
+	igt_debug("size: %d, group_size: %d, groups: %d\n",
+		  size, GROUP_SIZE, groups);
+
+	for (i = 0; i < size / sizeof(uint32_t); i++) {
+		if (ptr1[i] == ptr2[i]) {
+			ok++;
+		} else {
+			fail++;
+			hist[i * sizeof(uint32_t) / GROUP_SIZE]++;
+		}
+	}
+
+	for (i = 0; i < groups; i++) {
+		if (hist[i])
+			igt_debug("[group %4x]: %d\n", i, hist[i]);
+	}
+	free(hist);
+
+	igt_debug("ok: %d, fail: %d\n", ok, fail);
+
+	return fail;
+}
+
+static int compare_bufs(struct intel_buf *buf1, struct intel_buf *buf2,
+			 bool detail_compare)
+{
+	void *ptr1, *ptr2;
+	int fd1, fd2, ret;
+
+	igt_assert(buf1->surface[0].size == buf2->surface[0].size);
+
+	fd1 = buf_ops_get_fd(buf1->bops);
+	fd2 = buf_ops_get_fd(buf2->bops);
+
+	ptr1 = xe_bo_map(fd1, buf1->handle, buf1->surface[0].size);
+	ptr2 = xe_bo_map(fd2, buf2->handle, buf2->surface[0].size);
+	ret = memcmp(ptr1, ptr2, buf1->surface[0].size);
+	if (detail_compare)
+		ret = compare_detail(ptr1, ptr2, buf1->surface[0].size);
+
+	munmap(ptr1, buf1->surface[0].size);
+	munmap(ptr2, buf2->surface[0].size);
+
+	return ret;
+}
+
+#define LINELEN 76ul
+static int dump_base64(const char *name, struct intel_buf *buf)
+{
+	void *ptr;
+	int fd, ret;
+	uLongf outsize = buf->surface[0].size * 3 / 2;
+	Bytef *destbuf = malloc(outsize);
+	gchar *str, *pos;
+
+	fd = buf_ops_get_fd(buf->bops);
+
+	ptr = gem_mmap__device_coherent(fd, buf->handle, 0,
+					buf->surface[0].size, PROT_READ);
+
+	ret = compress2(destbuf, &outsize, ptr, buf->surface[0].size,
+			Z_BEST_COMPRESSION);
+	if (ret != Z_OK) {
+		igt_warn("error compressing, ret: %d\n", ret);
+	} else {
+		igt_info("compressed %" PRIu64 " -> %lu\n",
+			 buf->surface[0].size, outsize);
+
+		igt_info("--- %s ---\n", name);
+		pos = str = g_base64_encode(destbuf, outsize);
+		outsize = strlen(str);
+		while (pos) {
+			char line[LINELEN + 1];
+			int to_copy = min(LINELEN, outsize);
+
+			memcpy(line, pos, to_copy);
+			line[to_copy] = 0;
+			igt_info("%s\n", line);
+			pos += LINELEN;
+			outsize -= to_copy;
+
+			if (outsize == 0)
+				break;
+		}
+		free(str);
+	}
+
+	munmap(ptr, buf->surface[0].size);
+	free(destbuf);
+
+	return ret;
+}
+
+static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling)
+{
+	struct intel_bb *ibb;
+	const int width = 1024;
+	const int height = 1024;
+	struct intel_buf src, dst, final;
+	char name[128];
+	int xe = buf_ops_get_fd(bops), fails;
+
+	ibb = intel_bb_create(xe, PAGE_SIZE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	scratch_buf_init(bops, &src, width, height, I915_TILING_NONE,
+			 I915_COMPRESSION_NONE);
+	scratch_buf_init(bops, &dst, width, height, tiling,
+			 I915_COMPRESSION_NONE);
+	scratch_buf_init(bops, &final, width, height, I915_TILING_NONE,
+			 I915_COMPRESSION_NONE);
+
+	if (buf_info) {
+		intel_buf_print(&src);
+		intel_buf_print(&dst);
+	}
+
+	scratch_buf_draw_pattern(bops, &src,
+				 0, 0, width, height,
+				 0, 0, width, height, 0);
+
+	intel_bb_blt_copy(ibb,
+			  &src, 0, 0, src.surface[0].stride,
+			  &dst, 0, 0, dst.surface[0].stride,
+			  intel_buf_width(&dst),
+			  intel_buf_height(&dst),
+			  dst.bpp);
+
+	intel_bb_blt_copy(ibb,
+			  &dst, 0, 0, dst.surface[0].stride,
+			  &final, 0, 0, final.surface[0].stride,
+			  intel_buf_width(&dst),
+			  intel_buf_height(&dst),
+			  dst.bpp);
+
+	igt_assert(intel_bb_sync(ibb) == 0);
+	intel_bb_destroy(ibb);
+
+	if (write_png) {
+		snprintf(name, sizeof(name) - 1,
+			 "bb_blit_dst_tiling_%d.png", tiling);
+		intel_buf_write_to_png(&src, "bb_blit_src_tiling_none.png");
+		intel_buf_write_to_png(&dst, name);
+		intel_buf_write_to_png(&final, "bb_blit_final_tiling_none.png");
+	}
+
+	/* We'll fail on src <-> final compare so just warn */
+	if (tiling == I915_TILING_NONE) {
+		if (compare_bufs(&src, &dst, false) > 0)
+			igt_warn("none->none blit failed!");
+	} else {
+		if (compare_bufs(&src, &dst, false) == 0)
+			igt_warn("none->tiled blit failed!");
+	}
+
+	fails = compare_bufs(&src, &final, true);
+
+	intel_buf_close(bops, &src);
+	intel_buf_close(bops, &dst);
+	intel_buf_close(bops, &final);
+
+	return fails;
+}
+
+/**
+ * SUBTEST: intel-bb-blit-%s
+ * Description: Run simple bb xe %arg[1] test
+ * Run type: BAT
+ *
+ * arg[1]:
+ *
+ * @none:				none
+ * @x:					x
+ * @y:					y
+ */
+static void do_intel_bb_blit(struct buf_ops *bops, int loops, uint32_t tiling)
+{
+	int i, fails = 0, xe = buf_ops_get_fd(bops);
+
+	/* We'll fix it for gen2/3 later. */
+	igt_require(intel_gen(intel_get_drm_devid(xe)) > 3);
+
+	for (i = 0; i < loops; i++)
+		fails += __do_intel_bb_blit(bops, tiling);
+
+	igt_assert_f(fails == 0, "intel-bb-blit (tiling: %d) fails: %d\n",
+		     tiling, fails);
+}
+
+/**
+ * SUBTEST: offset-control
+ * Description: check offset is kept on default simple allocator
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void offset_control(struct buf_ops *bops)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_bb *ibb;
+	struct intel_buf *src, *dst1, *dst2, *dst3;
+	uint64_t poff_src, poff_dst1, poff_dst2;
+
+	ibb = intel_bb_create(xe, PAGE_SIZE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	src = create_buf(bops, WIDTH, HEIGHT, COLOR_CC);
+	dst1 = create_buf(bops, WIDTH, HEIGHT, COLOR_00);
+	dst2 = create_buf(bops, WIDTH, HEIGHT, COLOR_77);
+
+	intel_bb_add_object(ibb, src->handle, intel_buf_bo_size(src),
+			    src->addr.offset, 0, false);
+	intel_bb_add_object(ibb, dst1->handle, intel_buf_bo_size(dst1),
+			    dst1->addr.offset, 0, true);
+	intel_bb_add_object(ibb, dst2->handle, intel_buf_bo_size(dst2),
+			    dst2->addr.offset, 0, true);
+
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 8);
+
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
+
+	if (buf_info) {
+		print_buf(src, "src ");
+		print_buf(dst1, "dst1");
+		print_buf(dst2, "dst2");
+	}
+
+	poff_src = src->addr.offset;
+	poff_dst1 = dst1->addr.offset;
+	poff_dst2 = dst2->addr.offset;
+	intel_bb_reset(ibb, true);
+
+	dst3 = create_buf(bops, WIDTH, HEIGHT, COLOR_33);
+	intel_bb_add_object(ibb, dst3->handle, intel_buf_bo_size(dst3),
+			    dst3->addr.offset, 0, true);
+	intel_bb_add_object(ibb, src->handle, intel_buf_bo_size(src),
+			    src->addr.offset, 0, false);
+	intel_bb_add_object(ibb, dst1->handle, intel_buf_bo_size(dst1),
+			    dst1->addr.offset, 0, true);
+	intel_bb_add_object(ibb, dst2->handle, intel_buf_bo_size(dst2),
+			    dst2->addr.offset, 0, true);
+
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 8);
+
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
+	intel_bb_sync(ibb);
+	intel_bb_reset(ibb, true);
+
+	igt_assert(poff_src == src->addr.offset);
+	igt_assert(poff_dst1 == dst1->addr.offset);
+	igt_assert(poff_dst2 == dst2->addr.offset);
+
+	if (buf_info) {
+		print_buf(src, "src ");
+		print_buf(dst1, "dst1");
+		print_buf(dst2, "dst2");
+	}
+
+	intel_buf_destroy(src);
+	intel_buf_destroy(dst1);
+	intel_buf_destroy(dst2);
+	intel_buf_destroy(dst3);
+	intel_bb_destroy(ibb);
+}
+
+/*
+ * Idea of the test is to verify delta is properly added to address
+ * when emit_reloc() is called.
+ */
+
+/**
+ * SUBTEST: delta-check
+ * Description: check delta is honoured in intel-bb pipelines
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+#define DELTA_BUFFERS 3
+static void delta_check(struct buf_ops *bops)
+{
+	const uint32_t expected = 0x1234abcd;
+	int xe = buf_ops_get_fd(bops);
+	uint32_t *ptr, hi, lo, val;
+	struct intel_buf *buf;
+	struct intel_bb *ibb;
+	uint64_t offset;
+	uint64_t obj_size = xe_get_default_alignment(xe) + 0x2000;
+	uint64_t obj_offset = (1ULL << 32) - xe_get_default_alignment(xe);
+	uint64_t delta = xe_get_default_alignment(xe) + 0x1000;
+
+	ibb = intel_bb_create_with_allocator(xe, 0, NULL, PAGE_SIZE,
+					     INTEL_ALLOCATOR_SIMPLE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	buf = create_buf(bops, obj_size, 0x1, COLOR_CC);
+	buf->addr.offset = obj_offset;
+	intel_bb_add_object(ibb, buf->handle, intel_buf_bo_size(buf),
+			    buf->addr.offset, 0, false);
+
+	intel_bb_out(ibb, MI_STORE_DWORD_IMM_GEN4);
+	intel_bb_emit_reloc(ibb, buf->handle,
+			    I915_GEM_DOMAIN_RENDER,
+			    I915_GEM_DOMAIN_RENDER,
+			    delta, buf->addr.offset);
+	intel_bb_out(ibb, expected);
+
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 8);
+
+	intel_bb_exec(ibb, intel_bb_offset(ibb), I915_EXEC_DEFAULT, false);
+	intel_bb_sync(ibb);
+
+	/* Buffer should be @ obj_offset */
+	offset = intel_bb_get_object_offset(ibb, buf->handle);
+	igt_assert_eq_u64(offset, obj_offset);
+
+	ptr = xe_bo_map(xe, ibb->handle, ibb->size);
+	lo = ptr[1];
+	hi = ptr[2];
+	gem_munmap(ptr, ibb->size);
+
+	ptr = xe_bo_map(xe, buf->handle, intel_buf_size(buf));
+	val = ptr[delta / sizeof(uint32_t)];
+	gem_munmap(ptr, intel_buf_size(buf));
+
+	intel_buf_destroy(buf);
+	intel_bb_destroy(ibb);
+
+	/* Assert after all resources are freed */
+	igt_assert_f(lo == 0x1000 && hi == 0x1,
+		     "intel-bb doesn't properly handle delta in emit relocation\n");
+	igt_assert_f(val == expected,
+		     "Address doesn't contain expected [%x] value [%x]\n",
+		     expected, val);
+}
+
+/**
+ * SUBTEST: full-batch
+ * Description: check bb totally filled is executing correct
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void full_batch(struct buf_ops *bops)
+{
+	int xe = buf_ops_get_fd(bops);
+	struct intel_bb *ibb;
+	int i;
+
+	ibb = intel_bb_create(xe, PAGE_SIZE);
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	for (i = 0; i < PAGE_SIZE / sizeof(uint32_t) - 1; i++)
+		intel_bb_out(ibb, 0);
+	intel_bb_emit_bbe(ibb);
+
+	igt_assert(intel_bb_offset(ibb) == PAGE_SIZE);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+	intel_bb_reset(ibb, false);
+
+	intel_bb_destroy(ibb);
+}
+
+/**
+ * SUBTEST: render
+ * Description: check intel-bb render pipeline
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static int render(struct buf_ops *bops, uint32_t tiling,
+		  uint32_t width, uint32_t height)
+{
+	struct intel_bb *ibb;
+	struct intel_buf src, dst, final;
+	int xe = buf_ops_get_fd(bops);
+	uint32_t fails = 0;
+	char name[128];
+	uint32_t devid = intel_get_drm_devid(xe);
+	igt_render_copyfunc_t render_copy = NULL;
+
+	igt_debug("%s() gen: %d\n", __func__, intel_gen(devid));
+
+	ibb = intel_bb_create(xe, PAGE_SIZE);
+
+	if (debug_bb)
+		intel_bb_set_debug(ibb, true);
+
+	if (print_base64)
+		intel_bb_set_dump_base64(ibb, true);
+
+	scratch_buf_init(bops, &src, width, height, I915_TILING_NONE,
+			 I915_COMPRESSION_NONE);
+	scratch_buf_init(bops, &dst, width, height, tiling,
+			 I915_COMPRESSION_NONE);
+	scratch_buf_init(bops, &final, width, height, I915_TILING_NONE,
+			 I915_COMPRESSION_NONE);
+
+	scratch_buf_draw_pattern(bops, &src,
+				 0, 0, width, height,
+				 0, 0, width, height, 0);
+
+	render_copy = igt_get_render_copyfunc(devid);
+	igt_assert(render_copy);
+
+	render_copy(ibb,
+		    &src,
+		    0, 0, width, height,
+		    &dst,
+		    0, 0);
+
+	render_copy(ibb,
+		    &dst,
+		    0, 0, width, height,
+		    &final,
+		    0, 0);
+
+	intel_bb_sync(ibb);
+	intel_bb_destroy(ibb);
+
+	if (write_png) {
+		snprintf(name, sizeof(name) - 1,
+			 "render_dst_tiling_%d.png", tiling);
+		intel_buf_write_to_png(&src, "render_src_tiling_none.png");
+		intel_buf_write_to_png(&dst, name);
+		intel_buf_write_to_png(&final, "render_final_tiling_none.png");
+	}
+
+	/* We'll fail on src <-> final compare so just warn */
+	if (tiling == I915_TILING_NONE) {
+		if (compare_bufs(&src, &dst, false) > 0)
+			igt_warn("%s: none->none failed!\n", __func__);
+	} else {
+		if (compare_bufs(&src, &dst, false) == 0)
+			igt_warn("%s: none->tiled failed!\n", __func__);
+	}
+
+	fails = compare_bufs(&src, &final, true);
+
+	if (fails && print_base64) {
+		dump_base64("src", &src);
+		dump_base64("dst", &dst);
+		dump_base64("final", &final);
+	}
+
+	intel_buf_close(bops, &src);
+	intel_buf_close(bops, &dst);
+	intel_buf_close(bops, &final);
+
+	igt_assert_f(fails == 0, "%s: (tiling: %d) fails: %d\n",
+		     __func__, tiling, fails);
+
+	return fails;
+}
+
+static int opt_handler(int opt, int opt_index, void *data)
+{
+	switch (opt) {
+	case 'd':
+		debug_bb = true;
+		break;
+	case 'p':
+		write_png = true;
+		break;
+	case 'i':
+		buf_info = true;
+		break;
+	case 'b':
+		print_base64 = true;
+		break;
+	default:
+		return IGT_OPT_HANDLER_ERROR;
+	}
+
+	return IGT_OPT_HANDLER_SUCCESS;
+}
+
+const char *help_str =
+	"  -d\tDebug bb\n"
+	"  -p\tWrite surfaces to png\n"
+	"  -i\tPrint buffer info\n"
+	"  -b\tDump to base64 (bb and images)\n"
+	;
+
+igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
+{
+	int xe, i;
+	struct buf_ops *bops;
+	uint32_t width;
+
+	struct test {
+		uint32_t tiling;
+		const char *tiling_name;
+	} tests[] = {
+		{ I915_TILING_NONE, "none" },
+		{ I915_TILING_X, "x" },
+		{ I915_TILING_Y, "y" },
+	};
+
+	igt_fixture {
+		xe = drm_open_driver(DRIVER_XE);
+		bops = buf_ops_create(xe);
+		xe_device_get(xe);
+	}
+
+	igt_describe("Ensure reset is possible on fresh bb");
+	igt_subtest("reset-bb")
+		reset_bb(bops);
+
+	igt_subtest_f("purge-bb")
+		purge_bb(bops);
+
+	igt_subtest("simple-bb")
+		simple_bb(bops, false);
+
+	igt_subtest("simple-bb-ctx")
+		simple_bb(bops, true);
+
+	igt_subtest("bb-with-allocator")
+		bb_with_allocator(bops);
+
+	igt_subtest("lot-of-buffers")
+		lot_of_buffers(bops);
+
+	igt_subtest("add-remove-objects")
+		add_remove_objects(bops);
+
+	igt_subtest("destroy-bb")
+		destroy_bb(bops);
+
+	igt_subtest_with_dynamic("create-in-region") {
+		uint64_t memreg = all_memory_regions(xe), region;
+
+		xe_for_each_mem_region(fd, memreg, region)
+			igt_dynamic_f("region-%s", xe_region_name(region))
+				create_in_region(bops, region);
+	}
+
+	igt_subtest("blit-simple")
+		blit(bops, INTEL_ALLOCATOR_SIMPLE);
+
+	igt_subtest("blit-reloc")
+		blit(bops, INTEL_ALLOCATOR_RELOC);
+
+	igt_subtest("intel-bb-blit-none")
+		do_intel_bb_blit(bops, 3, I915_TILING_NONE);
+
+	igt_subtest("intel-bb-blit-x")
+		do_intel_bb_blit(bops, 3, I915_TILING_X);
+
+	igt_subtest("intel-bb-blit-y") {
+		igt_require(intel_gen(intel_get_drm_devid(xe)) >= 6);
+		do_intel_bb_blit(bops, 3, I915_TILING_Y);
+	}
+
+	igt_subtest("offset-control")
+		offset_control(bops);
+
+	igt_subtest("delta-check")
+		delta_check(bops);
+
+	igt_subtest("full-batch")
+		full_batch(bops);
+
+	igt_subtest_with_dynamic("render") {
+		for (i = 0; i < ARRAY_SIZE(tests); i++) {
+			const struct test *t = &tests[i];
+
+			for (width = 512; width <= 1024; width += 512)
+				igt_dynamic_f("render-%s-%u", t->tiling_name, width)
+					render(bops, t->tiling, width, width);
+		}
+	}
+
+	igt_fixture {
+		xe_device_put(xe);
+		buf_ops_destroy(bops);
+		close(xe);
+	}
+}
-- 
2.40.0

[igt-dev] [i-g-t V5 12/47] tests/xe-fast-feedback: Add xe_intel_bb test to BAT

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Verifies intel-bb integration with xe.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
---
 tests/intel-ci/xe-fast-feedback.testlist | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/tests/intel-ci/xe-fast-feedback.testlist b/tests/intel-ci/xe-fast-feedback.testlist
index 987e72ef4..3d0603fd9 100644
--- a/tests/intel-ci/xe-fast-feedback.testlist
+++ b/tests/intel-ci/xe-fast-feedback.testlist
@@ -106,6 +106,24 @@ igt@xe_guc_pc@freq_range_idle
 igt@xe_guc_pc@rc6_on_idle
 igt@xe_guc_pc@rc0_on_exec
 igt@xe_huc_copy@huc_copy
+igt@xe_intel_bb@add-remove-objects
+igt@xe_intel_bb@bb-with-allocator
+igt@xe_intel_bb@blit-reloc
+igt@xe_intel_bb@blit-simple
+igt@xe_intel_bb@create-in-region
+igt@xe_intel_bb@delta-check
+igt@xe_intel_bb@destroy-bb
+igt@xe_intel_bb@full-batch
+igt@xe_intel_bb@intel-bb-blit-none
+igt@xe_intel_bb@intel-bb-blit-x
+igt@xe_intel_bb@intel-bb-blit-y
+igt@xe_intel_bb@lot-of-buffers
+igt@xe_intel_bb@offset-control
+igt@xe_intel_bb@purge-bb
+igt@xe_intel_bb@render
+igt@xe_intel_bb@reset-bb
+igt@xe_intel_bb@simple-bb
+igt@xe_intel_bb@simple-bb-ctx
 igt@xe_mmap@system
 igt@xe_mmap@vram
 igt@xe_mmap@vram-system
-- 
2.40.0

[igt-dev] [i-g-t V5 13/47] lib/gpgpu_fill: Use RENDER engine flag to work on Xe

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Using I915_EXEC_DEFAULT works fine for i915 selecting appropriate
command streamer. Unfortunately this cannot be used on Xe as it
requires explicit engine selection. Submitting gpgpu work on
render is fine so change to I915_EXEC_RENDER doesn't break i915
and allows run on valid engine on Xe.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
---
 lib/gpgpu_fill.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
index 4f7bab68f..4db877514 100644
--- a/lib/gpgpu_fill.c
+++ b/lib/gpgpu_fill.c
@@ -288,7 +288,7 @@ __gen9_gpgpu_fillfunc(int i915,
 	intel_bb_ptr_align(ibb, 32);
 
 	intel_bb_exec(ibb, intel_bb_offset(ibb),
-		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+		      I915_EXEC_RENDER | I915_EXEC_NO_RELOC, true);
 
 	intel_bb_destroy(ibb);
 }
@@ -329,7 +329,7 @@ __xehp_gpgpu_fillfunc(int i915,
 	intel_bb_ptr_align(ibb, 32);
 
 	intel_bb_exec(ibb, intel_bb_offset(ibb),
-		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+		      I915_EXEC_RENDER | I915_EXEC_NO_RELOC, true);
 
 	intel_bb_destroy(ibb);
 }
-- 
2.40.0

[igt-dev] [i-g-t V5 14/47] tests/xe_gpgpu_fill: Exercise gpgpu fill on Xe

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Reuse gpgpu fill already exercised on i915 on Xe.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
---
 tests/intel-ci/xe-fast-feedback.testlist |   1 +
 tests/meson.build                        |   1 +
 tests/xe/xe_gpgpu_fill.c                 | 135 +++++++++++++++++++++++
 3 files changed, 137 insertions(+)
 create mode 100644 tests/xe/xe_gpgpu_fill.c

diff --git a/tests/intel-ci/xe-fast-feedback.testlist b/tests/intel-ci/xe-fast-feedback.testlist
index 3d0603fd9..ecf44ca73 100644
--- a/tests/intel-ci/xe-fast-feedback.testlist
+++ b/tests/intel-ci/xe-fast-feedback.testlist
@@ -100,6 +100,7 @@ igt@xe_exec_threads@threads-mixed-fd-basic
 igt@xe_exec_threads@threads-bal-mixed-basic
 igt@xe_exec_threads@threads-bal-mixed-shared-vm-basic
 igt@xe_exec_threads@threads-bal-mixed-fd-basic
+igt@xe_gpgpu_fill@basic
 igt@xe_guc_pc@freq_basic_api
 igt@xe_guc_pc@freq_fixed_idle
 igt@xe_guc_pc@freq_range_idle
diff --git a/tests/meson.build b/tests/meson.build
index b026fac48..c15eb3a08 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -254,6 +254,7 @@ xe_progs = [
 	'xe_exec_fault_mode',
 	'xe_exec_reset',
 	'xe_exec_threads',
+	'xe_gpgpu_fill',
 	'xe_guc_pc',
 	'xe_huc_copy',
 	'xe_intel_bb',
diff --git a/tests/xe/xe_gpgpu_fill.c b/tests/xe/xe_gpgpu_fill.c
new file mode 100644
index 000000000..5bca19c87
--- /dev/null
+++ b/tests/xe/xe_gpgpu_fill.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+/**
+ * TEST: Basic tests for gpgpu functionality
+ * Category: Software building block
+ * Sub-category: gpgpu
+ * Test category: functionality test
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <unistd.h>
+
+#include "drm.h"
+#include "i915/gem.h"
+#include "igt.h"
+#include "igt_collection.h"
+#include "intel_bufops.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define WIDTH 64
+#define HEIGHT 64
+#define STRIDE (WIDTH)
+#define SIZE (HEIGHT*STRIDE)
+#define COLOR_C4	0xc4
+#define COLOR_4C	0x4c
+
+typedef struct {
+	int drm_fd;
+	uint32_t devid;
+	struct buf_ops *bops;
+} data_t;
+
+static struct intel_buf *
+create_buf(data_t *data, int width, int height, uint8_t color, uint64_t region)
+{
+	struct intel_buf *buf;
+	uint8_t *ptr;
+	int i;
+
+	buf = calloc(1, sizeof(*buf));
+	igt_assert(buf);
+
+	buf = intel_buf_create(data->bops, width/4, height, 32, 0,
+			       I915_TILING_NONE, 0);
+
+	ptr = xe_bo_map(data->drm_fd, buf->handle, buf->surface[0].size);
+
+	for (i = 0; i < buf->surface[0].size; i++)
+		ptr[i] = color;
+
+	munmap(ptr, buf->surface[0].size);
+
+	return buf;
+}
+
+static void buf_check(uint8_t *ptr, int x, int y, uint8_t color)
+{
+	uint8_t val;
+
+	val = ptr[y * WIDTH + x];
+	igt_assert_f(val == color,
+		     "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
+		     color, val, x, y);
+}
+
+/**
+ * SUBTEST: basic
+ * Description: run gpgpu fill
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+
+static void gpgpu_fill(data_t *data, igt_fillfunc_t fill, uint32_t region)
+{
+	struct intel_buf *buf;
+	uint8_t *ptr;
+	int i, j;
+
+	buf = create_buf(data, WIDTH, HEIGHT, COLOR_C4, region);
+	ptr = xe_bo_map(data->drm_fd, buf->handle, buf->surface[0].size);
+
+	for (i = 0; i < WIDTH; i++)
+		for (j = 0; j < HEIGHT; j++)
+			buf_check(ptr, i, j, COLOR_C4);
+
+	fill(data->drm_fd, buf, 0, 0, WIDTH / 2, HEIGHT / 2, COLOR_4C);
+
+	for (i = 0; i < WIDTH; i++)
+		for (j = 0; j < HEIGHT; j++)
+			if (i < WIDTH / 2 && j < HEIGHT / 2)
+				buf_check(ptr, i, j, COLOR_4C);
+			else
+				buf_check(ptr, i, j, COLOR_C4);
+
+	munmap(ptr, buf->surface[0].size);
+}
+
+igt_main
+{
+	data_t data = {0, };
+	igt_fillfunc_t fill_fn = NULL;
+
+	igt_fixture {
+		data.drm_fd = drm_open_driver_render(DRIVER_XE);
+		data.devid = intel_get_drm_devid(data.drm_fd);
+		data.bops = buf_ops_create(data.drm_fd);
+
+		fill_fn = igt_get_gpgpu_fillfunc(data.devid);
+		igt_require_f(fill_fn, "no gpgpu-fill function\n");
+
+		xe_device_get(data.drm_fd);
+	}
+
+	igt_subtest("basic") {
+		gpgpu_fill(&data, fill_fn, 0);
+	}
+
+	igt_fixture {
+		xe_device_put(data.drm_fd);
+		buf_ops_destroy(data.bops);
+	}
+}
-- 
2.40.0

[igt-dev] [i-g-t V5 15/47] lib/igt_fb: For xe assume vram is used on discrete

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Assume fb bo's were created on vram on discrete, otherwise use system
memory.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
 lib/igt_fb.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 7379b99aa..df3d7d91a 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -2545,6 +2545,7 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
 {
 	struct intel_buf *buf;
 	uint32_t bo_name, handle, compression;
+	uint64_t region;
 	int num_surfaces;
 	int i;
 
@@ -2571,12 +2572,16 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
 	bo_name = gem_flink(fd, fb->gem_handle);
 	handle = gem_open(fd, bo_name);
 
-	buf = intel_buf_create_using_handle_and_size(bops, handle,
-						     fb->width, fb->height,
-						     fb->plane_bpp[0], 0,
-						     igt_fb_mod_to_tiling(fb->modifier),
-						     compression, fb->size,
-						     fb->strides[0]);
+	/* For i915 region doesn't matter, for xe does */
+	region = buf_ops_get_driver(bops) == INTEL_DRIVER_XE ?
+				vram_if_possible(fd, 0) : -1;
+	buf = intel_buf_create_full(bops, handle,
+				    fb->width, fb->height,
+				    fb->plane_bpp[0], 0,
+				    igt_fb_mod_to_tiling(fb->modifier),
+				    compression, fb->size,
+				    fb->strides[0],
+				    region);
 	intel_buf_set_name(buf, name);
 
 	/* Make sure we close handle on destroy path */
-- 
2.40.0

[igt-dev] [i-g-t V5 16/47] lib/igt_draw: Pass region while building intel_buf from flink

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

For i915 region doesn't matter but for xe we need to be more strict and
region aware. This is related to size and alignment constraints. As we
don't have information about flink buffer origin let's assume region
is vram if possible, otherwise choose system region.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
 lib/igt_draw.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index ac512fac5..c5f2fdfe2 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -37,6 +37,7 @@
 #include "i915/gem_create.h"
 #include "i915/gem_mman.h"
 #include "i915/intel_mocs.h"
+#include "xe/xe_query.h"
 
 #ifndef PAGE_ALIGN
 #ifndef PAGE_SIZE
@@ -634,17 +635,24 @@ static struct intel_buf *create_buf(int fd, struct buf_ops *bops,
 				    struct buf_data *from, uint32_t tiling)
 {
 	struct intel_buf *buf;
+	enum intel_driver driver = buf_ops_get_driver(bops);
 	uint32_t handle, name, width, height;
+	uint64_t region = driver == INTEL_DRIVER_XE ? vram_if_possible(fd, 0) : -1;
+	uint64_t size = from->size;
 
 	width = from->stride / (from->bpp / 8);
 	height = from->size / from->stride;
+	if (driver == INTEL_DRIVER_XE)
+		size = ALIGN(size, xe_get_default_alignment(fd));
 
 	name = gem_flink(fd, from->handle);
 	handle = gem_open(fd, name);
 
-	buf = intel_buf_create_using_handle(bops, handle,
-					    width, height, from->bpp, 0,
-					    tiling, 0);
+	buf = intel_buf_create_full(bops, handle,
+				    width, height, from->bpp, 0,
+				    tiling, 0,
+				    size, 0,
+				    region);
 
 	/* Make sure we close handle on destroy path */
 	intel_buf_set_ownership(buf, true);
-- 
2.40.0

[igt-dev] [i-g-t V5 17/47] tests/kms_big_fb: Deduce region for xe framebuffer

[Bhanuprakash Modem]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

For discrete framebuffer reside on vram/device memory and for
integrated on system memory. Due to xe requirement regarding
size and alignment on different memory regions during intel_buf
creation pass deduced memory region.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
 tests/i915/kms_big_fb.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/tests/i915/kms_big_fb.c b/tests/i915/kms_big_fb.c
index a29a05a28..a0d5ef730 100644
--- a/tests/i915/kms_big_fb.c
+++ b/tests/i915/kms_big_fb.c
@@ -28,6 +28,7 @@
 #include <string.h>
 
 #include "i915/gem_create.h"
+#include "xe/xe_query.h"
 
 IGT_TEST_DESCRIPTION("Test big framebuffers");
 
@@ -62,7 +63,10 @@ static struct intel_buf *init_buf(data_t *data,
 				  const char *buf_name)
 {
 	struct intel_buf *buf;
+	enum intel_driver driver = buf_ops_get_driver(data->bops);
 	uint32_t name, handle, tiling, stride, width, height, bpp, size;
+	uint64_t region = driver == INTEL_DRIVER_XE ?
+				vram_if_possible(data->drm_fd, 0) : -1;
 
 	igt_assert_eq(fb->offsets[0], 0);
 
@@ -75,8 +79,10 @@ static struct intel_buf *init_buf(data_t *data,
 
 	name = gem_flink(data->drm_fd, fb->gem_handle);
 	handle = gem_open(data->drm_fd, name);
-	buf = intel_buf_create_using_handle(data->bops, handle, width, height,
-					    bpp, 0, tiling, 0);
+	buf = intel_buf_create_full(data->bops, handle, width, height,
+				    bpp, 0, tiling, 0, size, 0,
+				    region);
+
 	intel_buf_set_name(buf, buf_name);
 	intel_buf_set_ownership(buf, true);
 
-- 
2.40.0

[igt-dev] [i-g-t V5 18/47] lib/igt_fb: Add copy engine support for XE

[Bhanuprakash Modem]

Add copy engine support for kms framebuffer mappings.

V2: - Drop unused syncobj(Zbigniew)

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Acked-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Swati Sharma <swati2.sharma@intel.com>
---
 lib/igt_fb.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index df3d7d91a..0fe5b6adf 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -45,6 +45,7 @@
 #include "igt_amd.h"
 #include "igt_x86.h"
 #include "igt_nouveau.h"
+#include "igt_syncobj.h"
 #include "ioctl_wrappers.h"
 #include "intel_batchbuffer.h"
 #include "intel_chipset.h"
@@ -2489,12 +2490,13 @@ static bool blitter_ok(const struct igt_fb *fb)
 
 static bool use_enginecopy(const struct igt_fb *fb)
 {
-	if (blitter_ok(fb))
+	if (!is_xe_device(fb->fd) && blitter_ok(fb))
 		return false;
 
 	return fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	       is_ccs_modifier(fb->modifier) ||
-	       !gem_has_mappable_ggtt(fb->fd);
+	       (is_xe_device(fb->fd) && fb->modifier == DRM_FORMAT_MOD_LINEAR) ||
+	       (is_i915_device(fb->fd) && !gem_has_mappable_ggtt(fb->fd));
 }
 
 static bool use_blitter(const struct igt_fb *fb)
@@ -2504,7 +2506,7 @@ static bool use_blitter(const struct igt_fb *fb)
 
 	return fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 	       fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
-	       !gem_has_mappable_ggtt(fb->fd);
+	       (is_i915_device(fb->fd) && !gem_has_mappable_ggtt(fb->fd));
 }
 
 static void init_buf_ccs(struct intel_buf *buf, int ccs_idx,
@@ -2706,7 +2708,7 @@ static void blitcopy(const struct igt_fb *dst_fb,
 	src_tiling = igt_fb_mod_to_tiling(src_fb->modifier);
 	dst_tiling = igt_fb_mod_to_tiling(dst_fb->modifier);
 
-	if (!gem_has_relocations(dst_fb->fd)) {
+	if (is_i915_device(dst_fb->fd) && !gem_has_relocations(dst_fb->fd)) {
 		igt_require(gem_has_contexts(dst_fb->fd));
 		ctx = gem_context_create(dst_fb->fd);
 		ahnd = get_reloc_ahnd(dst_fb->fd, ctx);
@@ -2786,6 +2788,12 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
 	} else if (is_nouveau_device(fd)) {
 		igt_nouveau_fb_blit(fb, &linear->fb);
 		igt_nouveau_delete_bo(&linear->fb);
+	} else if (is_xe_device(fd)) {
+		gem_munmap(linear->map, linear->fb.size);
+		copy_with_engine(blit, fb, &linear->fb);
+
+		syncobj_wait(fd, &blit->ibb->engine_syncobj, 1, INT64_MAX, 0, NULL);
+		gem_close(fd, linear->fb.gem_handle);
 	} else {
 		gem_munmap(linear->map, linear->fb.size);
 		gem_set_domain(fd, linear->fb.gem_handle,
@@ -2863,6 +2871,11 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
 		igt_nouveau_fb_blit(&linear->fb, fb);
 
 		linear->map = igt_nouveau_mmap_bo(&linear->fb, PROT_READ | PROT_WRITE);
+	} else if (is_xe_device(fd)) {
+		copy_with_engine(blit, &linear->fb, fb);
+
+		linear->map = xe_bo_mmap_ext(fd, linear->fb.gem_handle,
+					     linear->fb.size, PROT_READ | PROT_WRITE);
 	} else {
 		/* Copy fb content to linear BO */
 		gem_set_domain(fd, linear->fb.gem_handle,
@@ -2969,6 +2982,9 @@ static void *map_bo(int fd, struct igt_fb *fb)
 				      PROT_READ | PROT_WRITE);
 	else if (is_nouveau_device(fd))
 		ptr = igt_nouveau_mmap_bo(fb, PROT_READ | PROT_WRITE);
+	else if (is_xe_device(fd))
+		ptr = xe_bo_mmap_ext(fd, fb->gem_handle,
+				     fb->size, PROT_READ | PROT_WRITE);
 	else
 		igt_assert(false);
 
-- 
2.40.0

[igt-dev] [i-g-t V5 19/47] lib/igt_draw: Add gpu draw routine support for XE

[Bhanuprakash Modem]

Add GPU blt, render & WC draw routine support for XE driver.

V2: - Rebase

Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Acked-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Nidhi Gupta <nidhi1.gupta@intel.com>
---
 lib/igt_draw.c | 81 +++++++++++++++++++++++++++++++++++---------------
 lib/igt_draw.h |  2 ++
 2 files changed, 59 insertions(+), 24 deletions(-)

diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index c5f2fdfe2..d719b2400 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -37,6 +37,7 @@
 #include "i915/gem_create.h"
 #include "i915/gem_mman.h"
 #include "i915/intel_mocs.h"
+#include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 
 #ifndef PAGE_ALIGN
@@ -494,24 +495,29 @@ static void draw_rect_mmap_wc(int fd, struct buf_data *buf, struct rect *rect,
 {
 	uint32_t *ptr;
 
-	gem_set_domain(fd, buf->handle, I915_GEM_DOMAIN_GTT,
-		       I915_GEM_DOMAIN_GTT);
-
-	/* We didn't implement suport for the older tiling methods yet. */
-	if (tiling != I915_TILING_NONE)
-		igt_require(intel_display_ver(intel_get_drm_devid(fd)) >= 5);
-
-	if (gem_has_lmem(fd))
-		ptr = gem_mmap_offset__fixed(fd, buf->handle, 0,
-					     PAGE_ALIGN(buf->size),
-					     PROT_READ | PROT_WRITE);
-	else if (gem_has_legacy_mmap(fd))
-		ptr = gem_mmap__wc(fd, buf->handle, 0, PAGE_ALIGN(buf->size),
-				   PROT_READ | PROT_WRITE);
-	else
-		ptr = gem_mmap_offset__wc(fd, buf->handle, 0,
-					  PAGE_ALIGN(buf->size),
-					  PROT_READ | PROT_WRITE);
+	if (is_i915_device(fd)) {
+		gem_set_domain(fd, buf->handle, I915_GEM_DOMAIN_GTT,
+			       I915_GEM_DOMAIN_GTT);
+
+		/* We didn't implement suport for the older tiling methods yet. */
+		if (tiling != I915_TILING_NONE)
+			igt_require(intel_display_ver(intel_get_drm_devid(fd)) >= 5);
+
+		if (gem_has_lmem(fd))
+			ptr = gem_mmap_offset__fixed(fd, buf->handle, 0,
+						     PAGE_ALIGN(buf->size),
+						     PROT_READ | PROT_WRITE);
+		else if (gem_has_legacy_mmap(fd))
+			ptr = gem_mmap__wc(fd, buf->handle, 0, PAGE_ALIGN(buf->size),
+					   PROT_READ | PROT_WRITE);
+		else
+			ptr = gem_mmap_offset__wc(fd, buf->handle, 0,
+						  PAGE_ALIGN(buf->size),
+						  PROT_READ | PROT_WRITE);
+	} else {
+		ptr = xe_bo_mmap_ext(fd, buf->handle, buf->size,
+				     PROT_READ | PROT_WRITE);
+	}
 
 	switch (tiling) {
 	case I915_TILING_NONE:
@@ -671,11 +677,14 @@ static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
 	int gen = intel_gen(devid);
 	int pitch;
 
+	if (tiling)
+		igt_require_i915(fd);
+
 	dst = create_buf(fd, cmd_data->bops, buf, tiling);
 	ibb = intel_bb_create(fd, PAGE_SIZE);
 	intel_bb_add_intel_buf(ibb, dst, true);
 
-	if (HAS_4TILE(intel_get_drm_devid(fd))) {
+	if (is_i915_device(fd) && HAS_4TILE(intel_get_drm_devid(fd))) {
 		int buf_height = buf->size / buf->stride;
 
 		switch (buf->bpp) {
@@ -780,11 +789,21 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
 
 	/* We create a temporary buffer and copy from it using rendercopy. */
 	tmp.size = rect->w * rect->h * pixel_size;
-	tmp.handle = gem_create(fd, tmp.size);
+	if (is_i915_device(fd))
+		tmp.handle = gem_create(fd, tmp.size);
+	else
+		tmp.handle = xe_bo_create_flags(fd, 0,
+						ALIGN(tmp.size, xe_get_default_alignment(fd)),
+						vram_if_possible(fd, 0));
+
 	tmp.stride = rect->w * pixel_size;
 	tmp.bpp = buf->bpp;
-	draw_rect_mmap_cpu(fd, &tmp, &(struct rect){0, 0, rect->w, rect->h},
-			   I915_TILING_NONE, I915_BIT_6_SWIZZLE_NONE, color);
+	if (is_i915_device(fd))
+		draw_rect_mmap_cpu(fd, &tmp, &(struct rect){0, 0, rect->w, rect->h},
+				   I915_TILING_NONE, I915_BIT_6_SWIZZLE_NONE, color);
+	else
+		draw_rect_mmap_wc(fd, &tmp, &(struct rect){0, 0, rect->w, rect->h},
+				  I915_TILING_NONE, I915_BIT_6_SWIZZLE_NONE, color);
 
 	src = create_buf(fd, cmd_data->bops, &tmp, I915_TILING_NONE);
 	dst = create_buf(fd, cmd_data->bops, buf, tiling);
@@ -912,7 +931,21 @@ void igt_draw_rect_fb(int fd, struct buf_ops *bops,
 void igt_draw_fill_fb(int fd, struct igt_fb *fb, uint32_t color)
 {
 	igt_draw_rect_fb(fd, NULL, 0, fb,
-			 gem_has_mappable_ggtt(fd) ? IGT_DRAW_MMAP_GTT :
-						     IGT_DRAW_MMAP_WC,
+			 igt_draw_supports_method(fd, IGT_DRAW_MMAP_GTT) ?
+			 IGT_DRAW_MMAP_GTT : IGT_DRAW_MMAP_WC,
 			 0, 0, fb->width, fb->height, color);
 }
+
+bool igt_draw_supports_method(int fd, enum igt_draw_method method)
+{
+	if (method == IGT_DRAW_MMAP_GTT)
+		return is_i915_device(fd) && gem_has_mappable_ggtt(fd);
+
+	if (method == IGT_DRAW_MMAP_WC)
+		return (is_i915_device(fd) && gem_mmap__has_wc(fd)) || is_xe_device(fd);
+
+	if (method == IGT_DRAW_MMAP_CPU || method == IGT_DRAW_PWRITE)
+		return is_i915_device(fd);
+
+	return true;
+}
diff --git a/lib/igt_draw.h b/lib/igt_draw.h
index 2d18ef6c9..fe7531b79 100644
--- a/lib/igt_draw.h
+++ b/lib/igt_draw.h
@@ -50,6 +50,8 @@ enum igt_draw_method {
 
 const char *igt_draw_get_method_name(enum igt_draw_method method);
 
+bool igt_draw_supports_method(int fd, enum igt_draw_method method);
+
 void igt_draw_rect(int fd, struct buf_ops *bops, uint32_t ctx,
 		   uint32_t buf_handle, uint32_t buf_size, uint32_t buf_stride,
 		   uint32_t tiling, enum igt_draw_method method,
-- 
2.40.0

[igt-dev] [i-g-t V5 20/47] tests/i915/kms_big_fb: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/kms_big_fb.c | 74 ++++++++++++++++++++++++++++++++---------
 1 file changed, 59 insertions(+), 15 deletions(-)

diff --git a/tests/i915/kms_big_fb.c b/tests/i915/kms_big_fb.c
index a0d5ef730..c120a14a6 100644
--- a/tests/i915/kms_big_fb.c
+++ b/tests/i915/kms_big_fb.c
@@ -28,6 +28,7 @@
 #include <string.h>
 
 #include "i915/gem_create.h"
+#include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 
 IGT_TEST_DESCRIPTION("Test big framebuffers");
@@ -104,10 +105,12 @@ static void copy_pattern(data_t *data,
 	src = init_buf(data, src_fb, "big fb src");
 	dst = init_buf(data, dst_fb, "big fb dst");
 
-	gem_set_domain(data->drm_fd, dst_fb->gem_handle,
-		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
-	gem_set_domain(data->drm_fd, src_fb->gem_handle,
-		       I915_GEM_DOMAIN_GTT, 0);
+	if (is_i915_device(data->drm_fd)) {
+		gem_set_domain(data->drm_fd, dst_fb->gem_handle,
+			       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+		gem_set_domain(data->drm_fd, src_fb->gem_handle,
+			       I915_GEM_DOMAIN_GTT, 0);
+	}
 
 	/*
 	 * We expect the kernel to limit the max fb
@@ -638,7 +641,7 @@ test_size_overflow(data_t *data)
 					       data->modifier));
 
 	/*
-	 * Try to hit a specific integer overflow in i915 fb size
+	 * Try to hit a specific integer overflow in intel fb size
 	 * calculations. 256k * 16k == 1<<32 which is checked
 	 * against the bo size. The check should fail on account
 	 * of the bo being smaller, but due to the overflow the
@@ -647,8 +650,13 @@ test_size_overflow(data_t *data)
 	igt_require(data->max_fb_width >= 16383 &&
 		    data->max_fb_height >= 16383);
 
-	bo = gem_buffer_create_fb_obj(data->drm_fd, (1ULL << 32) - 4096);
-
+	if (is_i915_device(data->drm_fd))
+		bo = gem_buffer_create_fb_obj(data->drm_fd, (1ULL << 32) - 4096);
+	else
+		bo = xe_bo_create_flags(data->drm_fd, 0,
+					ALIGN(((1ULL << 32) - 4096),
+					      xe_get_default_alignment(data->drm_fd)),
+					vram_if_possible(data->drm_fd, 0));
 	igt_require(bo);
 
 	ret = __kms_addfb(data->drm_fd, bo,
@@ -677,7 +685,7 @@ test_size_offset_overflow(data_t *data)
 					       data->modifier));
 
 	/*
-	 * Try to hit a specific integer overflow in i915 fb size
+	 * Try to hit a specific integer overflow in intel fb size
 	 * calculations. This time it's offsets[1] + the tile
 	 * aligned chroma plane size that overflows and
 	 * incorrectly passes the bo size check.
@@ -686,7 +694,13 @@ test_size_offset_overflow(data_t *data)
 					       DRM_FORMAT_NV12,
 					       data->modifier));
 
-	bo = gem_buffer_create_fb_obj(data->drm_fd, (1ULL << 32) - 4096);
+	if (is_i915_device(data->drm_fd))
+		bo = gem_buffer_create_fb_obj(data->drm_fd, (1ULL << 32) - 4096);
+	else
+		bo = xe_bo_create_flags(data->drm_fd, 0,
+					ALIGN(((1ULL << 32) - 4096),
+					      xe_get_default_alignment(data->drm_fd)),
+					vram_if_possible(data->drm_fd, 0));
 	igt_require(bo);
 
 	offsets[0] = 0;
@@ -745,10 +759,15 @@ test_addfb(data_t *data)
 			 format, data->modifier,
 			 &size, &strides[0]);
 
-	bo = gem_buffer_create_fb_obj(data->drm_fd, size);
+	if (is_i915_device(data->drm_fd))
+		bo = gem_buffer_create_fb_obj(data->drm_fd, size);
+	else
+		bo = xe_bo_create_flags(data->drm_fd, 0,
+					ALIGN(size, xe_get_default_alignment(data->drm_fd)),
+					vram_if_possible(data->drm_fd, 0));
 	igt_require(bo);
 
-	if (intel_display_ver(data->devid) < 4)
+	if (is_i915_device(data->drm_fd) && intel_display_ver(data->devid) < 4)
 		gem_set_tiling(data->drm_fd, bo,
 			       igt_fb_mod_to_tiling(data->modifier), strides[0]);
 
@@ -844,9 +863,9 @@ igt_main
 	igt_fixture {
 		drmModeResPtr res;
 
-		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
+		data.drm_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_XE);
 
-		igt_require(is_i915_device(data.drm_fd));
+		igt_require(is_intel_device(data.drm_fd));
 
 		data.devid = intel_get_drm_devid(data.drm_fd);
 
@@ -868,7 +887,11 @@ igt_main
 			 data.max_fb_width, data.max_fb_height);
 
 		data.ram_size = igt_get_total_ram_mb() << 20;
-		data.aper_size = gem_aperture_size(data.drm_fd);
+
+		if (is_i915_device(data.drm_fd))
+			data.aper_size = gem_aperture_size(data.drm_fd);
+		else
+			data.aper_size = (1ULL << xe_va_bits(data.drm_fd));
 		data.mappable_size = gem_mappable_aperture_size(data.drm_fd);
 
 		igt_info("RAM: %"PRIu64" MiB, GPU address space: %"PRId64" MiB, GGTT mappable size: %"PRId64" MiB\n",
@@ -905,6 +928,10 @@ igt_main
 	for (int i = 1; i < ARRAY_SIZE(modifiers); i++) {
 		igt_subtest_f("%s-addfb-size-overflow",
 			      modifiers[i].name) {
+			/* No tiling support in XE. */
+			igt_skip_on(is_xe_device(data.drm_fd) &&
+				    modifiers[i].modifier != DRM_FORMAT_MOD_LINEAR);
+
 			data.modifier = modifiers[i].modifier;
 			test_size_overflow(&data);
 		}
@@ -914,6 +941,10 @@ igt_main
 	for (int i = 1; i < ARRAY_SIZE(modifiers); i++) {
 		igt_subtest_f("%s-addfb-size-offset-overflow",
 			      modifiers[i].name) {
+			/* No tiling support in XE. */
+			igt_skip_on(is_xe_device(data.drm_fd) &&
+				    modifiers[i].modifier != DRM_FORMAT_MOD_LINEAR);
+
 			data.modifier = modifiers[i].modifier;
 			test_size_offset_overflow(&data);
 		}
@@ -922,6 +953,10 @@ igt_main
 	igt_describe("Sanity check if addfb ioctl works correctly for given size and strides of fb");
 	for (int i = 0; i < ARRAY_SIZE(modifiers); i++) {
 		igt_subtest_f("%s-addfb", modifiers[i].name) {
+			/* No tiling support in XE. */
+			igt_skip_on(is_xe_device(data.drm_fd) &&
+				    modifiers[i].modifier != DRM_FORMAT_MOD_LINEAR);
+
 			data.modifier = modifiers[i].modifier;
 			test_addfb(&data);
 		}
@@ -939,8 +974,13 @@ igt_main
 				igt_describe("Sanity check if addfb ioctl works correctly for given "
 						"combination of modifier formats and rotation");
 				igt_subtest_f("%s-%dbpp-rotate-%d", modifiers[i].name,
-					      formats[j].bpp, rotations[k].angle)
+					      formats[j].bpp, rotations[k].angle) {
+					/* No tiling support in XE. */
+					igt_skip_on(is_xe_device(data.drm_fd) &&
+						    data.modifier != DRM_FORMAT_MOD_LINEAR);
+
 					test_scanout(&data);
+				}
 			}
 
 			igt_fixture
@@ -982,6 +1022,10 @@ igt_main
 						igt_require(intel_display_ver(intel_get_drm_devid(data.drm_fd)) >= 5);
 						data.max_hw_fb_width = min(data.hw_stride / (formats[j].bpp >> 3), data.max_fb_width);
 
+						/* No tiling support in XE. */
+						igt_skip_on(is_xe_device(data.drm_fd) &&
+							    modifiers[i].modifier != DRM_FORMAT_MOD_LINEAR);
+
 						test_scanout(&data);
 					}
 
-- 
2.40.0

[igt-dev] [i-g-t V5 21/47] tests/i915/kms_big_joiner: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Nidhi Gupta <nidhi1.gupta@intel.com>
---
 tests/i915/kms_big_joiner.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/i915/kms_big_joiner.c b/tests/i915/kms_big_joiner.c
index 8be60ea11..b9dda58f6 100644
--- a/tests/i915/kms_big_joiner.c
+++ b/tests/i915/kms_big_joiner.c
@@ -188,7 +188,7 @@ igt_main
 	enum pipe pipe_seq[IGT_MAX_PIPES];
 
 	igt_fixture {
-		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
+		data.drm_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_XE);
 		kmstest_set_vt_graphics_mode();
 
 		igt_display_require(&data.display, data.drm_fd);
-- 
2.40.0

[igt-dev] [i-g-t V5 22/47] tests/i915/kms_cdclk: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 tests/i915/kms_cdclk.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tests/i915/kms_cdclk.c b/tests/i915/kms_cdclk.c
index bb0036802..0f9b8dc58 100644
--- a/tests/i915/kms_cdclk.c
+++ b/tests/i915/kms_cdclk.c
@@ -65,6 +65,9 @@ static int get_current_cdclk_freq(int debugfs_fd)
 	 * Display specific clock frequency info is moved to i915_cdclk_info,
 	 * On older kernels if this debugfs is not found, fallback to read from
 	 * i915_frequency_info.
+	 *
+	 * FIXME: As of now, XE debugfs is still using i915 namespace, once the
+	 * Kernel changes are landed, update this to use the XE specific debugfs.
 	 */
 	res = igt_debugfs_simple_read(debugfs_fd, "i915_cdclk_info",
 				      buf, sizeof(buf));
@@ -368,7 +371,7 @@ igt_main
 	data_t data = {};
 
 	igt_fixture {
-		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
+		data.drm_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_XE);
 		igt_require(data.drm_fd >= 0);
 		data.debugfs_fd = igt_debugfs_dir(data.drm_fd);
 		igt_require(data.debugfs_fd);
-- 
2.40.0

[igt-dev] [i-g-t V5 23/47] tests/i915/kms_draw_crc: Add XE support

[Bhanuprakash Modem]

Add XE driver support for differnt draw methods.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Nidhi Gupta <nidhi1.gupta@intel.com>
---
 tests/i915/kms_draw_crc.c | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/tests/i915/kms_draw_crc.c b/tests/i915/kms_draw_crc.c
index 3a3cd99a0..db6d71f2e 100644
--- a/tests/i915/kms_draw_crc.c
+++ b/tests/i915/kms_draw_crc.c
@@ -149,8 +149,8 @@ static void draw_method_subtest(enum igt_draw_method method,
 	 * comparison. Cache the value so we don't recompute it for every single
 	 * subtest. */
 	if (!base_crcs[format_index].set) {
-		get_method_crc(gem_has_mappable_ggtt(drm_fd) ? IGT_DRAW_MMAP_GTT :
-							       IGT_DRAW_MMAP_WC,
+		get_method_crc(igt_draw_supports_method(drm_fd, IGT_DRAW_MMAP_GTT) ?
+			       IGT_DRAW_MMAP_GTT : IGT_DRAW_MMAP_WC,
 			       formats[format_index],
 			       DRM_FORMAT_MOD_LINEAR,
 			       &base_crcs[format_index].crc);
@@ -195,8 +195,8 @@ static void fill_fb_subtest(void)
 	igt_plane_set_fb(primary, &fb);
 
 	igt_draw_rect_fb(drm_fd, bops, 0, &fb,
-			 gem_has_mappable_ggtt(drm_fd) ? IGT_DRAW_MMAP_GTT :
-							 IGT_DRAW_MMAP_WC,
+			 igt_draw_supports_method(drm_fd, IGT_DRAW_MMAP_GTT) ?
+			 IGT_DRAW_MMAP_GTT : IGT_DRAW_MMAP_WC,
 			 0, 0, fb.width, fb.height, 0xFF);
 
 	rc = igt_display_commit2(&display, display.is_atomic ? COMMIT_ATOMIC : COMMIT_LEGACY);
@@ -222,7 +222,7 @@ static void fill_fb_subtest(void)
 
 static void setup_environment(void)
 {
-	drm_fd = drm_open_driver_master(DRIVER_INTEL);
+	drm_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_XE);
 	igt_require(drm_fd >= 0);
 	igt_display_require(&display, drm_fd);
 	igt_display_require_output(&display);
@@ -289,13 +289,17 @@ igt_main
 			       "method (%s) with different modifiers & DRM formats.",
 			       igt_draw_get_method_name(method));
 		igt_subtest_with_dynamic_f("draw-method-%s", igt_draw_get_method_name(method)) {
-			igt_skip_on(method == IGT_DRAW_MMAP_WC && !gem_mmap__has_wc(drm_fd));
-			igt_skip_on(method == IGT_DRAW_MMAP_GTT && !gem_has_mappable_ggtt(drm_fd));
+			if (!igt_draw_supports_method(drm_fd, method))
+				continue;
 
-			for (format_idx = 0; format_idx < ARRAY_SIZE(formats); format_idx++) {
-				for (modifier_idx = 0; modifier_idx < ARRAY_SIZE(modifiers); modifier_idx++) {
-					modifier = modifiers[modifier_idx];
+			for (modifier_idx = 0; modifier_idx < ARRAY_SIZE(modifiers); modifier_idx++) {
+				modifier = modifiers[modifier_idx];
 
+				/* No tiling support in XE. */
+				if (is_xe_device(drm_fd) && modifier != DRM_FORMAT_MOD_LINEAR)
+					continue;
+
+				for (format_idx = 0; format_idx < ARRAY_SIZE(formats); format_idx++) {
 					if (!igt_display_has_format_mod(&display, formats[format_idx], modifier))
 						continue;
 
-- 
2.40.0

[igt-dev] [i-g-t V5 24/47] tests/i915/kms_dsc: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 tests/i915/kms_dsc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/i915/kms_dsc.c b/tests/i915/kms_dsc.c
index cf34dc8a8..c4dfc9251 100644
--- a/tests/i915/kms_dsc.c
+++ b/tests/i915/kms_dsc.c
@@ -212,7 +212,7 @@ igt_main
 	data_t data = {};
 
 	igt_fixture {
-		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
+		data.drm_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_XE);
 		data.devid = intel_get_drm_devid(data.drm_fd);
 		data.disp_ver = intel_display_ver(data.devid);
 		kmstest_set_vt_graphics_mode();
-- 
2.40.0

[igt-dev] [i-g-t V5 25/47] tests/i915/kms_flip_scaled_crc: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 tests/i915/kms_flip_scaled_crc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tests/i915/kms_flip_scaled_crc.c b/tests/i915/kms_flip_scaled_crc.c
index 7f7a59b93..f5dc430e3 100644
--- a/tests/i915/kms_flip_scaled_crc.c
+++ b/tests/i915/kms_flip_scaled_crc.c
@@ -623,7 +623,7 @@ igt_main
 	drmModeModeInfoPtr modetoset = NULL;
 
 	igt_fixture {
-		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
+		data.drm_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_XE);
 		data.gen = intel_display_ver(intel_get_drm_devid(data.drm_fd));
 		igt_require(data.gen >= 9);
 		igt_display_require(&data.display, data.drm_fd);
@@ -644,6 +644,12 @@ igt_main
 	for (int index = 0; index < ARRAY_SIZE(flip_scenario_test); index++) {
 		igt_describe(flip_scenario_test[index].describe);
 		igt_subtest_with_dynamic(flip_scenario_test[index].name) {
+			/* No tiling support in XE. */
+			if (is_xe_device(data.drm_fd) &&
+			    (flip_scenario_test[index].firstmodifier != DRM_FORMAT_MOD_LINEAR ||
+			     flip_scenario_test[index].secondmodifier != DRM_FORMAT_MOD_LINEAR))
+				continue;
+
 			free_fbs(&data);
 			for_each_pipe(&data.display, pipe) {
 				bool found = false;
-- 
2.40.0

[igt-dev] [i-g-t V5 26/47] tests/i915/kms_flip_tiling: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 tests/i915/kms_flip_tiling.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tests/i915/kms_flip_tiling.c b/tests/i915/kms_flip_tiling.c
index 4cc063f63..a22f12382 100644
--- a/tests/i915/kms_flip_tiling.c
+++ b/tests/i915/kms_flip_tiling.c
@@ -177,7 +177,7 @@ igt_output_t *output;
 igt_main
 {
 	igt_fixture {
-		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
+		data.drm_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_XE);
 		data.gen = intel_display_ver(intel_get_drm_devid(data.drm_fd));
 
 		data.testformat = DRM_FORMAT_XRGB8888;
@@ -217,6 +217,12 @@ igt_main
 					if (plane->formats[j] != data.testformat)
 						continue;
 
+					/* No tiling support in XE. */
+					if (is_xe_device(data.drm_fd) &&
+					    (plane->modifiers[i] != DRM_FORMAT_MOD_LINEAR ||
+					     plane->modifiers[j] != DRM_FORMAT_MOD_LINEAR))
+						continue;
+
 					igt_dynamic_f("%s-pipe-%s-%s-to-%s",
 						      igt_output_name(output),
 						      kmstest_pipe_name(pipe),
-- 
2.40.0

[igt-dev] [i-g-t V5 27/47] tests/i915/kms_mmap_write_crc: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/i915/kms_mmap_write_crc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/i915/kms_mmap_write_crc.c b/tests/i915/kms_mmap_write_crc.c
index 4f7a86bf4..bc51975f6 100644
--- a/tests/i915/kms_mmap_write_crc.c
+++ b/tests/i915/kms_mmap_write_crc.c
@@ -102,7 +102,7 @@ static void test(data_t *data)
 	igt_plane_set_fb(data->primary, &data->fb[0]);
 	igt_display_commit(display);
 
-	if (!gem_has_lmem(data->drm_fd)) {
+	if (is_i915_device(data->drm_fd) && !gem_has_lmem(data->drm_fd)) {
 		uint32_t caching;
 
 		/* make sure caching mode has become UC/WT */
@@ -259,7 +259,7 @@ igt_main_args("n", NULL, NULL, opt_handler, NULL)
 	enum pipe pipe;
 
 	igt_fixture {
-		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
+		data.drm_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_XE);
 
 		data.devid = intel_get_drm_devid(data.drm_fd);
 
-- 
2.40.0

[igt-dev] [i-g-t V5 28/47] tests/kms_3d: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
---
 tests/kms_3d.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/tests/kms_3d.c b/tests/kms_3d.c
index c6bef67c1..437c8a481 100644
--- a/tests/kms_3d.c
+++ b/tests/kms_3d.c
@@ -23,6 +23,7 @@
  */
 
 #include "igt.h"
+#include "xe/xe_query.h"
 
 IGT_TEST_DESCRIPTION("Tests 3D mode setting.");
 
@@ -36,6 +37,9 @@ igt_simple_main
 
 	drm_fd = drm_open_driver_master(DRIVER_ANY);
 
+	if (is_xe_device(drm_fd))
+		xe_device_get(drm_fd);
+
 	res = drmModeGetResources(drm_fd);
 	igt_require(res);
 
@@ -111,5 +115,9 @@ igt_simple_main
 	kmstest_force_edid(drm_fd, connector, NULL);
 
 	drmModeFreeConnector(connector);
+
+	if (is_xe_device(drm_fd))
+		xe_device_put(drm_fd);
+
 	close(drm_fd);
 }
-- 
2.40.0

[igt-dev] [i-g-t V5 29/47] tests/kms_async_flips: No XE support

[Bhanuprakash Modem]

Async flips won't work with linear buffers on Intel hardware,
hence don't run tests on XE device as XE won't support tiling.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
---
 tests/kms_async_flips.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tests/kms_async_flips.c b/tests/kms_async_flips.c
index 1e6506e3d..51ffa523a 100644
--- a/tests/kms_async_flips.c
+++ b/tests/kms_async_flips.c
@@ -592,7 +592,13 @@ igt_main_args("e", NULL, help_str, opt_handler, &data)
 	int i;
 
 	igt_fixture {
-		data.drm_fd = drm_open_driver_master(DRIVER_ANY);
+		/*
+		 * FIXME: As of now, Async flips won't work with linear buffers
+		 * on Intel hardware, hence don't run tests on XE device as XE
+		 * won't support tiling.
+		 * Once Kernel changes got landed, please update this logic.
+		 */
+		data.drm_fd = drm_open_driver_master(DRIVER_ANY & ~DRIVER_XE);
 		kmstest_set_vt_graphics_mode();
 		igt_display_require(&data.display, data.drm_fd);
 		igt_display_require_output(&data.display);
-- 
2.40.0

[igt-dev] [i-g-t V5 30/47] tests/kms_atomic_transition: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Swati Sharma <swati2.sharma@intel.com>
---
 tests/kms_atomic_transition.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/kms_atomic_transition.c b/tests/kms_atomic_transition.c
index 7c7be578c..9f39d033d 100644
--- a/tests/kms_atomic_transition.c
+++ b/tests/kms_atomic_transition.c
@@ -136,7 +136,7 @@ static bool skip_plane(data_t *data, igt_plane_t *plane)
 	if (data->extended)
 		return false;
 
-	if (!is_i915_device(data->drm_fd))
+	if (!is_intel_device(data->drm_fd))
 		return false;
 
 	if (plane->type == DRM_PLANE_TYPE_CURSOR)
@@ -848,7 +848,7 @@ retry:
 		/* count enable pipes to set max iteration */
 		j += 1;
 
-		if (is_i915_device(data->drm_fd))
+		if (is_intel_device(data->drm_fd))
 			data->pipe_crcs[i] = igt_pipe_crc_new(data->drm_fd, i,
 							      IGT_PIPE_CRC_SOURCE_AUTO);
 
@@ -943,7 +943,7 @@ retry:
 			commit_display(data, i, nonblocking);
 			collect_crcs_mask(data->pipe_crcs, i, crcs[4]);
 
-			if (!is_i915_device(data->drm_fd))
+			if (!is_intel_device(data->drm_fd))
 				continue;
 
 			for (int k = 0; k < IGT_MAX_PIPES; k++) {
@@ -996,7 +996,7 @@ static void run_modeset_transition(data_t *data, int requested_outputs, bool non
 	unset_output_pipe(&data->display);
 	igt_display_commit2(&data->display, COMMIT_ATOMIC);
 
-	if (is_i915_device(data->drm_fd)) {
+	if (is_intel_device(data->drm_fd)) {
 		for_each_pipe(&data->display, pipe)
 			igt_pipe_crc_free(data->pipe_crcs[pipe]);
 	}
-- 
2.40.0

[igt-dev] [i-g-t V5 31/47] tests/color: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/chamelium/kms_chamelium_color.c |  2 +-
 tests/kms_color.c                     | 10 +++++-----
 tests/kms_color_helper.c              |  2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/tests/chamelium/kms_chamelium_color.c b/tests/chamelium/kms_chamelium_color.c
index b7c84ae4d..26239a6b8 100644
--- a/tests/chamelium/kms_chamelium_color.c
+++ b/tests/chamelium/kms_chamelium_color.c
@@ -680,7 +680,7 @@ igt_main
 
 	igt_fixture {
 		data.drm_fd = drm_open_driver_master(DRIVER_ANY);
-		if (is_i915_device(data.drm_fd))
+		if (is_intel_device(data.drm_fd))
 			data.devid = intel_get_drm_devid(data.drm_fd);
 
 		igt_display_require(&data.display, data.drm_fd);
diff --git a/tests/kms_color.c b/tests/kms_color.c
index cd03c1354..fdc7120c7 100644
--- a/tests/kms_color.c
+++ b/tests/kms_color.c
@@ -499,11 +499,11 @@ static bool test_pipe_ctm(data_t *data,
 	disable_gamma(primary->pipe);
 
 	/*
-	 * Only program LUT's for i915, but not for max CTM as limitation of
+	 * Only program LUT's for intel, but not for max CTM as limitation of
 	 * representing intermediate values between 0 and 1.0 causes
 	 * rounding issues and inaccuracies leading to crc mismatch.
 	 */
-	if (is_i915_device(data->drm_fd) && memcmp(before, after, sizeof(color_t))) {
+	if (is_intel_device(data->drm_fd) && memcmp(before, after, sizeof(color_t))) {
 		igt_require(igt_pipe_obj_has_prop(primary->pipe, IGT_CRTC_DEGAMMA_LUT));
 		igt_require(igt_pipe_obj_has_prop(primary->pipe, IGT_CRTC_GAMMA_LUT));
 
@@ -813,7 +813,7 @@ run_deep_color_tests_for_pipe(data_t *data, enum pipe p)
 			 0.0, 1.0, 0.0,
 			 1.0, 0.0, 1.0 };
 
-	if (is_i915_device(data->drm_fd))
+	if (is_intel_device(data->drm_fd))
 		igt_require_f((intel_display_ver(data->devid) >= 11),
 				"At least GEN 11 is required to validate Deep-color.\n");
 
@@ -833,7 +833,7 @@ run_deep_color_tests_for_pipe(data_t *data, enum pipe p)
 		igt_output_set_prop_value(output, IGT_CONNECTOR_MAX_BPC, 10);
 		igt_output_set_pipe(output, p);
 
-		if (is_i915_device(data->drm_fd) &&
+		if (is_intel_device(data->drm_fd) &&
 		    !igt_max_bpc_constraint(&data->display, p, output, 10))
 			continue;
 
@@ -1054,7 +1054,7 @@ igt_main
 
 	igt_fixture {
 		data.drm_fd = drm_open_driver_master(DRIVER_ANY);
-		if (is_i915_device(data.drm_fd))
+		if (is_intel_device(data.drm_fd))
 			data.devid = intel_get_drm_devid(data.drm_fd);
 		kmstest_set_vt_graphics_mode();
 
diff --git a/tests/kms_color_helper.c b/tests/kms_color_helper.c
index 2f9950f80..b01c38ef6 100644
--- a/tests/kms_color_helper.c
+++ b/tests/kms_color_helper.c
@@ -181,7 +181,7 @@ struct drm_color_lut *coeffs_to_lut(data_t *data,
 	uint32_t max_value = (1 << 16) - 1;
 	uint32_t mask;
 
-	if (is_i915_device(data->drm_fd))
+	if (is_intel_device(data->drm_fd))
 		mask = ((1 << color_depth) - 1) << (16 - color_depth);
 	else
 		mask = max_value;
-- 
2.40.0

[igt-dev] [i-g-t V5 32/47] tests/kms_concurrent: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_concurrent.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/kms_concurrent.c b/tests/kms_concurrent.c
index e6d61a84d..e1e581723 100644
--- a/tests/kms_concurrent.c
+++ b/tests/kms_concurrent.c
@@ -387,7 +387,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
 		kmstest_set_vt_graphics_mode();
 		igt_display_require(&data.display, data.drm_fd);
 		igt_require(data.display.is_atomic);
-		if (is_i915_device(data.drm_fd))
+		if (is_intel_device(data.drm_fd))
 			intel_allocator_multiprocess_start();
 	}
 
@@ -397,7 +397,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
 	}
 
 	igt_fixture {
-		if (is_i915_device(data.drm_fd))
+		if (is_intel_device(data.drm_fd))
 			intel_allocator_multiprocess_stop();
 		igt_display_fini(&data.display);
 		close(data.drm_fd);
-- 
2.40.0

[igt-dev] [i-g-t V5 33/47] tests/kms_content_protection: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_content_protection.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/tests/kms_content_protection.c b/tests/kms_content_protection.c
index 638e1301a..344cac505 100644
--- a/tests/kms_content_protection.c
+++ b/tests/kms_content_protection.c
@@ -392,7 +392,12 @@ static bool sink_hdcp_capable(igt_output_t *output)
 	if (fd < 0)
 		return false;
 
-	if (is_i915_device(data.drm_fd))
+	/*
+	 * FIXME: As of now XE's debugfs is using i915 namespace. Once Kernel
+	 * changes got landed, please update this logic to use XE specific
+	 * debugfs.
+	 */
+	if (is_intel_device(data.drm_fd))
 		debugfs_read(fd, "i915_hdcp_sink_capability", buf);
 	else
 		debugfs_read(fd, "hdcp_sink_capability", buf);
@@ -413,7 +418,8 @@ static bool sink_hdcp2_capable(igt_output_t *output)
 	if (fd < 0)
 		return false;
 
-	if (is_i915_device(data.drm_fd))
+	/* FIXME: XE specific debugfs as mentioned above. */
+	if (is_intel_device(data.drm_fd))
 		debugfs_read(fd, "i915_hdcp_sink_capability", buf);
 	else
 		debugfs_read(fd, "hdcp_sink_capability", buf);
@@ -763,7 +769,7 @@ static const struct {
 	  .content_type = HDCP_CONTENT_TYPE_1,
 	},
 	{ .desc = "Test the teardown and rebuild of the interface between "
-		  "I915 and mei hdcp.",
+		  "Intel and mei hdcp.",
 	  .name = "mei_interface",
 	  .cp_tests = CP_MEI_RELOAD,
 	  .content_type = HDCP_CONTENT_TYPE_1,
-- 
2.40.0

[igt-dev] [i-g-t V5 34/47] tests/kms_cursor_crc: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_cursor_crc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c
index cc9dfcb1d..3a353a032 100644
--- a/tests/kms_cursor_crc.c
+++ b/tests/kms_cursor_crc.c
@@ -143,7 +143,7 @@ static bool chv_cursor_broken(data_t *data, int x)
 {
 	uint32_t devid;
 
-	if (!is_i915_device(data->drm_fd))
+	if (!is_intel_device(data->drm_fd))
 		return false;
 
 	devid = intel_get_drm_devid(data->drm_fd);
@@ -152,7 +152,7 @@ static bool chv_cursor_broken(data_t *data, int x)
 	 * CHV gets a FIFO underrun on pipe C when cursor x coordinate
 	 * is negative and the cursor visible.
 	 *
-	 * i915 is fixed to return -EINVAL on cursor updates with those
+	 * intel is fixed to return -EINVAL on cursor updates with those
 	 * negative coordinates, so require cursor update to fail with
 	 * -EINVAL in that case.
 	 *
-- 
2.40.0

[igt-dev] [i-g-t V5 35/47] tests/kms_flip_event_leak: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_flip_event_leak.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/tests/kms_flip_event_leak.c b/tests/kms_flip_event_leak.c
index bc26597de..b79cd5030 100644
--- a/tests/kms_flip_event_leak.c
+++ b/tests/kms_flip_event_leak.c
@@ -29,6 +29,7 @@
 #include <string.h>
 
 #include "igt_device.h"
+#include "xe/xe_query.h"
 
 typedef struct {
 	int drm_fd;
@@ -64,6 +65,8 @@ static void test(data_t *data, enum pipe pipe, igt_output_t *output)
 	igt_device_drop_master(data->drm_fd);
 
 	igt_device_set_master(fd);
+	if (is_xe_device(fd))
+		xe_device_get(fd);
 
 	igt_create_fb(fd, mode->hdisplay, mode->vdisplay,
 		      DRM_FORMAT_XRGB8888,
@@ -74,6 +77,8 @@ static void test(data_t *data, enum pipe pipe, igt_output_t *output)
 			      data);
 	igt_assert_eq(ret, 0);
 
+	if (is_xe_device(fd))
+		xe_device_put(fd);
 	ret = close(fd);
 	igt_assert_eq(ret, 0);
 
-- 
2.40.0

[igt-dev] [i-g-t V5 36/47] tests/kms_getfb: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_getfb.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/tests/kms_getfb.c b/tests/kms_getfb.c
index 813417e77..4adc7eee2 100644
--- a/tests/kms_getfb.c
+++ b/tests/kms_getfb.c
@@ -42,6 +42,7 @@
 #include "drm_fourcc.h"
 #include "i915/gem_create.h"
 #include "igt_device.h"
+#include "xe/xe_query.h"
 
 IGT_TEST_DESCRIPTION("Tests GETFB and GETFB2 ioctls.");
 
@@ -91,7 +92,6 @@ static void get_ccs_fb(int fd, struct drm_mode_fb_cmd2 *ret)
 	uint32_t devid;
 
 	igt_require(has_addfb2_iface(fd));
-	igt_require_intel(fd);
 	devid = intel_get_drm_devid(fd);
 
 	if (HAS_FLATCCS(devid)) {
@@ -265,7 +265,7 @@ static void test_duplicate_handles(int fd)
 		struct drm_mode_fb_cmd2 add_ccs = { };
 		struct drm_mode_fb_cmd get = { };
 
-		igt_require(is_i915_device(fd));
+		igt_require_i915(fd);
 		igt_require_f(!HAS_FLATCCS(intel_get_drm_devid(fd)),
 			      "skip because flat ccs has only one buffer.\n");
 
@@ -340,6 +340,7 @@ static void test_getfb2(int fd)
 		struct drm_mode_fb_cmd2 get = { };
 		int i;
 
+		igt_require_i915(fd);
 		get_ccs_fb(fd, &add_ccs);
 		igt_require(add_ccs.fb_id != 0);
 		get.fb_id = add_ccs.fb_id;
@@ -398,6 +399,9 @@ static void test_handle_protection(void) {
 	igt_fixture {
 		non_master_fd = drm_open_driver(DRIVER_ANY);
 
+		if (is_xe_device(non_master_fd))
+			xe_device_get(non_master_fd);
+
 		non_master_add.width = 1024;
 		non_master_add.height = 1024;
 		non_master_add.pixel_format = DRM_FORMAT_XRGB8888;
@@ -444,6 +448,11 @@ static void test_handle_protection(void) {
 	igt_fixture {
 		do_ioctl(non_master_fd, DRM_IOCTL_MODE_RMFB, &non_master_add.fb_id);
 		gem_close(non_master_fd, non_master_add.handles[0]);
+
+		if (is_xe_device(non_master_fd))
+			xe_device_get(non_master_fd);
+
+		close(non_master_fd);
 	}
 }
 
@@ -454,6 +463,9 @@ igt_main
 	igt_fixture {
 		fd = drm_open_driver_master(DRIVER_ANY);
 		igt_require(has_getfb_iface(fd));
+
+		if (is_xe_device(fd))
+			xe_device_get(fd);
 	}
 
 	igt_subtest_group
@@ -468,6 +480,10 @@ igt_main
 	igt_subtest_group
 		test_handle_protection();
 
-	igt_fixture
+	igt_fixture {
+		if (is_xe_device(fd))
+			xe_device_put(fd);
+
 		close(fd);
+	}
 }
-- 
2.40.0

[igt-dev] [i-g-t V5 37/47] tests/kms_hdmi_inject: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_hdmi_inject.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/tests/kms_hdmi_inject.c b/tests/kms_hdmi_inject.c
index b6418faf0..2085d1453 100644
--- a/tests/kms_hdmi_inject.c
+++ b/tests/kms_hdmi_inject.c
@@ -29,6 +29,7 @@
 #include "igt.h"
 #include "igt_edid.h"
 #include "igt_eld.h"
+#include "xe/xe_query.h"
 
 #define HDISPLAY_4K	3840
 #define VDISPLAY_4K	2160
@@ -83,7 +84,7 @@ hdmi_inject_4k(int drm_fd, drmModeConnector *connector)
 	struct igt_fb fb;
 	uint8_t found_4k_mode = 0;
 
-	if (is_i915_device(drm_fd)) {
+	if (is_intel_device(drm_fd)) {
 		uint32_t devid = intel_get_drm_devid(drm_fd);
 
 		/* 4K requires at least HSW */
@@ -205,6 +206,9 @@ igt_main
 		igt_require(connector);
 
 		kmstest_unset_all_crtcs(drm_fd, res);
+
+		if (is_xe_device(drm_fd))
+			xe_device_get(drm_fd);
 	}
 
 	igt_describe("Make sure that 4K modes exposed by DRM match the "
@@ -219,6 +223,10 @@ igt_main
 
 	igt_fixture {
 		drmModeFreeConnector(connector);
+
+		if (is_xe_device(drm_fd))
+			xe_device_put(drm_fd);
+
 		close(drm_fd);
 	}
 }
-- 
2.40.0

[igt-dev] [i-g-t V5 38/47] tests/kms_hdr: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 tests/kms_hdr.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/kms_hdr.c b/tests/kms_hdr.c
index 23f12c14a..81a32dbf8 100644
--- a/tests/kms_hdr.c
+++ b/tests/kms_hdr.c
@@ -226,7 +226,7 @@ static void test_bpc_switch(data_t *data, uint32_t flags)
 			if (igt_pipe_connector_valid(pipe, output)) {
 				prepare_test(data, output, pipe);
 
-				if (is_i915_device(data->fd) &&
+				if (is_intel_device(data->fd) &&
 				    !igt_max_bpc_constraint(display, pipe, output, 10)) {
 					test_fini(data);
 					break;
@@ -503,7 +503,7 @@ static void test_static_swap(data_t *data, enum pipe pipe, igt_output_t *output)
 	igt_pipe_crc_collect_crc(data->pipe_crc, &ref_crc);
 
 	/* Change the mastering information, no modeset allowed
-	 * for amd driver, whereas a modeset is required for i915
+	 * for amd driver, whereas a modeset is required for intel
 	 * driver. */
 	hdr.hdmi_metadata_type1.max_display_mastering_luminance = 200;
 	hdr.hdmi_metadata_type1.max_fall = 200;
@@ -517,7 +517,7 @@ static void test_static_swap(data_t *data, enum pipe pipe, igt_output_t *output)
 
 	/* Enter SDR via metadata, no modeset allowed for
 	 * amd driver, whereas a modeset is required for
-	 * i915 driver. */
+	 * intel driver. */
 	fill_hdr_output_metadata_sdr(&hdr);
 	set_hdr_output_metadata(data, &hdr);
 	if (is_amdgpu_device(data->fd))
@@ -590,7 +590,7 @@ static void test_hdr(data_t *data, uint32_t flags)
 			if (igt_pipe_connector_valid(pipe, output)) {
 				prepare_test(data, output, pipe);
 
-				if (is_i915_device(data->fd) &&
+				if (is_intel_device(data->fd) &&
 				    !igt_max_bpc_constraint(display, pipe, output, 10)) {
 					test_fini(data);
 					break;
-- 
2.40.0

[igt-dev] [i-g-t V5 39/47] tests/kms_panel_fitting: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 tests/kms_panel_fitting.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/tests/kms_panel_fitting.c b/tests/kms_panel_fitting.c
index 2d0590da2..97ef1ae48 100644
--- a/tests/kms_panel_fitting.c
+++ b/tests/kms_panel_fitting.c
@@ -23,6 +23,7 @@
  */
 
 #include "igt.h"
+#include <limits.h>
 #include <math.h>
 #include <sys/stat.h>
 
@@ -133,7 +134,7 @@ test_panel_fitting_legacy(data_t *d, igt_display_t *display,
 	igt_fb_set_size(&d->fb2, d->plane2, d->fb2.width-200, d->fb2.height-200);
 	igt_plane_set_position(d->plane2, 100, 100);
 
-	if (is_i915_device(display->drm_fd)) {
+	if (is_intel_device(display->drm_fd)) {
 		uint32_t devid = intel_get_drm_devid(display->drm_fd);
 		/*
 		 * Most of gen7 and all of gen8 doesn't support plane scaling
@@ -233,10 +234,15 @@ static void test_panel_fitting(data_t *data, enum test_type type)
 	struct stat sb;
 
 	if (type == TEST_ATOMIC) {
-		igt_require_f(is_i915_device(display->drm_fd), "not valid for non-i915 devices\n");
+		char path[PATH_MAX];
+
+		igt_require_f(is_intel_device(display->drm_fd), "not valid for non-intel devices\n");
 
 		/* Until this is force enabled, force modeset evasion. */
-		if (stat("/sys/module/i915/parameters/fastboot", &sb) == 0)
+		snprintf(path, PATH_MAX, "/sys/module/%s/parameters/fastboot",
+					 is_i915_device(data->drm_fd) ? "i915" : "xe");
+
+		if (stat(path, &sb) == 0)
 			igt_set_module_param_int(data->drm_fd, "fastboot", 1);
 
 		igt_require(intel_display_ver(intel_get_drm_devid(display->drm_fd)) >= 5);
-- 
2.40.0

[igt-dev] [i-g-t V5 40/47] tests/kms_plane: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_plane.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/tests/kms_plane.c b/tests/kms_plane.c
index 62aee9ad0..10e16b638 100644
--- a/tests/kms_plane.c
+++ b/tests/kms_plane.c
@@ -30,6 +30,7 @@
 #include <stdbool.h>
 #include <stdio.h>
 #include <string.h>
+#include "xe/xe_query.h"
 
 /*
  * Throw away enough lsbs in pixel formats tests
@@ -399,6 +400,18 @@ test_plane_panning(data_t *data, enum pipe pipe)
 
 	}
 
+	if (is_xe_device(data->drm_fd)) {
+		struct drm_xe_query_mem_region *memregion;
+		uint64_t memreg = all_memory_regions(data->drm_fd), region;
+
+		xe_for_each_mem_region(data->drm_fd, memreg, region) {
+			memregion = xe_mem_region(data->drm_fd, region);
+
+			if (XE_IS_CLASS_VRAM(memregion))
+				mem_size = memregion->total_size;
+		}
+	}
+
 	for_each_connector_mode(output) {
 		drmModeModeInfo *m = &output->config.connector->modes[j__];
 		uint32_t fb_size = m->hdisplay * m->vdisplay * 4;
@@ -976,6 +989,10 @@ static bool test_format_plane(data_t *data, enum pipe pipe,
 			.modifier = plane->modifiers[i],
 		};
 
+		if (is_xe_device(data->drm_fd) &&
+		    f.modifier != DRM_FORMAT_MOD_LINEAR)
+			continue;
+
 		if (f.format == ref.format &&
 		    f.modifier == ref.modifier)
 			continue;
@@ -1050,7 +1067,7 @@ static bool skip_plane(data_t *data, igt_plane_t *plane)
 	if (data->extended)
 		return false;
 
-	if (!is_i915_device(data->drm_fd))
+	if (!is_intel_device(data->drm_fd))
 		return false;
 
 	if (plane->type == DRM_PLANE_TYPE_CURSOR)
-- 
2.40.0

[igt-dev] [i-g-t V5 41/47] tests/kms_plane_lowers: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_plane_lowres.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/tests/kms_plane_lowres.c b/tests/kms_plane_lowres.c
index 958d3ec6f..db9f5a54c 100644
--- a/tests/kms_plane_lowres.c
+++ b/tests/kms_plane_lowres.c
@@ -266,8 +266,11 @@ static void run_test(data_t *data, uint64_t modifier)
 	enum pipe pipe;
 	igt_output_t *output;
 
-	igt_skip_on(!igt_display_has_format_mod(&data->display,
-						DRM_FORMAT_XRGB8888, modifier));
+	if(!igt_display_has_format_mod(&data->display, DRM_FORMAT_XRGB8888, modifier))
+		return;
+
+	if (is_xe_device(data->drm_fd) && modifier != DRM_FORMAT_MOD_LINEAR)
+		return;
 
 	for_each_pipe(&data->display, pipe) {
 		for_each_valid_output_on_pipe(&data->display, pipe, output) {
@@ -318,7 +321,7 @@ igt_main
 
 	igt_fixture {
 		data.drm_fd = drm_open_driver_master(DRIVER_ANY);
-		data.devid = is_i915_device(data.drm_fd) ?
+		data.devid = is_intel_device(data.drm_fd) ?
 			intel_get_drm_devid(data.drm_fd) : 0;
 
 		kmstest_set_vt_graphics_mode();
-- 
2.40.0

[igt-dev] [i-g-t V5 42/47] tests/kms_plane_scaling: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_plane_scaling.c | 41 ++++++++++++++++++++++-----------------
 1 file changed, 23 insertions(+), 18 deletions(-)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 19528a405..a37abd16d 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -52,9 +52,9 @@ struct invalid_paramtests {
 	} params[8];
 };
 
-static const struct invalid_paramtests i915_paramtests[] = {
+static const struct invalid_paramtests intel_paramtests[] = {
 	{
-		.testname = "i915-max-src-size",
+		.testname = "intel-max-src-size",
 		.planesize = {3840, 2160},
 	},
 };
@@ -463,7 +463,7 @@ static const igt_rotation_t rotations[] = {
 
 static bool can_scale(data_t *d, unsigned format)
 {
-	if (!is_i915_device(d->drm_fd))
+	if (!is_intel_device(d->drm_fd))
 		return true;
 
 	switch (format) {
@@ -488,7 +488,7 @@ static bool test_format(data_t *data,
 	if (!igt_fb_supported_format(format))
 		return false;
 
-	if (!is_i915_device(data->drm_fd) ||
+	if (!is_intel_device(data->drm_fd) ||
 	    data->extended)
 		return true;
 
@@ -505,7 +505,7 @@ static bool test_format(data_t *data,
 
 static bool test_pipe_iteration(data_t *data, enum pipe pipe, int iteration)
 {
-	if (!is_i915_device(data->drm_fd) ||
+	if (!is_intel_device(data->drm_fd) ||
 	    data->extended)
 		return true;
 
@@ -544,6 +544,10 @@ static void test_scaler_with_modifier_pipe(data_t *d,
 		for (int i = 0; i < ARRAY_SIZE(modifiers); i++) {
 			uint64_t modifier = modifiers[i];
 
+			if (is_xe_device(d->drm_fd) &&
+			    modifier != DRM_FORMAT_MOD_LINEAR)
+				continue;
+
 			if (igt_plane_has_format_mod(plane, format, modifier))
 				check_scaling_pipe_plane_rot(d, plane,
 							     format, modifier,
@@ -829,11 +833,12 @@ test_invalid_num_scalers(data_t *d, enum pipe pipe, igt_output_t *output)
 	igt_plane_set_size(plane[1], mode->hdisplay, mode->vdisplay);
 	igt_plane_set_size(plane[2], mode->hdisplay, mode->vdisplay);
 
-	/* This commit is expected to fail for i915 devices. i915 devices support
+	/*
+	 * This commit is expected to fail for intel devices. intel devices support
 	 * max 2 scalers/pipe. In dmesg we can find: Too many scaling requests 3 > 2.
-	 * For devices (non-i915, or possible future i915) that are able to perform this
-	 * amount of scaling; handle that case aswell.
-	 * */
+	 * For devices (non-intel, or possible future intel) that are able to perform
+	 * this amount of scaling; handle that case aswell.
+	 */
 	ret = igt_display_try_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
 	igt_skip_on_f(ret == 0, "Cannot test handling of too many scaling ops, the device supports a large amount.\n");
 	igt_assert(ret == -EINVAL || ret == -ERANGE);
@@ -1010,7 +1015,7 @@ static drmModeModeInfo *find_mode(data_t *data, igt_output_t *output, const uint
 }
 
 /*
- *	Max source/destination width/height for i915 driver.
+ *	Max source/destination width/height for intel driver.
  *	These numbers are coming from
  *	drivers/gpu/drm/i915/display/skl_scaler.c in kernel sources.
  *
@@ -1038,8 +1043,8 @@ static drmModeModeInfo *find_mode(data_t *data, igt_output_t *output, const uint
  *		max_dst_w = 8192
  *		max_dst_h = 8192
  */
-static void i915_max_source_size_test(data_t *d, enum pipe pipe, igt_output_t *output,
-				      drmModeModeInfo *mode, const uint32_t planesize[])
+static void intel_max_source_size_test(data_t *d, enum pipe pipe, igt_output_t *output,
+				       drmModeModeInfo *mode, const uint32_t planesize[])
 {
 	igt_fb_t fb;
 	igt_plane_t *plane;
@@ -1117,7 +1122,7 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 	igt_fixture {
 		data.drm_fd = drm_open_driver_master(DRIVER_ANY);
 		igt_display_require(&data.display, data.drm_fd);
-		data.devid = is_i915_device(data.drm_fd) ?
+		data.devid = is_intel_device(data.drm_fd) ?
 			intel_get_drm_devid(data.drm_fd) : 0;
 		igt_require(data.display.is_atomic);
 	}
@@ -1271,9 +1276,9 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 			}
 		}
 
-		for (int index = 0; index < ARRAY_SIZE(i915_paramtests); index++) {
+		for (int index = 0; index < ARRAY_SIZE(intel_paramtests); index++) {
 			igt_describe("Test for validating max source size.");
-			igt_subtest_with_dynamic(i915_paramtests[index].testname) {
+			igt_subtest_with_dynamic(intel_paramtests[index].testname) {
 				igt_require_intel(data.drm_fd);
 				for_each_pipe(&data.display, pipe) {
 					for_each_valid_output_on_pipe(&data.display, pipe, output) {
@@ -1282,12 +1287,12 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 						 * Need to find mode with lowest vrefresh else
 						 * we can exceed cdclk limits.
 						 */
-						mode = find_mode(&data, output, i915_paramtests[index].planesize);
+						mode = find_mode(&data, output, intel_paramtests[index].planesize);
 						if (mode) {
 							igt_dynamic_f("pipe-%s-%s",
 								       kmstest_pipe_name(pipe), igt_output_name(output))
-								i915_max_source_size_test(&data, pipe, output, mode,
-											  i915_paramtests[index].planesize);
+								intel_max_source_size_test(&data, pipe, output, mode,
+											   intel_paramtests[index].planesize);
 						}
 						continue;
 					}
-- 
2.40.0

[igt-dev] [i-g-t V5 43/47] tests/kms_prime: Use Rendercopy instead of Blit

[Bhanuprakash Modem]

Instead of using Blitter, use Rendercopy to export the color
frame buffer.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_prime.c | 71 ++++++++++++++++++++++++++++++++---------------
 1 file changed, 48 insertions(+), 23 deletions(-)

diff --git a/tests/kms_prime.c b/tests/kms_prime.c
index dd5ab993e..0828bf6b5 100644
--- a/tests/kms_prime.c
+++ b/tests/kms_prime.c
@@ -150,35 +150,60 @@ static void prepare_fb(int importer_fd, struct dumb_bo *scratch, struct igt_fb *
 		    color_encoding, color_range);
 }
 
+static struct intel_buf * create_buf(int fd, struct buf_ops *bops, int width,
+				     int height, uint32_t gem_handle)
+{
+	struct intel_buf *buf;
+	uint32_t name, handle;
+
+	name = gem_flink(fd, gem_handle);
+	handle = gem_open(fd, name);
+
+	buf = intel_buf_create_using_handle(bops, handle,
+					    width, height, 32, 0,
+					    I915_TILING_NONE, 0);
+
+	/* Make sure we close handle on destroy path */
+	intel_buf_set_ownership(buf, true);
+	return buf;
+}
+
 static void import_fb(int importer_fd, struct igt_fb *fb,
 		      int dmabuf_fd, uint32_t pitch)
 {
 	uint32_t offsets[4] = {}, pitches[4] = {}, handles[4] = {}, temp_buf_handle;
 	int ret;
 
-	if (is_i915_device(importer_fd)) {
-		if (gem_has_lmem(importer_fd)) {
-			uint64_t ahnd = get_reloc_ahnd(importer_fd, 0);
-			uint64_t fb_size = 0;
-
-			igt_info("Importer is dGPU\n");
-			temp_buf_handle = prime_fd_to_handle(importer_fd, dmabuf_fd);
-			igt_assert(temp_buf_handle > 0);
-			fb->gem_handle = igt_create_bo_with_dimensions(importer_fd, fb->width, fb->height,
-								       fb->drm_format, fb->modifier, pitch, &fb_size, NULL, NULL);
-			igt_assert(fb->gem_handle > 0);
-
-			igt_blitter_src_copy(importer_fd, ahnd, 0, NULL, temp_buf_handle,
-					     0, pitch, fb->modifier, 0, 0, fb_size, fb->width,
-					     fb->height, 32, fb->gem_handle, 0, pitch, fb->modifier,
-					     0, 0, fb_size);
-
-			gem_sync(importer_fd, fb->gem_handle);
-			gem_close(importer_fd, temp_buf_handle);
-			put_ahnd(ahnd);
-		} else {
-			fb->gem_handle = prime_fd_to_handle(importer_fd, dmabuf_fd);
-		}
+	if (is_i915_device(importer_fd) && gem_has_lmem(importer_fd)) {
+		uint32_t devid = intel_get_drm_devid(importer_fd);
+		struct buf_ops *bops = buf_ops_create(importer_fd);
+		igt_render_copyfunc_t rendercopy = igt_get_render_copyfunc(devid);
+		struct intel_bb *ibb = intel_bb_create(importer_fd, 4096);
+		struct intel_buf *src, *dst;
+		uint32_t *ptr;
+		uint64_t fb_size = 0;
+
+		igt_info("Importer is dGPU\n");
+		temp_buf_handle = prime_fd_to_handle(importer_fd, dmabuf_fd);
+		igt_assert(temp_buf_handle > 0);
+		fb->gem_handle = igt_create_bo_with_dimensions(importer_fd, fb->width, fb->height,
+							       fb->drm_format, fb->modifier, pitch, &fb_size, NULL, NULL);
+		igt_assert(fb->gem_handle > 0);
+
+		ptr = gem_mmap__device_coherent(importer_fd, temp_buf_handle, 0,
+						ALIGN(fb_size, 4096),
+						PROT_READ | PROT_WRITE);
+
+		src = create_buf(importer_fd, bops, fb->width, fb->height, temp_buf_handle);
+		dst = create_buf(importer_fd, bops, fb->width, fb->height, fb->gem_handle);
+		rendercopy(ibb, src, 0, 0, fb->width, fb->height, dst, 0, 0);
+
+		igt_assert(gem_munmap(ptr, fb_size) == 0);
+		intel_bb_destroy(ibb);
+		intel_buf_destroy(src);
+		intel_buf_destroy(dst);
+		buf_ops_destroy(bops);
+		gem_close(importer_fd, temp_buf_handle);
 	} else {
 		fb->gem_handle = prime_fd_to_handle(importer_fd, dmabuf_fd);
 	}
-- 
2.40.0

[igt-dev] [i-g-t V5 44/47] tests/kms_prime: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

V2: - Use rendercopy method for both i915 & xe
    - Minor cleanup
V3: - New patch for cleanup & rendercopy

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
 tests/kms_prime.c | 183 ++++++++++++++++++++++++++++++++++++----------
 1 file changed, 146 insertions(+), 37 deletions(-)

diff --git a/tests/kms_prime.c b/tests/kms_prime.c
index 0828bf6b5..4442104a0 100644
--- a/tests/kms_prime.c
+++ b/tests/kms_prime.c
@@ -27,9 +27,12 @@
 #include "igt_sysfs.h"
 #include <fcntl.h>
 
+#include <limits.h>
 #include <sys/ioctl.h>
 #include <sys/poll.h>
 #include <time.h>
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
 
 #define KMS_HELPER "/sys/module/drm_kms_helper/parameters/"
 #define KMS_POLL_DISABLE 0
@@ -112,7 +115,29 @@ static void prepare_scratch(int exporter_fd, struct dumb_bo *scratch,
 	scratch->height = mode->vdisplay;
 	scratch->bpp = 32;
 
-	if (!is_i915_device(exporter_fd)) {
+	if (is_intel_device(exporter_fd)) {
+		igt_calc_fb_size(exporter_fd, mode->hdisplay, mode->vdisplay, DRM_FORMAT_XRGB8888,
+				 DRM_FORMAT_MOD_LINEAR, &scratch->size, &scratch->pitch);
+
+		if (is_i915_device(exporter_fd)) {
+			if (gem_has_lmem(exporter_fd))
+				scratch->handle = gem_create_in_memory_regions(exporter_fd, scratch->size,
+								       REGION_LMEM(0), REGION_SMEM);
+			else
+				scratch->handle = gem_create_in_memory_regions(exporter_fd, scratch->size,
+								       REGION_SMEM);
+
+			ptr = gem_mmap__device_coherent(exporter_fd, scratch->handle, 0,
+							scratch->size, PROT_WRITE | PROT_READ);
+		} else {
+			scratch->handle = xe_bo_create_flags(exporter_fd, 0,
+							     ALIGN(scratch->size, xe_get_default_alignment(exporter_fd)),
+							     vram_if_possible(exporter_fd, 0));
+
+			ptr = xe_bo_mmap_ext(exporter_fd, scratch->handle,
+					     scratch->size, PROT_READ | PROT_WRITE);
+		}
+	} else {
 		scratch->handle = kmstest_dumb_create(exporter_fd,
 						      ALIGN(scratch->width, 256),
 						      scratch->height, scratch->bpp,
@@ -120,18 +145,6 @@ static void prepare_scratch(int exporter_fd, struct dumb_bo *scratch,
 
 		ptr = kmstest_dumb_map_buffer(exporter_fd, scratch->handle,
 					      scratch->size, PROT_WRITE);
-	} else {
-		igt_calc_fb_size(exporter_fd, mode->hdisplay, mode->vdisplay, DRM_FORMAT_XRGB8888,
-				 DRM_FORMAT_MOD_LINEAR, &scratch->size, &scratch->pitch);
-		if (gem_has_lmem(exporter_fd))
-			scratch->handle = gem_create_in_memory_regions(exporter_fd, scratch->size,
-								       REGION_LMEM(0), REGION_SMEM);
-		else
-			scratch->handle = gem_create_in_memory_regions(exporter_fd, scratch->size,
-								       REGION_SMEM);
-
-		ptr = gem_mmap__device_coherent(exporter_fd, scratch->handle, 0, scratch->size,
-						PROT_WRITE | PROT_READ);
 	}
 
 	for (size_t idx = 0; idx < scratch->size / sizeof(*ptr); ++idx)
@@ -151,17 +164,21 @@ static void prepare_fb(int importer_fd, struct dumb_bo *scratch, struct igt_fb *
 }
 
 static struct intel_buf * create_buf(int fd, struct buf_ops *bops, int width,
-				     int height, uint32_t gem_handle)
+				     int height, uint64_t size, uint32_t gem_handle)
 {
 	struct intel_buf *buf;
 	uint32_t name, handle;
+	uint64_t region = (buf_ops_get_driver(bops) == INTEL_DRIVER_XE) ?
+						vram_if_possible(fd, 0) : -1;
 
 	name = gem_flink(fd, gem_handle);
 	handle = gem_open(fd, name);
 
-	buf = intel_buf_create_using_handle(bops, handle,
-					    width, height, 32, 0,
-					    I915_TILING_NONE, 0);
+	buf = intel_buf_create_full(bops, handle,
+				    width, height, 32, 0,
+				    I915_TILING_NONE, 0,
+				    size, 0,
+				    region);
 
 	/* Make sure we close handle on destroy path */
 	intel_buf_set_ownership(buf, true);
@@ -174,7 +191,8 @@ static void import_fb(int importer_fd, struct igt_fb *fb,
 	uint32_t offsets[4] = {}, pitches[4] = {}, handles[4] = {}, temp_buf_handle;
 	int ret;
 
-	if (is_i915_device(importer_fd) && gem_has_lmem(importer_fd)) {
+	if ((is_i915_device(importer_fd) && gem_has_lmem(importer_fd)) ||
+	    (is_xe_device(importer_fd) && xe_has_vram(importer_fd)))  {
 		uint32_t devid = intel_get_drm_devid(importer_fd);
 		struct buf_ops *bops = buf_ops_create(importer_fd);
 		igt_render_copyfunc_t rendercopy = igt_get_render_copyfunc(devid);
@@ -190,12 +208,18 @@ static void import_fb(int importer_fd, struct igt_fb *fb,
 							       fb->drm_format, fb->modifier, pitch, &fb_size, NULL, NULL);
 		igt_assert(fb->gem_handle > 0);
 
-		ptr = gem_mmap__device_coherent(importer_fd, temp_buf_handle, 0,
-						ALIGN(fb_size, 4096),
-						PROT_READ | PROT_WRITE);
+		if (is_i915_device(importer_fd)) {
+			ptr = gem_mmap__device_coherent(importer_fd, temp_buf_handle, 0,
+							ALIGN(fb_size, 4096),
+							PROT_READ | PROT_WRITE);
+		} else {
+			ptr = xe_bo_mmap_ext(importer_fd, temp_buf_handle,
+					     ALIGN(fb_size, xe_get_default_alignment(importer_fd)),
+					     PROT_READ | PROT_WRITE);
+		}
 
-		src = create_buf(importer_fd, bops, fb->width, fb->height, temp_buf_handle);
-		dst = create_buf(importer_fd, bops, fb->width, fb->height, fb->gem_handle);
+		src = create_buf(importer_fd, bops, fb->width, fb->height, fb_size, temp_buf_handle);
+		dst = create_buf(importer_fd, bops, fb->width, fb->height, fb_size, fb->gem_handle);
 		rendercopy(ibb, src, 0, 0, fb->width, fb->height, dst, 0, 0);
 
 		igt_assert(gem_munmap(ptr, fb_size) == 0);
@@ -355,12 +379,6 @@ static bool has_connected_output(int drm_fd)
 	return false;
 }
 
-static void validate_d3_hot(int drm_fd)
-{
-	igt_assert(igt_debugfs_search(drm_fd, "i915_runtime_pm_status", "GPU idle: yes"));
-	igt_assert(igt_debugfs_search(drm_fd, "i915_runtime_pm_status", "PCI device power state: D3hot [3]"));
-}
-
 static void kms_poll_state_restore(void)
 {
 	int sysfs_fd;
@@ -382,6 +400,88 @@ static void kms_poll_disable(void)
 	close(sysfs_fd);
 }
 
+static bool runtime_usage_available(struct pci_device *pci)
+{
+	char name[PATH_MAX];
+	snprintf(name, PATH_MAX, "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/runtime_usage",
+		 pci->domain, pci->bus, pci->dev, pci->func);
+	return access(name, F_OK) == 0;
+}
+
+static bool in_d3_hot(struct pci_device *pci)
+{
+	uint16_t val;
+
+	/* We need to wait for the autosuspend to kick in before we can check */
+	if (!igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED))
+		return false;
+
+	if (runtime_usage_available(pci) &&
+	    igt_pm_get_runtime_usage(pci) != 0)
+		return false;
+
+	igt_assert_eq(pci_device_cfg_read_u16(pci, &val, 0xd4), 0);
+
+	return (val & 0x3) == 0x3;
+}
+
+static void validate_d3_hot(int drm_fd, struct pci_device *pci)
+{
+	if (is_i915_device(drm_fd)) {
+		igt_assert(igt_debugfs_search(drm_fd, "i915_runtime_pm_status", "GPU idle: yes"));
+		igt_assert(igt_debugfs_search(drm_fd, "i915_runtime_pm_status", "PCI device power state: D3hot [3]"));
+	} else {
+		igt_assert(in_d3_hot(pci));
+	}
+}
+
+static int open_d3_allowed(struct pci_device *pci)
+{
+	char name[PATH_MAX];
+	int fd;
+
+	snprintf(name, PATH_MAX, "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/d3cold_allowed",
+		 pci->domain, pci->bus, pci->dev, pci->func);
+
+	fd = open(name, O_RDWR);
+	igt_assert_f(fd >= 0, "Can't open %s\n", name);
+
+	return fd;
+}
+
+static void get_d3_allowed(struct pci_device *pci, char *d3_allowed)
+{
+	int fd = open_d3_allowed(pci);
+
+	igt_assert(read(fd, d3_allowed, 2));
+	close(fd);
+}
+
+static void set_d3_allowed(struct pci_device *pci, const char *d3_allowed)
+{
+	int fd = open_d3_allowed(pci);
+
+	igt_assert(write(fd, d3_allowed, 2));
+	close(fd);
+}
+
+static void setup_d3_hot(int fd, struct pci_device *pci)
+{
+	if (is_xe_device(fd)) {
+		igt_assert(igt_setup_runtime_pm(fd));
+
+		set_d3_allowed(pci, "0\n");
+
+		igt_assert(in_d3_hot(pci));
+	} else {
+		igt_set_timeout(10, "Wait for dGPU to enter D3hot before starting the subtest");
+		while (!igt_debugfs_search(fd,
+			"i915_runtime_pm_status",
+			"PCI device power state: D3hot [3]"));
+		igt_reset_timeout();
+	}
+}
+
 igt_main
 {
 	int first_fd = -1;
@@ -435,21 +535,28 @@ igt_main
 
 		igt_describe("Validate pci state of dGPU when dGPU is idle and  scanout is on iGPU");
 		igt_subtest("D3hot") {
-			igt_require_f(is_i915_device(second_fd_hybrid), "i915 device required\n");
-			igt_require_f(gem_has_lmem(second_fd_hybrid), "Second GPU is not dGPU\n");
+			char d3_allowed[2];
+			struct pci_device *pci;
+
+			igt_require_f(is_intel_device(second_fd_hybrid), "intel device required\n");
+			if (is_i915_device(second_fd_hybrid))
+				igt_require_f(gem_has_lmem(second_fd_hybrid), "Second GPU is not dGPU\n");
+			else
+				igt_require_f(xe_has_vram(second_fd_hybrid), "Second GPU is not dGPU\n");
 			igt_require_f(first_output, "No display connected to iGPU\n");
 			igt_require_f(!second_output, "Display connected to dGPU\n");
 
 			kms_poll_disable();
 
-			igt_set_timeout(10, "Wait for dGPU to enter D3hot before starting the subtest");
-			while (!igt_debugfs_search(second_fd_hybrid,
-			       "i915_runtime_pm_status",
-			       "PCI device power state: D3hot [3]"));
-			igt_reset_timeout();
+			pci = igt_device_get_pci_device(second_fd_hybrid);
+			get_d3_allowed(pci, d3_allowed);
+
+			setup_d3_hot(second_fd_hybrid, pci);
 
 			test_basic_modeset(first_fd);
-			validate_d3_hot(second_fd_hybrid);
+			validate_d3_hot(second_fd_hybrid, pci);
+
+			set_d3_allowed(pci, d3_allowed);
 		}
 
 		igt_fixture {
@@ -467,6 +574,8 @@ igt_main
 			igt_require(second_fd_vgem >= 0);
 			if (is_i915_device(first_fd))
 				igt_require(!gem_has_lmem(first_fd));
+			if (is_xe_device(first_fd))
+				igt_require(!xe_has_vram(first_fd));
 		}
 
 		igt_describe("Make a dumb color buffer, export to another device and"
-- 
2.40.0

[igt-dev] [i-g-t V5 45/47] tests/kms_rotation_crc: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

V2: - Drop i915 check for bad-tiling test.
    - Skip exhaust-fences as it needs Y-tiling

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Swati Sharma <swati2.sharma@intel.com>
---
 tests/kms_rotation_crc.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 295aed762..28b4fd27c 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -459,7 +459,7 @@ static bool test_format(data_t *data,
 	if (!igt_fb_supported_format(format))
 		return false;
 
-	if (!is_i915_device(data->gfx_fd) ||
+	if (!is_intel_device(data->gfx_fd) ||
 	    data->extended)
 		return true;
 
@@ -545,14 +545,14 @@ static void test_plane_rotation(data_t *data, int plane_type, bool test_bad_form
 		igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
 		igt_require(igt_plane_has_rotation(plane, data->rotation));
 		/* CHV can't rotate and reflect simultaneously */
-		igt_require(!is_i915_device(data->gfx_fd) ||
+		igt_require(!is_intel_device(data->gfx_fd) ||
 			    !IS_CHERRYVIEW(data->devid) ||
 			    data->rotation != (IGT_ROTATION_180 | IGT_REFLECT_X));
 
 		prepare_crtc(data, output, pipe, plane, true);
 
 		for (i = 0; i < num_rectangle_types; i++) {
-			/* Unsupported on i915 */
+			/* Unsupported on intel */
 			if (plane_type == DRM_PLANE_TYPE_CURSOR &&
 			    i != square)
 				continue;
@@ -560,9 +560,8 @@ static void test_plane_rotation(data_t *data, int plane_type, bool test_bad_form
 			/* Only support partial covering primary plane on gen9+ */
 			if (is_amdgpu_device(data->gfx_fd) ||
 				(plane_type == DRM_PLANE_TYPE_PRIMARY &&
-				 is_i915_device(data->gfx_fd) &&
-				 intel_display_ver(
-					 intel_get_drm_devid(data->gfx_fd)) < 9)) {
+				 is_intel_device(data->gfx_fd) &&
+				 intel_display_ver(data->devid) < 9)) {
 				if (i != rectangle)
 					continue;
 				else
@@ -592,7 +591,7 @@ static void test_plane_rotation(data_t *data, int plane_type, bool test_bad_form
 						 data->override_fmt, test_bad_format);
 			}
 		}
-		if (is_i915_device(data->gfx_fd)) {
+		if (is_intel_device(data->gfx_fd)) {
 			igt_pipe_crc_stop(data->pipe_crc);
 		}
 	}
@@ -841,6 +840,10 @@ static void test_multi_plane_rotation(data_t *data, enum pipe pipe)
 		igt_pipe_crc_start(data->pipe_crc);
 
 		for (i = 0; i < ARRAY_SIZE(planeconfigs); i++) {
+			if (is_xe_device(data->gfx_fd) &&
+			    planeconfigs[i].modifier != DRM_FORMAT_MOD_LINEAR)
+				continue;
+
 			p[0].fbinfo = &planeconfigs[i];
 			pointlocation(data, p, mode, 0);
 
@@ -1137,7 +1140,7 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 
 	igt_fixture {
 		data.gfx_fd = drm_open_driver_master(DRIVER_ANY);
-		if (is_i915_device(data.gfx_fd)) {
+		if (is_intel_device(data.gfx_fd)) {
 			data.devid = intel_get_drm_devid(data.gfx_fd);
 			gen = intel_display_ver(data.devid);
 		}
@@ -1201,6 +1204,9 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 
 	igt_describe("Tiling and Rotation test for gen 10+ for primary plane");
 	for (reflect_x = reflect_x_subtests; reflect_x->modifier; reflect_x++) {
+		igt_fixture
+			igt_require_i915(data.gfx_fd);
+
 		igt_subtest_f("primary-%s-reflect-x-%s",
 			      modifier_test_str(reflect_x->modifier),
 			      rot_test_str(reflect_x->rot)) {
@@ -1260,6 +1266,7 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 		enum pipe pipe;
 		igt_output_t *output;
 
+		igt_require_i915(data.gfx_fd);
 		igt_display_require_output(&data.display);
 
 		for_each_pipe_with_valid_output(&data.display, pipe, output) {
-- 
2.40.0

[igt-dev] [i-g-t V5 46/47] tests/kms_setmode: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Nidhi Gupta <nidhi1.gupta@intel.com>
---
 tests/kms_setmode.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/tests/kms_setmode.c b/tests/kms_setmode.c
index bfa108916..a611d9382 100644
--- a/tests/kms_setmode.c
+++ b/tests/kms_setmode.c
@@ -30,6 +30,7 @@
 #include <string.h>
 #include <sys/time.h>
 #include <math.h>
+#include "xe/xe_query.h"
 
 #define MAX_CONNECTORS  10
 #define MAX_CRTCS       6
@@ -954,6 +955,9 @@ igt_main_args("det:", NULL, help_str, opt_handler, NULL)
 
 		drm_resources = drmModeGetResources(drm_fd);
 		igt_require(drm_resources);
+
+		if (is_xe_device(drm_fd))
+			xe_device_get(drm_fd);
 	}
 
 	for (i = 0; i < ARRAY_SIZE(tests); i++) {
@@ -971,6 +975,9 @@ igt_main_args("det:", NULL, help_str, opt_handler, NULL)
 	igt_fixture {
 		drmModeFreeResources(drm_resources);
 
+		if (is_xe_device(drm_fd))
+			xe_device_put(drm_fd);
+
 		close(drm_fd);
 	}
 }
-- 
2.40.0

[igt-dev] [i-g-t V5 47/47] tests/kms_universal_plane: Add XE support

[Bhanuprakash Modem]

Add XE driver support for kms tests.

Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Reviewed-by: Nidhi Gupta <nidhi1.gupta@intel.com>
---
 tests/kms_universal_plane.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/tests/kms_universal_plane.c b/tests/kms_universal_plane.c
index b2435b517..635a136ab 100644
--- a/tests/kms_universal_plane.c
+++ b/tests/kms_universal_plane.c
@@ -577,13 +577,18 @@ cursor_leak_test_fini(data_t *data,
 }
 
 static int
-i915_gem_fb_count(data_t *data)
+intel_gem_fb_count(data_t *data)
 {
 	char buf[1024];
 	FILE *fp;
 	int fd;
 	int count = 0;
 
+	/*
+	 * FIXME: As of now, XE's debugfs is using i915 namespace. Once Kernel
+	 * changes got landed, please update this logic to use XE specific
+	 * debugfs.
+	 */
 	fd = igt_debugfs_open(data->drm_fd, "i915_gem_framebuffer", O_RDONLY);
 	fp = fdopen(fd, "r");
 	igt_require(fp);
@@ -618,7 +623,7 @@ cursor_leak_test_pipe(data_t *data, enum pipe pipe, igt_output_t *output)
 	mode = igt_output_get_mode(output);
 
 	/* Count GEM framebuffers before creating our cursor FB's */
-	count1 = i915_gem_fb_count(data);
+	count1 = intel_gem_fb_count(data);
 
 	/* Black background FB */
 	igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
@@ -676,7 +681,7 @@ cursor_leak_test_pipe(data_t *data, enum pipe pipe, igt_output_t *output)
 	cursor_leak_test_fini(data, output, &background_fb, cursor_fb);
 
 	/* We should be back to the same framebuffer count as when we started */
-	count2 = i915_gem_fb_count(data);
+	count2 = intel_gem_fb_count(data);
 
 	igt_assert_eq(count1, count2);
 }
@@ -738,7 +743,7 @@ pageflip_win_test_pipe(data_t *data, enum pipe pipe, igt_output_t *output)
 
 	int ret = 0;
 
-	igt_skip_on(is_i915_device(data->drm_fd) && data->display_ver < 9);
+	igt_skip_on(is_intel_device(data->drm_fd) && data->display_ver < 9);
 	igt_require_pipe(&data->display, pipe);
 
 	igt_info("Using (pipe %s + %s) to run the subtest.\n",
@@ -896,7 +901,7 @@ igt_main
 
 	igt_fixture {
 		data.drm_fd = drm_open_driver_master(DRIVER_ANY);
-		if (is_i915_device(data.drm_fd))
+		if (is_intel_device(data.drm_fd))
 			data.display_ver = intel_display_ver(intel_get_drm_devid(data.drm_fd));
 
 		kmstest_set_vt_graphics_mode();
-- 
2.40.0

[igt-dev] ✓ Fi.CI.BAT: success for Add IGT display support for XE (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3175 bytes --]

== Series Details ==

Series: Add IGT display support for XE (rev8)
URL   : https://patchwork.freedesktop.org/series/116658/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13071 -> IGTPW_8882
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/index.html

Participating hosts (38 -> 36)
------------------------------

  Missing    (2): bat-mtlp-8 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_8882:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@requests:
    - {bat-mtlp-6}:       [ABORT][1] ([i915#7920]) -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/bat-mtlp-6/igt@i915_selftest@live@requests.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/bat-mtlp-6/igt@i915_selftest@live@requests.html

  
Known issues
------------

  Here are the changes found in IGTPW_8882 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@mman:
    - bat-rpls-1:         [PASS][3] -> [TIMEOUT][4] ([i915#7392])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/bat-rpls-1/igt@i915_selftest@live@mman.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/bat-rpls-1/igt@i915_selftest@live@mman.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-glk-j4005:       [FAIL][5] ([i915#7916]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7916]: https://gitlab.freedesktop.org/drm/intel/issues/7916
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7273 -> IGTPW_8882

  CI-20190529: 20190529
  CI_DRM_13071: b9458e7075652669ec0e04abe039a5ed001701fe @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8882: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/index.html
  IGT_7273: f40ef4b058466219968b7792d22ff0648b82396b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@kms_plane_scaling@intel-max-src-size
-igt@kms_plane_scaling@i915-max-src-size

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/index.html

[-- Attachment #2: Type: text/html, Size: 3555 bytes --]

[igt-dev] ✗ Fi.CI.IGT: failure for Add IGT display support for XE (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 19618 bytes --]

== Series Details ==

Series: Add IGT display support for XE (rev8)
URL   : https://patchwork.freedesktop.org/series/116658/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13071_full -> IGTPW_8882_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_8882_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_8882_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/index.html

Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_8882_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_barrier_race@remote-request@rcs0:
    - shard-apl:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-apl2/igt@gem_barrier_race@remote-request@rcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-apl7/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@i915_selftest@perf@engine_cs:
    - shard-snb:          [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-snb2/igt@i915_selftest@perf@engine_cs.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-snb2/igt@i915_selftest@perf@engine_cs.html

  * {igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1} (NEW):
    - {shard-tglu}:       NOTRUN -> [FAIL][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-tglu-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html

  * {igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4} (NEW):
    - {shard-dg1}:        NOTRUN -> [FAIL][6]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-dg1-12/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - {shard-dg1}:        [SKIP][7] ([i915#3281]) -> [SKIP][8] +3 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-16/igt@api_intel_bb@blit-reloc-purge-cache.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-dg1-13/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@api_intel_bb@object-reloc-keep-cache:
    - {shard-rkl}:        [SKIP][9] ([i915#3281]) -> [SKIP][10] +6 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-rkl-7/igt@api_intel_bb@object-reloc-keep-cache.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-rkl-2/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@kms_draw_crc@draw-method-mmap-gtt:
    - {shard-dg1}:        [SKIP][11] ([i915#5431]) -> [SKIP][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-16/igt@kms_draw_crc@draw-method-mmap-gtt.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-dg1-16/igt@kms_draw_crc@draw-method-mmap-gtt.html

  * igt@kms_draw_crc@draw-method-mmap-wc:
    - {shard-dg1}:        [SKIP][13] ([i915#8155]) -> [SKIP][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-15/igt@kms_draw_crc@draw-method-mmap-wc.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-dg1-16/igt@kms_draw_crc@draw-method-mmap-wc.html

  * igt@kms_plane_lowres@tiling-4:
    - {shard-tglu}:       [SKIP][15] ([fdo#112054] / [i915#5288]) -> [SKIP][16] +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-tglu-5/igt@kms_plane_lowres@tiling-4.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-tglu-2/igt@kms_plane_lowres@tiling-4.html

  * igt@kms_plane_lowres@tiling-yf:
    - {shard-rkl}:        [SKIP][17] ([fdo#112054] / [i915#5288]) -> [SKIP][18] +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-rkl-2/igt@kms_plane_lowres@tiling-yf.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-rkl-7/igt@kms_plane_lowres@tiling-yf.html
    - {shard-dg1}:        [SKIP][19] ([fdo#112054] / [i915#5288]) -> [SKIP][20] +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-12/igt@kms_plane_lowres@tiling-yf.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-dg1-16/igt@kms_plane_lowres@tiling-yf.html

  
New tests
---------

  New tests have been introduced between CI_DRM_13071_full and IGTPW_8882_full:

### New IGT tests (5) ###

  * igt@kms_plane_scaling@intel-max-src-size:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
    - Statuses : 1 fail(s) 1 pass(s)
    - Exec time: [0.0] s

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
    - Statuses : 2 pass(s)
    - Exec time: [0.0] s

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
    - Statuses : 1 fail(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_8882_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([i915#2846])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-glk9/igt@gem_exec_fair@basic-deadline.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-glk4/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [PASS][23] -> [FAIL][24] ([i915#2842])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-glk:          [PASS][25] -> [FAIL][26] ([i915#2842])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-glk9/igt@gem_exec_fair@basic-pace@rcs0.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-glk5/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#2190])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-apl6/igt@gem_huc_copy@huc-copy.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
    - shard-snb:          [PASS][28] -> [ABORT][29] ([i915#5161])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-snb1/igt@gem_mmap_gtt@fault-concurrent-y.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-snb1/igt@gem_mmap_gtt@fault-concurrent-y.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-apl:          NOTRUN -> [SKIP][30] ([fdo#109271]) +24 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-apl6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_cdclk@mode-transition:
    - shard-glk:          NOTRUN -> [SKIP][31] ([fdo#109271]) +6 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-glk6/igt@kms_cdclk@mode-transition.html

  * igt@kms_content_protection@atomic@pipe-a-dp-1:
    - shard-apl:          NOTRUN -> [TIMEOUT][32] ([i915#7173])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-apl3/igt@kms_content_protection@atomic@pipe-a-dp-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-apl:          [PASS][33] -> [FAIL][34] ([i915#2346])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1:
    - shard-glk:          [PASS][35] -> [FAIL][36] ([i915#79])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html

  * igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][37] ([fdo#109271]) +31 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-snb2/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-glk:          NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#658])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-glk4/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  
#### Possible fixes ####

  * igt@gem_barrier_race@remote-request@rcs0:
    - {shard-dg1}:        [ABORT][39] ([i915#7461] / [i915#8234]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-16/igt@gem_barrier_race@remote-request@rcs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-dg1-16/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-tglu}:       [FAIL][41] ([i915#6268]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_eio@hibernate:
    - shard-apl:          [ABORT][43] ([i915#8213]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-apl3/igt@gem_eio@hibernate.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-apl4/igt@gem_eio@hibernate.html

  * igt@gem_eio@unwedge-stress:
    - {shard-dg1}:        [FAIL][45] ([i915#5784]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-14/igt@gem_eio@unwedge-stress.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-dg1-16/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - {shard-rkl}:        [FAIL][47] ([i915#2846]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-rkl-7/igt@gem_exec_fair@basic-deadline.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-rkl-7/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - {shard-rkl}:        [FAIL][49] ([i915#2842]) -> [PASS][50] +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-rkl-7/igt@gem_exec_fair@basic-pace@rcs0.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - {shard-dg1}:        [TIMEOUT][51] ([i915#5493]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [FAIL][53] ([i915#2346]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [FAIL][55] ([i915#2346]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_plane@pixel-format@pipe-a-planes:
    - shard-glk:          [FAIL][57] ([i915#1623]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-glk9/igt@kms_plane@pixel-format@pipe-a-planes.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-glk4/igt@kms_plane@pixel-format@pipe-a-planes.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - {shard-tglu}:       [ABORT][59] ([i915#5122]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13071/shard-tglu-5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/shard-tglu-3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1623]: https://gitlab.freedesktop.org/drm/intel/issues/1623
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5161]: https://gitlab.freedesktop.org/drm/intel/issues/5161
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5431]: https://gitlab.freedesktop.org/drm/intel/issues/5431
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
  [i915#8102]: https://gitlab.freedesktop.org/drm/intel/issues/8102
  [i915#8155]: https://gitlab.freedesktop.org/drm/intel/issues/8155
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7273 -> IGTPW_8882
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_13071: b9458e7075652669ec0e04abe039a5ed001701fe @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8882: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/index.html
  IGT_7273: f40ef4b058466219968b7792d22ff0648b82396b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8882/index.html

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