* [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg
@ 2023-04-29 6:23 Lucas De Marchi
2023-04-29 6:23 ` [Intel-xe] [PATCH 1/7] fixup! drm/xe: Drop gen afixes from registers Lucas De Marchi
` (10 more replies)
0 siblings, 11 replies; 27+ messages in thread
From: Lucas De Marchi @ 2023-04-29 6:23 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi
Now that struct xe_reg is in place, convert xe_mmio to use it so we
avoid mistakes of passing the wrong argument.
Lucas De Marchi (7):
fixup! drm/xe: Drop gen afixes from registers
drm/xe/guc: Handle RCU_MODE as masked from definition
drm/xe: Use media base for GMD_ID access
drm/xe/mmio: Use struct xe_reg
fixup! drm/xe/display: Implement display support
drm/xe: Rename reg field to addr
drm/xe: Fix indent in xe_hw_engine_print_state()
drivers/gpu/drm/xe/display/xe_de.h | 89 ++++++++------
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 6 +-
drivers/gpu/drm/xe/regs/xe_reg_defs.h | 6 +-
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 2 +-
drivers/gpu/drm/xe/xe_device.c | 2 +-
drivers/gpu/drm/xe/xe_execlist.c | 18 +--
drivers/gpu/drm/xe/xe_force_wake.c | 25 ++--
drivers/gpu/drm/xe/xe_force_wake_types.h | 6 +-
drivers/gpu/drm/xe/xe_ggtt.c | 6 +-
drivers/gpu/drm/xe/xe_gt.c | 4 +-
drivers/gpu/drm/xe/xe_gt_clock.c | 6 +-
drivers/gpu/drm/xe/xe_gt_mcr.c | 39 ++++---
drivers/gpu/drm/xe/xe_gt_topology.c | 18 +--
drivers/gpu/drm/xe/xe_guc.c | 61 +++++-----
drivers/gpu/drm/xe/xe_guc_ads.c | 34 +++---
drivers/gpu/drm/xe/xe_guc_pc.c | 32 +++---
drivers/gpu/drm/xe/xe_guc_types.h | 3 +-
drivers/gpu/drm/xe/xe_huc.c | 4 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 105 +++++++++--------
drivers/gpu/drm/xe/xe_irq.c | 140 +++++++++++------------
drivers/gpu/drm/xe/xe_mmio.c | 33 +++---
drivers/gpu/drm/xe/xe_mmio.h | 47 ++++----
drivers/gpu/drm/xe/xe_mocs.c | 11 +-
drivers/gpu/drm/xe/xe_pat.c | 14 ++-
drivers/gpu/drm/xe/xe_pci.c | 9 +-
drivers/gpu/drm/xe/xe_pcode.c | 16 +--
drivers/gpu/drm/xe/xe_reg_sr.c | 18 +--
drivers/gpu/drm/xe/xe_ring_ops.c | 11 +-
drivers/gpu/drm/xe/xe_rtp.c | 2 +-
drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 4 +-
drivers/gpu/drm/xe/xe_uc_fw.c | 16 +--
drivers/gpu/drm/xe/xe_wopcm.c | 16 +--
32 files changed, 427 insertions(+), 376 deletions(-)
--
2.40.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-xe] [PATCH 1/7] fixup! drm/xe: Drop gen afixes from registers
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
@ 2023-04-29 6:23 ` Lucas De Marchi
2023-05-05 16:55 ` Rodrigo Vivi
2023-04-29 6:23 ` [Intel-xe] [PATCH 2/7] drm/xe/guc: Handle RCU_MODE as masked from definition Lucas De Marchi
` (9 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Lucas De Marchi @ 2023-04-29 6:23 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi
Maybe an abuse of fixup, but easy enough not to deserve a separate
commit.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 566b62815dab..795302bcd3ae 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -573,7 +573,7 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
hw_engine_mmio_read32(hwe, IPEHR(0).reg));
if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
- drm_printf(p, "\tGEN12_RCU_MODE: 0x%08x\n",
+ drm_printf(p, "\tRCU_MODE: 0x%08x\n",
xe_mmio_read32(hwe->gt, RCU_MODE.reg));
}
--
2.40.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-xe] [PATCH 2/7] drm/xe/guc: Handle RCU_MODE as masked from definition
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
2023-04-29 6:23 ` [Intel-xe] [PATCH 1/7] fixup! drm/xe: Drop gen afixes from registers Lucas De Marchi
@ 2023-04-29 6:23 ` Lucas De Marchi
2023-05-05 16:55 ` Rodrigo Vivi
2023-04-29 6:23 ` [Intel-xe] [PATCH 3/7] drm/xe: Use media base for GMD_ID access Lucas De Marchi
` (8 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Lucas De Marchi @ 2023-04-29 6:23 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi
guc_mmio_regset_write() had a flags for the registers to be added to the
GuC's regset list. The only register actually using that was RCU_MODE,
but it was setting the flags to a bogus value. From
struct xe_guc_fwif.h,
#define GUC_REGSET_MASKED BIT(0)
#define GUC_REGSET_MASKED_WITH_VALUE BIT(2)
#define GUC_REGSET_RESTORE_ONLY BIT(3)
Cross checking with i915, the only flag to set in RCU_MODE is
GUC_REGSET_MASKED. That can be done automatically from the register, as
long as the definition is correct.
Add the XE_REG_OPTION_MASKED annotation to RCU_MODE and kill the "flags"
field in guc_mmio_regset_write(): guc_mmio_regset_write_one() can decide
that based on the register being passed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 31 +++++++++++-----------------
2 files changed, 13 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 68e89d71cd1c..4d87f1fe010d 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -325,7 +325,7 @@
#define SARB_CHICKEN1 XE_REG_MCR(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
-#define RCU_MODE XE_REG(0x14800)
+#define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED)
#define RCU_MODE_CCS_ENABLE REG_BIT(0)
#define FORCEWAKE_ACK_GT XE_REG(0x130044)
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 676137dcb510..84c2d7c624c6 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -422,12 +422,12 @@ static void guc_capture_list_init(struct xe_guc_ads *ads)
static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,
struct iosys_map *regset_map,
- u32 reg, u32 flags,
+ struct xe_reg reg,
unsigned int n_entry)
{
struct guc_mmio_reg entry = {
- .offset = reg,
- .flags = flags,
+ .offset = reg.reg,
+ .flags = reg.masked ? GUC_REGSET_MASKED : 0,
/* TODO: steering */
};
@@ -446,40 +446,33 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
unsigned long idx;
unsigned count = 0;
const struct {
- u32 reg;
- u32 flags;
+ struct xe_reg reg;
bool skip;
} *e, extra_regs[] = {
- { .reg = RING_MODE(hwe->mmio_base).reg, },
- { .reg = RING_HWS_PGA(hwe->mmio_base).reg, },
- { .reg = RING_IMR(hwe->mmio_base).reg, },
- { .reg = RCU_MODE.reg, .flags = 0x3,
- .skip = hwe != hwe_rcs_reset_domain },
+ { .reg = RING_MODE(hwe->mmio_base), },
+ { .reg = RING_HWS_PGA(hwe->mmio_base), },
+ { .reg = RING_IMR(hwe->mmio_base), },
+ { .reg = RCU_MODE, .skip = hwe != hwe_rcs_reset_domain },
};
u32 i;
BUILD_BUG_ON(ARRAY_SIZE(extra_regs) > ADS_REGSET_EXTRA_MAX);
- xa_for_each(&hwe->reg_sr.xa, idx, entry) {
- u32 flags = entry->reg.masked ? GUC_REGSET_MASKED : 0;
-
- guc_mmio_regset_write_one(ads, regset_map, idx, flags, count++);
- }
+ xa_for_each(&hwe->reg_sr.xa, idx, entry)
+ guc_mmio_regset_write_one(ads, regset_map, entry->reg, count++);
for (e = extra_regs; e < extra_regs + ARRAY_SIZE(extra_regs); e++) {
if (e->skip)
continue;
- guc_mmio_regset_write_one(ads, regset_map,
- e->reg, e->flags, count++);
+ guc_mmio_regset_write_one(ads, regset_map, e->reg, count++);
}
/* Wa_1607983814 */
if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) {
for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) {
guc_mmio_regset_write_one(ads, regset_map,
- LNCFCMOCS(i).reg, 0,
- count++);
+ LNCFCMOCS(i), count++);
}
}
--
2.40.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-xe] [PATCH 3/7] drm/xe: Use media base for GMD_ID access
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
2023-04-29 6:23 ` [Intel-xe] [PATCH 1/7] fixup! drm/xe: Drop gen afixes from registers Lucas De Marchi
2023-04-29 6:23 ` [Intel-xe] [PATCH 2/7] drm/xe/guc: Handle RCU_MODE as masked from definition Lucas De Marchi
@ 2023-04-29 6:23 ` Lucas De Marchi
2023-04-30 17:47 ` Michal Wajdeczko
2023-04-29 6:23 ` [Intel-xe] [PATCH 4/7] drm/xe/mmio: Use struct xe_reg Lucas De Marchi
` (7 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Lucas De Marchi @ 2023-04-29 6:23 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi
Instead of adding a hardcoded base, define GMD_ID() with a base
argument and use it in all places.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +++-
drivers/gpu/drm/xe/xe_pci.c | 9 +++++----
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 4d87f1fe010d..da7b6d2c7e01 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -8,6 +8,8 @@
#include "regs/xe_reg_defs.h"
+#define MTL_MEDIA_GT_BASE 0x380000
+
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 XE_REG(0xd00)
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
@@ -21,7 +23,7 @@
#define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4)
#define FORCEWAKE_ACK_RENDER XE_REG(0xd84)
-#define GMD_ID XE_REG(0xd8c)
+#define GMD_ID(base) XE_REG((base) + 0xd8c)
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
#define GMD_ID_STEP REG_GENMASK(5, 0)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 35dcb8781f2a..8687e51cb0a4 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -276,7 +276,7 @@ static const struct xe_gt_desc xelpmp_gts[] = {
.type = XE_GT_TYPE_MEDIA,
.vram_id = 0,
.mmio_adj_limit = 0x40000,
- .mmio_adj_offset = 0x380000,
+ .mmio_adj_offset = MTL_MEDIA_GT_BASE,
},
};
@@ -391,8 +391,9 @@ find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
return NULL;
}
-static u32 peek_gmdid(struct xe_device *xe, u32 gmdid_offset)
+static u32 peek_gmdid(struct xe_device *xe, struct xe_reg gmdid_reg)
{
+ u32 gmdid_offset = gmdid_reg.reg;
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
void __iomem *map = pci_iomap_range(pdev, 0, gmdid_offset, sizeof(u32));
u32 ver;
@@ -441,7 +442,7 @@ static void handle_gmdid(struct xe_device *xe,
{
u32 ver;
- ver = peek_gmdid(xe, GMD_ID.reg);
+ ver = peek_gmdid(xe, GMD_ID(0));
for (int i = 0; i < ARRAY_SIZE(graphics_ip_map); i++) {
if (ver == graphics_ip_map[i].ver) {
xe->info.graphics_verx100 = ver;
@@ -456,7 +457,7 @@ static void handle_gmdid(struct xe_device *xe,
ver / 100, ver % 100);
}
- ver = peek_gmdid(xe, GMD_ID.reg + 0x380000);
+ ver = peek_gmdid(xe, GMD_ID(MTL_MEDIA_GT_BASE));
for (int i = 0; i < ARRAY_SIZE(media_ip_map); i++) {
if (ver == media_ip_map[i].ver) {
xe->info.media_verx100 = ver;
--
2.40.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-xe] [PATCH 4/7] drm/xe/mmio: Use struct xe_reg
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
` (2 preceding siblings ...)
2023-04-29 6:23 ` [Intel-xe] [PATCH 3/7] drm/xe: Use media base for GMD_ID access Lucas De Marchi
@ 2023-04-29 6:23 ` Lucas De Marchi
2023-05-05 16:57 ` Rodrigo Vivi
2023-04-29 6:23 ` [Intel-xe] [PATCH 5/7] fixup! drm/xe/display: Implement display support Lucas De Marchi
` (6 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Lucas De Marchi @ 2023-04-29 6:23 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi
Convert all the callers to deal with xe_mmio_*() using struct xe_reg
instead of plain u32. In a few places there was also a rename
s/reg/reg_val/ when dealing with the value returned so it doesn't get
mixed up with the register address.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_device.c | 2 +-
drivers/gpu/drm/xe/xe_execlist.c | 18 +--
drivers/gpu/drm/xe/xe_force_wake.c | 25 ++--
drivers/gpu/drm/xe/xe_force_wake_types.h | 6 +-
drivers/gpu/drm/xe/xe_ggtt.c | 6 +-
drivers/gpu/drm/xe/xe_gt.c | 4 +-
drivers/gpu/drm/xe/xe_gt_clock.c | 6 +-
drivers/gpu/drm/xe/xe_gt_mcr.c | 37 +++---
drivers/gpu/drm/xe/xe_gt_topology.c | 18 +--
drivers/gpu/drm/xe/xe_guc.c | 61 +++++-----
drivers/gpu/drm/xe/xe_guc_ads.c | 3 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 32 +++---
drivers/gpu/drm/xe/xe_guc_types.h | 3 +-
drivers/gpu/drm/xe/xe_huc.c | 4 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 85 +++++++-------
drivers/gpu/drm/xe/xe_irq.c | 138 +++++++++++------------
drivers/gpu/drm/xe/xe_mmio.c | 31 +++--
drivers/gpu/drm/xe/xe_mmio.h | 47 ++++----
drivers/gpu/drm/xe/xe_mocs.c | 7 +-
drivers/gpu/drm/xe/xe_pat.c | 14 ++-
drivers/gpu/drm/xe/xe_pcode.c | 16 +--
drivers/gpu/drm/xe/xe_reg_sr.c | 14 ++-
drivers/gpu/drm/xe/xe_ring_ops.c | 11 +-
drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 4 +-
drivers/gpu/drm/xe/xe_uc_fw.c | 16 +--
drivers/gpu/drm/xe/xe_wopcm.c | 12 +-
26 files changed, 325 insertions(+), 295 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 45d6e5ff47fd..f7f4837ded37 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -393,7 +393,7 @@ void xe_device_wmb(struct xe_device *xe)
wmb();
if (IS_DGFX(xe))
- xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33.reg, 0);
+ xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);
}
u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index de4f0044b211..5d2d26e361b9 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -60,7 +60,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
}
if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
- xe_mmio_write32(hwe->gt, RCU_MODE.reg,
+ xe_mmio_write32(hwe->gt, RCU_MODE,
_MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
@@ -78,17 +78,17 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
*/
wmb();
- xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base).reg,
+ xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base),
xe_bo_ggtt_addr(hwe->hwsp));
- xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base).reg);
- xe_mmio_write32(gt, RING_MODE(hwe->mmio_base).reg,
+ xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base));
+ xe_mmio_write32(gt, RING_MODE(hwe->mmio_base),
_MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
- xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base).reg,
+ xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
lower_32_bits(lrc_desc));
- xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base).reg,
+ xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),
upper_32_bits(lrc_desc));
- xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base).reg,
+ xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base),
EL_CTRL_LOAD);
}
@@ -173,8 +173,8 @@ static u64 read_execlist_status(struct xe_hw_engine *hwe)
struct xe_gt *gt = hwe->gt;
u32 hi, lo;
- lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base).reg);
- hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base).reg);
+ lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base));
+ hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base));
printk(KERN_INFO "EXECLIST_STATUS %d:%d = 0x%08x %08x\n", hwe->class,
hwe->instance, hi, lo);
diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index 53d73f36a121..363b81c3d746 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -8,6 +8,7 @@
#include <drm/drm_util.h>
#include "regs/xe_gt_regs.h"
+#include "regs/xe_reg_defs.h"
#include "xe_gt.h"
#include "xe_mmio.h"
@@ -27,7 +28,7 @@ fw_to_xe(struct xe_force_wake *fw)
static void domain_init(struct xe_force_wake_domain *domain,
enum xe_force_wake_domain_id id,
- u32 reg, u32 ack, u32 val, u32 mask)
+ struct xe_reg reg, struct xe_reg ack, u32 val, u32 mask)
{
domain->id = id;
domain->reg_ctl = reg;
@@ -49,14 +50,14 @@ void xe_force_wake_init_gt(struct xe_gt *gt, struct xe_force_wake *fw)
if (xe->info.graphics_verx100 >= 1270) {
domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],
XE_FW_DOMAIN_ID_GT,
- FORCEWAKE_GT.reg,
- FORCEWAKE_ACK_GT_MTL.reg,
+ FORCEWAKE_GT,
+ FORCEWAKE_ACK_GT_MTL,
BIT(0), BIT(16));
} else {
domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],
XE_FW_DOMAIN_ID_GT,
- FORCEWAKE_GT.reg,
- FORCEWAKE_ACK_GT.reg,
+ FORCEWAKE_GT,
+ FORCEWAKE_ACK_GT,
BIT(0), BIT(16));
}
}
@@ -71,8 +72,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
if (!xe_gt_is_media_type(gt))
domain_init(&fw->domains[XE_FW_DOMAIN_ID_RENDER],
XE_FW_DOMAIN_ID_RENDER,
- FORCEWAKE_RENDER.reg,
- FORCEWAKE_ACK_RENDER.reg,
+ FORCEWAKE_RENDER,
+ FORCEWAKE_ACK_RENDER,
BIT(0), BIT(16));
for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
@@ -81,8 +82,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j],
XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j,
- FORCEWAKE_MEDIA_VDBOX(j).reg,
- FORCEWAKE_ACK_MEDIA_VDBOX(j).reg,
+ FORCEWAKE_MEDIA_VDBOX(j),
+ FORCEWAKE_ACK_MEDIA_VDBOX(j),
BIT(0), BIT(16));
}
@@ -92,8 +93,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j],
XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j,
- FORCEWAKE_MEDIA_VEBOX(j).reg,
- FORCEWAKE_ACK_MEDIA_VEBOX(j).reg,
+ FORCEWAKE_MEDIA_VEBOX(j),
+ FORCEWAKE_ACK_MEDIA_VEBOX(j),
BIT(0), BIT(16));
}
}
@@ -128,7 +129,7 @@ static int domain_sleep_wait(struct xe_gt *gt,
for (tmp__ = (mask__); tmp__; tmp__ &= ~BIT(ffs(tmp__) - 1)) \
for_each_if((domain__ = ((fw__)->domains + \
(ffs(tmp__) - 1))) && \
- domain__->reg_ctl)
+ domain__->reg_ctl.reg)
int xe_force_wake_get(struct xe_force_wake *fw,
enum xe_force_wake_domains domains)
diff --git a/drivers/gpu/drm/xe/xe_force_wake_types.h b/drivers/gpu/drm/xe/xe_force_wake_types.h
index 208dd629d7b1..cb782696855b 100644
--- a/drivers/gpu/drm/xe/xe_force_wake_types.h
+++ b/drivers/gpu/drm/xe/xe_force_wake_types.h
@@ -9,6 +9,8 @@
#include <linux/mutex.h>
#include <linux/types.h>
+#include "regs/xe_reg_defs.h"
+
enum xe_force_wake_domain_id {
XE_FW_DOMAIN_ID_GT = 0,
XE_FW_DOMAIN_ID_RENDER,
@@ -56,9 +58,9 @@ struct xe_force_wake_domain {
/** @id: domain force wake id */
enum xe_force_wake_domain_id id;
/** @reg_ctl: domain wake control register address */
- u32 reg_ctl;
+ struct xe_reg reg_ctl;
/** @reg_ack: domain ack register address */
- u32 reg_ack;
+ struct xe_reg reg_ack;
/** @val: domain wake write value */
u32 val;
/** @mask: domain mask */
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 9c08031c9350..546240261e0a 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -207,12 +207,12 @@ void xe_ggtt_invalidate(struct xe_gt *gt)
struct xe_device *xe = gt_to_xe(gt);
if (xe->info.platform == XE_PVC) {
- xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1.reg,
+ xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1,
PVC_GUC_TLB_INV_DESC1_INVALIDATE);
- xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0.reg,
+ xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0,
PVC_GUC_TLB_INV_DESC0_VALID);
} else
- xe_mmio_write32(gt, GUC_TLB_INV_CR.reg,
+ xe_mmio_write32(gt, GUC_TLB_INV_CR,
GUC_TLB_INV_CR_INVALIDATE);
}
}
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 0d4664e344da..1cc9314e0d43 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -541,8 +541,8 @@ static int do_gt_reset(struct xe_gt *gt)
struct xe_device *xe = gt_to_xe(gt);
int err;
- xe_mmio_write32(gt, GDRST.reg, GRDOM_FULL);
- err = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_FULL, 5000,
+ xe_mmio_write32(gt, GDRST, GRDOM_FULL);
+ err = xe_mmio_wait32(gt, GDRST, 0, GRDOM_FULL, 5000,
NULL, false);
if (err)
drm_err(&xe->drm,
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index 49625d49bdcc..7cf11078ff57 100644
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -14,7 +14,7 @@
static u32 read_reference_ts_freq(struct xe_gt *gt)
{
- u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE.reg);
+ u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE);
u32 base_freq, frac_freq;
base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK,
@@ -54,7 +54,7 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg)
int xe_gt_clock_init(struct xe_gt *gt)
{
- u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE.reg);
+ u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE);
u32 freq = 0;
/* Assuming gen11+ so assert this assumption is correct */
@@ -63,7 +63,7 @@ int xe_gt_clock_init(struct xe_gt *gt)
if (ctc_reg & CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(gt);
} else {
- u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0.reg);
+ u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0);
freq = get_crystal_clock_freq(c0);
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 55b240a5eaa7..2461e51c0abf 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -40,6 +40,8 @@
* non-terminated instance.
*/
+#define STEER_SEMAPHORE XE_REG(0xFD0)
+
static inline struct xe_reg to_xe_reg(struct xe_reg_mcr reg_mcr)
{
return reg_mcr.__reg;
@@ -183,9 +185,9 @@ static void init_steering_l3bank(struct xe_gt *gt)
{
if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
- xe_mmio_read32(gt, MIRROR_FUSE3.reg));
+ xe_mmio_read32(gt, MIRROR_FUSE3));
u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK,
- xe_mmio_read32(gt, XEHP_FUSE4.reg));
+ xe_mmio_read32(gt, XEHP_FUSE4));
/*
* Group selects mslice, instance selects bank within mslice.
@@ -196,7 +198,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
bank_mask & BIT(0) ? 0 : 2;
} else if (gt_to_xe(gt)->info.platform == XE_DG2) {
u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
- xe_mmio_read32(gt, MIRROR_FUSE3.reg));
+ xe_mmio_read32(gt, MIRROR_FUSE3));
u32 bank = __ffs(mslice_mask) * 8;
/*
@@ -208,7 +210,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
gt->steering[L3BANK].instance_target = bank & 0x3;
} else {
u32 fuse = REG_FIELD_GET(L3BANK_MASK,
- ~xe_mmio_read32(gt, MIRROR_FUSE3.reg));
+ ~xe_mmio_read32(gt, MIRROR_FUSE3));
gt->steering[L3BANK].group_target = 0; /* unused */
gt->steering[L3BANK].instance_target = __ffs(fuse);
@@ -218,7 +220,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
static void init_steering_mslice(struct xe_gt *gt)
{
u32 mask = REG_FIELD_GET(MEML3_EN_MASK,
- xe_mmio_read32(gt, MIRROR_FUSE3.reg));
+ xe_mmio_read32(gt, MIRROR_FUSE3));
/*
* mslice registers are valid (not terminated) if either the meml3
@@ -337,8 +339,8 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |
REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);
- xe_mmio_write32(gt, MCFG_MCR_SELECTOR.reg, steer_val);
- xe_mmio_write32(gt, SF_MCR_SELECTOR.reg, steer_val);
+ xe_mmio_write32(gt, MCFG_MCR_SELECTOR, steer_val);
+ xe_mmio_write32(gt, SF_MCR_SELECTOR, steer_val);
/*
* For GAM registers, all reads should be directed to instance 1
* (unicast reads against other instances are not allowed),
@@ -376,7 +378,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
continue;
for (int i = 0; gt->steering[type].ranges[i].end > 0; i++) {
- if (xe_mmio_in_range(>->steering[type].ranges[i], reg.reg)) {
+ if (xe_mmio_in_range(>->steering[type].ranges[i], reg)) {
*group = gt->steering[type].group_target;
*instance = gt->steering[type].instance_target;
return true;
@@ -387,7 +389,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
implicit_ranges = gt->steering[IMPLICIT_STEERING].ranges;
if (implicit_ranges)
for (int i = 0; implicit_ranges[i].end > 0; i++)
- if (xe_mmio_in_range(&implicit_ranges[i], reg.reg))
+ if (xe_mmio_in_range(&implicit_ranges[i], reg))
return false;
/*
@@ -403,8 +405,6 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
return true;
}
-#define STEER_SEMAPHORE 0xFD0
-
/*
* Obtain exclusive access to MCR steering. On MTL and beyond we also need
* to synchronize with external clients (e.g., firmware), so a semaphore
@@ -446,16 +446,17 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
u8 rw_flag, int group, int instance, u32 value)
{
const struct xe_reg reg = to_xe_reg(reg_mcr);
- u32 steer_reg, steer_val, val = 0;
+ struct xe_reg steer_reg;
+ u32 steer_val, val = 0;
lockdep_assert_held(>->mcr_lock);
if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
- steer_reg = MTL_MCR_SELECTOR.reg;
+ steer_reg = MTL_MCR_SELECTOR;
steer_val = REG_FIELD_PREP(MTL_MCR_GROUPID, group) |
REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance);
} else {
- steer_reg = MCR_SELECTOR.reg;
+ steer_reg = MCR_SELECTOR;
steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, group) |
REG_FIELD_PREP(MCR_SUBSLICE_MASK, instance);
}
@@ -473,9 +474,9 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
xe_mmio_write32(gt, steer_reg, steer_val);
if (rw_flag == MCR_OP_READ)
- val = xe_mmio_read32(gt, reg.reg);
+ val = xe_mmio_read32(gt, reg);
else
- xe_mmio_write32(gt, reg.reg, value);
+ xe_mmio_write32(gt, reg, value);
/*
* If we turned off the multicast bit (during a write) we're required
@@ -517,7 +518,7 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr reg_mcr)
group, instance, 0);
mcr_unlock(gt);
} else {
- val = xe_mmio_read32(gt, reg.reg);
+ val = xe_mmio_read32(gt, reg);
}
return val;
@@ -584,7 +585,7 @@ void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
* to touch the steering register.
*/
mcr_lock(gt);
- xe_mmio_write32(gt, reg.reg, value);
+ xe_mmio_write32(gt, reg, value);
mcr_unlock(gt);
}
diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
index 14cf135fd648..7c3e347e4d74 100644
--- a/drivers/gpu/drm/xe/xe_gt_topology.c
+++ b/drivers/gpu/drm/xe/xe_gt_topology.c
@@ -26,7 +26,7 @@ load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)
va_start(argp, numregs);
for (i = 0; i < numregs; i++)
- fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, u32));
+ fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, struct xe_reg));
va_end(argp);
bitmap_from_arr32(mask, fuse_val, numregs * 32);
@@ -36,7 +36,7 @@ static void
load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
{
struct xe_device *xe = gt_to_xe(gt);
- u32 reg = xe_mmio_read32(gt, XELP_EU_ENABLE.reg);
+ u32 reg_val = xe_mmio_read32(gt, XELP_EU_ENABLE);
u32 val = 0;
int i;
@@ -47,15 +47,15 @@ load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
* of enable).
*/
if (GRAPHICS_VERx100(xe) < 1250)
- reg = ~reg & XELP_EU_MASK;
+ reg_val = ~reg_val & XELP_EU_MASK;
/* On PVC, one bit = one EU */
if (GRAPHICS_VERx100(xe) == 1260) {
- val = reg;
+ val = reg_val;
} else {
/* All other platforms, one bit = 2 EU */
- for (i = 0; i < fls(reg); i++)
- if (reg & BIT(i))
+ for (i = 0; i < fls(reg_val); i++)
+ if (reg_val & BIT(i))
val |= 0x3 << 2 * i;
}
@@ -95,10 +95,10 @@ xe_gt_topology_init(struct xe_gt *gt)
load_dss_mask(gt, gt->fuse_topo.g_dss_mask,
num_geometry_regs,
- XELP_GT_GEOMETRY_DSS_ENABLE.reg);
+ XELP_GT_GEOMETRY_DSS_ENABLE);
load_dss_mask(gt, gt->fuse_topo.c_dss_mask, num_compute_regs,
- XEHP_GT_COMPUTE_DSS_ENABLE.reg,
- XEHPC_GT_COMPUTE_DSS_ENABLE_EXT.reg);
+ XEHP_GT_COMPUTE_DSS_ENABLE,
+ XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
load_eu_mask(gt, gt->fuse_topo.eu_mask_per_dss);
xe_gt_topology_dump(gt, &p);
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 89d20faced19..12b636910460 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -240,10 +240,10 @@ static void guc_write_params(struct xe_guc *guc)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- xe_mmio_write32(gt, SOFT_SCRATCH(0).reg, 0);
+ xe_mmio_write32(gt, SOFT_SCRATCH(0), 0);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- xe_mmio_write32(gt, SOFT_SCRATCH(1 + i).reg, guc->params[i]);
+ xe_mmio_write32(gt, SOFT_SCRATCH(1 + i), guc->params[i]);
}
int xe_guc_init(struct xe_guc *guc)
@@ -276,9 +276,9 @@ int xe_guc_init(struct xe_guc *guc)
guc_init_params(guc);
if (xe_gt_is_media_type(gt))
- guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT.reg;
+ guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT;
else
- guc->notify_reg = GUC_HOST_INTERRUPT.reg;
+ guc->notify_reg = GUC_HOST_INTERRUPT;
xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE);
@@ -317,9 +317,9 @@ int xe_guc_reset(struct xe_guc *guc)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- xe_mmio_write32(gt, GDRST.reg, GRDOM_GUC);
+ xe_mmio_write32(gt, GDRST, GRDOM_GUC);
- ret = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_GUC, 5000,
+ ret = xe_mmio_wait32(gt, GDRST, 0, GRDOM_GUC, 5000,
&gdrst, false);
if (ret) {
drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",
@@ -327,7 +327,7 @@ int xe_guc_reset(struct xe_guc *guc)
goto err_out;
}
- guc_status = xe_mmio_read32(gt, GUC_STATUS.reg);
+ guc_status = xe_mmio_read32(gt, GUC_STATUS);
if (!(guc_status & GS_MIA_IN_RESET)) {
drm_err(&xe->drm,
"GuC status: 0x%x, MIA core expected to be in reset\n",
@@ -360,9 +360,9 @@ static void guc_prepare_xfer(struct xe_guc *guc)
shim_flags |= PVC_GUC_MOCS_INDEX(PVC_GUC_MOCS_UC_INDEX);
/* Must program this register before loading the ucode with DMA */
- xe_mmio_write32(gt, GUC_SHIM_CONTROL.reg, shim_flags);
+ xe_mmio_write32(gt, GUC_SHIM_CONTROL, shim_flags);
- xe_mmio_write32(gt, GT_PM_CONFIG.reg, GT_DOORBELL_ENABLE);
+ xe_mmio_write32(gt, GT_PM_CONFIG, GT_DOORBELL_ENABLE);
}
/*
@@ -378,7 +378,7 @@ static int guc_xfer_rsa(struct xe_guc *guc)
if (guc->fw.rsa_size > 256) {
u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) +
xe_uc_fw_rsa_offset(&guc->fw);
- xe_mmio_write32(gt, UOS_RSA_SCRATCH(0).reg, rsa_ggtt_addr);
+ xe_mmio_write32(gt, UOS_RSA_SCRATCH(0), rsa_ggtt_addr);
return 0;
}
@@ -387,7 +387,7 @@ static int guc_xfer_rsa(struct xe_guc *guc)
return -ENOMEM;
for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
- xe_mmio_write32(gt, UOS_RSA_SCRATCH(i).reg, rsa[i]);
+ xe_mmio_write32(gt, UOS_RSA_SCRATCH(i), rsa[i]);
return 0;
}
@@ -415,7 +415,7 @@ static int guc_wait_ucode(struct xe_guc *guc)
* 200ms. Even at slowest clock, this should be sufficient. And
* in the working case, a larger timeout makes no difference.
*/
- ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS.reg,
+ ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS,
FIELD_PREP(GS_UKERNEL_MASK,
XE_GUC_LOAD_STATUS_READY),
GS_UKERNEL_MASK, 200000, &status, false);
@@ -443,7 +443,7 @@ static int guc_wait_ucode(struct xe_guc *guc)
XE_GUC_LOAD_STATUS_EXCEPTION) {
drm_info(drm, "GuC firmware exception. EIP: %#x\n",
xe_mmio_read32(guc_to_gt(guc),
- SOFT_SCRATCH(13).reg));
+ SOFT_SCRATCH(13)));
ret = -ENXIO;
}
@@ -540,10 +540,10 @@ static void guc_handle_mmio_msg(struct xe_guc *guc)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- msg = xe_mmio_read32(gt, SOFT_SCRATCH(15).reg);
+ msg = xe_mmio_read32(gt, SOFT_SCRATCH(15));
msg &= XE_GUC_RECV_MSG_EXCEPTION |
XE_GUC_RECV_MSG_CRASH_DUMP_POSTED;
- xe_mmio_write32(gt, SOFT_SCRATCH(15).reg, 0);
+ xe_mmio_write32(gt, SOFT_SCRATCH(15), 0);
if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED)
drm_err(&guc_to_xe(guc)->drm,
@@ -561,12 +561,12 @@ static void guc_enable_irq(struct xe_guc *guc)
REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) :
REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
- xe_mmio_write32(gt, GUC_SG_INTR_ENABLE.reg,
+ xe_mmio_write32(gt, GUC_SG_INTR_ENABLE,
REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST));
if (xe_gt_is_media_type(gt))
- xe_mmio_rmw32(gt, GUC_SG_INTR_MASK.reg, events, 0);
+ xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0);
else
- xe_mmio_write32(gt, GUC_SG_INTR_MASK.reg, ~events);
+ xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~events);
}
int xe_guc_enable_communication(struct xe_guc *guc)
@@ -575,7 +575,7 @@ int xe_guc_enable_communication(struct xe_guc *guc)
guc_enable_irq(guc);
- xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK.reg,
+ xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK,
ARAT_EXPIRED_INTRMSK, 0);
err = xe_guc_ct_enable(&guc->ct);
@@ -628,8 +628,8 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
struct xe_device *xe = guc_to_xe(guc);
struct xe_gt *gt = guc_to_gt(guc);
u32 header, reply;
- u32 reply_reg = xe_gt_is_media_type(gt) ?
- MED_VF_SW_FLAG(0).reg : VF_SW_FLAG(0).reg;
+ struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?
+ MED_VF_SW_FLAG(0) : VF_SW_FLAG(0);
const u32 LAST_INDEX = VF_SW_FLAG_COUNT;
int ret;
int i;
@@ -649,14 +649,14 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
/* Not in critical data-path, just do if else for GT type */
if (xe_gt_is_media_type(gt)) {
for (i = 0; i < len; ++i)
- xe_mmio_write32(gt, MED_VF_SW_FLAG(i).reg,
+ xe_mmio_write32(gt, MED_VF_SW_FLAG(i),
request[i]);
- xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX).reg);
+ xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX));
} else {
for (i = 0; i < len; ++i)
- xe_mmio_write32(gt, VF_SW_FLAG(i).reg,
+ xe_mmio_write32(gt, VF_SW_FLAG(i),
request[i]);
- xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX).reg);
+ xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX));
}
xe_guc_notify(guc);
@@ -720,9 +720,10 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
if (response_buf) {
response_buf[0] = header;
- for (i = 1; i < VF_SW_FLAG_COUNT; i++)
- response_buf[i] =
- xe_mmio_read32(gt, reply_reg + i * sizeof(u32));
+ for (i = 1; i < VF_SW_FLAG_COUNT; i++) {
+ reply_reg.reg += i * sizeof(u32);
+ response_buf[i] = xe_mmio_read32(gt, reply_reg);
+ }
}
/* Use data from the GuC response as our return value */
@@ -844,7 +845,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
if (err)
return;
- status = xe_mmio_read32(gt, GUC_STATUS.reg);
+ status = xe_mmio_read32(gt, GUC_STATUS);
drm_printf(p, "\nGuC status 0x%08x:\n", status);
drm_printf(p, "\tBootrom status = 0x%x\n",
@@ -859,7 +860,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
drm_puts(p, "\nScratch registers:\n");
for (i = 0; i < SOFT_SCRATCH_COUNT; i++) {
drm_printf(p, "\t%2d: \t0x%x\n",
- i, xe_mmio_read32(gt, SOFT_SCRATCH(i).reg));
+ i, xe_mmio_read32(gt, SOFT_SCRATCH(i)));
}
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 84c2d7c624c6..683f2df09c49 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -428,7 +428,6 @@ static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,
struct guc_mmio_reg entry = {
.offset = reg.reg,
.flags = reg.masked ? GUC_REGSET_MASKED : 0,
- /* TODO: steering */
};
xe_map_memcpy_to(ads_to_xe(ads), regset_map, n_entry * sizeof(entry),
@@ -551,7 +550,7 @@ static void guc_doorbell_init(struct xe_guc_ads *ads)
if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) {
u32 distdbreg =
- xe_mmio_read32(gt, DIST_DBS_POPULATED.reg);
+ xe_mmio_read32(gt, DIST_DBS_POPULATED);
ads_blob_write(ads,
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 72d460d5323b..e799faa1c6b8 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -317,9 +317,9 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
u32 reg;
if (xe_gt_is_media_type(gt))
- reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY.reg);
+ reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY);
else
- reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY.reg);
+ reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY);
pc->rpe_freq = REG_FIELD_GET(MTL_RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
}
@@ -336,9 +336,9 @@ static void tgl_update_rpe_value(struct xe_guc_pc *pc)
* PCODE at a different register
*/
if (xe->info.platform == XE_PVC)
- reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP.reg);
+ reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);
else
- reg = xe_mmio_read32(gt, GEN10_FREQ_INFO_REC.reg);
+ reg = xe_mmio_read32(gt, GEN10_FREQ_INFO_REC);
pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
}
@@ -380,10 +380,10 @@ static ssize_t freq_act_show(struct device *dev,
goto out;
if (xe->info.platform == XE_METEORLAKE) {
- freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1.reg);
+ freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);
freq = REG_FIELD_GET(MTL_CAGF_MASK, freq);
} else {
- freq = xe_mmio_read32(gt, GEN12_RPSTAT1.reg);
+ freq = xe_mmio_read32(gt, GEN12_RPSTAT1);
freq = REG_FIELD_GET(GEN12_CAGF_MASK, freq);
}
@@ -413,7 +413,7 @@ static ssize_t freq_cur_show(struct device *dev,
if (ret)
goto out;
- freq = xe_mmio_read32(gt, RPNSWREQ.reg);
+ freq = xe_mmio_read32(gt, RPNSWREQ);
freq = REG_FIELD_GET(REQ_RATIO_MASK, freq);
ret = sysfs_emit(buf, "%d\n", decode_freq(freq));
@@ -588,7 +588,7 @@ static ssize_t rc_status_show(struct device *dev,
u32 reg;
xe_device_mem_access_get(gt_to_xe(gt));
- reg = xe_mmio_read32(gt, GT_CORE_STATUS.reg);
+ reg = xe_mmio_read32(gt, GT_CORE_STATUS);
xe_device_mem_access_put(gt_to_xe(gt));
switch (REG_FIELD_GET(RCN_MASK, reg)) {
@@ -615,7 +615,7 @@ static ssize_t rc6_residency_show(struct device *dev,
if (ret)
goto out;
- reg = xe_mmio_read32(gt, GT_GFX_RC6.reg);
+ reg = xe_mmio_read32(gt, GT_GFX_RC6);
ret = sysfs_emit(buff, "%u\n", reg);
XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
@@ -646,9 +646,9 @@ static void mtl_init_fused_rp_values(struct xe_guc_pc *pc)
xe_device_assert_mem_access(pc_to_xe(pc));
if (xe_gt_is_media_type(gt))
- reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP.reg);
+ reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP);
else
- reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP.reg);
+ reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP);
pc->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, reg) *
GT_FREQUENCY_MULTIPLIER;
pc->rpn_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, reg) *
@@ -664,9 +664,9 @@ static void tgl_init_fused_rp_values(struct xe_guc_pc *pc)
xe_device_assert_mem_access(pc_to_xe(pc));
if (xe->info.platform == XE_PVC)
- reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP.reg);
+ reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);
else
- reg = xe_mmio_read32(gt, GEN6_RP_STATE_CAP.reg);
+ reg = xe_mmio_read32(gt, GEN6_RP_STATE_CAP);
pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
}
@@ -745,9 +745,9 @@ static int pc_gucrc_disable(struct xe_guc_pc *pc)
if (ret)
return ret;
- xe_mmio_write32(gt, PG_ENABLE.reg, 0);
- xe_mmio_write32(gt, RC_CONTROL.reg, 0);
- xe_mmio_write32(gt, RC_STATE.reg, 0);
+ xe_mmio_write32(gt, PG_ENABLE, 0);
+ xe_mmio_write32(gt, RC_CONTROL, 0);
+ xe_mmio_write32(gt, RC_STATE, 0);
XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
return 0;
diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
index ac7eec28934d..a304dce4e9f4 100644
--- a/drivers/gpu/drm/xe/xe_guc_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_types.h
@@ -9,6 +9,7 @@
#include <linux/idr.h>
#include <linux/xarray.h>
+#include "regs/xe_reg_defs.h"
#include "xe_guc_ads_types.h"
#include "xe_guc_ct_types.h"
#include "xe_guc_fwif.h"
@@ -74,7 +75,7 @@ struct xe_guc {
/**
* @notify_reg: Register which is written to notify GuC of H2G messages
*/
- u32 notify_reg;
+ struct xe_reg notify_reg;
/** @params: Control params for fw initialization */
u32 params[GUC_CTL_MAX_DWORDS];
};
diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
index 55dcaab34ea4..e0377083d1f2 100644
--- a/drivers/gpu/drm/xe/xe_huc.c
+++ b/drivers/gpu/drm/xe/xe_huc.c
@@ -84,7 +84,7 @@ int xe_huc_auth(struct xe_huc *huc)
goto fail;
}
- ret = xe_mmio_wait32(gt, HUC_KERNEL_LOAD_INFO.reg,
+ ret = xe_mmio_wait32(gt, HUC_KERNEL_LOAD_INFO,
HUC_LOAD_SUCCESSFUL,
HUC_LOAD_SUCCESSFUL, 100000, NULL, false);
if (ret) {
@@ -126,7 +126,7 @@ void xe_huc_print_info(struct xe_huc *huc, struct drm_printer *p)
return;
drm_printf(p, "\nHuC status: 0x%08x\n",
- xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO.reg));
+ xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO));
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
}
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 795302bcd3ae..d1b7ac35c4a0 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -232,20 +232,25 @@ static void hw_engine_fini(struct drm_device *drm, void *arg)
hwe->gt = NULL;
}
-static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, u32 reg, u32 val)
+static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg,
+ u32 val)
{
- XE_BUG_ON(reg & hwe->mmio_base);
+ XE_BUG_ON(reg.reg & hwe->mmio_base);
xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
- xe_mmio_write32(hwe->gt, reg + hwe->mmio_base, val);
+ reg.reg += hwe->mmio_base;
+
+ xe_mmio_write32(hwe->gt, reg, val);
}
-static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, u32 reg)
+static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)
{
- XE_BUG_ON(reg & hwe->mmio_base);
+ XE_BUG_ON(reg.reg & hwe->mmio_base);
xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
- return xe_mmio_read32(hwe->gt, reg + hwe->mmio_base);
+ reg.reg += hwe->mmio_base;
+
+ return xe_mmio_read32(hwe->gt, reg);
}
void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
@@ -254,17 +259,17 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
- xe_mmio_write32(hwe->gt, RCU_MODE.reg,
+ xe_mmio_write32(hwe->gt, RCU_MODE,
_MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
- hw_engine_mmio_write32(hwe, RING_HWSTAM(0).reg, ~0x0);
- hw_engine_mmio_write32(hwe, RING_HWS_PGA(0).reg,
+ hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0);
+ hw_engine_mmio_write32(hwe, RING_HWS_PGA(0),
xe_bo_ggtt_addr(hwe->hwsp));
- hw_engine_mmio_write32(hwe, RING_MODE(0).reg,
+ hw_engine_mmio_write32(hwe, RING_MODE(0),
_MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
- hw_engine_mmio_write32(hwe, RING_MI_MODE(0).reg,
+ hw_engine_mmio_write32(hwe, RING_MI_MODE(0),
_MASKED_BIT_DISABLE(STOP_RING));
- hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg);
+ hw_engine_mmio_read32(hwe, RING_MI_MODE(0));
}
static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
@@ -379,7 +384,7 @@ static void read_media_fuses(struct xe_gt *gt)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE.reg);
+ media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE);
/*
* Pre-Xe_HP platforms had register bits representing absent engines,
@@ -421,7 +426,7 @@ static void read_copy_fuses(struct xe_gt *gt)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3.reg);
+ bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3);
bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
/* BCS0 is always present; only BCS1-BCS8 may be fused off */
@@ -518,63 +523,63 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
drm_printf(p, "\tMMIO base: 0x%08x\n", hwe->mmio_base);
drm_printf(p, "\tHWSTAM: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_HWSTAM(0).reg));
+ hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_HWS_PGA(0).reg));
+ hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
drm_printf(p, "\tRING_EXECLIST_STATUS_LO: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0).reg));
+ hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
drm_printf(p, "\tRING_EXECLIST_STATUS_HI: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0).reg));
+ hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_LO: 0x%08x\n",
hw_engine_mmio_read32(hwe,
- RING_EXECLIST_SQ_CONTENTS_LO(0).reg));
+ RING_EXECLIST_SQ_CONTENTS_LO(0)));
drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_HI: 0x%08x\n",
hw_engine_mmio_read32(hwe,
- RING_EXECLIST_SQ_CONTENTS_HI(0).reg));
+ RING_EXECLIST_SQ_CONTENTS_HI(0)));
drm_printf(p, "\tRING_EXECLIST_CONTROL: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0).reg));
+ hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
drm_printf(p, "\tRING_START: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_START(0).reg));
+ hw_engine_mmio_read32(hwe, RING_START(0)));
drm_printf(p, "\tRING_HEAD: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_HEAD(0).reg) & HEAD_ADDR);
+ hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
drm_printf(p, "\tRING_TAIL: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_TAIL(0).reg) & TAIL_ADDR);
+ hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
drm_printf(p, "\tRING_CTL: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_CTL(0).reg));
+ hw_engine_mmio_read32(hwe, RING_CTL(0)));
drm_printf(p, "\tRING_MODE: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg));
+ hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
drm_printf(p, "\tRING_MODE_GEN7: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_MODE(0).reg));
+ hw_engine_mmio_read32(hwe, RING_MODE(0)));
drm_printf(p, "\tRING_IMR: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_IMR(0).reg));
+ hw_engine_mmio_read32(hwe, RING_IMR(0)));
drm_printf(p, "\tRING_ESR: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_ESR(0).reg));
+ hw_engine_mmio_read32(hwe, RING_ESR(0)));
drm_printf(p, "\tRING_EMR: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_EMR(0).reg));
+ hw_engine_mmio_read32(hwe, RING_EMR(0)));
drm_printf(p, "\tRING_EIR: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_EIR(0).reg));
+ hw_engine_mmio_read32(hwe, RING_EIR(0)));
drm_printf(p, "\tACTHD: 0x%08x_%08x\n",
- hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0).reg),
- hw_engine_mmio_read32(hwe, RING_ACTHD(0).reg));
+ hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
+ hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
- hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0).reg),
- hw_engine_mmio_read32(hwe, RING_BBADDR(0).reg));
+ hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
+ hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
- hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0).reg),
- hw_engine_mmio_read32(hwe, RING_DMA_FADD(0).reg));
+ hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
+ hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
drm_printf(p, "\tIPEIR: 0x%08x\n",
- hw_engine_mmio_read32(hwe, IPEIR(0).reg));
+ hw_engine_mmio_read32(hwe, IPEIR(0)));
drm_printf(p, "\tIPEHR: 0x%08x\n\n",
- hw_engine_mmio_read32(hwe, IPEHR(0).reg));
+ hw_engine_mmio_read32(hwe, IPEHR(0)));
if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
drm_printf(p, "\tRCU_MODE: 0x%08x\n",
- xe_mmio_read32(hwe->gt, RCU_MODE.reg));
+ xe_mmio_read32(hwe->gt, RCU_MODE));
}
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index ac72c1a38e5c..7aa245792927 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -29,7 +29,7 @@
static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
{
- u32 val = xe_mmio_read32(gt, reg.reg);
+ u32 val = xe_mmio_read32(gt, reg);
if (val == 0)
return;
@@ -37,10 +37,10 @@ static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
drm_WARN(>_to_xe(gt)->drm, 1,
"Interrupt register 0x%x is not zero: 0x%08x\n",
reg.reg, val);
- xe_mmio_write32(gt, reg.reg, 0xffffffff);
- xe_mmio_read32(gt, reg.reg);
- xe_mmio_write32(gt, reg.reg, 0xffffffff);
- xe_mmio_read32(gt, reg.reg);
+ xe_mmio_write32(gt, reg, 0xffffffff);
+ xe_mmio_read32(gt, reg);
+ xe_mmio_write32(gt, reg, 0xffffffff);
+ xe_mmio_read32(gt, reg);
}
/*
@@ -55,32 +55,32 @@ static void unmask_and_enable(struct xe_gt *gt, u32 irqregs, u32 bits)
*/
assert_iir_is_zero(gt, IIR(irqregs));
- xe_mmio_write32(gt, IER(irqregs).reg, bits);
- xe_mmio_write32(gt, IMR(irqregs).reg, ~bits);
+ xe_mmio_write32(gt, IER(irqregs), bits);
+ xe_mmio_write32(gt, IMR(irqregs), ~bits);
/* Posting read */
- xe_mmio_read32(gt, IMR(irqregs).reg);
+ xe_mmio_read32(gt, IMR(irqregs));
}
/* Mask and disable all interrupts. */
static void mask_and_disable(struct xe_gt *gt, u32 irqregs)
{
- xe_mmio_write32(gt, IMR(irqregs).reg, ~0);
+ xe_mmio_write32(gt, IMR(irqregs), ~0);
/* Posting read */
- xe_mmio_read32(gt, IMR(irqregs).reg);
+ xe_mmio_read32(gt, IMR(irqregs));
- xe_mmio_write32(gt, IER(irqregs).reg, 0);
+ xe_mmio_write32(gt, IER(irqregs), 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- xe_mmio_write32(gt, IIR(irqregs).reg, ~0);
- xe_mmio_read32(gt, IIR(irqregs).reg);
- xe_mmio_write32(gt, IIR(irqregs).reg, ~0);
- xe_mmio_read32(gt, IIR(irqregs).reg);
+ xe_mmio_write32(gt, IIR(irqregs), ~0);
+ xe_mmio_read32(gt, IIR(irqregs));
+ xe_mmio_write32(gt, IIR(irqregs), ~0);
+ xe_mmio_read32(gt, IIR(irqregs));
}
static u32 xelp_intr_disable(struct xe_gt *gt)
{
- xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, 0);
+ xe_mmio_write32(gt, GFX_MSTR_IRQ, 0);
/*
* Now with master disabled, get a sample of level indications
@@ -88,7 +88,7 @@ static u32 xelp_intr_disable(struct xe_gt *gt)
* New indications can and will light up during processing,
* and will generate new interrupt after enabling master.
*/
- return xe_mmio_read32(gt, GFX_MSTR_IRQ.reg);
+ return xe_mmio_read32(gt, GFX_MSTR_IRQ);
}
static u32
@@ -99,18 +99,18 @@ gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
if (!(master_ctl & GU_MISC_IRQ))
return 0;
- iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET).reg);
+ iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET));
if (likely(iir))
- xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET).reg, iir);
+ xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET), iir);
return iir;
}
static inline void xelp_intr_enable(struct xe_gt *gt, bool stall)
{
- xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, MASTER_IRQ);
+ xe_mmio_write32(gt, GFX_MSTR_IRQ, MASTER_IRQ);
if (stall)
- xe_mmio_read32(gt, GFX_MSTR_IRQ.reg);
+ xe_mmio_read32(gt, GFX_MSTR_IRQ);
}
static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
@@ -133,41 +133,41 @@ static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
smask = irqs << 16;
/* Enable RCS, BCS, VCS and VECS class interrupts. */
- xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE.reg, dmask);
- xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE.reg, dmask);
+ xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
+ xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
if (ccs_mask)
- xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE.reg, smask);
+ xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
- xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK.reg, ~smask);
- xe_mmio_write32(gt, BCS_RSVD_INTR_MASK.reg, ~smask);
+ xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
+ xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
if (bcs_mask & (BIT(1)|BIT(2)))
- xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK.reg, ~dmask);
+ xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
if (bcs_mask & (BIT(3)|BIT(4)))
- xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK.reg, ~dmask);
+ xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
if (bcs_mask & (BIT(5)|BIT(6)))
- xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK.reg, ~dmask);
+ xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
if (bcs_mask & (BIT(7)|BIT(8)))
- xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK.reg, ~dmask);
- xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK.reg, ~dmask);
- xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK.reg, ~dmask);
- xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK.reg, ~dmask);
+ xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
+ xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
+ xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
+ xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
if (ccs_mask & (BIT(0)|BIT(1)))
- xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK.reg, ~dmask);
+ xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
if (ccs_mask & (BIT(2)|BIT(3)))
- xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK.reg, ~dmask);
+ xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled.
*/
/* TODO: gt->pm_ier, gt->pm_imr */
- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE.reg, 0);
- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK.reg, ~0);
+ xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
+ xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
/* Same thing for GuC interrupts */
- xe_mmio_write32(gt, GUC_SG_INTR_ENABLE.reg, 0);
- xe_mmio_write32(gt, GUC_SG_INTR_MASK.reg, ~0);
+ xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
+ xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
}
static void xelp_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
@@ -192,7 +192,7 @@ gt_engine_identity(struct xe_device *xe,
lockdep_assert_held(&xe->irq.lock);
- xe_mmio_write32(gt, IIR_REG_SELECTOR(bank).reg, BIT(bit));
+ xe_mmio_write32(gt, IIR_REG_SELECTOR(bank), BIT(bit));
/*
* NB: Specs do not specify how long to spin wait,
@@ -200,7 +200,7 @@ gt_engine_identity(struct xe_device *xe,
*/
timeout_ts = (local_clock() >> 10) + 100;
do {
- ident = xe_mmio_read32(gt, INTR_IDENTITY_REG(bank).reg);
+ ident = xe_mmio_read32(gt, INTR_IDENTITY_REG(bank));
} while (!(ident & INTR_DATA_VALID) &&
!time_after32(local_clock() >> 10, timeout_ts));
@@ -210,7 +210,7 @@ gt_engine_identity(struct xe_device *xe,
return 0;
}
- xe_mmio_write32(gt, INTR_IDENTITY_REG(bank).reg, INTR_DATA_VALID);
+ xe_mmio_write32(gt, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
return ident;
}
@@ -249,11 +249,11 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
if (!xe_gt_is_media_type(gt)) {
intr_dw[bank] =
- xe_mmio_read32(gt, GT_INTR_DW(bank).reg);
+ xe_mmio_read32(gt, GT_INTR_DW(bank));
for_each_set_bit(bit, intr_dw + bank, 32)
identity[bit] = gt_engine_identity(xe, gt,
bank, bit);
- xe_mmio_write32(gt, GT_INTR_DW(bank).reg,
+ xe_mmio_write32(gt, GT_INTR_DW(bank),
intr_dw[bank]);
}
@@ -315,14 +315,14 @@ static u32 dg1_intr_disable(struct xe_device *xe)
u32 val;
/* First disable interrupts */
- xe_mmio_write32(gt, DG1_MSTR_TILE_INTR.reg, 0);
+ xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, 0);
/* Get the indication levels and ack the master unit */
- val = xe_mmio_read32(gt, DG1_MSTR_TILE_INTR.reg);
+ val = xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
if (unlikely(!val))
return 0;
- xe_mmio_write32(gt, DG1_MSTR_TILE_INTR.reg, val);
+ xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, val);
return val;
}
@@ -331,9 +331,9 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
{
struct xe_gt *gt = xe_device_get_gt(xe, 0);
- xe_mmio_write32(gt, DG1_MSTR_TILE_INTR.reg, DG1_MSTR_IRQ);
+ xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
if (stall)
- xe_mmio_read32(gt, DG1_MSTR_TILE_INTR.reg);
+ xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
}
static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
@@ -373,7 +373,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
continue;
if (!xe_gt_is_media_type(gt))
- master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ.reg);
+ master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ);
/*
* We might be in irq handler just when PCIe DPC is initiated
@@ -387,7 +387,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
}
if (!xe_gt_is_media_type(gt))
- xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, master_ctl);
+ xe_mmio_write32(gt, GFX_MSTR_IRQ, master_ctl);
gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
/*
@@ -416,34 +416,34 @@ static void gt_irq_reset(struct xe_gt *gt)
u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
/* Disable RCS, BCS, VCS and VECS class engines. */
- xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE.reg, 0);
- xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE.reg, 0);
+ xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, 0);
+ xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, 0);
if (ccs_mask)
- xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE.reg, 0);
+ xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, 0);
/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
- xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK.reg, ~0);
- xe_mmio_write32(gt, BCS_RSVD_INTR_MASK.reg, ~0);
+ xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~0);
+ xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~0);
if (bcs_mask & (BIT(1)|BIT(2)))
- xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK.reg, ~0);
+ xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
if (bcs_mask & (BIT(3)|BIT(4)))
- xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK.reg, ~0);
+ xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
if (bcs_mask & (BIT(5)|BIT(6)))
- xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK.reg, ~0);
+ xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
if (bcs_mask & (BIT(7)|BIT(8)))
- xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK.reg, ~0);
- xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK.reg, ~0);
- xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK.reg, ~0);
- xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK.reg, ~0);
+ xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
+ xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~0);
+ xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~0);
+ xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~0);
if (ccs_mask & (BIT(0)|BIT(1)))
- xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK.reg, ~0);
+ xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~0);
if (ccs_mask & (BIT(2)|BIT(3)))
- xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK.reg, ~0);
+ xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~0);
- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE.reg, 0);
- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK.reg, ~0);
- xe_mmio_write32(gt, GUC_SG_INTR_ENABLE.reg, 0);
- xe_mmio_write32(gt, GUC_SG_INTR_MASK.reg, ~0);
+ xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
+ xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
+ xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
+ xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
}
static void xelp_irq_reset(struct xe_gt *gt)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 3b719c774efa..0e91004fa06d 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -153,13 +153,13 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_si
struct xe_gt *gt = xe_device_get_gt(xe, 0);
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
int err;
- u32 reg;
+ u32 reg_val;
if (!xe->info.has_flat_ccs) {
*vram_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
if (usable_size)
*usable_size = min(*vram_size,
- xe_mmio_read64(gt, GSMBASE.reg));
+ xe_mmio_read64(gt, GSMBASE));
return 0;
}
@@ -167,11 +167,11 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_si
if (err)
return err;
- reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE0_ADDR_RANGE);
- *vram_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
+ reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE0_ADDR_RANGE);
+ *vram_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg_val) * SZ_1G;
if (usable_size) {
- reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
- *usable_size = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
+ reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
+ *usable_size = (u64)REG_FIELD_GET(GENMASK(31, 8), reg_val) * SZ_64K;
drm_info(&xe->drm, "vram_size: 0x%llx usable_size: 0x%llx\n",
*vram_size, *usable_size);
}
@@ -298,7 +298,7 @@ static void xe_mmio_probe_tiles(struct xe_device *xe)
if (xe->info.tile_count == 1)
return;
- mtcfg = xe_mmio_read64(gt, XEHP_MTCFG_ADDR.reg);
+ mtcfg = xe_mmio_read64(gt, XEHP_MTCFG_ADDR);
adj_tile_count = xe->info.tile_count =
REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
if (xe->info.media_verx100 >= 1300)
@@ -374,7 +374,7 @@ int xe_mmio_init(struct xe_device *xe)
* keep the GT powered down; we won't be able to communicate with it
* and we should not continue with driver initialization.
*/
- if (IS_DGFX(xe) && !(xe_mmio_read32(gt, GU_CNTL.reg) & LMEM_INIT)) {
+ if (IS_DGFX(xe) && !(xe_mmio_read32(gt, GU_CNTL) & LMEM_INIT)) {
drm_err(&xe->drm, "VRAM not initialized by firmware\n");
return -ENODEV;
}
@@ -403,6 +403,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
struct xe_device *xe = to_xe_device(dev);
struct drm_xe_mmio *args = data;
unsigned int bits_flag, bytes;
+ struct xe_reg reg;
bool allowed;
int ret = 0;
@@ -435,6 +436,12 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
if (XE_IOCTL_ERR(xe, args->addr + bytes > xe->mmio.size))
return -EINVAL;
+ /*
+ * TODO: migrate to xe_gt_mcr to lookup the mmio range and handle
+ * multicast registers. Steering would need uapi extension.
+ */
+ reg = XE_REG(args->addr);
+
xe_force_wake_get(gt_to_fw(&xe->gt[0]), XE_FORCEWAKE_ALL);
if (args->flags & DRM_XE_MMIO_WRITE) {
@@ -444,10 +451,10 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
ret = -EINVAL;
goto exit;
}
- xe_mmio_write32(to_gt(xe), args->addr, args->value);
+ xe_mmio_write32(to_gt(xe), reg, args->value);
break;
case DRM_XE_MMIO_64BIT:
- xe_mmio_write64(to_gt(xe), args->addr, args->value);
+ xe_mmio_write64(to_gt(xe), reg, args->value);
break;
default:
drm_dbg(&xe->drm, "Invalid MMIO bit size");
@@ -462,10 +469,10 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
if (args->flags & DRM_XE_MMIO_READ) {
switch (bits_flag) {
case DRM_XE_MMIO_32BIT:
- args->value = xe_mmio_read32(to_gt(xe), args->addr);
+ args->value = xe_mmio_read32(to_gt(xe), reg);
break;
case DRM_XE_MMIO_64BIT:
- args->value = xe_mmio_read64(to_gt(xe), args->addr);
+ args->value = xe_mmio_read64(to_gt(xe), reg);
break;
default:
drm_dbg(&xe->drm, "Invalid MMIO bit size");
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 1a32e0f52261..0f792a196545 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -9,6 +9,7 @@
#include <linux/delay.h>
#include <linux/io-64-nonatomic-lo-hi.h>
+#include "regs/xe_reg_defs.h"
#include "xe_gt_types.h"
struct drm_device;
@@ -18,23 +19,23 @@ struct xe_device;
int xe_mmio_init(struct xe_device *xe);
static inline void xe_mmio_write32(struct xe_gt *gt,
- u32 reg, u32 val)
+ struct xe_reg reg, u32 val)
{
- if (reg < gt->mmio.adj_limit)
- reg += gt->mmio.adj_offset;
+ if (reg.reg < gt->mmio.adj_limit)
+ reg.reg += gt->mmio.adj_offset;
- writel(val, gt->mmio.regs + reg);
+ writel(val, gt->mmio.regs + reg.reg);
}
-static inline u32 xe_mmio_read32(struct xe_gt *gt, u32 reg)
+static inline u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
{
- if (reg < gt->mmio.adj_limit)
- reg += gt->mmio.adj_offset;
+ if (reg.reg < gt->mmio.adj_limit)
+ reg.reg += gt->mmio.adj_offset;
- return readl(gt->mmio.regs + reg);
+ return readl(gt->mmio.regs + reg.reg);
}
-static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 clr,
+static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,
u32 set)
{
u32 old, reg_val;
@@ -47,24 +48,24 @@ static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 clr,
}
static inline void xe_mmio_write64(struct xe_gt *gt,
- u32 reg, u64 val)
+ struct xe_reg reg, u64 val)
{
- if (reg < gt->mmio.adj_limit)
- reg += gt->mmio.adj_offset;
+ if (reg.reg < gt->mmio.adj_limit)
+ reg.reg += gt->mmio.adj_offset;
- writeq(val, gt->mmio.regs + reg);
+ writeq(val, gt->mmio.regs + reg.reg);
}
-static inline u64 xe_mmio_read64(struct xe_gt *gt, u32 reg)
+static inline u64 xe_mmio_read64(struct xe_gt *gt, struct xe_reg reg)
{
- if (reg < gt->mmio.adj_limit)
- reg += gt->mmio.adj_offset;
+ if (reg.reg < gt->mmio.adj_limit)
+ reg.reg += gt->mmio.adj_offset;
- return readq(gt->mmio.regs + reg);
+ return readq(gt->mmio.regs + reg.reg);
}
static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
- u32 reg, u32 val,
+ struct xe_reg reg, u32 val,
u32 mask, u32 eval)
{
u32 reg_val;
@@ -75,8 +76,9 @@ static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
return (reg_val & mask) != eval ? -EINVAL : 0;
}
-static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val, u32 mask,
- u32 timeout_us, u32 *out_val, bool atomic)
+static inline int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 val,
+ u32 mask, u32 timeout_us, u32 *out_val,
+ bool atomic)
{
ktime_t cur = ktime_get_raw();
const ktime_t end = ktime_add_us(cur, timeout_us);
@@ -114,9 +116,10 @@ static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val, u32 mask,
int xe_mmio_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
-static inline bool xe_mmio_in_range(const struct xe_mmio_range *range, u32 reg)
+static inline bool xe_mmio_in_range(const struct xe_mmio_range *range,
+ struct xe_reg reg)
{
- return range && reg >= range->start && reg <= range->end;
+ return range && reg.reg >= range->start && reg.reg <= range->end;
}
int xe_mmio_probe_vram(struct xe_device *xe);
diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index f2ceecd536ed..7ad43e53f826 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -477,8 +477,9 @@ static void __init_mocs_table(struct xe_gt *gt,
for (i = 0;
i < info->n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;
i++) {
- mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, XE_REG(addr + i * 4).reg, mocs);
- xe_mmio_write32(gt, XE_REG(addr + i * 4).reg, mocs);
+ struct xe_reg reg = XE_REG(addr + i * 4);
+ mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, reg.reg, mocs);
+ xe_mmio_write32(gt, reg, mocs);
}
}
@@ -514,7 +515,7 @@ static void init_l3cc_table(struct xe_gt *gt,
i++) {
mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).reg,
l3cc);
- xe_mmio_write32(gt, LNCFCMOCS(i).reg, l3cc);
+ xe_mmio_write32(gt, LNCFCMOCS(i), l3cc);
}
}
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index abee41fa3cb9..b56a65779d26 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -64,14 +64,20 @@ static const u32 mtl_pat_table[] = {
static void program_pat(struct xe_gt *gt, const u32 table[], int n_entries)
{
- for (int i = 0; i < n_entries; i++)
- xe_mmio_write32(gt, _PAT_INDEX(i), table[i]);
+ for (int i = 0; i < n_entries; i++) {
+ struct xe_reg reg = XE_REG(_PAT_INDEX(i));
+
+ xe_mmio_write32(gt, reg, table[i]);
+ }
}
static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries)
{
- for (int i = 0; i < n_entries; i++)
- xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_INDEX(i)), table[i]);
+ for (int i = 0; i < n_entries; i++) {
+ struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i));
+
+ xe_gt_mcr_multicast_write(gt, reg_mcr, table[i]);
+ }
}
void xe_pat_init(struct xe_gt *gt)
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 99bb730684ed..7ab70a83f88d 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -43,7 +43,7 @@ static int pcode_mailbox_status(struct xe_gt *gt)
lockdep_assert_held(>->pcode.lock);
- err = xe_mmio_read32(gt, PCODE_MAILBOX.reg) & PCODE_ERROR_MASK;
+ err = xe_mmio_read32(gt, PCODE_MAILBOX) & PCODE_ERROR_MASK;
if (err) {
drm_err(>_to_xe(gt)->drm, "PCODE Mailbox failed: %d %s", err,
err_decode[err].str ?: "Unknown");
@@ -60,22 +60,22 @@ static int pcode_mailbox_rw(struct xe_gt *gt, u32 mbox, u32 *data0, u32 *data1,
int err;
lockdep_assert_held(>->pcode.lock);
- if ((xe_mmio_read32(gt, PCODE_MAILBOX.reg) & PCODE_READY) != 0)
+ if ((xe_mmio_read32(gt, PCODE_MAILBOX) & PCODE_READY) != 0)
return -EAGAIN;
- xe_mmio_write32(gt, PCODE_DATA0.reg, *data0);
- xe_mmio_write32(gt, PCODE_DATA1.reg, data1 ? *data1 : 0);
- xe_mmio_write32(gt, PCODE_MAILBOX.reg, PCODE_READY | mbox);
+ xe_mmio_write32(gt, PCODE_DATA0, *data0);
+ xe_mmio_write32(gt, PCODE_DATA1, data1 ? *data1 : 0);
+ xe_mmio_write32(gt, PCODE_MAILBOX, PCODE_READY | mbox);
- err = xe_mmio_wait32(gt, PCODE_MAILBOX.reg, 0, PCODE_READY,
+ err = xe_mmio_wait32(gt, PCODE_MAILBOX, 0, PCODE_READY,
timeout_ms * 1000, NULL, atomic);
if (err)
return err;
if (return_data) {
- *data0 = xe_mmio_read32(gt, PCODE_DATA0.reg);
+ *data0 = xe_mmio_read32(gt, PCODE_DATA0);
if (data1)
- *data1 = xe_mmio_read32(gt, PCODE_DATA1.reg);
+ *data1 = xe_mmio_read32(gt, PCODE_DATA1);
}
return pcode_mailbox_status(gt);
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index 801f211fb733..51a40a9e532d 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -163,7 +163,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
else if (entry->clr_bits + 1)
val = (reg.mcr ?
xe_gt_mcr_unicast_read_any(gt, reg_mcr) :
- xe_mmio_read32(gt, reg.reg)) & (~entry->clr_bits);
+ xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
else
val = 0;
@@ -179,7 +179,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
if (entry->reg.mcr)
xe_gt_mcr_multicast_write(gt, reg_mcr, val);
else
- xe_mmio_write32(gt, reg.reg, val);
+ xe_mmio_write32(gt, reg, val);
}
void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt)
@@ -232,15 +232,17 @@ void xe_reg_sr_apply_whitelist(struct xe_reg_sr *sr, u32 mmio_base,
p = drm_debug_printer(KBUILD_MODNAME);
xa_for_each(&sr->xa, reg, entry) {
xe_reg_whitelist_print_entry(&p, 0, reg, entry);
- xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot).reg,
+ xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot),
reg | entry->set_bits);
slot++;
}
/* And clear the rest just in case of garbage */
- for (; slot < RING_MAX_NONPRIV_SLOTS; slot++)
- xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot).reg,
- RING_NOPID(mmio_base).reg);
+ for (; slot < RING_MAX_NONPRIV_SLOTS; slot++) {
+ u32 addr = RING_NOPID(mmio_base).reg;
+
+ xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
+ }
err = xe_force_wake_put(>->mmio.fw, XE_FORCEWAKE_ALL);
XE_WARN_ON(err);
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 5e61b6e61f3a..efc59eb4a491 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -44,10 +44,11 @@ static u32 preparser_disable(bool state)
return MI_ARB_CHECK | BIT(8) | state;
}
-static int emit_aux_table_inv(struct xe_gt *gt, u32 addr, u32 *dw, int i)
+static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
+ u32 *dw, int i)
{
dw[i++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
- dw[i++] = addr + gt->mmio.adj_offset;
+ dw[i++] = reg.reg + gt->mmio.adj_offset;
dw[i++] = AUX_INV;
dw[i++] = MI_NOOP;
@@ -202,9 +203,9 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
/* Wa_1809175790 */
if (!xe->info.has_flat_ccs) {
if (decode)
- i = emit_aux_table_inv(gt, VD0_AUX_NV.reg, dw, i);
+ i = emit_aux_table_inv(gt, VD0_AUX_NV, dw, i);
else
- i = emit_aux_table_inv(gt, VE0_AUX_NV.reg, dw, i);
+ i = emit_aux_table_inv(gt, VE0_AUX_NV, dw, i);
}
dw[i++] = preparser_disable(false);
@@ -246,7 +247,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
i = emit_pipe_invalidate(mask_flags, dw, i);
/* Wa_1809175790 */
if (!xe->info.has_flat_ccs)
- i = emit_aux_table_inv(gt, GFX_CCS_AUX_NV.reg, dw, i);
+ i = emit_aux_table_inv(gt, GFX_CCS_AUX_NV, dw, i);
dw[i++] = preparser_disable(false);
i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
index 9ce0a0585539..a3855870321f 100644
--- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
@@ -65,7 +65,7 @@ static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
}
/* Use DSM base address instead for stolen memory */
- mgr->stolen_base = xe_mmio_read64(gt, DSMBASE.reg) & BDSM_MASK;
+ mgr->stolen_base = xe_mmio_read64(gt, DSMBASE) & BDSM_MASK;
if (drm_WARN_ON(&xe->drm, vram_size < mgr->stolen_base))
return 0;
@@ -88,7 +88,7 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr
u32 stolen_size;
u32 ggc, gms;
- ggc = xe_mmio_read32(to_gt(xe), GGC.reg);
+ ggc = xe_mmio_read32(to_gt(xe), GGC);
/* check GGMS, should be fixed 0x3 (8MB) */
if (drm_WARN_ON(&xe->drm, (ggc & GGMS_MASK) != GGMS_MASK))
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index cd5433b5c970..5c3a571d2a29 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -462,33 +462,33 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
/* Set the source address for the uCode */
src_offset = uc_fw_ggtt_offset(uc_fw);
- xe_mmio_write32(gt, DMA_ADDR_0_LOW.reg, lower_32_bits(src_offset));
- xe_mmio_write32(gt, DMA_ADDR_0_HIGH.reg, upper_32_bits(src_offset));
+ xe_mmio_write32(gt, DMA_ADDR_0_LOW, lower_32_bits(src_offset));
+ xe_mmio_write32(gt, DMA_ADDR_0_HIGH, upper_32_bits(src_offset));
/* Set the DMA destination */
- xe_mmio_write32(gt, DMA_ADDR_1_LOW.reg, offset);
- xe_mmio_write32(gt, DMA_ADDR_1_HIGH.reg, DMA_ADDRESS_SPACE_WOPCM);
+ xe_mmio_write32(gt, DMA_ADDR_1_LOW, offset);
+ xe_mmio_write32(gt, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
/*
* Set the transfer size. The header plus uCode will be copied to WOPCM
* via DMA, excluding any other components
*/
- xe_mmio_write32(gt, DMA_COPY_SIZE.reg,
+ xe_mmio_write32(gt, DMA_COPY_SIZE,
sizeof(struct uc_css_header) + uc_fw->ucode_size);
/* Start the DMA */
- xe_mmio_write32(gt, DMA_CTRL.reg,
+ xe_mmio_write32(gt, DMA_CTRL,
_MASKED_BIT_ENABLE(dma_flags | START_DMA));
/* Wait for DMA to finish */
- ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100000, &dma_ctrl,
+ ret = xe_mmio_wait32(gt, DMA_CTRL, 0, START_DMA, 100000, &dma_ctrl,
false);
if (ret)
drm_err(&xe->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);
/* Disable the bits once DMA is over */
- xe_mmio_write32(gt, DMA_CTRL.reg, _MASKED_BIT_DISABLE(dma_flags));
+ xe_mmio_write32(gt, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
return ret;
}
diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
index 7b5014aea9c8..11eea970c207 100644
--- a/drivers/gpu/drm/xe/xe_wopcm.c
+++ b/drivers/gpu/drm/xe/xe_wopcm.c
@@ -124,8 +124,8 @@ static bool __check_layout(struct xe_device *xe, u32 wopcm_size,
static bool __wopcm_regs_locked(struct xe_gt *gt,
u32 *guc_wopcm_base, u32 *guc_wopcm_size)
{
- u32 reg_base = xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET.reg);
- u32 reg_size = xe_mmio_read32(gt, GUC_WOPCM_SIZE.reg);
+ u32 reg_base = xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET);
+ u32 reg_size = xe_mmio_read32(gt, GUC_WOPCM_SIZE);
if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) ||
!(reg_base & GUC_WOPCM_OFFSET_VALID))
@@ -152,13 +152,13 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
XE_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
- err = xe_mmio_write32_and_verify(gt, GUC_WOPCM_SIZE.reg, size, mask,
+ err = xe_mmio_write32_and_verify(gt, GUC_WOPCM_SIZE, size, mask,
size | GUC_WOPCM_SIZE_LOCKED);
if (err)
goto err_out;
mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
- err = xe_mmio_write32_and_verify(gt, DMA_GUC_WOPCM_OFFSET.reg,
+ err = xe_mmio_write32_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
base | huc_agent, mask,
base | huc_agent |
GUC_WOPCM_OFFSET_VALID);
@@ -171,10 +171,10 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
drm_notice(&xe->drm, "Failed to init uC WOPCM registers!\n");
drm_notice(&xe->drm, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
DMA_GUC_WOPCM_OFFSET.reg,
- xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET.reg));
+ xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET));
drm_notice(&xe->drm, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
GUC_WOPCM_SIZE.reg,
- xe_mmio_read32(gt, GUC_WOPCM_SIZE.reg));
+ xe_mmio_read32(gt, GUC_WOPCM_SIZE));
return err;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-xe] [PATCH 5/7] fixup! drm/xe/display: Implement display support
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
` (3 preceding siblings ...)
2023-04-29 6:23 ` [Intel-xe] [PATCH 4/7] drm/xe/mmio: Use struct xe_reg Lucas De Marchi
@ 2023-04-29 6:23 ` Lucas De Marchi
2023-05-05 16:59 ` Rodrigo Vivi
2023-04-29 6:23 ` [Intel-xe] [PATCH 6/7] drm/xe: Rename reg field to addr Lucas De Marchi
` (5 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Lucas De Marchi @ 2023-04-29 6:23 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi
With the move of display above xe_reg conversion in xe_mmio,
it should use the new types everywhere.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/display/xe_de.h | 89 +++++++++++++++++++-----------
1 file changed, 57 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_de.h b/drivers/gpu/drm/xe/display/xe_de.h
index 0c76b0d24d96..e6021f6d031d 100644
--- a/drivers/gpu/drm/xe/display/xe_de.h
+++ b/drivers/gpu/drm/xe/display/xe_de.h
@@ -14,79 +14,95 @@
#include "i915_reg.h"
static inline u32
-intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
+intel_de_read(struct drm_i915_private *i915, i915_reg_t i915_reg)
{
- return xe_mmio_read32(to_gt(i915), reg.reg);
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ return xe_mmio_read32(to_gt(i915), reg);
}
static inline u64
intel_de_read64_2x32(struct drm_i915_private *i915,
- i915_reg_t lower_reg, i915_reg_t upper_reg)
+ i915_reg_t i915_lower_reg, i915_reg_t i915_upper_reg)
{
+ struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));
+ struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));
u32 upper, lower;
- lower = xe_mmio_read32(to_gt(i915), lower_reg.reg);
- upper = xe_mmio_read32(to_gt(i915), upper_reg.reg);
+ lower = xe_mmio_read32(to_gt(i915), lower_reg);
+ upper = xe_mmio_read32(to_gt(i915), upper_reg);
return (u64)upper << 32 | lower;
}
static inline void
-intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
+intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t i915_reg)
{
- xe_mmio_read32(to_gt(i915), reg.reg);
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ xe_mmio_read32(to_gt(i915), reg);
}
static inline void
-intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
+intel_de_write(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 val)
{
- xe_mmio_write32(to_gt(i915), reg.reg, val);
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ xe_mmio_write32(to_gt(i915), reg, val);
}
static inline u32
-intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
+intel_de_rmw(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 clear, u32 set)
{
- return xe_mmio_rmw32(to_gt(i915), reg.reg, clear, set);
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ return xe_mmio_rmw32(to_gt(i915), reg, clear, set);
}
static inline int
-intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
+intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t i915_reg,
u32 mask, u32 value, unsigned int timeout)
{
- return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
- false);
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ return xe_mmio_wait32(to_gt(i915), reg, value, mask,
+ timeout * USEC_PER_MSEC, NULL, false);
}
static inline int
-intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
+intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t i915_reg,
u32 mask, u32 value, unsigned int timeout)
{
- return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
- false);
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ return xe_mmio_wait32(to_gt(i915), reg, value, mask,
+ timeout * USEC_PER_MSEC, NULL, false);
}
static inline int
-__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
+__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t i915_reg,
u32 mask, u32 value,
unsigned int fast_timeout_us,
unsigned int slow_timeout_ms, u32 *out_value)
{
- return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask,
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ return xe_mmio_wait32(to_gt(i915), reg, value, mask,
fast_timeout_us + 1000 * slow_timeout_ms,
out_value, false);
}
static inline int
-intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
+intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t i915_reg,
u32 mask, unsigned int timeout)
{
- return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
+ return intel_de_wait_for_register(i915, i915_reg, mask, mask, timeout);
}
static inline int
-intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
+intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t i915_reg,
u32 mask, unsigned int timeout)
{
- return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
+ return intel_de_wait_for_register(i915, i915_reg, mask, 0, timeout);
}
/*
@@ -98,19 +114,23 @@ intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
* a more localised lock guarding all access to that bank of registers.
*/
static inline u32
-intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
+intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t i915_reg)
{
- return xe_mmio_read32(to_gt(i915), reg.reg);
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ return xe_mmio_read32(to_gt(i915), reg);
}
static inline void
-intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
+intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 val)
{
- xe_mmio_write32(to_gt(i915), reg.reg, val);
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ xe_mmio_write32(to_gt(i915), reg, val);
}
static inline void
-intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
+intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t i915_reg)
{
/*
* Not implemented, requires lock on all reads/writes.
@@ -120,15 +140,20 @@ intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
}
static inline u32
-intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
+intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t i915_reg)
{
- return xe_mmio_read32(to_gt(i915), reg.reg);
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ return xe_mmio_read32(to_gt(i915), reg);
}
static inline void
-intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
+intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t i915_reg,
+ u32 val)
{
- xe_mmio_write32(to_gt(i915), reg.reg, val);
+ struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
+
+ xe_mmio_write32(to_gt(i915), reg, val);
}
static inline int
--
2.40.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-xe] [PATCH 6/7] drm/xe: Rename reg field to addr
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
` (4 preceding siblings ...)
2023-04-29 6:23 ` [Intel-xe] [PATCH 5/7] fixup! drm/xe/display: Implement display support Lucas De Marchi
@ 2023-04-29 6:23 ` Lucas De Marchi
2023-05-05 17:00 ` Rodrigo Vivi
2023-04-29 6:23 ` [Intel-xe] [PATCH 7/7] drm/xe: Fix indent in xe_hw_engine_print_state() Lucas De Marchi
` (4 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Lucas De Marchi @ 2023-04-29 6:23 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi
Rename the address field to "addr" rather than "reg" so it's easier to
understand what it is.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_reg_defs.h | 6 +++---
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 2 +-
drivers/gpu/drm/xe/xe_force_wake.c | 2 +-
drivers/gpu/drm/xe/xe_gt_mcr.c | 2 +-
drivers/gpu/drm/xe/xe_guc.c | 2 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 2 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 8 ++++----
drivers/gpu/drm/xe/xe_irq.c | 2 +-
drivers/gpu/drm/xe/xe_mmio.c | 2 +-
drivers/gpu/drm/xe/xe_mmio.h | 26 +++++++++++++-------------
drivers/gpu/drm/xe/xe_mocs.c | 6 +++---
drivers/gpu/drm/xe/xe_pci.c | 2 +-
drivers/gpu/drm/xe/xe_reg_sr.c | 6 +++---
drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
drivers/gpu/drm/xe/xe_rtp.c | 2 +-
drivers/gpu/drm/xe/xe_wopcm.c | 4 ++--
16 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
index da781bc7bdc7..4554362ff4d9 100644
--- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
+++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
@@ -18,8 +18,8 @@
struct xe_reg {
union {
struct {
- /** @reg: address */
- u32 reg:22;
+ /** @addr: address */
+ u32 addr:22;
/**
* @masked: register is "masked", with upper 16bits used
* to identify the bits that are updated on the lower
@@ -71,7 +71,7 @@ struct xe_reg_mcr {
* object of the right type. However when initializing static const storage,
* where a compound statement is not allowed, this can be used instead.
*/
-#define XE_REG_INITIALIZER(r_, ...) { .reg = r_, __VA_ARGS__ }
+#define XE_REG_INITIALIZER(r_, ...) { .addr = r_, __VA_ARGS__ }
/**
diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index ad2fe8a39a78..4b2aac5ccf28 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -244,7 +244,7 @@ static void xe_rtp_process_tests(struct kunit *test)
xe_rtp_process(param->entries, reg_sr, &xe->gt[0], NULL);
xa_for_each(®_sr->xa, idx, sre) {
- if (idx == param->expected_reg.reg)
+ if (idx == param->expected_reg.addr)
sr_entry = sre;
count++;
diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index 363b81c3d746..f0f0592fc598 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -129,7 +129,7 @@ static int domain_sleep_wait(struct xe_gt *gt,
for (tmp__ = (mask__); tmp__; tmp__ &= ~BIT(ffs(tmp__) - 1)) \
for_each_if((domain__ = ((fw__)->domains + \
(ffs(tmp__) - 1))) && \
- domain__->reg_ctl.reg)
+ domain__->reg_ctl.addr)
int xe_force_wake_get(struct xe_force_wake *fw,
enum xe_force_wake_domains domains)
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 2461e51c0abf..6a9be9d031d4 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -398,7 +398,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
*/
drm_WARN(>_to_xe(gt)->drm, true,
"Did not find MCR register %#x in any MCR steering table\n",
- reg.reg);
+ reg.addr);
*group = 0;
*instance = 0;
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 12b636910460..af7b09086358 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -721,7 +721,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
response_buf[0] = header;
for (i = 1; i < VF_SW_FLAG_COUNT; i++) {
- reply_reg.reg += i * sizeof(u32);
+ reply_reg.addr += i * sizeof(u32);
response_buf[i] = xe_mmio_read32(gt, reply_reg);
}
}
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 683f2df09c49..6d550d746909 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -426,7 +426,7 @@ static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,
unsigned int n_entry)
{
struct guc_mmio_reg entry = {
- .offset = reg.reg,
+ .offset = reg.addr,
.flags = reg.masked ? GUC_REGSET_MASKED : 0,
};
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index d1b7ac35c4a0..e62662bc3a86 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -235,20 +235,20 @@ static void hw_engine_fini(struct drm_device *drm, void *arg)
static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg,
u32 val)
{
- XE_BUG_ON(reg.reg & hwe->mmio_base);
+ XE_BUG_ON(reg.addr & hwe->mmio_base);
xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
- reg.reg += hwe->mmio_base;
+ reg.addr += hwe->mmio_base;
xe_mmio_write32(hwe->gt, reg, val);
}
static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)
{
- XE_BUG_ON(reg.reg & hwe->mmio_base);
+ XE_BUG_ON(reg.addr & hwe->mmio_base);
xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
- reg.reg += hwe->mmio_base;
+ reg.addr += hwe->mmio_base;
return xe_mmio_read32(hwe->gt, reg);
}
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 7aa245792927..5bf359c81cc5 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -36,7 +36,7 @@ static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
drm_WARN(>_to_xe(gt)->drm, 1,
"Interrupt register 0x%x is not zero: 0x%08x\n",
- reg.reg, val);
+ reg.addr, val);
xe_mmio_write32(gt, reg, 0xffffffff);
xe_mmio_read32(gt, reg);
xe_mmio_write32(gt, reg, 0xffffffff);
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 0e91004fa06d..c7fbb1cc1f64 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -421,7 +421,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
unsigned int i;
for (i = 0; i < ARRAY_SIZE(mmio_read_whitelist); i++) {
- if (mmio_read_whitelist[i].reg == args->addr) {
+ if (mmio_read_whitelist[i].addr == args->addr) {
allowed = true;
break;
}
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 0f792a196545..3b722ff0428e 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -21,18 +21,18 @@ int xe_mmio_init(struct xe_device *xe);
static inline void xe_mmio_write32(struct xe_gt *gt,
struct xe_reg reg, u32 val)
{
- if (reg.reg < gt->mmio.adj_limit)
- reg.reg += gt->mmio.adj_offset;
+ if (reg.addr < gt->mmio.adj_limit)
+ reg.addr += gt->mmio.adj_offset;
- writel(val, gt->mmio.regs + reg.reg);
+ writel(val, gt->mmio.regs + reg.addr);
}
static inline u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
{
- if (reg.reg < gt->mmio.adj_limit)
- reg.reg += gt->mmio.adj_offset;
+ if (reg.addr < gt->mmio.adj_limit)
+ reg.addr += gt->mmio.adj_offset;
- return readl(gt->mmio.regs + reg.reg);
+ return readl(gt->mmio.regs + reg.addr);
}
static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,
@@ -50,18 +50,18 @@ static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,
static inline void xe_mmio_write64(struct xe_gt *gt,
struct xe_reg reg, u64 val)
{
- if (reg.reg < gt->mmio.adj_limit)
- reg.reg += gt->mmio.adj_offset;
+ if (reg.addr < gt->mmio.adj_limit)
+ reg.addr += gt->mmio.adj_offset;
- writeq(val, gt->mmio.regs + reg.reg);
+ writeq(val, gt->mmio.regs + reg.addr);
}
static inline u64 xe_mmio_read64(struct xe_gt *gt, struct xe_reg reg)
{
- if (reg.reg < gt->mmio.adj_limit)
- reg.reg += gt->mmio.adj_offset;
+ if (reg.addr < gt->mmio.adj_limit)
+ reg.addr += gt->mmio.adj_offset;
- return readq(gt->mmio.regs + reg.reg);
+ return readq(gt->mmio.regs + reg.addr);
}
static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
@@ -119,7 +119,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
static inline bool xe_mmio_in_range(const struct xe_mmio_range *range,
struct xe_reg reg)
{
- return range && reg.reg >= range->start && reg.reg <= range->end;
+ return range && reg.addr >= range->start && reg.addr <= range->end;
}
int xe_mmio_probe_vram(struct xe_device *xe);
diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 7ad43e53f826..3ab58b267bda 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -478,7 +478,7 @@ static void __init_mocs_table(struct xe_gt *gt,
i < info->n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;
i++) {
struct xe_reg reg = XE_REG(addr + i * 4);
- mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, reg.reg, mocs);
+ mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, reg.addr, mocs);
xe_mmio_write32(gt, reg, mocs);
}
}
@@ -513,7 +513,7 @@ static void init_l3cc_table(struct xe_gt *gt,
(l3cc = l3cc_combine(get_entry_l3cc(info, 2 * i),
get_entry_l3cc(info, 2 * i + 1))), 1 : 0;
i++) {
- mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).reg,
+ mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).addr,
l3cc);
xe_mmio_write32(gt, LNCFCMOCS(i), l3cc);
}
@@ -533,7 +533,7 @@ void xe_mocs_init(struct xe_gt *gt)
gt->mocs.wb_index = table.wb_index;
if (flags & HAS_GLOBAL_MOCS)
- __init_mocs_table(gt, &table, GLOBAL_MOCS(0).reg);
+ __init_mocs_table(gt, &table, GLOBAL_MOCS(0).addr);
/*
* Initialize the L3CC table as part of mocs initalization to make
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 8687e51cb0a4..6e55809cfb3d 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -393,7 +393,7 @@ find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
static u32 peek_gmdid(struct xe_device *xe, struct xe_reg gmdid_reg)
{
- u32 gmdid_offset = gmdid_reg.reg;
+ u32 gmdid_offset = gmdid_reg.addr;
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
void __iomem *map = pci_iomap_range(pdev, 0, gmdid_offset, sizeof(u32));
u32 ver;
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index 51a40a9e532d..0312823101ad 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -93,7 +93,7 @@ static void reg_sr_inc_error(struct xe_reg_sr *sr)
int xe_reg_sr_add(struct xe_reg_sr *sr,
const struct xe_reg_sr_entry *e)
{
- unsigned long idx = e->reg.reg;
+ unsigned long idx = e->reg.addr;
struct xe_reg_sr_entry *pentry = xa_load(&sr->xa, idx);
int ret;
@@ -174,7 +174,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
*/
val |= entry->set_bits;
- drm_dbg(&xe->drm, "REG[0x%x] = 0x%08x", reg.reg, val);
+ drm_dbg(&xe->drm, "REG[0x%x] = 0x%08x", reg.addr, val);
if (entry->reg.mcr)
xe_gt_mcr_multicast_write(gt, reg_mcr, val);
@@ -239,7 +239,7 @@ void xe_reg_sr_apply_whitelist(struct xe_reg_sr *sr, u32 mmio_base,
/* And clear the rest just in case of garbage */
for (; slot < RING_MAX_NONPRIV_SLOTS; slot++) {
- u32 addr = RING_NOPID(mmio_base).reg;
+ u32 addr = RING_NOPID(mmio_base).addr;
xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
}
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index efc59eb4a491..7d90ffa16078 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -48,7 +48,7 @@ static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
u32 *dw, int i)
{
dw[i++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
- dw[i++] = reg.reg + gt->mmio.adj_offset;
+ dw[i++] = reg.addr + gt->mmio.adj_offset;
dw[i++] = AUX_INV;
dw[i++] = MI_NOOP;
diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index f2a0e8eb4936..0c6a23e14a71 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -101,7 +101,7 @@ static void rtp_add_sr_entry(const struct xe_rtp_action *action,
.read_mask = action->read_mask,
};
- sr_entry.reg.reg += mmio_base;
+ sr_entry.reg.addr += mmio_base;
xe_reg_sr_add(sr, &sr_entry);
}
diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
index 11eea970c207..35fde8965bca 100644
--- a/drivers/gpu/drm/xe/xe_wopcm.c
+++ b/drivers/gpu/drm/xe/xe_wopcm.c
@@ -170,10 +170,10 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
err_out:
drm_notice(&xe->drm, "Failed to init uC WOPCM registers!\n");
drm_notice(&xe->drm, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
- DMA_GUC_WOPCM_OFFSET.reg,
+ DMA_GUC_WOPCM_OFFSET.addr,
xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET));
drm_notice(&xe->drm, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
- GUC_WOPCM_SIZE.reg,
+ GUC_WOPCM_SIZE.addr,
xe_mmio_read32(gt, GUC_WOPCM_SIZE));
return err;
--
2.40.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-xe] [PATCH 7/7] drm/xe: Fix indent in xe_hw_engine_print_state()
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
` (5 preceding siblings ...)
2023-04-29 6:23 ` [Intel-xe] [PATCH 6/7] drm/xe: Rename reg field to addr Lucas De Marchi
@ 2023-04-29 6:23 ` Lucas De Marchi
2023-05-05 17:01 ` Rodrigo Vivi
2023-04-29 6:27 ` [Intel-xe] ✓ CI.Patch_applied: success for Convert xe_mmio to struct xe_reg Patchwork
` (3 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Lucas De Marchi @ 2023-04-29 6:23 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi
Fix the indent to align with open parenthesis, following the coding
style.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_hw_engine.c | 66 +++++++++++++++----------------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index e62662bc3a86..ca98160dc5ee 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -516,70 +516,70 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
return;
drm_printf(p, "%s (physical), logical instance=%d\n", hwe->name,
- hwe->logical_instance);
+ hwe->logical_instance);
drm_printf(p, "\tForcewake: domain 0x%x, ref %d\n",
- hwe->domain,
- xe_force_wake_ref(gt_to_fw(hwe->gt), hwe->domain));
+ hwe->domain,
+ xe_force_wake_ref(gt_to_fw(hwe->gt), hwe->domain));
drm_printf(p, "\tMMIO base: 0x%08x\n", hwe->mmio_base);
drm_printf(p, "\tHWSTAM: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
+ hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
+ hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
drm_printf(p, "\tRING_EXECLIST_STATUS_LO: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
+ hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
drm_printf(p, "\tRING_EXECLIST_STATUS_HI: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
+ hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_LO: 0x%08x\n",
- hw_engine_mmio_read32(hwe,
+ hw_engine_mmio_read32(hwe,
RING_EXECLIST_SQ_CONTENTS_LO(0)));
drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_HI: 0x%08x\n",
- hw_engine_mmio_read32(hwe,
+ hw_engine_mmio_read32(hwe,
RING_EXECLIST_SQ_CONTENTS_HI(0)));
drm_printf(p, "\tRING_EXECLIST_CONTROL: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
+ hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
drm_printf(p, "\tRING_START: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_START(0)));
+ hw_engine_mmio_read32(hwe, RING_START(0)));
drm_printf(p, "\tRING_HEAD: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
+ hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
drm_printf(p, "\tRING_TAIL: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
+ hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
drm_printf(p, "\tRING_CTL: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_CTL(0)));
+ hw_engine_mmio_read32(hwe, RING_CTL(0)));
drm_printf(p, "\tRING_MODE: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
+ hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
drm_printf(p, "\tRING_MODE_GEN7: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_MODE(0)));
+ hw_engine_mmio_read32(hwe, RING_MODE(0)));
drm_printf(p, "\tRING_IMR: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_IMR(0)));
+ hw_engine_mmio_read32(hwe, RING_IMR(0)));
drm_printf(p, "\tRING_ESR: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_ESR(0)));
+ hw_engine_mmio_read32(hwe, RING_ESR(0)));
drm_printf(p, "\tRING_EMR: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_EMR(0)));
+ hw_engine_mmio_read32(hwe, RING_EMR(0)));
drm_printf(p, "\tRING_EIR: 0x%08x\n",
- hw_engine_mmio_read32(hwe, RING_EIR(0)));
-
- drm_printf(p, "\tACTHD: 0x%08x_%08x\n",
- hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
- hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
- drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
- hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
- hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
- drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
- hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
- hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
+ hw_engine_mmio_read32(hwe, RING_EIR(0)));
+
+ drm_printf(p, "\tACTHD: 0x%08x_%08x\n",
+ hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
+ hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
+ drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
+ hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
+ hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
+ drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
+ hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
+ hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
drm_printf(p, "\tIPEIR: 0x%08x\n",
- hw_engine_mmio_read32(hwe, IPEIR(0)));
+ hw_engine_mmio_read32(hwe, IPEIR(0)));
drm_printf(p, "\tIPEHR: 0x%08x\n\n",
- hw_engine_mmio_read32(hwe, IPEHR(0)));
+ hw_engine_mmio_read32(hwe, IPEHR(0)));
if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
drm_printf(p, "\tRCU_MODE: 0x%08x\n",
- xe_mmio_read32(hwe->gt, RCU_MODE));
+ xe_mmio_read32(hwe->gt, RCU_MODE));
}
--
2.40.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-xe] ✓ CI.Patch_applied: success for Convert xe_mmio to struct xe_reg
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
` (6 preceding siblings ...)
2023-04-29 6:23 ` [Intel-xe] [PATCH 7/7] drm/xe: Fix indent in xe_hw_engine_print_state() Lucas De Marchi
@ 2023-04-29 6:27 ` Patchwork
2023-04-29 6:28 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-04-29 6:27 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
== Series Details ==
Series: Convert xe_mmio to struct xe_reg
URL : https://patchwork.freedesktop.org/series/117138/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: f7b51a4d5 drm/xe: Fix media detection for pre-GMD_ID platforms
=== git am output follows ===
Applying: fixup! drm/xe: Drop gen afixes from registers
Applying: drm/xe/guc: Handle RCU_MODE as masked from definition
Applying: drm/xe: Use media base for GMD_ID access
Applying: drm/xe/mmio: Use struct xe_reg
Applying: fixup! drm/xe/display: Implement display support
Applying: drm/xe: Rename reg field to addr
Applying: drm/xe: Fix indent in xe_hw_engine_print_state()
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-xe] ✓ CI.KUnit: success for Convert xe_mmio to struct xe_reg
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
` (7 preceding siblings ...)
2023-04-29 6:27 ` [Intel-xe] ✓ CI.Patch_applied: success for Convert xe_mmio to struct xe_reg Patchwork
@ 2023-04-29 6:28 ` Patchwork
2023-04-29 6:32 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-04-29 6:58 ` [Intel-xe] ○ CI.BAT: info " Patchwork
10 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-04-29 6:28 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
== Series Details ==
Series: Convert xe_mmio to struct xe_reg
URL : https://patchwork.freedesktop.org/series/117138/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
stty: 'standard input': Inappropriate ioctl for device
[06:27:40] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:27:44] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[06:28:06] Starting KUnit Kernel (1/1)...
[06:28:06] ============================================================
[06:28:06] ==================== xe_bo (2 subtests) ====================
[06:28:06] [SKIPPED] xe_ccs_migrate_kunit
[06:28:06] [SKIPPED] xe_bo_evict_kunit
[06:28:06] ===================== [SKIPPED] xe_bo ======================
[06:28:06] ================== xe_dma_buf (1 subtest) ==================
[06:28:06] [SKIPPED] xe_dma_buf_kunit
[06:28:06] =================== [SKIPPED] xe_dma_buf ===================
[06:28:06] ================== xe_migrate (1 subtest) ==================
[06:28:06] [SKIPPED] xe_migrate_sanity_kunit
[06:28:06] =================== [SKIPPED] xe_migrate ===================
[06:28:06] =================== xe_pci (2 subtests) ====================
[06:28:06] [PASSED] xe_gmdid_graphics_ip
[06:28:06] [PASSED] xe_gmdid_media_ip
[06:28:06] ===================== [PASSED] xe_pci ======================
[06:28:06] ==================== xe_rtp (1 subtest) ====================
[06:28:06] ================== xe_rtp_process_tests ===================
[06:28:06] [PASSED] coalesce-same-reg
[06:28:06] [PASSED] no-match-no-add
[06:28:06] [PASSED] no-match-no-add-multiple-rules
[06:28:06] [PASSED] two-regs-two-entries
[06:28:06] [PASSED] clr-one-set-other
[06:28:06] [PASSED] set-field
[06:28:06] [PASSED] conflict-duplicate
[06:28:06] [PASSED] conflict-not-disjoint
[06:28:06] [PASSED] conflict-reg-type
[06:28:06] ============== [PASSED] xe_rtp_process_tests ===============
[06:28:06] ===================== [PASSED] xe_rtp ======================
[06:28:06] ==================== xe_wa (1 subtest) =====================
[06:28:06] ======================== xe_wa_gt =========================
[06:28:06] [PASSED] TIGERLAKE (B0)
[06:28:06] [PASSED] DG1 (A0)
[06:28:06] [PASSED] DG1 (B0)
[06:28:06] [PASSED] ALDERLAKE_S (A0)
[06:28:06] [PASSED] ALDERLAKE_S (B0)
[06:28:06] [PASSED] ALDERLAKE_S (C0)
[06:28:06] [PASSED] ALDERLAKE_S (D0)
[06:28:06] [PASSED] DG2_G10 (A0)
[06:28:06] [PASSED] DG2_G10 (A1)
[06:28:06] [PASSED] DG2_G10 (B0)
[06:28:06] [PASSED] DG2_G10 (C0)
[06:28:06] [PASSED] DG2_G11 (A0)
[06:28:06] [PASSED] DG2_G11 (B0)
[06:28:06] [PASSED] DG2_G11 (B1)
[06:28:06] [PASSED] DG2_G12 (A0)
[06:28:06] [PASSED] DG2_G12 (A1)
[06:28:06] [PASSED] PVC (B0)
[06:28:06] [PASSED] PVC (B1)
[06:28:06] [PASSED] PVC (C0)
[06:28:06] ==================== [PASSED] xe_wa_gt =====================
[06:28:06] ====================== [PASSED] xe_wa ======================
[06:28:06] ============================================================
[06:28:06] Testing complete. Ran 34 tests: passed: 30, skipped: 4
[06:28:06] Elapsed time: 26.142s total, 4.223s configuring, 21.800s building, 0.097s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:28:06] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:28:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[06:28:27] Starting KUnit Kernel (1/1)...
[06:28:27] ============================================================
[06:28:27] ============ drm_test_pick_cmdline (2 subtests) ============
[06:28:27] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:28:27] =============== drm_test_pick_cmdline_named ===============
[06:28:27] [PASSED] NTSC
[06:28:27] [PASSED] NTSC-J
[06:28:27] [PASSED] PAL
[06:28:27] [PASSED] PAL-M
[06:28:27] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:28:27] ============== [PASSED] drm_test_pick_cmdline ==============
[06:28:27] ================== drm_buddy (6 subtests) ==================
[06:28:27] [PASSED] drm_test_buddy_alloc_limit
[06:28:27] [PASSED] drm_test_buddy_alloc_range
[06:28:27] [PASSED] drm_test_buddy_alloc_optimistic
[06:28:27] [PASSED] drm_test_buddy_alloc_pessimistic
[06:28:27] [PASSED] drm_test_buddy_alloc_smoke
[06:28:27] [PASSED] drm_test_buddy_alloc_pathological
[06:28:27] ==================== [PASSED] drm_buddy ====================
[06:28:27] ============= drm_cmdline_parser (40 subtests) =============
[06:28:27] [PASSED] drm_test_cmdline_force_d_only
[06:28:27] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:28:27] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:28:27] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:28:27] [PASSED] drm_test_cmdline_force_e_only
[06:28:27] [PASSED] drm_test_cmdline_res
[06:28:27] [PASSED] drm_test_cmdline_res_vesa
[06:28:27] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:28:27] [PASSED] drm_test_cmdline_res_rblank
[06:28:27] [PASSED] drm_test_cmdline_res_bpp
[06:28:27] [PASSED] drm_test_cmdline_res_refresh
[06:28:27] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:28:27] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:28:27] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:28:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:28:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:28:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:28:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:28:27] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:28:27] [PASSED] drm_test_cmdline_res_margins_force_on
[06:28:27] [PASSED] drm_test_cmdline_res_vesa_margins
[06:28:27] [PASSED] drm_test_cmdline_name
[06:28:27] [PASSED] drm_test_cmdline_name_bpp
[06:28:27] [PASSED] drm_test_cmdline_name_option
[06:28:27] [PASSED] drm_test_cmdline_name_bpp_option
[06:28:27] [PASSED] drm_test_cmdline_rotate_0
[06:28:27] [PASSED] drm_test_cmdline_rotate_90
[06:28:27] [PASSED] drm_test_cmdline_rotate_180
[06:28:27] [PASSED] drm_test_cmdline_rotate_270
[06:28:27] [PASSED] drm_test_cmdline_hmirror
[06:28:27] [PASSED] drm_test_cmdline_vmirror
[06:28:27] [PASSED] drm_test_cmdline_margin_options
[06:28:27] [PASSED] drm_test_cmdline_multiple_options
[06:28:27] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:28:27] [PASSED] drm_test_cmdline_extra_and_option
[06:28:27] [PASSED] drm_test_cmdline_freestanding_options
[06:28:27] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:28:27] [PASSED] drm_test_cmdline_panel_orientation
[06:28:27] ================ drm_test_cmdline_invalid =================
[06:28:27] [PASSED] margin_only
[06:28:27] [PASSED] interlace_only
[06:28:27] [PASSED] res_missing_x
[06:28:27] [PASSED] res_missing_y
[06:28:27] [PASSED] res_bad_y
[06:28:27] [PASSED] res_missing_y_bpp
[06:28:27] [PASSED] res_bad_bpp
[06:28:27] [PASSED] res_bad_refresh
[06:28:27] [PASSED] res_bpp_refresh_force_on_off
[06:28:27] [PASSED] res_invalid_mode
[06:28:27] [PASSED] res_bpp_wrong_place_mode
[06:28:27] [PASSED] name_bpp_refresh
[06:28:27] [PASSED] name_refresh
[06:28:27] [PASSED] name_refresh_wrong_mode
[06:28:27] [PASSED] name_refresh_invalid_mode
[06:28:27] [PASSED] rotate_multiple
[06:28:27] [PASSED] rotate_invalid_val
[06:28:27] [PASSED] rotate_truncated
[06:28:27] [PASSED] invalid_option
[06:28:27] [PASSED] invalid_tv_option
[06:28:27] [PASSED] truncated_tv_option
[06:28:27] ============ [PASSED] drm_test_cmdline_invalid =============
[06:28:27] =============== drm_test_cmdline_tv_options ===============
[06:28:27] [PASSED] NTSC
[06:28:27] [PASSED] NTSC_443
[06:28:27] [PASSED] NTSC_J
[06:28:27] [PASSED] PAL
[06:28:27] [PASSED] PAL_M
[06:28:27] [PASSED] PAL_N
[06:28:27] [PASSED] SECAM
[06:28:27] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:28:27] =============== [PASSED] drm_cmdline_parser ================
[06:28:27] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:28:27] ========== drm_test_get_tv_mode_from_name_valid ===========
[06:28:27] [PASSED] NTSC
[06:28:27] [PASSED] NTSC-443
[06:28:27] [PASSED] NTSC-J
[06:28:27] [PASSED] PAL
[06:28:27] [PASSED] PAL-M
[06:28:27] [PASSED] PAL-N
[06:28:27] [PASSED] SECAM
[06:28:27] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:28:27] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:28:27] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:28:27] ============= drm_damage_helper (21 subtests) ==============
[06:28:27] [PASSED] drm_test_damage_iter_no_damage
[06:28:27] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:28:27] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:28:27] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:28:27] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:28:27] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:28:27] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:28:27] [PASSED] drm_test_damage_iter_simple_damage
[06:28:27] [PASSED] drm_test_damage_iter_single_damage
[06:28:27] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:28:27] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:28:27] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:28:27] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:28:27] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:28:27] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:28:27] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:28:27] [PASSED] drm_test_damage_iter_damage
[06:28:27] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:28:27] [PASSED] drm_test_damage_iter_damage_one_outside
[06:28:27] [PASSED] drm_test_damage_iter_damage_src_moved
[06:28:27] [PASSED] drm_test_damage_iter_damage_not_visible
[06:28:27] ================ [PASSED] drm_damage_helper ================
[06:28:27] ============== drm_dp_mst_helper (2 subtests) ==============
[06:28:27] ============== drm_test_dp_mst_calc_pbn_mode ==============
[06:28:27] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:28:27] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:28:27] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:28:27] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:28:27] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:28:27] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:28:27] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[06:28:27] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:28:27] [PASSED] DP_POWER_UP_PHY with port number
[06:28:27] [PASSED] DP_POWER_DOWN_PHY with port number
[06:28:27] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:28:27] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:28:27] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:28:27] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:28:27] [PASSED] DP_QUERY_PAYLOAD with port number
[06:28:27] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:28:27] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:28:27] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:28:27] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:28:27] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:28:27] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:28:27] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:28:27] [PASSED] DP_REMOTE_I2C_READ with port number
[06:28:27] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:28:27] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:28:27] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:28:27] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:28:27] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:28:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:28:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:28:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:28:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:28:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:28:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:28:27] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:28:27] ================ [PASSED] drm_dp_mst_helper ================
[06:28:27] =========== drm_format_helper_test (11 subtests) ===========
[06:28:27] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:28:27] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:28:27] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:28:27] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:28:27] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:28:27] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:28:27] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:28:27] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:28:27] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:28:27] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:28:27] ============== drm_test_fb_xrgb8888_to_mono ===============
[06:28:27] [PASSED] single_pixel_source_buffer
[06:28:27] [PASSED] single_pixel_clip_rectangle
[06:28:27] [PASSED] well_known_colors
[06:28:27] [PASSED] destination_pitch
[06:28:27] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:28:27] ============= [PASSED] drm_format_helper_test ==============
[06:28:27] ================= drm_format (18 subtests) =================
[06:28:27] [PASSED] drm_test_format_block_width_invalid
[06:28:27] [PASSED] drm_test_format_block_width_one_plane
[06:28:27] [PASSED] drm_test_format_block_width_two_plane
[06:28:27] [PASSED] drm_test_format_block_width_three_plane
[06:28:27] [PASSED] drm_test_format_block_width_tiled
[06:28:27] [PASSED] drm_test_format_block_height_invalid
[06:28:27] [PASSED] drm_test_format_block_height_one_plane
[06:28:27] [PASSED] drm_test_format_block_height_two_plane
[06:28:27] [PASSED] drm_test_format_block_height_three_plane
[06:28:27] [PASSED] drm_test_format_block_height_tiled
[06:28:27] [PASSED] drm_test_format_min_pitch_invalid
[06:28:27] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:28:27] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:28:27] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:28:27] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:28:27] [PASSED] drm_test_format_min_pitch_two_plane
[06:28:27] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:28:27] [PASSED] drm_test_format_min_pitch_tiled
[06:28:27] =================== [PASSED] drm_format ====================
[06:28:27] =============== drm_framebuffer (1 subtest) ================
[06:28:27] =============== drm_test_framebuffer_create ===============
[06:28:27] [PASSED] ABGR8888 normal sizes
[06:28:27] [PASSED] ABGR8888 max sizes
[06:28:27] [PASSED] ABGR8888 pitch greater than min required
[06:28:27] [PASSED] ABGR8888 pitch less than min required
[06:28:27] [PASSED] ABGR8888 Invalid width
[06:28:27] [PASSED] ABGR8888 Invalid buffer handle
[06:28:27] [PASSED] No pixel format
[06:28:27] [PASSED] ABGR8888 Width 0
[06:28:27] [PASSED] ABGR8888 Height 0
[06:28:27] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:28:27] [PASSED] ABGR8888 Large buffer offset
[06:28:27] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:28:27] [PASSED] ABGR8888 Valid buffer modifier
[06:28:27] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:28:27] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:28:27] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:28:27] [PASSED] NV12 Normal sizes
[06:28:27] [PASSED] NV12 Max sizes
[06:28:27] [PASSED] NV12 Invalid pitch
[06:28:27] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:28:27] [PASSED] NV12 different modifier per-plane
[06:28:27] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:28:27] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:28:27] [PASSED] NV12 Modifier for inexistent plane
[06:28:27] [PASSED] NV12 Handle for inexistent plane
[06:28:27] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:28:27] [PASSED] YVU420 Normal sizes
[06:28:27] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:28:27] [PASSED] YVU420 Max sizes
[06:28:27] [PASSED] YVU420 Invalid pitch
[06:28:27] [PASSED] YVU420 Different pitches
[06:28:27] [PASSED] YVU420 Different buffer offsets/pitches
[06:28:27] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:28:27] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:28:27] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:28:27] [PASSED] YVU420 Valid modifier
[06:28:27] [PASSED] YVU420 Different modifiers per plane
[06:28:27] [PASSED] YVU420 Modifier for inexistent plane
[06:28:27] [PASSED] X0L2 Normal sizes
[06:28:27] [PASSED] X0L2 Max sizes
[06:28:27] [PASSED] X0L2 Invalid pitch
[06:28:27] [PASSED] X0L2 Pitch greater than minimum required
stty: 'standard input': Inappropriate ioctl for device
[06:28:27] [PASSED] X0L2 Handle for inexistent plane
[06:28:27] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:28:27] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:28:27] [PASSED] X0L2 Valid modifier
[06:28:27] [PASSED] X0L2 Modifier for inexistent plane
[06:28:27] =========== [PASSED] drm_test_framebuffer_create ===========
[06:28:27] ================= [PASSED] drm_framebuffer =================
[06:28:27] =============== drm-test-managed (1 subtest) ===============
[06:28:27] [PASSED] drm_test_managed_run_action
[06:28:27] ================ [PASSED] drm-test-managed =================
[06:28:27] =================== drm_mm (19 subtests) ===================
[06:28:27] [PASSED] drm_test_mm_init
[06:28:27] [PASSED] drm_test_mm_debug
[06:28:37] [PASSED] drm_test_mm_reserve
[06:28:47] [PASSED] drm_test_mm_insert
[06:28:48] [PASSED] drm_test_mm_replace
[06:28:48] [PASSED] drm_test_mm_insert_range
[06:28:48] [PASSED] drm_test_mm_frag
[06:28:48] [PASSED] drm_test_mm_align
[06:28:48] [PASSED] drm_test_mm_align32
[06:28:48] [PASSED] drm_test_mm_align64
[06:28:49] [PASSED] drm_test_mm_evict
[06:28:49] [PASSED] drm_test_mm_evict_range
[06:28:49] [PASSED] drm_test_mm_topdown
[06:28:49] [PASSED] drm_test_mm_bottomup
[06:28:49] [PASSED] drm_test_mm_lowest
[06:28:49] [PASSED] drm_test_mm_highest
[06:28:49] [PASSED] drm_test_mm_color
[06:28:50] [PASSED] drm_test_mm_color_evict
[06:28:50] [PASSED] drm_test_mm_color_evict_range
[06:28:50] ===================== [PASSED] drm_mm ======================
[06:28:50] ============= drm_modes_analog_tv (4 subtests) =============
[06:28:50] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:28:50] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:28:50] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:28:50] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:28:50] =============== [PASSED] drm_modes_analog_tv ===============
[06:28:50] ============== drm_plane_helper (2 subtests) ===============
[06:28:50] =============== drm_test_check_plane_state ================
[06:28:50] [PASSED] clipping_simple
[06:28:50] [PASSED] clipping_rotate_reflect
[06:28:50] [PASSED] positioning_simple
[06:28:50] [PASSED] upscaling
[06:28:50] [PASSED] downscaling
[06:28:50] [PASSED] rounding1
[06:28:50] [PASSED] rounding2
[06:28:50] [PASSED] rounding3
[06:28:50] [PASSED] rounding4
[06:28:50] =========== [PASSED] drm_test_check_plane_state ============
[06:28:50] =========== drm_test_check_invalid_plane_state ============
[06:28:50] [PASSED] positioning_invalid
[06:28:50] [PASSED] upscaling_invalid
[06:28:50] [PASSED] downscaling_invalid
[06:28:50] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:28:50] ================ [PASSED] drm_plane_helper =================
[06:28:50] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:28:50] ====== drm_test_connector_helper_tv_get_modes_check =======
[06:28:50] [PASSED] None
[06:28:50] [PASSED] PAL
[06:28:50] [PASSED] NTSC
[06:28:50] [PASSED] Both, NTSC Default
[06:28:50] [PASSED] Both, PAL Default
[06:28:50] [PASSED] Both, NTSC Default, with PAL on command-line
[06:28:50] [PASSED] Both, PAL Default, with NTSC on command-line
[06:28:50] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:28:50] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:28:50] ================== drm_rect (4 subtests) ===================
[06:28:50] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:28:50] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:28:50] [PASSED] drm_test_rect_clip_scaled_clipped
[06:28:50] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:28:50] ==================== [PASSED] drm_rect =====================
[06:28:50] ============================================================
[06:28:50] Testing complete. Ran 294 tests: passed: 294
[06:28:50] Elapsed time: 43.572s total, 1.701s configuring, 18.691s building, 23.145s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-xe] ✓ CI.Build: success for Convert xe_mmio to struct xe_reg
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
` (8 preceding siblings ...)
2023-04-29 6:28 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
@ 2023-04-29 6:32 ` Patchwork
2023-04-29 6:58 ` [Intel-xe] ○ CI.BAT: info " Patchwork
10 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-04-29 6:32 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
== Series Details ==
Series: Convert xe_mmio to struct xe_reg
URL : https://patchwork.freedesktop.org/series/117138/
State : success
== Summary ==
+ trap cleanup EXIT
+ cd /kernel
+ git clone https://gitlab.freedesktop.org/drm/xe/ci.git .ci
Cloning into '.ci'...
++ date +%s
+ echo -e '\e[0Ksection_start:1682749739:build_x86_64[collapsed=true]\r\e[0KBuild x86-64'
+ mkdir -p build64
^[[0Ksection_start:1682749739:build_x86_64[collapsed=true]
^[[0KBuild x86-64
+ cat .ci/kernel/kconfig
+ make O=build64 olddefconfig
make[1]: Entering directory '/kernel/build64'
GEN Makefile
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
HOSTCC scripts/kconfig/confdata.o
HOSTCC scripts/kconfig/expr.o
LEX scripts/kconfig/lexer.lex.c
YACC scripts/kconfig/parser.tab.[ch]
HOSTCC scripts/kconfig/lexer.lex.o
HOSTCC scripts/kconfig/menu.o
HOSTCC scripts/kconfig/parser.tab.o
HOSTCC scripts/kconfig/preprocess.o
HOSTCC scripts/kconfig/symbol.o
HOSTCC scripts/kconfig/util.o
HOSTLD scripts/kconfig/conf
#
# configuration written to .config
#
make[1]: Leaving directory '/kernel/build64'
++ nproc
+ make O=build64 -j48
make[1]: Entering directory '/kernel/build64'
GEN Makefile
WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h
WRAP arch/x86/include/generated/uapi/asm/errno.h
WRAP arch/x86/include/generated/uapi/asm/fcntl.h
WRAP arch/x86/include/generated/uapi/asm/ioctl.h
WRAP arch/x86/include/generated/uapi/asm/ioctls.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h
WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h
WRAP arch/x86/include/generated/uapi/asm/param.h
WRAP arch/x86/include/generated/uapi/asm/resource.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h
WRAP arch/x86/include/generated/uapi/asm/poll.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h
SYSHDR arch/x86/include/generated/asm/unistd_32_ia32.h
SYSTBL arch/x86/include/generated/asm/syscalls_32.h
WRAP arch/x86/include/generated/uapi/asm/socket.h
WRAP arch/x86/include/generated/uapi/asm/sockios.h
SYSHDR arch/x86/include/generated/asm/unistd_64_x32.h
SYSTBL arch/x86/include/generated/asm/syscalls_64.h
WRAP arch/x86/include/generated/uapi/asm/termbits.h
WRAP arch/x86/include/generated/uapi/asm/termios.h
WRAP arch/x86/include/generated/uapi/asm/types.h
UPD include/generated/uapi/linux/version.h
UPD include/config/kernel.release
WRAP arch/x86/include/generated/asm/export.h
WRAP arch/x86/include/generated/asm/early_ioremap.h
WRAP arch/x86/include/generated/asm/mcs_spinlock.h
HOSTCC arch/x86/tools/relocs_32.o
WRAP arch/x86/include/generated/asm/kmap_size.h
WRAP arch/x86/include/generated/asm/irq_regs.h
HOSTCC arch/x86/tools/relocs_64.o
WRAP arch/x86/include/generated/asm/local64.h
HOSTCC arch/x86/tools/relocs_common.o
WRAP arch/x86/include/generated/asm/module.lds.h
WRAP arch/x86/include/generated/asm/mmiowb.h
UPD include/generated/compile.h
WRAP arch/x86/include/generated/asm/rwonce.h
WRAP arch/x86/include/generated/asm/unaligned.h
HOSTCC scripts/unifdef
UPD include/generated/utsrelease.h
HOSTCC scripts/kallsyms
HOSTCC scripts/sorttable
HOSTCC scripts/asn1_compiler
DESCEND objtool
HOSTCC /kernel/build64/tools/objtool/fixdep.o
HOSTLD /kernel/build64/tools/objtool/fixdep-in.o
LINK /kernel/build64/tools/objtool/fixdep
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/exec-cmd.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/help.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/pager.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/parse-options.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/run-command.h
CC /kernel/build64/tools/objtool/libsubcmd/exec-cmd.o
CC /kernel/build64/tools/objtool/libsubcmd/help.o
CC /kernel/build64/tools/objtool/libsubcmd/pager.o
CC /kernel/build64/tools/objtool/libsubcmd/parse-options.o
INSTALL libsubcmd_headers
CC /kernel/build64/tools/objtool/libsubcmd/run-command.o
CC /kernel/build64/tools/objtool/libsubcmd/sigchain.o
CC /kernel/build64/tools/objtool/libsubcmd/subcmd-config.o
HOSTLD arch/x86/tools/relocs
CC scripts/mod/empty.o
HOSTCC scripts/mod/mk_elfconfig
CC scripts/mod/devicetable-offsets.s
HDRINST usr/include/video/edid.h
HDRINST usr/include/video/sisfb.h
HDRINST usr/include/video/uvesafb.h
HDRINST usr/include/drm/i915_drm.h
HDRINST usr/include/drm/amdgpu_drm.h
HDRINST usr/include/drm/virtgpu_drm.h
HDRINST usr/include/drm/vgem_drm.h
HDRINST usr/include/drm/xe_drm.h
HDRINST usr/include/drm/omap_drm.h
HDRINST usr/include/drm/radeon_drm.h
HDRINST usr/include/drm/tegra_drm.h
HDRINST usr/include/drm/drm_mode.h
HDRINST usr/include/drm/ivpu_accel.h
HDRINST usr/include/drm/exynos_drm.h
HDRINST usr/include/drm/v3d_drm.h
HDRINST usr/include/drm/drm_sarea.h
HDRINST usr/include/drm/drm_fourcc.h
HDRINST usr/include/drm/nouveau_drm.h
HDRINST usr/include/drm/qxl_drm.h
HDRINST usr/include/drm/habanalabs_accel.h
HDRINST usr/include/drm/vmwgfx_drm.h
HDRINST usr/include/drm/msm_drm.h
HDRINST usr/include/drm/etnaviv_drm.h
HDRINST usr/include/drm/vc4_drm.h
HDRINST usr/include/drm/panfrost_drm.h
HDRINST usr/include/drm/drm.h
HDRINST usr/include/drm/lima_drm.h
HDRINST usr/include/drm/armada_drm.h
HDRINST usr/include/mtd/inftl-user.h
HDRINST usr/include/mtd/nftl-user.h
HDRINST usr/include/mtd/ubi-user.h
HDRINST usr/include/mtd/mtd-user.h
HDRINST usr/include/mtd/mtd-abi.h
HDRINST usr/include/xen/gntdev.h
HDRINST usr/include/xen/evtchn.h
HDRINST usr/include/xen/gntalloc.h
HDRINST usr/include/xen/privcmd.h
HDRINST usr/include/asm-generic/auxvec.h
HDRINST usr/include/asm-generic/posix_types.h
HDRINST usr/include/asm-generic/bitsperlong.h
HDRINST usr/include/asm-generic/ioctls.h
HDRINST usr/include/asm-generic/mman.h
HDRINST usr/include/asm-generic/shmbuf.h
HDRINST usr/include/asm-generic/bpf_perf_event.h
HDRINST usr/include/asm-generic/types.h
HDRINST usr/include/asm-generic/poll.h
HDRINST usr/include/asm-generic/msgbuf.h
HDRINST usr/include/asm-generic/swab.h
HDRINST usr/include/asm-generic/statfs.h
HDRINST usr/include/asm-generic/unistd.h
HDRINST usr/include/asm-generic/hugetlb_encode.h
HDRINST usr/include/asm-generic/resource.h
HDRINST usr/include/asm-generic/param.h
HDRINST usr/include/asm-generic/termbits-common.h
HDRINST usr/include/asm-generic/sockios.h
HDRINST usr/include/asm-generic/kvm_para.h
HDRINST usr/include/asm-generic/errno.h
HDRINST usr/include/asm-generic/termios.h
HDRINST usr/include/asm-generic/mman-common.h
HDRINST usr/include/asm-generic/ioctl.h
HDRINST usr/include/asm-generic/socket.h
HDRINST usr/include/asm-generic/signal-defs.h
HDRINST usr/include/asm-generic/termbits.h
HDRINST usr/include/asm-generic/int-ll64.h
HDRINST usr/include/asm-generic/signal.h
HDRINST usr/include/asm-generic/siginfo.h
HDRINST usr/include/asm-generic/stat.h
HDRINST usr/include/asm-generic/int-l64.h
HDRINST usr/include/asm-generic/errno-base.h
HDRINST usr/include/asm-generic/fcntl.h
HDRINST usr/include/asm-generic/setup.h
HDRINST usr/include/asm-generic/ipcbuf.h
HDRINST usr/include/asm-generic/sembuf.h
HDRINST usr/include/asm-generic/ucontext.h
HDRINST usr/include/rdma/mlx5_user_ioctl_cmds.h
UPD scripts/mod/devicetable-offsets.h
HDRINST usr/include/rdma/irdma-abi.h
HDRINST usr/include/rdma/mana-abi.h
HDRINST usr/include/rdma/hfi/hfi1_user.h
HDRINST usr/include/rdma/hfi/hfi1_ioctl.h
HDRINST usr/include/rdma/rdma_user_rxe.h
HDRINST usr/include/rdma/rdma_user_ioctl.h
HDRINST usr/include/rdma/mlx5_user_ioctl_verbs.h
HDRINST usr/include/rdma/bnxt_re-abi.h
HDRINST usr/include/rdma/hns-abi.h
HDRINST usr/include/rdma/qedr-abi.h
HDRINST usr/include/rdma/ib_user_ioctl_cmds.h
HDRINST usr/include/rdma/vmw_pvrdma-abi.h
HDRINST usr/include/rdma/ib_user_sa.h
HDRINST usr/include/rdma/ib_user_ioctl_verbs.h
HDRINST usr/include/rdma/rvt-abi.h
HDRINST usr/include/rdma/mlx5-abi.h
HDRINST usr/include/rdma/rdma_netlink.h
HDRINST usr/include/rdma/erdma-abi.h
HDRINST usr/include/rdma/rdma_user_ioctl_cmds.h
HDRINST usr/include/rdma/rdma_user_cm.h
HDRINST usr/include/rdma/ib_user_verbs.h
HDRINST usr/include/rdma/efa-abi.h
HDRINST usr/include/rdma/siw-abi.h
HDRINST usr/include/rdma/mlx4-abi.h
HDRINST usr/include/rdma/mthca-abi.h
HDRINST usr/include/rdma/ib_user_mad.h
HDRINST usr/include/rdma/ocrdma-abi.h
HDRINST usr/include/rdma/cxgb4-abi.h
HDRINST usr/include/misc/xilinx_sdfec.h
HDRINST usr/include/misc/uacce/hisi_qm.h
HDRINST usr/include/misc/uacce/uacce.h
HDRINST usr/include/misc/cxl.h
HDRINST usr/include/misc/ocxl.h
HDRINST usr/include/misc/fastrpc.h
HDRINST usr/include/misc/pvpanic.h
HDRINST usr/include/linux/i8k.h
HDRINST usr/include/linux/acct.h
HDRINST usr/include/linux/atmmpc.h
HDRINST usr/include/linux/fs.h
HDRINST usr/include/linux/cifs/cifs_mount.h
HDRINST usr/include/linux/cifs/cifs_netlink.h
HDRINST usr/include/linux/if_packet.h
HDRINST usr/include/linux/route.h
HDRINST usr/include/linux/patchkey.h
HDRINST usr/include/linux/tc_ematch/tc_em_cmp.h
HDRINST usr/include/linux/tc_ematch/tc_em_ipt.h
HDRINST usr/include/linux/tc_ematch/tc_em_meta.h
HDRINST usr/include/linux/tc_ematch/tc_em_text.h
HDRINST usr/include/linux/tc_ematch/tc_em_nbyte.h
HDRINST usr/include/linux/virtio_pmem.h
HDRINST usr/include/linux/rkisp1-config.h
HDRINST usr/include/linux/vhost.h
HDRINST usr/include/linux/cec-funcs.h
HDRINST usr/include/linux/ppdev.h
HDRINST usr/include/linux/isdn/capicmd.h
HDRINST usr/include/linux/virtio_fs.h
HDRINST usr/include/linux/netfilter_ipv6.h
HDRINST usr/include/linux/lirc.h
HDRINST usr/include/linux/mroute6.h
MKELF scripts/mod/elfconfig.h
HDRINST usr/include/linux/nl80211-vnd-intel.h
HDRINST usr/include/linux/ivtvfb.h
HDRINST usr/include/linux/auxvec.h
HDRINST usr/include/linux/dm-log-userspace.h
HOSTCC scripts/mod/modpost.o
HDRINST usr/include/linux/dccp.h
HOSTCC scripts/mod/file2alias.o
HDRINST usr/include/linux/virtio_scmi.h
HOSTCC scripts/mod/sumversion.o
HDRINST usr/include/linux/atmarp.h
HDRINST usr/include/linux/arcfb.h
HDRINST usr/include/linux/nbd-netlink.h
HDRINST usr/include/linux/sched/types.h
HDRINST usr/include/linux/tcp.h
HDRINST usr/include/linux/neighbour.h
HDRINST usr/include/linux/dlm_device.h
HDRINST usr/include/linux/wmi.h
HDRINST usr/include/linux/btrfs_tree.h
HDRINST usr/include/linux/virtio_crypto.h
HDRINST usr/include/linux/vbox_err.h
HDRINST usr/include/linux/edd.h
HDRINST usr/include/linux/loop.h
HDRINST usr/include/linux/nvme_ioctl.h
HDRINST usr/include/linux/mmtimer.h
HDRINST usr/include/linux/if_pppol2tp.h
HDRINST usr/include/linux/mtio.h
HDRINST usr/include/linux/if_arcnet.h
HDRINST usr/include/linux/romfs_fs.h
HDRINST usr/include/linux/posix_types.h
HDRINST usr/include/linux/rtc.h
HDRINST usr/include/linux/landlock.h
HDRINST usr/include/linux/gpio.h
HDRINST usr/include/linux/selinux_netlink.h
HDRINST usr/include/linux/pps.h
HDRINST usr/include/linux/ndctl.h
HDRINST usr/include/linux/virtio_gpu.h
HDRINST usr/include/linux/android/binderfs.h
HDRINST usr/include/linux/android/binder.h
HDRINST usr/include/linux/virtio_vsock.h
HDRINST usr/include/linux/sound.h
HDRINST usr/include/linux/vtpm_proxy.h
HDRINST usr/include/linux/nfs_fs.h
HDRINST usr/include/linux/elf-fdpic.h
HDRINST usr/include/linux/adfs_fs.h
HDRINST usr/include/linux/target_core_user.h
HDRINST usr/include/linux/netlink_diag.h
HDRINST usr/include/linux/const.h
HDRINST usr/include/linux/firewire-cdev.h
HDRINST usr/include/linux/vdpa.h
HDRINST usr/include/linux/if_infiniband.h
HDRINST usr/include/linux/serial.h
HDRINST usr/include/linux/iio/types.h
HDRINST usr/include/linux/iio/buffer.h
HDRINST usr/include/linux/iio/events.h
HDRINST usr/include/linux/baycom.h
HDRINST usr/include/linux/major.h
HDRINST usr/include/linux/atmppp.h
HDRINST usr/include/linux/ipv6_route.h
HDRINST usr/include/linux/spi/spidev.h
HDRINST usr/include/linux/spi/spi.h
HDRINST usr/include/linux/virtio_ring.h
HDRINST usr/include/linux/hdlc/ioctl.h
HDRINST usr/include/linux/remoteproc_cdev.h
HDRINST usr/include/linux/hyperv.h
HDRINST usr/include/linux/rpl_iptunnel.h
HDRINST usr/include/linux/sync_file.h
HDRINST usr/include/linux/igmp.h
HDRINST usr/include/linux/v4l2-dv-timings.h
HDRINST usr/include/linux/virtio_i2c.h
HDRINST usr/include/linux/xfrm.h
HDRINST usr/include/linux/capability.h
HDRINST usr/include/linux/gtp.h
HDRINST usr/include/linux/xdp_diag.h
HDRINST usr/include/linux/pkt_cls.h
HDRINST usr/include/linux/suspend_ioctls.h
HDRINST usr/include/linux/vt.h
HDRINST usr/include/linux/loadpin.h
HDRINST usr/include/linux/dlm_plock.h
HDRINST usr/include/linux/fb.h
HDRINST usr/include/linux/max2175.h
HDRINST usr/include/linux/sunrpc/debug.h
HDRINST usr/include/linux/gsmmux.h
HDRINST usr/include/linux/watchdog.h
HDRINST usr/include/linux/vhost_types.h
HDRINST usr/include/linux/vduse.h
HDRINST usr/include/linux/ila.h
HDRINST usr/include/linux/tdx-guest.h
HDRINST usr/include/linux/close_range.h
HDRINST usr/include/linux/ivtv.h
HDRINST usr/include/linux/cryptouser.h
HDRINST usr/include/linux/netfilter/xt_string.h
HDRINST usr/include/linux/netfilter/nfnetlink_compat.h
HDRINST usr/include/linux/netfilter/nf_nat.h
HDRINST usr/include/linux/netfilter/xt_recent.h
HDRINST usr/include/linux/netfilter/xt_addrtype.h
HDRINST usr/include/linux/netfilter/nf_conntrack_tcp.h
HDRINST usr/include/linux/netfilter/xt_MARK.h
HDRINST usr/include/linux/netfilter/xt_SYNPROXY.h
HDRINST usr/include/linux/netfilter/xt_multiport.h
HDRINST usr/include/linux/netfilter/nfnetlink.h
HDRINST usr/include/linux/netfilter/xt_cgroup.h
HDRINST usr/include/linux/netfilter/nf_synproxy.h
HDRINST usr/include/linux/netfilter/nfnetlink_log.h
HDRINST usr/include/linux/netfilter/xt_TCPOPTSTRIP.h
HDRINST usr/include/linux/netfilter/xt_TPROXY.h
HDRINST usr/include/linux/netfilter/xt_u32.h
HDRINST usr/include/linux/netfilter/nfnetlink_osf.h
HDRINST usr/include/linux/netfilter/xt_ecn.h
HDRINST usr/include/linux/netfilter/xt_esp.h
HDRINST usr/include/linux/netfilter/nfnetlink_hook.h
HDRINST usr/include/linux/netfilter/xt_mac.h
HDRINST usr/include/linux/netfilter/xt_comment.h
HDRINST usr/include/linux/netfilter/xt_NFQUEUE.h
HDRINST usr/include/linux/netfilter/xt_osf.h
HDRINST usr/include/linux/netfilter/xt_hashlimit.h
HDRINST usr/include/linux/netfilter/nf_conntrack_sctp.h
HDRINST usr/include/linux/netfilter/xt_socket.h
HDRINST usr/include/linux/netfilter/xt_connmark.h
HDRINST usr/include/linux/netfilter/xt_sctp.h
HDRINST usr/include/linux/netfilter/xt_tcpudp.h
HDRINST usr/include/linux/netfilter/xt_DSCP.h
HDRINST usr/include/linux/netfilter/xt_time.h
HDRINST usr/include/linux/netfilter/xt_IDLETIMER.h
HDRINST usr/include/linux/netfilter/xt_policy.h
HDRINST usr/include/linux/netfilter/xt_rpfilter.h
HDRINST usr/include/linux/netfilter/xt_nfacct.h
HDRINST usr/include/linux/netfilter/xt_SECMARK.h
HDRINST usr/include/linux/netfilter/xt_length.h
HDRINST usr/include/linux/netfilter/nfnetlink_cthelper.h
HDRINST usr/include/linux/netfilter/xt_quota.h
HDRINST usr/include/linux/netfilter/xt_CLASSIFY.h
HDRINST usr/include/linux/netfilter/xt_ipcomp.h
HDRINST usr/include/linux/netfilter/xt_iprange.h
HDRINST usr/include/linux/netfilter/xt_bpf.h
HDRINST usr/include/linux/netfilter/xt_LOG.h
HDRINST usr/include/linux/netfilter/xt_rateest.h
HDRINST usr/include/linux/netfilter/xt_CONNSECMARK.h
HDRINST usr/include/linux/netfilter/xt_HMARK.h
HDRINST usr/include/linux/netfilter/xt_CONNMARK.h
HDRINST usr/include/linux/netfilter/xt_ipvs.h
HDRINST usr/include/linux/netfilter/xt_pkttype.h
HDRINST usr/include/linux/netfilter/xt_devgroup.h
HDRINST usr/include/linux/netfilter/xt_AUDIT.h
HDRINST usr/include/linux/netfilter/xt_realm.h
HDRINST usr/include/linux/netfilter/nf_conntrack_common.h
HDRINST usr/include/linux/netfilter/xt_set.h
HDRINST usr/include/linux/netfilter/xt_LED.h
HDRINST usr/include/linux/netfilter/xt_connlabel.h
HDRINST usr/include/linux/netfilter/xt_owner.h
HDRINST usr/include/linux/netfilter/xt_dccp.h
HDRINST usr/include/linux/netfilter/xt_limit.h
HDRINST usr/include/linux/netfilter/xt_conntrack.h
HDRINST usr/include/linux/netfilter/xt_TEE.h
HDRINST usr/include/linux/netfilter/xt_RATEEST.h
HDRINST usr/include/linux/netfilter/xt_connlimit.h
HDRINST usr/include/linux/netfilter/ipset/ip_set.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_list.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_hash.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_bitmap.h
HDRINST usr/include/linux/netfilter/x_tables.h
HDRINST usr/include/linux/netfilter/xt_dscp.h
HDRINST usr/include/linux/netfilter/nf_conntrack_ftp.h
HDRINST usr/include/linux/netfilter/xt_cluster.h
HDRINST usr/include/linux/netfilter/nf_conntrack_tuple_common.h
HDRINST usr/include/linux/netfilter/nf_log.h
HDRINST usr/include/linux/netfilter/xt_tcpmss.h
HDRINST usr/include/linux/netfilter/xt_NFLOG.h
HDRINST usr/include/linux/netfilter/xt_l2tp.h
HDRINST usr/include/linux/netfilter/xt_helper.h
HDRINST usr/include/linux/netfilter/xt_statistic.h
HDRINST usr/include/linux/netfilter/nfnetlink_queue.h
HDRINST usr/include/linux/netfilter/nfnetlink_cttimeout.h
HDRINST usr/include/linux/netfilter/xt_CT.h
HDRINST usr/include/linux/netfilter/xt_CHECKSUM.h
HDRINST usr/include/linux/netfilter/xt_connbytes.h
HDRINST usr/include/linux/netfilter/nf_tables.h
HDRINST usr/include/linux/netfilter/xt_state.h
HDRINST usr/include/linux/netfilter/xt_mark.h
HDRINST usr/include/linux/netfilter/xt_cpu.h
HDRINST usr/include/linux/netfilter/nf_tables_compat.h
HDRINST usr/include/linux/netfilter/xt_physdev.h
HDRINST usr/include/linux/netfilter/nfnetlink_conntrack.h
HDRINST usr/include/linux/netfilter/nfnetlink_acct.h
HDRINST usr/include/linux/netfilter/xt_TCPMSS.h
HDRINST usr/include/linux/tty_flags.h
HDRINST usr/include/linux/if_phonet.h
HDRINST usr/include/linux/elf-em.h
HDRINST usr/include/linux/vm_sockets.h
HDRINST usr/include/linux/dlmconstants.h
HDRINST usr/include/linux/bsg.h
HDRINST usr/include/linux/matroxfb.h
HDRINST usr/include/linux/sysctl.h
HDRINST usr/include/linux/unix_diag.h
HDRINST usr/include/linux/pcitest.h
HDRINST usr/include/linux/mman.h
HDRINST usr/include/linux/if_plip.h
HDRINST usr/include/linux/virtio_balloon.h
HDRINST usr/include/linux/pidfd.h
HDRINST usr/include/linux/f2fs.h
HDRINST usr/include/linux/x25.h
HDRINST usr/include/linux/if_cablemodem.h
HDRINST usr/include/linux/utsname.h
HDRINST usr/include/linux/counter.h
HDRINST usr/include/linux/atm_tcp.h
HDRINST usr/include/linux/atalk.h
HDRINST usr/include/linux/virtio_rng.h
HDRINST usr/include/linux/vboxguest.h
HDRINST usr/include/linux/bpf_perf_event.h
HDRINST usr/include/linux/ipmi_ssif_bmc.h
HDRINST usr/include/linux/nfs_mount.h
HDRINST usr/include/linux/sonet.h
HDRINST usr/include/linux/netfilter.h
HDRINST usr/include/linux/keyctl.h
HDRINST usr/include/linux/nl80211.h
HDRINST usr/include/linux/misc/bcm_vk.h
HDRINST usr/include/linux/audit.h
HDRINST usr/include/linux/tipc_config.h
HDRINST usr/include/linux/tipc_sockets_diag.h
HDRINST usr/include/linux/futex.h
HDRINST usr/include/linux/sev-guest.h
HDRINST usr/include/linux/ublk_cmd.h
HDRINST usr/include/linux/types.h
HDRINST usr/include/linux/virtio_input.h
HDRINST usr/include/linux/if_slip.h
HDRINST usr/include/linux/personality.h
HDRINST usr/include/linux/openat2.h
HDRINST usr/include/linux/poll.h
HDRINST usr/include/linux/posix_acl.h
HDRINST usr/include/linux/smc_diag.h
HDRINST usr/include/linux/snmp.h
HDRINST usr/include/linux/errqueue.h
HDRINST usr/include/linux/if_tunnel.h
HDRINST usr/include/linux/fanotify.h
HDRINST usr/include/linux/kernel.h
HDRINST usr/include/linux/rtnetlink.h
HDRINST usr/include/linux/rpl.h
HDRINST usr/include/linux/memfd.h
HDRINST usr/include/linux/serial_core.h
HDRINST usr/include/linux/dns_resolver.h
HDRINST usr/include/linux/pr.h
HDRINST usr/include/linux/atm_eni.h
HDRINST usr/include/linux/lp.h
HDRINST usr/include/linux/ultrasound.h
HDRINST usr/include/linux/virtio_mem.h
HDRINST usr/include/linux/sctp.h
HDRINST usr/include/linux/uio.h
HDRINST usr/include/linux/tcp_metrics.h
HDRINST usr/include/linux/wwan.h
HDRINST usr/include/linux/atmbr2684.h
HDRINST usr/include/linux/in_route.h
HDRINST usr/include/linux/qemu_fw_cfg.h
HDRINST usr/include/linux/if_macsec.h
HDRINST usr/include/linux/usb/charger.h
HDRINST usr/include/linux/usb/g_uvc.h
HDRINST usr/include/linux/usb/gadgetfs.h
HDRINST usr/include/linux/usb/raw_gadget.h
HDRINST usr/include/linux/usb/cdc-wdm.h
HDRINST usr/include/linux/usb/g_printer.h
HDRINST usr/include/linux/usb/midi.h
HDRINST usr/include/linux/usb/tmc.h
HDRINST usr/include/linux/usb/video.h
HDRINST usr/include/linux/usb/functionfs.h
HDRINST usr/include/linux/usb/audio.h
HDRINST usr/include/linux/usb/ch11.h
HDRINST usr/include/linux/usb/ch9.h
HDRINST usr/include/linux/usb/cdc.h
HDRINST usr/include/linux/jffs2.h
HDRINST usr/include/linux/ax25.h
HDRINST usr/include/linux/auto_fs.h
HDRINST usr/include/linux/tiocl.h
HDRINST usr/include/linux/scc.h
HDRINST usr/include/linux/psci.h
HDRINST usr/include/linux/swab.h
HDRINST usr/include/linux/cec.h
HDRINST usr/include/linux/kfd_ioctl.h
HDRINST usr/include/linux/smc.h
HDRINST usr/include/linux/qrtr.h
HDRINST usr/include/linux/screen_info.h
HDRINST usr/include/linux/nfsacl.h
HDRINST usr/include/linux/seg6_hmac.h
HDRINST usr/include/linux/gameport.h
HDRINST usr/include/linux/wireless.h
HDRINST usr/include/linux/fdreg.h
HDRINST usr/include/linux/cciss_defs.h
HDRINST usr/include/linux/serial_reg.h
HDRINST usr/include/linux/perf_event.h
HDRINST usr/include/linux/in6.h
HDRINST usr/include/linux/hid.h
HDRINST usr/include/linux/netlink.h
HDRINST usr/include/linux/fuse.h
HDRINST usr/include/linux/magic.h
HDRINST usr/include/linux/ioam6_iptunnel.h
HDRINST usr/include/linux/stm.h
HDRINST usr/include/linux/vsockmon.h
HDRINST usr/include/linux/seg6.h
HDRINST usr/include/linux/idxd.h
HDRINST usr/include/linux/nitro_enclaves.h
HDRINST usr/include/linux/ptrace.h
HDRINST usr/include/linux/ioam6_genl.h
HDRINST usr/include/linux/qnx4_fs.h
HDRINST usr/include/linux/fsl_mc.h
HDRINST usr/include/linux/net_tstamp.h
HDRINST usr/include/linux/msg.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_TTL.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ttl.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ah.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ECN.h
HDRINST usr/include/linux/netfilter_ipv4/ip_tables.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ecn.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_REJECT.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_LOG.h
HDRINST usr/include/linux/sem.h
HDRINST usr/include/linux/net_namespace.h
HDRINST usr/include/linux/radeonfb.h
HDRINST usr/include/linux/tee.h
HDRINST usr/include/linux/udp.h
HDRINST usr/include/linux/virtio_bt.h
HDRINST usr/include/linux/v4l2-subdev.h
HDRINST usr/include/linux/posix_acl_xattr.h
HDRINST usr/include/linux/v4l2-mediabus.h
HDRINST usr/include/linux/atmapi.h
HDRINST usr/include/linux/raid/md_p.h
HDRINST usr/include/linux/raid/md_u.h
HDRINST usr/include/linux/zorro_ids.h
HDRINST usr/include/linux/nbd.h
HDRINST usr/include/linux/isst_if.h
HDRINST usr/include/linux/rxrpc.h
HDRINST usr/include/linux/unistd.h
HDRINST usr/include/linux/if_arp.h
HDRINST usr/include/linux/atm_zatm.h
HDRINST usr/include/linux/io_uring.h
HDRINST usr/include/linux/if_fddi.h
HDRINST usr/include/linux/bpqether.h
HDRINST usr/include/linux/sysinfo.h
HDRINST usr/include/linux/auto_dev-ioctl.h
HDRINST usr/include/linux/nfs4_mount.h
HDRINST usr/include/linux/keyboard.h
HDRINST usr/include/linux/virtio_mmio.h
HDRINST usr/include/linux/input.h
HDRINST usr/include/linux/qnxtypes.h
HDRINST usr/include/linux/mdio.h
HDRINST usr/include/linux/lwtunnel.h
HDRINST usr/include/linux/gfs2_ondisk.h
HDRINST usr/include/linux/nfs4.h
HDRINST usr/include/linux/ptp_clock.h
HDRINST usr/include/linux/nubus.h
HDRINST usr/include/linux/if_bonding.h
HDRINST usr/include/linux/kcov.h
HDRINST usr/include/linux/fadvise.h
HDRINST usr/include/linux/taskstats.h
HDRINST usr/include/linux/veth.h
HDRINST usr/include/linux/atm.h
HDRINST usr/include/linux/ipmi.h
HDRINST usr/include/linux/kdev_t.h
HDRINST usr/include/linux/mount.h
HDRINST usr/include/linux/shm.h
HDRINST usr/include/linux/resource.h
HDRINST usr/include/linux/prctl.h
HDRINST usr/include/linux/watch_queue.h
HDRINST usr/include/linux/sched.h
HDRINST usr/include/linux/phonet.h
HDRINST usr/include/linux/random.h
HDRINST usr/include/linux/tty.h
HDRINST usr/include/linux/apm_bios.h
HDRINST usr/include/linux/fd.h
HDRINST usr/include/linux/um_timetravel.h
HDRINST usr/include/linux/tls.h
HDRINST usr/include/linux/rpmsg_types.h
HDRINST usr/include/linux/pfrut.h
HDRINST usr/include/linux/mei.h
HDRINST usr/include/linux/fsi.h
HDRINST usr/include/linux/rds.h
HDRINST usr/include/linux/if_x25.h
HDRINST usr/include/linux/param.h
HDRINST usr/include/linux/netdevice.h
HDRINST usr/include/linux/binfmts.h
HDRINST usr/include/linux/if_pppox.h
HDRINST usr/include/linux/sockios.h
HDRINST usr/include/linux/kcm.h
HDRINST usr/include/linux/virtio_9p.h
HDRINST usr/include/linux/genwqe/genwqe_card.h
HDRINST usr/include/linux/if_tun.h
HDRINST usr/include/linux/if_ether.h
HDRINST usr/include/linux/kvm_para.h
HDRINST usr/include/linux/kernel-page-flags.h
HDRINST usr/include/linux/cdrom.h
HDRINST usr/include/linux/un.h
HDRINST usr/include/linux/module.h
HDRINST usr/include/linux/mqueue.h
HDRINST usr/include/linux/a.out.h
HDRINST usr/include/linux/input-event-codes.h
HDRINST usr/include/linux/coda.h
HDRINST usr/include/linux/rio_mport_cdev.h
HDRINST usr/include/linux/ipsec.h
HDRINST usr/include/linux/blkpg.h
HDRINST usr/include/linux/blkzoned.h
HDRINST usr/include/linux/netfilter_bridge/ebt_arpreply.h
HDRINST usr/include/linux/netfilter_bridge/ebt_redirect.h
HDRINST usr/include/linux/netfilter_bridge/ebt_nflog.h
HDRINST usr/include/linux/netfilter_bridge/ebt_802_3.h
HDRINST usr/include/linux/netfilter_bridge/ebt_nat.h
HDRINST usr/include/linux/netfilter_bridge/ebt_mark_m.h
HDRINST usr/include/linux/netfilter_bridge/ebtables.h
HDRINST usr/include/linux/netfilter_bridge/ebt_vlan.h
HDRINST usr/include/linux/netfilter_bridge/ebt_limit.h
HDRINST usr/include/linux/netfilter_bridge/ebt_log.h
HDRINST usr/include/linux/netfilter_bridge/ebt_stp.h
HDRINST usr/include/linux/netfilter_bridge/ebt_pkttype.h
HDRINST usr/include/linux/netfilter_bridge/ebt_ip.h
HDRINST usr/include/linux/netfilter_bridge/ebt_ip6.h
HDRINST usr/include/linux/netfilter_bridge/ebt_arp.h
HDRINST usr/include/linux/netfilter_bridge/ebt_mark_t.h
HDRINST usr/include/linux/netfilter_bridge/ebt_among.h
HDRINST usr/include/linux/reiserfs_fs.h
HDRINST usr/include/linux/cciss_ioctl.h
HDRINST usr/include/linux/fsmap.h
HDRINST usr/include/linux/smiapp.h
HDRINST usr/include/linux/switchtec_ioctl.h
HDRINST usr/include/linux/atmdev.h
HDRINST usr/include/linux/hpet.h
HDRINST usr/include/linux/virtio_config.h
HDRINST usr/include/linux/string.h
HDRINST usr/include/linux/kfd_sysfs.h
HDRINST usr/include/linux/inet_diag.h
HDRINST usr/include/linux/netdev.h
HDRINST usr/include/linux/xattr.h
HDRINST usr/include/linux/iommufd.h
HDRINST usr/include/linux/errno.h
HDRINST usr/include/linux/icmp.h
HDRINST usr/include/linux/i2o-dev.h
HDRINST usr/include/linux/pg.h
HDRINST usr/include/linux/if_bridge.h
HDRINST usr/include/linux/thermal.h
HDRINST usr/include/linux/uinput.h
HDRINST usr/include/linux/dqblk_xfs.h
HDRINST usr/include/linux/v4l2-common.h
HDRINST usr/include/linux/nvram.h
LD /kernel/build64/tools/objtool/libsubcmd/libsubcmd-in.o
HDRINST usr/include/linux/if_vlan.h
HDRINST usr/include/linux/uhid.h
HDRINST usr/include/linux/omap3isp.h
HDRINST usr/include/linux/rose.h
HDRINST usr/include/linux/phantom.h
HDRINST usr/include/linux/ipmi_msgdefs.h
HDRINST usr/include/linux/bcm933xx_hcs.h
HDRINST usr/include/linux/bpf.h
HDRINST usr/include/linux/mempolicy.h
HDRINST usr/include/linux/efs_fs_sb.h
HDRINST usr/include/linux/nexthop.h
HDRINST usr/include/linux/net_dropmon.h
HDRINST usr/include/linux/surface_aggregator/cdev.h
HDRINST usr/include/linux/surface_aggregator/dtx.h
HDRINST usr/include/linux/net.h
HDRINST usr/include/linux/mii.h
HDRINST usr/include/linux/cm4000_cs.h
HDRINST usr/include/linux/virtio_pcidev.h
HDRINST usr/include/linux/termios.h
HDRINST usr/include/linux/cgroupstats.h
HDRINST usr/include/linux/mpls.h
HDRINST usr/include/linux/iommu.h
HDRINST usr/include/linux/toshiba.h
HDRINST usr/include/linux/virtio_scsi.h
HDRINST usr/include/linux/zorro.h
HDRINST usr/include/linux/chio.h
HDRINST usr/include/linux/pkt_sched.h
HDRINST usr/include/linux/cramfs_fs.h
HDRINST usr/include/linux/nfs3.h
HDRINST usr/include/linux/vfio_ccw.h
HDRINST usr/include/linux/atm_nicstar.h
HDRINST usr/include/linux/ncsi.h
HDRINST usr/include/linux/virtio_net.h
HDRINST usr/include/linux/ioctl.h
HDRINST usr/include/linux/stddef.h
AR /kernel/build64/tools/objtool/libsubcmd/libsubcmd.a
HDRINST usr/include/linux/limits.h
HDRINST usr/include/linux/ipmi_bmc.h
HDRINST usr/include/linux/netfilter_arp.h
HDRINST usr/include/linux/if_addr.h
HDRINST usr/include/linux/rpmsg.h
HDRINST usr/include/linux/media-bus-format.h
HDRINST usr/include/linux/ppp_defs.h
HDRINST usr/include/linux/kernelcapi.h
HDRINST usr/include/linux/ethtool.h
HDRINST usr/include/linux/aspeed-video.h
HDRINST usr/include/linux/hdlc.h
HDRINST usr/include/linux/fscrypt.h
HDRINST usr/include/linux/batadv_packet.h
HDRINST usr/include/linux/uuid.h
HDRINST usr/include/linux/capi.h
HDRINST usr/include/linux/mptcp.h
HDRINST usr/include/linux/hidraw.h
HDRINST usr/include/linux/virtio_console.h
HDRINST usr/include/linux/irqnr.h
HDRINST usr/include/linux/coresight-stm.h
HDRINST usr/include/linux/cxl_mem.h
HDRINST usr/include/linux/iso_fs.h
HDRINST usr/include/linux/virtio_blk.h
HDRINST usr/include/linux/udf_fs_i.h
HDRINST usr/include/linux/coff.h
HDRINST usr/include/linux/dma-buf.h
HDRINST usr/include/linux/ife.h
HDRINST usr/include/linux/agpgart.h
HDRINST usr/include/linux/socket.h
HDRINST usr/include/linux/nilfs2_ondisk.h
HDRINST usr/include/linux/connector.h
HDRINST usr/include/linux/auto_fs4.h
HDRINST usr/include/linux/bt-bmc.h
HDRINST usr/include/linux/map_to_7segment.h
HDRINST usr/include/linux/tc_act/tc_skbedit.h
HDRINST usr/include/linux/tc_act/tc_ctinfo.h
HDRINST usr/include/linux/tc_act/tc_defact.h
HDRINST usr/include/linux/tc_act/tc_gact.h
HDRINST usr/include/linux/tc_act/tc_vlan.h
HDRINST usr/include/linux/tc_act/tc_skbmod.h
HDRINST usr/include/linux/tc_act/tc_sample.h
HDRINST usr/include/linux/tc_act/tc_tunnel_key.h
HDRINST usr/include/linux/tc_act/tc_gate.h
HDRINST usr/include/linux/tc_act/tc_mirred.h
HDRINST usr/include/linux/tc_act/tc_nat.h
HDRINST usr/include/linux/tc_act/tc_csum.h
HDRINST usr/include/linux/tc_act/tc_connmark.h
HDRINST usr/include/linux/tc_act/tc_ife.h
HDRINST usr/include/linux/tc_act/tc_mpls.h
HDRINST usr/include/linux/tc_act/tc_ct.h
HDRINST usr/include/linux/tc_act/tc_pedit.h
HDRINST usr/include/linux/tc_act/tc_bpf.h
HDRINST usr/include/linux/tc_act/tc_ipt.h
HDRINST usr/include/linux/netrom.h
HDRINST usr/include/linux/joystick.h
HDRINST usr/include/linux/falloc.h
HDRINST usr/include/linux/cycx_cfm.h
HDRINST usr/include/linux/omapfb.h
HDRINST usr/include/linux/msdos_fs.h
HDRINST usr/include/linux/virtio_types.h
HDRINST usr/include/linux/mroute.h
HDRINST usr/include/linux/psample.h
HDRINST usr/include/linux/ipv6.h
HDRINST usr/include/linux/dw100.h
HDRINST usr/include/linux/psp-sev.h
HDRINST usr/include/linux/vfio.h
HDRINST usr/include/linux/if_ppp.h
HDRINST usr/include/linux/byteorder/big_endian.h
HDRINST usr/include/linux/byteorder/little_endian.h
CC /kernel/build64/tools/objtool/weak.o
HDRINST usr/include/linux/comedi.h
HDRINST usr/include/linux/scif_ioctl.h
HDRINST usr/include/linux/timerfd.h
CC /kernel/build64/tools/objtool/check.o
CC /kernel/build64/tools/objtool/special.o
HDRINST usr/include/linux/time_types.h
HDRINST usr/include/linux/firewire-constants.h
HDRINST usr/include/linux/virtio_snd.h
MKDIR /kernel/build64/tools/objtool/arch/x86/
HDRINST usr/include/linux/ppp-ioctl.h
CC /kernel/build64/tools/objtool/builtin-check.o
HDRINST usr/include/linux/fib_rules.h
CC /kernel/build64/tools/objtool/elf.o
MKDIR /kernel/build64/tools/objtool/arch/x86/lib/
CC /kernel/build64/tools/objtool/objtool.o
HDRINST usr/include/linux/gen_stats.h
HDRINST usr/include/linux/virtio_iommu.h
CC /kernel/build64/tools/objtool/orc_gen.o
HDRINST usr/include/linux/genetlink.h
HDRINST usr/include/linux/uvcvideo.h
CC /kernel/build64/tools/objtool/arch/x86/special.o
HDRINST usr/include/linux/pfkeyv2.h
HDRINST usr/include/linux/soundcard.h
CC /kernel/build64/tools/objtool/orc_dump.o
HDRINST usr/include/linux/times.h
CC /kernel/build64/tools/objtool/libstring.o
HDRINST usr/include/linux/nfc.h
HDRINST usr/include/linux/affs_hardblocks.h
HDRINST usr/include/linux/nilfs2_api.h
GEN /kernel/build64/tools/objtool/arch/x86/lib/inat-tables.c
HDRINST usr/include/linux/rseq.h
CC /kernel/build64/tools/objtool/libctype.o
CC /kernel/build64/tools/objtool/str_error_r.o
CC /kernel/build64/tools/objtool/librbtree.o
HDRINST usr/include/linux/caif/caif_socket.h
HDRINST usr/include/linux/caif/if_caif.h
HDRINST usr/include/linux/i2c-dev.h
HDRINST usr/include/linux/cuda.h
HDRINST usr/include/linux/cn_proc.h
HDRINST usr/include/linux/parport.h
HDRINST usr/include/linux/v4l2-controls.h
HDRINST usr/include/linux/hsi/cs-protocol.h
HDRINST usr/include/linux/hsi/hsi_char.h
HDRINST usr/include/linux/seg6_genl.h
HDRINST usr/include/linux/am437x-vpfe.h
HDRINST usr/include/linux/amt.h
HDRINST usr/include/linux/netconf.h
HDRINST usr/include/linux/erspan.h
HDRINST usr/include/linux/nsfs.h
HDRINST usr/include/linux/xilinx-v4l2-controls.h
HDRINST usr/include/linux/aspeed-p2a-ctrl.h
HDRINST usr/include/linux/vfio_zdev.h
HDRINST usr/include/linux/serio.h
HDRINST usr/include/linux/acrn.h
HDRINST usr/include/linux/nfs2.h
HDRINST usr/include/linux/virtio_pci.h
HDRINST usr/include/linux/ipc.h
HDRINST usr/include/linux/ethtool_netlink.h
HDRINST usr/include/linux/kd.h
HDRINST usr/include/linux/elf.h
HDRINST usr/include/linux/videodev2.h
HDRINST usr/include/linux/if_alg.h
HDRINST usr/include/linux/sonypi.h
HDRINST usr/include/linux/fsverity.h
HDRINST usr/include/linux/if.h
HDRINST usr/include/linux/btrfs.h
HDRINST usr/include/linux/vm_sockets_diag.h
HDRINST usr/include/linux/netfilter_bridge.h
HDRINST usr/include/linux/packet_diag.h
HDRINST usr/include/linux/netfilter_ipv4.h
HDRINST usr/include/linux/kvm.h
HDRINST usr/include/linux/pci.h
HDRINST usr/include/linux/if_addrlabel.h
HDRINST usr/include/linux/hdlcdrv.h
HDRINST usr/include/linux/cfm_bridge.h
HDRINST usr/include/linux/fiemap.h
HDRINST usr/include/linux/dm-ioctl.h
HDRINST usr/include/linux/aspeed-lpc-ctrl.h
HDRINST usr/include/linux/atmioc.h
HDRINST usr/include/linux/dlm.h
HDRINST usr/include/linux/pci_regs.h
HDRINST usr/include/linux/cachefiles.h
HDRINST usr/include/linux/membarrier.h
HDRINST usr/include/linux/nfs_idmap.h
HDRINST usr/include/linux/ip.h
HDRINST usr/include/linux/atm_he.h
HDRINST usr/include/linux/nfsd/export.h
HDRINST usr/include/linux/nfsd/stats.h
HDRINST usr/include/linux/nfsd/debug.h
HDRINST usr/include/linux/nfsd/cld.h
HDRINST usr/include/linux/ip_vs.h
HDRINST usr/include/linux/vmcore.h
HDRINST usr/include/linux/vbox_vmmdev_types.h
HDRINST usr/include/linux/dvb/osd.h
HDRINST usr/include/linux/dvb/dmx.h
HDRINST usr/include/linux/dvb/net.h
HDRINST usr/include/linux/dvb/frontend.h
HDRINST usr/include/linux/dvb/ca.h
HDRINST usr/include/linux/dvb/version.h
HDRINST usr/include/linux/dvb/video.h
HDRINST usr/include/linux/dvb/audio.h
HDRINST usr/include/linux/nfs.h
HDRINST usr/include/linux/if_link.h
HDRINST usr/include/linux/wait.h
HDRINST usr/include/linux/icmpv6.h
HDRINST usr/include/linux/media.h
HDRINST usr/include/linux/seg6_local.h
HDRINST usr/include/linux/openvswitch.h
CC /kernel/build64/tools/objtool/arch/x86/decode.o
HDRINST usr/include/linux/atmsap.h
HDRINST usr/include/linux/fpga-dfl.h
HDRINST usr/include/linux/bpfilter.h
HDRINST usr/include/linux/userio.h
HDRINST usr/include/linux/signal.h
HDRINST usr/include/linux/map_to_14segment.h
HDRINST usr/include/linux/hdreg.h
HDRINST usr/include/linux/utime.h
HDRINST usr/include/linux/usbdevice_fs.h
HDRINST usr/include/linux/timex.h
HDRINST usr/include/linux/if_fc.h
HDRINST usr/include/linux/reiserfs_xattr.h
HDRINST usr/include/linux/hw_breakpoint.h
HDRINST usr/include/linux/quota.h
HDRINST usr/include/linux/ioprio.h
HDRINST usr/include/linux/eventpoll.h
HDRINST usr/include/linux/atmclip.h
HDRINST usr/include/linux/can.h
HDRINST usr/include/linux/if_team.h
HDRINST usr/include/linux/usbip.h
HDRINST usr/include/linux/stat.h
HDRINST usr/include/linux/fou.h
HDRINST usr/include/linux/hash_info.h
HDRINST usr/include/linux/ppp-comp.h
HDRINST usr/include/linux/ip6_tunnel.h
HDRINST usr/include/linux/tipc_netlink.h
HDRINST usr/include/linux/in.h
HDRINST usr/include/linux/wireguard.h
HDRINST usr/include/linux/btf.h
HDRINST usr/include/linux/batman_adv.h
HDRINST usr/include/linux/fcntl.h
HDRINST usr/include/linux/if_ltalk.h
HDRINST usr/include/linux/i2c.h
HDRINST usr/include/linux/atm_idt77105.h
HDRINST usr/include/linux/kexec.h
HDRINST usr/include/linux/arm_sdei.h
HDRINST usr/include/linux/netfilter_ipv6/ip6_tables.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_ah.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_NPT.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_rt.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_REJECT.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_opts.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_srh.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_LOG.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_mh.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_HL.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_hl.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_frag.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_ipv6header.h
HDRINST usr/include/linux/minix_fs.h
HDRINST usr/include/linux/aio_abi.h
HDRINST usr/include/linux/pktcdvd.h
HDRINST usr/include/linux/libc-compat.h
HDRINST usr/include/linux/atmlec.h
HDRINST usr/include/linux/signalfd.h
HDRINST usr/include/linux/bpf_common.h
HDRINST usr/include/linux/seg6_iptunnel.h
HDRINST usr/include/linux/synclink.h
HDRINST usr/include/linux/mpls_iptunnel.h
HDRINST usr/include/linux/mctp.h
HDRINST usr/include/linux/if_xdp.h
HDRINST usr/include/linux/llc.h
HDRINST usr/include/linux/atmsvc.h
HDRINST usr/include/linux/sed-opal.h
HDRINST usr/include/linux/sock_diag.h
HDRINST usr/include/linux/time.h
HDRINST usr/include/linux/securebits.h
HDRINST usr/include/linux/fsl_hypervisor.h
HDRINST usr/include/linux/if_hippi.h
HDRINST usr/include/linux/dlm_netlink.h
HDRINST usr/include/linux/seccomp.h
HDRINST usr/include/linux/oom.h
HDRINST usr/include/linux/filter.h
HDRINST usr/include/linux/inotify.h
HDRINST usr/include/linux/rfkill.h
HDRINST usr/include/linux/reboot.h
HDRINST usr/include/linux/can/vxcan.h
HDRINST usr/include/linux/can/j1939.h
HDRINST usr/include/linux/can/netlink.h
HDRINST usr/include/linux/can/bcm.h
HDRINST usr/include/linux/can/raw.h
HDRINST usr/include/linux/can/gw.h
HDRINST usr/include/linux/can/error.h
HDRINST usr/include/linux/can/isotp.h
HDRINST usr/include/linux/if_eql.h
HDRINST usr/include/linux/hiddev.h
HDRINST usr/include/linux/blktrace_api.h
HDRINST usr/include/linux/ccs.h
HDRINST usr/include/linux/ioam6.h
HDRINST usr/include/linux/hsr_netlink.h
HDRINST usr/include/linux/mmc/ioctl.h
HDRINST usr/include/linux/bfs_fs.h
HDRINST usr/include/linux/rio_cm_cdev.h
HDRINST usr/include/linux/uleds.h
HDRINST usr/include/linux/mrp_bridge.h
HDRINST usr/include/linux/adb.h
HDRINST usr/include/linux/pmu.h
HDRINST usr/include/linux/udmabuf.h
HDRINST usr/include/linux/kcmp.h
HDRINST usr/include/linux/dma-heap.h
HDRINST usr/include/linux/userfaultfd.h
HDRINST usr/include/linux/netfilter_arp/arpt_mangle.h
HDRINST usr/include/linux/netfilter_arp/arp_tables.h
HDRINST usr/include/linux/tipc.h
HDRINST usr/include/linux/virtio_ids.h
HDRINST usr/include/linux/l2tp.h
HDRINST usr/include/linux/devlink.h
HDRINST usr/include/linux/virtio_gpio.h
HDRINST usr/include/linux/dcbnl.h
HDRINST usr/include/linux/cyclades.h
HDRINST usr/include/sound/intel/avs/tokens.h
HDRINST usr/include/sound/sof/fw.h
HDRINST usr/include/sound/sof/abi.h
HDRINST usr/include/sound/sof/tokens.h
HDRINST usr/include/sound/sof/header.h
HDRINST usr/include/sound/usb_stream.h
HDRINST usr/include/sound/sfnt_info.h
HDRINST usr/include/sound/asequencer.h
HDRINST usr/include/sound/tlv.h
HDRINST usr/include/sound/asound.h
HDRINST usr/include/sound/asoc.h
HDRINST usr/include/sound/sb16_csp.h
HDRINST usr/include/sound/compress_offload.h
HDRINST usr/include/sound/hdsp.h
HDRINST usr/include/sound/emu10k1.h
HDRINST usr/include/sound/snd_ar_tokens.h
HDRINST usr/include/sound/snd_sst_tokens.h
HDRINST usr/include/sound/asound_fm.h
HDRINST usr/include/sound/hdspm.h
HDRINST usr/include/sound/compress_params.h
HDRINST usr/include/sound/firewire.h
HDRINST usr/include/sound/skl-tplg-interface.h
HDRINST usr/include/scsi/scsi_bsg_ufs.h
HDRINST usr/include/scsi/scsi_netlink_fc.h
HDRINST usr/include/scsi/scsi_bsg_mpi3mr.h
HDRINST usr/include/scsi/fc/fc_ns.h
HDRINST usr/include/scsi/fc/fc_fs.h
HDRINST usr/include/scsi/fc/fc_els.h
HDRINST usr/include/scsi/fc/fc_gs.h
HDRINST usr/include/scsi/scsi_bsg_fc.h
HDRINST usr/include/scsi/cxlflash_ioctl.h
HDRINST usr/include/scsi/scsi_netlink.h
HDRINST usr/include/linux/version.h
HDRINST usr/include/asm/processor-flags.h
HDRINST usr/include/asm/auxvec.h
HDRINST usr/include/asm/svm.h
HDRINST usr/include/asm/bitsperlong.h
HDRINST usr/include/asm/kvm_perf.h
HDRINST usr/include/asm/mce.h
HDRINST usr/include/asm/posix_types.h
HDRINST usr/include/asm/msr.h
HDRINST usr/include/asm/sigcontext32.h
HDRINST usr/include/asm/mman.h
HDRINST usr/include/asm/shmbuf.h
HDRINST usr/include/asm/e820.h
HDRINST usr/include/asm/posix_types_64.h
HDRINST usr/include/asm/vsyscall.h
HDRINST usr/include/asm/msgbuf.h
HDRINST usr/include/asm/swab.h
HDRINST usr/include/asm/statfs.h
HDRINST usr/include/asm/posix_types_x32.h
HDRINST usr/include/asm/ptrace.h
HDRINST usr/include/asm/unistd.h
HDRINST usr/include/asm/ist.h
HDRINST usr/include/asm/prctl.h
HDRINST usr/include/asm/boot.h
HDRINST usr/include/asm/sigcontext.h
HDRINST usr/include/asm/posix_types_32.h
HDRINST usr/include/asm/kvm_para.h
HDRINST usr/include/asm/a.out.h
HDRINST usr/include/asm/mtrr.h
HDRINST usr/include/asm/amd_hsmp.h
HDRINST usr/include/asm/hwcap2.h
HDRINST usr/include/asm/vm86.h
HDRINST usr/include/asm/ptrace-abi.h
HDRINST usr/include/asm/vmx.h
HDRINST usr/include/asm/ldt.h
HDRINST usr/include/asm/perf_regs.h
HDRINST usr/include/asm/debugreg.h
HDRINST usr/include/asm/kvm.h
HDRINST usr/include/asm/signal.h
HDRINST usr/include/asm/bootparam.h
HDRINST usr/include/asm/siginfo.h
HDRINST usr/include/asm/hw_breakpoint.h
HDRINST usr/include/asm/stat.h
HDRINST usr/include/asm/setup.h
HDRINST usr/include/asm/sembuf.h
HDRINST usr/include/asm/sgx.h
HDRINST usr/include/asm/ucontext.h
HDRINST usr/include/asm/byteorder.h
HDRINST usr/include/asm/unistd_64.h
HDRINST usr/include/asm/ioctls.h
HDRINST usr/include/asm/bpf_perf_event.h
HDRINST usr/include/asm/types.h
HDRINST usr/include/asm/poll.h
HDRINST usr/include/asm/resource.h
HDRINST usr/include/asm/param.h
HDRINST usr/include/asm/sockios.h
HDRINST usr/include/asm/errno.h
HDRINST usr/include/asm/unistd_x32.h
HDRINST usr/include/asm/termios.h
HDRINST usr/include/asm/ioctl.h
HDRINST usr/include/asm/socket.h
HDRINST usr/include/asm/unistd_32.h
HDRINST usr/include/asm/termbits.h
HDRINST usr/include/asm/fcntl.h
HDRINST usr/include/asm/ipcbuf.h
HOSTLD scripts/mod/modpost
CC kernel/bounds.s
CHKSHA1 ../include/linux/atomic/atomic-arch-fallback.h
CHKSHA1 ../include/linux/atomic/atomic-instrumented.h
CHKSHA1 ../include/linux/atomic/atomic-long.h
UPD include/generated/timeconst.h
UPD include/generated/bounds.h
CC arch/x86/kernel/asm-offsets.s
LD /kernel/build64/tools/objtool/arch/x86/objtool-in.o
UPD include/generated/asm-offsets.h
CALL ../scripts/checksyscalls.sh
LD /kernel/build64/tools/objtool/objtool-in.o
LINK /kernel/build64/tools/objtool/objtool
LDS scripts/module.lds
CC ipc/compat.o
CC ipc/util.o
CC ipc/msgutil.o
AR certs/built-in.a
CC ipc/msg.o
CC ipc/sem.o
CC ipc/shm.o
HOSTCC usr/gen_init_cpio
CC init/main.o
CC ipc/syscall.o
CC ipc/ipc_sysctl.o
CC ipc/mqueue.o
AS arch/x86/lib/clear_page_64.o
CC security/commoncap.o
CC io_uring/io_uring.o
CC ipc/namespace.o
AR arch/x86/video/built-in.a
CC arch/x86/power/cpu.o
CC arch/x86/pci/i386.o
CC init/do_mounts.o
UPD init/utsversion-tmp.h
AR sound/ppc/built-in.a
AR sound/arm/built-in.a
AR sound/sh/built-in.a
CC [M] arch/x86/video/fbdev.o
AR virt/lib/built-in.a
CC arch/x86/realmode/init.o
AS arch/x86/crypto/aesni-intel_asm.o
CC block/partitions/core.o
AR sound/firewire/built-in.a
AR arch/x86/ia32/built-in.a
AR sound/drivers/opl3/built-in.a
AR drivers/irqchip/built-in.a
AR sound/i2c/other/built-in.a
CC net/core/sock.o
CC security/keys/gc.o
CC [M] virt/lib/irqbypass.o
CC arch/x86/events/amd/core.o
AR sound/isa/ad1816a/built-in.a
CC arch/x86/mm/init.o
AR sound/usb/misc/built-in.a
CC security/keys/key.o
CC sound/core/seq/seq.o
CC block/bdev.o
AR sound/synth/emux/built-in.a
AR sound/pci/asihpi/built-in.a
AR sound/i2c/built-in.a
CC arch/x86/entry/vsyscall/vsyscall_64.o
AR sound/pci/ali5451/built-in.a
AR sound/pci/ac97/built-in.a
CC arch/x86/mm/pat/set_memory.o
CC fs/notify/dnotify/dnotify.o
CC arch/x86/kernel/fpu/init.o
AR sound/synth/built-in.a
AR sound/isa/ad1848/built-in.a
CC security/min_addr.o
CC arch/x86/lib/cmdline.o
AR sound/drivers/opl4/built-in.a
AR sound/usb/usx2y/built-in.a
AR sound/usb/caiaq/built-in.a
CC lib/kunit/test.o
CC arch/x86/entry/vdso/vma.o
AR sound/pci/au88x0/built-in.a
AR drivers/bus/mhi/built-in.a
AR sound/isa/cs423x/built-in.a
CC arch/x86/events/intel/core.o
AR sound/drivers/mpu401/built-in.a
AR sound/usb/6fire/built-in.a
CC arch/x86/mm/pat/memtype.o
AR sound/drivers/vx/built-in.a
AR drivers/bus/built-in.a
AR sound/pci/aw2/built-in.a
CC arch/x86/mm/pat/memtype_interval.o
AR sound/isa/es1688/built-in.a
CC mm/kasan/common.o
CC kernel/sched/core.o
AR sound/usb/hiface/built-in.a
AR sound/drivers/pcsp/built-in.a
CC arch/x86/crypto/aesni-intel_glue.o
AR sound/pci/ctxfi/built-in.a
CC crypto/api.o
AR sound/isa/galaxy/built-in.a
AR sound/drivers/built-in.a
AR sound/usb/bcd2000/built-in.a
AR sound/pci/ca0106/built-in.a
AR drivers/phy/allwinner/built-in.a
AR sound/usb/built-in.a
AR sound/isa/gus/built-in.a
AR sound/pci/cs46xx/built-in.a
CC kernel/sched/fair.o
AR drivers/phy/amlogic/built-in.a
AR sound/isa/msnd/built-in.a
AR sound/pci/cs5535audio/built-in.a
CC net/llc/llc_core.o
AR drivers/phy/broadcom/built-in.a
AR sound/isa/opti9xx/built-in.a
AR sound/pci/lola/built-in.a
AR drivers/phy/cadence/built-in.a
AR sound/isa/sb/built-in.a
AR sound/pci/lx6464es/built-in.a
AR drivers/phy/freescale/built-in.a
AR sound/isa/wavefront/built-in.a
AR sound/pci/echoaudio/built-in.a
AR drivers/phy/hisilicon/built-in.a
AR sound/isa/wss/built-in.a
AS arch/x86/lib/cmpxchg16b_emu.o
AR sound/isa/built-in.a
AR sound/pci/emu10k1/built-in.a
AR drivers/phy/ingenic/built-in.a
AR sound/pci/hda/built-in.a
AR drivers/phy/intel/built-in.a
CC arch/x86/lib/copy_mc.o
CC [M] sound/pci/hda/hda_bind.o
AR drivers/phy/lantiq/built-in.a
CC [M] sound/pci/hda/hda_codec.o
AR drivers/phy/marvell/built-in.a
AR drivers/phy/mediatek/built-in.a
AR drivers/phy/microchip/built-in.a
AR drivers/phy/motorola/built-in.a
AR drivers/phy/mscc/built-in.a
AR drivers/phy/qualcomm/built-in.a
AR drivers/phy/ralink/built-in.a
GEN usr/initramfs_data.cpio
AR drivers/phy/renesas/built-in.a
COPY usr/initramfs_inc_data
AS usr/initramfs_data.o
AR drivers/phy/rockchip/built-in.a
AR drivers/phy/samsung/built-in.a
AR usr/built-in.a
AR drivers/phy/socionext/built-in.a
AS arch/x86/entry/entry.o
AR drivers/phy/st/built-in.a
AR drivers/phy/sunplus/built-in.a
CC arch/x86/mm/init_64.o
AR drivers/phy/tegra/built-in.a
AR drivers/phy/ti/built-in.a
AR drivers/phy/xilinx/built-in.a
CC drivers/phy/phy-core.o
AR virt/built-in.a
AS arch/x86/lib/copy_mc_64.o
CC mm/kasan/report.o
AS arch/x86/lib/copy_page_64.o
AS arch/x86/lib/copy_user_64.o
CC drivers/gpio/gpiolib.o
AR drivers/pinctrl/actions/built-in.a
AR drivers/pinctrl/bcm/built-in.a
CC sound/core/seq/seq_lock.o
AR drivers/pinctrl/cirrus/built-in.a
CC crypto/cipher.o
AS arch/x86/realmode/rm/header.o
AR drivers/pinctrl/freescale/built-in.a
CC lib/math/div64.o
CC arch/x86/lib/cpu.o
CC arch/x86/kernel/fpu/bugs.o
CC drivers/pinctrl/intel/pinctrl-baytrail.o
AS arch/x86/realmode/rm/trampoline_64.o
AS arch/x86/realmode/rm/stack.o
CC drivers/pinctrl/intel/pinctrl-intel.o
CC [M] drivers/pinctrl/intel/pinctrl-cherryview.o
CC lib/math/gcd.o
CC [M] drivers/pinctrl/intel/pinctrl-broxton.o
AR fs/notify/dnotify/built-in.a
AS arch/x86/realmode/rm/reboot.o
CC fs/notify/inotify/inotify_fsnotify.o
AR drivers/pinctrl/mediatek/built-in.a
CC arch/x86/mm/fault.o
AS arch/x86/realmode/rm/wakeup_asm.o
CC arch/x86/pci/init.o
CC lib/math/lcm.o
CC lib/crypto/memneq.o
CC arch/x86/realmode/rm/wakemain.o
CC lib/kunit/resource.o
CC arch/x86/kernel/fpu/core.o
CC lib/math/int_pow.o
CC kernel/locking/mutex.o
CC arch/x86/realmode/rm/video-mode.o
CC arch/x86/entry/vdso/extable.o
AS arch/x86/entry/vsyscall/vsyscall_emu_64.o
CC lib/math/int_sqrt.o
CC arch/x86/power/hibernate_64.o
AS arch/x86/realmode/rm/copy.o
AR arch/x86/entry/vsyscall/built-in.a
CC block/partitions/ldm.o
CC init/do_mounts_initrd.o
AS arch/x86/crypto/aesni-intel_avx-x86_64.o
CC lib/math/reciprocal_div.o
CC block/partitions/msdos.o
CC net/llc/llc_input.o
AS arch/x86/realmode/rm/bioscall.o
AS arch/x86/power/hibernate_asm_64.o
CC sound/core/seq/seq_clientmgr.o
CC arch/x86/realmode/rm/regs.o
CC security/keys/keyring.o
CC arch/x86/lib/delay.o
AS arch/x86/lib/getuser.o
GEN arch/x86/lib/inat-tables.c
CC lib/math/rational.o
CC block/partitions/efi.o
CC crypto/compress.o
CC arch/x86/realmode/rm/video-vga.o
CC arch/x86/power/hibernate.o
CC [M] lib/math/prime_numbers.o
CC kernel/sched/build_policy.o
CC arch/x86/events/amd/lbr.o
CC arch/x86/realmode/rm/video-vesa.o
CC lib/crypto/utils.o
CC security/inode.o
CC [M] sound/pci/hda/hda_jack.o
CC mm/filemap.o
CC arch/x86/entry/vdso/vdso32-setup.o
AS arch/x86/crypto/aes_ctrby8_avx-x86_64.o
CC arch/x86/realmode/rm/video-bios.o
CC fs/notify/inotify/inotify_user.o
CC lib/kunit/static_stub.o
CC lib/kunit/string-stream.o
CC mm/kasan/init.o
AS [M] arch/x86/crypto/ghash-clmulni-intel_asm.o
PASYMS arch/x86/realmode/rm/pasyms.h
CC arch/x86/lib/insn-eval.o
LDS arch/x86/realmode/rm/realmode.lds
LD arch/x86/realmode/rm/realmode.elf
CC arch/x86/pci/mmconfig_64.o
RELOCS arch/x86/realmode/rm/realmode.relocs
CC [M] arch/x86/crypto/ghash-clmulni-intel_glue.o
OBJCOPY arch/x86/realmode/rm/realmode.bin
AS arch/x86/realmode/rmpiggy.o
AR drivers/phy/built-in.a
AR arch/x86/realmode/built-in.a
AR drivers/pwm/built-in.a
CC ipc/mq_sysctl.o
AR arch/x86/net/built-in.a
AR arch/x86/platform/atom/built-in.a
AR arch/x86/platform/ce4100/built-in.a
CC lib/kunit/assert.o
CC arch/x86/platform/efi/memmap.o
CC [M] arch/x86/kvm/../../../virt/kvm/kvm_main.o
CC crypto/algapi.o
CC arch/x86/platform/efi/quirks.o
LDS arch/x86/entry/vdso/vdso.lds
AS [M] arch/x86/crypto/crc32-pclmul_asm.o
AS arch/x86/entry/vdso/vdso-note.o
CC init/initramfs.o
CC arch/x86/entry/vdso/vclock_gettime.o
CC mm/kasan/generic.o
CC security/keys/keyctl.o
CC lib/crypto/chacha.o
AR arch/x86/mm/pat/built-in.a
AR lib/math/built-in.a
CC arch/x86/lib/insn.o
CC drivers/pci/msi/pcidev_msi.o
AS arch/x86/lib/memcpy_64.o
CC lib/zlib_inflate/inffast.o
CC arch/x86/pci/direct.o
CC drivers/pci/msi/api.o
CC lib/crypto/aes.o
CC lib/crypto/gf128mul.o
AR arch/x86/power/built-in.a
CC lib/zlib_inflate/inflate.o
CC net/llc/llc_output.o
CC lib/crypto/blake2s.o
CC arch/x86/pci/mmconfig-shared.o
CC [M] drivers/pinctrl/intel/pinctrl-geminilake.o
CC lib/crypto/blake2s-generic.o
CC drivers/pci/msi/msi.o
CC [M] arch/x86/crypto/crc32-pclmul_glue.o
CC arch/x86/events/amd/ibs.o
CC arch/x86/events/amd/uncore.o
CC drivers/pci/msi/irqdomain.o
CC lib/kunit/try-catch.o
AR sound/pci/ice1712/built-in.a
CC kernel/sched/build_utility.o
AR block/partitions/built-in.a
CC arch/x86/mm/ioremap.o
CC arch/x86/kernel/fpu/regset.o
CC block/fops.o
AR arch/x86/platform/geode/built-in.a
CC lib/kunit/executor.o
CC arch/x86/pci/fixup.o
CC arch/x86/entry/vdso/vgetcpu.o
AS arch/x86/lib/memmove_64.o
HOSTCC arch/x86/entry/vdso/vdso2c
CC mm/mempool.o
CC drivers/video/console/dummycon.o
CC drivers/idle/intel_idle.o
CC drivers/video/console/vgacon.o
AR drivers/char/ipmi/built-in.a
AR ipc/built-in.a
CC drivers/acpi/acpica/dsargs.o
CC security/keys/permission.o
AR fs/notify/inotify/built-in.a
AS arch/x86/lib/memset_64.o
CC fs/notify/fanotify/fanotify.o
CC drivers/acpi/acpica/dscontrol.o
CC arch/x86/lib/misc.o
CC [M] drivers/pinctrl/intel/pinctrl-sunrisepoint.o
AS [M] arch/x86/crypto/crct10dif-pcl-asm_64.o
CC arch/x86/platform/efi/efi.o
CC arch/x86/lib/pc-conf-reg.o
CC [M] arch/x86/crypto/crct10dif-pclmul_glue.o
CC drivers/acpi/apei/apei-base.o
CC sound/core/seq/seq_memory.o
CC drivers/acpi/apei/hest.o
CC init/calibrate.o
CC security/keys/process_keys.o
CC lib/crypto/blake2s-selftest.o
CC [M] sound/pci/hda/hda_auto_parser.o
CC mm/kasan/report_generic.o
CC mm/kasan/shadow.o
AR net/llc/built-in.a
LDS arch/x86/entry/vdso/vdso32/vdso32.lds
CC lib/zlib_inflate/infutil.o
CC drivers/acpi/apei/erst.o
AS arch/x86/lib/putuser.o
AS arch/x86/entry/vdso/vdso32/note.o
CC lib/kunit/hooks.o
AS arch/x86/lib/retpoline.o
AS arch/x86/entry/vdso/vdso32/system_call.o
CC sound/core/seq/seq_queue.o
AS arch/x86/entry/vdso/vdso32/sigreturn.o
CC arch/x86/lib/usercopy.o
CC arch/x86/entry/vdso/vdso32/vclock_gettime.o
CC lib/crypto/des.o
CC lib/crypto/sha1.o
CC net/ethernet/eth.o
CC crypto/scatterwalk.o
CC drivers/acpi/acpica/dsdebug.o
CC drivers/acpi/acpica/dsfield.o
CC arch/x86/platform/efi/efi_64.o
CC init/init_task.o
CC arch/x86/kernel/fpu/signal.o
AS arch/x86/platform/efi/efi_stub_64.o
LD [M] arch/x86/crypto/ghash-clmulni-intel.o
CC kernel/locking/semaphore.o
CC [M] sound/pci/hda/hda_sysfs.o
LD [M] arch/x86/crypto/crc32-pclmul.o
CC [M] sound/pci/hda/hda_controller.o
AR lib/kunit/built-in.a
AR drivers/pinctrl/intel/built-in.a
LD [M] arch/x86/crypto/crct10dif-pclmul.o
CC kernel/locking/rwsem.o
AR drivers/pinctrl/mvebu/built-in.a
AR arch/x86/crypto/built-in.a
AR drivers/pci/msi/built-in.a
CC arch/x86/lib/usercopy_64.o
CC security/keys/request_key.o
AR drivers/pinctrl/nomadik/built-in.a
CC arch/x86/events/intel/bts.o
CC arch/x86/pci/acpi.o
CC drivers/pci/pcie/portdrv.o
AR drivers/pinctrl/nuvoton/built-in.a
CC arch/x86/mm/extable.o
AR drivers/pinctrl/sprd/built-in.a
CC lib/zlib_inflate/inftrees.o
AR drivers/pinctrl/sunplus/built-in.a
AR drivers/pinctrl/ti/built-in.a
CC drivers/pinctrl/core.o
CC mm/kasan/quarantine.o
AR arch/x86/events/amd/built-in.a
AR arch/x86/platform/iris/built-in.a
CC arch/x86/platform/intel/iosf_mbi.o
CC block/bio.o
CC lib/zlib_inflate/inflate_syms.o
CC arch/x86/lib/msr-smp.o
CC drivers/acpi/apei/bert.o
AR sound/pci/korg1212/built-in.a
CC arch/x86/events/zhaoxin/core.o
AR sound/pci/mixart/built-in.a
AR arch/x86/platform/intel-mid/built-in.a
CC arch/x86/events/core.o
CC drivers/acpi/apei/ghes.o
AR arch/x86/platform/intel-quark/built-in.a
CC sound/core/seq/seq_fifo.o
CC kernel/locking/percpu-rwsem.o
AR drivers/video/console/built-in.a
CC drivers/video/logo/logo.o
HOSTCC drivers/video/logo/pnmtologo
CC drivers/acpi/acpica/dsinit.o
CC crypto/proc.o
CC arch/x86/entry/vdso/vdso32/vgetcpu.o
CC fs/notify/fanotify/fanotify_user.o
CC arch/x86/lib/cache-smp.o
AR drivers/idle/built-in.a
CC security/device_cgroup.o
VDSO arch/x86/entry/vdso/vdso64.so.dbg
CC security/keys/request_key_auth.o
CC drivers/gpio/gpiolib-devres.o
CC security/keys/user_defined.o
CC net/core/request_sock.o
VDSO arch/x86/entry/vdso/vdso32.so.dbg
CC security/keys/compat.o
OBJCOPY arch/x86/entry/vdso/vdso64.so
CC init/version.o
OBJCOPY arch/x86/entry/vdso/vdso32.so
VDSO2C arch/x86/entry/vdso/vdso-image-64.c
VDSO2C arch/x86/entry/vdso/vdso-image-32.c
CC arch/x86/entry/vdso/vdso-image-64.o
AR lib/zlib_inflate/built-in.a
CC lib/crypto/sha256.o
CC lib/zlib_deflate/deflate.o
CC arch/x86/lib/msr.o
CC lib/zlib_deflate/deftree.o
CC security/keys/proc.o
CC security/keys/sysctl.o
CC lib/zlib_deflate/deflate_syms.o
CC drivers/pinctrl/pinctrl-utils.o
AR arch/x86/platform/efi/built-in.a
CC kernel/locking/irqflag-debug.o
CC arch/x86/pci/legacy.o
LOGO drivers/video/logo/logo_linux_clut224.c
CC drivers/video/logo/logo_linux_clut224.o
CC arch/x86/kernel/fpu/xstate.o
CC drivers/pci/pcie/rcec.o
CC arch/x86/mm/mmap.o
CC arch/x86/pci/irq.o
CC arch/x86/entry/vdso/vdso-image-32.o
CC drivers/acpi/acpica/dsmethod.o
CC fs/notify/fsnotify.o
AR drivers/video/logo/built-in.a
AR init/built-in.a
CC drivers/video/backlight/backlight.o
CC arch/x86/events/intel/ds.o
CC [M] arch/x86/kvm/../../../virt/kvm/eventfd.o
AR mm/kasan/built-in.a
CC drivers/acpi/acpica/dsmthdat.o
AR arch/x86/platform/intel/built-in.a
CC [M] arch/x86/kvm/../../../virt/kvm/binary_stats.o
AR arch/x86/platform/olpc/built-in.a
AR arch/x86/platform/scx200/built-in.a
CC crypto/aead.o
AR arch/x86/platform/ts5500/built-in.a
AR arch/x86/platform/uv/built-in.a
AR arch/x86/platform/built-in.a
CC drivers/pnp/pnpacpi/core.o
CC drivers/pnp/pnpacpi/rsparser.o
CC sound/core/seq/seq_prioq.o
CC drivers/pnp/core.o
CC crypto/geniv.o
AR arch/x86/entry/vdso/built-in.a
AR net/ethernet/built-in.a
AS arch/x86/entry/entry_64.o
CC fs/notify/notification.o
AR arch/x86/events/zhaoxin/built-in.a
CC arch/x86/mm/pgtable.o
CC drivers/gpio/gpiolib-legacy.o
CC kernel/locking/mutex-debug.o
CC arch/x86/entry/syscall_64.o
CC [M] lib/crypto/arc4.o
AS arch/x86/lib/msr-reg.o
CC kernel/locking/lockdep.o
CC drivers/pinctrl/pinmux.o
CC kernel/locking/lockdep_proc.o
CC drivers/acpi/acpica/dsobject.o
AR security/keys/built-in.a
CC drivers/acpi/acpica/dsopcode.o
CC arch/x86/entry/common.o
CC [M] arch/x86/kvm/../../../virt/kvm/vfio.o
CC drivers/gpio/gpiolib-cdev.o
CC sound/core/seq/seq_timer.o
CC sound/core/seq/seq_system.o
CC sound/core/seq/seq_ports.o
CC [M] sound/pci/hda/hda_proc.o
CC net/core/skbuff.o
CC arch/x86/lib/msr-reg-export.o
CC [M] arch/x86/kvm/../../../virt/kvm/coalesced_mmio.o
CC drivers/pci/pcie/aspm.o
AR drivers/acpi/apei/built-in.a
AS arch/x86/entry/thunk_64.o
CC net/802/p8022.o
AS arch/x86/lib/hweight.o
CC arch/x86/lib/iomem.o
AR lib/zlib_deflate/built-in.a
CC net/802/psnap.o
AR lib/crypto/built-in.a
LD [M] lib/crypto/libarc4.o
CC net/sched/sch_generic.o
CC io_uring/xattr.o
CC lib/lzo/lzo1x_compress.o
CC io_uring/nop.o
CC net/sched/sch_mq.o
CC lib/lzo/lzo1x_decompress_safe.o
CC io_uring/fs.o
CC lib/lz4/lz4_compress.o
CC [M] arch/x86/kvm/../../../virt/kvm/async_pf.o
CC [M] arch/x86/kvm/../../../virt/kvm/irqchip.o
AR security/built-in.a
AR drivers/video/backlight/built-in.a
CC net/sched/sch_frag.o
CC drivers/video/fbdev/core/fb_notify.o
CC net/sched/sch_api.o
CC [M] arch/x86/kvm/../../../virt/kvm/dirty_ring.o
CC mm/oom_kill.o
CC crypto/skcipher.o
CC drivers/acpi/acpica/dspkginit.o
CC lib/zstd/zstd_compress_module.o
AR fs/notify/fanotify/built-in.a
CC fs/notify/group.o
AR drivers/pnp/pnpacpi/built-in.a
CC drivers/pnp/card.o
CC mm/fadvise.o
AS arch/x86/lib/iomap_copy_64.o
CC block/elevator.o
CC arch/x86/lib/inat.o
CC drivers/pinctrl/pinconf.o
AS arch/x86/entry/entry_64_compat.o
CC arch/x86/pci/common.o
CC arch/x86/mm/physaddr.o
AR arch/x86/kernel/fpu/built-in.a
CC arch/x86/entry/syscall_32.o
CC arch/x86/kernel/cpu/mce/core.o
CC arch/x86/kernel/cpu/mce/severity.o
CC arch/x86/kernel/cpu/mce/genpool.o
AR arch/x86/lib/built-in.a
AR arch/x86/lib/lib.a
CC arch/x86/kernel/cpu/mce/intel.o
CC arch/x86/kernel/cpu/mtrr/mtrr.o
AR lib/lzo/built-in.a
CC arch/x86/kernel/cpu/cacheinfo.o
CC arch/x86/kernel/cpu/mtrr/if.o
CC block/blk-core.o
CC sound/core/seq/seq_info.o
CC arch/x86/kernel/cpu/mce/threshold.o
CC kernel/locking/spinlock.o
AR drivers/acpi/pmic/built-in.a
CC arch/x86/events/probe.o
CC net/sched/sch_blackhole.o
CC drivers/acpi/acpica/dsutils.o
CC lib/zstd/compress/fse_compress.o
CC net/802/stp.o
CC arch/x86/pci/early.o
CC [M] sound/pci/hda/hda_hwdep.o
CC [M] drivers/video/fbdev/core/fbmem.o
CC io_uring/splice.o
CC arch/x86/mm/tlb.o
CC arch/x86/events/intel/knc.o
CC fs/notify/mark.o
CC drivers/acpi/dptf/int340x_thermal.o
CC drivers/pinctrl/pinconf-generic.o
CC drivers/pci/pcie/aer.o
CC drivers/pci/pcie/err.o
CC drivers/pnp/driver.o
CC io_uring/sync.o
CC fs/notify/fdinfo.o
CC arch/x86/events/intel/lbr.o
CC mm/maccess.o
CC arch/x86/events/intel/p4.o
AR arch/x86/entry/built-in.a
CC drivers/acpi/tables.o
CC [M] arch/x86/kvm/../../../virt/kvm/pfncache.o
AR sound/core/seq/built-in.a
CC sound/core/sound.o
CC lib/zstd/compress/hist.o
CC mm/page-writeback.o
CC kernel/locking/osq_lock.o
CC drivers/acpi/blacklist.o
CC block/blk-sysfs.o
CC block/blk-flush.o
CC drivers/acpi/acpica/dswexec.o
CC block/blk-settings.o
CC lib/zstd/compress/huf_compress.o
CC arch/x86/kernel/cpu/mtrr/generic.o
CC drivers/gpio/gpiolib-sysfs.o
CC arch/x86/pci/bus_numa.o
CC crypto/seqiv.o
CC [M] sound/pci/hda/hda_generic.o
CC arch/x86/kernel/cpu/mtrr/cleanup.o
CC [M] sound/pci/hda/patch_realtek.o
CC drivers/acpi/osi.o
CC drivers/pci/pcie/aer_inject.o
AR drivers/acpi/dptf/built-in.a
CC io_uring/advise.o
CC crypto/echainiv.o
AR net/802/built-in.a
CC arch/x86/mm/cpu_entry_area.o
CC drivers/pnp/resource.o
AR drivers/pinctrl/built-in.a
CC drivers/pnp/manager.o
CC drivers/acpi/acpica/dswload.o
CC drivers/gpio/gpiolib-acpi.o
CC lib/zstd/compress/zstd_compress.o
CC arch/x86/kernel/cpu/scattered.o
CC lib/lz4/lz4hc_compress.o
AR sound/pci/nm256/built-in.a
CC drivers/gpio/gpiolib-swnode.o
AR sound/pci/oxygen/built-in.a
CC arch/x86/kernel/cpu/topology.o
CC drivers/acpi/osl.o
CC arch/x86/kernel/cpu/common.o
CC sound/core/init.o
CC arch/x86/kernel/cpu/rdrand.o
CC lib/xz/xz_dec_syms.o
CC [M] arch/x86/kvm/x86.o
AR fs/notify/built-in.a
CC fs/nfs_common/grace.o
CC drivers/acpi/utils.o
CC arch/x86/events/utils.o
CC kernel/locking/qspinlock.o
CC arch/x86/pci/amd_bus.o
CC drivers/acpi/reboot.o
CC drivers/acpi/acpica/dswload2.o
CC drivers/acpi/nvs.o
CC arch/x86/mm/maccess.o
CC net/sched/sch_fifo.o
CC drivers/acpi/acpica/dswscope.o
CC io_uring/filetable.o
CC lib/xz/xz_dec_stream.o
CC io_uring/openclose.o
CC [M] drivers/video/fbdev/core/fbmon.o
CC arch/x86/kernel/cpu/mce/apei.o
CC crypto/ahash.o
CC arch/x86/kernel/cpu/match.o
CC io_uring/uring_cmd.o
CC lib/xz/xz_dec_lzma2.o
CC arch/x86/mm/pgprot.o
CC lib/xz/xz_dec_bcj.o
CC io_uring/epoll.o
CC arch/x86/kernel/cpu/bugs.o
CC lib/lz4/lz4_decompress.o
CC [M] drivers/video/fbdev/core/fbcmap.o
CC arch/x86/events/intel/p6.o
CC drivers/pci/pcie/pme.o
CC sound/core/memory.o
CC lib/zstd/compress/zstd_compress_literals.o
CC lib/zstd/compress/zstd_compress_sequences.o
CC net/netlink/af_netlink.o
CC net/netlink/genetlink.o
AR arch/x86/kernel/cpu/mtrr/built-in.a
CC crypto/shash.o
CC crypto/akcipher.o
CC drivers/acpi/acpica/dswstate.o
CC drivers/acpi/acpica/evevent.o
CC drivers/pnp/support.o
CC drivers/pnp/interface.o
CC arch/x86/mm/hugetlbpage.o
CC sound/core/control.o
CC drivers/acpi/acpica/evgpe.o
AR fs/nfs_common/built-in.a
CC fs/iomap/trace.o
CC arch/x86/events/rapl.o
CC arch/x86/mm/kasan_init_64.o
AR drivers/gpio/built-in.a
CC fs/iomap/iter.o
AR fs/quota/built-in.a
CC kernel/locking/rtmutex_api.o
CC drivers/pnp/quirks.o
CC arch/x86/events/intel/pt.o
CC drivers/video/aperture.o
AR arch/x86/pci/built-in.a
AR drivers/video/fbdev/omap/built-in.a
AR kernel/sched/built-in.a
CC block/blk-ioc.o
CC drivers/video/cmdline.o
AR arch/x86/kernel/cpu/mce/built-in.a
CC fs/iomap/buffered-io.o
AR drivers/amba/built-in.a
CC arch/x86/kernel/cpu/aperfmperf.o
CC arch/x86/mm/pkeys.o
AR drivers/clk/actions/built-in.a
CC block/blk-map.o
AR drivers/clk/analogbits/built-in.a
AR drivers/clk/bcm/built-in.a
AR drivers/clk/imgtec/built-in.a
AR drivers/clk/imx/built-in.a
AR drivers/clk/ingenic/built-in.a
AR drivers/clk/mediatek/built-in.a
AR drivers/clk/microchip/built-in.a
CC io_uring/statx.o
AR drivers/clk/mstar/built-in.a
AR drivers/clk/mvebu/built-in.a
AR lib/xz/built-in.a
AR drivers/clk/ralink/built-in.a
CC drivers/acpi/wakeup.o
CC fs/iomap/direct-io.o
CC fs/proc/task_mmu.o
AR drivers/clk/renesas/built-in.a
AR drivers/clk/socfpga/built-in.a
AR net/sched/built-in.a
CC lib/zstd/compress/zstd_compress_superblock.o
AR drivers/clk/sprd/built-in.a
CC drivers/pci/pcie/dpc.o
AR drivers/clk/sunxi-ng/built-in.a
CC lib/raid6/algos.o
AR drivers/clk/ti/built-in.a
CC drivers/acpi/sleep.o
AR drivers/clk/versatile/built-in.a
CC lib/raid6/recov.o
CC drivers/clk/x86/clk-lpss-atom.o
HOSTCC lib/raid6/mktables
CC block/blk-merge.o
CC crypto/kpp.o
CC io_uring/net.o
CC arch/x86/kernel/cpu/cpuid-deps.o
CC drivers/acpi/acpica/evgpeblk.o
CC lib/fonts/fonts.o
CC [M] drivers/video/fbdev/core/fbsysfs.o
CC drivers/pnp/system.o
CC lib/fonts/font_8x8.o
AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a
CC lib/zstd/compress/zstd_double_fast.o
AR lib/lz4/built-in.a
AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a
CC mm/folio-compat.o
UNROLL lib/raid6/int1.c
AR drivers/video/fbdev/omap2/omapfb/built-in.a
CC lib/argv_split.o
AR drivers/video/fbdev/omap2/built-in.a
CC net/core/datagram.o
CC net/core/stream.o
CC mm/readahead.o
CC crypto/acompress.o
CC [M] drivers/video/fbdev/uvesafb.o
CC [M] drivers/video/fbdev/core/modedb.o
CC net/core/scm.o
CC net/core/gen_stats.o
CC arch/x86/mm/pti.o
CC drivers/clk/x86/clk-pmc-atom.o
CC lib/fonts/font_8x16.o
CC block/blk-timeout.o
CC [M] drivers/video/fbdev/core/fbcvt.o
CC drivers/acpi/acpica/evgpeinit.o
CC arch/x86/events/msr.o
CC drivers/acpi/acpica/evgpeutil.o
CC drivers/acpi/acpica/evglock.o
CC drivers/acpi/device_sysfs.o
CC drivers/acpi/device_pm.o
CC arch/x86/kernel/cpu/umwait.o
CC arch/x86/kernel/cpu/proc.o
CC drivers/acpi/proc.o
UNROLL lib/raid6/int2.c
UNROLL lib/raid6/int4.c
UNROLL lib/raid6/int8.c
UNROLL lib/raid6/int16.c
UNROLL lib/raid6/int32.c
CC lib/raid6/recov_ssse3.o
AR drivers/pnp/built-in.a
CC lib/raid6/recov_avx2.o
CC drivers/acpi/acpica/evhandler.o
CC kernel/locking/spinlock_debug.o
AR drivers/pci/pcie/built-in.a
CC drivers/pci/hotplug/pci_hotplug_core.o
CC drivers/pci/hotplug/acpi_pcihp.o
CC drivers/pci/hotplug/pciehp_core.o
AR net/bpf/built-in.a
AR lib/fonts/built-in.a
CC lib/bug.o
CC kernel/power/qos.o
CC kernel/power/main.o
CC drivers/acpi/acpica/evmisc.o
CC arch/x86/events/intel/uncore.o
AR drivers/clk/x86/built-in.a
CC drivers/acpi/bus.o
AR drivers/clk/xilinx/built-in.a
CC drivers/clk/clk-devres.o
CC drivers/dma/dw/core.o
AR drivers/soc/apple/built-in.a
CC drivers/acpi/glue.o
AR drivers/soc/aspeed/built-in.a
CC drivers/acpi/scan.o
CC drivers/acpi/acpica/evregion.o
CC crypto/scompress.o
AR drivers/soc/bcm/bcm63xx/built-in.a
AR drivers/soc/bcm/built-in.a
CC drivers/acpi/resource.o
AR drivers/soc/fsl/built-in.a
CC kernel/locking/qrwlock.o
AR drivers/soc/fujitsu/built-in.a
CC mm/swap.o
AR drivers/soc/imx/built-in.a
CC drivers/acpi/acpica/evrgnini.o
AR drivers/soc/ixp4xx/built-in.a
AR drivers/soc/loongson/built-in.a
AR arch/x86/mm/built-in.a
AR drivers/soc/mediatek/built-in.a
CC [M] sound/pci/hda/patch_analog.o
AR drivers/soc/microchip/built-in.a
AR drivers/soc/nuvoton/built-in.a
AR drivers/soc/pxa/built-in.a
AR drivers/soc/amlogic/built-in.a
CC drivers/acpi/acpica/evsci.o
AR drivers/soc/qcom/built-in.a
CC drivers/dma/dw/dw.o
AR drivers/soc/renesas/built-in.a
AR drivers/soc/rockchip/built-in.a
CC drivers/dma/dw/idma32.o
CC lib/raid6/mmx.o
AR drivers/soc/sifive/built-in.a
CC block/blk-lib.o
AR drivers/soc/sunxi/built-in.a
CC arch/x86/events/intel/uncore_nhmex.o
AR drivers/soc/ti/built-in.a
MKCAP arch/x86/kernel/cpu/capflags.c
CC sound/core/misc.o
CC lib/raid6/sse1.o
AR drivers/soc/xilinx/built-in.a
CC [M] drivers/video/fbdev/core/fb_cmdline.o
AR drivers/soc/built-in.a
CC lib/raid6/sse2.o
CC block/blk-mq.o
CC [M] drivers/video/fbdev/simplefb.o
CC block/blk-mq-tag.o
CC drivers/acpi/acpica/evxface.o
CC sound/core/device.o
CC block/blk-stat.o
CC block/blk-mq-sysfs.o
CC drivers/clk/clk-bulk.o
CC drivers/clk/clkdev.o
CC drivers/clk/clk.o
CC [M] arch/x86/kvm/emulate.o
CC arch/x86/kernel/acpi/boot.o
AR kernel/locking/built-in.a
CC drivers/pci/hotplug/pciehp_ctrl.o
CC net/core/gen_estimator.o
CC drivers/pci/hotplug/pciehp_pci.o
CC fs/proc/inode.o
CC fs/proc/root.o
CC drivers/pci/hotplug/pciehp_hpc.o
CC kernel/printk/printk.o
CC fs/iomap/fiemap.o
CC net/core/net_namespace.o
CC mm/truncate.o
CC sound/core/info.o
CC crypto/algboss.o
CC drivers/acpi/acpi_processor.o
CC drivers/dma/dw/acpi.o
CC drivers/acpi/acpica/evxfevnt.o
CC kernel/power/console.o
CC io_uring/msg_ring.o
CC fs/proc/base.o
CC drivers/acpi/processor_core.o
CC net/core/secure_seq.o
CC net/core/flow_dissector.o
CC [M] arch/x86/kvm/i8259.o
CC kernel/power/process.o
CC crypto/testmgr.o
CC [M] sound/pci/hda/patch_hdmi.o
CC drivers/dma/dw/pci.o
CC drivers/virtio/virtio.o
CC [M] drivers/video/fbdev/core/fb_defio.o
CC lib/raid6/avx2.o
CC drivers/virtio/virtio_ring.o
CC kernel/irq/irqdesc.o
CC drivers/pci/hotplug/acpiphp_core.o
CC kernel/rcu/update.o
CC kernel/irq/handle.o
CC kernel/rcu/sync.o
CC lib/buildid.o
CC lib/cmdline.o
CC fs/iomap/seek.o
CC drivers/acpi/acpica/evxfgpe.o
CC net/netlink/policy.o
CC drivers/virtio/virtio_anchor.o
CC drivers/acpi/acpica/evxfregn.o
CC drivers/acpi/acpica/exconcat.o
CC drivers/acpi/processor_pdc.o
AR sound/pci/pcxhr/built-in.a
AR sound/pci/riptide/built-in.a
AR sound/pci/rme9652/built-in.a
AR kernel/livepatch/built-in.a
CC drivers/acpi/ec.o
CC kernel/dma/mapping.o
CC kernel/dma/direct.o
CC drivers/virtio/virtio_pci_modern_dev.o
CC kernel/power/suspend.o
CC kernel/power/hibernate.o
CC net/core/sysctl_net_core.o
CC arch/x86/events/intel/uncore_snb.o
CC sound/core/isadma.o
AR drivers/dma/dw/built-in.a
CC drivers/dma/hsu/hsu.o
CC arch/x86/kernel/acpi/sleep.o
AS arch/x86/kernel/acpi/wakeup_64.o
CC lib/raid6/avx512.o
CC drivers/acpi/dock.o
CC drivers/pci/hotplug/acpiphp_glue.o
CC net/core/dev.o
CC drivers/acpi/pci_root.o
CC drivers/acpi/acpica/exconfig.o
CC drivers/virtio/virtio_pci_legacy_dev.o
CC net/core/dev_addr_lists.o
CC sound/core/vmaster.o
CC [M] sound/pci/hda/hda_eld.o
CC io_uring/timeout.o
CC [M] drivers/video/fbdev/core/fbcon.o
CC io_uring/sqpoll.o
CC fs/iomap/swapfile.o
CC drivers/virtio/virtio_pci_modern.o
CC drivers/tty/vt/vt_ioctl.o
CC drivers/char/hw_random/core.o
CC kernel/irq/manage.o
CC kernel/power/snapshot.o
CC kernel/power/swap.o
CC mm/vmscan.o
CC drivers/char/hw_random/intel-rng.o
CC net/netlink/diag.o
CC drivers/tty/vt/vc_screen.o
CC crypto/cmac.o
CC drivers/acpi/acpica/exconvrt.o
CC net/ethtool/ioctl.o
CC arch/x86/kernel/acpi/apei.o
CC net/ethtool/common.o
CC net/ethtool/netlink.o
CC lib/raid6/recov_avx512.o
CC sound/core/ctljack.o
AR drivers/iommu/amd/built-in.a
CC drivers/iommu/intel/dmar.o
CC kernel/dma/ops_helpers.o
CC arch/x86/events/intel/uncore_snbep.o
AR drivers/dma/hsu/built-in.a
AR drivers/dma/idxd/built-in.a
AR drivers/dma/mediatek/built-in.a
AR drivers/dma/qcom/built-in.a
AR drivers/dma/ti/built-in.a
AR drivers/dma/xilinx/built-in.a
AR fs/iomap/built-in.a
CC [M] drivers/dma/ioat/init.o
CC drivers/iommu/intel/iommu.o
CC [M] drivers/dma/ioat/dma.o
CC drivers/virtio/virtio_pci_common.o
CC kernel/power/user.o
CC kernel/rcu/srcutree.o
CC kernel/printk/printk_safe.o
CC kernel/printk/printk_ringbuffer.o
CC drivers/iommu/intel/pasid.o
CC kernel/power/poweroff.o
AR drivers/char/hw_random/built-in.a
CC [M] drivers/dma/ioat/prep.o
CC drivers/char/agp/backend.o
CC drivers/char/agp/generic.o
AR drivers/iommu/arm/arm-smmu/built-in.a
CC drivers/acpi/acpica/excreate.o
AR drivers/iommu/arm/arm-smmu-v3/built-in.a
AR drivers/iommu/arm/built-in.a
CC net/core/dst.o
AR drivers/pci/hotplug/built-in.a
AR drivers/pci/controller/dwc/built-in.a
AR drivers/pci/controller/mobiveil/built-in.a
CC sound/core/jack.o
CC drivers/pci/controller/vmd.o
TABLE lib/raid6/tables.c
AR drivers/gpu/host1x/built-in.a
CC lib/raid6/int1.o
AR drivers/gpu/drm/tests/built-in.a
CC io_uring/fdinfo.o
CC [M] drivers/gpu/drm/tests/drm_kunit_helpers.o
CC [M] drivers/gpu/drm/tests/drm_buddy_test.o
CC drivers/tty/hvc/hvc_console.o
AR drivers/gpu/vga/built-in.a
CC drivers/acpi/pci_link.o
CC drivers/acpi/pci_irq.o
CC arch/x86/kernel/acpi/cppc.o
CC lib/raid6/int2.o
CC drivers/tty/vt/selection.o
CC kernel/dma/dummy.o
AR net/netlink/built-in.a
AR drivers/pci/switch/built-in.a
CC fs/proc/generic.o
CC [M] sound/pci/hda/hda_intel.o
CC drivers/char/agp/isoch.o
CC drivers/char/agp/intel-agp.o
CC drivers/acpi/acpica/exdebug.o
CC crypto/hmac.o
CC lib/zstd/compress/zstd_fast.o
AR drivers/iommu/iommufd/built-in.a
CC drivers/pci/access.o
CC kernel/printk/sysctl.o
CC lib/zstd/compress/zstd_lazy.o
CC drivers/pci/bus.o
CC kernel/irq/spurious.o
CC drivers/pci/probe.o
AR kernel/power/built-in.a
CC lib/zstd/compress/zstd_ldm.o
CC drivers/tty/vt/keyboard.o
CC drivers/virtio/virtio_pci_legacy.o
CC arch/x86/kernel/acpi/cstate.o
CC sound/core/timer.o
CC crypto/vmac.o
AR kernel/printk/built-in.a
CC sound/core/hrtimer.o
CC arch/x86/kernel/cpu/powerflags.o
CC kernel/dma/contiguous.o
CC drivers/acpi/acpica/exdump.o
LD [M] sound/pci/hda/snd-hda-codec.o
CC lib/raid6/int4.o
CC drivers/clk/clk-divider.o
LD [M] sound/pci/hda/snd-hda-codec-generic.o
CC [M] net/netfilter/ipvs/ip_vs_conn.o
CC [M] drivers/dma/ioat/dca.o
CC [M] drivers/dma/ioat/sysfs.o
CC arch/x86/kernel/cpu/feat_ctl.o
CC drivers/acpi/acpi_lpss.o
CC [M] net/netfilter/ipvs/ip_vs_core.o
CC [M] net/netfilter/ipvs/ip_vs_ctl.o
CC [M] drivers/video/fbdev/core/bitblit.o
CC net/netfilter/core.o
CC kernel/rcu/tree.o
CC drivers/tty/vt/consolemap.o
CC block/blk-mq-cpumap.o
AR drivers/tty/hvc/built-in.a
CC block/blk-mq-sched.o
CC [M] drivers/virtio/virtio_mem.o
CC block/ioctl.o
AR drivers/pci/controller/built-in.a
CC lib/cpumask.o
CC kernel/rcu/rcu_segcblist.o
CC kernel/irq/resend.o
CC fs/proc/array.o
CC fs/proc/fd.o
CC lib/ctype.o
CC [M] drivers/gpu/drm/tests/drm_cmdline_parser_test.o
CC drivers/acpi/acpica/exfield.o
CC io_uring/tctx.o
CC io_uring/poll.o
CC drivers/char/agp/intel-gtt.o
CC drivers/acpi/acpica/exfldio.o
CC [M] drivers/video/fbdev/core/softcursor.o
AR arch/x86/kernel/acpi/built-in.a
CC [M] net/netfilter/ipvs/ip_vs_sched.o
CC net/core/netevent.o
CC io_uring/cancel.o
CC arch/x86/kernel/cpu/intel.o
CC kernel/dma/swiotlb.o
CC [M] arch/x86/kvm/irq.o
CC drivers/iommu/intel/trace.o
CC lib/raid6/int8.o
CC crypto/xcbc.o
CC drivers/clk/clk-fixed-factor.o
CC drivers/clk/clk-fixed-rate.o
LD [M] drivers/dma/ioat/ioatdma.o
CC kernel/irq/chip.o
CC drivers/acpi/acpica/exmisc.o
CC arch/x86/kernel/apic/apic.o
CC drivers/dma/dmaengine.o
CC fs/proc/proc_tty.o
CC arch/x86/events/intel/uncore_discovery.o
CC drivers/acpi/acpica/exmutex.o
CC arch/x86/kernel/kprobes/core.o
CC net/ethtool/bitset.o
CC arch/x86/kernel/kprobes/opt.o
CC [M] drivers/video/fbdev/core/tileblit.o
LD [M] sound/pci/hda/snd-hda-codec-realtek.o
CC kernel/dma/remap.o
LD [M] sound/pci/hda/snd-hda-codec-analog.o
LD [M] sound/pci/hda/snd-hda-codec-hdmi.o
CC arch/x86/kernel/kprobes/ftrace.o
LD [M] sound/pci/hda/snd-hda-intel.o
CC lib/dec_and_lock.o
AR sound/pci/trident/built-in.a
CC [M] drivers/video/fbdev/core/cfbfillrect.o
AR sound/pci/ymfpci/built-in.a
CC io_uring/kbuf.o
AR sound/pci/vx222/built-in.a
AR sound/pci/built-in.a
CC net/ethtool/strset.o
CC block/genhd.o
CC net/ethtool/linkinfo.o
CC net/ethtool/linkmodes.o
CC drivers/acpi/acpica/exnames.o
CC crypto/crypto_null.o
CC drivers/clk/clk-gate.o
CC net/core/neighbour.o
HOSTCC drivers/tty/vt/conmakehash
CC lib/decompress.o
AR drivers/char/agp/built-in.a
CC lib/raid6/int16.o
CC drivers/pci/host-bridge.o
CC drivers/pci/remove.o
CC drivers/char/tpm/tpm-chip.o
CC fs/proc/cmdline.o
CC sound/core/seq_device.o
CC drivers/char/tpm/tpm-dev-common.o
CC lib/raid6/int32.o
CC lib/decompress_bunzip2.o
CC arch/x86/events/intel/cstate.o
CC drivers/char/tpm/tpm-dev.o
CC net/netfilter/nf_log.o
CC drivers/char/tpm/tpm-interface.o
CC drivers/tty/vt/vt.o
CC arch/x86/kernel/cpu/intel_pconfig.o
COPY drivers/tty/vt/defkeymap.c
CC kernel/irq/dummychip.o
AR kernel/dma/built-in.a
CC fs/proc/consoles.o
CC drivers/acpi/acpica/exoparg1.o
CC kernel/entry/common.o
CC drivers/clk/clk-multiplier.o
CC arch/x86/kernel/cpu/tsx.o
CC kernel/module/main.o
CC crypto/md5.o
CC kernel/module/strict_rwx.o
CC kernel/irq/devres.o
LDS arch/x86/kernel/vmlinux.lds
CC drivers/clk/clk-mux.o
AS arch/x86/kernel/head_64.o
CC kernel/irq/autoprobe.o
CC drivers/iommu/intel/cap_audit.o
AR arch/x86/kernel/kprobes/built-in.a
CC kernel/entry/syscall_user_dispatch.o
AR drivers/virtio/built-in.a
CC kernel/entry/kvm.o
CC [M] drivers/gpu/drm/tests/drm_connector_test.o
CC drivers/tty/serial/8250/8250_core.o
CC drivers/tty/serial/serial_core.o
CC [M] sound/core/control_led.o
CC [M] drivers/video/fbdev/core/cfbcopyarea.o
CC lib/raid6/tables.o
CC drivers/tty/serial/earlycon.o
CC drivers/pci/pci.o
CC arch/x86/kernel/head64.o
CC drivers/dma/virt-dma.o
CC kernel/module/tree_lookup.o
CC drivers/tty/serial/8250/8250_pnp.o
CC io_uring/rsrc.o
CC drivers/clk/clk-composite.o
CC mm/shmem.o
CC arch/x86/kernel/cpu/intel_epb.o
CC arch/x86/kernel/cpu/amd.o
CC net/ethtool/rss.o
CC fs/proc/cpuinfo.o
AR sound/sparc/built-in.a
CC mm/util.o
CC lib/decompress_inflate.o
AR arch/x86/events/intel/built-in.a
CC drivers/acpi/acpica/exoparg2.o
CC drivers/acpi/acpica/exoparg3.o
AR arch/x86/events/built-in.a
CC arch/x86/kernel/cpu/hygon.o
CC drivers/pci/pci-driver.o
CC arch/x86/kernel/cpu/centaur.o
CC drivers/pci/search.o
CC drivers/char/tpm/tpm1-cmd.o
CC crypto/sha1_generic.o
CC drivers/char/tpm/tpm2-cmd.o
CC arch/x86/kernel/apic/apic_common.o
CC kernel/irq/irqdomain.o
CC net/ethtool/linkstate.o
CC block/ioprio.o
CC [M] drivers/gpu/drm/tests/drm_damage_helper_test.o
CC arch/x86/kernel/apic/apic_noop.o
CC net/netfilter/nf_queue.o
CC drivers/pci/pci-sysfs.o
CC arch/x86/kernel/cpu/zhaoxin.o
CC drivers/tty/serial/8250/8250_port.o
AR lib/raid6/built-in.a
CC kernel/time/time.o
CC kernel/futex/core.o
AR kernel/entry/built-in.a
CC fs/proc/devices.o
CC kernel/cgroup/cgroup.o
CC kernel/time/timer.o
CC fs/proc/interrupts.o
CC [M] sound/core/hwdep.o
CC drivers/acpi/acpica/exoparg6.o
CC drivers/clk/clk-fractional-divider.o
CC fs/proc/loadavg.o
CC drivers/dma/acpi-dma.o
CC lib/decompress_unlz4.o
CC drivers/acpi/acpica/exprep.o
CC drivers/acpi/acpica/exregion.o
CC drivers/clk/clk-gpio.o
CC arch/x86/kernel/apic/ipi.o
CC [M] drivers/video/fbdev/core/cfbimgblt.o
CC drivers/iommu/iommu.o
CC drivers/iommu/intel/irq_remapping.o
CC crypto/sha256_generic.o
CC [M] net/netfilter/ipvs/ip_vs_xmit.o
CC drivers/pci/rom.o
CC kernel/time/hrtimer.o
CC [M] drivers/video/fbdev/core/sysfillrect.o
CC arch/x86/kernel/cpu/perfctr-watchdog.o
CC arch/x86/kernel/cpu/vmware.o
CC arch/x86/kernel/apic/vector.o
CC drivers/char/tpm/tpmrm-dev.o
CC arch/x86/kernel/cpu/hypervisor.o
CC drivers/tty/serial/serial_mctrl_gpio.o
CC kernel/futex/syscalls.o
CC block/badblocks.o
CC drivers/connector/cn_queue.o
CC drivers/acpi/acpica/exresnte.o
CC drivers/block/loop.o
CC [M] drivers/block/nbd.o
CC drivers/base/power/sysfs.o
CC fs/proc/meminfo.o
CC net/ethtool/debug.o
CC drivers/base/power/generic_ops.o
AR drivers/clk/built-in.a
CC net/ethtool/wol.o
CC crypto/sha512_generic.o
AR drivers/dma/built-in.a
CC crypto/blake2b_generic.o
CC arch/x86/kernel/cpu/mshyperv.o
CC [M] sound/core/pcm.o
CC kernel/irq/proc.o
CC drivers/pci/setup-res.o
AR sound/spi/built-in.a
CC [M] drivers/video/fbdev/core/syscopyarea.o
CC [M] drivers/gpu/drm/tests/drm_dp_mst_helper_test.o
CC [M] drivers/video/fbdev/core/sysimgblt.o
CC kernel/futex/pi.o
CC net/core/rtnetlink.o
CC drivers/acpi/acpica/exresolv.o
CC [M] drivers/gpu/drm/tests/drm_format_helper_test.o
CC [M] drivers/video/fbdev/core/fb_sys_fops.o
CC drivers/char/tpm/tpm2-space.o
CC kernel/time/timekeeping.o
CC drivers/pci/irq.o
CC kernel/irq/migration.o
AR sound/parisc/built-in.a
CC fs/proc/stat.o
CC drivers/base/power/common.o
CC block/blk-rq-qos.o
CC block/disk-events.o
CC kernel/time/ntp.o
CC io_uring/rw.o
CC drivers/acpi/acpica/exresop.o
CC kernel/module/debug_kmemleak.o
CC kernel/futex/requeue.o
CONMK drivers/tty/vt/consolemap_deftbl.c
CC drivers/tty/vt/defkeymap.o
CC [M] sound/core/pcm_native.o
CC drivers/acpi/acpica/exserial.o
CC drivers/iommu/intel/perfmon.o
CC drivers/connector/connector.o
CC drivers/acpi/acpica/exstore.o
CC arch/x86/kernel/cpu/capflags.o
CC drivers/tty/vt/consolemap_deftbl.o
CC kernel/futex/waitwake.o
AR arch/x86/kernel/cpu/built-in.a
CC arch/x86/kernel/ebda.o
CC kernel/irq/cpuhotplug.o
CC net/ethtool/features.o
CC arch/x86/kernel/platform-quirks.o
CC arch/x86/kernel/process_64.o
AR drivers/tty/vt/built-in.a
CC crypto/ecb.o
CC drivers/pci/vpd.o
CC crypto/cbc.o
CC drivers/pci/setup-bus.o
CC drivers/acpi/acpica/exstoren.o
CC drivers/base/power/qos.o
CC [M] sound/core/pcm_lib.o
CC drivers/acpi/acpica/exstorob.o
CC kernel/module/kallsyms.o
CC arch/x86/kernel/apic/hw_nmi.o
CC fs/proc/uptime.o
CC drivers/base/power/runtime.o
CC arch/x86/kernel/signal.o
CC drivers/tty/serial/8250/8250_dma.o
LD [M] drivers/video/fbdev/core/fb.o
CC [M] drivers/gpu/drm/tests/drm_format_test.o
CC kernel/irq/pm.o
CC kernel/irq/msi.o
AR drivers/video/fbdev/core/built-in.a
CC arch/x86/kernel/signal_64.o
AR drivers/video/fbdev/built-in.a
CC drivers/video/nomodeset.o
AR kernel/rcu/built-in.a
CC drivers/char/tpm/tpm-sysfs.o
CC drivers/iommu/iommu-traces.o
CC [M] arch/x86/kvm/lapic.o
CC drivers/iommu/iommu-sysfs.o
CC block/blk-ia-ranges.o
CC block/bsg.o
CC drivers/char/tpm/eventlog/common.o
CC [M] net/netfilter/ipvs/ip_vs_app.o
CC kernel/trace/trace_clock.o
CC fs/proc/util.o
CC drivers/char/tpm/eventlog/tpm1.o
CC crypto/pcbc.o
CC kernel/module/procfs.o
CC arch/x86/kernel/traps.o
AR kernel/futex/built-in.a
CC drivers/char/tpm/eventlog/tpm2.o
CC arch/x86/kernel/idt.o
CC mm/mmzone.o
CC drivers/acpi/acpica/exsystem.o
CC mm/vmstat.o
CC net/ethtool/privflags.o
CC drivers/video/hdmi.o
CC kernel/trace/ftrace.o
CC arch/x86/kernel/apic/io_apic.o
CC drivers/tty/serial/8250/8250_dwlib.o
CC drivers/pci/vc.o
CC drivers/connector/cn_proc.o
CC drivers/acpi/acpica/extrace.o
CC [M] net/netfilter/ipvs/ip_vs_sync.o
CC kernel/module/sysfs.o
CC fs/proc/version.o
CC arch/x86/kernel/irq.o
CC crypto/cts.o
CC kernel/time/clocksource.o
CC arch/x86/kernel/irq_64.o
CC drivers/iommu/dma-iommu.o
CC kernel/time/jiffies.o
CC drivers/char/tpm/tpm_ppi.o
CC kernel/irq/affinity.o
CC net/ethtool/rings.o
CC kernel/time/timer_list.o
CC block/bsg-lib.o
CC kernel/bpf/core.o
CC crypto/lrw.o
AR drivers/iommu/intel/built-in.a
CC net/core/utils.o
CC net/core/link_watch.o
CC mm/backing-dev.o
CC lib/decompress_unlzma.o
CC io_uring/opdef.o
CC arch/x86/kernel/dumpstack_64.o
CC [M] drivers/gpu/drm/tests/drm_framebuffer_test.o
CC kernel/time/timeconv.o
CC drivers/iommu/ioasid.o
CC kernel/irq/matrix.o
CC drivers/acpi/acpica/exutils.o
CC net/ethtool/channels.o
CC drivers/base/power/wakeirq.o
CC fs/proc/softirqs.o
CC fs/proc/namespaces.o
AR drivers/block/built-in.a
CC drivers/tty/serial/8250/8250_pcilib.o
AR drivers/misc/eeprom/built-in.a
AR drivers/misc/cb710/built-in.a
AR drivers/misc/ti-st/built-in.a
CC drivers/tty/serial/8250/8250_pci.o
AR drivers/misc/lis3lv02d/built-in.a
AR drivers/misc/cardreader/built-in.a
AR drivers/video/built-in.a
CC arch/x86/kernel/time.o
AR drivers/misc/built-in.a
CC drivers/mfd/mfd-core.o
CC [M] drivers/misc/mei/hdcp/mei_hdcp.o
CC [M] drivers/misc/mei/pxp/mei_pxp.o
CC drivers/mfd/intel-lpss.o
CC drivers/pci/mmap.o
CC kernel/time/timecounter.o
CC arch/x86/kernel/apic/msi.o
CC net/core/filter.o
AR kernel/module/built-in.a
CC drivers/iommu/iova.o
CC drivers/pci/setup-irq.o
CC arch/x86/kernel/apic/x2apic_phys.o
CC [M] drivers/gpu/drm/tests/drm_managed_test.o
CC drivers/char/tpm/eventlog/acpi.o
CC [M] drivers/gpu/drm/tests/drm_mm_test.o
CC arch/x86/kernel/ioport.o
CC drivers/char/tpm/eventlog/efi.o
CC drivers/acpi/acpica/hwacpi.o
CC net/ethtool/coalesce.o
CC crypto/xts.o
CC net/ethtool/pause.o
CC block/blk-cgroup.o
CC drivers/mfd/intel-lpss-pci.o
CC drivers/base/power/main.o
CC kernel/time/alarmtimer.o
CC fs/proc/self.o
CC drivers/base/firmware_loader/builtin/main.o
AR drivers/connector/built-in.a
CC drivers/base/firmware_loader/main.o
CC arch/x86/kernel/dumpstack.o
CC net/ethtool/eee.o
CC io_uring/notif.o
CC fs/proc/thread_self.o
CC drivers/pci/proc.o
CC lib/zstd/compress/zstd_opt.o
CC drivers/pci/slot.o
CC [M] net/netfilter/ipvs/ip_vs_est.o
AR drivers/gpu/drm/arm/built-in.a
CC drivers/acpi/acpica/hwesleep.o
CC arch/x86/kernel/apic/x2apic_cluster.o
CC [M] drivers/gpu/drm/tests/drm_modes_test.o
CC [M] drivers/gpu/drm/tests/drm_plane_helper_test.o
AR drivers/base/firmware_loader/builtin/built-in.a
CC net/ethtool/tsinfo.o
CC fs/kernfs/mount.o
CC arch/x86/kernel/nmi.o
CC fs/kernfs/inode.o
CC net/netfilter/nf_sockopt.o
CC arch/x86/kernel/apic/apic_flat_64.o
CC fs/sysfs/file.o
CC arch/x86/kernel/ldt.o
CC drivers/char/tpm/tpm_crb.o
AR drivers/gpu/drm/display/built-in.a
CC [M] drivers/gpu/drm/display/drm_display_helper_mod.o
AR kernel/irq/built-in.a
CC [M] drivers/misc/mei/init.o
CC [M] drivers/misc/mei/hbm.o
CC [M] drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
CC arch/x86/kernel/setup.o
CC drivers/iommu/irq_remapping.o
CC crypto/ctr.o
CC drivers/mfd/intel-lpss-acpi.o
CC mm/mm_init.o
CC [M] net/netfilter/ipvs/ip_vs_proto.o
CC drivers/acpi/acpica/hwgpe.o
CC fs/proc/proc_sysctl.o
CC [M] drivers/misc/mei/interrupt.o
CC [M] sound/core/pcm_misc.o
CC arch/x86/kernel/x86_init.o
CC fs/configfs/inode.o
CC fs/devpts/inode.o
CC drivers/tty/serial/8250/8250_exar.o
CC arch/x86/kernel/apic/probe_64.o
CC [M] drivers/gpu/drm/tests/drm_probe_helper_test.o
CC [M] sound/core/pcm_memory.o
CC arch/x86/kernel/i8259.o
CC [M] net/netfilter/ipvs/ip_vs_pe.o
CC drivers/pci/pci-acpi.o
CC arch/x86/kernel/irqinit.o
CC [M] sound/core/memalloc.o
CC [M] sound/core/pcm_timer.o
AR drivers/base/firmware_loader/built-in.a
CC drivers/pci/quirks.o
CC [M] arch/x86/kvm/i8254.o
CC kernel/time/posix-timers.o
CC drivers/mfd/intel_soc_pmic_crc.o
CC fs/kernfs/dir.o
CC crypto/gcm.o
CC io_uring/io-wq.o
AR arch/x86/kernel/apic/built-in.a
CC lib/zstd/zstd_decompress_module.o
CC drivers/tty/serial/8250/8250_early.o
CC fs/sysfs/dir.o
AR drivers/iommu/built-in.a
CC drivers/base/regmap/regmap.o
CC arch/x86/kernel/jump_label.o
CC drivers/acpi/acpica/hwregs.o
CC kernel/cgroup/rstat.o
CC kernel/cgroup/namespace.o
CC net/ethtool/cabletest.o
CC mm/percpu.o
AR drivers/char/tpm/built-in.a
CC drivers/char/mem.o
CC [M] drivers/gpu/drm/display/drm_dp_helper.o
CC drivers/base/regmap/regcache.o
LD [M] sound/core/snd-ctl-led.o
CC arch/x86/kernel/irq_work.o
CC fs/configfs/file.o
CC mm/slab_common.o
CC fs/configfs/dir.o
CC drivers/base/power/wakeup.o
CC lib/zstd/decompress/huf_decompress.o
CC kernel/cgroup/cgroup-v1.o
CC kernel/time/posix-cpu-timers.o
CC [M] drivers/gpu/drm/tests/drm_rect_test.o
CC kernel/time/posix-clock.o
CC [M] drivers/misc/mei/client.o
AR fs/devpts/built-in.a
CC [M] drivers/misc/mei/main.o
CC fs/ext4/balloc.o
AR kernel/bpf/built-in.a
CC fs/sysfs/symlink.o
CC drivers/pci/ats.o
CC fs/configfs/symlink.o
CC [M] drivers/mfd/lpc_sch.o
CC drivers/acpi/acpica/hwsleep.o
CC drivers/acpi/acpica/hwvalid.o
CC [M] drivers/misc/mei/dma-ring.o
CC kernel/trace/ring_buffer.o
CC drivers/tty/serial/8250/8250_dw.o
CC fs/configfs/mount.o
CC drivers/base/power/wakeup_stats.o
CC block/blk-cgroup-rwstat.o
CC kernel/cgroup/freezer.o
CC kernel/cgroup/legacy_freezer.o
LD [M] sound/core/snd-hwdep.o
LD [M] sound/core/snd-pcm.o
CC [M] net/netfilter/ipvs/ip_vs_proto_tcp.o
AR sound/core/built-in.a
AR sound/pcmcia/vx/built-in.a
CC drivers/base/power/domain.o
CC drivers/pci/iov.o
AR sound/pcmcia/pdaudiocf/built-in.a
AR sound/pcmcia/built-in.a
CC [M] arch/x86/kvm/ioapic.o
AR sound/mips/built-in.a
AR sound/soc/built-in.a
AR sound/atmel/built-in.a
AR sound/hda/built-in.a
CC [M] sound/hda/hda_bus_type.o
CC arch/x86/kernel/probe_roms.o
CC drivers/char/random.o
CC drivers/char/misc.o
CC drivers/pci/pci-label.o
CC crypto/pcrypt.o
CC drivers/acpi/acpica/hwxface.o
CC drivers/pci/pci-stub.o
CC fs/sysfs/mount.o
CC fs/kernfs/file.o
CC kernel/trace/trace.o
CC fs/proc/proc_net.o
CC net/ethtool/tunnels.o
CC drivers/base/power/domain_governor.o
CC fs/configfs/item.o
AR drivers/gpu/drm/rcar-du/built-in.a
CC fs/sysfs/group.o
CC [M] drivers/misc/mei/bus.o
CC kernel/events/core.o
CC [M] drivers/misc/mei/bus-fixup.o
CC [M] drivers/mfd/lpc_ich.o
CC kernel/time/itimer.o
CC block/blk-throttle.o
CC block/mq-deadline.o
AR io_uring/built-in.a
CC block/kyber-iosched.o
CC drivers/acpi/acpica/hwxfsleep.o
AR sound/x86/built-in.a
CC [M] drivers/misc/mei/debugfs.o
CC drivers/base/power/clock_ops.o
CC kernel/trace/trace_output.o
CC kernel/cgroup/pids.o
CC drivers/tty/serial/8250/8250_lpss.o
CC [M] sound/hda/hdac_bus.o
CC block/bfq-iosched.o
CC crypto/cryptd.o
CC block/bfq-wf2q.o
CC crypto/des_generic.o
CC kernel/trace/trace_seq.o
AR fs/configfs/built-in.a
CC drivers/char/virtio_console.o
CC kernel/fork.o
CC kernel/trace/trace_stat.o
CC drivers/pci/vgaarb.o
CC arch/x86/kernel/sys_ia32.o
CC block/bfq-cgroup.o
AR fs/sysfs/built-in.a
CC mm/compaction.o
CC fs/jbd2/transaction.o
CC fs/proc/kcore.o
CC drivers/acpi/acpica/hwpci.o
CC kernel/trace/trace_printk.o
CC fs/ramfs/inode.o
CC kernel/trace/pid_list.o
CC [M] drivers/gpu/drm/display/drm_dp_mst_topology.o
CC fs/kernfs/symlink.o
CC [M] arch/x86/kvm/irq_comm.o
AR drivers/mfd/built-in.a
CC fs/ramfs/file-mmu.o
CC fs/ext4/bitmap.o
CC arch/x86/kernel/signal_32.o
CC [M] drivers/gpu/drm/display/drm_dsc_helper.o
CC [M] net/netfilter/ipvs/ip_vs_proto_udp.o
CC kernel/cgroup/cpuset.o
CC [M] drivers/gpu/drm/display/drm_hdcp_helper.o
CC kernel/trace/trace_sched_switch.o
CC drivers/tty/serial/8250/8250_mid.o
CC [M] drivers/misc/mei/mei-trace.o
CC kernel/time/clockevents.o
AR drivers/nfc/built-in.a
CC net/ethtool/fec.o
CC [M] sound/hda/hdac_device.o
AR drivers/dax/hmem/built-in.a
CC drivers/dax/super.o
CC drivers/acpi/acpica/nsaccess.o
CC kernel/time/tick-common.o
CC [M] net/netfilter/ipvs/ip_vs_nfct.o
CC net/ethtool/eeprom.o
AR drivers/base/power/built-in.a
AR drivers/base/test/built-in.a
CC fs/jbd2/commit.o
CC [M] sound/hda/hdac_sysfs.o
CC crypto/aes_generic.o
CC [M] arch/x86/kvm/cpuid.o
AR fs/kernfs/built-in.a
AR drivers/gpu/drm/omapdrm/built-in.a
AR drivers/gpu/drm/tilcdc/built-in.a
CC block/blk-mq-pci.o
CC crypto/deflate.o
CC mm/interval_tree.o
CC fs/hugetlbfs/inode.o
AR fs/ramfs/built-in.a
CC fs/fat/cache.o
AR drivers/gpu/drm/imx/built-in.a
CC kernel/trace/trace_functions.o
AR drivers/gpu/drm/i2c/built-in.a
CC block/blk-mq-virtio.o
CC fs/ext4/block_validity.o
CC fs/fat/dir.o
CC drivers/base/regmap/regcache-rbtree.o
CC fs/proc/kmsg.o
CC [M] arch/x86/kvm/pmu.o
AR drivers/pci/built-in.a
CC net/ethtool/stats.o
CC drivers/tty/serial/8250/8250_pericom.o
CC [M] arch/x86/kvm/mtrr.o
CC drivers/acpi/acpica/nsalloc.o
CC arch/x86/kernel/sys_x86_64.o
CC mm/list_lru.o
CC fs/ext4/dir.o
CC fs/fat/fatent.o
CC kernel/time/tick-broadcast.o
CC block/blk-mq-debugfs.o
CC [M] drivers/misc/mei/pci-me.o
CC drivers/char/hpet.o
CC drivers/dax/bus.o
CC drivers/base/component.o
CC [M] sound/hda/hdac_regmap.o
CC mm/workingset.o
CC [M] drivers/gpu/drm/display/drm_hdmi_helper.o
CC fs/ext4/ext4_jbd2.o
CC drivers/char/nvram.o
CC drivers/base/core.o
CC drivers/base/bus.o
CC fs/proc/page.o
CC arch/x86/kernel/espfix_64.o
AR sound/xen/built-in.a
CC drivers/acpi/acpica/nsarguments.o
CC drivers/acpi/acpica/nsconvert.o
CC kernel/trace/trace_preemptirq.o
CC crypto/crc32c_generic.o
CC [M] net/netfilter/ipvs/ip_vs_rr.o
CC drivers/base/regmap/regcache-flat.o
AR drivers/tty/serial/8250/built-in.a
CC net/netfilter/utils.o
AR drivers/tty/serial/built-in.a
AR drivers/tty/ipwireless/built-in.a
CC drivers/tty/tty_io.o
CC [M] net/netfilter/nfnetlink.o
CC fs/ext4/extents.o
CC drivers/dma-buf/dma-buf.o
AR net/ipv4/netfilter/built-in.a
CC [M] net/ipv4/netfilter/nf_defrag_ipv4.o
CC net/xfrm/xfrm_policy.o
CC fs/ext4/extents_status.o
CC kernel/time/tick-broadcast-hrtimer.o
CC [M] drivers/misc/mei/hw-me.o
CC [M] net/ipv4/netfilter/nf_reject_ipv4.o
CC drivers/acpi/acpica/nsdump.o
CC drivers/dma-buf/dma-fence.o
CC crypto/crct10dif_common.o
CC [M] arch/x86/kvm/hyperv.o
CC [M] net/ipv4/netfilter/ip_tables.o
CC drivers/acpi/acpica/nseval.o
CC [M] sound/hda/hdac_controller.o
CC net/ethtool/phc_vclocks.o
CC net/ipv4/route.o
CC fs/jbd2/recovery.o
AR fs/hugetlbfs/built-in.a
CC net/ipv4/inetpeer.o
CC [M] arch/x86/kvm/debugfs.o
CC fs/ext4/file.o
CC drivers/acpi/acpica/nsinit.o
CC drivers/base/regmap/regmap-debugfs.o
AR drivers/char/built-in.a
CC fs/jbd2/checkpoint.o
AR drivers/gpu/drm/panel/built-in.a
CC arch/x86/kernel/ksysfs.o
CC fs/fat/file.o
CC fs/jbd2/revoke.o
CC kernel/time/tick-oneshot.o
CC fs/ext4/fsmap.o
CC kernel/trace/trace_nop.o
CC [M] arch/x86/kvm/mmu/mmu.o
CC crypto/crct10dif_generic.o
AR drivers/dax/built-in.a
AR fs/proc/built-in.a
CC fs/jbd2/journal.o
AR drivers/macintosh/built-in.a
AR drivers/cxl/core/built-in.a
AR drivers/cxl/built-in.a
CC crypto/authenc.o
CC drivers/scsi/scsi.o
CC kernel/exec_domain.o
CC drivers/acpi/acpica/nsload.o
LD [M] net/netfilter/ipvs/ip_vs.o
CC drivers/acpi/acpica/nsnames.o
CC [M] net/netfilter/nf_conntrack_core.o
CC kernel/time/tick-sched.o
CC fs/ext4/fsync.o
CC drivers/nvme/host/core.o
CC block/blk-pm.o
CC crypto/authencesn.o
CC drivers/ata/libata-core.o
CC drivers/nvme/host/ioctl.o
CC arch/x86/kernel/bootflag.o
CC [M] net/ipv4/netfilter/iptable_filter.o
CC [M] arch/x86/kvm/mmu/page_track.o
CC [M] sound/hda/hdac_stream.o
CC mm/debug.o
AR kernel/cgroup/built-in.a
CC net/ethtool/mm.o
CC lib/decompress_unlzo.o
CC drivers/spi/spi.o
CC drivers/base/regmap/regmap-i2c.o
CC lib/decompress_unxz.o
CC fs/ext4/hash.o
AR sound/virtio/built-in.a
CC lib/decompress_unzstd.o
CC sound/sound_core.o
CC lib/dump_stack.o
CC fs/ext4/ialloc.o
CC drivers/acpi/acpica/nsobject.o
CC fs/fat/inode.o
CC drivers/dma-buf/dma-fence-array.o
CC drivers/nvme/host/trace.o
CC kernel/trace/trace_functions_graph.o
CC drivers/base/dd.o
CC [M] drivers/gpu/drm/display/drm_scdc_helper.o
CC [M] drivers/gpu/drm/display/drm_dp_aux_dev.o
CC crypto/lzo.o
CC block/holder.o
CC arch/x86/kernel/e820.o
CC drivers/tty/n_tty.o
CC sound/last.o
CC drivers/ata/libata-scsi.o
CC arch/x86/kernel/pci-dma.o
CC arch/x86/kernel/quirks.o
CC [M] drivers/misc/mei/gsc-me.o
CC drivers/acpi/acpica/nsparse.o
CC drivers/scsi/hosts.o
CC lib/zstd/decompress/zstd_ddict.o
CC fs/fat/misc.o
CC drivers/dma-buf/dma-fence-chain.o
CC kernel/time/vsyscall.o
CC fs/ext4/indirect.o
CC mm/gup.o
CC arch/x86/kernel/topology.o
CC fs/ext4/inline.o
CC drivers/scsi/scsi_ioctl.o
CC drivers/base/regmap/regmap-irq.o
CC lib/earlycpio.o
CC drivers/dma-buf/dma-fence-unwrap.o
CC lib/zstd/decompress/zstd_decompress.o
CC [M] net/ipv4/netfilter/iptable_mangle.o
CC [M] sound/hda/array.o
CC [M] net/ipv4/netfilter/iptable_nat.o
CC lib/extable.o
CC crypto/lzo-rle.o
CC net/core/sock_diag.o
CC net/ethtool/module.o
CC net/ipv4/protocol.o
CC [M] net/netfilter/nf_conntrack_standalone.o
CC drivers/acpi/acpica/nspredef.o
AR block/built-in.a
CC [M] net/netfilter/nf_conntrack_expect.o
CC drivers/acpi/acpica/nsprepkg.o
CC kernel/trace/fgraph.o
CC drivers/nvme/host/pci.o
LD [M] drivers/gpu/drm/display/drm_display_helper.o
CC kernel/time/timekeeping_debug.o
CC drivers/base/syscore.o
AR drivers/gpu/drm/bridge/analogix/built-in.a
CC drivers/base/driver.o
AR drivers/gpu/drm/bridge/cadence/built-in.a
AR drivers/gpu/drm/bridge/imx/built-in.a
AR drivers/gpu/drm/bridge/synopsys/built-in.a
AR drivers/gpu/drm/bridge/built-in.a
LD [M] drivers/misc/mei/mei.o
LD [M] drivers/misc/mei/mei-me.o
AR drivers/gpu/drm/hisilicon/built-in.a
AR drivers/gpu/drm/mxsfb/built-in.a
LD [M] drivers/misc/mei/mei-gsc.o
CC mm/mmap_lock.o
AR drivers/gpu/drm/tiny/built-in.a
AR drivers/nvme/target/built-in.a
CC lib/zstd/decompress/zstd_decompress_block.o
CC kernel/time/namespace.o
CC [M] net/netfilter/nf_conntrack_helper.o
AR drivers/gpu/drm/xlnx/built-in.a
CC drivers/dma-buf/dma-resv.o
CC lib/zstd/zstd_common_module.o
AR drivers/gpu/drm/gud/built-in.a
CC [M] net/netfilter/nf_conntrack_proto.o
AR drivers/gpu/drm/solomon/built-in.a
CC [M] drivers/gpu/drm/ttm/ttm_tt.o
CC kernel/trace/blktrace.o
CC [M] sound/hda/hdmi_chmap.o
CC [M] drivers/gpu/drm/ttm/ttm_bo.o
CC [M] net/ipv4/netfilter/ipt_REJECT.o
CC crypto/lz4.o
CC fs/fat/nfs.o
CC arch/x86/kernel/kdebugfs.o
CC lib/flex_proportions.o
CC drivers/acpi/acpica/nsrepair.o
CC drivers/scsi/scsicam.o
CC drivers/scsi/scsi_error.o
CC fs/ext4/inode.o
CC arch/x86/kernel/alternative.o
CC net/ipv4/ip_input.o
CC lib/idr.o
CC net/ethtool/pse-pd.o
CC [M] net/netfilter/nf_conntrack_proto_generic.o
CC crypto/lz4hc.o
CC [M] net/netfilter/nf_conntrack_proto_tcp.o
AR drivers/base/regmap/built-in.a
CC net/core/dev_ioctl.o
CC drivers/base/class.o
CC drivers/base/platform.o
CC lib/irq_regs.o
AR kernel/time/built-in.a
CC drivers/acpi/acpica/nsrepair2.o
CC kernel/trace/trace_events.o
CC drivers/base/cpu.o
AR fs/jbd2/built-in.a
CC drivers/tty/tty_ioctl.o
CC [M] net/netfilter/nf_conntrack_proto_udp.o
CC lib/is_single_threaded.o
CC fs/fat/namei_vfat.o
CC drivers/tty/tty_ldisc.o
CC kernel/trace/trace_export.o
CC drivers/net/phy/mdio-boardinfo.o
CC drivers/net/phy/mdio_devres.o
CC [M] drivers/gpu/drm/ttm/ttm_bo_util.o
CC [M] sound/hda/trace.o
CC mm/highmem.o
CC drivers/dma-buf/sync_file.o
CC fs/fat/namei_msdos.o
CC net/core/tso.o
CC net/ipv4/ip_fragment.o
CC [M] net/netfilter/nf_conntrack_proto_icmp.o
CC crypto/xxhash_generic.o
CC kernel/trace/trace_event_perf.o
CC [M] arch/x86/kvm/mmu/spte.o
CC lib/zstd/common/debug.o
CC kernel/events/ring_buffer.o
AR drivers/firewire/built-in.a
CC [M] arch/x86/kvm/mmu/tdp_iter.o
CC lib/klist.o
CC drivers/acpi/acpica/nssearch.o
CC lib/kobject.o
CC lib/zstd/common/entropy_common.o
CC drivers/base/firmware.o
CC drivers/base/init.o
CC lib/zstd/common/error_private.o
CC [M] arch/x86/kvm/mmu/tdp_mmu.o
CC net/ethtool/plca.o
CC drivers/net/phy/phy.o
CC lib/kobject_uevent.o
CC crypto/rng.o
CC crypto/drbg.o
AR drivers/cdrom/built-in.a
CC drivers/dma-buf/sw_sync.o
AR drivers/auxdisplay/built-in.a
CC drivers/base/map.o
CC drivers/base/devres.o
CC drivers/base/attribute_container.o
CC net/xfrm/xfrm_state.o
CC [M] arch/x86/kvm/smm.o
CC drivers/tty/tty_buffer.o
CC [M] drivers/gpu/drm/scheduler/sched_main.o
CC drivers/acpi/acpi_apd.o
CC mm/memory.o
CC drivers/acpi/acpica/nsutils.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_drv.o
CC drivers/acpi/acpi_platform.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o
CC arch/x86/kernel/i8253.o
AR drivers/spi/built-in.a
CC arch/x86/kernel/hw_breakpoint.o
CC kernel/events/callchain.o
CC [M] drivers/gpu/drm/ttm/ttm_bo_vm.o
CC [M] sound/hda/hdac_component.o
CC [M] sound/hda/hdac_i915.o
CC drivers/scsi/scsi_lib.o
CC lib/logic_pio.o
AR fs/fat/built-in.a
CC drivers/scsi/scsi_lib_dma.o
CC drivers/net/phy/phy-c45.o
CC [M] net/netfilter/nf_conntrack_extend.o
CC drivers/base/transport_class.o
CC drivers/usb/common/common.o
CC drivers/usb/core/usb.o
AR drivers/usb/phy/built-in.a
CC net/core/sock_reuseport.o
CC fs/ext4/ioctl.o
CC drivers/usb/host/pci-quirks.o
CC drivers/usb/core/hub.o
AR drivers/nvme/host/built-in.a
CC lib/maple_tree.o
AR drivers/nvme/built-in.a
CC drivers/usb/host/ehci-hcd.o
CC [M] arch/x86/kvm/vmx/vmx.o
CC drivers/usb/storage/scsiglue.o
CC drivers/usb/common/debug.o
CC drivers/usb/storage/protocol.o
CC drivers/usb/storage/transport.o
CC drivers/acpi/acpica/nswalk.o
CC net/ipv4/ip_forward.o
CC fs/nfs/client.o
CC fs/nfs/dir.o
CC fs/exportfs/expfs.o
AR net/ethtool/built-in.a
CC net/ipv4/ip_options.o
CC drivers/tty/tty_port.o
CC fs/lockd/clntlock.o
CC drivers/dma-buf/sync_debug.o
CC drivers/base/topology.o
CC kernel/events/hw_breakpoint.o
CC kernel/events/uprobes.o
CC fs/ext4/mballoc.o
CC fs/ext4/migrate.o
CC arch/x86/kernel/tsc.o
CC [M] sound/hda/intel-dsp-config.o
CC net/xfrm/xfrm_hash.o
CC fs/lockd/clntproc.o
CC [M] drivers/gpu/drm/ttm/ttm_module.o
AR drivers/usb/common/built-in.a
CC drivers/base/container.o
CC drivers/acpi/acpica/nsxfeval.o
CC drivers/ata/libata-eh.o
CC [M] arch/x86/kvm/kvm-asm-offsets.s
CC lib/memcat_p.o
CC crypto/jitterentropy.o
CC drivers/usb/storage/usb.o
CC crypto/jitterentropy-kcapi.o
CC fs/ext4/mmp.o
CC drivers/usb/host/ehci-pci.o
CC [M] drivers/gpu/drm/scheduler/sched_fence.o
CC [M] drivers/dma-buf/selftest.o
AR fs/exportfs/built-in.a
CC [M] net/netfilter/nf_conntrack_acct.o
CC drivers/acpi/acpica/nsxfname.o
CC [M] net/netfilter/nf_conntrack_seqadj.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_kms.o
CC kernel/trace/trace_events_filter.o
CC drivers/usb/host/ohci-hcd.o
CC drivers/base/property.o
CC [M] drivers/gpu/drm/ttm/ttm_execbuf_util.o
CC drivers/net/phy/phy-core.o
CC drivers/input/serio/serio.o
CC lib/zstd/common/fse_decompress.o
CC net/ipv4/ip_output.o
CC drivers/input/serio/i8042.o
CC drivers/scsi/scsi_scan.o
CC drivers/tty/tty_mutex.o
CC [M] sound/hda/intel-nhlt.o
CC crypto/ghash-generic.o
CC net/core/fib_notifier.o
CC [M] drivers/gpu/drm/scheduler/sched_entity.o
CC net/ipv4/ip_sockglue.o
CC [M] drivers/dma-buf/st-dma-fence.o
CC fs/ext4/move_extent.o
CC drivers/ata/libata-transport.o
CC drivers/acpi/acpica/nsxfobj.o
CC fs/ext4/namei.o
CC arch/x86/kernel/tsc_msr.o
GEN drivers/scsi/scsi_devinfo_tbl.c
CC net/ipv4/inet_hashtables.o
CC drivers/tty/tty_ldsem.o
CC drivers/ata/libata-trace.o
CC drivers/ata/libata-sata.o
CC drivers/usb/serial/usb-serial.o
CC [M] drivers/gpu/drm/ttm/ttm_range_manager.o
CC drivers/usb/serial/generic.o
CC fs/ext4/page-io.o
CC arch/x86/kernel/io_delay.o
CC [M] sound/hda/intel-sdw-acpi.o
CC fs/lockd/clntxdr.o
CC drivers/usb/storage/initializers.o
CC crypto/af_alg.o
CC drivers/usb/serial/bus.o
CC mm/mincore.o
CC drivers/acpi/acpica/psargs.o
AR drivers/usb/misc/built-in.a
CC [M] drivers/usb/misc/ftdi-elan.o
CC drivers/net/phy/phy_device.o
CC fs/nfs/file.o
CC lib/zstd/common/zstd_common.o
AR lib/zstd/built-in.a
CC lib/nmi_backtrace.o
CC drivers/base/cacheinfo.o
CC arch/x86/kernel/rtc.o
CC [M] drivers/dma-buf/st-dma-fence-chain.o
AR kernel/events/built-in.a
CC [M] net/netfilter/nf_conntrack_proto_icmpv6.o
LD [M] drivers/gpu/drm/scheduler/gpu-sched.o
CC [M] net/netfilter/nf_conntrack_proto_dccp.o
CC drivers/ata/libata-sff.o
CC net/core/xdp.o
LD [M] sound/hda/snd-hda-core.o
CC drivers/tty/tty_baudrate.o
CC [M] drivers/gpu/drm/ttm/ttm_resource.o
LD [M] sound/hda/snd-intel-dspcfg.o
CC drivers/scsi/scsi_devinfo.o
CC kernel/trace/trace_events_trigger.o
CC drivers/input/serio/libps2.o
LD [M] sound/hda/snd-intel-sdw-acpi.o
CC net/core/flow_offload.o
AR sound/built-in.a
CC drivers/acpi/acpica/psloop.o
CC net/core/gro.o
CC net/core/netdev-genl.o
CC drivers/usb/storage/sierra_ms.o
CC [M] drivers/gpu/drm/ttm/ttm_pool.o
CC net/ipv4/inet_timewait_sock.o
CC net/ipv4/inet_connection_sock.o
CC drivers/usb/serial/console.o
CC kernel/trace/trace_eprobe.o
CC crypto/algif_hash.o
CC net/xfrm/xfrm_input.o
CC arch/x86/kernel/resource.o
CC crypto/algif_skcipher.o
CC crypto/xor.o
CC fs/lockd/host.o
CC kernel/trace/trace_kprobe.o
CC drivers/base/swnode.o
CC fs/ext4/readpage.o
CC drivers/tty/tty_jobctrl.o
CC drivers/acpi/acpica/psobject.o
AS arch/x86/kernel/irqflags.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.o
CC arch/x86/kernel/static_call.o
CC drivers/usb/serial/ftdi_sio.o
AR drivers/input/serio/built-in.a
CC drivers/scsi/scsi_sysctl.o
CC [M] drivers/dma-buf/st-dma-fence-unwrap.o
CC drivers/ata/libata-pmp.o
CC drivers/usb/storage/option_ms.o
CC drivers/usb/core/hcd.o
CC fs/nfs/getroot.o
CC arch/x86/kernel/process.o
CC [M] net/netfilter/nf_conntrack_proto_sctp.o
CC drivers/ata/libata-acpi.o
CC fs/ext4/resize.o
CC drivers/usb/storage/usual-tables.o
CC fs/nfs/inode.o
CC [M] drivers/gpu/drm/ttm/ttm_device.o
CC crypto/hash_info.o
CC net/ipv4/tcp.o
CC kernel/trace/error_report-traces.o
CC [M] drivers/gpu/drm/ttm/ttm_sys_manager.o
CC kernel/trace/power-traces.o
CC drivers/acpi/acpica/psopcode.o
CC [M] drivers/dma-buf/st-dma-resv.o
CC net/core/netdev-genl-gen.o
CC net/ipv4/tcp_input.o
CC crypto/simd.o
CC drivers/scsi/scsi_debugfs.o
CC fs/nfs/super.o
CC drivers/tty/n_null.o
CC fs/ext4/super.o
CC drivers/base/auxiliary.o
CC net/core/net-sysfs.o
AR drivers/dma-buf/built-in.a
CC drivers/usb/core/urb.o
CC fs/nfs/io.o
CC fs/lockd/svc.o
CC net/ipv4/tcp_output.o
CC [M] net/netfilter/nf_conntrack_netlink.o
CC drivers/ata/libata-pata-timings.o
CC drivers/net/phy/linkmode.o
CC fs/nfs/direct.o
CC drivers/acpi/acpica/psopinfo.o
AR drivers/usb/storage/built-in.a
CC kernel/trace/rpm-traces.o
LD [M] drivers/dma-buf/dmabuf_selftests.o
CC [M] drivers/gpu/drm/ttm/ttm_agp_backend.o
CC drivers/input/keyboard/atkbd.o
CC kernel/trace/trace_dynevent.o
AR drivers/input/mouse/built-in.a
CC fs/lockd/svclock.o
CC drivers/net/phy/mdio_bus.o
CC drivers/acpi/acpica/psparse.o
CC drivers/net/phy/mdio_device.o
CC drivers/usb/host/ohci-pci.o
CC [M] crypto/md4.o
CC drivers/net/phy/swphy.o
CC drivers/rtc/lib.o
CC drivers/tty/pty.o
CC drivers/base/devtmpfs.o
CC drivers/base/memory.o
CC mm/mlock.o
CC mm/mmap.o
CC drivers/scsi/scsi_trace.o
CC net/core/net-procfs.o
CC net/xfrm/xfrm_output.o
CC [M] drivers/gpu/drm/i915/i915_driver.o
CC drivers/usb/serial/pl2303.o
CC [M] drivers/gpu/drm/i915/i915_drm_client.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_crtc.o
CC drivers/ata/ahci.o
CC drivers/acpi/acpica/psscope.o
CC net/ipv4/tcp_timer.o
CC arch/x86/kernel/ptrace.o
LD [M] drivers/gpu/drm/ttm/ttm.o
CC drivers/acpi/acpica/pstree.o
CC mm/mmu_gather.o
CC drivers/acpi/acpica/psutils.o
CC net/xfrm/xfrm_sysctl.o
CC net/ipv4/tcp_ipv4.o
CC drivers/acpi/acpica/pswalk.o
CC [M] crypto/ccm.o
CC net/ipv4/tcp_minisocks.o
CC drivers/usb/host/uhci-hcd.o
CC drivers/rtc/class.o
CC drivers/input/input.o
CC drivers/net/phy/fixed_phy.o
CC drivers/usb/core/message.o
CC fs/nfs/pagelist.o
CC fs/ext4/symlink.o
CC kernel/trace/trace_probe.o
CC fs/lockd/svcshare.o
CC drivers/scsi/scsi_logging.o
CC arch/x86/kernel/tls.o
CC [M] crypto/arc4.o
CC drivers/tty/sysrq.o
CC [M] crypto/ecc.o
CC drivers/base/module.o
CC drivers/acpi/acpica/psxface.o
AR drivers/input/keyboard/built-in.a
CC arch/x86/kernel/step.o
CC arch/x86/kernel/i8237.o
CC fs/ext4/sysfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.o
CC [M] drivers/net/phy/phylink.o
CC [M] drivers/gpu/drm/amd/amdgpu/atom.o
CC fs/lockd/svcproc.o
AR drivers/usb/serial/built-in.a
CC net/ipv4/tcp_cong.o
CC drivers/rtc/interface.o
CC net/core/netpoll.o
CC net/ipv4/tcp_metrics.o
CC arch/x86/kernel/stacktrace.o
CC drivers/base/pinctrl.o
CC drivers/ata/libahci.o
CC drivers/acpi/acpica/rsaddr.o
CC drivers/acpi/acpica/rscalc.o
CC lib/plist.o
CC [M] net/netfilter/nf_nat_core.o
CC kernel/trace/trace_uprobe.o
CC drivers/base/platform-msi.o
CC drivers/rtc/nvmem.o
CC lib/radix-tree.o
CC lib/ratelimit.o
CC [M] drivers/net/phy/aquantia_main.o
CC kernel/trace/rethook.o
CC net/core/fib_rules.o
CC fs/nfs/read.o
CC fs/nfs/symlink.o
CC drivers/scsi/scsi_pm.o
CC [M] drivers/net/phy/aquantia_hwmon.o
CC drivers/usb/gadget/udc/core.o
AR drivers/usb/gadget/function/built-in.a
CC fs/lockd/svcsubs.o
CC [M] drivers/net/phy/ax88796b.o
CC lib/rbtree.o
CC [M] crypto/essiv.o
CC arch/x86/kernel/reboot.o
CC fs/nfs/unlink.o
CC drivers/acpi/acpica/rscreate.o
AR drivers/tty/built-in.a
CC [M] arch/x86/kvm/vmx/pmu_intel.o
CC [M] arch/x86/kvm/vmx/vmcs12.o
CC drivers/ata/ata_piix.o
CC net/xfrm/xfrm_replay.o
CC [M] drivers/gpu/drm/i915/i915_config.o
CC drivers/input/input-compat.o
AR drivers/net/pse-pd/built-in.a
CC net/ipv4/tcp_fastopen.o
CC drivers/base/physical_location.o
CC drivers/rtc/dev.o
CC drivers/rtc/proc.o
CC drivers/usb/core/driver.o
CC [M] drivers/gpu/drm/i915/i915_getparam.o
CC drivers/acpi/acpica/rsdumpinfo.o
CC net/xfrm/xfrm_device.o
CC drivers/input/input-mt.o
CC drivers/scsi/scsi_bsg.o
CC drivers/usb/core/config.o
CC drivers/usb/gadget/udc/trace.o
CC [M] drivers/net/phy/bcm7xxx.o
CC fs/lockd/mon.o
CC fs/ext4/xattr.o
CC lib/seq_buf.o
CC fs/ext4/xattr_hurd.o
CC drivers/base/trace.o
CC arch/x86/kernel/msr.o
CC drivers/acpi/acpi_pnp.o
CC drivers/acpi/acpica/rsinfo.o
CC drivers/acpi/acpica/rsio.o
CC [M] crypto/ecdh.o
CC drivers/input/input-poller.o
CC lib/show_mem.o
CC drivers/scsi/scsi_common.o
CC drivers/scsi/sd.o
CC drivers/rtc/sysfs.o
CC fs/lockd/xdr.o
CC fs/nfs/write.o
CC mm/mprotect.o
CC [M] crypto/ecdh_helper.o
CC drivers/usb/host/xhci.o
CC drivers/acpi/acpica/rsirq.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fence.o
CC [M] net/netfilter/nf_nat_proto.o
CC lib/siphash.o
CC arch/x86/kernel/cpuid.o
AR drivers/i2c/algos/built-in.a
CC [M] drivers/i2c/algos/i2c-algo-bit.o
CC drivers/input/ff-core.o
CC lib/string.o
AR drivers/i3c/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.o
CC drivers/input/touchscreen.o
CC drivers/i2c/busses/i2c-designware-common.o
CC [M] drivers/gpu/drm/i915/i915_ioctl.o
CC drivers/i2c/busses/i2c-designware-master.o
CC lib/timerqueue.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_object.o
CC drivers/scsi/sg.o
AR drivers/ata/built-in.a
CC [M] drivers/gpu/drm/i915/i915_irq.o
CC net/xfrm/xfrm_algo.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gart.o
CC drivers/acpi/acpica/rslist.o
CC net/xfrm/xfrm_user.o
CC net/core/selftests.o
CC net/core/net-traces.o
LD [M] crypto/ecdh_generic.o
CC drivers/acpi/power.o
AR drivers/base/built-in.a
CC [M] drivers/gpu/drm/i915/i915_mitigations.o
AR crypto/built-in.a
CC [M] drivers/gpu/drm/i915/i915_module.o
CC fs/ext4/xattr_trusted.o
CC net/unix/af_unix.o
CC drivers/net/mdio/acpi_mdio.o
AR drivers/net/pcs/built-in.a
CC drivers/usb/core/file.o
AR kernel/trace/built-in.a
CC kernel/panic.o
CC [M] arch/x86/kvm/vmx/hyperv.o
CC drivers/net/mdio/fwnode_mdio.o
CC [M] drivers/net/phy/bcm87xx.o
CC [M] arch/x86/kvm/vmx/nested.o
CC drivers/rtc/rtc-mc146818-lib.o
CC fs/nfs/namespace.o
CC [M] drivers/net/phy/bcm-phy-lib.o
CC kernel/cpu.o
CC drivers/usb/core/buffer.o
CC [M] drivers/usb/class/usbtmc.o
CC drivers/i2c/busses/i2c-designware-platdrv.o
CC arch/x86/kernel/early-quirks.o
AR drivers/usb/gadget/udc/built-in.a
AR drivers/usb/gadget/legacy/built-in.a
CC drivers/usb/gadget/usbstring.o
CC lib/vsprintf.o
CC lib/win_minmax.o
CC drivers/acpi/acpica/rsmemory.o
CC drivers/input/ff-memless.o
CC fs/lockd/clnt4xdr.o
CC fs/ext4/xattr_user.o
AR drivers/i2c/muxes/built-in.a
CC [M] drivers/gpu/drm/i915/i915_params.o
CC [M] drivers/i2c/muxes/i2c-mux-gpio.o
CC drivers/i2c/i2c-boardinfo.o
CC drivers/usb/core/sysfs.o
CC drivers/rtc/rtc-cmos.o
CC net/ipv4/tcp_rate.o
CC drivers/acpi/acpica/rsmisc.o
CC net/ipv4/tcp_recovery.o
CC drivers/usb/gadget/config.o
CC net/core/ptp_classifier.o
CC [M] drivers/net/phy/broadcom.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.o
AR drivers/net/mdio/built-in.a
CC [M] drivers/gpu/drm/i915/i915_pci.o
CC drivers/usb/core/endpoint.o
CC [M] net/netfilter/nf_nat_helper.o
CC drivers/acpi/acpica/rsserial.o
CC [M] net/netfilter/nf_nat_redirect.o
CC net/core/netprio_cgroup.o
AR drivers/net/ethernet/adi/built-in.a
AR drivers/net/usb/built-in.a
AR drivers/net/ethernet/alacritech/built-in.a
CC [M] drivers/net/usb/pegasus.o
AR drivers/net/ethernet/amazon/built-in.a
CC mm/mremap.o
AR drivers/net/ethernet/aquantia/built-in.a
AR drivers/net/ethernet/asix/built-in.a
AR drivers/net/ethernet/cadence/built-in.a
AR drivers/net/ethernet/broadcom/built-in.a
CC [M] drivers/net/ethernet/broadcom/b44.o
CC [M] drivers/net/usb/rtl8150.o
CC drivers/i2c/busses/i2c-designware-baytrail.o
CC arch/x86/kernel/smp.o
CC [M] drivers/net/ethernet/broadcom/bnx2.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_display.o
CC drivers/usb/core/devio.o
CC mm/msync.o
CC arch/x86/kernel/smpboot.o
CC drivers/input/vivaldi-fmap.o
AR drivers/net/ethernet/cavium/common/built-in.a
AR drivers/net/ethernet/cavium/thunder/built-in.a
AR drivers/net/ethernet/cavium/liquidio/built-in.a
AR drivers/net/ethernet/cavium/octeon/built-in.a
AR drivers/media/i2c/built-in.a
AR drivers/net/ethernet/cavium/built-in.a
CC drivers/acpi/acpica/rsutils.o
AR drivers/media/tuners/built-in.a
CC drivers/acpi/acpica/rsxface.o
AR drivers/media/rc/keymaps/built-in.a
AR drivers/media/rc/built-in.a
AR drivers/net/ethernet/cortina/built-in.a
AR drivers/media/common/b2c2/built-in.a
CC drivers/i2c/i2c-core-base.o
AR drivers/ptp/built-in.a
AR drivers/media/common/saa7146/built-in.a
CC [M] drivers/ptp/ptp_clock.o
AR drivers/media/common/siano/built-in.a
AR drivers/media/common/v4l2-tpg/built-in.a
AR drivers/media/common/videobuf2/built-in.a
AR drivers/media/common/built-in.a
CC drivers/i2c/i2c-core-smbus.o
AR drivers/media/platform/allegro-dvt/built-in.a
CC drivers/usb/core/notify.o
CC drivers/i2c/i2c-core-acpi.o
AR drivers/media/pci/ttpci/built-in.a
AR drivers/media/platform/amlogic/meson-ge2d/built-in.a
AR drivers/media/platform/amlogic/built-in.a
AR drivers/media/pci/b2c2/built-in.a
AR drivers/media/platform/amphion/built-in.a
AR drivers/media/pci/pluto2/built-in.a
AR drivers/media/platform/aspeed/built-in.a
AR drivers/media/pci/dm1105/built-in.a
AR drivers/media/platform/atmel/built-in.a
AR drivers/media/pci/pt1/built-in.a
AR drivers/media/platform/cadence/built-in.a
CC drivers/usb/gadget/epautoconf.o
CC fs/lockd/xdr4.o
AR drivers/media/pci/pt3/built-in.a
CC drivers/i2c/i2c-core-slave.o
AR drivers/media/platform/chips-media/built-in.a
AR drivers/media/pci/mantis/built-in.a
AR drivers/media/platform/intel/built-in.a
AR drivers/media/pci/ngene/built-in.a
CC drivers/input/input-leds.o
AR drivers/media/platform/marvell/built-in.a
AR drivers/media/pci/ddbridge/built-in.a
AR drivers/media/platform/mediatek/jpeg/built-in.a
AR drivers/media/pci/saa7146/built-in.a
AR drivers/media/platform/mediatek/mdp/built-in.a
AR drivers/media/pci/smipcie/built-in.a
AR drivers/media/platform/mediatek/vcodec/built-in.a
AR drivers/media/pci/netup_unidvb/built-in.a
AR drivers/media/platform/mediatek/vpu/built-in.a
AR drivers/media/platform/mediatek/mdp3/built-in.a
AR drivers/media/pci/intel/ipu3/built-in.a
AR drivers/media/platform/mediatek/built-in.a
AR drivers/media/pci/intel/built-in.a
AR drivers/media/pci/built-in.a
AR drivers/media/platform/microchip/built-in.a
AR drivers/media/platform/nvidia/tegra-vde/built-in.a
CC [M] drivers/net/ipvlan/ipvlan_core.o
AR drivers/media/platform/nvidia/built-in.a
AR drivers/media/platform/nxp/dw100/built-in.a
CC [M] drivers/net/ipvlan/ipvlan_main.o
AR drivers/media/platform/nxp/imx-jpeg/built-in.a
AR drivers/media/platform/nxp/built-in.a
AR drivers/media/platform/qcom/camss/built-in.a
CC [M] drivers/net/phy/lxt.o
CC [M] drivers/i2c/busses/i2c-scmi.o
AR drivers/rtc/built-in.a
AR drivers/media/platform/qcom/venus/built-in.a
CC drivers/scsi/scsi_sysfs.o
AR drivers/media/platform/qcom/built-in.a
CC [M] drivers/net/ipvlan/ipvlan_l3s.o
CC drivers/usb/gadget/composite.o
AR drivers/media/platform/renesas/rcar-vin/built-in.a
CC drivers/usb/gadget/functions.o
AR drivers/media/platform/renesas/rzg2l-cru/built-in.a
AR drivers/media/platform/rockchip/rga/built-in.a
AR drivers/media/platform/rockchip/rkisp1/built-in.a
CC [M] drivers/i2c/busses/i2c-ccgx-ucsi.o
AR drivers/media/platform/renesas/vsp1/built-in.a
CC [M] drivers/net/phy/realtek.o
CC drivers/acpi/acpica/tbdata.o
AR drivers/media/platform/rockchip/built-in.a
AR drivers/media/platform/renesas/built-in.a
CC drivers/input/mousedev.o
CC [M] drivers/gpu/drm/i915/i915_scatterlist.o
CC net/core/dst_cache.o
AR drivers/media/platform/samsung/exynos-gsc/built-in.a
AR drivers/media/platform/samsung/exynos4-is/built-in.a
AR drivers/media/platform/samsung/s3c-camif/built-in.a
AR drivers/media/platform/samsung/s5p-g2d/built-in.a
AR drivers/media/platform/samsung/s5p-jpeg/built-in.a
AR drivers/power/reset/built-in.a
CC drivers/hwmon/hwmon.o
AR drivers/media/platform/samsung/s5p-mfc/built-in.a
CC drivers/power/supply/power_supply_core.o
AR drivers/media/platform/samsung/built-in.a
CC net/ipv4/tcp_ulp.o
AR drivers/media/platform/st/sti/bdisp/built-in.a
AR drivers/media/platform/st/sti/c8sectpfe/built-in.a
AR drivers/media/platform/st/sti/delta/built-in.a
AR drivers/media/platform/st/sti/hva/built-in.a
AR drivers/media/platform/sunxi/sun4i-csi/built-in.a
AR drivers/media/platform/st/stm32/built-in.a
AR drivers/media/platform/sunxi/sun6i-csi/built-in.a
AR drivers/media/platform/st/built-in.a
AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
CC [M] net/netfilter/nf_nat_masquerade.o
AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
CC [M] drivers/gpu/drm/i915/i915_suspend.o
AR drivers/media/platform/ti/am437x/built-in.a
CC [M] net/netfilter/x_tables.o
AR drivers/media/platform/sunxi/sun8i-di/built-in.a
AR drivers/media/platform/ti/cal/built-in.a
AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a
AR drivers/media/platform/ti/vpe/built-in.a
AR drivers/media/platform/sunxi/built-in.a
CC fs/nfs/mount_clnt.o
AR drivers/media/platform/ti/davinci/built-in.a
CC [M] net/netfilter/xt_tcpudp.o
AR drivers/media/platform/ti/omap/built-in.a
AR drivers/media/platform/ti/omap3isp/built-in.a
AR drivers/media/platform/ti/built-in.a
CC net/core/gro_cells.o
AR drivers/media/platform/verisilicon/built-in.a
AR drivers/thermal/broadcom/built-in.a
AR drivers/media/platform/via/built-in.a
AR drivers/thermal/samsung/built-in.a
AR drivers/media/platform/xilinx/built-in.a
AR drivers/media/platform/built-in.a
CC drivers/thermal/intel/intel_tcc.o
CC mm/page_vma_mapped.o
AR drivers/thermal/st/built-in.a
CC kernel/exit.o
CC kernel/softirq.o
AR drivers/media/usb/b2c2/built-in.a
AR drivers/media/usb/dvb-usb/built-in.a
AR drivers/media/usb/dvb-usb-v2/built-in.a
AR drivers/media/usb/s2255/built-in.a
AR drivers/media/usb/siano/built-in.a
CC [M] drivers/ptp/ptp_chardev.o
AR drivers/media/usb/ttusb-budget/built-in.a
AR drivers/media/usb/ttusb-dec/built-in.a
AR drivers/media/usb/built-in.a
CC [M] drivers/net/usb/r8152.o
AR drivers/media/mmc/siano/built-in.a
CC drivers/thermal/intel/therm_throt.o
AR drivers/media/mmc/built-in.a
AR drivers/media/firewire/built-in.a
CC [M] drivers/net/ethernet/broadcom/cnic.o
AR drivers/media/spi/built-in.a
AR drivers/media/test-drivers/built-in.a
AR drivers/media/built-in.a
CC arch/x86/kernel/tsc_sync.o
CC drivers/i2c/i2c-dev.o
CC drivers/acpi/acpica/tbfadt.o
CC drivers/watchdog/watchdog_core.o
AR net/xfrm/built-in.a
CC [M] drivers/hwmon/acpi_power_meter.o
CC drivers/acpi/acpica/tbfind.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o
CC [M] drivers/i2c/busses/i2c-i801.o
CC net/unix/garbage.o
CC fs/lockd/svc4proc.o
CC drivers/power/supply/power_supply_sysfs.o
CC drivers/input/evdev.o
CC [M] drivers/gpu/drm/i915/i915_switcheroo.o
CC drivers/usb/host/xhci-mem.o
CC drivers/acpi/acpica/tbinstal.o
CC [M] drivers/net/phy/smsc.o
CC [M] drivers/i2c/busses/i2c-isch.o
CC [M] drivers/gpu/drm/i915/i915_sysfs.o
CC drivers/usb/host/xhci-ext-caps.o
CC lib/xarray.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.o
CC [M] drivers/thermal/intel/intel_menlow.o
CC [M] drivers/i2c/i2c-smbus.o
CC arch/x86/kernel/setup_percpu.o
CC drivers/acpi/acpica/tbprint.o
CC arch/x86/kernel/ftrace.o
CC fs/lockd/procfs.o
CC [M] drivers/net/usb/asix_devices.o
CC drivers/usb/gadget/configfs.o
CC net/ipv4/tcp_offload.o
CC drivers/power/supply/power_supply_leds.o
CC fs/nfs/nfstrace.o
CC mm/pagewalk.o
AR drivers/scsi/built-in.a
CC [M] drivers/i2c/i2c-mux.o
CC [M] drivers/ptp/ptp_sysfs.o
LD [M] drivers/net/ipvlan/ipvlan.o
CC drivers/net/loopback.o
CC net/ipv4/tcp_plb.o
CC drivers/net/netconsole.o
CC [M] drivers/net/vxlan/vxlan_core.o
CC [M] drivers/ptp/ptp_vclock.o
CC mm/pgtable-generic.o
CC drivers/usb/core/generic.o
CC [M] drivers/net/ethernet/broadcom/tg3.o
CC [M] drivers/hwmon/coretemp.o
CC [M] drivers/md/persistent-data/dm-array.o
CC drivers/acpi/acpica/tbutils.o
CC drivers/opp/core.o
CC drivers/watchdog/watchdog_dev.o
CC drivers/opp/cpu.o
CC drivers/opp/debugfs.o
CC drivers/power/supply/power_supply_hwmon.o
AS arch/x86/kernel/ftrace_64.o
CC net/unix/sysctl_net_unix.o
CC [M] drivers/i2c/busses/i2c-ismt.o
CC drivers/cpufreq/cpufreq.o
AR drivers/thermal/intel/built-in.a
AR drivers/thermal/qcom/built-in.a
AR drivers/thermal/tegra/built-in.a
CC drivers/cpufreq/freq_table.o
AR drivers/thermal/mediatek/built-in.a
CC drivers/usb/gadget/u_f.o
CC drivers/thermal/thermal_core.o
CC drivers/usb/core/quirks.o
LD [M] drivers/net/phy/aquantia.o
AR fs/lockd/built-in.a
AR drivers/net/phy/built-in.a
CC drivers/thermal/thermal_sysfs.o
CC fs/nls/nls_base.o
CC [M] drivers/gpu/drm/i915/i915_utils.o
CC drivers/thermal/thermal_trip.o
CC arch/x86/kernel/trace_clock.o
CC drivers/acpi/acpica/tbxface.o
AR drivers/input/built-in.a
CC fs/nls/nls_cp437.o
CC arch/x86/kernel/trace.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gem.o
CC drivers/usb/core/devices.o
CC [M] drivers/i2c/busses/i2c-piix4.o
CC drivers/acpi/event.o
AR net/core/built-in.a
CC [M] arch/x86/kvm/vmx/posted_intr.o
CC drivers/acpi/acpica/tbxfload.o
CC [M] drivers/ptp/ptp_kvm_x86.o
CC [M] drivers/ptp/ptp_kvm_common.o
LD [M] arch/x86/kvm/kvm.o
CC mm/rmap.o
CC [M] net/netfilter/xt_mark.o
AR drivers/power/supply/built-in.a
AR drivers/power/built-in.a
CC drivers/watchdog/softdog.o
AR drivers/hwmon/built-in.a
UPD arch/x86/kvm/kvm-asm-offsets.h
CC arch/x86/kernel/rethook.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ring.o
CC drivers/cpuidle/governors/menu.o
CC drivers/cpufreq/cpufreq_performance.o
CC drivers/cpuidle/governors/haltpoll.o
CC kernel/resource.o
CC [M] drivers/md/persistent-data/dm-bitset.o
CC fs/nls/nls_ascii.o
CC kernel/sysctl.o
CC drivers/cpuidle/cpuidle.o
AS [M] arch/x86/kvm/vmx/vmenter.o
CC [M] drivers/gpu/drm/vgem/vgem_drv.o
CC [M] drivers/net/dummy.o
CC net/ipv4/datagram.o
CC net/unix/diag.o
CC net/ipv4/raw.o
LD [M] drivers/ptp/ptp.o
CC [M] drivers/md/persistent-data/dm-block-manager.o
CC [M] drivers/gpu/drm/nouveau/nvif/object.o
CC drivers/usb/core/phy.o
AR drivers/usb/gadget/built-in.a
CC [M] drivers/md/persistent-data/dm-space-map-common.o
CC lib/lockref.o
CC [M] drivers/md/persistent-data/dm-space-map-disk.o
CC drivers/acpi/acpica/tbxfroot.o
CC drivers/usb/core/port.o
CC [M] drivers/gpu/drm/xe/tests/xe_bo_test.o
AR drivers/watchdog/built-in.a
CC [M] drivers/i2c/busses/i2c-designware-pcidrv.o
CC [M] drivers/gpu/drm/i915/intel_clock_gating.o
CC fs/nls/nls_iso8859-1.o
CC [M] drivers/gpu/drm/nouveau/nvif/client.o
CC lib/bcd.o
CC [M] drivers/net/macvlan.o
CC net/unix/scm.o
LD [M] drivers/ptp/ptp_kvm.o
CC lib/sort.o
CC drivers/usb/core/hcd-pci.o
CC [M] drivers/net/mii.o
CC net/ipv4/udp.o
CC arch/x86/kernel/crash_core_64.o
CC net/ipv4/udplite.o
CC lib/parser.o
CC drivers/usb/host/xhci-ring.o
CC [M] net/netfilter/xt_nat.o
CC drivers/acpi/acpica/utaddress.o
CC [M] drivers/gpu/drm/xe/tests/xe_dma_buf_test.o
CC [M] drivers/gpu/drm/xe/tests/xe_migrate_test.o
AR drivers/opp/built-in.a
CC drivers/usb/host/xhci-hub.o
AR drivers/cpuidle/governors/built-in.a
CC fs/nls/nls_utf8.o
CC [M] drivers/gpu/drm/vgem/vgem_fence.o
CC [M] drivers/gpu/drm/i915/intel_device_info.o
CC drivers/cpufreq/cpufreq_ondemand.o
CC [M] drivers/md/persistent-data/dm-space-map-metadata.o
CC [M] net/netfilter/xt_REDIRECT.o
CC fs/ext4/fast_commit.o
CC net/packet/af_packet.o
AR net/ipv6/netfilter/built-in.a
CC [M] net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
CC net/ipv6/af_inet6.o
CC lib/debug_locks.o
CC [M] net/ipv6/netfilter/nf_conntrack_reasm.o
CC drivers/thermal/thermal_helpers.o
CC arch/x86/kernel/module.o
CC [M] drivers/net/mdio.o
AR fs/unicode/built-in.a
CC [M] drivers/gpu/drm/xe/tests/xe_pci_test.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_cs.o
LD [M] drivers/i2c/busses/i2c-designware-pci.o
CC fs/ntfs/aops.o
AR fs/nls/built-in.a
CC fs/ntfs/attrib.o
CC drivers/acpi/acpica/utalloc.o
CC net/packet/diag.o
AR drivers/i2c/busses/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_bios.o
AR drivers/i2c/built-in.a
CC drivers/usb/core/usb-acpi.o
CC lib/random32.o
CC drivers/cpuidle/driver.o
CC [M] drivers/gpu/drm/nouveau/nvif/conn.o
CC net/key/af_key.o
CC fs/ext4/orphan.o
CC [M] drivers/net/tun.o
CC arch/x86/kernel/early_printk.o
CC arch/x86/kernel/hpet.o
AR net/unix/built-in.a
LD [M] arch/x86/kvm/kvm-intel.o
CC kernel/capability.o
LD [M] drivers/gpu/drm/vgem/vgem.o
CC kernel/ptrace.o
CC [M] drivers/gpu/drm/ast/ast_drv.o
CC drivers/gpu/drm/drm_mipi_dsi.o
CC net/ipv4/udp_offload.o
CC drivers/acpi/acpica/utascii.o
CC fs/ntfs/collate.o
CC drivers/thermal/thermal_hwmon.o
CC lib/bust_spinlocks.o
CC [M] drivers/md/persistent-data/dm-transaction-manager.o
CC drivers/cpufreq/cpufreq_governor.o
CC net/ipv6/anycast.o
CC [M] net/netfilter/xt_MASQUERADE.o
CC drivers/cpuidle/governor.o
AR net/bridge/netfilter/built-in.a
CC drivers/cpuidle/sysfs.o
CC net/bridge/br.o
CC [M] drivers/gpu/drm/xe/tests/xe_rtp_test.o
CC drivers/cpuidle/poll_state.o
CC [M] drivers/gpu/drm/i915/intel_memory_region.o
AR drivers/usb/core/built-in.a
CC [M] net/netfilter/xt_addrtype.o
CC [M] drivers/gpu/drm/xe/tests/xe_wa_test.o
CC [M] net/netfilter/xt_conntrack.o
CC drivers/acpi/acpica/utbuffer.o
CC [M] drivers/gpu/drm/nouveau/nvif/device.o
CC net/ipv4/arp.o
CC arch/x86/kernel/amd_nb.o
CC drivers/cpufreq/cpufreq_governor_attr_set.o
CC [M] net/sunrpc/auth_gss/auth_gss.o
CC mm/vmalloc.o
CC net/8021q/vlan_core.o
CC net/dcb/dcbnl.o
CC drivers/thermal/gov_fair_share.o
CC net/dcb/dcbevent.o
CC fs/ntfs/compress.o
CC lib/kasprintf.o
CC lib/bitmap.o
CC drivers/thermal/gov_step_wise.o
CC [M] net/sunrpc/auth_gss/gss_generic_token.o
CC [M] drivers/gpu/drm/ast/ast_i2c.o
CC arch/x86/kernel/kvm.o
CC drivers/cpuidle/cpuidle-haltpoll.o
CC drivers/cpufreq/acpi-cpufreq.o
CC net/sunrpc/clnt.o
CC drivers/acpi/acpica/utcksum.o
CC [M] drivers/md/persistent-data/dm-btree.o
LD [M] net/ipv6/netfilter/nf_defrag_ipv6.o
CC drivers/acpi/acpica/utcopy.o
CC [M] drivers/gpu/drm/ast/ast_main.o
CC drivers/acpi/acpica/utexcep.o
CC [M] drivers/gpu/drm/nouveau/nvif/disp.o
CC net/ipv4/icmp.o
CC [M] drivers/gpu/drm/i915/intel_pcode.o
CC drivers/cpufreq/intel_pstate.o
CC lib/scatterlist.o
CC lib/list_sort.o
CC [M] drivers/gpu/drm/xe/xe_bb.o
CC kernel/user.o
CC net/sunrpc/xprt.o
AR drivers/net/ethernet/engleder/built-in.a
CC [M] drivers/gpu/drm/ast/ast_mm.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.o
CC drivers/thermal/gov_user_space.o
AR drivers/cpuidle/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_dp.o
CC [M] drivers/md/persistent-data/dm-btree-remove.o
CC net/bridge/br_device.o
CC arch/x86/kernel/kvmclock.o
CC net/sunrpc/socklib.o
CC net/ipv6/ip6_output.o
CC drivers/acpi/acpica/utdebug.o
CC [M] drivers/net/veth.o
CC [M] net/netfilter/xt_ipvs.o
CC net/sunrpc/xprtsock.o
CC [M] drivers/net/usb/asix_common.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.o
CC [M] drivers/gpu/drm/ast/ast_mode.o
CC fs/nfs/export.o
AR fs/ext4/built-in.a
CC [M] drivers/net/vxlan/vxlan_multicast.o
CC kernel/signal.o
CC fs/nfs/sysfs.o
CC [M] net/sunrpc/auth_gss/gss_mech_switch.o
AR drivers/thermal/built-in.a
CC arch/x86/kernel/paravirt.o
CC [M] drivers/gpu/drm/nouveau/nvif/driver.o
CC drivers/acpi/acpica/utdecode.o
CC fs/ntfs/debug.o
CC arch/x86/kernel/pvclock.o
CC net/bridge/br_fdb.o
CC [M] drivers/gpu/drm/xe/xe_bo.o
CC fs/ntfs/dir.o
CC [M] drivers/gpu/drm/drm_aperture.o
CC [M] net/8021q/vlan.o
CC arch/x86/kernel/pcspeaker.o
CC [M] drivers/net/usb/ax88172a.o
CC lib/uuid.o
CC drivers/mmc/core/core.o
CC [M] drivers/net/usb/ax88179_178a.o
CC drivers/mmc/host/sdhci.o
CC [M] drivers/md/persistent-data/dm-btree-spine.o
CC drivers/acpi/acpica/utdelete.o
CC lib/iov_iter.o
CC drivers/mmc/host/sdhci-pci-core.o
CC drivers/usb/host/xhci-dbg.o
AR net/key/built-in.a
CC [M] drivers/gpu/drm/i915/intel_region_ttm.o
CC drivers/usb/host/xhci-trace.o
CC net/bridge/br_forward.o
CC [M] drivers/net/usb/cdc_ether.o
CC fs/ntfs/file.o
CC [M] drivers/gpu/drm/i915/intel_runtime_pm.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.o
CC drivers/usb/host/xhci-debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_encoders.o
CC net/ipv4/devinet.o
CC arch/x86/kernel/check.o
CC [M] drivers/gpu/drm/drm_atomic.o
CC [M] drivers/gpu/drm/nouveau/nvif/event.o
CC net/sunrpc/sched.o
LD [M] net/netfilter/nf_conntrack.o
AR net/dcb/built-in.a
CC net/l3mdev/l3mdev.o
LD [M] net/netfilter/nf_nat.o
CC [M] drivers/net/usb/cdc_eem.o
AR net/netfilter/built-in.a
CC fs/nfs/fs_context.o
CC [M] drivers/gpu/drm/nouveau/nvif/fifo.o
CC drivers/acpi/acpica/uterror.o
LD [M] drivers/md/persistent-data/dm-persistent-data.o
AR net/packet/built-in.a
CC [M] net/bluetooth/af_bluetooth.o
CC [M] drivers/net/vxlan/vxlan_vnifilter.o
CC drivers/md/md.o
CC drivers/md/md-bitmap.o
CC fs/nfs/sysctl.o
CC [M] net/bluetooth/hci_core.o
CC [M] net/sunrpc/auth_gss/svcauth_gss.o
CC drivers/md/md-autodetect.o
CC arch/x86/kernel/uprobes.o
CC [M] drivers/gpu/drm/nouveau/nvif/head.o
CC fs/ntfs/index.o
CC [M] drivers/gpu/drm/ast/ast_post.o
CC net/sunrpc/auth.o
CC [M] net/8021q/vlan_dev.o
AR drivers/cpufreq/built-in.a
CC drivers/acpi/evged.o
CC drivers/acpi/acpica/uteval.o
CC [M] drivers/gpu/drm/i915/intel_sbi.o
CC [M] drivers/gpu/drm/i915/intel_step.o
CC [M] drivers/gpu/drm/ast/ast_dp501.o
CC net/ipv4/af_inet.o
AR net/l3mdev/built-in.a
CC [M] net/dns_resolver/dns_key.o
CC [M] drivers/gpu/drm/nouveau/nvif/mem.o
CC [M] drivers/gpu/drm/nouveau/nvif/mmu.o
CC [M] net/dns_resolver/dns_query.o
AR drivers/ufs/built-in.a
CC fs/nfs/nfs2super.o
CC net/bridge/br_if.o
CC [M] drivers/net/usb/smsc75xx.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sa.o
CC drivers/acpi/acpica/uthex.o
CC drivers/acpi/acpica/utglobal.o
CC fs/nfs/proc.o
CC [M] drivers/gpu/drm/i915/intel_uncore.o
CC fs/ntfs/inode.o
CC [M] drivers/gpu/drm/nouveau/nvif/outp.o
CC drivers/acpi/acpica/utids.o
CC [M] drivers/gpu/drm/xe/xe_bo_evict.o
CC arch/x86/kernel/perf_regs.o
AR drivers/leds/trigger/built-in.a
CC mm/page_alloc.o
CC [M] drivers/leds/trigger/ledtrig-audio.o
CC [M] drivers/gpu/drm/drm_atomic_uapi.o
CC [M] drivers/gpu/drm/drm_auth.o
CC drivers/mmc/core/bus.o
CC net/ipv6/ip6_input.o
AR drivers/firmware/arm_ffa/built-in.a
CC net/ipv6/addrconf.o
CC [M] drivers/gpu/drm/i915/intel_wakeref.o
AR drivers/firmware/arm_scmi/built-in.a
AR drivers/firmware/broadcom/built-in.a
CC arch/x86/kernel/tracepoint.o
AR drivers/crypto/stm32/built-in.a
LD [M] net/dns_resolver/dns_resolver.o
AR drivers/firmware/cirrus/built-in.a
CC mm/init-mm.o
AR drivers/crypto/xilinx/built-in.a
AR drivers/firmware/meson/built-in.a
AR drivers/crypto/hisilicon/built-in.a
CC net/ipv6/addrlabel.o
CC net/devres.o
AR drivers/crypto/keembay/built-in.a
AR drivers/crypto/built-in.a
CC net/socket.o
CC net/compat.o
CC net/ipv6/route.o
CC net/bridge/br_input.o
CC drivers/acpi/acpica/utinit.o
CC drivers/firmware/efi/libstub/efi-stub-helper.o
CC [M] net/8021q/vlan_netlink.o
CC drivers/firmware/efi/libstub/gop.o
CC drivers/usb/host/xhci-pci.o
AR drivers/leds/blink/built-in.a
AR drivers/leds/simple/built-in.a
CC drivers/leds/led-core.o
CC fs/nfs/nfs2xdr.o
CC fs/nfs/nfs3super.o
CC fs/nfs/nfs3client.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_i2c.o
CC [M] drivers/gpu/drm/ast/ast_dp.o
CC [M] drivers/gpu/drm/nouveau/nvif/timer.o
CC arch/x86/kernel/itmt.o
CC [M] drivers/gpu/drm/drm_blend.o
CC [M] drivers/gpu/drm/xe/xe_debugfs.o
CC fs/ntfs/mft.o
CC net/ipv6/ip6_fib.o
CC [M] drivers/gpu/drm/nouveau/nvif/vmm.o
CC drivers/acpi/acpica/utlock.o
CC lib/clz_ctz.o
AR drivers/firmware/imx/built-in.a
CC drivers/mmc/host/sdhci-pci-o2micro.o
CC drivers/mmc/core/host.o
CC lib/bsearch.o
LD [M] drivers/net/vxlan/vxlan.o
CC [M] net/sunrpc/auth_gss/gss_rpc_upcall.o
CC net/sunrpc/auth_null.o
CC [M] drivers/gpu/drm/nouveau/nvif/user.o
CC kernel/sys.o
CC drivers/mmc/host/sdhci-pci-arasan.o
CC net/bridge/br_ioctl.o
CC lib/find_bit.o
CC drivers/leds/led-class.o
CC drivers/firmware/efi/libstub/secureboot.o
CC kernel/umh.o
CC net/ipv4/igmp.o
CC drivers/md/dm-uevent.o
CC drivers/acpi/acpica/utmath.o
CC arch/x86/kernel/umip.o
CC [M] net/8021q/vlanproc.o
CC fs/ntfs/mst.o
CC fs/ntfs/namei.o
CC net/sysctl_net.o
CC drivers/firmware/efi/efi-bgrt.o
CC drivers/acpi/acpica/utmisc.o
CC [M] drivers/net/usb/smsc95xx.o
CC drivers/acpi/acpica/utmutex.o
CC drivers/firmware/efi/libstub/tpm.o
CC [M] drivers/gpu/drm/xe/xe_device.o
LD [M] drivers/gpu/drm/ast/ast.o
CC lib/llist.o
CC fs/ntfs/runlist.o
CC net/ipv4/fib_frontend.o
CC [M] net/bluetooth/hci_conn.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.o
AR drivers/usb/host/built-in.a
CC [M] drivers/net/usb/mcs7830.o
AR drivers/usb/built-in.a
CC [M] drivers/gpu/drm/xe/xe_dma_buf.o
CC drivers/leds/led-triggers.o
CC fs/nfs/nfs3proc.o
CC lib/memweight.o
CC [M] drivers/gpu/drm/drm_bridge.o
CC [M] drivers/gpu/drm/nouveau/nvif/userc361.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/client.o
CC [M] drivers/net/usb/usbnet.o
CC lib/kfifo.o
CC mm/memblock.o
CC kernel/workqueue.o
CC [M] drivers/gpu/drm/xe/xe_engine.o
CC drivers/mmc/core/mmc.o
CC drivers/acpi/sysfs.o
CC [M] drivers/net/usb/cdc_ncm.o
CC drivers/acpi/acpica/utnonansi.o
CC drivers/mmc/host/sdhci-pci-dwc-mshc.o
CC fs/nfs/nfs3xdr.o
CC fs/autofs/init.o
CC fs/debugfs/inode.o
CC fs/ntfs/super.o
CC arch/x86/kernel/unwind_orc.o
CC [M] net/sunrpc/auth_gss/gss_rpc_xdr.o
CC drivers/firmware/efi/efi.o
CC fs/ntfs/sysctl.o
CC drivers/acpi/acpica/utobject.o
CC [M] drivers/gpu/drm/xe/xe_exec.o
CC net/bridge/br_stp.o
CC drivers/firmware/efi/libstub/file.o
AR net/8021q/built-in.a
LD [M] net/8021q/8021q.o
CC net/bridge/br_stp_bpdu.o
AR drivers/net/ethernet/ezchip/built-in.a
AR drivers/net/ethernet/fungible/built-in.a
AR drivers/net/ethernet/huawei/built-in.a
CC [M] drivers/net/ethernet/intel/e1000/e1000_main.o
CC [M] drivers/net/ethernet/intel/e1000e/82571.o
CC net/ipv4/fib_semantics.o
AR drivers/leds/built-in.a
CC drivers/mmc/host/sdhci-pci-gli.o
CC [M] drivers/net/ethernet/intel/igb/igb_main.o
CC fs/autofs/inode.o
CC [M] drivers/net/ethernet/intel/igc/igc_main.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/engine.o
CC [M] drivers/net/ethernet/intel/igc/igc_mac.o
CC arch/x86/kernel/callthunks.o
CC [M] drivers/net/ethernet/intel/igc/igc_i225.o
CC lib/percpu-refcount.o
CC [M] drivers/net/usb/r8153_ecm.o
CC drivers/acpi/acpica/utosi.o
CC drivers/mmc/core/mmc_ops.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o
CC [M] drivers/gpu/drm/drm_cache.o
CC [M] drivers/gpu/drm/i915/vlv_sideband.o
CC arch/x86/kernel/mmconf-fam10h_64.o
CC fs/debugfs/file.o
CC drivers/firmware/efi/libstub/mem.o
CC drivers/firmware/efi/libstub/random.o
CC net/ipv4/fib_trie.o
CC [M] drivers/gpu/drm/xe/xe_execlist.o
CC drivers/acpi/acpica/utownerid.o
CC drivers/acpi/acpica/utpredef.o
CC net/ipv6/ipv6_sockglue.o
CC mm/memory_hotplug.o
CC mm/madvise.o
CC fs/autofs/root.o
CC drivers/acpi/acpica/utresdecode.o
CC net/ipv6/ndisc.o
CC [M] net/sunrpc/auth_gss/trace.o
CC [M] drivers/gpu/drm/drm_client.o
CC lib/rhashtable.o
CC [M] drivers/gpu/drm/xe/xe_force_wake.o
CC fs/ntfs/unistr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/enum.o
CC fs/ntfs/upcase.o
CC drivers/mmc/core/sd.o
CC net/bridge/br_stp_if.o
CC drivers/acpi/acpica/utresrc.o
CC drivers/firmware/efi/libstub/randomalloc.o
CC drivers/mmc/core/sd_ops.o
CC drivers/firmware/efi/libstub/pci.o
CC drivers/firmware/efi/libstub/skip_spaces.o
CC arch/x86/kernel/vsmp_64.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/event.o
CC [M] drivers/net/ethernet/intel/igc/igc_base.o
CC drivers/acpi/acpica/utstate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/firmware.o
CC [M] net/bluetooth/hci_event.o
CC [M] drivers/gpu/drm/drm_client_modeset.o
CC drivers/mmc/host/sdhci-acpi.o
CC net/bridge/br_stp_timer.o
CC [M] drivers/net/ethernet/intel/igb/igb_ethtool.o
LD [M] drivers/net/usb/asix.o
CC [M] drivers/net/ethernet/intel/e1000e/ich8lan.o
CC [M] drivers/net/ethernet/intel/e1000e/80003es2lan.o
AR fs/nfs/built-in.a
CC fs/tracefs/inode.o
AR fs/debugfs/built-in.a
CC [M] drivers/net/ethernet/intel/e1000e/mac.o
CC [M] drivers/gpu/drm/i915/vlv_suspend.o
AR arch/x86/kernel/built-in.a
CC [M] drivers/net/ethernet/intel/igc/igc_nvm.o
CC drivers/mmc/core/sdio.o
AR arch/x86/built-in.a
CC drivers/acpi/acpica/utstring.o
AR fs/ntfs/built-in.a
CC fs/autofs/symlink.o
CC net/ipv4/fib_notifier.o
CC fs/pstore/inode.o
CC net/ipv4/inet_fragment.o
CC [M] drivers/gpu/drm/xe/xe_ggtt.o
CC fs/btrfs/super.o
CC fs/btrfs/ctree.o
CC [M] drivers/gpu/drm/drm_color_mgmt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/gpuobj.o
CC drivers/firmware/efi/libstub/lib-cmdline.o
CC net/sunrpc/auth_unix.o
CC net/ipv4/ping.o
CC drivers/firmware/efi/libstub/lib-ctype.o
CC drivers/firmware/efi/libstub/alignedmem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/intr.o
CC [M] net/sunrpc/auth_gss/gss_krb5_mech.o
CC drivers/acpi/acpica/utstrsuppt.o
CC [M] net/bluetooth/mgmt.o
CC fs/autofs/waitq.o
CC [M] drivers/net/ethernet/intel/igbvf/vf.o
CC drivers/mmc/host/cqhci-core.o
CC [M] drivers/net/ethernet/intel/igbvf/mbx.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/ioctl.o
CC [M] net/bluetooth/hci_sock.o
AR fs/tracefs/built-in.a
CC net/bridge/br_netlink.o
CC [M] drivers/mmc/host/sdhci-pltfm.o
CC drivers/acpi/acpica/utstrtoul64.o
CC lib/base64.o
CC fs/pstore/platform.o
CC lib/once.o
CC [M] drivers/net/ethernet/intel/igc/igc_phy.o
CC [M] drivers/net/ethernet/intel/igc/igc_diag.o
AR drivers/firmware/psci/built-in.a
CC net/sunrpc/svc.o
CC drivers/acpi/acpica/utxface.o
CC drivers/firmware/efi/libstub/relocate.o
CC [M] drivers/gpu/drm/xe/xe_gt.o
CC net/ipv6/udp.o
CC drivers/firmware/efi/libstub/printk.o
CC net/sunrpc/svcsock.o
CC [M] drivers/gpu/drm/drm_connector.o
CC kernel/pid.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.o
CC net/ipv6/udplite.o
CC [M] drivers/gpu/drm/i915/soc/intel_dram.o
CC mm/page_io.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/memory.o
CC drivers/mmc/core/sdio_ops.o
CC net/ipv4/ip_tunnel_core.o
CC net/sunrpc/svcauth.o
CC fs/autofs/expire.o
CC lib/refcount.o
CC [M] drivers/gpu/drm/drm_crtc.o
CC [M] net/sunrpc/auth_gss/gss_krb5_seal.o
CC fs/autofs/dev-ioctl.o
CC [M] drivers/net/ethernet/intel/igc/igc_ethtool.o
CC drivers/mmc/core/sdio_bus.o
CC drivers/acpi/acpica/utxfinit.o
CC [M] drivers/net/ethernet/intel/igbvf/ethtool.o
CC fs/pstore/pmsg.o
CC net/ipv6/raw.o
CC lib/usercopy.o
CC lib/errseq.o
CC drivers/md/dm.o
CC [M] net/sunrpc/auth_gss/gss_krb5_unseal.o
CC [M] drivers/net/ethernet/intel/igc/igc_ptp.o
CC drivers/firmware/efi/libstub/vsprintf.o
CC drivers/firmware/efi/libstub/x86-stub.o
CC lib/bucket_locks.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_hw.o
CC lib/generic-radix-tree.o
CC drivers/acpi/acpica/utxferror.o
CC drivers/md/dm-table.o
CC drivers/md/dm-target.o
CC drivers/mmc/core/sdio_cis.o
CC drivers/md/dm-linear.o
STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_main.o
CC drivers/acpi/acpica/utxfmutex.o
CC drivers/firmware/efi/vars.o
AR drivers/mmc/host/built-in.a
CC [M] drivers/gpu/drm/drm_displayid.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/mm.o
CC [M] drivers/gpu/drm/drm_drv.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_ethtool.o
CC [M] drivers/gpu/drm/xe/xe_gt_clock.o
AR fs/pstore/built-in.a
CC net/bridge/br_netlink_tunnel.o
CC [M] drivers/net/ethernet/intel/ixgbevf/vf.o
AR fs/autofs/built-in.a
AR drivers/net/ethernet/i825xx/built-in.a
CC [M] drivers/gpu/drm/drm_dumb_buffers.o
CC [M] drivers/net/ethernet/intel/ixgbevf/mbx.o
CC net/ipv6/icmp.o
CC [M] drivers/gpu/drm/i915/soc/intel_gmch.o
CC mm/swap_state.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_main.o
CC lib/string_helpers.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_hw.o
CC [M] net/sunrpc/auth_gss/gss_krb5_seqnum.o
AR drivers/net/ethernet/intel/built-in.a
CC [M] drivers/gpu/drm/i915/soc/intel_pch.o
AR drivers/acpi/acpica/built-in.a
CC drivers/acpi/property.o
CC [M] drivers/net/ethernet/intel/e1000e/manage.o
CC kernel/task_work.o
CC net/bridge/br_arp_nd_proxy.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ib.o
CC [M] drivers/net/ethernet/intel/igbvf/netdev.o
CC [M] net/bluetooth/hci_sysfs.o
AR drivers/firmware/smccc/built-in.a
AR drivers/firmware/tegra/built-in.a
CC [M] drivers/gpu/drm/drm_edid.o
CC [M] net/bluetooth/l2cap_core.o
STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
STUBCPY drivers/firmware/efi/libstub/file.stub.o
STUBCPY drivers/firmware/efi/libstub/gop.stub.o
CC [M] drivers/net/ethernet/intel/e1000e/nvm.o
STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
CC net/ipv6/mcast.o
STUBCPY drivers/firmware/efi/libstub/mem.stub.o
CC net/ipv4/gre_offload.o
STUBCPY drivers/firmware/efi/libstub/pci.stub.o
STUBCPY drivers/firmware/efi/libstub/printk.stub.o
CC drivers/mmc/core/sdio_io.o
STUBCPY drivers/firmware/efi/libstub/random.stub.o
STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
AR drivers/firmware/efi/libstub/lib.a
CC drivers/firmware/efi/reboot.o
CC drivers/mmc/core/sdio_irq.o
CC drivers/acpi/acpi_cmos_rtc.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ethtool.o
CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o
CC [M] drivers/gpu/drm/drm_encoder.o
CC [M] drivers/net/ethernet/intel/igc/igc_dump.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/object.o
CC drivers/firmware/efi/memattr.o
CC [M] net/sunrpc/auth_gss/gss_krb5_wrap.o
CC [M] drivers/net/ethernet/intel/igc/igc_tsn.o
CC drivers/acpi/x86/apple.o
CC kernel/extable.o
CC lib/hexdump.o
CC kernel/params.o
CC drivers/acpi/x86/utils.o
CC drivers/acpi/x86/s2idle.o
CC lib/kstrtox.o
CC drivers/firmware/efi/tpm.o
CC drivers/firmware/efi/memmap.o
CC [M] drivers/net/ethernet/intel/e1000e/phy.o
CC net/ipv6/reassembly.o
CC [M] drivers/net/ethernet/intel/e100.o
CC [M] drivers/gpu/drm/drm_file.o
CC net/sunrpc/svcauth_unix.o
CC [M] drivers/gpu/drm/i915/i915_memcpy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/oproxy.o
CC mm/swapfile.o
CC [M] drivers/gpu/drm/drm_fourcc.o
CC drivers/mmc/core/slot-gpio.o
CC [M] drivers/gpu/drm/drm_framebuffer.o
CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o
CC drivers/clocksource/acpi_pm.o
CC drivers/clocksource/i8253.o
CC [M] drivers/gpu/drm/i915/i915_mm.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_pll.o
CC [M] drivers/gpu/drm/drm_gem.o
CC net/ipv6/tcp_ipv6.o
CC [M] drivers/gpu/drm/drm_ioctl.o
CC [M] drivers/gpu/drm/i915/i915_sw_fence.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.o
CC lib/debug_info.o
CC drivers/md/dm-stripe.o
CC net/bridge/br_sysfs_if.o
CC [M] net/sunrpc/auth_gss/gss_krb5_crypto.o
CC [M] drivers/gpu/drm/drm_lease.o
CC net/ipv4/metrics.o
CC [M] drivers/net/ethernet/intel/igc/igc_xdp.o
CC fs/btrfs/extent-tree.o
CC net/ipv6/ping.o
CC lib/iomap.o
CC [M] net/sunrpc/auth_gss/gss_krb5_keys.o
CC [M] drivers/gpu/drm/i915/i915_sw_fence_work.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.o
CC [M] drivers/net/ethernet/intel/e1000e/param.o
CC drivers/firmware/efi/esrt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/option.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_ee.o
CC kernel/kthread.o
CC [M] drivers/net/ethernet/intel/igb/e1000_82575.o
CC drivers/acpi/debugfs.o
CC drivers/mmc/core/regulator.o
AR drivers/clocksource/built-in.a
CC drivers/hid/usbhid/hid-core.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_param.o
AR drivers/staging/media/built-in.a
AR drivers/staging/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/ramht.o
CC drivers/hid/hid-core.o
CC drivers/hid/hid-input.o
CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o
CC drivers/hid/hid-quirks.o
CC drivers/md/dm-ioctl.o
CC [M] drivers/gpu/drm/drm_managed.o
CC drivers/firmware/efi/efi-pstore.o
LD [M] drivers/net/ethernet/intel/igbvf/igbvf.o
CC [M] drivers/net/ethernet/intel/igb/e1000_mac.o
CC [M] drivers/net/ethernet/intel/igb/e1000_nvm.o
CC drivers/acpi/acpi_lpat.o
CC [M] drivers/net/ethernet/intel/igb/e1000_phy.o
CC [M] drivers/net/ethernet/intel/igb/e1000_mbx.o
CC [M] drivers/gpu/drm/i915/i915_syncmap.o
CC drivers/md/dm-io.o
AR drivers/platform/x86/amd/built-in.a
AR drivers/platform/surface/built-in.a
CC drivers/firmware/efi/cper.o
CC drivers/platform/x86/intel/pmc/core.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_ethtool.o
LD [M] drivers/net/ethernet/intel/igc/igc.o
CC drivers/platform/x86/p2sb.o
CC drivers/mmc/core/debugfs.o
CC lib/pci_iomap.o
LD [M] net/sunrpc/auth_gss/auth_rpcgss.o
CC net/ipv4/netlink.o
CC lib/iomap_copy.o
CC drivers/platform/x86/intel/pmc/spt.o
CC net/bridge/br_sysfs_br.o
LD [M] net/sunrpc/auth_gss/rpcsec_gss_krb5.o
CC net/sunrpc/addr.o
CC [M] drivers/net/ethernet/intel/e1000e/ethtool.o
CC net/sunrpc/rpcb_clnt.o
CC drivers/md/dm-kcopyd.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_param.o
CC drivers/firmware/efi/cper_cxl.o
CC [M] drivers/net/ethernet/intel/e1000e/netdev.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/subdev.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.o
CC [M] drivers/net/ethernet/intel/e1000e/ptp.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sync.o
CC drivers/acpi/acpi_lpit.o
CC drivers/hid/hid-debug.o
CC drivers/md/dm-sysfs.o
CC [M] drivers/gpu/drm/drm_mm.o
LD [M] drivers/net/ethernet/intel/e1000/e1000.o
CC fs/btrfs/print-tree.o
CC mm/swap_slots.o
CC lib/devres.o
CC [M] drivers/platform/x86/intel/pmt/class.o
CC kernel/sys_ni.o
CC drivers/firmware/efi/runtime-wrappers.o
CC drivers/mmc/core/block.o
CC drivers/md/dm-stats.o
CC drivers/md/dm-rq.o
CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o
CC [M] drivers/gpu/drm/i915/i915_user_extensions.o
CC kernel/nsproxy.o
CC fs/btrfs/root-tree.o
CC drivers/firmware/efi/dev-path-parser.o
CC drivers/acpi/prmt.o
CC net/ipv4/nexthop.o
CC drivers/hid/usbhid/hiddev.o
CC [M] net/bluetooth/l2cap_sock.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ipsec.o
CC lib/check_signature.o
CC [M] drivers/net/ethernet/intel/igb/e1000_i210.o
CC mm/dmapool.o
CC mm/hugetlb.o
CC [M] drivers/gpu/drm/i915/i915_ioc32.o
LD [M] drivers/net/ethernet/intel/ixgb/ixgb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/uevent.o
CC drivers/platform/x86/intel/pmc/cnp.o
CC lib/interval_tree.o
CC net/sunrpc/timer.o
AR drivers/net/ethernet/microsoft/built-in.a
CC drivers/md/dm-io-rewind.o
CC lib/assoc_array.o
CC drivers/hid/hidraw.o
CC [M] drivers/gpu/drm/i915/i915_debugfs.o
CC lib/list_debug.o
CC [M] drivers/platform/x86/intel/pmt/telemetry.o
CC fs/btrfs/dir-item.o
CC fs/btrfs/file-item.o
CC net/sunrpc/xdr.o
CC [M] drivers/platform/x86/intel/pmt/crashlog.o
CC net/ipv6/exthdrs.o
CC net/bridge/br_nf_core.o
LD [M] drivers/platform/x86/intel/pmt/pmt_class.o
CC mm/hugetlb_vmemmap.o
CC drivers/mailbox/mailbox.o
CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
CC drivers/mailbox/pcc.o
CC lib/debugobjects.o
CC lib/bitrev.o
CC mm/sparse.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.o
CC drivers/firmware/efi/apple-properties.o
CC drivers/firmware/efi/earlycon.o
CC net/sunrpc/sunrpc_syms.o
CC drivers/platform/x86/intel/pmc/icl.o
CC [M] net/bluetooth/smp.o
CC [M] drivers/gpu/drm/drm_mode_config.o
CC drivers/md/dm-builtin.o
CC drivers/acpi/acpi_pcc.o
CC kernel/notifier.o
CC mm/sparse-vmemmap.o
CC drivers/devfreq/devfreq.o
CC [M] drivers/net/ethernet/intel/igb/igb_ptp.o
CC drivers/powercap/powercap_sys.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/fw.o
AR drivers/perf/built-in.a
CC [M] drivers/md/dm-bufio.o
LD [M] drivers/platform/x86/intel/pmt/pmt_telemetry.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/hs.o
LD [M] drivers/platform/x86/intel/pmt/pmt_crashlog.o
CC [M] drivers/md/dm-bio-prison-v1.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/ls.o
AR drivers/hid/usbhid/built-in.a
CC drivers/ras/ras.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/acr.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_common.o
AR drivers/net/ethernet/litex/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.o
CC net/ipv6/datagram.o
AR drivers/mailbox/built-in.a
CC drivers/platform/x86/intel/pmc/tgl.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.o
CC drivers/hid/hid-generic.o
AR drivers/hwtracing/intel_th/built-in.a
CC drivers/platform/x86/intel/pmc/adl.o
CC drivers/powercap/intel_rapl_common.o
CC drivers/platform/x86/intel/turbo_max_3.o
CC drivers/powercap/intel_rapl_msr.o
CC drivers/mmc/core/queue.o
CC drivers/acpi/ac.o
CC drivers/firmware/efi/cper-x86.o
CC net/bridge/br_multicast.o
LD [M] drivers/net/ethernet/intel/ixgbevf/ixgbevf.o
CC net/bridge/br_mdb.o
CC [M] drivers/gpu/drm/xe/xe_gt_topology.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o
CC [M] drivers/gpu/drm/i915/i915_debugfs_params.o
CC fs/btrfs/inode-item.o
CC kernel/ksysfs.o
CC lib/crc16.o
CC drivers/platform/x86/intel/pmc/mtl.o
AR drivers/net/ethernet/microchip/built-in.a
CC [M] drivers/md/dm-bio-prison-v2.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.o
AR drivers/firmware/xilinx/built-in.a
CC [M] drivers/devfreq/governor_simpleondemand.o
CC net/sunrpc/cache.o
CC net/ipv4/udp_tunnel_stub.o
CC drivers/platform/x86/intel/pmc/pltdrv.o
CC drivers/platform/x86/pmc_atom.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.o
CC [M] drivers/devfreq/governor_performance.o
CC [M] drivers/md/dm-crypt.o
CC [M] net/bluetooth/lib.o
CC net/sunrpc/rpc_pipe.o
CC drivers/hid/hid-a4tech.o
CC drivers/acpi/button.o
CC lib/crc-t10dif.o
CC drivers/acpi/fan_core.o
CC drivers/firmware/dmi_scan.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/base.o
AR drivers/firmware/efi/built-in.a
CC [M] drivers/gpu/drm/i915/display/intel_display_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.o
HOSTCC lib/gen_crc32table
CC net/ipv4/sysctl_net_ipv4.o
CC fs/btrfs/disk-io.o
CC fs/btrfs/transaction.o
CC lib/libcrc32c.o
CC drivers/ras/debugfs.o
CC kernel/cred.o
AR drivers/mmc/core/built-in.a
AR drivers/mmc/built-in.a
CC fs/btrfs/inode.o
CC [M] drivers/gpu/drm/xe/xe_guc.o
CC [M] drivers/gpu/drm/i915/display/intel_pipe_crc.o
CC net/ipv6/ip6_flowlabel.o
AR drivers/platform/x86/intel/pmc/built-in.a
CC [M] drivers/platform/x86/intel/vsec.o
CC [M] drivers/md/dm-thin.o
AR drivers/powercap/built-in.a
CC drivers/android/binderfs.o
CC drivers/android/binder.o
CC drivers/nvmem/core.o
CC drivers/hid/hid-apple.o
CC net/sunrpc/sysfs.o
CC drivers/android/binder_alloc.o
CC [M] drivers/net/ethernet/intel/igb/igb_hwmon.o
CC drivers/acpi/fan_attr.o
CC lib/xxhash.o
AR drivers/devfreq/built-in.a
CC drivers/hid/hid-belkin.o
CC lib/genalloc.o
AR drivers/ras/built-in.a
CC net/ipv4/proc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/fw.o
CC [M] drivers/gpu/drm/xe/xe_guc_ads.o
CC drivers/acpi/processor_driver.o
CC [M] drivers/gpu/drm/xe/xe_guc_ct.o
CC [M] net/bluetooth/ecdh_helper.o
CC lib/percpu_counter.o
CC net/ipv6/inet6_connection_sock.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sched.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/msgq.o
CC drivers/firmware/dmi-sysfs.o
CC [M] drivers/platform/x86/intel/rst.o
CC fs/btrfs/file.o
CC fs/efivarfs/inode.o
LD [M] drivers/platform/x86/intel/intel_vsec.o
CC fs/btrfs/defrag.o
CC mm/mmu_notifier.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ids.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.o
CC kernel/reboot.o
CC kernel/async.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.o
CC drivers/firmware/dmi-id.o
CC drivers/acpi/processor_thermal.o
CC drivers/acpi/processor_idle.o
CC net/sunrpc/svc_xprt.o
CC [M] net/bluetooth/hci_request.o
CC drivers/firmware/memmap.o
CC lib/fault-inject.o
CC drivers/hid/hid-cherry.o
CC fs/btrfs/extent_map.o
CC drivers/acpi/processor_throttling.o
LD [M] drivers/net/ethernet/intel/igb/igb.o
AR drivers/platform/x86/intel/built-in.a
LD [M] drivers/platform/x86/intel/intel-rst.o
CC net/sunrpc/xprtmultipath.o
CC kernel/range.o
CC [M] drivers/platform/x86/wmi.o
CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o
AR drivers/nvmem/built-in.a
CC net/sunrpc/stats.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_82599.o
CC fs/efivarfs/file.o
CC kernel/smpboot.o
CC net/ipv6/udp_offload.o
CC drivers/acpi/processor_perflib.o
CC [M] drivers/platform/x86/wmi-bmof.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/v1.o
LD [M] drivers/net/ethernet/intel/e1000e/e1000e.o
CC net/bridge/br_multicast_eht.o
CC kernel/ucount.o
CC [M] drivers/gpu/drm/i915/i915_pmu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/gm200.o
CC [M] drivers/gpu/drm/i915/gt/gen2_engine_cs.o
CC net/ipv6/seg6.o
CC lib/syscall.o
CC net/ipv4/syncookies.o
CC fs/efivarfs/super.o
CC net/bridge/br_vlan.o
CC net/ipv6/fib6_notifier.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.o
AR drivers/firmware/built-in.a
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_82598.o
CC [M] drivers/gpu/drm/drm_mode_object.o
CC kernel/regset.o
CC drivers/hid/hid-chicony.o
CC kernel/kmod.o
CC fs/efivarfs/vars.o
CC kernel/groups.o
CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.o
CC [M] drivers/platform/x86/mxm-wmi.o
CC [M] drivers/platform/x86/intel_ips.o
CC net/ipv4/esp4.o
CC net/bridge/br_vlan_tunnel.o
CC [M] drivers/md/dm-thin-metadata.o
CC drivers/acpi/container.o
CC drivers/acpi/thermal.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.o
CC [M] drivers/gpu/drm/xe/xe_guc_log.o
CC lib/dynamic_debug.o
AR drivers/net/ethernet/mscc/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_pc.o
CC net/sunrpc/sysctl.o
AR drivers/net/ethernet/neterion/built-in.a
AR drivers/net/ethernet/netronome/built-in.a
CC lib/errname.o
CC [M] drivers/gpu/drm/drm_modes.o
CC lib/nlattr.o
CC [M] net/bluetooth/mgmt_util.o
CC [M] drivers/gpu/drm/drm_modeset_lock.o
CC kernel/kcmp.o
CC lib/checksum.o
CC kernel/freezer.o
CC net/ipv6/rpl.o
CC mm/ksm.o
CC [M] drivers/mtd/chips/chipreg.o
CC kernel/stacktrace.o
CC mm/slub.o
CC [M] drivers/gpu/drm/drm_plane.o
CC fs/btrfs/sysfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_csa.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/gp102.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
CC net/ipv6/ioam6.o
CC drivers/hid/hid-cypress.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.o
AR fs/efivarfs/built-in.a
CC kernel/dma.o
CC net/ipv6/sysctl_net_ipv6.o
CC kernel/smp.o
CC kernel/uid16.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/ga100.o
CC [M] fs/netfs/buffered_read.o
CC drivers/acpi/acpi_memhotplug.o
CC [M] fs/netfs/io.o
CC [M] drivers/gpu/drm/i915/gt/gen6_engine_cs.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_phy.o
CC [M] drivers/gpu/drm/drm_prime.o
CC kernel/kallsyms.o
CC [M] drivers/gpu/drm/xe/xe_guc_submit.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine.o
AR drivers/platform/x86/built-in.a
AR drivers/platform/built-in.a
CC [M] drivers/gpu/drm/xe/xe_hw_fence.o
CC [M] drivers/mtd/mtdcore.o
CC kernel/acct.o
CC [M] drivers/gpu/drm/drm_print.o
CC net/bridge/br_vlan_options.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.o
CC kernel/crash_core.o
CC drivers/acpi/ioapic.o
CC drivers/hid/hid-ezkey.o
CC drivers/hid/hid-kensington.o
CC net/ipv6/xfrm6_policy.o
AR net/sunrpc/built-in.a
CC net/ipv6/xfrm6_state.o
CC [M] fs/fscache/cache.o
CC [M] fs/smbfs_common/cifs_arc4.o
CC [M] net/bluetooth/mgmt_config.o
LD [M] drivers/md/dm-bio-prison.o
CC [M] fs/smbfs_common/cifs_md4.o
LD [M] drivers/md/dm-thin-pool.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.o
CC [M] drivers/gpu/drm/xe/xe_huc.o
AR drivers/md/built-in.a
CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o
CC [M] fs/netfs/iterator.o
CC drivers/hid/hid-lg.o
CC fs/btrfs/accessors.o
CC net/ipv4/esp4_offload.o
CC lib/cpu_rmap.o
CC [M] drivers/uio/uio.o
CC net/ipv6/xfrm6_input.o
CC [M] fs/netfs/main.o
CC net/bridge/br_mst.o
CC mm/migrate.o
CC [M] fs/netfs/objects.o
CC [M] drivers/gpu/drm/drm_property.o
CC [M] drivers/gpu/drm/drm_pt_walk.o
CC kernel/compat.o
CC lib/dynamic_queue_limits.o
CC [M] fs/cifs/trace.o
CC [M] drivers/gpu/drm/i915/gt/gen6_ppgtt.o
CC [M] fs/cifs/cifsfs.o
CC [M] drivers/mtd/mtdsuper.o
CC drivers/acpi/battery.o
CC [M] drivers/gpu/drm/xe/xe_irq.o
CC [M] drivers/gpu/drm/xe/xe_lrc.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.o
CC [M] drivers/gpu/drm/xe/xe_migrate.o
CC [M] drivers/gpu/drm/i915/gt/gen7_renderclear.o
CC net/ipv4/netfilter.o
CC [M] fs/cifs/cifs_debug.o
CC lib/glob.o
CC [M] drivers/gpu/drm/drm_syncobj.o
CC [M] drivers/mtd/mtdconcat.o
CC [M] drivers/gpu/drm/xe/xe_mmio.o
CC [M] fs/fscache/cookie.o
CC [M] net/bridge/br_netfilter_hooks.o
CC [M] net/bridge/br_netfilter_ipv6.o
CC net/ipv4/inet_diag.o
CC [M] fs/fuse/dev.o
CC [M] fs/fuse/dir.o
CC [M] drivers/mtd/mtdpart.o
CC [M] net/bluetooth/hci_codec.o
CC mm/migrate_device.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.o
CC net/ipv4/tcp_diag.o
CC lib/strncpy_from_user.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_x540.o
CC net/ipv4/udp_diag.o
CC drivers/acpi/hed.o
CC [M] drivers/vfio/pci/vfio_pci_core.o
CC kernel/utsname.o
CC drivers/hid/hid-lg-g15.o
CC drivers/hid/hid-microsoft.o
CC kernel/user_namespace.o
CC kernel/pid_namespace.o
CC drivers/acpi/bgrt.o
LD [M] fs/netfs/netfs.o
CC [M] drivers/vfio/pci/vfio_pci_intrs.o
CC net/ipv4/tcp_cubic.o
CC [M] drivers/vfio/vfio_main.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.o
CC net/ipv6/xfrm6_output.o
AR drivers/android/built-in.a
CC [M] fs/fuse/file.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_x550.o
CC [M] net/bluetooth/eir.o
CC [M] drivers/gpu/drm/xe/xe_mocs.o
CC mm/huge_memory.o
CC lib/strnlen_user.o
CC [M] drivers/vfio/pci/vfio_pci_rdwr.o
UPD kernel/config_data
CC [M] drivers/gpu/drm/i915/gt/gen8_engine_cs.o
CC lib/net_utils.o
CC [M] drivers/gpu/drm/i915/gt/gen8_ppgtt.o
CC kernel/stop_machine.o
CC drivers/acpi/cppc_acpi.o
CC lib/sg_pool.o
CC drivers/acpi/spcr.o
CC net/ipv4/xfrm4_policy.o
CC net/ipv4/xfrm4_state.o
CC [M] drivers/mtd/mtdchar.o
CC drivers/acpi/acpi_pad.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.o
CC [M] net/bluetooth/hci_sync.o
CC drivers/hid/hid-monterey.o
CC net/ipv4/xfrm4_input.o
CC [M] drivers/vfio/pci/vfio_pci_config.o
CC [M] drivers/gpu/drm/drm_sysfs.o
CC [M] fs/cifs/connect.o
CC [M] net/bluetooth/sco.o
AR net/bridge/built-in.a
CC [M] drivers/gpu/drm/drm_trace_points.o
CC [M] net/bluetooth/iso.o
CC lib/stackdepot.o
CC [M] drivers/gpu/drm/xe/xe_module.o
CC [M] fs/fscache/io.o
CC [M] drivers/gpu/drm/xe/xe_pat.o
CC [M] drivers/gpu/drm/xe/xe_pci.o
CC [M] drivers/gpu/drm/xe/xe_pcode.o
CC mm/khugepaged.o
CC lib/ucs2_string.o
CC [M] drivers/gpu/drm/drm_vblank.o
CC [M] fs/fscache/main.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.o
AR drivers/net/ethernet/ni/built-in.a
CC [M] fs/cifs/dir.o
AR drivers/net/ethernet/packetengines/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
CC kernel/kprobes.o
CC net/ipv4/xfrm4_output.o
CC [M] drivers/gpu/drm/xe/xe_pm.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.o
CC mm/page_counter.o
AR drivers/net/ethernet/realtek/built-in.a
CC [M] drivers/net/ethernet/realtek/8139cp.o
CC net/ipv6/xfrm6_protocol.o
CC fs/btrfs/xattr.o
AR drivers/net/ethernet/renesas/built-in.a
CC net/ipv6/netfilter.o
CC [M] drivers/gpu/drm/i915/gt/intel_context.o
AR drivers/net/ethernet/sfc/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_umc.o
AR drivers/net/ethernet/smsc/built-in.a
CC [M] drivers/net/ethernet/smsc/smsc9420.o
CC [M] drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.o
CC mm/memcontrol.o
CC [M] fs/fuse/inode.o
CC [M] drivers/vfio/pci/vfio_pci.o
AR drivers/hid/built-in.a
CC lib/sbitmap.o
CC mm/vmpressure.o
CC [M] drivers/acpi/acpi_video.o
LD [M] drivers/mtd/mtd.o
CC [M] drivers/gpu/drm/drm_vblank_work.o
CC [M] drivers/gpu/drm/i915/gt/intel_context_sseu.o
CC [M] drivers/gpu/drm/drm_vma_manager.o
CC [M] fs/fuse/control.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.o
LD [M] net/bridge/br_netfilter.o
CC [M] drivers/gpu/drm/drm_writeback.o
CC lib/group_cpus.o
CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o
CC [M] drivers/net/ethernet/realtek/8139too.o
CC [M] fs/cifs/file.o
CC [M] drivers/pps/pps.o
CC [M] drivers/pps/kapi.o
CC [M] fs/overlayfs/super.o
CC [M] drivers/bluetooth/btusb.o
CC [M] fs/overlayfs/namei.o
CC [M] drivers/bluetooth/btintel.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_lib.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_rap.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.o
LD [M] drivers/vfio/pci/vfio-pci-core.o
LD [M] drivers/vfio/pci/vfio-pci.o
CC net/ipv4/xfrm4_protocol.o
CC [M] drivers/vfio/group.o
CC [M] drivers/gpu/drm/lib/drm_random.o
CC [M] fs/fscache/volume.o
CC [M] drivers/gpu/drm/xe/xe_pt.o
CC [M] lib/asn1_decoder.o
CC fs/open.o
CC [M] fs/cifs/inode.o
CC [M] net/ipv4/ip_tunnel.o
CC mm/swap_cgroup.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_cs.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.o
CC [M] drivers/pps/sysfs.o
CC [M] fs/fuse/xattr.o
CC [M] drivers/gpu/drm/xe/xe_query.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
CC mm/hugetlb_cgroup.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_pm.o
CC [M] net/ipv4/udp_tunnel_core.o
CC net/ipv6/fib6_rules.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.o
CC [M] net/ipv4/udp_tunnel_nic.o
CC fs/btrfs/ordered-data.o
CC [M] fs/fscache/proc.o
CC [M] drivers/bluetooth/btbcm.o
CC [M] drivers/acpi/video_detect.o
CC net/ipv6/proc.o
AR drivers/net/ethernet/socionext/built-in.a
AR drivers/net/ethernet/vertexcom/built-in.a
AR drivers/net/ethernet/wangxun/built-in.a
AR drivers/net/ethernet/xilinx/built-in.a
AR drivers/net/ethernet/synopsys/built-in.a
AR drivers/net/ethernet/pensando/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.o
LD [M] drivers/pps/pps_core.o
CC [M] drivers/vfio/iova_bitmap.o
CC kernel/hung_task.o
GEN lib/oid_registry_data.c
CC [M] fs/cifs/link.o
CC [M] lib/oid_registry.o
CC [M] fs/cifs/misc.o
CC [M] drivers/vfio/container.o
CC [M] drivers/net/ethernet/realtek/r8169_main.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_user.o
CC [M] fs/fuse/acl.o
CC [M] drivers/dca/dca-core.o
CC [M] drivers/ssb/main.o
CC [M] drivers/gpu/drm/i915/gt/intel_execlists_submission.o
CC [M] drivers/vhost/net.o
CC [M] drivers/ssb/scan.o
LD [M] fs/fscache/fscache.o
CC [M] drivers/vfio/virqfd.o
CC [M] drivers/net/ethernet/realtek/r8169_firmware.o
CC [M] fs/overlayfs/util.o
CC mm/kmemleak.o
AR lib/lib.a
CC [M] drivers/ssb/sprom.o
CC [M] drivers/dca/dca-sysfs.o
CC [M] drivers/vfio/vfio_iommu_type1.o
GEN lib/crc32table.h
CC lib/crc32.o
AR drivers/acpi/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt.o
LD [M] drivers/acpi/video.o
CC [M] drivers/bluetooth/btrtl.o
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
AR net/ipv4/built-in.a
CC mm/page_isolation.o
CC mm/early_ioremap.o
CC mm/cma.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mca.o
CC fs/read_write.o
CC [M] fs/cifs/netmisc.o
CC [M] drivers/net/ethernet/realtek/r8169_phy_config.o
CC [M] fs/fuse/readdir.o
CC kernel/watchdog.o
CC net/ipv6/syncookies.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt.o
CC kernel/watchdog_hld.o
CC [M] fs/overlayfs/inode.o
CC [M] fs/overlayfs/file.o
AR lib/built-in.a
CC net/ipv6/mip6.o
LD [M] drivers/dca/dca.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
LD [M] drivers/vfio/vfio.o
CC [M] drivers/gpu/drm/xe/xe_reg_sr.o
CC [M] fs/overlayfs/dir.o
CC [M] drivers/ssb/pci.o
CC [M] fs/overlayfs/readdir.o
CC [M] drivers/ssb/pcihost_wrapper.o
CC fs/file_table.o
CC [M] fs/cifs/smbencrypt.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.o
CC [M] drivers/vhost/vhost.o
CC fs/btrfs/extent_io.o
CC [M] net/bluetooth/a2mp.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.o
CC [M] fs/cifs/transport.o
CC [M] fs/overlayfs/copy_up.o
CC [M] drivers/gpu/drm/drm_ioc32.o
LD [M] net/ipv4/udp_tunnel.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.o
CC kernel/seccomp.o
CC [M] fs/cifs/cached_dir.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
CC fs/super.o
CC [M] fs/overlayfs/export.o
CC [M] fs/cifs/cifs_unicode.o
CC [M] fs/fuse/ioctl.o
CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.o
CC [M] drivers/vhost/iotlb.o
CC [M] drivers/gpu/drm/xe/xe_rtp.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
CC [M] drivers/gpu/drm/drm_panel.o
CC [M] drivers/gpu/drm/drm_pci.o
CC [M] fs/cifs/nterr.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_ring_ops.o
CC [M] drivers/gpu/drm/drm_debugfs.o
CC mm/secretmem.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_irq.o
CC fs/btrfs/volumes.o
CC net/ipv6/addrconf_core.o
CC fs/btrfs/async-thread.o
CC net/ipv6/exthdrs_core.o
CC kernel/relay.o
CC [M] net/bluetooth/amp.o
LD [M] drivers/vhost/vhost_net.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.o
CC [M] fs/cifs/cifsencrypt.o
CC [M] drivers/ssb/driver_chipcommon.o
CC [M] fs/cifs/readdir.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.o
CC [M] drivers/gpu/drm/xe/xe_sa.o
CC net/ipv6/ip6_checksum.o
CC [M] fs/cifs/ioctl.o
CC fs/char_dev.o
CC [M] drivers/gpu/drm/drm_debugfs_crc.o
CC [M] net/bluetooth/hci_debugfs.o
LD [M] fs/overlayfs/overlay.o
LD [M] fs/fuse/fuse.o
CC [M] fs/cifs/sess.o
CC mm/userfaultfd.o
CC fs/stat.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.o
CC net/ipv6/ip6_icmp.o
CC fs/exec.o
CC [M] drivers/gpu/drm/xe/xe_sched_job.o
LD [M] drivers/vhost/vhost_iotlb.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik_ih.o
CC [M] fs/cifs/export.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_mcr.o
CC [M] drivers/gpu/drm/xe/xe_step.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.o
CC [M] drivers/gpu/drm/drm_edid_load.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v8_0.o
CC fs/pipe.o
CC [M] fs/cifs/unc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga100.o
CC [M] drivers/gpu/drm/drm_panel_orientation_quirks.o
LD [M] drivers/net/ethernet/realtek/r8169.o
CC [M] drivers/gpu/drm/xe/xe_sync.o
CC kernel/utsname_sysctl.o
CC fs/namei.o
CC net/ipv6/output_core.o
CC [M] fs/cifs/winucase.o
CC [M] drivers/gpu/drm/xe/xe_trace.o
CC net/ipv6/protocol.o
CC [M] drivers/ssb/driver_chipcommon_pmu.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.o
CC [M] drivers/gpu/drm/drm_buddy.o
CC kernel/delayacct.o
CC kernel/taskstats.o
CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.o
CC fs/btrfs/ioctl.o
CC [M] drivers/ssb/driver_pcicore.o
CC mm/memremap.o
CC net/ipv6/ip6_offload.o
CC fs/fcntl.o
CC mm/hmm.o
CC kernel/tsacct.o
CC kernel/tracepoint.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
CC net/ipv6/tcpv6_offload.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.o
CC net/ipv6/exthdrs_offload.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v7_0.o
CC [M] fs/cifs/smb2ops.o
CC [M] drivers/gpu/drm/drm_gem_shmem_helper.o
CC kernel/latencytop.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.o
CC [M] fs/cifs/smb2maperror.o
CC [M] fs/cifs/smb2transport.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_requests.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik_sdma.o
CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
CC [M] drivers/gpu/drm/xe/xe_tuning.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
CC [M] drivers/gpu/drm/drm_suballoc.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v4_2.o
LD [M] drivers/ssb/ssb.o
CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o
CC [M] drivers/gpu/drm/xe/xe_uc.o
CC mm/memfd.o
LD [M] net/bluetooth/bluetooth.o
CC fs/btrfs/locking.o
CC kernel/irq_work.o
CC fs/ioctl.o
CC fs/readdir.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v2_0.o
CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o
CC net/ipv6/inet6_hashtables.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.o
CC kernel/static_call.o
CC mm/bootmem_info.o
CC kernel/static_call_inline.o
CC [M] drivers/gpu/drm/drm_atomic_helper.o
CC [M] drivers/gpu/drm/i915/gt/intel_gtt.o
CC fs/select.o
CC fs/btrfs/orphan.o
CC [M] fs/cifs/smb2misc.o
CC kernel/user-return-notifier.o
CC [M] drivers/gpu/drm/amd/amdgpu/si.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v6_0.o
CC [M] drivers/gpu/drm/drm_atomic_state_helper.o
CC [M] drivers/gpu/drm/xe/xe_uc_fw.o
CC kernel/padata.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v6_0.o
CC fs/dcache.o
CC [M] drivers/gpu/drm/xe/xe_vm.o
CC [M] drivers/gpu/drm/drm_bridge_connector.o
CC fs/btrfs/export.o
CC [M] fs/cifs/smb2pdu.o
CC [M] drivers/gpu/drm/drm_crtc_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.o
CC fs/inode.o
CC [M] drivers/gpu/drm/amd/amdgpu/si_ih.o
CC [M] drivers/gpu/drm/xe/xe_vm_madvise.o
CC [M] fs/cifs/smb2inode.o
CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o
CC [M] drivers/gpu/drm/xe/xe_wa.o
CC [M] drivers/gpu/drm/amd/amdgpu/si_dma.o
CC [M] fs/cifs/smb2file.o
CC [M] drivers/gpu/drm/xe/xe_wopcm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.o
CC fs/attr.o
CC fs/btrfs/tree-log.o
CC net/ipv6/mcast_snoop.o
AR mm/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.o
CC [M] drivers/gpu/drm/i915/gt/intel_llc.o
CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o
CC fs/bad_inode.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v6_0.o
CC [M] drivers/gpu/drm/drm_damage_helper.o
LD [M] drivers/net/ethernet/intel/ixgbe/ixgbe.o
CC [M] drivers/gpu/drm/drm_encoder_slave.o
CC fs/btrfs/free-space-cache.o
CC fs/btrfs/zlib.o
CC kernel/jump_label.o
AR drivers/net/ethernet/built-in.a
CC fs/btrfs/lzo.o
AR drivers/net/built-in.a
CC [M] drivers/gpu/drm/drm_flip_work.o
CC [M] net/ipv6/ip6_udp_tunnel.o
CC [M] drivers/gpu/drm/i915/gt/intel_migrate.o
CC [M] drivers/gpu/drm/xe/xe_display.o
CC kernel/context_tracking.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.o
CC kernel/iomem.o
CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o
CC fs/file.o
CC fs/btrfs/zstd.o
CC [M] drivers/gpu/drm/drm_format_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v3_1.o
CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o
CC [M] fs/cifs/cifsacl.o
CC fs/filesystems.o
CC [M] drivers/gpu/drm/drm_gem_atomic_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.o
CC fs/btrfs/compression.o
CC [M] drivers/gpu/drm/amd/amdgpu/vi.o
CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o
CC [M] drivers/gpu/drm/i915/gt/intel_mocs.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_vi.o
AR net/ipv6/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v6_1.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.o
CC [M] drivers/gpu/drm/drm_gem_framebuffer_helper.o
CC [M] fs/cifs/fs_context.o
CC [M] drivers/gpu/drm/drm_kms_helper_common.o
CC kernel/rseq.o
CC fs/btrfs/delayed-ref.o
CC [M] drivers/gpu/drm/amd/amdgpu/soc15.o
CC fs/namespace.o
CC fs/seq_file.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.o
CC [M] fs/cifs/dns_resolve.o
ASN.1 fs/cifs/cifs_spnego_negtokeninit.asn1.[ch]
CC [M] fs/cifs/smb1ops.o
CC fs/btrfs/relocation.o
CC fs/xattr.o
CC [M] drivers/gpu/drm/drm_modeset_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/emu_soc.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_ai.o
CC [M] drivers/gpu/drm/drm_plane_helper.o
AR net/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_ppgtt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.o
CC fs/libfs.o
CC fs/fs-writeback.o
CC fs/btrfs/delayed-inode.o
CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_clock_gating.o
CC [M] drivers/gpu/drm/drm_probe_helper.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_device_info.o
CC [M] drivers/gpu/drm/drm_rect.o
CC [M] drivers/gpu/drm/i915/gt/intel_rc6.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_0.o
CC [M] drivers/gpu/drm/drm_self_refresh_helper.o
CC fs/btrfs/scrub.o
CC fs/btrfs/backref.o
CC fs/btrfs/ulist.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega10_reg_init.o
GZIP kernel/config_data.gz
CC [M] drivers/gpu/drm/i915/gt/intel_region_lmem.o
CC [M] drivers/gpu/drm/i915/gt/intel_renderstate.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega20_reg_init.o
CC kernel/configs.o
CC fs/pnode.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_4.o
CC [M] drivers/gpu/drm/drm_simple_kms_helper.o
CC fs/splice.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v2_3.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_dram.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.o
CC [M] drivers/gpu/drm/bridge/panel.o
CC [M] drivers/gpu/drm/amd/amdgpu/nv.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_pch.o
CC [M] drivers/gpu/drm/amd/amdgpu/arct_reg_init.o
CC [M] fs/cifs/cifssmb.o
CC fs/btrfs/qgroup.o
CC [M] drivers/gpu/drm/i915/gt/intel_reset.o
CC fs/sync.o
CC [M] drivers/gpu/drm/drm_fbdev_generic.o
AR kernel/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.o
CC [M] drivers/gpu/drm/drm_fb_helper.o
CC [M] drivers/gpu/drm/xe/i915-display/icl_dsi.o
CC [M] fs/cifs/cifs_spnego_negtokeninit.asn1.o
CC [M] fs/cifs/asn1.o
CC [M] drivers/gpu/drm/i915/gt/intel_ring.o
CC fs/utimes.o
CC fs/btrfs/send.o
CC fs/d_path.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_nv.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_2.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v4_0.o
LD [M] drivers/gpu/drm/drm.o
CC fs/stack.o
CC [M] drivers/gpu/drm/i915/gt/intel_ring_submission.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v5_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.o
CC [M] drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.o
CC fs/btrfs/dev-replace.o
CC fs/fs_struct.o
CC [M] drivers/gpu/drm/i915/gt/intel_rps.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/i915/gt/intel_sa_media.o
CC fs/btrfs/raid56.o
CC fs/btrfs/uuid-tree.o
CC fs/statfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_audio.o
CC [M] drivers/gpu/drm/amd/amdgpu/aldebaran.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_backlight.o
CC [M] drivers/gpu/drm/i915/gt/intel_sseu.o
CC fs/btrfs/props.o
CC fs/fs_pin.o
CC [M] drivers/gpu/drm/amd/amdgpu/soc21.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.o
LD [M] drivers/gpu/drm/drm_shmem_helper.o
LD [M] drivers/gpu/drm/drm_suballoc_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.o
LD [M] drivers/gpu/drm/drm_ttm_helper.o
CC fs/nsfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/sienna_cichlid.o
CC fs/fs_types.o
CC [M] drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.o
CC fs/fs_context.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v4_3.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bios.o
CC fs/fs_parser.o
CC fs/fsopen.o
CC [M] drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
CC fs/init.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v6_0.o
CC fs/btrfs/free-space-tree.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bw.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_7.o
CC [M] drivers/gpu/drm/i915/gt/intel_timeline.o
CC fs/kernel_read_file.o
CC fs/mnt_idmapping.o
CC fs/remap_range.o
CC fs/buffer.o
CC fs/mpage.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cdclk.o
AR drivers/gpu/drm/built-in.a
LD [M] drivers/gpu/drm/drm_kms_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v5_2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.o
CC fs/btrfs/tree-checker.o
CC [M] drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.o
CC fs/proc_namespace.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.o
CC fs/direct-io.o
CC fs/eventpoll.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v1_7.o
CC fs/anon_inodes.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_color.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_combo_phy.o
CC [M] drivers/gpu/drm/i915/gt/intel_wopcm.o
CC fs/btrfs/space-info.o
CC fs/signalfd.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v3_6.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v4_3.o
CC fs/btrfs/block-rsv.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_connector.o
CC [M] drivers/gpu/drm/i915/gt/intel_workarounds.o
CC fs/btrfs/delalloc-space.o
CC [M] drivers/gpu/drm/i915/gt/shmem_utils.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v7_0.o
CC [M] drivers/gpu/drm/i915/gt/sysfs_engines.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.o
CC fs/timerfd.o
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
CC [M] drivers/gpu/drm/i915/gt/gen6_renderstate.o
CC fs/btrfs/block-group.o
CC fs/eventfd.o
CC fs/userfaultfd.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.o
CC fs/aio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v8_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v9_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o
CC fs/locks.o
CC fs/btrfs/discard.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.o
CC [M] drivers/gpu/drm/i915/gt/gen7_renderstate.o
CC [M] drivers/gpu/drm/i915/gt/gen8_renderstate.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.o
CC [M] drivers/gpu/drm/i915/gt/gen9_renderstate.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cursor.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi.o
CC fs/btrfs/reflink.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_busy.o
CC fs/binfmt_script.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_clflush.o
CC fs/binfmt_elf.o
CC fs/btrfs/subpage.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_context.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_create.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.o
CC fs/compat_binfmt_elf.o
CC fs/btrfs/tree-mod-log.o
CC fs/btrfs/extent-io-tree.o
CC fs/mbcache.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display.o
CC fs/btrfs/fs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.o
CC fs/posix_acl.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v10_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power.o
CC fs/coredump.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_domain.o
LD [M] fs/cifs/cifs.o
CC fs/btrfs/messages.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_map.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.o
CC fs/drop_caches.o
CC fs/btrfs/bio.o
CC fs/btrfs/lru_cache.o
CC fs/btrfs/acl.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_internal.o
CC fs/fhandle.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_object.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_well.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_trace.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_lmem.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_mman.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_pages.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v11_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_1.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_7.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v8_7.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v8_10.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_phys.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_pm.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_region.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_shmem.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_mst.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpt.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_irq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ih.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_drrs.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_stolen.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_throttle.o
AR fs/btrfs/built-in.a
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsb.o
AR fs/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/iceland_ih.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fb.o
CC [M] drivers/gpu/drm/amd/amdgpu/tonga_ih.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fbc.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_tiling.o
CC [M] drivers/gpu/drm/amd/amdgpu/cz_ih.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega10_ih.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fdi.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega20_ih.o
CC [M] drivers/gpu/drm/amd/amdgpu/navi10_ih.o
CC [M] drivers/gpu/drm/amd/amdgpu/ih_v6_0.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_global_state.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_gmbus.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/vpstate.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_userptr.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_psp.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_wait.o
CC [M] drivers/gpu/drm/i915/gem/i915_gemfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v3_1.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v10_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdmi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hti.o
CC [M] drivers/gpu/drm/i915/i915_active.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_lspcon.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/i915/i915_cmd_parser.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_panel.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pps.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v11_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v12_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v13_0.o
CC [M] drivers/gpu/drm/i915/i915_deps.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v10_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_psr.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v11_0.o
CC [M] drivers/gpu/drm/i915/i915_gem_evict.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_qp_tables.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_quirks.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_phy.o
CC [M] drivers/gpu/drm/i915/i915_gem_gtt.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.o
CC [M] drivers/gpu/drm/i915/i915_gem_ww.o
CC [M] drivers/gpu/drm/i915/i915_gem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.o
CC [M] drivers/gpu/drm/i915/i915_query.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_tc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vblank.o
CC [M] drivers/gpu/drm/i915/i915_request.o
CC [M] drivers/gpu/drm/i915/i915_scheduler.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v8_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vdsc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vga.o
CC [M] drivers/gpu/drm/i915/i915_trace_points.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vrr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_wm.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_scaler.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_universal_plane.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_watermark.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_acpi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_opregion.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4.o
CC [M] drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fbdev.o
HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v10_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.o
HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/imu_v11_0.o
HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v11_0.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h
CC [M] drivers/gpu/drm/i915/i915_vma.o
CC [M] drivers/gpu/drm/amd/amdgpu/imu_v11_0_3.o
CC [M] drivers/gpu/drm/i915/i915_vma_resource.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_config.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pm_types.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v2_4.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v3_0.o
HDRTEST drivers/gpu/drm/xe/display/ext/i915_irq.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.o
HDRTEST drivers/gpu/drm/xe/display/ext/intel_pch.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.o
HDRTEST drivers/gpu/drm/xe/display/ext/intel_dram.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.o
HDRTEST drivers/gpu/drm/xe/display/ext/intel_device_info.h
HDRTEST drivers/gpu/drm/xe/display/xe_de.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.o
HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.o
HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.o
HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.o
HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h
HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h
HDRTEST drivers/gpu/drm/xe/tests/xe_test.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.o
HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_0.o
HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_4.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h
HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h
HDRTEST drivers/gpu/drm/xe/xe_bb.h
HDRTEST drivers/gpu/drm/xe/xe_bb_types.h
HDRTEST drivers/gpu/drm/xe/xe_bo.h
HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h
HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h
HDRTEST drivers/gpu/drm/xe/xe_bo_types.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v5_0.o
HDRTEST drivers/gpu/drm/xe/xe_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_device.h
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v5_2.o
HDRTEST drivers/gpu/drm/xe/xe_device_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
HDRTEST drivers/gpu/drm/xe/xe_display.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v6_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.o
HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.o
HDRTEST drivers/gpu/drm/xe/xe_drv.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.o
HDRTEST drivers/gpu/drm/xe/xe_engine.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.o
HDRTEST drivers/gpu/drm/xe/xe_engine_types.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
HDRTEST drivers/gpu/drm/xe/xe_exec.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mes.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.o
HDRTEST drivers/gpu/drm/xe/xe_execlist.h
HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h
HDRTEST drivers/gpu/drm/xe/xe_force_wake.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.o
HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h
HDRTEST drivers/gpu/drm/xe/xe_ggtt.h
HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt.h
HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h
HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h
HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/mes_v10_1.o
HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/mes_v11_0.o
HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v5_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v6_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.o
HDRTEST drivers/gpu/drm/xe/xe_gt_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_guc_engine_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h
HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.o
HDRTEST drivers/gpu/drm/xe/xe_guc_log.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.o
HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v7_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vce.o
HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc.o
HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h
HDRTEST drivers/gpu/drm/xe/xe_guc_types.h
CC [M] drivers/gpu/drm/i915/gt/intel_gsc.o
HDRTEST drivers/gpu/drm/xe/xe_huc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.o
HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h
CC [M] drivers/gpu/drm/i915/i915_hwmon.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v3_0.o
HDRTEST drivers/gpu/drm/xe/xe_huc_types.h
HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h
HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h
HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.o
CC [M] drivers/gpu/drm/i915/display/hsw_ips.o
CC [M] drivers/gpu/drm/i915/display/intel_atomic.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.o
HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.o
CC [M] drivers/gpu/drm/i915/display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/i915/display/intel_audio.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v4_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.o
HDRTEST drivers/gpu/drm/xe/xe_irq.h
HDRTEST drivers/gpu/drm/xe/xe_lrc.h
HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.o
HDRTEST drivers/gpu/drm/xe/xe_macros.h
HDRTEST drivers/gpu/drm/xe/xe_map.h
HDRTEST drivers/gpu/drm/xe/xe_migrate.h
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.o
HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h
HDRTEST drivers/gpu/drm/xe/xe_mmio.h
CC [M] drivers/gpu/drm/i915/display/intel_bios.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.o
HDRTEST drivers/gpu/drm/xe/xe_mocs.h
HDRTEST drivers/gpu/drm/xe/xe_module.h
HDRTEST drivers/gpu/drm/xe/xe_pat.h
HDRTEST drivers/gpu/drm/xe/xe_pci.h
HDRTEST drivers/gpu/drm/xe/xe_pci_types.h
HDRTEST drivers/gpu/drm/xe/xe_pcode.h
CC [M] drivers/gpu/drm/i915/display/intel_bw.o
HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h
CC [M] drivers/gpu/drm/i915/display/intel_cdclk.o
HDRTEST drivers/gpu/drm/xe/xe_platform_types.h
HDRTEST drivers/gpu/drm/xe/xe_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.o
CC [M] drivers/gpu/drm/i915/display/intel_color.o
CC [M] drivers/gpu/drm/i915/display/intel_combo_phy.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v1_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v2_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v2_5.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.o
CC [M] drivers/gpu/drm/i915/display/intel_connector.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v3_0.o
HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h
CC [M] drivers/gpu/drm/i915/display/intel_crtc.o
CC [M] drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v4_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.o
CC [M] drivers/gpu/drm/i915/display/intel_cursor.o
CC [M] drivers/gpu/drm/i915/display/intel_display.o
HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h
HDRTEST drivers/gpu/drm/xe/xe_pt.h
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.o
HDRTEST drivers/gpu/drm/xe/xe_pt_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power_map.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power_well.o
CC [M] drivers/gpu/drm/i915/display/intel_display_rps.o
HDRTEST drivers/gpu/drm/xe/xe_query.h
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.o
HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h
CC [M] drivers/gpu/drm/i915/display/intel_dmc.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.o
CC [M] drivers/gpu/drm/i915/display/intel_dpio_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.o
CC [M] drivers/gpu/drm/i915/display/intel_dpll.o
HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h
HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h
HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h
HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v1_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v2_0.o
CC [M] drivers/gpu/drm/i915/display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.o
CC [M] drivers/gpu/drm/i915/display/intel_dpt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.o
CC [M] drivers/gpu/drm/i915/display/intel_drrs.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v2_1.o
HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h
HDRTEST drivers/gpu/drm/xe/xe_rtp.h
CC [M] drivers/gpu/drm/i915/display/intel_dsb.o
CC [M] drivers/gpu/drm/i915/display/intel_fb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.o
CC [M] drivers/gpu/drm/i915/display/intel_fb_pin.o
CC [M] drivers/gpu/drm/i915/display/intel_fbc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.o
HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h
HDRTEST drivers/gpu/drm/xe/xe_sa.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.o
CC [M] drivers/gpu/drm/i915/display/intel_fdi.o
HDRTEST drivers/gpu/drm/xe/xe_sa_types.h
HDRTEST drivers/gpu/drm/xe/xe_sched_job.h
CC [M] drivers/gpu/drm/i915/display/intel_fifo_underrun.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v3_0.o
CC [M] drivers/gpu/drm/i915/display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v9_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v11_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_reset.o
CC [M] drivers/gpu/drm/i915/display/intel_global_state.o
CC [M] drivers/gpu/drm/amd/amdgpu/mca_v3_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_module.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.o
CC [M] drivers/gpu/drm/i915/display/intel_hdcp.o
HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.o
HDRTEST drivers/gpu/drm/xe/xe_step.h
HDRTEST drivers/gpu/drm/xe/xe_step_types.h
HDRTEST drivers/gpu/drm/xe/xe_sync.h
HDRTEST drivers/gpu/drm/xe/xe_sync_types.h
HDRTEST drivers/gpu/drm/xe/xe_trace.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_pasid.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.o
CC [M] drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
HDRTEST drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.o
HDRTEST drivers/gpu/drm/xe/xe_ttm_sys_mgr.h
CC [M] drivers/gpu/drm/i915/display/intel_hotplug.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.o
HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
CC [M] drivers/gpu/drm/i915/display/intel_hti.o
CC [M] drivers/gpu/drm/i915/display/intel_lpe_audio.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_flat_memory.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.o
CC [M] drivers/gpu/drm/i915/display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/i915/display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_cik.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.o
CC [M] drivers/gpu/drm/i915/display/intel_overlay.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v9.o
CC [M] drivers/gpu/drm/i915/display/intel_pch_display.o
CC [M] drivers/gpu/drm/i915/display/intel_pch_refclk.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v11.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue.o
CC [M] drivers/gpu/drm/i915/display/intel_plane_initial.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager.o
HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
HDRTEST drivers/gpu/drm/xe/xe_tuning.h
HDRTEST drivers/gpu/drm/xe/xe_uc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.o
CC [M] drivers/gpu/drm/i915/display/intel_psr.o
CC [M] drivers/gpu/drm/i915/display/intel_quirks.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_vi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_v9.o
CC [M] drivers/gpu/drm/i915/display/intel_sprite.o
CC [M] drivers/gpu/drm/i915/display/intel_sprite_uapi.o
HDRTEST drivers/gpu/drm/xe/xe_uc_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process_queue_manager.o
HDRTEST drivers/gpu/drm/xe/xe_uc_fw.h
HDRTEST drivers/gpu/drm/xe/xe_uc_fw_abi.h
HDRTEST drivers/gpu/drm/xe/xe_uc_fw_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.o
HDRTEST drivers/gpu/drm/xe/xe_uc_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.o
CC [M] drivers/gpu/drm/i915/display/intel_tc.o
CC [M] drivers/gpu/drm/i915/display/intel_vblank.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_cik.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.o
CC [M] drivers/gpu/drm/i915/display/intel_vga.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_vi.o
HDRTEST drivers/gpu/drm/xe/xe_vm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v9.o
CC [M] drivers/gpu/drm/i915/display/intel_wm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v10.o
CC [M] drivers/gpu/drm/i915/display/i9xx_plane.o
HDRTEST drivers/gpu/drm/xe/xe_vm_doc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v11.o
HDRTEST drivers/gpu/drm/xe/xe_vm_madvise.h
HDRTEST drivers/gpu/drm/xe/xe_vm_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.o
CC [M] drivers/gpu/drm/i915/display/i9xx_wm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/cik_event_interrupt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.o
CC [M] drivers/gpu/drm/i915/display/skl_scaler.o
CC [M] drivers/gpu/drm/i915/display/skl_universal_plane.o
HDRTEST drivers/gpu/drm/xe/xe_wa.h
HDRTEST drivers/gpu/drm/xe/xe_wait_user_fence.h
HDRTEST drivers/gpu/drm/xe/xe_wopcm.h
HDRTEST drivers/gpu/drm/xe/xe_wopcm_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.o
LD [M] drivers/gpu/drm/xe/xe.o
CC [M] drivers/gpu/drm/i915/display/skl_watermark.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.o
CC [M] drivers/gpu/drm/i915/display/intel_acpi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.o
CC [M] drivers/gpu/drm/i915/display/intel_opregion.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.o
CC [M] drivers/gpu/drm/i915/display/intel_fbdev.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.o
CC [M] drivers/gpu/drm/i915/display/dvo_ch7017.o
CC [M] drivers/gpu/drm/i915/display/dvo_ch7xxx.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.o
CC [M] drivers/gpu/drm/i915/display/dvo_ivch.o
CC [M] drivers/gpu/drm/i915/display/dvo_ns2501.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.o
CC [M] drivers/gpu/drm/i915/display/dvo_sil164.o
drivers/gpu/drm/xe/xe.o: warning: objtool: intel_set_cpu_fifo_underrun_reporting+0x2b7: unreachable instruction
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.o
CC [M] drivers/gpu/drm/i915/display/dvo_tfp410.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_job.o
CC [M] drivers/gpu/drm/i915/display/g4x_dp.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_acp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../acp/acp_hw.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.o
CC [M] drivers/gpu/drm/i915/display/g4x_hdmi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.o
CC [M] drivers/gpu/drm/i915/display/icl_dsi.o
CC [M] drivers/gpu/drm/i915/display/intel_backlight.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/arcturus_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.o
CC [M] drivers/gpu/drm/i915/display/intel_crt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.o
CC [M] drivers/gpu/drm/i915/display/intel_ddi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/cyan_skillfish_ppt.o
CC [M] drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/smu_v11_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/renoir_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/smu_v12_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.o
CC [M] drivers/gpu/drm/i915/display/intel_display_trace.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.o
CC [M] drivers/gpu/drm/i915/display/intel_dkl_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.o
CC [M] drivers/gpu/drm/i915/display/intel_dp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_aux.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_0_ppt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_4_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_5_ppt.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_7_ppt.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_link_training.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu8_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_mst.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.o
CC [M] drivers/gpu/drm/i915/display/intel_dsi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/tonga_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/fiji_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/polaris10_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/iceland_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu7_smumgr.o
CC [M] drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
CC [M] drivers/gpu/drm/i915/display/intel_dsi_vbt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.o
CC [M] drivers/gpu/drm/i915/display/intel_dvo.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega10_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.o
CC [M] drivers/gpu/drm/i915/display/intel_gmbus.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu10_smumgr.o
CC [M] drivers/gpu/drm/i915/display/intel_hdmi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/ci_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega12_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vegam_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu9_smumgr.o
CC [M] drivers/gpu/drm/i915/display/intel_lspcon.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.o
CC [M] drivers/gpu/drm/i915/display/intel_lvds.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega20_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hwmgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.o
CC [M] drivers/gpu/drm/i915/display/intel_panel.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/processpptables.o
CC [M] drivers/gpu/drm/i915/display/intel_pps.o
CC [M] drivers/gpu/drm/i915/display/intel_qp_tables.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.o
CC [M] drivers/gpu/drm/i915/display/intel_sdvo.o
CC [M] drivers/gpu/drm/i915/display/intel_snps_phy.o
CC [M] drivers/gpu/drm/i915/display/intel_tv.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu8_hwmgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pppcielanes.o
CC [M] drivers/gpu/drm/i915/display/intel_vdsc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/process_pptables_v1_0.o
CC [M] drivers/gpu/drm/i915/display/intel_vrr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.o
CC [M] drivers/gpu/drm/i915/display/vlv_dsi.o
CC [M] drivers/gpu/drm/i915/display/vlv_dsi_pll.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomfwctrl.o
CC [M] drivers/gpu/drm/i915/i915_perf.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_powertune.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_thermal.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_clockpowergating.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_processpptables.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_cmd.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_powertune.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_thermal.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu10_hwmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_psm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_processpptables.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_hwmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_thermal.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_irq.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_overdriver.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu_helper.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_pm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_processpptables.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_hwmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_powertune.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_session.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_thermal.o
CC [M] drivers/gpu/drm/i915/i915_gpu_error.o
CC [M] drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/common_baco.o
CC [M] drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.o
CC [M] drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_baco.o
CC [M] drivers/gpu/drm/i915/selftests/i915_random.o
CC [M] drivers/gpu/drm/i915/selftests/i915_selftest.o
CC [M] drivers/gpu/drm/i915/selftests/igt_atomic.o
CC [M] drivers/gpu/drm/i915/selftests/igt_flush_test.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_baco.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_baco.o
CC [M] drivers/gpu/drm/i915/selftests/igt_live_test.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu9_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/tonga_baco.o
CC [M] drivers/gpu/drm/i915/selftests/igt_mmap.o
CC [M] drivers/gpu/drm/i915/selftests/igt_reset.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/polaris_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/fiji_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ci_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/amd_powerplay.o
CC [M] drivers/gpu/drm/i915/selftests/igt_spinner.o
CC [M] drivers/gpu/drm/i915/selftests/librapl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.o
CC [M] drivers/gpu/drm/i915/i915_vgpu.o
HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.o
HDRTEST drivers/gpu/drm/i915/display/hsw_ips.h
HDRTEST drivers/gpu/drm/i915/display/g4x_hdmi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/legacy_dpm.o
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_overlay.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_dpm.o
HDRTEST drivers/gpu/drm/i915/display/intel_display.h
HDRTEST drivers/gpu/drm/i915/display/intel_dmc.h
HDRTEST drivers/gpu/drm/i915/display/intel_vga.h
HDRTEST drivers/gpu/drm/i915/display/intel_audio.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_smc.o
HDRTEST drivers/gpu/drm/i915/display/intel_lvds.h
HDRTEST drivers/gpu/drm/i915/display/intel_modeset_setup.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_dpm.o
HDRTEST drivers/gpu/drm/i915/display/intel_cdclk.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_smc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv4e.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_pm.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_limits.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv50.o
HDRTEST drivers/gpu/drm/i915/display/intel_hotplug.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.o
HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy.h
HDRTEST drivers/gpu/drm/i915/display/intel_atomic.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.o
HDRTEST drivers/gpu/drm/i915/display/intel_dpll.h
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_mst.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crtc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.o
HDRTEST drivers/gpu/drm/i915/display/g4x_dp.h
HDRTEST drivers/gpu/drm/i915/display/intel_tc.h
HDRTEST drivers/gpu/drm/i915/display/intel_frontbuffer.h
HDRTEST drivers/gpu/drm/i915/display/intel_dsi_vbt.h
HDRTEST drivers/gpu/drm/i915/display/intel_psr.h
HDRTEST drivers/gpu/drm/i915/display/intel_crt.h
HDRTEST drivers/gpu/drm/i915/display/intel_opregion.h
HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
HDRTEST drivers/gpu/drm/i915/display/i9xx_wm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.o
HDRTEST drivers/gpu/drm/i915/display/intel_global_state.h
HDRTEST drivers/gpu/drm/i915/display/intel_lpe_audio.h
HDRTEST drivers/gpu/drm/i915/display/intel_drrs.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_rps.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_color.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_services.o
HDRTEST drivers/gpu/drm/i915/display/intel_fbdev.h
HDRTEST drivers/gpu/drm/i915/display/intel_hdmi.h
HDRTEST drivers/gpu/drm/i915/display/intel_fdi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.o
HDRTEST drivers/gpu/drm/i915/display/intel_fb.h
HDRTEST drivers/gpu/drm/i915/display/intel_qp_tables.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.o
HDRTEST drivers/gpu/drm/i915/display/intel_vdsc.h
HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_core.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.o
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.o
HDRTEST drivers/gpu/drm/i915/display/intel_dvo_dev.h
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.o
HDRTEST drivers/gpu/drm/i915/display/intel_sdvo_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crc.o
HDRTEST drivers/gpu/drm/i915/display/intel_pch_refclk.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_trace.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_power.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.o
HDRTEST drivers/gpu/drm/i915/display/i9xx_plane.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/conversion.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/fixpt31_32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/vector.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_backlight.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.o
HDRTEST drivers/gpu/drm/i915/display/intel_dpll_mgr.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_interface.o
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.o
HDRTEST drivers/gpu/drm/i915/display/intel_plane_initial.h
HDRTEST drivers/gpu/drm/i915/display/intel_fifo_underrun.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.o
HDRTEST drivers/gpu/drm/i915/display/intel_cursor.h
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_regs.h
HDRTEST drivers/gpu/drm/i915/display/skl_scaler.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.o
HDRTEST drivers/gpu/drm/i915/display/intel_hti.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.o
HDRTEST drivers/gpu/drm/i915/display/icl_dsi_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_atomic_plane.h
HDRTEST drivers/gpu/drm/i915/display/skl_watermark.h
HDRTEST drivers/gpu/drm/i915/display/intel_fbc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_reg_defs.h
HDRTEST drivers/gpu/drm/i915/display/intel_acpi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.o
HDRTEST drivers/gpu/drm/i915/display/intel_connector.h
HDRTEST drivers/gpu/drm/i915/display/intel_dpt.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_common.o
HDRTEST drivers/gpu/drm/i915/display/intel_quirks.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_link_training.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table2.o
HDRTEST drivers/gpu/drm/i915/display/intel_color.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper2.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce60/command_table_helper_dce60.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.o
HDRTEST drivers/gpu/drm/i915/display/intel_crtc.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.o
HDRTEST drivers/gpu/drm/i915/display/intel_modeset_verify.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper_dce112.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper2_dce112.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_power_well.h
HDRTEST drivers/gpu/drm/i915/display/intel_wm.h
HDRTEST drivers/gpu/drm/i915/display/intel_pipe_crc.h
HDRTEST drivers/gpu/drm/i915/display/intel_audio_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dce_calcs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.o
HDRTEST drivers/gpu/drm/i915/display/intel_panel.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/custom_float.o
HDRTEST drivers/gpu/drm/i915/display/intel_sprite.h
HDRTEST drivers/gpu/drm/i915/display/intel_wm_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/bw_fixed.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_rq_dlg_helpers.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.o
HDRTEST drivers/gpu/drm/i915/display/intel_tv.h
HDRTEST drivers/gpu/drm/i915/display/intel_hti_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.o
HDRTEST drivers/gpu/drm/i915/display/intel_vrr.h
HDRTEST drivers/gpu/drm/i915/display/skl_universal_plane.h
HDRTEST drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_bw.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dml1_display_rq_dlg_calc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn10/dcn10_fpu.o
HDRTEST drivers/gpu/drm/i915/display/intel_de.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_vba.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.o
HDRTEST drivers/gpu/drm/i915/display/intel_lvds_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_rq_dlg_calc_21.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_rq_dlg_calc_30.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.o
HDRTEST drivers/gpu/drm/i915/display/intel_gmbus_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.o
HDRTEST drivers/gpu/drm/i915/display/intel_dvo.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.o
HDRTEST drivers/gpu/drm/i915/display/intel_sdvo.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_rq_dlg_calc_31.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_mode_vba_314.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux.h
HDRTEST drivers/gpu/drm/i915/display/intel_vdsc_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.o
HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.o
HDRTEST drivers/gpu/drm/i915/display/intel_dvo_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.o
HDRTEST drivers/gpu/drm/i915/display/intel_gmbus.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.o
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn321/dcn321_fpu.o
HDRTEST drivers/gpu/drm/i915/display/intel_dsi.h
HDRTEST drivers/gpu/drm/i915/display/intel_dmc_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.o
HDRTEST drivers/gpu/drm/i915/display/intel_ddi.h
HDRTEST drivers/gpu/drm/i915/display/intel_dsb.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.o
HDRTEST drivers/gpu/drm/i915/display/intel_bios.h
HDRTEST drivers/gpu/drm/i915/display/intel_pch_display.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.o
HDRTEST drivers/gpu/drm/i915/display/intel_backlight.h
HDRTEST drivers/gpu/drm/i915/display/intel_vblank.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv04.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.o
HDRTEST drivers/gpu/drm/i915/display/intel_backlight_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_power_map.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn302/dcn302_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.o
HDRTEST drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
HDRTEST drivers/gpu/drm/i915/display/icl_dsi.h
HDRTEST drivers/gpu/drm/i915/display/intel_lspcon.h
HDRTEST drivers/gpu/drm/i915/display/intel_dpio_phy.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_hdcp.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.o
HDRTEST drivers/gpu/drm/i915/display/intel_fb_pin.h
HDRTEST drivers/gpu/drm/i915/display/intel_pps.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmmcp77.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dsc/rc_calc_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calcs.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_math.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_auto.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.o
HDRTEST drivers/gpu/drm/i915/display/intel_sprite_uapi.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce60/dce60_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_region.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context_types.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_lmem.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce100/dce_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce110/dce110_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_mman.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce112/dce112_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce120/dce120_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_clflush.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_tiling.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_stolen.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_create.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_move.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv2_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_domain.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_internal.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_context.h
HDRTEST drivers/gpu/drm/i915/gem/selftests/huge_gem_object.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_gem_object.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/dcn301_smu.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_userptr.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_pm.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gemfs.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.o
HDRTEST drivers/gpu/drm/i915/gt/intel_timeline_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_smu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.o
HDRTEST drivers/gpu/drm/i915/gt/selftest_engine.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.o
HDRTEST drivers/gpu/drm/i915/gt/intel_context_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_execlists_submission.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_smu.o
HDRTEST drivers/gpu/drm/i915/gt/selftest_rc6.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_llc_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt.h
HDRTEST drivers/gpu/drm/i915/gt/intel_region_lmem.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_requests.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_audio.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_link_encoder.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_scl_filters.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_print.h
HDRTEST drivers/gpu/drm/i915/gt/gen8_ppgtt.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_dmcu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_mcr.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.o
HDRTEST drivers/gpu/drm/i915/gt/intel_timeline.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_abm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_ipp.o
HDRTEST drivers/gpu/drm/i915/gt/gen6_engine_cs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.o
HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.o
HDRTEST drivers/gpu/drm/i915/gt/selftest_rps.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.o
HDRTEST drivers/gpu/drm/i915/gt/intel_sa_media.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h
HDRTEST drivers/gpu/drm/i915/gt/intel_rps_types.h
HDRTEST drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h
HDRTEST drivers/gpu/drm/i915/gt/sysfs_engines.h
HDRTEST drivers/gpu/drm/i915/gt/gen7_renderclear.h
HDRTEST drivers/gpu/drm/i915/gt/intel_context.h
HDRTEST drivers/gpu/drm/i915/gt/intel_wopcm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c.o
HDRTEST drivers/gpu/drm/i915/gt/intel_mocs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_hw.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_sw.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_psr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_panel_cntl.o
HDRTEST drivers/gpu/drm/i915/gt/intel_rc6.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ring_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_hw_lock_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_outbox.o
HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.o
HDRTEST drivers/gpu/drm/i915/gt/shmem_utils.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine.h
HDRTEST drivers/gpu/drm/i915/gt/intel_reset_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.o
HDRTEST drivers/gpu/drm/i915/gt/intel_reset.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
HDRTEST drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_factory.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_gpio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_hpd.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_ddc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_generic.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_translate.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce60/hw_translate_dce60.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce60/hw_factory_dce60.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_translate_dce80.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_factory_dce80.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_translate_dce110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_factory_dce110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_translate_dce120.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_factory_dce120.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_translate_dcn10.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_factory_dcn10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_translate_dcn20.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_factory_dcn20.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_translate_dcn21.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_factory_dcn21.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn30/hw_translate_dcn30.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn30/hw_factory_dcn30.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn315/hw_translate_dcn315.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn315/hw_factory_dcn315.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn32/hw_translate_dcn32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn32/hw_factory_dcn32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/irq_service.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce60/irq_service_dce60.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce80/irq_service_dce80.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce110/irq_service_dce110.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce120/irq_service_dce120.o
HDRTEST drivers/gpu/drm/i915/gt/intel_hwconfig.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn10/irq_service_dcn10.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn20/irq_service_dcn20.o
HDRTEST drivers/gpu/drm/i915/gt/intel_llc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.o
HDRTEST drivers/gpu/drm/i915/gt/gen8_engine_cs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_sseu_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_rc6_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/uvfn.o
HDRTEST drivers/gpu/drm/i915/gt/intel_context_param.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn30/irq_service_dcn30.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gpu_commands.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_user.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_irq.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gsc.h
HDRTEST drivers/gpu/drm/i915/gt/intel_rps.h
HDRTEST drivers/gpu/drm/i915/gt/selftest_llc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn302/irq_service_dcn302.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn303/irq_service_dcn303.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/tu102.o
HDRTEST drivers/gpu/drm/i915/gt/gen6_ppgtt.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
HDRTEST drivers/gpu/drm/i915/gt/intel_migrate_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn31/irq_service_dcn31.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/ga100.o
HDRTEST drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
HDRTEST drivers/gpu/drm/i915/gt/intel_lrc.h
HDRTEST drivers/gpu/drm/i915/gt/intel_lrc_reg.h
HDRTEST drivers/gpu/drm/i915/gt/intel_migrate.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn314/irq_service_dcn314.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn315/irq_service_dcn315.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn32/irq_service_dcn32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_detection.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.o
HDRTEST drivers/gpu/drm/i915/gt/mock_engine.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_stats.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_resource.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/accessories/link_dp_trace.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/accessories/link_dp_cts.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/accessories/link_fpga.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/falcon.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gtt.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/hwss/link_hwss_dio.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/hwss/link_hwss_dpia.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/hwss/link_hwss_hpo_dp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_hpd.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_ddc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/xtensa.o
HDRTEST drivers/gpu/drm/i915/gt/intel_ring.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_renderstate.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.o
HDRTEST drivers/gpu/drm/i915/gt/intel_sseu.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dpcd.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_dpia.o
HDRTEST drivers/gpu/drm/i915/gt/gen2_engine_cs.h
HDRTEST drivers/gpu/drm/i915/gvt/gvt.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_8b_10b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_128b_132b.o
HDRTEST drivers/gpu/drm/i915/gvt/trace.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_dpia.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.o
HDRTEST drivers/gpu/drm/i915/gvt/debug.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_auxless.o
HDRTEST drivers/gpu/drm/i915/gvt/edid.h
HDRTEST drivers/gpu/drm/i915/gvt/page_track.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.o
HDRTEST drivers/gpu/drm/i915/gvt/mmio.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.o
HDRTEST drivers/gpu/drm/i915/gvt/sched_policy.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.o
HDRTEST drivers/gpu/drm/i915/gvt/fb_decoder.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.o
HDRTEST drivers/gpu/drm/i915/gvt/cmd_parser.h
HDRTEST drivers/gpu/drm/i915/gvt/dmabuf.h
HDRTEST drivers/gpu/drm/i915/gvt/mmio_context.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_edp_panel_control.o
HDRTEST drivers/gpu/drm/i915/gvt/display.h
HDRTEST drivers/gpu/drm/i915/gvt/gtt.h
HDRTEST drivers/gpu/drm/i915/gvt/scheduler.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_irq_handler.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_dpia_bw.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/virtual/virtual_link_encoder.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/virtual/virtual_stream_encoder.o
HDRTEST drivers/gpu/drm/i915/gvt/reg.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.o
HDRTEST drivers/gpu/drm/i915/gvt/execlist.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/virtual/virtual_link_hwss.o
HDRTEST drivers/gpu/drm/i915/gvt/interrupt.h
HDRTEST drivers/gpu/drm/i915/i915_active.h
HDRTEST drivers/gpu/drm/i915/i915_active_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/ga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.o
HDRTEST drivers/gpu/drm/i915/i915_cmd_parser.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/rc_calc.o
HDRTEST drivers/gpu/drm/i915/i915_config.h
HDRTEST drivers/gpu/drm/i915/i915_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/rc_calc_dpi.o
HDRTEST drivers/gpu/drm/i915/i915_debugfs_params.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_init.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.o
HDRTEST drivers/gpu/drm/i915/i915_deps.h
HDRTEST drivers/gpu/drm/i915/i915_driver.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.o
HDRTEST drivers/gpu/drm/i915/i915_drm_client.h
HDRTEST drivers/gpu/drm/i915/i915_drv.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.o
HDRTEST drivers/gpu/drm/i915/i915_file_private.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp_cm.o
HDRTEST drivers/gpu/drm/i915/i915_fixed.h
HDRTEST drivers/gpu/drm/i915/i915_gem.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.o
HDRTEST drivers/gpu/drm/i915/i915_gem_evict.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/pci.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_mpc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_opp.o
HDRTEST drivers/gpu/drm/i915/i915_gem_gtt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/user.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubbub.o
HDRTEST drivers/gpu/drm/i915/i915_gem_ww.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/base.o
HDRTEST drivers/gpu/drm/i915/i915_getparam.h
HDRTEST drivers/gpu/drm/i915/i915_gpu_error.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_mmhubbub.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.o
HDRTEST drivers/gpu/drm/i915/i915_hwmon.h
HDRTEST drivers/gpu/drm/i915/i915_ioc32.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.o
HDRTEST drivers/gpu/drm/i915/i915_ioctl.h
HDRTEST drivers/gpu/drm/i915/i915_iosf_mbi.h
HDRTEST drivers/gpu/drm/i915/i915_irq.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_stream_encoder.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.o
HDRTEST drivers/gpu/drm/i915/i915_memcpy.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.o
HDRTEST drivers/gpu/drm/i915/i915_mitigations.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dccg.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_vmid.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/head.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dwb.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dwb_scl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.o
HDRTEST drivers/gpu/drm/i915/i915_mm.h
HDRTEST drivers/gpu/drm/i915/i915_params.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dsc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_init.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_resource.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_ipp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer_debug.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_opp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_optc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.o
HDRTEST drivers/gpu/drm/i915/i915_pci.h
HDRTEST drivers/gpu/drm/i915/i915_perf.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.o
HDRTEST drivers/gpu/drm/i915/i915_perf_oa_regs.h
HDRTEST drivers/gpu/drm/i915/i915_perf_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_mpc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp_dscl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.o
HDRTEST drivers/gpu/drm/i915/i915_pmu.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp_cm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_cm_common.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubbub.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_stream_encoder.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_init.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubp.o
HDRTEST drivers/gpu/drm/i915/i915_priolist_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubbub.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.o
HDRTEST drivers/gpu/drm/i915/i915_pvinfo.h
HDRTEST drivers/gpu/drm/i915/i915_query.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.o
HDRTEST drivers/gpu/drm/i915/i915_reg.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.o
HDRTEST drivers/gpu/drm/i915/i915_reg_defs.h
HDRTEST drivers/gpu/drm/i915/i915_request.h
HDRTEST drivers/gpu/drm/i915/i915_scatterlist.h
HDRTEST drivers/gpu/drm/i915/i915_scheduler.h
HDRTEST drivers/gpu/drm/i915/i915_scheduler_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.o
HDRTEST drivers/gpu/drm/i915/i915_selftest.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_link_encoder.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_dccg.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/base.o
HDRTEST drivers/gpu/drm/i915/i915_suspend.h
HDRTEST drivers/gpu/drm/i915/i915_sw_fence.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_init.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.o
HDRTEST drivers/gpu/drm/i915/i915_sw_fence_work.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/user.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.o
HDRTEST drivers/gpu/drm/i915/i915_switcheroo.h
HDRTEST drivers/gpu/drm/i915/i915_syncmap.h
HDRTEST drivers/gpu/drm/i915/i915_sysfs.h
HDRTEST drivers/gpu/drm/i915/i915_tasklet.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.o
HDRTEST drivers/gpu/drm/i915/i915_trace.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hubbub.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_mpc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.o
HDRTEST drivers/gpu/drm/i915/i915_ttm_buddy_manager.h
HDRTEST drivers/gpu/drm/i915/i915_user_extensions.h
HDRTEST drivers/gpu/drm/i915/i915_utils.h
HDRTEST drivers/gpu/drm/i915/i915_vgpu.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.o
HDRTEST drivers/gpu/drm/i915/i915_vma.h
HDRTEST drivers/gpu/drm/i915/i915_vma_resource.h
HDRTEST drivers/gpu/drm/i915/i915_vma_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hubp.o
HDRTEST drivers/gpu/drm/i915/intel_clock_gating.h
HDRTEST drivers/gpu/drm/i915/intel_device_info.h
HDRTEST drivers/gpu/drm/i915/intel_gvt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.o
HDRTEST drivers/gpu/drm/i915/intel_mchbar_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.o
HDRTEST drivers/gpu/drm/i915/intel_memory_region.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chid.o
HDRTEST drivers/gpu/drm/i915/intel_pci_config.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_opp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/runq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_optc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.o
HDRTEST drivers/gpu/drm/i915/intel_pcode.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.o
HDRTEST drivers/gpu/drm/i915/intel_region_ttm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dccg.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_link_encoder.o
HDRTEST drivers/gpu/drm/i915/intel_runtime_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_init.o
HDRTEST drivers/gpu/drm/i915/intel_sbi.h
HDRTEST drivers/gpu/drm/i915/intel_step.h
HDRTEST drivers/gpu/drm/i915/intel_uncore.h
HDRTEST drivers/gpu/drm/i915/intel_wakeref.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubbub.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_session.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/g98.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dpp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_types.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
HDRTEST drivers/gpu/drm/i915/selftests/igt_live_test.h
HDRTEST drivers/gpu/drm/i915/selftests/igt_atomic.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_gem_device.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_drm.h
HDRTEST drivers/gpu/drm/i915/selftests/igt_reset.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.o
HDRTEST drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dccg.o
HDRTEST drivers/gpu/drm/i915/selftests/lib_sw_fence.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.o
HDRTEST drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_uncore.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mpc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_vpg.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.o
HDRTEST drivers/gpu/drm/i915/selftests/mock_gtt.h
HDRTEST drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_afmt.o
HDRTEST drivers/gpu/drm/i915/selftests/mock_request.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.o
HDRTEST drivers/gpu/drm/i915/selftests/i915_random.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.o
HDRTEST drive
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-xe] ○ CI.BAT: info for Convert xe_mmio to struct xe_reg
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
` (9 preceding siblings ...)
2023-04-29 6:32 ` [Intel-xe] ✓ CI.Build: " Patchwork
@ 2023-04-29 6:58 ` Patchwork
10 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-04-29 6:58 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 328 bytes --]
== Series Details ==
Series: Convert xe_mmio to struct xe_reg
URL : https://patchwork.freedesktop.org/series/117138/
State : info
== Summary ==
Participating hosts:
bat-atsm-2
bat-dg2-oem2
bat-adlp-7
Missing hosts results[0]:
Results: [xe-pw-117138v1](https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-117138v1/index.html)
[-- Attachment #2: Type: text/html, Size: 838 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 3/7] drm/xe: Use media base for GMD_ID access
2023-04-29 6:23 ` [Intel-xe] [PATCH 3/7] drm/xe: Use media base for GMD_ID access Lucas De Marchi
@ 2023-04-30 17:47 ` Michal Wajdeczko
2023-05-01 15:07 ` Lucas De Marchi
0 siblings, 1 reply; 27+ messages in thread
From: Michal Wajdeczko @ 2023-04-30 17:47 UTC (permalink / raw)
To: Lucas De Marchi, intel-xe
On 29.04.2023 08:23, Lucas De Marchi wrote:
> Instead of adding a hardcoded base, define GMD_ID() with a base
> argument and use it in all places.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +++-
> drivers/gpu/drm/xe/xe_pci.c | 9 +++++----
> 2 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 4d87f1fe010d..da7b6d2c7e01 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -8,6 +8,8 @@
>
> #include "regs/xe_reg_defs.h"
>
> +#define MTL_MEDIA_GT_BASE 0x380000
maybe for completeness (and to avoid using anonymous 0 offset in other
places) we should define also:
#define GRAPHICS_GT_BASE 0x0
> +
> /* RPM unit config (Gen8+) */
> #define RPM_CONFIG0 XE_REG(0xd00)
> #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
> @@ -21,7 +23,7 @@
> #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4)
> #define FORCEWAKE_ACK_RENDER XE_REG(0xd84)
>
> -#define GMD_ID XE_REG(0xd8c)
> +#define GMD_ID(base) XE_REG((base) + 0xd8c)
this register is not the only one that's has it's counterpart at this
0x38000 MEDIA offset, and other registers we are treating in automatic
way, without the need to explicitly pass the 'base', so I'm not sure we
should change that here
> #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
> #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> #define GMD_ID_STEP REG_GENMASK(5, 0)
btw, is there a plan to s/REG_GENMASK/XE_REG_GENMASK or something ?
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 35dcb8781f2a..8687e51cb0a4 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -276,7 +276,7 @@ static const struct xe_gt_desc xelpmp_gts[] = {
> .type = XE_GT_TYPE_MEDIA,
> .vram_id = 0,
> .mmio_adj_limit = 0x40000,
> - .mmio_adj_offset = 0x380000,
> + .mmio_adj_offset = MTL_MEDIA_GT_BASE,
> },
> };
>
> @@ -391,8 +391,9 @@ find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
> return NULL;
> }
>
> -static u32 peek_gmdid(struct xe_device *xe, u32 gmdid_offset)
> +static u32 peek_gmdid(struct xe_device *xe, struct xe_reg gmdid_reg)
better to keep u32 but defined as new 'base' for the GMD_ID:
peek_gmdid(xe, GRAPHICS_GT_BASE)
peek_gmdid(xe, MTL_MEDIA_GT_BASE)
then since we parse the value according to the GMDID definition we will
prevent passing wrong register offset and always refer to the right
GMD_ID address inside the function:
static u32 peek_gmdid(struct xe_device *xe, u32 base)
{
xe_reg gmdid = XE_REG(GMD_ID.addr + base);
...
WARN_ON(base != GRAPHICS_GT_BASE && base != MTL_MEDIA_GT_BASE);
...
map = pci_iomap_range(pdev, 0, gmdid.addr, sizeof(u32));
...
REG_FIELD_GET(GMD_ID_ARCH_MASK, value)
Michal
> {
> + u32 gmdid_offset = gmdid_reg.reg;
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> void __iomem *map = pci_iomap_range(pdev, 0, gmdid_offset, sizeof(u32));
> u32 ver;
> @@ -441,7 +442,7 @@ static void handle_gmdid(struct xe_device *xe,
> {
> u32 ver;
>
> - ver = peek_gmdid(xe, GMD_ID.reg);
> + ver = peek_gmdid(xe, GMD_ID(0));
> for (int i = 0; i < ARRAY_SIZE(graphics_ip_map); i++) {
> if (ver == graphics_ip_map[i].ver) {
> xe->info.graphics_verx100 = ver;
> @@ -456,7 +457,7 @@ static void handle_gmdid(struct xe_device *xe,
> ver / 100, ver % 100);
> }
>
> - ver = peek_gmdid(xe, GMD_ID.reg + 0x380000);
> + ver = peek_gmdid(xe, GMD_ID(MTL_MEDIA_GT_BASE));
> for (int i = 0; i < ARRAY_SIZE(media_ip_map); i++) {
> if (ver == media_ip_map[i].ver) {
> xe->info.media_verx100 = ver;
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 3/7] drm/xe: Use media base for GMD_ID access
2023-04-30 17:47 ` Michal Wajdeczko
@ 2023-05-01 15:07 ` Lucas De Marchi
2023-05-05 17:05 ` Rodrigo Vivi
0 siblings, 1 reply; 27+ messages in thread
From: Lucas De Marchi @ 2023-05-01 15:07 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-xe
On Sun, Apr 30, 2023 at 07:47:38PM +0200, Michal Wajdeczko wrote:
>
>
>On 29.04.2023 08:23, Lucas De Marchi wrote:
>> Instead of adding a hardcoded base, define GMD_ID() with a base
>> argument and use it in all places.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +++-
>> drivers/gpu/drm/xe/xe_pci.c | 9 +++++----
>> 2 files changed, 8 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 4d87f1fe010d..da7b6d2c7e01 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -8,6 +8,8 @@
>>
>> #include "regs/xe_reg_defs.h"
>>
>> +#define MTL_MEDIA_GT_BASE 0x380000
>
>maybe for completeness (and to avoid using anonymous 0 offset in other
>places) we should define also:
>
>#define GRAPHICS_GT_BASE 0x0
there are very vew places in the driver that would care about the base.
Today the base is automatically applied for anything using xe_mmio_,
just like we have it automatically applied in intel_uncore for i915.
So, we really don't want to change each register to receive base as
param.
>
>> +
>> /* RPM unit config (Gen8+) */
>> #define RPM_CONFIG0 XE_REG(0xd00)
>> #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
>> @@ -21,7 +23,7 @@
>> #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4)
>> #define FORCEWAKE_ACK_RENDER XE_REG(0xd84)
>>
>> -#define GMD_ID XE_REG(0xd8c)
>> +#define GMD_ID(base) XE_REG((base) + 0xd8c)
>
>this register is not the only one that's has it's counterpart at this
>0x38000 MEDIA offset, and other registers we are treating in automatic
>way, without the need to explicitly pass the 'base', so I'm not sure we
>should change that here
becaues in the other cases the base is applied by xe_mmio
>
>> #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
>> #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
>> #define GMD_ID_STEP REG_GENMASK(5, 0)
>
>btw, is there a plan to s/REG_GENMASK/XE_REG_GENMASK or something ?
no. My plan is to eventually submit a patch to have
GENMASK_U32 and use it throughout the driver
>
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index 35dcb8781f2a..8687e51cb0a4 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -276,7 +276,7 @@ static const struct xe_gt_desc xelpmp_gts[] = {
>> .type = XE_GT_TYPE_MEDIA,
>> .vram_id = 0,
>> .mmio_adj_limit = 0x40000,
>> - .mmio_adj_offset = 0x380000,
>> + .mmio_adj_offset = MTL_MEDIA_GT_BASE,
>> },
>> };
>>
>> @@ -391,8 +391,9 @@ find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
>> return NULL;
>> }
>>
>> -static u32 peek_gmdid(struct xe_device *xe, u32 gmdid_offset)
>> +static u32 peek_gmdid(struct xe_device *xe, struct xe_reg gmdid_reg)
>
>better to keep u32 but defined as new 'base' for the GMD_ID:
>
>peek_gmdid(xe, GRAPHICS_GT_BASE)
>peek_gmdid(xe, MTL_MEDIA_GT_BASE)
>
>then since we parse the value according to the GMDID definition we will
>prevent passing wrong register offset and always refer to the right
>GMD_ID address inside the function:
>
>static u32 peek_gmdid(struct xe_device *xe, u32 base)
>{
> xe_reg gmdid = XE_REG(GMD_ID.addr + base);
we try to minimize those calculations outside the header.
I don't see a benefit of passing the base here over passing the register
to be used.
Lucas De Marchi
>...
> WARN_ON(base != GRAPHICS_GT_BASE && base != MTL_MEDIA_GT_BASE);
>...
> map = pci_iomap_range(pdev, 0, gmdid.addr, sizeof(u32));
>...
> REG_FIELD_GET(GMD_ID_ARCH_MASK, value)
>
>
>Michal
>
>> {
>> + u32 gmdid_offset = gmdid_reg.reg;
>> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>> void __iomem *map = pci_iomap_range(pdev, 0, gmdid_offset, sizeof(u32));
>> u32 ver;
>> @@ -441,7 +442,7 @@ static void handle_gmdid(struct xe_device *xe,
>> {
>> u32 ver;
>>
>> - ver = peek_gmdid(xe, GMD_ID.reg);
>> + ver = peek_gmdid(xe, GMD_ID(0));
>> for (int i = 0; i < ARRAY_SIZE(graphics_ip_map); i++) {
>> if (ver == graphics_ip_map[i].ver) {
>> xe->info.graphics_verx100 = ver;
>> @@ -456,7 +457,7 @@ static void handle_gmdid(struct xe_device *xe,
>> ver / 100, ver % 100);
>> }
>>
>> - ver = peek_gmdid(xe, GMD_ID.reg + 0x380000);
>> + ver = peek_gmdid(xe, GMD_ID(MTL_MEDIA_GT_BASE));
>> for (int i = 0; i < ARRAY_SIZE(media_ip_map); i++) {
>> if (ver == media_ip_map[i].ver) {
>> xe->info.media_verx100 = ver;
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 2/7] drm/xe/guc: Handle RCU_MODE as masked from definition
2023-04-29 6:23 ` [Intel-xe] [PATCH 2/7] drm/xe/guc: Handle RCU_MODE as masked from definition Lucas De Marchi
@ 2023-05-05 16:55 ` Rodrigo Vivi
2023-05-05 17:08 ` Lucas De Marchi
0 siblings, 1 reply; 27+ messages in thread
From: Rodrigo Vivi @ 2023-05-05 16:55 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Fri, Apr 28, 2023 at 11:23:27PM -0700, Lucas De Marchi wrote:
> guc_mmio_regset_write() had a flags for the registers to be added to the
> GuC's regset list. The only register actually using that was RCU_MODE,
> but it was setting the flags to a bogus value. From
> struct xe_guc_fwif.h,
>
> #define GUC_REGSET_MASKED BIT(0)
> #define GUC_REGSET_MASKED_WITH_VALUE BIT(2)
> #define GUC_REGSET_RESTORE_ONLY BIT(3)
>
> Cross checking with i915, the only flag to set in RCU_MODE is
> GUC_REGSET_MASKED. That can be done automatically from the register, as
> long as the definition is correct.
>
> Add the XE_REG_OPTION_MASKED annotation to RCU_MODE and kill the "flags"
> field in guc_mmio_regset_write(): guc_mmio_regset_write_one() can decide
> that based on the register being passed.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
I'm still trying to get familiarized with XE_REG_OPTION_MASKED
but this patch looks right to me:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
> drivers/gpu/drm/xe/xe_guc_ads.c | 31 +++++++++++-----------------
> 2 files changed, 13 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 68e89d71cd1c..4d87f1fe010d 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -325,7 +325,7 @@
> #define SARB_CHICKEN1 XE_REG_MCR(0xe90c)
> #define COMP_CKN_IN REG_GENMASK(30, 29)
>
> -#define RCU_MODE XE_REG(0x14800)
> +#define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED)
> #define RCU_MODE_CCS_ENABLE REG_BIT(0)
>
> #define FORCEWAKE_ACK_GT XE_REG(0x130044)
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 676137dcb510..84c2d7c624c6 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -422,12 +422,12 @@ static void guc_capture_list_init(struct xe_guc_ads *ads)
>
> static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,
> struct iosys_map *regset_map,
> - u32 reg, u32 flags,
> + struct xe_reg reg,
> unsigned int n_entry)
> {
> struct guc_mmio_reg entry = {
> - .offset = reg,
> - .flags = flags,
> + .offset = reg.reg,
> + .flags = reg.masked ? GUC_REGSET_MASKED : 0,
> /* TODO: steering */
> };
>
> @@ -446,40 +446,33 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
> unsigned long idx;
> unsigned count = 0;
> const struct {
> - u32 reg;
> - u32 flags;
> + struct xe_reg reg;
> bool skip;
> } *e, extra_regs[] = {
> - { .reg = RING_MODE(hwe->mmio_base).reg, },
> - { .reg = RING_HWS_PGA(hwe->mmio_base).reg, },
> - { .reg = RING_IMR(hwe->mmio_base).reg, },
> - { .reg = RCU_MODE.reg, .flags = 0x3,
> - .skip = hwe != hwe_rcs_reset_domain },
> + { .reg = RING_MODE(hwe->mmio_base), },
> + { .reg = RING_HWS_PGA(hwe->mmio_base), },
> + { .reg = RING_IMR(hwe->mmio_base), },
> + { .reg = RCU_MODE, .skip = hwe != hwe_rcs_reset_domain },
> };
> u32 i;
>
> BUILD_BUG_ON(ARRAY_SIZE(extra_regs) > ADS_REGSET_EXTRA_MAX);
>
> - xa_for_each(&hwe->reg_sr.xa, idx, entry) {
> - u32 flags = entry->reg.masked ? GUC_REGSET_MASKED : 0;
> -
> - guc_mmio_regset_write_one(ads, regset_map, idx, flags, count++);
> - }
> + xa_for_each(&hwe->reg_sr.xa, idx, entry)
> + guc_mmio_regset_write_one(ads, regset_map, entry->reg, count++);
>
> for (e = extra_regs; e < extra_regs + ARRAY_SIZE(extra_regs); e++) {
> if (e->skip)
> continue;
>
> - guc_mmio_regset_write_one(ads, regset_map,
> - e->reg, e->flags, count++);
> + guc_mmio_regset_write_one(ads, regset_map, e->reg, count++);
> }
>
> /* Wa_1607983814 */
> if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) {
> for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) {
> guc_mmio_regset_write_one(ads, regset_map,
> - LNCFCMOCS(i).reg, 0,
> - count++);
> + LNCFCMOCS(i), count++);
> }
> }
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 1/7] fixup! drm/xe: Drop gen afixes from registers
2023-04-29 6:23 ` [Intel-xe] [PATCH 1/7] fixup! drm/xe: Drop gen afixes from registers Lucas De Marchi
@ 2023-05-05 16:55 ` Rodrigo Vivi
0 siblings, 0 replies; 27+ messages in thread
From: Rodrigo Vivi @ 2023-05-05 16:55 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Fri, Apr 28, 2023 at 11:23:26PM -0700, Lucas De Marchi wrote:
> Maybe an abuse of fixup, but easy enough not to deserve a separate
> commit.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 566b62815dab..795302bcd3ae 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -573,7 +573,7 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
> hw_engine_mmio_read32(hwe, IPEHR(0).reg));
>
> if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
> - drm_printf(p, "\tGEN12_RCU_MODE: 0x%08x\n",
> + drm_printf(p, "\tRCU_MODE: 0x%08x\n",
> xe_mmio_read32(hwe->gt, RCU_MODE.reg));
>
> }
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 4/7] drm/xe/mmio: Use struct xe_reg
2023-04-29 6:23 ` [Intel-xe] [PATCH 4/7] drm/xe/mmio: Use struct xe_reg Lucas De Marchi
@ 2023-05-05 16:57 ` Rodrigo Vivi
2023-05-05 19:26 ` Lucas De Marchi
0 siblings, 1 reply; 27+ messages in thread
From: Rodrigo Vivi @ 2023-05-05 16:57 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Fri, Apr 28, 2023 at 11:23:29PM -0700, Lucas De Marchi wrote:
> Convert all the callers to deal with xe_mmio_*() using struct xe_reg
> instead of plain u32. In a few places there was also a rename
> s/reg/reg_val/ when dealing with the value returned so it doesn't get
> mixed up with the register address.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
have you auto generated this?
is this the possible conflict after rebasing that you had raised?
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device.c | 2 +-
> drivers/gpu/drm/xe/xe_execlist.c | 18 +--
> drivers/gpu/drm/xe/xe_force_wake.c | 25 ++--
> drivers/gpu/drm/xe/xe_force_wake_types.h | 6 +-
> drivers/gpu/drm/xe/xe_ggtt.c | 6 +-
> drivers/gpu/drm/xe/xe_gt.c | 4 +-
> drivers/gpu/drm/xe/xe_gt_clock.c | 6 +-
> drivers/gpu/drm/xe/xe_gt_mcr.c | 37 +++---
> drivers/gpu/drm/xe/xe_gt_topology.c | 18 +--
> drivers/gpu/drm/xe/xe_guc.c | 61 +++++-----
> drivers/gpu/drm/xe/xe_guc_ads.c | 3 +-
> drivers/gpu/drm/xe/xe_guc_pc.c | 32 +++---
> drivers/gpu/drm/xe/xe_guc_types.h | 3 +-
> drivers/gpu/drm/xe/xe_huc.c | 4 +-
> drivers/gpu/drm/xe/xe_hw_engine.c | 85 +++++++-------
> drivers/gpu/drm/xe/xe_irq.c | 138 +++++++++++------------
> drivers/gpu/drm/xe/xe_mmio.c | 31 +++--
> drivers/gpu/drm/xe/xe_mmio.h | 47 ++++----
> drivers/gpu/drm/xe/xe_mocs.c | 7 +-
> drivers/gpu/drm/xe/xe_pat.c | 14 ++-
> drivers/gpu/drm/xe/xe_pcode.c | 16 +--
> drivers/gpu/drm/xe/xe_reg_sr.c | 14 ++-
> drivers/gpu/drm/xe/xe_ring_ops.c | 11 +-
> drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 4 +-
> drivers/gpu/drm/xe/xe_uc_fw.c | 16 +--
> drivers/gpu/drm/xe/xe_wopcm.c | 12 +-
> 26 files changed, 325 insertions(+), 295 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 45d6e5ff47fd..f7f4837ded37 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -393,7 +393,7 @@ void xe_device_wmb(struct xe_device *xe)
>
> wmb();
> if (IS_DGFX(xe))
> - xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33.reg, 0);
> + xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);
> }
>
> u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
> index de4f0044b211..5d2d26e361b9 100644
> --- a/drivers/gpu/drm/xe/xe_execlist.c
> +++ b/drivers/gpu/drm/xe/xe_execlist.c
> @@ -60,7 +60,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
> }
>
> if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
> - xe_mmio_write32(hwe->gt, RCU_MODE.reg,
> + xe_mmio_write32(hwe->gt, RCU_MODE,
> _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
>
> xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
> @@ -78,17 +78,17 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
> */
> wmb();
>
> - xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base).reg,
> + xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base),
> xe_bo_ggtt_addr(hwe->hwsp));
> - xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base).reg);
> - xe_mmio_write32(gt, RING_MODE(hwe->mmio_base).reg,
> + xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base));
> + xe_mmio_write32(gt, RING_MODE(hwe->mmio_base),
> _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
>
> - xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base).reg,
> + xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
> lower_32_bits(lrc_desc));
> - xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base).reg,
> + xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),
> upper_32_bits(lrc_desc));
> - xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base).reg,
> + xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base),
> EL_CTRL_LOAD);
> }
>
> @@ -173,8 +173,8 @@ static u64 read_execlist_status(struct xe_hw_engine *hwe)
> struct xe_gt *gt = hwe->gt;
> u32 hi, lo;
>
> - lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base).reg);
> - hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base).reg);
> + lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base));
> + hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base));
>
> printk(KERN_INFO "EXECLIST_STATUS %d:%d = 0x%08x %08x\n", hwe->class,
> hwe->instance, hi, lo);
> diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
> index 53d73f36a121..363b81c3d746 100644
> --- a/drivers/gpu/drm/xe/xe_force_wake.c
> +++ b/drivers/gpu/drm/xe/xe_force_wake.c
> @@ -8,6 +8,7 @@
> #include <drm/drm_util.h>
>
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_reg_defs.h"
> #include "xe_gt.h"
> #include "xe_mmio.h"
>
> @@ -27,7 +28,7 @@ fw_to_xe(struct xe_force_wake *fw)
>
> static void domain_init(struct xe_force_wake_domain *domain,
> enum xe_force_wake_domain_id id,
> - u32 reg, u32 ack, u32 val, u32 mask)
> + struct xe_reg reg, struct xe_reg ack, u32 val, u32 mask)
> {
> domain->id = id;
> domain->reg_ctl = reg;
> @@ -49,14 +50,14 @@ void xe_force_wake_init_gt(struct xe_gt *gt, struct xe_force_wake *fw)
> if (xe->info.graphics_verx100 >= 1270) {
> domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],
> XE_FW_DOMAIN_ID_GT,
> - FORCEWAKE_GT.reg,
> - FORCEWAKE_ACK_GT_MTL.reg,
> + FORCEWAKE_GT,
> + FORCEWAKE_ACK_GT_MTL,
> BIT(0), BIT(16));
> } else {
> domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],
> XE_FW_DOMAIN_ID_GT,
> - FORCEWAKE_GT.reg,
> - FORCEWAKE_ACK_GT.reg,
> + FORCEWAKE_GT,
> + FORCEWAKE_ACK_GT,
> BIT(0), BIT(16));
> }
> }
> @@ -71,8 +72,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
> if (!xe_gt_is_media_type(gt))
> domain_init(&fw->domains[XE_FW_DOMAIN_ID_RENDER],
> XE_FW_DOMAIN_ID_RENDER,
> - FORCEWAKE_RENDER.reg,
> - FORCEWAKE_ACK_RENDER.reg,
> + FORCEWAKE_RENDER,
> + FORCEWAKE_ACK_RENDER,
> BIT(0), BIT(16));
>
> for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
> @@ -81,8 +82,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
>
> domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j],
> XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j,
> - FORCEWAKE_MEDIA_VDBOX(j).reg,
> - FORCEWAKE_ACK_MEDIA_VDBOX(j).reg,
> + FORCEWAKE_MEDIA_VDBOX(j),
> + FORCEWAKE_ACK_MEDIA_VDBOX(j),
> BIT(0), BIT(16));
> }
>
> @@ -92,8 +93,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
>
> domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j],
> XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j,
> - FORCEWAKE_MEDIA_VEBOX(j).reg,
> - FORCEWAKE_ACK_MEDIA_VEBOX(j).reg,
> + FORCEWAKE_MEDIA_VEBOX(j),
> + FORCEWAKE_ACK_MEDIA_VEBOX(j),
> BIT(0), BIT(16));
> }
> }
> @@ -128,7 +129,7 @@ static int domain_sleep_wait(struct xe_gt *gt,
> for (tmp__ = (mask__); tmp__; tmp__ &= ~BIT(ffs(tmp__) - 1)) \
> for_each_if((domain__ = ((fw__)->domains + \
> (ffs(tmp__) - 1))) && \
> - domain__->reg_ctl)
> + domain__->reg_ctl.reg)
>
> int xe_force_wake_get(struct xe_force_wake *fw,
> enum xe_force_wake_domains domains)
> diff --git a/drivers/gpu/drm/xe/xe_force_wake_types.h b/drivers/gpu/drm/xe/xe_force_wake_types.h
> index 208dd629d7b1..cb782696855b 100644
> --- a/drivers/gpu/drm/xe/xe_force_wake_types.h
> +++ b/drivers/gpu/drm/xe/xe_force_wake_types.h
> @@ -9,6 +9,8 @@
> #include <linux/mutex.h>
> #include <linux/types.h>
>
> +#include "regs/xe_reg_defs.h"
> +
> enum xe_force_wake_domain_id {
> XE_FW_DOMAIN_ID_GT = 0,
> XE_FW_DOMAIN_ID_RENDER,
> @@ -56,9 +58,9 @@ struct xe_force_wake_domain {
> /** @id: domain force wake id */
> enum xe_force_wake_domain_id id;
> /** @reg_ctl: domain wake control register address */
> - u32 reg_ctl;
> + struct xe_reg reg_ctl;
> /** @reg_ack: domain ack register address */
> - u32 reg_ack;
> + struct xe_reg reg_ack;
> /** @val: domain wake write value */
> u32 val;
> /** @mask: domain mask */
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 9c08031c9350..546240261e0a 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -207,12 +207,12 @@ void xe_ggtt_invalidate(struct xe_gt *gt)
> struct xe_device *xe = gt_to_xe(gt);
>
> if (xe->info.platform == XE_PVC) {
> - xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1.reg,
> + xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1,
> PVC_GUC_TLB_INV_DESC1_INVALIDATE);
> - xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0.reg,
> + xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0,
> PVC_GUC_TLB_INV_DESC0_VALID);
> } else
> - xe_mmio_write32(gt, GUC_TLB_INV_CR.reg,
> + xe_mmio_write32(gt, GUC_TLB_INV_CR,
> GUC_TLB_INV_CR_INVALIDATE);
> }
> }
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 0d4664e344da..1cc9314e0d43 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -541,8 +541,8 @@ static int do_gt_reset(struct xe_gt *gt)
> struct xe_device *xe = gt_to_xe(gt);
> int err;
>
> - xe_mmio_write32(gt, GDRST.reg, GRDOM_FULL);
> - err = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_FULL, 5000,
> + xe_mmio_write32(gt, GDRST, GRDOM_FULL);
> + err = xe_mmio_wait32(gt, GDRST, 0, GRDOM_FULL, 5000,
> NULL, false);
> if (err)
> drm_err(&xe->drm,
> diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> index 49625d49bdcc..7cf11078ff57 100644
> --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> @@ -14,7 +14,7 @@
>
> static u32 read_reference_ts_freq(struct xe_gt *gt)
> {
> - u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE.reg);
> + u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE);
> u32 base_freq, frac_freq;
>
> base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK,
> @@ -54,7 +54,7 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg)
>
> int xe_gt_clock_init(struct xe_gt *gt)
> {
> - u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE.reg);
> + u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE);
> u32 freq = 0;
>
> /* Assuming gen11+ so assert this assumption is correct */
> @@ -63,7 +63,7 @@ int xe_gt_clock_init(struct xe_gt *gt)
> if (ctc_reg & CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(gt);
> } else {
> - u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0.reg);
> + u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0);
>
> freq = get_crystal_clock_freq(c0);
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index 55b240a5eaa7..2461e51c0abf 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -40,6 +40,8 @@
> * non-terminated instance.
> */
>
> +#define STEER_SEMAPHORE XE_REG(0xFD0)
> +
> static inline struct xe_reg to_xe_reg(struct xe_reg_mcr reg_mcr)
> {
> return reg_mcr.__reg;
> @@ -183,9 +185,9 @@ static void init_steering_l3bank(struct xe_gt *gt)
> {
> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
> u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
> - xe_mmio_read32(gt, MIRROR_FUSE3.reg));
> + xe_mmio_read32(gt, MIRROR_FUSE3));
> u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK,
> - xe_mmio_read32(gt, XEHP_FUSE4.reg));
> + xe_mmio_read32(gt, XEHP_FUSE4));
>
> /*
> * Group selects mslice, instance selects bank within mslice.
> @@ -196,7 +198,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
> bank_mask & BIT(0) ? 0 : 2;
> } else if (gt_to_xe(gt)->info.platform == XE_DG2) {
> u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
> - xe_mmio_read32(gt, MIRROR_FUSE3.reg));
> + xe_mmio_read32(gt, MIRROR_FUSE3));
> u32 bank = __ffs(mslice_mask) * 8;
>
> /*
> @@ -208,7 +210,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
> gt->steering[L3BANK].instance_target = bank & 0x3;
> } else {
> u32 fuse = REG_FIELD_GET(L3BANK_MASK,
> - ~xe_mmio_read32(gt, MIRROR_FUSE3.reg));
> + ~xe_mmio_read32(gt, MIRROR_FUSE3));
>
> gt->steering[L3BANK].group_target = 0; /* unused */
> gt->steering[L3BANK].instance_target = __ffs(fuse);
> @@ -218,7 +220,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
> static void init_steering_mslice(struct xe_gt *gt)
> {
> u32 mask = REG_FIELD_GET(MEML3_EN_MASK,
> - xe_mmio_read32(gt, MIRROR_FUSE3.reg));
> + xe_mmio_read32(gt, MIRROR_FUSE3));
>
> /*
> * mslice registers are valid (not terminated) if either the meml3
> @@ -337,8 +339,8 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
> u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |
> REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);
>
> - xe_mmio_write32(gt, MCFG_MCR_SELECTOR.reg, steer_val);
> - xe_mmio_write32(gt, SF_MCR_SELECTOR.reg, steer_val);
> + xe_mmio_write32(gt, MCFG_MCR_SELECTOR, steer_val);
> + xe_mmio_write32(gt, SF_MCR_SELECTOR, steer_val);
> /*
> * For GAM registers, all reads should be directed to instance 1
> * (unicast reads against other instances are not allowed),
> @@ -376,7 +378,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> continue;
>
> for (int i = 0; gt->steering[type].ranges[i].end > 0; i++) {
> - if (xe_mmio_in_range(>->steering[type].ranges[i], reg.reg)) {
> + if (xe_mmio_in_range(>->steering[type].ranges[i], reg)) {
> *group = gt->steering[type].group_target;
> *instance = gt->steering[type].instance_target;
> return true;
> @@ -387,7 +389,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> implicit_ranges = gt->steering[IMPLICIT_STEERING].ranges;
> if (implicit_ranges)
> for (int i = 0; implicit_ranges[i].end > 0; i++)
> - if (xe_mmio_in_range(&implicit_ranges[i], reg.reg))
> + if (xe_mmio_in_range(&implicit_ranges[i], reg))
> return false;
>
> /*
> @@ -403,8 +405,6 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> return true;
> }
>
> -#define STEER_SEMAPHORE 0xFD0
> -
> /*
> * Obtain exclusive access to MCR steering. On MTL and beyond we also need
> * to synchronize with external clients (e.g., firmware), so a semaphore
> @@ -446,16 +446,17 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> u8 rw_flag, int group, int instance, u32 value)
> {
> const struct xe_reg reg = to_xe_reg(reg_mcr);
> - u32 steer_reg, steer_val, val = 0;
> + struct xe_reg steer_reg;
> + u32 steer_val, val = 0;
>
> lockdep_assert_held(>->mcr_lock);
>
> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
> - steer_reg = MTL_MCR_SELECTOR.reg;
> + steer_reg = MTL_MCR_SELECTOR;
> steer_val = REG_FIELD_PREP(MTL_MCR_GROUPID, group) |
> REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance);
> } else {
> - steer_reg = MCR_SELECTOR.reg;
> + steer_reg = MCR_SELECTOR;
> steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, group) |
> REG_FIELD_PREP(MCR_SUBSLICE_MASK, instance);
> }
> @@ -473,9 +474,9 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> xe_mmio_write32(gt, steer_reg, steer_val);
>
> if (rw_flag == MCR_OP_READ)
> - val = xe_mmio_read32(gt, reg.reg);
> + val = xe_mmio_read32(gt, reg);
> else
> - xe_mmio_write32(gt, reg.reg, value);
> + xe_mmio_write32(gt, reg, value);
>
> /*
> * If we turned off the multicast bit (during a write) we're required
> @@ -517,7 +518,7 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr reg_mcr)
> group, instance, 0);
> mcr_unlock(gt);
> } else {
> - val = xe_mmio_read32(gt, reg.reg);
> + val = xe_mmio_read32(gt, reg);
> }
>
> return val;
> @@ -584,7 +585,7 @@ void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> * to touch the steering register.
> */
> mcr_lock(gt);
> - xe_mmio_write32(gt, reg.reg, value);
> + xe_mmio_write32(gt, reg, value);
> mcr_unlock(gt);
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
> index 14cf135fd648..7c3e347e4d74 100644
> --- a/drivers/gpu/drm/xe/xe_gt_topology.c
> +++ b/drivers/gpu/drm/xe/xe_gt_topology.c
> @@ -26,7 +26,7 @@ load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)
>
> va_start(argp, numregs);
> for (i = 0; i < numregs; i++)
> - fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, u32));
> + fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, struct xe_reg));
> va_end(argp);
>
> bitmap_from_arr32(mask, fuse_val, numregs * 32);
> @@ -36,7 +36,7 @@ static void
> load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
> {
> struct xe_device *xe = gt_to_xe(gt);
> - u32 reg = xe_mmio_read32(gt, XELP_EU_ENABLE.reg);
> + u32 reg_val = xe_mmio_read32(gt, XELP_EU_ENABLE);
> u32 val = 0;
> int i;
>
> @@ -47,15 +47,15 @@ load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
> * of enable).
> */
> if (GRAPHICS_VERx100(xe) < 1250)
> - reg = ~reg & XELP_EU_MASK;
> + reg_val = ~reg_val & XELP_EU_MASK;
>
> /* On PVC, one bit = one EU */
> if (GRAPHICS_VERx100(xe) == 1260) {
> - val = reg;
> + val = reg_val;
> } else {
> /* All other platforms, one bit = 2 EU */
> - for (i = 0; i < fls(reg); i++)
> - if (reg & BIT(i))
> + for (i = 0; i < fls(reg_val); i++)
> + if (reg_val & BIT(i))
> val |= 0x3 << 2 * i;
> }
>
> @@ -95,10 +95,10 @@ xe_gt_topology_init(struct xe_gt *gt)
>
> load_dss_mask(gt, gt->fuse_topo.g_dss_mask,
> num_geometry_regs,
> - XELP_GT_GEOMETRY_DSS_ENABLE.reg);
> + XELP_GT_GEOMETRY_DSS_ENABLE);
> load_dss_mask(gt, gt->fuse_topo.c_dss_mask, num_compute_regs,
> - XEHP_GT_COMPUTE_DSS_ENABLE.reg,
> - XEHPC_GT_COMPUTE_DSS_ENABLE_EXT.reg);
> + XEHP_GT_COMPUTE_DSS_ENABLE,
> + XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
> load_eu_mask(gt, gt->fuse_topo.eu_mask_per_dss);
>
> xe_gt_topology_dump(gt, &p);
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 89d20faced19..12b636910460 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -240,10 +240,10 @@ static void guc_write_params(struct xe_guc *guc)
>
> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>
> - xe_mmio_write32(gt, SOFT_SCRATCH(0).reg, 0);
> + xe_mmio_write32(gt, SOFT_SCRATCH(0), 0);
>
> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> - xe_mmio_write32(gt, SOFT_SCRATCH(1 + i).reg, guc->params[i]);
> + xe_mmio_write32(gt, SOFT_SCRATCH(1 + i), guc->params[i]);
> }
>
> int xe_guc_init(struct xe_guc *guc)
> @@ -276,9 +276,9 @@ int xe_guc_init(struct xe_guc *guc)
> guc_init_params(guc);
>
> if (xe_gt_is_media_type(gt))
> - guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT.reg;
> + guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT;
> else
> - guc->notify_reg = GUC_HOST_INTERRUPT.reg;
> + guc->notify_reg = GUC_HOST_INTERRUPT;
>
> xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE);
>
> @@ -317,9 +317,9 @@ int xe_guc_reset(struct xe_guc *guc)
>
> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>
> - xe_mmio_write32(gt, GDRST.reg, GRDOM_GUC);
> + xe_mmio_write32(gt, GDRST, GRDOM_GUC);
>
> - ret = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_GUC, 5000,
> + ret = xe_mmio_wait32(gt, GDRST, 0, GRDOM_GUC, 5000,
> &gdrst, false);
> if (ret) {
> drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",
> @@ -327,7 +327,7 @@ int xe_guc_reset(struct xe_guc *guc)
> goto err_out;
> }
>
> - guc_status = xe_mmio_read32(gt, GUC_STATUS.reg);
> + guc_status = xe_mmio_read32(gt, GUC_STATUS);
> if (!(guc_status & GS_MIA_IN_RESET)) {
> drm_err(&xe->drm,
> "GuC status: 0x%x, MIA core expected to be in reset\n",
> @@ -360,9 +360,9 @@ static void guc_prepare_xfer(struct xe_guc *guc)
> shim_flags |= PVC_GUC_MOCS_INDEX(PVC_GUC_MOCS_UC_INDEX);
>
> /* Must program this register before loading the ucode with DMA */
> - xe_mmio_write32(gt, GUC_SHIM_CONTROL.reg, shim_flags);
> + xe_mmio_write32(gt, GUC_SHIM_CONTROL, shim_flags);
>
> - xe_mmio_write32(gt, GT_PM_CONFIG.reg, GT_DOORBELL_ENABLE);
> + xe_mmio_write32(gt, GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> }
>
> /*
> @@ -378,7 +378,7 @@ static int guc_xfer_rsa(struct xe_guc *guc)
> if (guc->fw.rsa_size > 256) {
> u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) +
> xe_uc_fw_rsa_offset(&guc->fw);
> - xe_mmio_write32(gt, UOS_RSA_SCRATCH(0).reg, rsa_ggtt_addr);
> + xe_mmio_write32(gt, UOS_RSA_SCRATCH(0), rsa_ggtt_addr);
> return 0;
> }
>
> @@ -387,7 +387,7 @@ static int guc_xfer_rsa(struct xe_guc *guc)
> return -ENOMEM;
>
> for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
> - xe_mmio_write32(gt, UOS_RSA_SCRATCH(i).reg, rsa[i]);
> + xe_mmio_write32(gt, UOS_RSA_SCRATCH(i), rsa[i]);
>
> return 0;
> }
> @@ -415,7 +415,7 @@ static int guc_wait_ucode(struct xe_guc *guc)
> * 200ms. Even at slowest clock, this should be sufficient. And
> * in the working case, a larger timeout makes no difference.
> */
> - ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS.reg,
> + ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS,
> FIELD_PREP(GS_UKERNEL_MASK,
> XE_GUC_LOAD_STATUS_READY),
> GS_UKERNEL_MASK, 200000, &status, false);
> @@ -443,7 +443,7 @@ static int guc_wait_ucode(struct xe_guc *guc)
> XE_GUC_LOAD_STATUS_EXCEPTION) {
> drm_info(drm, "GuC firmware exception. EIP: %#x\n",
> xe_mmio_read32(guc_to_gt(guc),
> - SOFT_SCRATCH(13).reg));
> + SOFT_SCRATCH(13)));
> ret = -ENXIO;
> }
>
> @@ -540,10 +540,10 @@ static void guc_handle_mmio_msg(struct xe_guc *guc)
>
> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>
> - msg = xe_mmio_read32(gt, SOFT_SCRATCH(15).reg);
> + msg = xe_mmio_read32(gt, SOFT_SCRATCH(15));
> msg &= XE_GUC_RECV_MSG_EXCEPTION |
> XE_GUC_RECV_MSG_CRASH_DUMP_POSTED;
> - xe_mmio_write32(gt, SOFT_SCRATCH(15).reg, 0);
> + xe_mmio_write32(gt, SOFT_SCRATCH(15), 0);
>
> if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED)
> drm_err(&guc_to_xe(guc)->drm,
> @@ -561,12 +561,12 @@ static void guc_enable_irq(struct xe_guc *guc)
> REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) :
> REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
>
> - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE.reg,
> + xe_mmio_write32(gt, GUC_SG_INTR_ENABLE,
> REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST));
> if (xe_gt_is_media_type(gt))
> - xe_mmio_rmw32(gt, GUC_SG_INTR_MASK.reg, events, 0);
> + xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0);
> else
> - xe_mmio_write32(gt, GUC_SG_INTR_MASK.reg, ~events);
> + xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~events);
> }
>
> int xe_guc_enable_communication(struct xe_guc *guc)
> @@ -575,7 +575,7 @@ int xe_guc_enable_communication(struct xe_guc *guc)
>
> guc_enable_irq(guc);
>
> - xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK.reg,
> + xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK,
> ARAT_EXPIRED_INTRMSK, 0);
>
> err = xe_guc_ct_enable(&guc->ct);
> @@ -628,8 +628,8 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
> struct xe_device *xe = guc_to_xe(guc);
> struct xe_gt *gt = guc_to_gt(guc);
> u32 header, reply;
> - u32 reply_reg = xe_gt_is_media_type(gt) ?
> - MED_VF_SW_FLAG(0).reg : VF_SW_FLAG(0).reg;
> + struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?
> + MED_VF_SW_FLAG(0) : VF_SW_FLAG(0);
> const u32 LAST_INDEX = VF_SW_FLAG_COUNT;
> int ret;
> int i;
> @@ -649,14 +649,14 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
> /* Not in critical data-path, just do if else for GT type */
> if (xe_gt_is_media_type(gt)) {
> for (i = 0; i < len; ++i)
> - xe_mmio_write32(gt, MED_VF_SW_FLAG(i).reg,
> + xe_mmio_write32(gt, MED_VF_SW_FLAG(i),
> request[i]);
> - xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX).reg);
> + xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX));
> } else {
> for (i = 0; i < len; ++i)
> - xe_mmio_write32(gt, VF_SW_FLAG(i).reg,
> + xe_mmio_write32(gt, VF_SW_FLAG(i),
> request[i]);
> - xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX).reg);
> + xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX));
> }
>
> xe_guc_notify(guc);
> @@ -720,9 +720,10 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
> if (response_buf) {
> response_buf[0] = header;
>
> - for (i = 1; i < VF_SW_FLAG_COUNT; i++)
> - response_buf[i] =
> - xe_mmio_read32(gt, reply_reg + i * sizeof(u32));
> + for (i = 1; i < VF_SW_FLAG_COUNT; i++) {
> + reply_reg.reg += i * sizeof(u32);
> + response_buf[i] = xe_mmio_read32(gt, reply_reg);
> + }
> }
>
> /* Use data from the GuC response as our return value */
> @@ -844,7 +845,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
> if (err)
> return;
>
> - status = xe_mmio_read32(gt, GUC_STATUS.reg);
> + status = xe_mmio_read32(gt, GUC_STATUS);
>
> drm_printf(p, "\nGuC status 0x%08x:\n", status);
> drm_printf(p, "\tBootrom status = 0x%x\n",
> @@ -859,7 +860,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
> drm_puts(p, "\nScratch registers:\n");
> for (i = 0; i < SOFT_SCRATCH_COUNT; i++) {
> drm_printf(p, "\t%2d: \t0x%x\n",
> - i, xe_mmio_read32(gt, SOFT_SCRATCH(i).reg));
> + i, xe_mmio_read32(gt, SOFT_SCRATCH(i)));
> }
>
> xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 84c2d7c624c6..683f2df09c49 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -428,7 +428,6 @@ static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,
> struct guc_mmio_reg entry = {
> .offset = reg.reg,
> .flags = reg.masked ? GUC_REGSET_MASKED : 0,
> - /* TODO: steering */
> };
>
> xe_map_memcpy_to(ads_to_xe(ads), regset_map, n_entry * sizeof(entry),
> @@ -551,7 +550,7 @@ static void guc_doorbell_init(struct xe_guc_ads *ads)
>
> if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) {
> u32 distdbreg =
> - xe_mmio_read32(gt, DIST_DBS_POPULATED.reg);
> + xe_mmio_read32(gt, DIST_DBS_POPULATED);
>
> ads_blob_write(ads,
> system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 72d460d5323b..e799faa1c6b8 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -317,9 +317,9 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
> u32 reg;
>
> if (xe_gt_is_media_type(gt))
> - reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY.reg);
> + reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY);
> else
> - reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY.reg);
> + reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY);
>
> pc->rpe_freq = REG_FIELD_GET(MTL_RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> }
> @@ -336,9 +336,9 @@ static void tgl_update_rpe_value(struct xe_guc_pc *pc)
> * PCODE at a different register
> */
> if (xe->info.platform == XE_PVC)
> - reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP.reg);
> + reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);
> else
> - reg = xe_mmio_read32(gt, GEN10_FREQ_INFO_REC.reg);
> + reg = xe_mmio_read32(gt, GEN10_FREQ_INFO_REC);
>
> pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> }
> @@ -380,10 +380,10 @@ static ssize_t freq_act_show(struct device *dev,
> goto out;
>
> if (xe->info.platform == XE_METEORLAKE) {
> - freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1.reg);
> + freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);
> freq = REG_FIELD_GET(MTL_CAGF_MASK, freq);
> } else {
> - freq = xe_mmio_read32(gt, GEN12_RPSTAT1.reg);
> + freq = xe_mmio_read32(gt, GEN12_RPSTAT1);
> freq = REG_FIELD_GET(GEN12_CAGF_MASK, freq);
> }
>
> @@ -413,7 +413,7 @@ static ssize_t freq_cur_show(struct device *dev,
> if (ret)
> goto out;
>
> - freq = xe_mmio_read32(gt, RPNSWREQ.reg);
> + freq = xe_mmio_read32(gt, RPNSWREQ);
>
> freq = REG_FIELD_GET(REQ_RATIO_MASK, freq);
> ret = sysfs_emit(buf, "%d\n", decode_freq(freq));
> @@ -588,7 +588,7 @@ static ssize_t rc_status_show(struct device *dev,
> u32 reg;
>
> xe_device_mem_access_get(gt_to_xe(gt));
> - reg = xe_mmio_read32(gt, GT_CORE_STATUS.reg);
> + reg = xe_mmio_read32(gt, GT_CORE_STATUS);
> xe_device_mem_access_put(gt_to_xe(gt));
>
> switch (REG_FIELD_GET(RCN_MASK, reg)) {
> @@ -615,7 +615,7 @@ static ssize_t rc6_residency_show(struct device *dev,
> if (ret)
> goto out;
>
> - reg = xe_mmio_read32(gt, GT_GFX_RC6.reg);
> + reg = xe_mmio_read32(gt, GT_GFX_RC6);
> ret = sysfs_emit(buff, "%u\n", reg);
>
> XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
> @@ -646,9 +646,9 @@ static void mtl_init_fused_rp_values(struct xe_guc_pc *pc)
> xe_device_assert_mem_access(pc_to_xe(pc));
>
> if (xe_gt_is_media_type(gt))
> - reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP.reg);
> + reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP);
> else
> - reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP.reg);
> + reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP);
> pc->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, reg) *
> GT_FREQUENCY_MULTIPLIER;
> pc->rpn_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, reg) *
> @@ -664,9 +664,9 @@ static void tgl_init_fused_rp_values(struct xe_guc_pc *pc)
> xe_device_assert_mem_access(pc_to_xe(pc));
>
> if (xe->info.platform == XE_PVC)
> - reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP.reg);
> + reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);
> else
> - reg = xe_mmio_read32(gt, GEN6_RP_STATE_CAP.reg);
> + reg = xe_mmio_read32(gt, GEN6_RP_STATE_CAP);
> pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> }
> @@ -745,9 +745,9 @@ static int pc_gucrc_disable(struct xe_guc_pc *pc)
> if (ret)
> return ret;
>
> - xe_mmio_write32(gt, PG_ENABLE.reg, 0);
> - xe_mmio_write32(gt, RC_CONTROL.reg, 0);
> - xe_mmio_write32(gt, RC_STATE.reg, 0);
> + xe_mmio_write32(gt, PG_ENABLE, 0);
> + xe_mmio_write32(gt, RC_CONTROL, 0);
> + xe_mmio_write32(gt, RC_STATE, 0);
>
> XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
> return 0;
> diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
> index ac7eec28934d..a304dce4e9f4 100644
> --- a/drivers/gpu/drm/xe/xe_guc_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_types.h
> @@ -9,6 +9,7 @@
> #include <linux/idr.h>
> #include <linux/xarray.h>
>
> +#include "regs/xe_reg_defs.h"
> #include "xe_guc_ads_types.h"
> #include "xe_guc_ct_types.h"
> #include "xe_guc_fwif.h"
> @@ -74,7 +75,7 @@ struct xe_guc {
> /**
> * @notify_reg: Register which is written to notify GuC of H2G messages
> */
> - u32 notify_reg;
> + struct xe_reg notify_reg;
> /** @params: Control params for fw initialization */
> u32 params[GUC_CTL_MAX_DWORDS];
> };
> diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
> index 55dcaab34ea4..e0377083d1f2 100644
> --- a/drivers/gpu/drm/xe/xe_huc.c
> +++ b/drivers/gpu/drm/xe/xe_huc.c
> @@ -84,7 +84,7 @@ int xe_huc_auth(struct xe_huc *huc)
> goto fail;
> }
>
> - ret = xe_mmio_wait32(gt, HUC_KERNEL_LOAD_INFO.reg,
> + ret = xe_mmio_wait32(gt, HUC_KERNEL_LOAD_INFO,
> HUC_LOAD_SUCCESSFUL,
> HUC_LOAD_SUCCESSFUL, 100000, NULL, false);
> if (ret) {
> @@ -126,7 +126,7 @@ void xe_huc_print_info(struct xe_huc *huc, struct drm_printer *p)
> return;
>
> drm_printf(p, "\nHuC status: 0x%08x\n",
> - xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO.reg));
> + xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO));
>
> xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> }
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 795302bcd3ae..d1b7ac35c4a0 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -232,20 +232,25 @@ static void hw_engine_fini(struct drm_device *drm, void *arg)
> hwe->gt = NULL;
> }
>
> -static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, u32 reg, u32 val)
> +static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg,
> + u32 val)
> {
> - XE_BUG_ON(reg & hwe->mmio_base);
> + XE_BUG_ON(reg.reg & hwe->mmio_base);
> xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
>
> - xe_mmio_write32(hwe->gt, reg + hwe->mmio_base, val);
> + reg.reg += hwe->mmio_base;
> +
> + xe_mmio_write32(hwe->gt, reg, val);
> }
>
> -static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, u32 reg)
> +static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)
> {
> - XE_BUG_ON(reg & hwe->mmio_base);
> + XE_BUG_ON(reg.reg & hwe->mmio_base);
> xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
>
> - return xe_mmio_read32(hwe->gt, reg + hwe->mmio_base);
> + reg.reg += hwe->mmio_base;
> +
> + return xe_mmio_read32(hwe->gt, reg);
> }
>
> void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
> @@ -254,17 +259,17 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
> xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
>
> if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
> - xe_mmio_write32(hwe->gt, RCU_MODE.reg,
> + xe_mmio_write32(hwe->gt, RCU_MODE,
> _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
>
> - hw_engine_mmio_write32(hwe, RING_HWSTAM(0).reg, ~0x0);
> - hw_engine_mmio_write32(hwe, RING_HWS_PGA(0).reg,
> + hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0);
> + hw_engine_mmio_write32(hwe, RING_HWS_PGA(0),
> xe_bo_ggtt_addr(hwe->hwsp));
> - hw_engine_mmio_write32(hwe, RING_MODE(0).reg,
> + hw_engine_mmio_write32(hwe, RING_MODE(0),
> _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
> - hw_engine_mmio_write32(hwe, RING_MI_MODE(0).reg,
> + hw_engine_mmio_write32(hwe, RING_MI_MODE(0),
> _MASKED_BIT_DISABLE(STOP_RING));
> - hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg);
> + hw_engine_mmio_read32(hwe, RING_MI_MODE(0));
> }
>
> static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
> @@ -379,7 +384,7 @@ static void read_media_fuses(struct xe_gt *gt)
>
> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>
> - media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE.reg);
> + media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE);
>
> /*
> * Pre-Xe_HP platforms had register bits representing absent engines,
> @@ -421,7 +426,7 @@ static void read_copy_fuses(struct xe_gt *gt)
>
> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>
> - bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3.reg);
> + bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3);
> bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
>
> /* BCS0 is always present; only BCS1-BCS8 may be fused off */
> @@ -518,63 +523,63 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
> drm_printf(p, "\tMMIO base: 0x%08x\n", hwe->mmio_base);
>
> drm_printf(p, "\tHWSTAM: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_HWSTAM(0).reg));
> + hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
> drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_HWS_PGA(0).reg));
> + hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
>
> drm_printf(p, "\tRING_EXECLIST_STATUS_LO: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0).reg));
> + hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
> drm_printf(p, "\tRING_EXECLIST_STATUS_HI: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0).reg));
> + hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
> drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_LO: 0x%08x\n",
> hw_engine_mmio_read32(hwe,
> - RING_EXECLIST_SQ_CONTENTS_LO(0).reg));
> + RING_EXECLIST_SQ_CONTENTS_LO(0)));
> drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_HI: 0x%08x\n",
> hw_engine_mmio_read32(hwe,
> - RING_EXECLIST_SQ_CONTENTS_HI(0).reg));
> + RING_EXECLIST_SQ_CONTENTS_HI(0)));
> drm_printf(p, "\tRING_EXECLIST_CONTROL: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0).reg));
> + hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
>
> drm_printf(p, "\tRING_START: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_START(0).reg));
> + hw_engine_mmio_read32(hwe, RING_START(0)));
> drm_printf(p, "\tRING_HEAD: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_HEAD(0).reg) & HEAD_ADDR);
> + hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
> drm_printf(p, "\tRING_TAIL: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_TAIL(0).reg) & TAIL_ADDR);
> + hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
> drm_printf(p, "\tRING_CTL: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_CTL(0).reg));
> + hw_engine_mmio_read32(hwe, RING_CTL(0)));
> drm_printf(p, "\tRING_MODE: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg));
> + hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
> drm_printf(p, "\tRING_MODE_GEN7: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_MODE(0).reg));
> + hw_engine_mmio_read32(hwe, RING_MODE(0)));
>
> drm_printf(p, "\tRING_IMR: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_IMR(0).reg));
> + hw_engine_mmio_read32(hwe, RING_IMR(0)));
> drm_printf(p, "\tRING_ESR: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_ESR(0).reg));
> + hw_engine_mmio_read32(hwe, RING_ESR(0)));
> drm_printf(p, "\tRING_EMR: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_EMR(0).reg));
> + hw_engine_mmio_read32(hwe, RING_EMR(0)));
> drm_printf(p, "\tRING_EIR: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_EIR(0).reg));
> + hw_engine_mmio_read32(hwe, RING_EIR(0)));
>
> drm_printf(p, "\tACTHD: 0x%08x_%08x\n",
> - hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0).reg),
> - hw_engine_mmio_read32(hwe, RING_ACTHD(0).reg));
> + hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
> + hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
> drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
> - hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0).reg),
> - hw_engine_mmio_read32(hwe, RING_BBADDR(0).reg));
> + hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
> + hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
> drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
> - hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0).reg),
> - hw_engine_mmio_read32(hwe, RING_DMA_FADD(0).reg));
> + hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
> + hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
>
> drm_printf(p, "\tIPEIR: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, IPEIR(0).reg));
> + hw_engine_mmio_read32(hwe, IPEIR(0)));
> drm_printf(p, "\tIPEHR: 0x%08x\n\n",
> - hw_engine_mmio_read32(hwe, IPEHR(0).reg));
> + hw_engine_mmio_read32(hwe, IPEHR(0)));
>
> if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
> drm_printf(p, "\tRCU_MODE: 0x%08x\n",
> - xe_mmio_read32(hwe->gt, RCU_MODE.reg));
> + xe_mmio_read32(hwe->gt, RCU_MODE));
>
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index ac72c1a38e5c..7aa245792927 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -29,7 +29,7 @@
>
> static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
> {
> - u32 val = xe_mmio_read32(gt, reg.reg);
> + u32 val = xe_mmio_read32(gt, reg);
>
> if (val == 0)
> return;
> @@ -37,10 +37,10 @@ static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
> drm_WARN(>_to_xe(gt)->drm, 1,
> "Interrupt register 0x%x is not zero: 0x%08x\n",
> reg.reg, val);
> - xe_mmio_write32(gt, reg.reg, 0xffffffff);
> - xe_mmio_read32(gt, reg.reg);
> - xe_mmio_write32(gt, reg.reg, 0xffffffff);
> - xe_mmio_read32(gt, reg.reg);
> + xe_mmio_write32(gt, reg, 0xffffffff);
> + xe_mmio_read32(gt, reg);
> + xe_mmio_write32(gt, reg, 0xffffffff);
> + xe_mmio_read32(gt, reg);
> }
>
> /*
> @@ -55,32 +55,32 @@ static void unmask_and_enable(struct xe_gt *gt, u32 irqregs, u32 bits)
> */
> assert_iir_is_zero(gt, IIR(irqregs));
>
> - xe_mmio_write32(gt, IER(irqregs).reg, bits);
> - xe_mmio_write32(gt, IMR(irqregs).reg, ~bits);
> + xe_mmio_write32(gt, IER(irqregs), bits);
> + xe_mmio_write32(gt, IMR(irqregs), ~bits);
>
> /* Posting read */
> - xe_mmio_read32(gt, IMR(irqregs).reg);
> + xe_mmio_read32(gt, IMR(irqregs));
> }
>
> /* Mask and disable all interrupts. */
> static void mask_and_disable(struct xe_gt *gt, u32 irqregs)
> {
> - xe_mmio_write32(gt, IMR(irqregs).reg, ~0);
> + xe_mmio_write32(gt, IMR(irqregs), ~0);
> /* Posting read */
> - xe_mmio_read32(gt, IMR(irqregs).reg);
> + xe_mmio_read32(gt, IMR(irqregs));
>
> - xe_mmio_write32(gt, IER(irqregs).reg, 0);
> + xe_mmio_write32(gt, IER(irqregs), 0);
>
> /* IIR can theoretically queue up two events. Be paranoid. */
> - xe_mmio_write32(gt, IIR(irqregs).reg, ~0);
> - xe_mmio_read32(gt, IIR(irqregs).reg);
> - xe_mmio_write32(gt, IIR(irqregs).reg, ~0);
> - xe_mmio_read32(gt, IIR(irqregs).reg);
> + xe_mmio_write32(gt, IIR(irqregs), ~0);
> + xe_mmio_read32(gt, IIR(irqregs));
> + xe_mmio_write32(gt, IIR(irqregs), ~0);
> + xe_mmio_read32(gt, IIR(irqregs));
> }
>
> static u32 xelp_intr_disable(struct xe_gt *gt)
> {
> - xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, 0);
> + xe_mmio_write32(gt, GFX_MSTR_IRQ, 0);
>
> /*
> * Now with master disabled, get a sample of level indications
> @@ -88,7 +88,7 @@ static u32 xelp_intr_disable(struct xe_gt *gt)
> * New indications can and will light up during processing,
> * and will generate new interrupt after enabling master.
> */
> - return xe_mmio_read32(gt, GFX_MSTR_IRQ.reg);
> + return xe_mmio_read32(gt, GFX_MSTR_IRQ);
> }
>
> static u32
> @@ -99,18 +99,18 @@ gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
> if (!(master_ctl & GU_MISC_IRQ))
> return 0;
>
> - iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET).reg);
> + iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET));
> if (likely(iir))
> - xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET).reg, iir);
> + xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET), iir);
>
> return iir;
> }
>
> static inline void xelp_intr_enable(struct xe_gt *gt, bool stall)
> {
> - xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, MASTER_IRQ);
> + xe_mmio_write32(gt, GFX_MSTR_IRQ, MASTER_IRQ);
> if (stall)
> - xe_mmio_read32(gt, GFX_MSTR_IRQ.reg);
> + xe_mmio_read32(gt, GFX_MSTR_IRQ);
> }
>
> static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> @@ -133,41 +133,41 @@ static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> smask = irqs << 16;
>
> /* Enable RCS, BCS, VCS and VECS class interrupts. */
> - xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE.reg, dmask);
> - xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE.reg, dmask);
> + xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
> + xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
> if (ccs_mask)
> - xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE.reg, smask);
> + xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
>
> /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> - xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK.reg, ~smask);
> - xe_mmio_write32(gt, BCS_RSVD_INTR_MASK.reg, ~smask);
> + xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
> + xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
> if (bcs_mask & (BIT(1)|BIT(2)))
> - xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK.reg, ~dmask);
> + xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
> if (bcs_mask & (BIT(3)|BIT(4)))
> - xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK.reg, ~dmask);
> + xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
> if (bcs_mask & (BIT(5)|BIT(6)))
> - xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK.reg, ~dmask);
> + xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
> if (bcs_mask & (BIT(7)|BIT(8)))
> - xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK.reg, ~dmask);
> - xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK.reg, ~dmask);
> - xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK.reg, ~dmask);
> - xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK.reg, ~dmask);
> + xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
> + xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
> + xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
> + xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
> if (ccs_mask & (BIT(0)|BIT(1)))
> - xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK.reg, ~dmask);
> + xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
> if (ccs_mask & (BIT(2)|BIT(3)))
> - xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK.reg, ~dmask);
> + xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
>
> /*
> * RPS interrupts will get enabled/disabled on demand when RPS itself
> * is enabled/disabled.
> */
> /* TODO: gt->pm_ier, gt->pm_imr */
> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE.reg, 0);
> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK.reg, ~0);
> + xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
> + xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
>
> /* Same thing for GuC interrupts */
> - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE.reg, 0);
> - xe_mmio_write32(gt, GUC_SG_INTR_MASK.reg, ~0);
> + xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
> + xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
> }
>
> static void xelp_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> @@ -192,7 +192,7 @@ gt_engine_identity(struct xe_device *xe,
>
> lockdep_assert_held(&xe->irq.lock);
>
> - xe_mmio_write32(gt, IIR_REG_SELECTOR(bank).reg, BIT(bit));
> + xe_mmio_write32(gt, IIR_REG_SELECTOR(bank), BIT(bit));
>
> /*
> * NB: Specs do not specify how long to spin wait,
> @@ -200,7 +200,7 @@ gt_engine_identity(struct xe_device *xe,
> */
> timeout_ts = (local_clock() >> 10) + 100;
> do {
> - ident = xe_mmio_read32(gt, INTR_IDENTITY_REG(bank).reg);
> + ident = xe_mmio_read32(gt, INTR_IDENTITY_REG(bank));
> } while (!(ident & INTR_DATA_VALID) &&
> !time_after32(local_clock() >> 10, timeout_ts));
>
> @@ -210,7 +210,7 @@ gt_engine_identity(struct xe_device *xe,
> return 0;
> }
>
> - xe_mmio_write32(gt, INTR_IDENTITY_REG(bank).reg, INTR_DATA_VALID);
> + xe_mmio_write32(gt, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
>
> return ident;
> }
> @@ -249,11 +249,11 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
>
> if (!xe_gt_is_media_type(gt)) {
> intr_dw[bank] =
> - xe_mmio_read32(gt, GT_INTR_DW(bank).reg);
> + xe_mmio_read32(gt, GT_INTR_DW(bank));
> for_each_set_bit(bit, intr_dw + bank, 32)
> identity[bit] = gt_engine_identity(xe, gt,
> bank, bit);
> - xe_mmio_write32(gt, GT_INTR_DW(bank).reg,
> + xe_mmio_write32(gt, GT_INTR_DW(bank),
> intr_dw[bank]);
> }
>
> @@ -315,14 +315,14 @@ static u32 dg1_intr_disable(struct xe_device *xe)
> u32 val;
>
> /* First disable interrupts */
> - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR.reg, 0);
> + xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, 0);
>
> /* Get the indication levels and ack the master unit */
> - val = xe_mmio_read32(gt, DG1_MSTR_TILE_INTR.reg);
> + val = xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
> if (unlikely(!val))
> return 0;
>
> - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR.reg, val);
> + xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, val);
>
> return val;
> }
> @@ -331,9 +331,9 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
> {
> struct xe_gt *gt = xe_device_get_gt(xe, 0);
>
> - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR.reg, DG1_MSTR_IRQ);
> + xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
> if (stall)
> - xe_mmio_read32(gt, DG1_MSTR_TILE_INTR.reg);
> + xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
> }
>
> static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> @@ -373,7 +373,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> continue;
>
> if (!xe_gt_is_media_type(gt))
> - master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ.reg);
> + master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ);
>
> /*
> * We might be in irq handler just when PCIe DPC is initiated
> @@ -387,7 +387,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> }
>
> if (!xe_gt_is_media_type(gt))
> - xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, master_ctl);
> + xe_mmio_write32(gt, GFX_MSTR_IRQ, master_ctl);
> gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
>
> /*
> @@ -416,34 +416,34 @@ static void gt_irq_reset(struct xe_gt *gt)
> u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
>
> /* Disable RCS, BCS, VCS and VECS class engines. */
> - xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE.reg, 0);
> - xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE.reg, 0);
> + xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, 0);
> + xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, 0);
> if (ccs_mask)
> - xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE.reg, 0);
> + xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, 0);
>
> /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> - xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK.reg, ~0);
> - xe_mmio_write32(gt, BCS_RSVD_INTR_MASK.reg, ~0);
> + xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~0);
> + xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~0);
> if (bcs_mask & (BIT(1)|BIT(2)))
> - xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK.reg, ~0);
> + xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
> if (bcs_mask & (BIT(3)|BIT(4)))
> - xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK.reg, ~0);
> + xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
> if (bcs_mask & (BIT(5)|BIT(6)))
> - xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK.reg, ~0);
> + xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
> if (bcs_mask & (BIT(7)|BIT(8)))
> - xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK.reg, ~0);
> - xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK.reg, ~0);
> - xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK.reg, ~0);
> - xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK.reg, ~0);
> + xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
> + xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~0);
> + xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~0);
> + xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~0);
> if (ccs_mask & (BIT(0)|BIT(1)))
> - xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK.reg, ~0);
> + xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~0);
> if (ccs_mask & (BIT(2)|BIT(3)))
> - xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK.reg, ~0);
> + xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~0);
>
> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE.reg, 0);
> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK.reg, ~0);
> - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE.reg, 0);
> - xe_mmio_write32(gt, GUC_SG_INTR_MASK.reg, ~0);
> + xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
> + xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
> + xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
> + xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
> }
>
> static void xelp_irq_reset(struct xe_gt *gt)
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 3b719c774efa..0e91004fa06d 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -153,13 +153,13 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_si
> struct xe_gt *gt = xe_device_get_gt(xe, 0);
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> int err;
> - u32 reg;
> + u32 reg_val;
>
> if (!xe->info.has_flat_ccs) {
> *vram_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
> if (usable_size)
> *usable_size = min(*vram_size,
> - xe_mmio_read64(gt, GSMBASE.reg));
> + xe_mmio_read64(gt, GSMBASE));
> return 0;
> }
>
> @@ -167,11 +167,11 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_si
> if (err)
> return err;
>
> - reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE0_ADDR_RANGE);
> - *vram_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
> + reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE0_ADDR_RANGE);
> + *vram_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg_val) * SZ_1G;
> if (usable_size) {
> - reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
> - *usable_size = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
> + reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
> + *usable_size = (u64)REG_FIELD_GET(GENMASK(31, 8), reg_val) * SZ_64K;
> drm_info(&xe->drm, "vram_size: 0x%llx usable_size: 0x%llx\n",
> *vram_size, *usable_size);
> }
> @@ -298,7 +298,7 @@ static void xe_mmio_probe_tiles(struct xe_device *xe)
> if (xe->info.tile_count == 1)
> return;
>
> - mtcfg = xe_mmio_read64(gt, XEHP_MTCFG_ADDR.reg);
> + mtcfg = xe_mmio_read64(gt, XEHP_MTCFG_ADDR);
> adj_tile_count = xe->info.tile_count =
> REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
> if (xe->info.media_verx100 >= 1300)
> @@ -374,7 +374,7 @@ int xe_mmio_init(struct xe_device *xe)
> * keep the GT powered down; we won't be able to communicate with it
> * and we should not continue with driver initialization.
> */
> - if (IS_DGFX(xe) && !(xe_mmio_read32(gt, GU_CNTL.reg) & LMEM_INIT)) {
> + if (IS_DGFX(xe) && !(xe_mmio_read32(gt, GU_CNTL) & LMEM_INIT)) {
> drm_err(&xe->drm, "VRAM not initialized by firmware\n");
> return -ENODEV;
> }
> @@ -403,6 +403,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
> struct xe_device *xe = to_xe_device(dev);
> struct drm_xe_mmio *args = data;
> unsigned int bits_flag, bytes;
> + struct xe_reg reg;
> bool allowed;
> int ret = 0;
>
> @@ -435,6 +436,12 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
> if (XE_IOCTL_ERR(xe, args->addr + bytes > xe->mmio.size))
> return -EINVAL;
>
> + /*
> + * TODO: migrate to xe_gt_mcr to lookup the mmio range and handle
> + * multicast registers. Steering would need uapi extension.
> + */
> + reg = XE_REG(args->addr);
> +
> xe_force_wake_get(gt_to_fw(&xe->gt[0]), XE_FORCEWAKE_ALL);
>
> if (args->flags & DRM_XE_MMIO_WRITE) {
> @@ -444,10 +451,10 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
> ret = -EINVAL;
> goto exit;
> }
> - xe_mmio_write32(to_gt(xe), args->addr, args->value);
> + xe_mmio_write32(to_gt(xe), reg, args->value);
> break;
> case DRM_XE_MMIO_64BIT:
> - xe_mmio_write64(to_gt(xe), args->addr, args->value);
> + xe_mmio_write64(to_gt(xe), reg, args->value);
> break;
> default:
> drm_dbg(&xe->drm, "Invalid MMIO bit size");
> @@ -462,10 +469,10 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
> if (args->flags & DRM_XE_MMIO_READ) {
> switch (bits_flag) {
> case DRM_XE_MMIO_32BIT:
> - args->value = xe_mmio_read32(to_gt(xe), args->addr);
> + args->value = xe_mmio_read32(to_gt(xe), reg);
> break;
> case DRM_XE_MMIO_64BIT:
> - args->value = xe_mmio_read64(to_gt(xe), args->addr);
> + args->value = xe_mmio_read64(to_gt(xe), reg);
> break;
> default:
> drm_dbg(&xe->drm, "Invalid MMIO bit size");
> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> index 1a32e0f52261..0f792a196545 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.h
> +++ b/drivers/gpu/drm/xe/xe_mmio.h
> @@ -9,6 +9,7 @@
> #include <linux/delay.h>
> #include <linux/io-64-nonatomic-lo-hi.h>
>
> +#include "regs/xe_reg_defs.h"
> #include "xe_gt_types.h"
>
> struct drm_device;
> @@ -18,23 +19,23 @@ struct xe_device;
> int xe_mmio_init(struct xe_device *xe);
>
> static inline void xe_mmio_write32(struct xe_gt *gt,
> - u32 reg, u32 val)
> + struct xe_reg reg, u32 val)
> {
> - if (reg < gt->mmio.adj_limit)
> - reg += gt->mmio.adj_offset;
> + if (reg.reg < gt->mmio.adj_limit)
> + reg.reg += gt->mmio.adj_offset;
>
> - writel(val, gt->mmio.regs + reg);
> + writel(val, gt->mmio.regs + reg.reg);
> }
>
> -static inline u32 xe_mmio_read32(struct xe_gt *gt, u32 reg)
> +static inline u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
> {
> - if (reg < gt->mmio.adj_limit)
> - reg += gt->mmio.adj_offset;
> + if (reg.reg < gt->mmio.adj_limit)
> + reg.reg += gt->mmio.adj_offset;
>
> - return readl(gt->mmio.regs + reg);
> + return readl(gt->mmio.regs + reg.reg);
> }
>
> -static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 clr,
> +static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,
> u32 set)
> {
> u32 old, reg_val;
> @@ -47,24 +48,24 @@ static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 clr,
> }
>
> static inline void xe_mmio_write64(struct xe_gt *gt,
> - u32 reg, u64 val)
> + struct xe_reg reg, u64 val)
> {
> - if (reg < gt->mmio.adj_limit)
> - reg += gt->mmio.adj_offset;
> + if (reg.reg < gt->mmio.adj_limit)
> + reg.reg += gt->mmio.adj_offset;
>
> - writeq(val, gt->mmio.regs + reg);
> + writeq(val, gt->mmio.regs + reg.reg);
> }
>
> -static inline u64 xe_mmio_read64(struct xe_gt *gt, u32 reg)
> +static inline u64 xe_mmio_read64(struct xe_gt *gt, struct xe_reg reg)
> {
> - if (reg < gt->mmio.adj_limit)
> - reg += gt->mmio.adj_offset;
> + if (reg.reg < gt->mmio.adj_limit)
> + reg.reg += gt->mmio.adj_offset;
>
> - return readq(gt->mmio.regs + reg);
> + return readq(gt->mmio.regs + reg.reg);
> }
>
> static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
> - u32 reg, u32 val,
> + struct xe_reg reg, u32 val,
> u32 mask, u32 eval)
> {
> u32 reg_val;
> @@ -75,8 +76,9 @@ static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
> return (reg_val & mask) != eval ? -EINVAL : 0;
> }
>
> -static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val, u32 mask,
> - u32 timeout_us, u32 *out_val, bool atomic)
> +static inline int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 val,
> + u32 mask, u32 timeout_us, u32 *out_val,
> + bool atomic)
> {
> ktime_t cur = ktime_get_raw();
> const ktime_t end = ktime_add_us(cur, timeout_us);
> @@ -114,9 +116,10 @@ static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val, u32 mask,
> int xe_mmio_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
>
> -static inline bool xe_mmio_in_range(const struct xe_mmio_range *range, u32 reg)
> +static inline bool xe_mmio_in_range(const struct xe_mmio_range *range,
> + struct xe_reg reg)
> {
> - return range && reg >= range->start && reg <= range->end;
> + return range && reg.reg >= range->start && reg.reg <= range->end;
> }
>
> int xe_mmio_probe_vram(struct xe_device *xe);
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index f2ceecd536ed..7ad43e53f826 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -477,8 +477,9 @@ static void __init_mocs_table(struct xe_gt *gt,
> for (i = 0;
> i < info->n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;
> i++) {
> - mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, XE_REG(addr + i * 4).reg, mocs);
> - xe_mmio_write32(gt, XE_REG(addr + i * 4).reg, mocs);
> + struct xe_reg reg = XE_REG(addr + i * 4);
> + mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, reg.reg, mocs);
> + xe_mmio_write32(gt, reg, mocs);
> }
> }
>
> @@ -514,7 +515,7 @@ static void init_l3cc_table(struct xe_gt *gt,
> i++) {
> mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).reg,
> l3cc);
> - xe_mmio_write32(gt, LNCFCMOCS(i).reg, l3cc);
> + xe_mmio_write32(gt, LNCFCMOCS(i), l3cc);
> }
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index abee41fa3cb9..b56a65779d26 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -64,14 +64,20 @@ static const u32 mtl_pat_table[] = {
>
> static void program_pat(struct xe_gt *gt, const u32 table[], int n_entries)
> {
> - for (int i = 0; i < n_entries; i++)
> - xe_mmio_write32(gt, _PAT_INDEX(i), table[i]);
> + for (int i = 0; i < n_entries; i++) {
> + struct xe_reg reg = XE_REG(_PAT_INDEX(i));
> +
> + xe_mmio_write32(gt, reg, table[i]);
> + }
> }
>
> static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries)
> {
> - for (int i = 0; i < n_entries; i++)
> - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_INDEX(i)), table[i]);
> + for (int i = 0; i < n_entries; i++) {
> + struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i));
> +
> + xe_gt_mcr_multicast_write(gt, reg_mcr, table[i]);
> + }
> }
>
> void xe_pat_init(struct xe_gt *gt)
> diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
> index 99bb730684ed..7ab70a83f88d 100644
> --- a/drivers/gpu/drm/xe/xe_pcode.c
> +++ b/drivers/gpu/drm/xe/xe_pcode.c
> @@ -43,7 +43,7 @@ static int pcode_mailbox_status(struct xe_gt *gt)
>
> lockdep_assert_held(>->pcode.lock);
>
> - err = xe_mmio_read32(gt, PCODE_MAILBOX.reg) & PCODE_ERROR_MASK;
> + err = xe_mmio_read32(gt, PCODE_MAILBOX) & PCODE_ERROR_MASK;
> if (err) {
> drm_err(>_to_xe(gt)->drm, "PCODE Mailbox failed: %d %s", err,
> err_decode[err].str ?: "Unknown");
> @@ -60,22 +60,22 @@ static int pcode_mailbox_rw(struct xe_gt *gt, u32 mbox, u32 *data0, u32 *data1,
> int err;
> lockdep_assert_held(>->pcode.lock);
>
> - if ((xe_mmio_read32(gt, PCODE_MAILBOX.reg) & PCODE_READY) != 0)
> + if ((xe_mmio_read32(gt, PCODE_MAILBOX) & PCODE_READY) != 0)
> return -EAGAIN;
>
> - xe_mmio_write32(gt, PCODE_DATA0.reg, *data0);
> - xe_mmio_write32(gt, PCODE_DATA1.reg, data1 ? *data1 : 0);
> - xe_mmio_write32(gt, PCODE_MAILBOX.reg, PCODE_READY | mbox);
> + xe_mmio_write32(gt, PCODE_DATA0, *data0);
> + xe_mmio_write32(gt, PCODE_DATA1, data1 ? *data1 : 0);
> + xe_mmio_write32(gt, PCODE_MAILBOX, PCODE_READY | mbox);
>
> - err = xe_mmio_wait32(gt, PCODE_MAILBOX.reg, 0, PCODE_READY,
> + err = xe_mmio_wait32(gt, PCODE_MAILBOX, 0, PCODE_READY,
> timeout_ms * 1000, NULL, atomic);
> if (err)
> return err;
>
> if (return_data) {
> - *data0 = xe_mmio_read32(gt, PCODE_DATA0.reg);
> + *data0 = xe_mmio_read32(gt, PCODE_DATA0);
> if (data1)
> - *data1 = xe_mmio_read32(gt, PCODE_DATA1.reg);
> + *data1 = xe_mmio_read32(gt, PCODE_DATA1);
> }
>
> return pcode_mailbox_status(gt);
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
> index 801f211fb733..51a40a9e532d 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr.c
> +++ b/drivers/gpu/drm/xe/xe_reg_sr.c
> @@ -163,7 +163,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
> else if (entry->clr_bits + 1)
> val = (reg.mcr ?
> xe_gt_mcr_unicast_read_any(gt, reg_mcr) :
> - xe_mmio_read32(gt, reg.reg)) & (~entry->clr_bits);
> + xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
> else
> val = 0;
>
> @@ -179,7 +179,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
> if (entry->reg.mcr)
> xe_gt_mcr_multicast_write(gt, reg_mcr, val);
> else
> - xe_mmio_write32(gt, reg.reg, val);
> + xe_mmio_write32(gt, reg, val);
> }
>
> void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt)
> @@ -232,15 +232,17 @@ void xe_reg_sr_apply_whitelist(struct xe_reg_sr *sr, u32 mmio_base,
> p = drm_debug_printer(KBUILD_MODNAME);
> xa_for_each(&sr->xa, reg, entry) {
> xe_reg_whitelist_print_entry(&p, 0, reg, entry);
> - xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot).reg,
> + xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot),
> reg | entry->set_bits);
> slot++;
> }
>
> /* And clear the rest just in case of garbage */
> - for (; slot < RING_MAX_NONPRIV_SLOTS; slot++)
> - xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot).reg,
> - RING_NOPID(mmio_base).reg);
> + for (; slot < RING_MAX_NONPRIV_SLOTS; slot++) {
> + u32 addr = RING_NOPID(mmio_base).reg;
> +
> + xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
> + }
>
> err = xe_force_wake_put(>->mmio.fw, XE_FORCEWAKE_ALL);
> XE_WARN_ON(err);
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index 5e61b6e61f3a..efc59eb4a491 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -44,10 +44,11 @@ static u32 preparser_disable(bool state)
> return MI_ARB_CHECK | BIT(8) | state;
> }
>
> -static int emit_aux_table_inv(struct xe_gt *gt, u32 addr, u32 *dw, int i)
> +static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
> + u32 *dw, int i)
> {
> dw[i++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
> - dw[i++] = addr + gt->mmio.adj_offset;
> + dw[i++] = reg.reg + gt->mmio.adj_offset;
> dw[i++] = AUX_INV;
> dw[i++] = MI_NOOP;
>
> @@ -202,9 +203,9 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
> /* Wa_1809175790 */
> if (!xe->info.has_flat_ccs) {
> if (decode)
> - i = emit_aux_table_inv(gt, VD0_AUX_NV.reg, dw, i);
> + i = emit_aux_table_inv(gt, VD0_AUX_NV, dw, i);
> else
> - i = emit_aux_table_inv(gt, VE0_AUX_NV.reg, dw, i);
> + i = emit_aux_table_inv(gt, VE0_AUX_NV, dw, i);
> }
> dw[i++] = preparser_disable(false);
>
> @@ -246,7 +247,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
> i = emit_pipe_invalidate(mask_flags, dw, i);
> /* Wa_1809175790 */
> if (!xe->info.has_flat_ccs)
> - i = emit_aux_table_inv(gt, GFX_CCS_AUX_NV.reg, dw, i);
> + i = emit_aux_table_inv(gt, GFX_CCS_AUX_NV, dw, i);
> dw[i++] = preparser_disable(false);
>
> i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
> diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> index 9ce0a0585539..a3855870321f 100644
> --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> @@ -65,7 +65,7 @@ static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
> }
>
> /* Use DSM base address instead for stolen memory */
> - mgr->stolen_base = xe_mmio_read64(gt, DSMBASE.reg) & BDSM_MASK;
> + mgr->stolen_base = xe_mmio_read64(gt, DSMBASE) & BDSM_MASK;
> if (drm_WARN_ON(&xe->drm, vram_size < mgr->stolen_base))
> return 0;
>
> @@ -88,7 +88,7 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr
> u32 stolen_size;
> u32 ggc, gms;
>
> - ggc = xe_mmio_read32(to_gt(xe), GGC.reg);
> + ggc = xe_mmio_read32(to_gt(xe), GGC);
>
> /* check GGMS, should be fixed 0x3 (8MB) */
> if (drm_WARN_ON(&xe->drm, (ggc & GGMS_MASK) != GGMS_MASK))
> diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
> index cd5433b5c970..5c3a571d2a29 100644
> --- a/drivers/gpu/drm/xe/xe_uc_fw.c
> +++ b/drivers/gpu/drm/xe/xe_uc_fw.c
> @@ -462,33 +462,33 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
>
> /* Set the source address for the uCode */
> src_offset = uc_fw_ggtt_offset(uc_fw);
> - xe_mmio_write32(gt, DMA_ADDR_0_LOW.reg, lower_32_bits(src_offset));
> - xe_mmio_write32(gt, DMA_ADDR_0_HIGH.reg, upper_32_bits(src_offset));
> + xe_mmio_write32(gt, DMA_ADDR_0_LOW, lower_32_bits(src_offset));
> + xe_mmio_write32(gt, DMA_ADDR_0_HIGH, upper_32_bits(src_offset));
>
> /* Set the DMA destination */
> - xe_mmio_write32(gt, DMA_ADDR_1_LOW.reg, offset);
> - xe_mmio_write32(gt, DMA_ADDR_1_HIGH.reg, DMA_ADDRESS_SPACE_WOPCM);
> + xe_mmio_write32(gt, DMA_ADDR_1_LOW, offset);
> + xe_mmio_write32(gt, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>
> /*
> * Set the transfer size. The header plus uCode will be copied to WOPCM
> * via DMA, excluding any other components
> */
> - xe_mmio_write32(gt, DMA_COPY_SIZE.reg,
> + xe_mmio_write32(gt, DMA_COPY_SIZE,
> sizeof(struct uc_css_header) + uc_fw->ucode_size);
>
> /* Start the DMA */
> - xe_mmio_write32(gt, DMA_CTRL.reg,
> + xe_mmio_write32(gt, DMA_CTRL,
> _MASKED_BIT_ENABLE(dma_flags | START_DMA));
>
> /* Wait for DMA to finish */
> - ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100000, &dma_ctrl,
> + ret = xe_mmio_wait32(gt, DMA_CTRL, 0, START_DMA, 100000, &dma_ctrl,
> false);
> if (ret)
> drm_err(&xe->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
> xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);
>
> /* Disable the bits once DMA is over */
> - xe_mmio_write32(gt, DMA_CTRL.reg, _MASKED_BIT_DISABLE(dma_flags));
> + xe_mmio_write32(gt, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
> index 7b5014aea9c8..11eea970c207 100644
> --- a/drivers/gpu/drm/xe/xe_wopcm.c
> +++ b/drivers/gpu/drm/xe/xe_wopcm.c
> @@ -124,8 +124,8 @@ static bool __check_layout(struct xe_device *xe, u32 wopcm_size,
> static bool __wopcm_regs_locked(struct xe_gt *gt,
> u32 *guc_wopcm_base, u32 *guc_wopcm_size)
> {
> - u32 reg_base = xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET.reg);
> - u32 reg_size = xe_mmio_read32(gt, GUC_WOPCM_SIZE.reg);
> + u32 reg_base = xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET);
> + u32 reg_size = xe_mmio_read32(gt, GUC_WOPCM_SIZE);
>
> if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) ||
> !(reg_base & GUC_WOPCM_OFFSET_VALID))
> @@ -152,13 +152,13 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
> XE_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
>
> mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
> - err = xe_mmio_write32_and_verify(gt, GUC_WOPCM_SIZE.reg, size, mask,
> + err = xe_mmio_write32_and_verify(gt, GUC_WOPCM_SIZE, size, mask,
> size | GUC_WOPCM_SIZE_LOCKED);
> if (err)
> goto err_out;
>
> mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
> - err = xe_mmio_write32_and_verify(gt, DMA_GUC_WOPCM_OFFSET.reg,
> + err = xe_mmio_write32_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
> base | huc_agent, mask,
> base | huc_agent |
> GUC_WOPCM_OFFSET_VALID);
> @@ -171,10 +171,10 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
> drm_notice(&xe->drm, "Failed to init uC WOPCM registers!\n");
> drm_notice(&xe->drm, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
> DMA_GUC_WOPCM_OFFSET.reg,
> - xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET.reg));
> + xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET));
> drm_notice(&xe->drm, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
> GUC_WOPCM_SIZE.reg,
> - xe_mmio_read32(gt, GUC_WOPCM_SIZE.reg));
> + xe_mmio_read32(gt, GUC_WOPCM_SIZE));
>
> return err;
> }
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 5/7] fixup! drm/xe/display: Implement display support
2023-04-29 6:23 ` [Intel-xe] [PATCH 5/7] fixup! drm/xe/display: Implement display support Lucas De Marchi
@ 2023-05-05 16:59 ` Rodrigo Vivi
2023-05-05 19:29 ` Lucas De Marchi
0 siblings, 1 reply; 27+ messages in thread
From: Rodrigo Vivi @ 2023-05-05 16:59 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Fri, Apr 28, 2023 at 11:23:30PM -0700, Lucas De Marchi wrote:
> With the move of display above xe_reg conversion in xe_mmio,
> it should use the new types everywhere.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
and this is the one that will likely conflict with the series from Jani
right?
I will try to merge his series today, then on your rebase you change
both this and the previous at once.
anyway, on the approach:
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/display/xe_de.h | 89 +++++++++++++++++++-----------
> 1 file changed, 57 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/display/xe_de.h b/drivers/gpu/drm/xe/display/xe_de.h
> index 0c76b0d24d96..e6021f6d031d 100644
> --- a/drivers/gpu/drm/xe/display/xe_de.h
> +++ b/drivers/gpu/drm/xe/display/xe_de.h
> @@ -14,79 +14,95 @@
> #include "i915_reg.h"
>
> static inline u32
> -intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
> +intel_de_read(struct drm_i915_private *i915, i915_reg_t i915_reg)
> {
> - return xe_mmio_read32(to_gt(i915), reg.reg);
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + return xe_mmio_read32(to_gt(i915), reg);
> }
>
> static inline u64
> intel_de_read64_2x32(struct drm_i915_private *i915,
> - i915_reg_t lower_reg, i915_reg_t upper_reg)
> + i915_reg_t i915_lower_reg, i915_reg_t i915_upper_reg)
> {
> + struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));
> + struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));
> u32 upper, lower;
>
> - lower = xe_mmio_read32(to_gt(i915), lower_reg.reg);
> - upper = xe_mmio_read32(to_gt(i915), upper_reg.reg);
> + lower = xe_mmio_read32(to_gt(i915), lower_reg);
> + upper = xe_mmio_read32(to_gt(i915), upper_reg);
> return (u64)upper << 32 | lower;
> }
>
> static inline void
> -intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
> +intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t i915_reg)
> {
> - xe_mmio_read32(to_gt(i915), reg.reg);
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + xe_mmio_read32(to_gt(i915), reg);
> }
>
> static inline void
> -intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
> +intel_de_write(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 val)
> {
> - xe_mmio_write32(to_gt(i915), reg.reg, val);
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + xe_mmio_write32(to_gt(i915), reg, val);
> }
>
> static inline u32
> -intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
> +intel_de_rmw(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 clear, u32 set)
> {
> - return xe_mmio_rmw32(to_gt(i915), reg.reg, clear, set);
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + return xe_mmio_rmw32(to_gt(i915), reg, clear, set);
> }
>
> static inline int
> -intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
> +intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t i915_reg,
> u32 mask, u32 value, unsigned int timeout)
> {
> - return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
> - false);
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + return xe_mmio_wait32(to_gt(i915), reg, value, mask,
> + timeout * USEC_PER_MSEC, NULL, false);
> }
>
> static inline int
> -intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
> +intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t i915_reg,
> u32 mask, u32 value, unsigned int timeout)
> {
> - return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
> - false);
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + return xe_mmio_wait32(to_gt(i915), reg, value, mask,
> + timeout * USEC_PER_MSEC, NULL, false);
> }
>
> static inline int
> -__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
> +__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t i915_reg,
> u32 mask, u32 value,
> unsigned int fast_timeout_us,
> unsigned int slow_timeout_ms, u32 *out_value)
> {
> - return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask,
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + return xe_mmio_wait32(to_gt(i915), reg, value, mask,
> fast_timeout_us + 1000 * slow_timeout_ms,
> out_value, false);
> }
>
> static inline int
> -intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
> +intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t i915_reg,
> u32 mask, unsigned int timeout)
> {
> - return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
> + return intel_de_wait_for_register(i915, i915_reg, mask, mask, timeout);
> }
>
> static inline int
> -intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
> +intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t i915_reg,
> u32 mask, unsigned int timeout)
> {
> - return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
> + return intel_de_wait_for_register(i915, i915_reg, mask, 0, timeout);
> }
>
> /*
> @@ -98,19 +114,23 @@ intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
> * a more localised lock guarding all access to that bank of registers.
> */
> static inline u32
> -intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
> +intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t i915_reg)
> {
> - return xe_mmio_read32(to_gt(i915), reg.reg);
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + return xe_mmio_read32(to_gt(i915), reg);
> }
>
> static inline void
> -intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
> +intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 val)
> {
> - xe_mmio_write32(to_gt(i915), reg.reg, val);
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + xe_mmio_write32(to_gt(i915), reg, val);
> }
>
> static inline void
> -intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
> +intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t i915_reg)
> {
> /*
> * Not implemented, requires lock on all reads/writes.
> @@ -120,15 +140,20 @@ intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
> }
>
> static inline u32
> -intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
> +intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t i915_reg)
> {
> - return xe_mmio_read32(to_gt(i915), reg.reg);
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + return xe_mmio_read32(to_gt(i915), reg);
> }
>
> static inline void
> -intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
> +intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t i915_reg,
> + u32 val)
> {
> - xe_mmio_write32(to_gt(i915), reg.reg, val);
> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> + xe_mmio_write32(to_gt(i915), reg, val);
> }
>
> static inline int
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 6/7] drm/xe: Rename reg field to addr
2023-04-29 6:23 ` [Intel-xe] [PATCH 6/7] drm/xe: Rename reg field to addr Lucas De Marchi
@ 2023-05-05 17:00 ` Rodrigo Vivi
0 siblings, 0 replies; 27+ messages in thread
From: Rodrigo Vivi @ 2023-05-05 17:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Fri, Apr 28, 2023 at 11:23:31PM -0700, Lucas De Marchi wrote:
> Rename the address field to "addr" rather than "reg" so it's easier to
> understand what it is.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
ops, another one impacted by the rebase... sorry
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_reg_defs.h | 6 +++---
> drivers/gpu/drm/xe/tests/xe_rtp_test.c | 2 +-
> drivers/gpu/drm/xe/xe_force_wake.c | 2 +-
> drivers/gpu/drm/xe/xe_gt_mcr.c | 2 +-
> drivers/gpu/drm/xe/xe_guc.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_ads.c | 2 +-
> drivers/gpu/drm/xe/xe_hw_engine.c | 8 ++++----
> drivers/gpu/drm/xe/xe_irq.c | 2 +-
> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
> drivers/gpu/drm/xe/xe_mmio.h | 26 +++++++++++++-------------
> drivers/gpu/drm/xe/xe_mocs.c | 6 +++---
> drivers/gpu/drm/xe/xe_pci.c | 2 +-
> drivers/gpu/drm/xe/xe_reg_sr.c | 6 +++---
> drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
> drivers/gpu/drm/xe/xe_rtp.c | 2 +-
> drivers/gpu/drm/xe/xe_wopcm.c | 4 ++--
> 16 files changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> index da781bc7bdc7..4554362ff4d9 100644
> --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
> @@ -18,8 +18,8 @@
> struct xe_reg {
> union {
> struct {
> - /** @reg: address */
> - u32 reg:22;
> + /** @addr: address */
> + u32 addr:22;
> /**
> * @masked: register is "masked", with upper 16bits used
> * to identify the bits that are updated on the lower
> @@ -71,7 +71,7 @@ struct xe_reg_mcr {
> * object of the right type. However when initializing static const storage,
> * where a compound statement is not allowed, this can be used instead.
> */
> -#define XE_REG_INITIALIZER(r_, ...) { .reg = r_, __VA_ARGS__ }
> +#define XE_REG_INITIALIZER(r_, ...) { .addr = r_, __VA_ARGS__ }
>
>
> /**
> diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> index ad2fe8a39a78..4b2aac5ccf28 100644
> --- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> +++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
> @@ -244,7 +244,7 @@ static void xe_rtp_process_tests(struct kunit *test)
> xe_rtp_process(param->entries, reg_sr, &xe->gt[0], NULL);
>
> xa_for_each(®_sr->xa, idx, sre) {
> - if (idx == param->expected_reg.reg)
> + if (idx == param->expected_reg.addr)
> sr_entry = sre;
>
> count++;
> diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
> index 363b81c3d746..f0f0592fc598 100644
> --- a/drivers/gpu/drm/xe/xe_force_wake.c
> +++ b/drivers/gpu/drm/xe/xe_force_wake.c
> @@ -129,7 +129,7 @@ static int domain_sleep_wait(struct xe_gt *gt,
> for (tmp__ = (mask__); tmp__; tmp__ &= ~BIT(ffs(tmp__) - 1)) \
> for_each_if((domain__ = ((fw__)->domains + \
> (ffs(tmp__) - 1))) && \
> - domain__->reg_ctl.reg)
> + domain__->reg_ctl.addr)
>
> int xe_force_wake_get(struct xe_force_wake *fw,
> enum xe_force_wake_domains domains)
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index 2461e51c0abf..6a9be9d031d4 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -398,7 +398,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> */
> drm_WARN(>_to_xe(gt)->drm, true,
> "Did not find MCR register %#x in any MCR steering table\n",
> - reg.reg);
> + reg.addr);
> *group = 0;
> *instance = 0;
>
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 12b636910460..af7b09086358 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -721,7 +721,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
> response_buf[0] = header;
>
> for (i = 1; i < VF_SW_FLAG_COUNT; i++) {
> - reply_reg.reg += i * sizeof(u32);
> + reply_reg.addr += i * sizeof(u32);
> response_buf[i] = xe_mmio_read32(gt, reply_reg);
> }
> }
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 683f2df09c49..6d550d746909 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -426,7 +426,7 @@ static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,
> unsigned int n_entry)
> {
> struct guc_mmio_reg entry = {
> - .offset = reg.reg,
> + .offset = reg.addr,
> .flags = reg.masked ? GUC_REGSET_MASKED : 0,
> };
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index d1b7ac35c4a0..e62662bc3a86 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -235,20 +235,20 @@ static void hw_engine_fini(struct drm_device *drm, void *arg)
> static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg,
> u32 val)
> {
> - XE_BUG_ON(reg.reg & hwe->mmio_base);
> + XE_BUG_ON(reg.addr & hwe->mmio_base);
> xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
>
> - reg.reg += hwe->mmio_base;
> + reg.addr += hwe->mmio_base;
>
> xe_mmio_write32(hwe->gt, reg, val);
> }
>
> static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)
> {
> - XE_BUG_ON(reg.reg & hwe->mmio_base);
> + XE_BUG_ON(reg.addr & hwe->mmio_base);
> xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
>
> - reg.reg += hwe->mmio_base;
> + reg.addr += hwe->mmio_base;
>
> return xe_mmio_read32(hwe->gt, reg);
> }
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 7aa245792927..5bf359c81cc5 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -36,7 +36,7 @@ static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
>
> drm_WARN(>_to_xe(gt)->drm, 1,
> "Interrupt register 0x%x is not zero: 0x%08x\n",
> - reg.reg, val);
> + reg.addr, val);
> xe_mmio_write32(gt, reg, 0xffffffff);
> xe_mmio_read32(gt, reg);
> xe_mmio_write32(gt, reg, 0xffffffff);
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 0e91004fa06d..c7fbb1cc1f64 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -421,7 +421,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
> unsigned int i;
>
> for (i = 0; i < ARRAY_SIZE(mmio_read_whitelist); i++) {
> - if (mmio_read_whitelist[i].reg == args->addr) {
> + if (mmio_read_whitelist[i].addr == args->addr) {
> allowed = true;
> break;
> }
> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> index 0f792a196545..3b722ff0428e 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.h
> +++ b/drivers/gpu/drm/xe/xe_mmio.h
> @@ -21,18 +21,18 @@ int xe_mmio_init(struct xe_device *xe);
> static inline void xe_mmio_write32(struct xe_gt *gt,
> struct xe_reg reg, u32 val)
> {
> - if (reg.reg < gt->mmio.adj_limit)
> - reg.reg += gt->mmio.adj_offset;
> + if (reg.addr < gt->mmio.adj_limit)
> + reg.addr += gt->mmio.adj_offset;
>
> - writel(val, gt->mmio.regs + reg.reg);
> + writel(val, gt->mmio.regs + reg.addr);
> }
>
> static inline u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
> {
> - if (reg.reg < gt->mmio.adj_limit)
> - reg.reg += gt->mmio.adj_offset;
> + if (reg.addr < gt->mmio.adj_limit)
> + reg.addr += gt->mmio.adj_offset;
>
> - return readl(gt->mmio.regs + reg.reg);
> + return readl(gt->mmio.regs + reg.addr);
> }
>
> static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,
> @@ -50,18 +50,18 @@ static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,
> static inline void xe_mmio_write64(struct xe_gt *gt,
> struct xe_reg reg, u64 val)
> {
> - if (reg.reg < gt->mmio.adj_limit)
> - reg.reg += gt->mmio.adj_offset;
> + if (reg.addr < gt->mmio.adj_limit)
> + reg.addr += gt->mmio.adj_offset;
>
> - writeq(val, gt->mmio.regs + reg.reg);
> + writeq(val, gt->mmio.regs + reg.addr);
> }
>
> static inline u64 xe_mmio_read64(struct xe_gt *gt, struct xe_reg reg)
> {
> - if (reg.reg < gt->mmio.adj_limit)
> - reg.reg += gt->mmio.adj_offset;
> + if (reg.addr < gt->mmio.adj_limit)
> + reg.addr += gt->mmio.adj_offset;
>
> - return readq(gt->mmio.regs + reg.reg);
> + return readq(gt->mmio.regs + reg.addr);
> }
>
> static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
> @@ -119,7 +119,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
> static inline bool xe_mmio_in_range(const struct xe_mmio_range *range,
> struct xe_reg reg)
> {
> - return range && reg.reg >= range->start && reg.reg <= range->end;
> + return range && reg.addr >= range->start && reg.addr <= range->end;
> }
>
> int xe_mmio_probe_vram(struct xe_device *xe);
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index 7ad43e53f826..3ab58b267bda 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -478,7 +478,7 @@ static void __init_mocs_table(struct xe_gt *gt,
> i < info->n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;
> i++) {
> struct xe_reg reg = XE_REG(addr + i * 4);
> - mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, reg.reg, mocs);
> + mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, reg.addr, mocs);
> xe_mmio_write32(gt, reg, mocs);
> }
> }
> @@ -513,7 +513,7 @@ static void init_l3cc_table(struct xe_gt *gt,
> (l3cc = l3cc_combine(get_entry_l3cc(info, 2 * i),
> get_entry_l3cc(info, 2 * i + 1))), 1 : 0;
> i++) {
> - mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).reg,
> + mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).addr,
> l3cc);
> xe_mmio_write32(gt, LNCFCMOCS(i), l3cc);
> }
> @@ -533,7 +533,7 @@ void xe_mocs_init(struct xe_gt *gt)
> gt->mocs.wb_index = table.wb_index;
>
> if (flags & HAS_GLOBAL_MOCS)
> - __init_mocs_table(gt, &table, GLOBAL_MOCS(0).reg);
> + __init_mocs_table(gt, &table, GLOBAL_MOCS(0).addr);
>
> /*
> * Initialize the L3CC table as part of mocs initalization to make
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 8687e51cb0a4..6e55809cfb3d 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -393,7 +393,7 @@ find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
>
> static u32 peek_gmdid(struct xe_device *xe, struct xe_reg gmdid_reg)
> {
> - u32 gmdid_offset = gmdid_reg.reg;
> + u32 gmdid_offset = gmdid_reg.addr;
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> void __iomem *map = pci_iomap_range(pdev, 0, gmdid_offset, sizeof(u32));
> u32 ver;
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
> index 51a40a9e532d..0312823101ad 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr.c
> +++ b/drivers/gpu/drm/xe/xe_reg_sr.c
> @@ -93,7 +93,7 @@ static void reg_sr_inc_error(struct xe_reg_sr *sr)
> int xe_reg_sr_add(struct xe_reg_sr *sr,
> const struct xe_reg_sr_entry *e)
> {
> - unsigned long idx = e->reg.reg;
> + unsigned long idx = e->reg.addr;
> struct xe_reg_sr_entry *pentry = xa_load(&sr->xa, idx);
> int ret;
>
> @@ -174,7 +174,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
> */
> val |= entry->set_bits;
>
> - drm_dbg(&xe->drm, "REG[0x%x] = 0x%08x", reg.reg, val);
> + drm_dbg(&xe->drm, "REG[0x%x] = 0x%08x", reg.addr, val);
>
> if (entry->reg.mcr)
> xe_gt_mcr_multicast_write(gt, reg_mcr, val);
> @@ -239,7 +239,7 @@ void xe_reg_sr_apply_whitelist(struct xe_reg_sr *sr, u32 mmio_base,
>
> /* And clear the rest just in case of garbage */
> for (; slot < RING_MAX_NONPRIV_SLOTS; slot++) {
> - u32 addr = RING_NOPID(mmio_base).reg;
> + u32 addr = RING_NOPID(mmio_base).addr;
>
> xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
> }
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index efc59eb4a491..7d90ffa16078 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -48,7 +48,7 @@ static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
> u32 *dw, int i)
> {
> dw[i++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
> - dw[i++] = reg.reg + gt->mmio.adj_offset;
> + dw[i++] = reg.addr + gt->mmio.adj_offset;
> dw[i++] = AUX_INV;
> dw[i++] = MI_NOOP;
>
> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> index f2a0e8eb4936..0c6a23e14a71 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.c
> +++ b/drivers/gpu/drm/xe/xe_rtp.c
> @@ -101,7 +101,7 @@ static void rtp_add_sr_entry(const struct xe_rtp_action *action,
> .read_mask = action->read_mask,
> };
>
> - sr_entry.reg.reg += mmio_base;
> + sr_entry.reg.addr += mmio_base;
> xe_reg_sr_add(sr, &sr_entry);
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
> index 11eea970c207..35fde8965bca 100644
> --- a/drivers/gpu/drm/xe/xe_wopcm.c
> +++ b/drivers/gpu/drm/xe/xe_wopcm.c
> @@ -170,10 +170,10 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
> err_out:
> drm_notice(&xe->drm, "Failed to init uC WOPCM registers!\n");
> drm_notice(&xe->drm, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
> - DMA_GUC_WOPCM_OFFSET.reg,
> + DMA_GUC_WOPCM_OFFSET.addr,
> xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET));
> drm_notice(&xe->drm, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
> - GUC_WOPCM_SIZE.reg,
> + GUC_WOPCM_SIZE.addr,
> xe_mmio_read32(gt, GUC_WOPCM_SIZE));
>
> return err;
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 7/7] drm/xe: Fix indent in xe_hw_engine_print_state()
2023-04-29 6:23 ` [Intel-xe] [PATCH 7/7] drm/xe: Fix indent in xe_hw_engine_print_state() Lucas De Marchi
@ 2023-05-05 17:01 ` Rodrigo Vivi
0 siblings, 0 replies; 27+ messages in thread
From: Rodrigo Vivi @ 2023-05-05 17:01 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Fri, Apr 28, 2023 at 11:23:32PM -0700, Lucas De Marchi wrote:
> Fix the indent to align with open parenthesis, following the coding
> style.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
if this lands first I change my devcoredump one...
Otherwise this will likely not get needed because I hope
that I'm fixing this there...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_hw_engine.c | 66 +++++++++++++++----------------
> 1 file changed, 33 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index e62662bc3a86..ca98160dc5ee 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -516,70 +516,70 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
> return;
>
> drm_printf(p, "%s (physical), logical instance=%d\n", hwe->name,
> - hwe->logical_instance);
> + hwe->logical_instance);
> drm_printf(p, "\tForcewake: domain 0x%x, ref %d\n",
> - hwe->domain,
> - xe_force_wake_ref(gt_to_fw(hwe->gt), hwe->domain));
> + hwe->domain,
> + xe_force_wake_ref(gt_to_fw(hwe->gt), hwe->domain));
> drm_printf(p, "\tMMIO base: 0x%08x\n", hwe->mmio_base);
>
> drm_printf(p, "\tHWSTAM: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
> + hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
> drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
> + hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
>
> drm_printf(p, "\tRING_EXECLIST_STATUS_LO: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
> + hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
> drm_printf(p, "\tRING_EXECLIST_STATUS_HI: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
> + hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
> drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_LO: 0x%08x\n",
> - hw_engine_mmio_read32(hwe,
> + hw_engine_mmio_read32(hwe,
> RING_EXECLIST_SQ_CONTENTS_LO(0)));
> drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_HI: 0x%08x\n",
> - hw_engine_mmio_read32(hwe,
> + hw_engine_mmio_read32(hwe,
> RING_EXECLIST_SQ_CONTENTS_HI(0)));
> drm_printf(p, "\tRING_EXECLIST_CONTROL: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
> + hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
>
> drm_printf(p, "\tRING_START: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_START(0)));
> + hw_engine_mmio_read32(hwe, RING_START(0)));
> drm_printf(p, "\tRING_HEAD: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
> + hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
> drm_printf(p, "\tRING_TAIL: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
> + hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
> drm_printf(p, "\tRING_CTL: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_CTL(0)));
> + hw_engine_mmio_read32(hwe, RING_CTL(0)));
> drm_printf(p, "\tRING_MODE: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
> + hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
> drm_printf(p, "\tRING_MODE_GEN7: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_MODE(0)));
> + hw_engine_mmio_read32(hwe, RING_MODE(0)));
>
> drm_printf(p, "\tRING_IMR: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_IMR(0)));
> + hw_engine_mmio_read32(hwe, RING_IMR(0)));
> drm_printf(p, "\tRING_ESR: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_ESR(0)));
> + hw_engine_mmio_read32(hwe, RING_ESR(0)));
> drm_printf(p, "\tRING_EMR: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_EMR(0)));
> + hw_engine_mmio_read32(hwe, RING_EMR(0)));
> drm_printf(p, "\tRING_EIR: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, RING_EIR(0)));
> -
> - drm_printf(p, "\tACTHD: 0x%08x_%08x\n",
> - hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
> - hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
> - drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
> - hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
> - hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
> - drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
> - hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
> - hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
> + hw_engine_mmio_read32(hwe, RING_EIR(0)));
> +
> + drm_printf(p, "\tACTHD: 0x%08x_%08x\n",
> + hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
> + hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
> + drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
> + hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
> + hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
> + drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
> + hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
> + hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
>
> drm_printf(p, "\tIPEIR: 0x%08x\n",
> - hw_engine_mmio_read32(hwe, IPEIR(0)));
> + hw_engine_mmio_read32(hwe, IPEIR(0)));
> drm_printf(p, "\tIPEHR: 0x%08x\n\n",
> - hw_engine_mmio_read32(hwe, IPEHR(0)));
> + hw_engine_mmio_read32(hwe, IPEHR(0)));
>
> if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
> drm_printf(p, "\tRCU_MODE: 0x%08x\n",
> - xe_mmio_read32(hwe->gt, RCU_MODE));
> + xe_mmio_read32(hwe->gt, RCU_MODE));
>
> }
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 3/7] drm/xe: Use media base for GMD_ID access
2023-05-01 15:07 ` Lucas De Marchi
@ 2023-05-05 17:05 ` Rodrigo Vivi
2023-05-05 20:19 ` Lucas De Marchi
0 siblings, 1 reply; 27+ messages in thread
From: Rodrigo Vivi @ 2023-05-05 17:05 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Mon, May 01, 2023 at 08:07:28AM -0700, Lucas De Marchi wrote:
> On Sun, Apr 30, 2023 at 07:47:38PM +0200, Michal Wajdeczko wrote:
> >
> >
> > On 29.04.2023 08:23, Lucas De Marchi wrote:
> > > Instead of adding a hardcoded base, define GMD_ID() with a base
> > > argument and use it in all places.
> > >
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +++-
> > > drivers/gpu/drm/xe/xe_pci.c | 9 +++++----
> > > 2 files changed, 8 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > index 4d87f1fe010d..da7b6d2c7e01 100644
> > > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > @@ -8,6 +8,8 @@
> > >
> > > #include "regs/xe_reg_defs.h"
> > >
> > > +#define MTL_MEDIA_GT_BASE 0x380000
> >
> > maybe for completeness (and to avoid using anonymous 0 offset in other
> > places) we should define also:
> >
> > #define GRAPHICS_GT_BASE 0x0
>
> there are very vew places in the driver that would care about the base.
> Today the base is automatically applied for anything using xe_mmio_,
> just like we have it automatically applied in intel_uncore for i915.
> So, we really don't want to change each register to receive base as
> param.
I'm with Michal here. I had the same thought when reviewing and just read
his comment afterwards. Although it is rarely used it would be good
to avoid later confusion.
>
> >
> > > +
> > > /* RPM unit config (Gen8+) */
> > > #define RPM_CONFIG0 XE_REG(0xd00)
> > > #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
> > > @@ -21,7 +23,7 @@
> > > #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4)
> > > #define FORCEWAKE_ACK_RENDER XE_REG(0xd84)
> > >
> > > -#define GMD_ID XE_REG(0xd8c)
> > > +#define GMD_ID(base) XE_REG((base) + 0xd8c)
> >
> > this register is not the only one that's has it's counterpart at this
> > 0x38000 MEDIA offset, and other registers we are treating in automatic
> > way, without the need to explicitly pass the 'base', so I'm not sure we
> > should change that here
>
> becaues in the other cases the base is applied by xe_mmio
>
> >
> > > #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
> > > #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> > > #define GMD_ID_STEP REG_GENMASK(5, 0)
> >
> > btw, is there a plan to s/REG_GENMASK/XE_REG_GENMASK or something ?
>
> no. My plan is to eventually submit a patch to have
> GENMASK_U32 and use it throughout the driver
good idea!
>
> >
> > > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > > index 35dcb8781f2a..8687e51cb0a4 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > @@ -276,7 +276,7 @@ static const struct xe_gt_desc xelpmp_gts[] = {
> > > .type = XE_GT_TYPE_MEDIA,
> > > .vram_id = 0,
> > > .mmio_adj_limit = 0x40000,
> > > - .mmio_adj_offset = 0x380000,
> > > + .mmio_adj_offset = MTL_MEDIA_GT_BASE,
> > > },
> > > };
> > >
> > > @@ -391,8 +391,9 @@ find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
> > > return NULL;
> > > }
> > >
> > > -static u32 peek_gmdid(struct xe_device *xe, u32 gmdid_offset)
> > > +static u32 peek_gmdid(struct xe_device *xe, struct xe_reg gmdid_reg)
> >
> > better to keep u32 but defined as new 'base' for the GMD_ID:
> >
> > peek_gmdid(xe, GRAPHICS_GT_BASE)
> > peek_gmdid(xe, MTL_MEDIA_GT_BASE)
> >
> > then since we parse the value according to the GMDID definition we will
> > prevent passing wrong register offset and always refer to the right
> > GMD_ID address inside the function:
> >
> > static u32 peek_gmdid(struct xe_device *xe, u32 base)
> > {
> > xe_reg gmdid = XE_REG(GMD_ID.addr + base);
>
> we try to minimize those calculations outside the header.
> I don't see a benefit of passing the base here over passing the register
> to be used.
>
> Lucas De Marchi
>
> > ...
> > WARN_ON(base != GRAPHICS_GT_BASE && base != MTL_MEDIA_GT_BASE);
> > ...
> > map = pci_iomap_range(pdev, 0, gmdid.addr, sizeof(u32));
> > ...
> > REG_FIELD_GET(GMD_ID_ARCH_MASK, value)
> >
> >
> > Michal
> >
> > > {
> > > + u32 gmdid_offset = gmdid_reg.reg;
> > > struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> > > void __iomem *map = pci_iomap_range(pdev, 0, gmdid_offset, sizeof(u32));
> > > u32 ver;
> > > @@ -441,7 +442,7 @@ static void handle_gmdid(struct xe_device *xe,
> > > {
> > > u32 ver;
> > >
> > > - ver = peek_gmdid(xe, GMD_ID.reg);
> > > + ver = peek_gmdid(xe, GMD_ID(0));
> > > for (int i = 0; i < ARRAY_SIZE(graphics_ip_map); i++) {
> > > if (ver == graphics_ip_map[i].ver) {
> > > xe->info.graphics_verx100 = ver;
> > > @@ -456,7 +457,7 @@ static void handle_gmdid(struct xe_device *xe,
> > > ver / 100, ver % 100);
> > > }
> > >
> > > - ver = peek_gmdid(xe, GMD_ID.reg + 0x380000);
> > > + ver = peek_gmdid(xe, GMD_ID(MTL_MEDIA_GT_BASE));
> > > for (int i = 0; i < ARRAY_SIZE(media_ip_map); i++) {
> > > if (ver == media_ip_map[i].ver) {
> > > xe->info.media_verx100 = ver;
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 2/7] drm/xe/guc: Handle RCU_MODE as masked from definition
2023-05-05 16:55 ` Rodrigo Vivi
@ 2023-05-05 17:08 ` Lucas De Marchi
2023-05-05 18:17 ` Rodrigo Vivi
0 siblings, 1 reply; 27+ messages in thread
From: Lucas De Marchi @ 2023-05-05 17:08 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe
On Fri, May 05, 2023 at 12:55:28PM -0400, Rodrigo Vivi wrote:
>On Fri, Apr 28, 2023 at 11:23:27PM -0700, Lucas De Marchi wrote:
>> guc_mmio_regset_write() had a flags for the registers to be added to the
>> GuC's regset list. The only register actually using that was RCU_MODE,
>> but it was setting the flags to a bogus value. From
>> struct xe_guc_fwif.h,
>>
>> #define GUC_REGSET_MASKED BIT(0)
>> #define GUC_REGSET_MASKED_WITH_VALUE BIT(2)
>> #define GUC_REGSET_RESTORE_ONLY BIT(3)
>>
>> Cross checking with i915, the only flag to set in RCU_MODE is
>> GUC_REGSET_MASKED. That can be done automatically from the register, as
>> long as the definition is correct.
>>
>> Add the XE_REG_OPTION_MASKED annotation to RCU_MODE and kill the "flags"
>> field in guc_mmio_regset_write(): guc_mmio_regset_write_one() can decide
>> that based on the register being passed.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>I'm still trying to get familiarized with XE_REG_OPTION_MASKED
>but this patch looks right to me:
basically the definition if the register is masked or not comes from
bspec: if the spec says the upper 16bits are the mask, we add the define
in the header saying so.
XE_REG(1) -> creates a normal register with no flags/options
XE_REG(1, XE_REG_OPTION_MASKED) -> creates a masked register
XE_REG_MCR(1) -> creates an MCR register: here it applies both a
flag/option (for places that deal with that in runtime, e.g. RTP
tables), and a different type, for the rest of the driver.
it will be much easier to eventually convert to an auto-generated
header so these options come directly from the spec, which is my
master plan here :)
>
>
>Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 2/7] drm/xe/guc: Handle RCU_MODE as masked from definition
2023-05-05 17:08 ` Lucas De Marchi
@ 2023-05-05 18:17 ` Rodrigo Vivi
0 siblings, 0 replies; 27+ messages in thread
From: Rodrigo Vivi @ 2023-05-05 18:17 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Fri, May 05, 2023 at 10:08:48AM -0700, Lucas De Marchi wrote:
> On Fri, May 05, 2023 at 12:55:28PM -0400, Rodrigo Vivi wrote:
> > On Fri, Apr 28, 2023 at 11:23:27PM -0700, Lucas De Marchi wrote:
> > > guc_mmio_regset_write() had a flags for the registers to be added to the
> > > GuC's regset list. The only register actually using that was RCU_MODE,
> > > but it was setting the flags to a bogus value. From
> > > struct xe_guc_fwif.h,
> > >
> > > #define GUC_REGSET_MASKED BIT(0)
> > > #define GUC_REGSET_MASKED_WITH_VALUE BIT(2)
> > > #define GUC_REGSET_RESTORE_ONLY BIT(3)
> > >
> > > Cross checking with i915, the only flag to set in RCU_MODE is
> > > GUC_REGSET_MASKED. That can be done automatically from the register, as
> > > long as the definition is correct.
> > >
> > > Add the XE_REG_OPTION_MASKED annotation to RCU_MODE and kill the "flags"
> > > field in guc_mmio_regset_write(): guc_mmio_regset_write_one() can decide
> > > that based on the register being passed.
> > >
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >
> > I'm still trying to get familiarized with XE_REG_OPTION_MASKED
> > but this patch looks right to me:
>
> basically the definition if the register is masked or not comes from
> bspec: if the spec says the upper 16bits are the mask, we add the define
> in the header saying so.
>
> XE_REG(1) -> creates a normal register with no flags/options
> XE_REG(1, XE_REG_OPTION_MASKED) -> creates a masked register
> XE_REG_MCR(1) -> creates an MCR register: here it applies both a
> flag/option (for places that deal with that in runtime, e.g. RTP
> tables), and a different type, for the rest of the driver.
it makes sense! thanks for the explanation!
>
> it will be much easier to eventually convert to an auto-generated
> header so these options come directly from the spec, which is my
> master plan here :)
\o/
ack!
>
> >
> >
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> thanks
> Lucas De Marchi
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 4/7] drm/xe/mmio: Use struct xe_reg
2023-05-05 16:57 ` Rodrigo Vivi
@ 2023-05-05 19:26 ` Lucas De Marchi
0 siblings, 0 replies; 27+ messages in thread
From: Lucas De Marchi @ 2023-05-05 19:26 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe
On Fri, May 05, 2023 at 12:57:56PM -0400, Rodrigo Vivi wrote:
>On Fri, Apr 28, 2023 at 11:23:29PM -0700, Lucas De Marchi wrote:
>> Convert all the callers to deal with xe_mmio_*() using struct xe_reg
>> instead of plain u32. In a few places there was also a rename
>> s/reg/reg_val/ when dealing with the value returned so it doesn't get
>> mixed up with the register address.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>have you auto generated this?
kind of. More like a search and replace approach and fixing code nearby,
possibly in a separate commit.
Looking at my bash history I see things like:
git grep -l "[A-Z_0-9]\+\.reg" -- drivers/gpu/drm/xe | \
xargs sed -i 's/\([A-Z_0-9]\+\)\.reg/\1/g'
but that is far from the end result in this patch.
>is this the possible conflict after rebasing that you had raised?
it will, for sure.
Lucas De Marchi
>
>Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>> ---
>> drivers/gpu/drm/xe/xe_device.c | 2 +-
>> drivers/gpu/drm/xe/xe_execlist.c | 18 +--
>> drivers/gpu/drm/xe/xe_force_wake.c | 25 ++--
>> drivers/gpu/drm/xe/xe_force_wake_types.h | 6 +-
>> drivers/gpu/drm/xe/xe_ggtt.c | 6 +-
>> drivers/gpu/drm/xe/xe_gt.c | 4 +-
>> drivers/gpu/drm/xe/xe_gt_clock.c | 6 +-
>> drivers/gpu/drm/xe/xe_gt_mcr.c | 37 +++---
>> drivers/gpu/drm/xe/xe_gt_topology.c | 18 +--
>> drivers/gpu/drm/xe/xe_guc.c | 61 +++++-----
>> drivers/gpu/drm/xe/xe_guc_ads.c | 3 +-
>> drivers/gpu/drm/xe/xe_guc_pc.c | 32 +++---
>> drivers/gpu/drm/xe/xe_guc_types.h | 3 +-
>> drivers/gpu/drm/xe/xe_huc.c | 4 +-
>> drivers/gpu/drm/xe/xe_hw_engine.c | 85 +++++++-------
>> drivers/gpu/drm/xe/xe_irq.c | 138 +++++++++++------------
>> drivers/gpu/drm/xe/xe_mmio.c | 31 +++--
>> drivers/gpu/drm/xe/xe_mmio.h | 47 ++++----
>> drivers/gpu/drm/xe/xe_mocs.c | 7 +-
>> drivers/gpu/drm/xe/xe_pat.c | 14 ++-
>> drivers/gpu/drm/xe/xe_pcode.c | 16 +--
>> drivers/gpu/drm/xe/xe_reg_sr.c | 14 ++-
>> drivers/gpu/drm/xe/xe_ring_ops.c | 11 +-
>> drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 4 +-
>> drivers/gpu/drm/xe/xe_uc_fw.c | 16 +--
>> drivers/gpu/drm/xe/xe_wopcm.c | 12 +-
>> 26 files changed, 325 insertions(+), 295 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>> index 45d6e5ff47fd..f7f4837ded37 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -393,7 +393,7 @@ void xe_device_wmb(struct xe_device *xe)
>>
>> wmb();
>> if (IS_DGFX(xe))
>> - xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33.reg, 0);
>> + xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);
>> }
>>
>> u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
>> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
>> index de4f0044b211..5d2d26e361b9 100644
>> --- a/drivers/gpu/drm/xe/xe_execlist.c
>> +++ b/drivers/gpu/drm/xe/xe_execlist.c
>> @@ -60,7 +60,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
>> }
>>
>> if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
>> - xe_mmio_write32(hwe->gt, RCU_MODE.reg,
>> + xe_mmio_write32(hwe->gt, RCU_MODE,
>> _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
>>
>> xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
>> @@ -78,17 +78,17 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
>> */
>> wmb();
>>
>> - xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base).reg,
>> + xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base),
>> xe_bo_ggtt_addr(hwe->hwsp));
>> - xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base).reg);
>> - xe_mmio_write32(gt, RING_MODE(hwe->mmio_base).reg,
>> + xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base));
>> + xe_mmio_write32(gt, RING_MODE(hwe->mmio_base),
>> _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
>>
>> - xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base).reg,
>> + xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
>> lower_32_bits(lrc_desc));
>> - xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base).reg,
>> + xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),
>> upper_32_bits(lrc_desc));
>> - xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base).reg,
>> + xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base),
>> EL_CTRL_LOAD);
>> }
>>
>> @@ -173,8 +173,8 @@ static u64 read_execlist_status(struct xe_hw_engine *hwe)
>> struct xe_gt *gt = hwe->gt;
>> u32 hi, lo;
>>
>> - lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base).reg);
>> - hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base).reg);
>> + lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base));
>> + hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base));
>>
>> printk(KERN_INFO "EXECLIST_STATUS %d:%d = 0x%08x %08x\n", hwe->class,
>> hwe->instance, hi, lo);
>> diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
>> index 53d73f36a121..363b81c3d746 100644
>> --- a/drivers/gpu/drm/xe/xe_force_wake.c
>> +++ b/drivers/gpu/drm/xe/xe_force_wake.c
>> @@ -8,6 +8,7 @@
>> #include <drm/drm_util.h>
>>
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_reg_defs.h"
>> #include "xe_gt.h"
>> #include "xe_mmio.h"
>>
>> @@ -27,7 +28,7 @@ fw_to_xe(struct xe_force_wake *fw)
>>
>> static void domain_init(struct xe_force_wake_domain *domain,
>> enum xe_force_wake_domain_id id,
>> - u32 reg, u32 ack, u32 val, u32 mask)
>> + struct xe_reg reg, struct xe_reg ack, u32 val, u32 mask)
>> {
>> domain->id = id;
>> domain->reg_ctl = reg;
>> @@ -49,14 +50,14 @@ void xe_force_wake_init_gt(struct xe_gt *gt, struct xe_force_wake *fw)
>> if (xe->info.graphics_verx100 >= 1270) {
>> domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],
>> XE_FW_DOMAIN_ID_GT,
>> - FORCEWAKE_GT.reg,
>> - FORCEWAKE_ACK_GT_MTL.reg,
>> + FORCEWAKE_GT,
>> + FORCEWAKE_ACK_GT_MTL,
>> BIT(0), BIT(16));
>> } else {
>> domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],
>> XE_FW_DOMAIN_ID_GT,
>> - FORCEWAKE_GT.reg,
>> - FORCEWAKE_ACK_GT.reg,
>> + FORCEWAKE_GT,
>> + FORCEWAKE_ACK_GT,
>> BIT(0), BIT(16));
>> }
>> }
>> @@ -71,8 +72,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
>> if (!xe_gt_is_media_type(gt))
>> domain_init(&fw->domains[XE_FW_DOMAIN_ID_RENDER],
>> XE_FW_DOMAIN_ID_RENDER,
>> - FORCEWAKE_RENDER.reg,
>> - FORCEWAKE_ACK_RENDER.reg,
>> + FORCEWAKE_RENDER,
>> + FORCEWAKE_ACK_RENDER,
>> BIT(0), BIT(16));
>>
>> for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
>> @@ -81,8 +82,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
>>
>> domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j],
>> XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j,
>> - FORCEWAKE_MEDIA_VDBOX(j).reg,
>> - FORCEWAKE_ACK_MEDIA_VDBOX(j).reg,
>> + FORCEWAKE_MEDIA_VDBOX(j),
>> + FORCEWAKE_ACK_MEDIA_VDBOX(j),
>> BIT(0), BIT(16));
>> }
>>
>> @@ -92,8 +93,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
>>
>> domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j],
>> XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j,
>> - FORCEWAKE_MEDIA_VEBOX(j).reg,
>> - FORCEWAKE_ACK_MEDIA_VEBOX(j).reg,
>> + FORCEWAKE_MEDIA_VEBOX(j),
>> + FORCEWAKE_ACK_MEDIA_VEBOX(j),
>> BIT(0), BIT(16));
>> }
>> }
>> @@ -128,7 +129,7 @@ static int domain_sleep_wait(struct xe_gt *gt,
>> for (tmp__ = (mask__); tmp__; tmp__ &= ~BIT(ffs(tmp__) - 1)) \
>> for_each_if((domain__ = ((fw__)->domains + \
>> (ffs(tmp__) - 1))) && \
>> - domain__->reg_ctl)
>> + domain__->reg_ctl.reg)
>>
>> int xe_force_wake_get(struct xe_force_wake *fw,
>> enum xe_force_wake_domains domains)
>> diff --git a/drivers/gpu/drm/xe/xe_force_wake_types.h b/drivers/gpu/drm/xe/xe_force_wake_types.h
>> index 208dd629d7b1..cb782696855b 100644
>> --- a/drivers/gpu/drm/xe/xe_force_wake_types.h
>> +++ b/drivers/gpu/drm/xe/xe_force_wake_types.h
>> @@ -9,6 +9,8 @@
>> #include <linux/mutex.h>
>> #include <linux/types.h>
>>
>> +#include "regs/xe_reg_defs.h"
>> +
>> enum xe_force_wake_domain_id {
>> XE_FW_DOMAIN_ID_GT = 0,
>> XE_FW_DOMAIN_ID_RENDER,
>> @@ -56,9 +58,9 @@ struct xe_force_wake_domain {
>> /** @id: domain force wake id */
>> enum xe_force_wake_domain_id id;
>> /** @reg_ctl: domain wake control register address */
>> - u32 reg_ctl;
>> + struct xe_reg reg_ctl;
>> /** @reg_ack: domain ack register address */
>> - u32 reg_ack;
>> + struct xe_reg reg_ack;
>> /** @val: domain wake write value */
>> u32 val;
>> /** @mask: domain mask */
>> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
>> index 9c08031c9350..546240261e0a 100644
>> --- a/drivers/gpu/drm/xe/xe_ggtt.c
>> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
>> @@ -207,12 +207,12 @@ void xe_ggtt_invalidate(struct xe_gt *gt)
>> struct xe_device *xe = gt_to_xe(gt);
>>
>> if (xe->info.platform == XE_PVC) {
>> - xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1.reg,
>> + xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1,
>> PVC_GUC_TLB_INV_DESC1_INVALIDATE);
>> - xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0.reg,
>> + xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0,
>> PVC_GUC_TLB_INV_DESC0_VALID);
>> } else
>> - xe_mmio_write32(gt, GUC_TLB_INV_CR.reg,
>> + xe_mmio_write32(gt, GUC_TLB_INV_CR,
>> GUC_TLB_INV_CR_INVALIDATE);
>> }
>> }
>> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>> index 0d4664e344da..1cc9314e0d43 100644
>> --- a/drivers/gpu/drm/xe/xe_gt.c
>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>> @@ -541,8 +541,8 @@ static int do_gt_reset(struct xe_gt *gt)
>> struct xe_device *xe = gt_to_xe(gt);
>> int err;
>>
>> - xe_mmio_write32(gt, GDRST.reg, GRDOM_FULL);
>> - err = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_FULL, 5000,
>> + xe_mmio_write32(gt, GDRST, GRDOM_FULL);
>> + err = xe_mmio_wait32(gt, GDRST, 0, GRDOM_FULL, 5000,
>> NULL, false);
>> if (err)
>> drm_err(&xe->drm,
>> diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
>> index 49625d49bdcc..7cf11078ff57 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_clock.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
>> @@ -14,7 +14,7 @@
>>
>> static u32 read_reference_ts_freq(struct xe_gt *gt)
>> {
>> - u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE.reg);
>> + u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE);
>> u32 base_freq, frac_freq;
>>
>> base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK,
>> @@ -54,7 +54,7 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg)
>>
>> int xe_gt_clock_init(struct xe_gt *gt)
>> {
>> - u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE.reg);
>> + u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE);
>> u32 freq = 0;
>>
>> /* Assuming gen11+ so assert this assumption is correct */
>> @@ -63,7 +63,7 @@ int xe_gt_clock_init(struct xe_gt *gt)
>> if (ctc_reg & CTC_SOURCE_DIVIDE_LOGIC) {
>> freq = read_reference_ts_freq(gt);
>> } else {
>> - u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0.reg);
>> + u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0);
>>
>> freq = get_crystal_clock_freq(c0);
>>
>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>> index 55b240a5eaa7..2461e51c0abf 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>> @@ -40,6 +40,8 @@
>> * non-terminated instance.
>> */
>>
>> +#define STEER_SEMAPHORE XE_REG(0xFD0)
>> +
>> static inline struct xe_reg to_xe_reg(struct xe_reg_mcr reg_mcr)
>> {
>> return reg_mcr.__reg;
>> @@ -183,9 +185,9 @@ static void init_steering_l3bank(struct xe_gt *gt)
>> {
>> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
>> u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
>> - xe_mmio_read32(gt, MIRROR_FUSE3.reg));
>> + xe_mmio_read32(gt, MIRROR_FUSE3));
>> u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK,
>> - xe_mmio_read32(gt, XEHP_FUSE4.reg));
>> + xe_mmio_read32(gt, XEHP_FUSE4));
>>
>> /*
>> * Group selects mslice, instance selects bank within mslice.
>> @@ -196,7 +198,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
>> bank_mask & BIT(0) ? 0 : 2;
>> } else if (gt_to_xe(gt)->info.platform == XE_DG2) {
>> u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
>> - xe_mmio_read32(gt, MIRROR_FUSE3.reg));
>> + xe_mmio_read32(gt, MIRROR_FUSE3));
>> u32 bank = __ffs(mslice_mask) * 8;
>>
>> /*
>> @@ -208,7 +210,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
>> gt->steering[L3BANK].instance_target = bank & 0x3;
>> } else {
>> u32 fuse = REG_FIELD_GET(L3BANK_MASK,
>> - ~xe_mmio_read32(gt, MIRROR_FUSE3.reg));
>> + ~xe_mmio_read32(gt, MIRROR_FUSE3));
>>
>> gt->steering[L3BANK].group_target = 0; /* unused */
>> gt->steering[L3BANK].instance_target = __ffs(fuse);
>> @@ -218,7 +220,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
>> static void init_steering_mslice(struct xe_gt *gt)
>> {
>> u32 mask = REG_FIELD_GET(MEML3_EN_MASK,
>> - xe_mmio_read32(gt, MIRROR_FUSE3.reg));
>> + xe_mmio_read32(gt, MIRROR_FUSE3));
>>
>> /*
>> * mslice registers are valid (not terminated) if either the meml3
>> @@ -337,8 +339,8 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
>> u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |
>> REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);
>>
>> - xe_mmio_write32(gt, MCFG_MCR_SELECTOR.reg, steer_val);
>> - xe_mmio_write32(gt, SF_MCR_SELECTOR.reg, steer_val);
>> + xe_mmio_write32(gt, MCFG_MCR_SELECTOR, steer_val);
>> + xe_mmio_write32(gt, SF_MCR_SELECTOR, steer_val);
>> /*
>> * For GAM registers, all reads should be directed to instance 1
>> * (unicast reads against other instances are not allowed),
>> @@ -376,7 +378,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
>> continue;
>>
>> for (int i = 0; gt->steering[type].ranges[i].end > 0; i++) {
>> - if (xe_mmio_in_range(>->steering[type].ranges[i], reg.reg)) {
>> + if (xe_mmio_in_range(>->steering[type].ranges[i], reg)) {
>> *group = gt->steering[type].group_target;
>> *instance = gt->steering[type].instance_target;
>> return true;
>> @@ -387,7 +389,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
>> implicit_ranges = gt->steering[IMPLICIT_STEERING].ranges;
>> if (implicit_ranges)
>> for (int i = 0; implicit_ranges[i].end > 0; i++)
>> - if (xe_mmio_in_range(&implicit_ranges[i], reg.reg))
>> + if (xe_mmio_in_range(&implicit_ranges[i], reg))
>> return false;
>>
>> /*
>> @@ -403,8 +405,6 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
>> return true;
>> }
>>
>> -#define STEER_SEMAPHORE 0xFD0
>> -
>> /*
>> * Obtain exclusive access to MCR steering. On MTL and beyond we also need
>> * to synchronize with external clients (e.g., firmware), so a semaphore
>> @@ -446,16 +446,17 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
>> u8 rw_flag, int group, int instance, u32 value)
>> {
>> const struct xe_reg reg = to_xe_reg(reg_mcr);
>> - u32 steer_reg, steer_val, val = 0;
>> + struct xe_reg steer_reg;
>> + u32 steer_val, val = 0;
>>
>> lockdep_assert_held(>->mcr_lock);
>>
>> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
>> - steer_reg = MTL_MCR_SELECTOR.reg;
>> + steer_reg = MTL_MCR_SELECTOR;
>> steer_val = REG_FIELD_PREP(MTL_MCR_GROUPID, group) |
>> REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance);
>> } else {
>> - steer_reg = MCR_SELECTOR.reg;
>> + steer_reg = MCR_SELECTOR;
>> steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, group) |
>> REG_FIELD_PREP(MCR_SUBSLICE_MASK, instance);
>> }
>> @@ -473,9 +474,9 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
>> xe_mmio_write32(gt, steer_reg, steer_val);
>>
>> if (rw_flag == MCR_OP_READ)
>> - val = xe_mmio_read32(gt, reg.reg);
>> + val = xe_mmio_read32(gt, reg);
>> else
>> - xe_mmio_write32(gt, reg.reg, value);
>> + xe_mmio_write32(gt, reg, value);
>>
>> /*
>> * If we turned off the multicast bit (during a write) we're required
>> @@ -517,7 +518,7 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr reg_mcr)
>> group, instance, 0);
>> mcr_unlock(gt);
>> } else {
>> - val = xe_mmio_read32(gt, reg.reg);
>> + val = xe_mmio_read32(gt, reg);
>> }
>>
>> return val;
>> @@ -584,7 +585,7 @@ void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
>> * to touch the steering register.
>> */
>> mcr_lock(gt);
>> - xe_mmio_write32(gt, reg.reg, value);
>> + xe_mmio_write32(gt, reg, value);
>> mcr_unlock(gt);
>> }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
>> index 14cf135fd648..7c3e347e4d74 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_topology.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_topology.c
>> @@ -26,7 +26,7 @@ load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)
>>
>> va_start(argp, numregs);
>> for (i = 0; i < numregs; i++)
>> - fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, u32));
>> + fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, struct xe_reg));
>> va_end(argp);
>>
>> bitmap_from_arr32(mask, fuse_val, numregs * 32);
>> @@ -36,7 +36,7 @@ static void
>> load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
>> {
>> struct xe_device *xe = gt_to_xe(gt);
>> - u32 reg = xe_mmio_read32(gt, XELP_EU_ENABLE.reg);
>> + u32 reg_val = xe_mmio_read32(gt, XELP_EU_ENABLE);
>> u32 val = 0;
>> int i;
>>
>> @@ -47,15 +47,15 @@ load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
>> * of enable).
>> */
>> if (GRAPHICS_VERx100(xe) < 1250)
>> - reg = ~reg & XELP_EU_MASK;
>> + reg_val = ~reg_val & XELP_EU_MASK;
>>
>> /* On PVC, one bit = one EU */
>> if (GRAPHICS_VERx100(xe) == 1260) {
>> - val = reg;
>> + val = reg_val;
>> } else {
>> /* All other platforms, one bit = 2 EU */
>> - for (i = 0; i < fls(reg); i++)
>> - if (reg & BIT(i))
>> + for (i = 0; i < fls(reg_val); i++)
>> + if (reg_val & BIT(i))
>> val |= 0x3 << 2 * i;
>> }
>>
>> @@ -95,10 +95,10 @@ xe_gt_topology_init(struct xe_gt *gt)
>>
>> load_dss_mask(gt, gt->fuse_topo.g_dss_mask,
>> num_geometry_regs,
>> - XELP_GT_GEOMETRY_DSS_ENABLE.reg);
>> + XELP_GT_GEOMETRY_DSS_ENABLE);
>> load_dss_mask(gt, gt->fuse_topo.c_dss_mask, num_compute_regs,
>> - XEHP_GT_COMPUTE_DSS_ENABLE.reg,
>> - XEHPC_GT_COMPUTE_DSS_ENABLE_EXT.reg);
>> + XEHP_GT_COMPUTE_DSS_ENABLE,
>> + XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
>> load_eu_mask(gt, gt->fuse_topo.eu_mask_per_dss);
>>
>> xe_gt_topology_dump(gt, &p);
>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>> index 89d20faced19..12b636910460 100644
>> --- a/drivers/gpu/drm/xe/xe_guc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>> @@ -240,10 +240,10 @@ static void guc_write_params(struct xe_guc *guc)
>>
>> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>
>> - xe_mmio_write32(gt, SOFT_SCRATCH(0).reg, 0);
>> + xe_mmio_write32(gt, SOFT_SCRATCH(0), 0);
>>
>> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
>> - xe_mmio_write32(gt, SOFT_SCRATCH(1 + i).reg, guc->params[i]);
>> + xe_mmio_write32(gt, SOFT_SCRATCH(1 + i), guc->params[i]);
>> }
>>
>> int xe_guc_init(struct xe_guc *guc)
>> @@ -276,9 +276,9 @@ int xe_guc_init(struct xe_guc *guc)
>> guc_init_params(guc);
>>
>> if (xe_gt_is_media_type(gt))
>> - guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT.reg;
>> + guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT;
>> else
>> - guc->notify_reg = GUC_HOST_INTERRUPT.reg;
>> + guc->notify_reg = GUC_HOST_INTERRUPT;
>>
>> xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE);
>>
>> @@ -317,9 +317,9 @@ int xe_guc_reset(struct xe_guc *guc)
>>
>> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>
>> - xe_mmio_write32(gt, GDRST.reg, GRDOM_GUC);
>> + xe_mmio_write32(gt, GDRST, GRDOM_GUC);
>>
>> - ret = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_GUC, 5000,
>> + ret = xe_mmio_wait32(gt, GDRST, 0, GRDOM_GUC, 5000,
>> &gdrst, false);
>> if (ret) {
>> drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",
>> @@ -327,7 +327,7 @@ int xe_guc_reset(struct xe_guc *guc)
>> goto err_out;
>> }
>>
>> - guc_status = xe_mmio_read32(gt, GUC_STATUS.reg);
>> + guc_status = xe_mmio_read32(gt, GUC_STATUS);
>> if (!(guc_status & GS_MIA_IN_RESET)) {
>> drm_err(&xe->drm,
>> "GuC status: 0x%x, MIA core expected to be in reset\n",
>> @@ -360,9 +360,9 @@ static void guc_prepare_xfer(struct xe_guc *guc)
>> shim_flags |= PVC_GUC_MOCS_INDEX(PVC_GUC_MOCS_UC_INDEX);
>>
>> /* Must program this register before loading the ucode with DMA */
>> - xe_mmio_write32(gt, GUC_SHIM_CONTROL.reg, shim_flags);
>> + xe_mmio_write32(gt, GUC_SHIM_CONTROL, shim_flags);
>>
>> - xe_mmio_write32(gt, GT_PM_CONFIG.reg, GT_DOORBELL_ENABLE);
>> + xe_mmio_write32(gt, GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>> }
>>
>> /*
>> @@ -378,7 +378,7 @@ static int guc_xfer_rsa(struct xe_guc *guc)
>> if (guc->fw.rsa_size > 256) {
>> u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) +
>> xe_uc_fw_rsa_offset(&guc->fw);
>> - xe_mmio_write32(gt, UOS_RSA_SCRATCH(0).reg, rsa_ggtt_addr);
>> + xe_mmio_write32(gt, UOS_RSA_SCRATCH(0), rsa_ggtt_addr);
>> return 0;
>> }
>>
>> @@ -387,7 +387,7 @@ static int guc_xfer_rsa(struct xe_guc *guc)
>> return -ENOMEM;
>>
>> for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
>> - xe_mmio_write32(gt, UOS_RSA_SCRATCH(i).reg, rsa[i]);
>> + xe_mmio_write32(gt, UOS_RSA_SCRATCH(i), rsa[i]);
>>
>> return 0;
>> }
>> @@ -415,7 +415,7 @@ static int guc_wait_ucode(struct xe_guc *guc)
>> * 200ms. Even at slowest clock, this should be sufficient. And
>> * in the working case, a larger timeout makes no difference.
>> */
>> - ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS.reg,
>> + ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS,
>> FIELD_PREP(GS_UKERNEL_MASK,
>> XE_GUC_LOAD_STATUS_READY),
>> GS_UKERNEL_MASK, 200000, &status, false);
>> @@ -443,7 +443,7 @@ static int guc_wait_ucode(struct xe_guc *guc)
>> XE_GUC_LOAD_STATUS_EXCEPTION) {
>> drm_info(drm, "GuC firmware exception. EIP: %#x\n",
>> xe_mmio_read32(guc_to_gt(guc),
>> - SOFT_SCRATCH(13).reg));
>> + SOFT_SCRATCH(13)));
>> ret = -ENXIO;
>> }
>>
>> @@ -540,10 +540,10 @@ static void guc_handle_mmio_msg(struct xe_guc *guc)
>>
>> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>
>> - msg = xe_mmio_read32(gt, SOFT_SCRATCH(15).reg);
>> + msg = xe_mmio_read32(gt, SOFT_SCRATCH(15));
>> msg &= XE_GUC_RECV_MSG_EXCEPTION |
>> XE_GUC_RECV_MSG_CRASH_DUMP_POSTED;
>> - xe_mmio_write32(gt, SOFT_SCRATCH(15).reg, 0);
>> + xe_mmio_write32(gt, SOFT_SCRATCH(15), 0);
>>
>> if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED)
>> drm_err(&guc_to_xe(guc)->drm,
>> @@ -561,12 +561,12 @@ static void guc_enable_irq(struct xe_guc *guc)
>> REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) :
>> REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
>>
>> - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE.reg,
>> + xe_mmio_write32(gt, GUC_SG_INTR_ENABLE,
>> REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST));
>> if (xe_gt_is_media_type(gt))
>> - xe_mmio_rmw32(gt, GUC_SG_INTR_MASK.reg, events, 0);
>> + xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0);
>> else
>> - xe_mmio_write32(gt, GUC_SG_INTR_MASK.reg, ~events);
>> + xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~events);
>> }
>>
>> int xe_guc_enable_communication(struct xe_guc *guc)
>> @@ -575,7 +575,7 @@ int xe_guc_enable_communication(struct xe_guc *guc)
>>
>> guc_enable_irq(guc);
>>
>> - xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK.reg,
>> + xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK,
>> ARAT_EXPIRED_INTRMSK, 0);
>>
>> err = xe_guc_ct_enable(&guc->ct);
>> @@ -628,8 +628,8 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
>> struct xe_device *xe = guc_to_xe(guc);
>> struct xe_gt *gt = guc_to_gt(guc);
>> u32 header, reply;
>> - u32 reply_reg = xe_gt_is_media_type(gt) ?
>> - MED_VF_SW_FLAG(0).reg : VF_SW_FLAG(0).reg;
>> + struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?
>> + MED_VF_SW_FLAG(0) : VF_SW_FLAG(0);
>> const u32 LAST_INDEX = VF_SW_FLAG_COUNT;
>> int ret;
>> int i;
>> @@ -649,14 +649,14 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
>> /* Not in critical data-path, just do if else for GT type */
>> if (xe_gt_is_media_type(gt)) {
>> for (i = 0; i < len; ++i)
>> - xe_mmio_write32(gt, MED_VF_SW_FLAG(i).reg,
>> + xe_mmio_write32(gt, MED_VF_SW_FLAG(i),
>> request[i]);
>> - xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX).reg);
>> + xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX));
>> } else {
>> for (i = 0; i < len; ++i)
>> - xe_mmio_write32(gt, VF_SW_FLAG(i).reg,
>> + xe_mmio_write32(gt, VF_SW_FLAG(i),
>> request[i]);
>> - xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX).reg);
>> + xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX));
>> }
>>
>> xe_guc_notify(guc);
>> @@ -720,9 +720,10 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
>> if (response_buf) {
>> response_buf[0] = header;
>>
>> - for (i = 1; i < VF_SW_FLAG_COUNT; i++)
>> - response_buf[i] =
>> - xe_mmio_read32(gt, reply_reg + i * sizeof(u32));
>> + for (i = 1; i < VF_SW_FLAG_COUNT; i++) {
>> + reply_reg.reg += i * sizeof(u32);
>> + response_buf[i] = xe_mmio_read32(gt, reply_reg);
>> + }
>> }
>>
>> /* Use data from the GuC response as our return value */
>> @@ -844,7 +845,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
>> if (err)
>> return;
>>
>> - status = xe_mmio_read32(gt, GUC_STATUS.reg);
>> + status = xe_mmio_read32(gt, GUC_STATUS);
>>
>> drm_printf(p, "\nGuC status 0x%08x:\n", status);
>> drm_printf(p, "\tBootrom status = 0x%x\n",
>> @@ -859,7 +860,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
>> drm_puts(p, "\nScratch registers:\n");
>> for (i = 0; i < SOFT_SCRATCH_COUNT; i++) {
>> drm_printf(p, "\t%2d: \t0x%x\n",
>> - i, xe_mmio_read32(gt, SOFT_SCRATCH(i).reg));
>> + i, xe_mmio_read32(gt, SOFT_SCRATCH(i)));
>> }
>>
>> xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
>> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
>> index 84c2d7c624c6..683f2df09c49 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
>> @@ -428,7 +428,6 @@ static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,
>> struct guc_mmio_reg entry = {
>> .offset = reg.reg,
>> .flags = reg.masked ? GUC_REGSET_MASKED : 0,
>> - /* TODO: steering */
>> };
>>
>> xe_map_memcpy_to(ads_to_xe(ads), regset_map, n_entry * sizeof(entry),
>> @@ -551,7 +550,7 @@ static void guc_doorbell_init(struct xe_guc_ads *ads)
>>
>> if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) {
>> u32 distdbreg =
>> - xe_mmio_read32(gt, DIST_DBS_POPULATED.reg);
>> + xe_mmio_read32(gt, DIST_DBS_POPULATED);
>>
>> ads_blob_write(ads,
>> system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
>> index 72d460d5323b..e799faa1c6b8 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>> @@ -317,9 +317,9 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
>> u32 reg;
>>
>> if (xe_gt_is_media_type(gt))
>> - reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY.reg);
>> + reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY);
>> else
>> - reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY.reg);
>> + reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY);
>>
>> pc->rpe_freq = REG_FIELD_GET(MTL_RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
>> }
>> @@ -336,9 +336,9 @@ static void tgl_update_rpe_value(struct xe_guc_pc *pc)
>> * PCODE at a different register
>> */
>> if (xe->info.platform == XE_PVC)
>> - reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP.reg);
>> + reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);
>> else
>> - reg = xe_mmio_read32(gt, GEN10_FREQ_INFO_REC.reg);
>> + reg = xe_mmio_read32(gt, GEN10_FREQ_INFO_REC);
>>
>> pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
>> }
>> @@ -380,10 +380,10 @@ static ssize_t freq_act_show(struct device *dev,
>> goto out;
>>
>> if (xe->info.platform == XE_METEORLAKE) {
>> - freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1.reg);
>> + freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);
>> freq = REG_FIELD_GET(MTL_CAGF_MASK, freq);
>> } else {
>> - freq = xe_mmio_read32(gt, GEN12_RPSTAT1.reg);
>> + freq = xe_mmio_read32(gt, GEN12_RPSTAT1);
>> freq = REG_FIELD_GET(GEN12_CAGF_MASK, freq);
>> }
>>
>> @@ -413,7 +413,7 @@ static ssize_t freq_cur_show(struct device *dev,
>> if (ret)
>> goto out;
>>
>> - freq = xe_mmio_read32(gt, RPNSWREQ.reg);
>> + freq = xe_mmio_read32(gt, RPNSWREQ);
>>
>> freq = REG_FIELD_GET(REQ_RATIO_MASK, freq);
>> ret = sysfs_emit(buf, "%d\n", decode_freq(freq));
>> @@ -588,7 +588,7 @@ static ssize_t rc_status_show(struct device *dev,
>> u32 reg;
>>
>> xe_device_mem_access_get(gt_to_xe(gt));
>> - reg = xe_mmio_read32(gt, GT_CORE_STATUS.reg);
>> + reg = xe_mmio_read32(gt, GT_CORE_STATUS);
>> xe_device_mem_access_put(gt_to_xe(gt));
>>
>> switch (REG_FIELD_GET(RCN_MASK, reg)) {
>> @@ -615,7 +615,7 @@ static ssize_t rc6_residency_show(struct device *dev,
>> if (ret)
>> goto out;
>>
>> - reg = xe_mmio_read32(gt, GT_GFX_RC6.reg);
>> + reg = xe_mmio_read32(gt, GT_GFX_RC6);
>> ret = sysfs_emit(buff, "%u\n", reg);
>>
>> XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
>> @@ -646,9 +646,9 @@ static void mtl_init_fused_rp_values(struct xe_guc_pc *pc)
>> xe_device_assert_mem_access(pc_to_xe(pc));
>>
>> if (xe_gt_is_media_type(gt))
>> - reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP.reg);
>> + reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP);
>> else
>> - reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP.reg);
>> + reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP);
>> pc->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, reg) *
>> GT_FREQUENCY_MULTIPLIER;
>> pc->rpn_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, reg) *
>> @@ -664,9 +664,9 @@ static void tgl_init_fused_rp_values(struct xe_guc_pc *pc)
>> xe_device_assert_mem_access(pc_to_xe(pc));
>>
>> if (xe->info.platform == XE_PVC)
>> - reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP.reg);
>> + reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);
>> else
>> - reg = xe_mmio_read32(gt, GEN6_RP_STATE_CAP.reg);
>> + reg = xe_mmio_read32(gt, GEN6_RP_STATE_CAP);
>> pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
>> pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
>> }
>> @@ -745,9 +745,9 @@ static int pc_gucrc_disable(struct xe_guc_pc *pc)
>> if (ret)
>> return ret;
>>
>> - xe_mmio_write32(gt, PG_ENABLE.reg, 0);
>> - xe_mmio_write32(gt, RC_CONTROL.reg, 0);
>> - xe_mmio_write32(gt, RC_STATE.reg, 0);
>> + xe_mmio_write32(gt, PG_ENABLE, 0);
>> + xe_mmio_write32(gt, RC_CONTROL, 0);
>> + xe_mmio_write32(gt, RC_STATE, 0);
>>
>> XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
>> return 0;
>> diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
>> index ac7eec28934d..a304dce4e9f4 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_types.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_types.h
>> @@ -9,6 +9,7 @@
>> #include <linux/idr.h>
>> #include <linux/xarray.h>
>>
>> +#include "regs/xe_reg_defs.h"
>> #include "xe_guc_ads_types.h"
>> #include "xe_guc_ct_types.h"
>> #include "xe_guc_fwif.h"
>> @@ -74,7 +75,7 @@ struct xe_guc {
>> /**
>> * @notify_reg: Register which is written to notify GuC of H2G messages
>> */
>> - u32 notify_reg;
>> + struct xe_reg notify_reg;
>> /** @params: Control params for fw initialization */
>> u32 params[GUC_CTL_MAX_DWORDS];
>> };
>> diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
>> index 55dcaab34ea4..e0377083d1f2 100644
>> --- a/drivers/gpu/drm/xe/xe_huc.c
>> +++ b/drivers/gpu/drm/xe/xe_huc.c
>> @@ -84,7 +84,7 @@ int xe_huc_auth(struct xe_huc *huc)
>> goto fail;
>> }
>>
>> - ret = xe_mmio_wait32(gt, HUC_KERNEL_LOAD_INFO.reg,
>> + ret = xe_mmio_wait32(gt, HUC_KERNEL_LOAD_INFO,
>> HUC_LOAD_SUCCESSFUL,
>> HUC_LOAD_SUCCESSFUL, 100000, NULL, false);
>> if (ret) {
>> @@ -126,7 +126,7 @@ void xe_huc_print_info(struct xe_huc *huc, struct drm_printer *p)
>> return;
>>
>> drm_printf(p, "\nHuC status: 0x%08x\n",
>> - xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO.reg));
>> + xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO));
>>
>> xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
>> }
>> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>> index 795302bcd3ae..d1b7ac35c4a0 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>> @@ -232,20 +232,25 @@ static void hw_engine_fini(struct drm_device *drm, void *arg)
>> hwe->gt = NULL;
>> }
>>
>> -static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, u32 reg, u32 val)
>> +static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg,
>> + u32 val)
>> {
>> - XE_BUG_ON(reg & hwe->mmio_base);
>> + XE_BUG_ON(reg.reg & hwe->mmio_base);
>> xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
>>
>> - xe_mmio_write32(hwe->gt, reg + hwe->mmio_base, val);
>> + reg.reg += hwe->mmio_base;
>> +
>> + xe_mmio_write32(hwe->gt, reg, val);
>> }
>>
>> -static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, u32 reg)
>> +static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)
>> {
>> - XE_BUG_ON(reg & hwe->mmio_base);
>> + XE_BUG_ON(reg.reg & hwe->mmio_base);
>> xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
>>
>> - return xe_mmio_read32(hwe->gt, reg + hwe->mmio_base);
>> + reg.reg += hwe->mmio_base;
>> +
>> + return xe_mmio_read32(hwe->gt, reg);
>> }
>>
>> void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
>> @@ -254,17 +259,17 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
>> xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
>>
>> if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
>> - xe_mmio_write32(hwe->gt, RCU_MODE.reg,
>> + xe_mmio_write32(hwe->gt, RCU_MODE,
>> _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
>>
>> - hw_engine_mmio_write32(hwe, RING_HWSTAM(0).reg, ~0x0);
>> - hw_engine_mmio_write32(hwe, RING_HWS_PGA(0).reg,
>> + hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0);
>> + hw_engine_mmio_write32(hwe, RING_HWS_PGA(0),
>> xe_bo_ggtt_addr(hwe->hwsp));
>> - hw_engine_mmio_write32(hwe, RING_MODE(0).reg,
>> + hw_engine_mmio_write32(hwe, RING_MODE(0),
>> _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
>> - hw_engine_mmio_write32(hwe, RING_MI_MODE(0).reg,
>> + hw_engine_mmio_write32(hwe, RING_MI_MODE(0),
>> _MASKED_BIT_DISABLE(STOP_RING));
>> - hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg);
>> + hw_engine_mmio_read32(hwe, RING_MI_MODE(0));
>> }
>>
>> static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>> @@ -379,7 +384,7 @@ static void read_media_fuses(struct xe_gt *gt)
>>
>> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>
>> - media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE.reg);
>> + media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE);
>>
>> /*
>> * Pre-Xe_HP platforms had register bits representing absent engines,
>> @@ -421,7 +426,7 @@ static void read_copy_fuses(struct xe_gt *gt)
>>
>> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>>
>> - bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3.reg);
>> + bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3);
>> bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
>>
>> /* BCS0 is always present; only BCS1-BCS8 may be fused off */
>> @@ -518,63 +523,63 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
>> drm_printf(p, "\tMMIO base: 0x%08x\n", hwe->mmio_base);
>>
>> drm_printf(p, "\tHWSTAM: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_HWSTAM(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
>> drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_HWS_PGA(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
>>
>> drm_printf(p, "\tRING_EXECLIST_STATUS_LO: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
>> drm_printf(p, "\tRING_EXECLIST_STATUS_HI: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
>> drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_LO: 0x%08x\n",
>> hw_engine_mmio_read32(hwe,
>> - RING_EXECLIST_SQ_CONTENTS_LO(0).reg));
>> + RING_EXECLIST_SQ_CONTENTS_LO(0)));
>> drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_HI: 0x%08x\n",
>> hw_engine_mmio_read32(hwe,
>> - RING_EXECLIST_SQ_CONTENTS_HI(0).reg));
>> + RING_EXECLIST_SQ_CONTENTS_HI(0)));
>> drm_printf(p, "\tRING_EXECLIST_CONTROL: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
>>
>> drm_printf(p, "\tRING_START: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_START(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_START(0)));
>> drm_printf(p, "\tRING_HEAD: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_HEAD(0).reg) & HEAD_ADDR);
>> + hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
>> drm_printf(p, "\tRING_TAIL: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_TAIL(0).reg) & TAIL_ADDR);
>> + hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
>> drm_printf(p, "\tRING_CTL: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_CTL(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_CTL(0)));
>> drm_printf(p, "\tRING_MODE: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
>> drm_printf(p, "\tRING_MODE_GEN7: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_MODE(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_MODE(0)));
>>
>> drm_printf(p, "\tRING_IMR: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_IMR(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_IMR(0)));
>> drm_printf(p, "\tRING_ESR: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_ESR(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_ESR(0)));
>> drm_printf(p, "\tRING_EMR: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_EMR(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_EMR(0)));
>> drm_printf(p, "\tRING_EIR: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_EIR(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_EIR(0)));
>>
>> drm_printf(p, "\tACTHD: 0x%08x_%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0).reg),
>> - hw_engine_mmio_read32(hwe, RING_ACTHD(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
>> + hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
>> drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0).reg),
>> - hw_engine_mmio_read32(hwe, RING_BBADDR(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
>> + hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
>> drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
>> - hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0).reg),
>> - hw_engine_mmio_read32(hwe, RING_DMA_FADD(0).reg));
>> + hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
>> + hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
>>
>> drm_printf(p, "\tIPEIR: 0x%08x\n",
>> - hw_engine_mmio_read32(hwe, IPEIR(0).reg));
>> + hw_engine_mmio_read32(hwe, IPEIR(0)));
>> drm_printf(p, "\tIPEHR: 0x%08x\n\n",
>> - hw_engine_mmio_read32(hwe, IPEHR(0).reg));
>> + hw_engine_mmio_read32(hwe, IPEHR(0)));
>>
>> if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
>> drm_printf(p, "\tRCU_MODE: 0x%08x\n",
>> - xe_mmio_read32(hwe->gt, RCU_MODE.reg));
>> + xe_mmio_read32(hwe->gt, RCU_MODE));
>>
>> }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index ac72c1a38e5c..7aa245792927 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -29,7 +29,7 @@
>>
>> static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
>> {
>> - u32 val = xe_mmio_read32(gt, reg.reg);
>> + u32 val = xe_mmio_read32(gt, reg);
>>
>> if (val == 0)
>> return;
>> @@ -37,10 +37,10 @@ static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
>> drm_WARN(>_to_xe(gt)->drm, 1,
>> "Interrupt register 0x%x is not zero: 0x%08x\n",
>> reg.reg, val);
>> - xe_mmio_write32(gt, reg.reg, 0xffffffff);
>> - xe_mmio_read32(gt, reg.reg);
>> - xe_mmio_write32(gt, reg.reg, 0xffffffff);
>> - xe_mmio_read32(gt, reg.reg);
>> + xe_mmio_write32(gt, reg, 0xffffffff);
>> + xe_mmio_read32(gt, reg);
>> + xe_mmio_write32(gt, reg, 0xffffffff);
>> + xe_mmio_read32(gt, reg);
>> }
>>
>> /*
>> @@ -55,32 +55,32 @@ static void unmask_and_enable(struct xe_gt *gt, u32 irqregs, u32 bits)
>> */
>> assert_iir_is_zero(gt, IIR(irqregs));
>>
>> - xe_mmio_write32(gt, IER(irqregs).reg, bits);
>> - xe_mmio_write32(gt, IMR(irqregs).reg, ~bits);
>> + xe_mmio_write32(gt, IER(irqregs), bits);
>> + xe_mmio_write32(gt, IMR(irqregs), ~bits);
>>
>> /* Posting read */
>> - xe_mmio_read32(gt, IMR(irqregs).reg);
>> + xe_mmio_read32(gt, IMR(irqregs));
>> }
>>
>> /* Mask and disable all interrupts. */
>> static void mask_and_disable(struct xe_gt *gt, u32 irqregs)
>> {
>> - xe_mmio_write32(gt, IMR(irqregs).reg, ~0);
>> + xe_mmio_write32(gt, IMR(irqregs), ~0);
>> /* Posting read */
>> - xe_mmio_read32(gt, IMR(irqregs).reg);
>> + xe_mmio_read32(gt, IMR(irqregs));
>>
>> - xe_mmio_write32(gt, IER(irqregs).reg, 0);
>> + xe_mmio_write32(gt, IER(irqregs), 0);
>>
>> /* IIR can theoretically queue up two events. Be paranoid. */
>> - xe_mmio_write32(gt, IIR(irqregs).reg, ~0);
>> - xe_mmio_read32(gt, IIR(irqregs).reg);
>> - xe_mmio_write32(gt, IIR(irqregs).reg, ~0);
>> - xe_mmio_read32(gt, IIR(irqregs).reg);
>> + xe_mmio_write32(gt, IIR(irqregs), ~0);
>> + xe_mmio_read32(gt, IIR(irqregs));
>> + xe_mmio_write32(gt, IIR(irqregs), ~0);
>> + xe_mmio_read32(gt, IIR(irqregs));
>> }
>>
>> static u32 xelp_intr_disable(struct xe_gt *gt)
>> {
>> - xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, 0);
>> + xe_mmio_write32(gt, GFX_MSTR_IRQ, 0);
>>
>> /*
>> * Now with master disabled, get a sample of level indications
>> @@ -88,7 +88,7 @@ static u32 xelp_intr_disable(struct xe_gt *gt)
>> * New indications can and will light up during processing,
>> * and will generate new interrupt after enabling master.
>> */
>> - return xe_mmio_read32(gt, GFX_MSTR_IRQ.reg);
>> + return xe_mmio_read32(gt, GFX_MSTR_IRQ);
>> }
>>
>> static u32
>> @@ -99,18 +99,18 @@ gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
>> if (!(master_ctl & GU_MISC_IRQ))
>> return 0;
>>
>> - iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET).reg);
>> + iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET));
>> if (likely(iir))
>> - xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET).reg, iir);
>> + xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET), iir);
>>
>> return iir;
>> }
>>
>> static inline void xelp_intr_enable(struct xe_gt *gt, bool stall)
>> {
>> - xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, MASTER_IRQ);
>> + xe_mmio_write32(gt, GFX_MSTR_IRQ, MASTER_IRQ);
>> if (stall)
>> - xe_mmio_read32(gt, GFX_MSTR_IRQ.reg);
>> + xe_mmio_read32(gt, GFX_MSTR_IRQ);
>> }
>>
>> static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
>> @@ -133,41 +133,41 @@ static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
>> smask = irqs << 16;
>>
>> /* Enable RCS, BCS, VCS and VECS class interrupts. */
>> - xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE.reg, dmask);
>> - xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE.reg, dmask);
>> + xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
>> + xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
>> if (ccs_mask)
>> - xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE.reg, smask);
>> + xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
>>
>> /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
>> - xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK.reg, ~smask);
>> - xe_mmio_write32(gt, BCS_RSVD_INTR_MASK.reg, ~smask);
>> + xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
>> + xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
>> if (bcs_mask & (BIT(1)|BIT(2)))
>> - xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK.reg, ~dmask);
>> + xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
>> if (bcs_mask & (BIT(3)|BIT(4)))
>> - xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK.reg, ~dmask);
>> + xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
>> if (bcs_mask & (BIT(5)|BIT(6)))
>> - xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK.reg, ~dmask);
>> + xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
>> if (bcs_mask & (BIT(7)|BIT(8)))
>> - xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK.reg, ~dmask);
>> - xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK.reg, ~dmask);
>> - xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK.reg, ~dmask);
>> - xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK.reg, ~dmask);
>> + xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
>> + xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
>> + xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
>> + xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
>> if (ccs_mask & (BIT(0)|BIT(1)))
>> - xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK.reg, ~dmask);
>> + xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
>> if (ccs_mask & (BIT(2)|BIT(3)))
>> - xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK.reg, ~dmask);
>> + xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
>>
>> /*
>> * RPS interrupts will get enabled/disabled on demand when RPS itself
>> * is enabled/disabled.
>> */
>> /* TODO: gt->pm_ier, gt->pm_imr */
>> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE.reg, 0);
>> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK.reg, ~0);
>> + xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
>> + xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
>>
>> /* Same thing for GuC interrupts */
>> - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE.reg, 0);
>> - xe_mmio_write32(gt, GUC_SG_INTR_MASK.reg, ~0);
>> + xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
>> + xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
>> }
>>
>> static void xelp_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
>> @@ -192,7 +192,7 @@ gt_engine_identity(struct xe_device *xe,
>>
>> lockdep_assert_held(&xe->irq.lock);
>>
>> - xe_mmio_write32(gt, IIR_REG_SELECTOR(bank).reg, BIT(bit));
>> + xe_mmio_write32(gt, IIR_REG_SELECTOR(bank), BIT(bit));
>>
>> /*
>> * NB: Specs do not specify how long to spin wait,
>> @@ -200,7 +200,7 @@ gt_engine_identity(struct xe_device *xe,
>> */
>> timeout_ts = (local_clock() >> 10) + 100;
>> do {
>> - ident = xe_mmio_read32(gt, INTR_IDENTITY_REG(bank).reg);
>> + ident = xe_mmio_read32(gt, INTR_IDENTITY_REG(bank));
>> } while (!(ident & INTR_DATA_VALID) &&
>> !time_after32(local_clock() >> 10, timeout_ts));
>>
>> @@ -210,7 +210,7 @@ gt_engine_identity(struct xe_device *xe,
>> return 0;
>> }
>>
>> - xe_mmio_write32(gt, INTR_IDENTITY_REG(bank).reg, INTR_DATA_VALID);
>> + xe_mmio_write32(gt, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
>>
>> return ident;
>> }
>> @@ -249,11 +249,11 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
>>
>> if (!xe_gt_is_media_type(gt)) {
>> intr_dw[bank] =
>> - xe_mmio_read32(gt, GT_INTR_DW(bank).reg);
>> + xe_mmio_read32(gt, GT_INTR_DW(bank));
>> for_each_set_bit(bit, intr_dw + bank, 32)
>> identity[bit] = gt_engine_identity(xe, gt,
>> bank, bit);
>> - xe_mmio_write32(gt, GT_INTR_DW(bank).reg,
>> + xe_mmio_write32(gt, GT_INTR_DW(bank),
>> intr_dw[bank]);
>> }
>>
>> @@ -315,14 +315,14 @@ static u32 dg1_intr_disable(struct xe_device *xe)
>> u32 val;
>>
>> /* First disable interrupts */
>> - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR.reg, 0);
>> + xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, 0);
>>
>> /* Get the indication levels and ack the master unit */
>> - val = xe_mmio_read32(gt, DG1_MSTR_TILE_INTR.reg);
>> + val = xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
>> if (unlikely(!val))
>> return 0;
>>
>> - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR.reg, val);
>> + xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, val);
>>
>> return val;
>> }
>> @@ -331,9 +331,9 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
>> {
>> struct xe_gt *gt = xe_device_get_gt(xe, 0);
>>
>> - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR.reg, DG1_MSTR_IRQ);
>> + xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
>> if (stall)
>> - xe_mmio_read32(gt, DG1_MSTR_TILE_INTR.reg);
>> + xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
>> }
>>
>> static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
>> @@ -373,7 +373,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>> continue;
>>
>> if (!xe_gt_is_media_type(gt))
>> - master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ.reg);
>> + master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ);
>>
>> /*
>> * We might be in irq handler just when PCIe DPC is initiated
>> @@ -387,7 +387,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>> }
>>
>> if (!xe_gt_is_media_type(gt))
>> - xe_mmio_write32(gt, GFX_MSTR_IRQ.reg, master_ctl);
>> + xe_mmio_write32(gt, GFX_MSTR_IRQ, master_ctl);
>> gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
>>
>> /*
>> @@ -416,34 +416,34 @@ static void gt_irq_reset(struct xe_gt *gt)
>> u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
>>
>> /* Disable RCS, BCS, VCS and VECS class engines. */
>> - xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE.reg, 0);
>> - xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE.reg, 0);
>> + xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, 0);
>> + xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, 0);
>> if (ccs_mask)
>> - xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE.reg, 0);
>> + xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, 0);
>>
>> /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
>> - xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK.reg, ~0);
>> - xe_mmio_write32(gt, BCS_RSVD_INTR_MASK.reg, ~0);
>> + xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~0);
>> + xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~0);
>> if (bcs_mask & (BIT(1)|BIT(2)))
>> - xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK.reg, ~0);
>> + xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
>> if (bcs_mask & (BIT(3)|BIT(4)))
>> - xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK.reg, ~0);
>> + xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
>> if (bcs_mask & (BIT(5)|BIT(6)))
>> - xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK.reg, ~0);
>> + xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
>> if (bcs_mask & (BIT(7)|BIT(8)))
>> - xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK.reg, ~0);
>> - xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK.reg, ~0);
>> - xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK.reg, ~0);
>> - xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK.reg, ~0);
>> + xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
>> + xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~0);
>> + xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~0);
>> + xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~0);
>> if (ccs_mask & (BIT(0)|BIT(1)))
>> - xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK.reg, ~0);
>> + xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~0);
>> if (ccs_mask & (BIT(2)|BIT(3)))
>> - xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK.reg, ~0);
>> + xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~0);
>>
>> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE.reg, 0);
>> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK.reg, ~0);
>> - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE.reg, 0);
>> - xe_mmio_write32(gt, GUC_SG_INTR_MASK.reg, ~0);
>> + xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
>> + xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
>> + xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
>> + xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
>> }
>>
>> static void xelp_irq_reset(struct xe_gt *gt)
>> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
>> index 3b719c774efa..0e91004fa06d 100644
>> --- a/drivers/gpu/drm/xe/xe_mmio.c
>> +++ b/drivers/gpu/drm/xe/xe_mmio.c
>> @@ -153,13 +153,13 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_si
>> struct xe_gt *gt = xe_device_get_gt(xe, 0);
>> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>> int err;
>> - u32 reg;
>> + u32 reg_val;
>>
>> if (!xe->info.has_flat_ccs) {
>> *vram_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
>> if (usable_size)
>> *usable_size = min(*vram_size,
>> - xe_mmio_read64(gt, GSMBASE.reg));
>> + xe_mmio_read64(gt, GSMBASE));
>> return 0;
>> }
>>
>> @@ -167,11 +167,11 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_si
>> if (err)
>> return err;
>>
>> - reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE0_ADDR_RANGE);
>> - *vram_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
>> + reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE0_ADDR_RANGE);
>> + *vram_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg_val) * SZ_1G;
>> if (usable_size) {
>> - reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
>> - *usable_size = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
>> + reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
>> + *usable_size = (u64)REG_FIELD_GET(GENMASK(31, 8), reg_val) * SZ_64K;
>> drm_info(&xe->drm, "vram_size: 0x%llx usable_size: 0x%llx\n",
>> *vram_size, *usable_size);
>> }
>> @@ -298,7 +298,7 @@ static void xe_mmio_probe_tiles(struct xe_device *xe)
>> if (xe->info.tile_count == 1)
>> return;
>>
>> - mtcfg = xe_mmio_read64(gt, XEHP_MTCFG_ADDR.reg);
>> + mtcfg = xe_mmio_read64(gt, XEHP_MTCFG_ADDR);
>> adj_tile_count = xe->info.tile_count =
>> REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
>> if (xe->info.media_verx100 >= 1300)
>> @@ -374,7 +374,7 @@ int xe_mmio_init(struct xe_device *xe)
>> * keep the GT powered down; we won't be able to communicate with it
>> * and we should not continue with driver initialization.
>> */
>> - if (IS_DGFX(xe) && !(xe_mmio_read32(gt, GU_CNTL.reg) & LMEM_INIT)) {
>> + if (IS_DGFX(xe) && !(xe_mmio_read32(gt, GU_CNTL) & LMEM_INIT)) {
>> drm_err(&xe->drm, "VRAM not initialized by firmware\n");
>> return -ENODEV;
>> }
>> @@ -403,6 +403,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
>> struct xe_device *xe = to_xe_device(dev);
>> struct drm_xe_mmio *args = data;
>> unsigned int bits_flag, bytes;
>> + struct xe_reg reg;
>> bool allowed;
>> int ret = 0;
>>
>> @@ -435,6 +436,12 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
>> if (XE_IOCTL_ERR(xe, args->addr + bytes > xe->mmio.size))
>> return -EINVAL;
>>
>> + /*
>> + * TODO: migrate to xe_gt_mcr to lookup the mmio range and handle
>> + * multicast registers. Steering would need uapi extension.
>> + */
>> + reg = XE_REG(args->addr);
>> +
>> xe_force_wake_get(gt_to_fw(&xe->gt[0]), XE_FORCEWAKE_ALL);
>>
>> if (args->flags & DRM_XE_MMIO_WRITE) {
>> @@ -444,10 +451,10 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
>> ret = -EINVAL;
>> goto exit;
>> }
>> - xe_mmio_write32(to_gt(xe), args->addr, args->value);
>> + xe_mmio_write32(to_gt(xe), reg, args->value);
>> break;
>> case DRM_XE_MMIO_64BIT:
>> - xe_mmio_write64(to_gt(xe), args->addr, args->value);
>> + xe_mmio_write64(to_gt(xe), reg, args->value);
>> break;
>> default:
>> drm_dbg(&xe->drm, "Invalid MMIO bit size");
>> @@ -462,10 +469,10 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
>> if (args->flags & DRM_XE_MMIO_READ) {
>> switch (bits_flag) {
>> case DRM_XE_MMIO_32BIT:
>> - args->value = xe_mmio_read32(to_gt(xe), args->addr);
>> + args->value = xe_mmio_read32(to_gt(xe), reg);
>> break;
>> case DRM_XE_MMIO_64BIT:
>> - args->value = xe_mmio_read64(to_gt(xe), args->addr);
>> + args->value = xe_mmio_read64(to_gt(xe), reg);
>> break;
>> default:
>> drm_dbg(&xe->drm, "Invalid MMIO bit size");
>> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
>> index 1a32e0f52261..0f792a196545 100644
>> --- a/drivers/gpu/drm/xe/xe_mmio.h
>> +++ b/drivers/gpu/drm/xe/xe_mmio.h
>> @@ -9,6 +9,7 @@
>> #include <linux/delay.h>
>> #include <linux/io-64-nonatomic-lo-hi.h>
>>
>> +#include "regs/xe_reg_defs.h"
>> #include "xe_gt_types.h"
>>
>> struct drm_device;
>> @@ -18,23 +19,23 @@ struct xe_device;
>> int xe_mmio_init(struct xe_device *xe);
>>
>> static inline void xe_mmio_write32(struct xe_gt *gt,
>> - u32 reg, u32 val)
>> + struct xe_reg reg, u32 val)
>> {
>> - if (reg < gt->mmio.adj_limit)
>> - reg += gt->mmio.adj_offset;
>> + if (reg.reg < gt->mmio.adj_limit)
>> + reg.reg += gt->mmio.adj_offset;
>>
>> - writel(val, gt->mmio.regs + reg);
>> + writel(val, gt->mmio.regs + reg.reg);
>> }
>>
>> -static inline u32 xe_mmio_read32(struct xe_gt *gt, u32 reg)
>> +static inline u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
>> {
>> - if (reg < gt->mmio.adj_limit)
>> - reg += gt->mmio.adj_offset;
>> + if (reg.reg < gt->mmio.adj_limit)
>> + reg.reg += gt->mmio.adj_offset;
>>
>> - return readl(gt->mmio.regs + reg);
>> + return readl(gt->mmio.regs + reg.reg);
>> }
>>
>> -static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 clr,
>> +static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,
>> u32 set)
>> {
>> u32 old, reg_val;
>> @@ -47,24 +48,24 @@ static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 clr,
>> }
>>
>> static inline void xe_mmio_write64(struct xe_gt *gt,
>> - u32 reg, u64 val)
>> + struct xe_reg reg, u64 val)
>> {
>> - if (reg < gt->mmio.adj_limit)
>> - reg += gt->mmio.adj_offset;
>> + if (reg.reg < gt->mmio.adj_limit)
>> + reg.reg += gt->mmio.adj_offset;
>>
>> - writeq(val, gt->mmio.regs + reg);
>> + writeq(val, gt->mmio.regs + reg.reg);
>> }
>>
>> -static inline u64 xe_mmio_read64(struct xe_gt *gt, u32 reg)
>> +static inline u64 xe_mmio_read64(struct xe_gt *gt, struct xe_reg reg)
>> {
>> - if (reg < gt->mmio.adj_limit)
>> - reg += gt->mmio.adj_offset;
>> + if (reg.reg < gt->mmio.adj_limit)
>> + reg.reg += gt->mmio.adj_offset;
>>
>> - return readq(gt->mmio.regs + reg);
>> + return readq(gt->mmio.regs + reg.reg);
>> }
>>
>> static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
>> - u32 reg, u32 val,
>> + struct xe_reg reg, u32 val,
>> u32 mask, u32 eval)
>> {
>> u32 reg_val;
>> @@ -75,8 +76,9 @@ static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
>> return (reg_val & mask) != eval ? -EINVAL : 0;
>> }
>>
>> -static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val, u32 mask,
>> - u32 timeout_us, u32 *out_val, bool atomic)
>> +static inline int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 val,
>> + u32 mask, u32 timeout_us, u32 *out_val,
>> + bool atomic)
>> {
>> ktime_t cur = ktime_get_raw();
>> const ktime_t end = ktime_add_us(cur, timeout_us);
>> @@ -114,9 +116,10 @@ static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val, u32 mask,
>> int xe_mmio_ioctl(struct drm_device *dev, void *data,
>> struct drm_file *file);
>>
>> -static inline bool xe_mmio_in_range(const struct xe_mmio_range *range, u32 reg)
>> +static inline bool xe_mmio_in_range(const struct xe_mmio_range *range,
>> + struct xe_reg reg)
>> {
>> - return range && reg >= range->start && reg <= range->end;
>> + return range && reg.reg >= range->start && reg.reg <= range->end;
>> }
>>
>> int xe_mmio_probe_vram(struct xe_device *xe);
>> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
>> index f2ceecd536ed..7ad43e53f826 100644
>> --- a/drivers/gpu/drm/xe/xe_mocs.c
>> +++ b/drivers/gpu/drm/xe/xe_mocs.c
>> @@ -477,8 +477,9 @@ static void __init_mocs_table(struct xe_gt *gt,
>> for (i = 0;
>> i < info->n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;
>> i++) {
>> - mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, XE_REG(addr + i * 4).reg, mocs);
>> - xe_mmio_write32(gt, XE_REG(addr + i * 4).reg, mocs);
>> + struct xe_reg reg = XE_REG(addr + i * 4);
>> + mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, reg.reg, mocs);
>> + xe_mmio_write32(gt, reg, mocs);
>> }
>> }
>>
>> @@ -514,7 +515,7 @@ static void init_l3cc_table(struct xe_gt *gt,
>> i++) {
>> mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).reg,
>> l3cc);
>> - xe_mmio_write32(gt, LNCFCMOCS(i).reg, l3cc);
>> + xe_mmio_write32(gt, LNCFCMOCS(i), l3cc);
>> }
>> }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
>> index abee41fa3cb9..b56a65779d26 100644
>> --- a/drivers/gpu/drm/xe/xe_pat.c
>> +++ b/drivers/gpu/drm/xe/xe_pat.c
>> @@ -64,14 +64,20 @@ static const u32 mtl_pat_table[] = {
>>
>> static void program_pat(struct xe_gt *gt, const u32 table[], int n_entries)
>> {
>> - for (int i = 0; i < n_entries; i++)
>> - xe_mmio_write32(gt, _PAT_INDEX(i), table[i]);
>> + for (int i = 0; i < n_entries; i++) {
>> + struct xe_reg reg = XE_REG(_PAT_INDEX(i));
>> +
>> + xe_mmio_write32(gt, reg, table[i]);
>> + }
>> }
>>
>> static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries)
>> {
>> - for (int i = 0; i < n_entries; i++)
>> - xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_INDEX(i)), table[i]);
>> + for (int i = 0; i < n_entries; i++) {
>> + struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i));
>> +
>> + xe_gt_mcr_multicast_write(gt, reg_mcr, table[i]);
>> + }
>> }
>>
>> void xe_pat_init(struct xe_gt *gt)
>> diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
>> index 99bb730684ed..7ab70a83f88d 100644
>> --- a/drivers/gpu/drm/xe/xe_pcode.c
>> +++ b/drivers/gpu/drm/xe/xe_pcode.c
>> @@ -43,7 +43,7 @@ static int pcode_mailbox_status(struct xe_gt *gt)
>>
>> lockdep_assert_held(>->pcode.lock);
>>
>> - err = xe_mmio_read32(gt, PCODE_MAILBOX.reg) & PCODE_ERROR_MASK;
>> + err = xe_mmio_read32(gt, PCODE_MAILBOX) & PCODE_ERROR_MASK;
>> if (err) {
>> drm_err(>_to_xe(gt)->drm, "PCODE Mailbox failed: %d %s", err,
>> err_decode[err].str ?: "Unknown");
>> @@ -60,22 +60,22 @@ static int pcode_mailbox_rw(struct xe_gt *gt, u32 mbox, u32 *data0, u32 *data1,
>> int err;
>> lockdep_assert_held(>->pcode.lock);
>>
>> - if ((xe_mmio_read32(gt, PCODE_MAILBOX.reg) & PCODE_READY) != 0)
>> + if ((xe_mmio_read32(gt, PCODE_MAILBOX) & PCODE_READY) != 0)
>> return -EAGAIN;
>>
>> - xe_mmio_write32(gt, PCODE_DATA0.reg, *data0);
>> - xe_mmio_write32(gt, PCODE_DATA1.reg, data1 ? *data1 : 0);
>> - xe_mmio_write32(gt, PCODE_MAILBOX.reg, PCODE_READY | mbox);
>> + xe_mmio_write32(gt, PCODE_DATA0, *data0);
>> + xe_mmio_write32(gt, PCODE_DATA1, data1 ? *data1 : 0);
>> + xe_mmio_write32(gt, PCODE_MAILBOX, PCODE_READY | mbox);
>>
>> - err = xe_mmio_wait32(gt, PCODE_MAILBOX.reg, 0, PCODE_READY,
>> + err = xe_mmio_wait32(gt, PCODE_MAILBOX, 0, PCODE_READY,
>> timeout_ms * 1000, NULL, atomic);
>> if (err)
>> return err;
>>
>> if (return_data) {
>> - *data0 = xe_mmio_read32(gt, PCODE_DATA0.reg);
>> + *data0 = xe_mmio_read32(gt, PCODE_DATA0);
>> if (data1)
>> - *data1 = xe_mmio_read32(gt, PCODE_DATA1.reg);
>> + *data1 = xe_mmio_read32(gt, PCODE_DATA1);
>> }
>>
>> return pcode_mailbox_status(gt);
>> diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
>> index 801f211fb733..51a40a9e532d 100644
>> --- a/drivers/gpu/drm/xe/xe_reg_sr.c
>> +++ b/drivers/gpu/drm/xe/xe_reg_sr.c
>> @@ -163,7 +163,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
>> else if (entry->clr_bits + 1)
>> val = (reg.mcr ?
>> xe_gt_mcr_unicast_read_any(gt, reg_mcr) :
>> - xe_mmio_read32(gt, reg.reg)) & (~entry->clr_bits);
>> + xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
>> else
>> val = 0;
>>
>> @@ -179,7 +179,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
>> if (entry->reg.mcr)
>> xe_gt_mcr_multicast_write(gt, reg_mcr, val);
>> else
>> - xe_mmio_write32(gt, reg.reg, val);
>> + xe_mmio_write32(gt, reg, val);
>> }
>>
>> void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt)
>> @@ -232,15 +232,17 @@ void xe_reg_sr_apply_whitelist(struct xe_reg_sr *sr, u32 mmio_base,
>> p = drm_debug_printer(KBUILD_MODNAME);
>> xa_for_each(&sr->xa, reg, entry) {
>> xe_reg_whitelist_print_entry(&p, 0, reg, entry);
>> - xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot).reg,
>> + xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot),
>> reg | entry->set_bits);
>> slot++;
>> }
>>
>> /* And clear the rest just in case of garbage */
>> - for (; slot < RING_MAX_NONPRIV_SLOTS; slot++)
>> - xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot).reg,
>> - RING_NOPID(mmio_base).reg);
>> + for (; slot < RING_MAX_NONPRIV_SLOTS; slot++) {
>> + u32 addr = RING_NOPID(mmio_base).reg;
>> +
>> + xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
>> + }
>>
>> err = xe_force_wake_put(>->mmio.fw, XE_FORCEWAKE_ALL);
>> XE_WARN_ON(err);
>> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
>> index 5e61b6e61f3a..efc59eb4a491 100644
>> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
>> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
>> @@ -44,10 +44,11 @@ static u32 preparser_disable(bool state)
>> return MI_ARB_CHECK | BIT(8) | state;
>> }
>>
>> -static int emit_aux_table_inv(struct xe_gt *gt, u32 addr, u32 *dw, int i)
>> +static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
>> + u32 *dw, int i)
>> {
>> dw[i++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
>> - dw[i++] = addr + gt->mmio.adj_offset;
>> + dw[i++] = reg.reg + gt->mmio.adj_offset;
>> dw[i++] = AUX_INV;
>> dw[i++] = MI_NOOP;
>>
>> @@ -202,9 +203,9 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
>> /* Wa_1809175790 */
>> if (!xe->info.has_flat_ccs) {
>> if (decode)
>> - i = emit_aux_table_inv(gt, VD0_AUX_NV.reg, dw, i);
>> + i = emit_aux_table_inv(gt, VD0_AUX_NV, dw, i);
>> else
>> - i = emit_aux_table_inv(gt, VE0_AUX_NV.reg, dw, i);
>> + i = emit_aux_table_inv(gt, VE0_AUX_NV, dw, i);
>> }
>> dw[i++] = preparser_disable(false);
>>
>> @@ -246,7 +247,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
>> i = emit_pipe_invalidate(mask_flags, dw, i);
>> /* Wa_1809175790 */
>> if (!xe->info.has_flat_ccs)
>> - i = emit_aux_table_inv(gt, GFX_CCS_AUX_NV.reg, dw, i);
>> + i = emit_aux_table_inv(gt, GFX_CCS_AUX_NV, dw, i);
>> dw[i++] = preparser_disable(false);
>>
>> i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
>> diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
>> index 9ce0a0585539..a3855870321f 100644
>> --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
>> +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
>> @@ -65,7 +65,7 @@ static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
>> }
>>
>> /* Use DSM base address instead for stolen memory */
>> - mgr->stolen_base = xe_mmio_read64(gt, DSMBASE.reg) & BDSM_MASK;
>> + mgr->stolen_base = xe_mmio_read64(gt, DSMBASE) & BDSM_MASK;
>> if (drm_WARN_ON(&xe->drm, vram_size < mgr->stolen_base))
>> return 0;
>>
>> @@ -88,7 +88,7 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr
>> u32 stolen_size;
>> u32 ggc, gms;
>>
>> - ggc = xe_mmio_read32(to_gt(xe), GGC.reg);
>> + ggc = xe_mmio_read32(to_gt(xe), GGC);
>>
>> /* check GGMS, should be fixed 0x3 (8MB) */
>> if (drm_WARN_ON(&xe->drm, (ggc & GGMS_MASK) != GGMS_MASK))
>> diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
>> index cd5433b5c970..5c3a571d2a29 100644
>> --- a/drivers/gpu/drm/xe/xe_uc_fw.c
>> +++ b/drivers/gpu/drm/xe/xe_uc_fw.c
>> @@ -462,33 +462,33 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
>>
>> /* Set the source address for the uCode */
>> src_offset = uc_fw_ggtt_offset(uc_fw);
>> - xe_mmio_write32(gt, DMA_ADDR_0_LOW.reg, lower_32_bits(src_offset));
>> - xe_mmio_write32(gt, DMA_ADDR_0_HIGH.reg, upper_32_bits(src_offset));
>> + xe_mmio_write32(gt, DMA_ADDR_0_LOW, lower_32_bits(src_offset));
>> + xe_mmio_write32(gt, DMA_ADDR_0_HIGH, upper_32_bits(src_offset));
>>
>> /* Set the DMA destination */
>> - xe_mmio_write32(gt, DMA_ADDR_1_LOW.reg, offset);
>> - xe_mmio_write32(gt, DMA_ADDR_1_HIGH.reg, DMA_ADDRESS_SPACE_WOPCM);
>> + xe_mmio_write32(gt, DMA_ADDR_1_LOW, offset);
>> + xe_mmio_write32(gt, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>>
>> /*
>> * Set the transfer size. The header plus uCode will be copied to WOPCM
>> * via DMA, excluding any other components
>> */
>> - xe_mmio_write32(gt, DMA_COPY_SIZE.reg,
>> + xe_mmio_write32(gt, DMA_COPY_SIZE,
>> sizeof(struct uc_css_header) + uc_fw->ucode_size);
>>
>> /* Start the DMA */
>> - xe_mmio_write32(gt, DMA_CTRL.reg,
>> + xe_mmio_write32(gt, DMA_CTRL,
>> _MASKED_BIT_ENABLE(dma_flags | START_DMA));
>>
>> /* Wait for DMA to finish */
>> - ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100000, &dma_ctrl,
>> + ret = xe_mmio_wait32(gt, DMA_CTRL, 0, START_DMA, 100000, &dma_ctrl,
>> false);
>> if (ret)
>> drm_err(&xe->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
>> xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);
>>
>> /* Disable the bits once DMA is over */
>> - xe_mmio_write32(gt, DMA_CTRL.reg, _MASKED_BIT_DISABLE(dma_flags));
>> + xe_mmio_write32(gt, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
>>
>> return ret;
>> }
>> diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
>> index 7b5014aea9c8..11eea970c207 100644
>> --- a/drivers/gpu/drm/xe/xe_wopcm.c
>> +++ b/drivers/gpu/drm/xe/xe_wopcm.c
>> @@ -124,8 +124,8 @@ static bool __check_layout(struct xe_device *xe, u32 wopcm_size,
>> static bool __wopcm_regs_locked(struct xe_gt *gt,
>> u32 *guc_wopcm_base, u32 *guc_wopcm_size)
>> {
>> - u32 reg_base = xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET.reg);
>> - u32 reg_size = xe_mmio_read32(gt, GUC_WOPCM_SIZE.reg);
>> + u32 reg_base = xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET);
>> + u32 reg_size = xe_mmio_read32(gt, GUC_WOPCM_SIZE);
>>
>> if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) ||
>> !(reg_base & GUC_WOPCM_OFFSET_VALID))
>> @@ -152,13 +152,13 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
>> XE_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
>>
>> mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
>> - err = xe_mmio_write32_and_verify(gt, GUC_WOPCM_SIZE.reg, size, mask,
>> + err = xe_mmio_write32_and_verify(gt, GUC_WOPCM_SIZE, size, mask,
>> size | GUC_WOPCM_SIZE_LOCKED);
>> if (err)
>> goto err_out;
>>
>> mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
>> - err = xe_mmio_write32_and_verify(gt, DMA_GUC_WOPCM_OFFSET.reg,
>> + err = xe_mmio_write32_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
>> base | huc_agent, mask,
>> base | huc_agent |
>> GUC_WOPCM_OFFSET_VALID);
>> @@ -171,10 +171,10 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
>> drm_notice(&xe->drm, "Failed to init uC WOPCM registers!\n");
>> drm_notice(&xe->drm, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
>> DMA_GUC_WOPCM_OFFSET.reg,
>> - xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET.reg));
>> + xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET));
>> drm_notice(&xe->drm, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
>> GUC_WOPCM_SIZE.reg,
>> - xe_mmio_read32(gt, GUC_WOPCM_SIZE.reg));
>> + xe_mmio_read32(gt, GUC_WOPCM_SIZE));
>>
>> return err;
>> }
>> --
>> 2.40.1
>>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 5/7] fixup! drm/xe/display: Implement display support
2023-05-05 16:59 ` Rodrigo Vivi
@ 2023-05-05 19:29 ` Lucas De Marchi
2023-05-05 19:47 ` Rodrigo Vivi
0 siblings, 1 reply; 27+ messages in thread
From: Lucas De Marchi @ 2023-05-05 19:29 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe
On Fri, May 05, 2023 at 12:59:32PM -0400, Rodrigo Vivi wrote:
>On Fri, Apr 28, 2023 at 11:23:30PM -0700, Lucas De Marchi wrote:
>> With the move of display above xe_reg conversion in xe_mmio,
>> it should use the new types everywhere.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>and this is the one that will likely conflict with the series from Jani
>right?
>
>I will try to merge his series today, then on your rebase you change
>both this and the previous at once.
not sure I understand. Aren't we going to move display up anymore?
If I squash this patch on the previous one, it will create a conflict
when we move display up again, so I'd rather keep this separate as a
fixup commit to be squashed in the initial display commit.
Lucas De Marchi
>
>anyway, on the approach:
>
>Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>
>> ---
>> drivers/gpu/drm/xe/display/xe_de.h | 89 +++++++++++++++++++-----------
>> 1 file changed, 57 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/display/xe_de.h b/drivers/gpu/drm/xe/display/xe_de.h
>> index 0c76b0d24d96..e6021f6d031d 100644
>> --- a/drivers/gpu/drm/xe/display/xe_de.h
>> +++ b/drivers/gpu/drm/xe/display/xe_de.h
>> @@ -14,79 +14,95 @@
>> #include "i915_reg.h"
>>
>> static inline u32
>> -intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
>> +intel_de_read(struct drm_i915_private *i915, i915_reg_t i915_reg)
>> {
>> - return xe_mmio_read32(to_gt(i915), reg.reg);
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + return xe_mmio_read32(to_gt(i915), reg);
>> }
>>
>> static inline u64
>> intel_de_read64_2x32(struct drm_i915_private *i915,
>> - i915_reg_t lower_reg, i915_reg_t upper_reg)
>> + i915_reg_t i915_lower_reg, i915_reg_t i915_upper_reg)
>> {
>> + struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));
>> + struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));
>> u32 upper, lower;
>>
>> - lower = xe_mmio_read32(to_gt(i915), lower_reg.reg);
>> - upper = xe_mmio_read32(to_gt(i915), upper_reg.reg);
>> + lower = xe_mmio_read32(to_gt(i915), lower_reg);
>> + upper = xe_mmio_read32(to_gt(i915), upper_reg);
>> return (u64)upper << 32 | lower;
>> }
>>
>> static inline void
>> -intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
>> +intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t i915_reg)
>> {
>> - xe_mmio_read32(to_gt(i915), reg.reg);
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + xe_mmio_read32(to_gt(i915), reg);
>> }
>>
>> static inline void
>> -intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
>> +intel_de_write(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 val)
>> {
>> - xe_mmio_write32(to_gt(i915), reg.reg, val);
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + xe_mmio_write32(to_gt(i915), reg, val);
>> }
>>
>> static inline u32
>> -intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
>> +intel_de_rmw(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 clear, u32 set)
>> {
>> - return xe_mmio_rmw32(to_gt(i915), reg.reg, clear, set);
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + return xe_mmio_rmw32(to_gt(i915), reg, clear, set);
>> }
>>
>> static inline int
>> -intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
>> +intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t i915_reg,
>> u32 mask, u32 value, unsigned int timeout)
>> {
>> - return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
>> - false);
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + return xe_mmio_wait32(to_gt(i915), reg, value, mask,
>> + timeout * USEC_PER_MSEC, NULL, false);
>> }
>>
>> static inline int
>> -intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
>> +intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t i915_reg,
>> u32 mask, u32 value, unsigned int timeout)
>> {
>> - return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
>> - false);
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + return xe_mmio_wait32(to_gt(i915), reg, value, mask,
>> + timeout * USEC_PER_MSEC, NULL, false);
>> }
>>
>> static inline int
>> -__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
>> +__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t i915_reg,
>> u32 mask, u32 value,
>> unsigned int fast_timeout_us,
>> unsigned int slow_timeout_ms, u32 *out_value)
>> {
>> - return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask,
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + return xe_mmio_wait32(to_gt(i915), reg, value, mask,
>> fast_timeout_us + 1000 * slow_timeout_ms,
>> out_value, false);
>> }
>>
>> static inline int
>> -intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
>> +intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t i915_reg,
>> u32 mask, unsigned int timeout)
>> {
>> - return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
>> + return intel_de_wait_for_register(i915, i915_reg, mask, mask, timeout);
>> }
>>
>> static inline int
>> -intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
>> +intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t i915_reg,
>> u32 mask, unsigned int timeout)
>> {
>> - return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
>> + return intel_de_wait_for_register(i915, i915_reg, mask, 0, timeout);
>> }
>>
>> /*
>> @@ -98,19 +114,23 @@ intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
>> * a more localised lock guarding all access to that bank of registers.
>> */
>> static inline u32
>> -intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
>> +intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t i915_reg)
>> {
>> - return xe_mmio_read32(to_gt(i915), reg.reg);
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + return xe_mmio_read32(to_gt(i915), reg);
>> }
>>
>> static inline void
>> -intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
>> +intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 val)
>> {
>> - xe_mmio_write32(to_gt(i915), reg.reg, val);
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + xe_mmio_write32(to_gt(i915), reg, val);
>> }
>>
>> static inline void
>> -intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
>> +intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t i915_reg)
>> {
>> /*
>> * Not implemented, requires lock on all reads/writes.
>> @@ -120,15 +140,20 @@ intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
>> }
>>
>> static inline u32
>> -intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
>> +intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t i915_reg)
>> {
>> - return xe_mmio_read32(to_gt(i915), reg.reg);
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + return xe_mmio_read32(to_gt(i915), reg);
>> }
>>
>> static inline void
>> -intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
>> +intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t i915_reg,
>> + u32 val)
>> {
>> - xe_mmio_write32(to_gt(i915), reg.reg, val);
>> + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>> +
>> + xe_mmio_write32(to_gt(i915), reg, val);
>> }
>>
>> static inline int
>> --
>> 2.40.1
>>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 5/7] fixup! drm/xe/display: Implement display support
2023-05-05 19:29 ` Lucas De Marchi
@ 2023-05-05 19:47 ` Rodrigo Vivi
0 siblings, 0 replies; 27+ messages in thread
From: Rodrigo Vivi @ 2023-05-05 19:47 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Fri, May 05, 2023 at 12:29:42PM -0700, Lucas De Marchi wrote:
> On Fri, May 05, 2023 at 12:59:32PM -0400, Rodrigo Vivi wrote:
> > On Fri, Apr 28, 2023 at 11:23:30PM -0700, Lucas De Marchi wrote:
> > > With the move of display above xe_reg conversion in xe_mmio,
> > > it should use the new types everywhere.
> > >
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >
> > and this is the one that will likely conflict with the series from Jani
> > right?
> >
> > I will try to merge his series today, then on your rebase you change
> > both this and the previous at once.
>
> not sure I understand. Aren't we going to move display up anymore?
oh! indeed... I had promised to take a look this week on that...
where did the week go?! :)
>
> If I squash this patch on the previous one, it will create a conflict
> when we move display up again, so I'd rather keep this separate as a
> fixup commit to be squashed in the initial display commit.
ack
>
> Lucas De Marchi
>
> >
> > anyway, on the approach:
> >
> > Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> >
> > > ---
> > > drivers/gpu/drm/xe/display/xe_de.h | 89 +++++++++++++++++++-----------
> > > 1 file changed, 57 insertions(+), 32 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/display/xe_de.h b/drivers/gpu/drm/xe/display/xe_de.h
> > > index 0c76b0d24d96..e6021f6d031d 100644
> > > --- a/drivers/gpu/drm/xe/display/xe_de.h
> > > +++ b/drivers/gpu/drm/xe/display/xe_de.h
> > > @@ -14,79 +14,95 @@
> > > #include "i915_reg.h"
> > >
> > > static inline u32
> > > -intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
> > > +intel_de_read(struct drm_i915_private *i915, i915_reg_t i915_reg)
> > > {
> > > - return xe_mmio_read32(to_gt(i915), reg.reg);
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + return xe_mmio_read32(to_gt(i915), reg);
> > > }
> > >
> > > static inline u64
> > > intel_de_read64_2x32(struct drm_i915_private *i915,
> > > - i915_reg_t lower_reg, i915_reg_t upper_reg)
> > > + i915_reg_t i915_lower_reg, i915_reg_t i915_upper_reg)
> > > {
> > > + struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));
> > > + struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));
> > > u32 upper, lower;
> > >
> > > - lower = xe_mmio_read32(to_gt(i915), lower_reg.reg);
> > > - upper = xe_mmio_read32(to_gt(i915), upper_reg.reg);
> > > + lower = xe_mmio_read32(to_gt(i915), lower_reg);
> > > + upper = xe_mmio_read32(to_gt(i915), upper_reg);
> > > return (u64)upper << 32 | lower;
> > > }
> > >
> > > static inline void
> > > -intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
> > > +intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t i915_reg)
> > > {
> > > - xe_mmio_read32(to_gt(i915), reg.reg);
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + xe_mmio_read32(to_gt(i915), reg);
> > > }
> > >
> > > static inline void
> > > -intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
> > > +intel_de_write(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 val)
> > > {
> > > - xe_mmio_write32(to_gt(i915), reg.reg, val);
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + xe_mmio_write32(to_gt(i915), reg, val);
> > > }
> > >
> > > static inline u32
> > > -intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
> > > +intel_de_rmw(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 clear, u32 set)
> > > {
> > > - return xe_mmio_rmw32(to_gt(i915), reg.reg, clear, set);
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + return xe_mmio_rmw32(to_gt(i915), reg, clear, set);
> > > }
> > >
> > > static inline int
> > > -intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
> > > +intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t i915_reg,
> > > u32 mask, u32 value, unsigned int timeout)
> > > {
> > > - return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
> > > - false);
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + return xe_mmio_wait32(to_gt(i915), reg, value, mask,
> > > + timeout * USEC_PER_MSEC, NULL, false);
> > > }
> > >
> > > static inline int
> > > -intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
> > > +intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t i915_reg,
> > > u32 mask, u32 value, unsigned int timeout)
> > > {
> > > - return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
> > > - false);
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + return xe_mmio_wait32(to_gt(i915), reg, value, mask,
> > > + timeout * USEC_PER_MSEC, NULL, false);
> > > }
> > >
> > > static inline int
> > > -__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
> > > +__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t i915_reg,
> > > u32 mask, u32 value,
> > > unsigned int fast_timeout_us,
> > > unsigned int slow_timeout_ms, u32 *out_value)
> > > {
> > > - return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask,
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + return xe_mmio_wait32(to_gt(i915), reg, value, mask,
> > > fast_timeout_us + 1000 * slow_timeout_ms,
> > > out_value, false);
> > > }
> > >
> > > static inline int
> > > -intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
> > > +intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t i915_reg,
> > > u32 mask, unsigned int timeout)
> > > {
> > > - return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
> > > + return intel_de_wait_for_register(i915, i915_reg, mask, mask, timeout);
> > > }
> > >
> > > static inline int
> > > -intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
> > > +intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t i915_reg,
> > > u32 mask, unsigned int timeout)
> > > {
> > > - return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
> > > + return intel_de_wait_for_register(i915, i915_reg, mask, 0, timeout);
> > > }
> > >
> > > /*
> > > @@ -98,19 +114,23 @@ intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
> > > * a more localised lock guarding all access to that bank of registers.
> > > */
> > > static inline u32
> > > -intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
> > > +intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t i915_reg)
> > > {
> > > - return xe_mmio_read32(to_gt(i915), reg.reg);
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + return xe_mmio_read32(to_gt(i915), reg);
> > > }
> > >
> > > static inline void
> > > -intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
> > > +intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 val)
> > > {
> > > - xe_mmio_write32(to_gt(i915), reg.reg, val);
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + xe_mmio_write32(to_gt(i915), reg, val);
> > > }
> > >
> > > static inline void
> > > -intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
> > > +intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t i915_reg)
> > > {
> > > /*
> > > * Not implemented, requires lock on all reads/writes.
> > > @@ -120,15 +140,20 @@ intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
> > > }
> > >
> > > static inline u32
> > > -intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
> > > +intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t i915_reg)
> > > {
> > > - return xe_mmio_read32(to_gt(i915), reg.reg);
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + return xe_mmio_read32(to_gt(i915), reg);
> > > }
> > >
> > > static inline void
> > > -intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
> > > +intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t i915_reg,
> > > + u32 val)
> > > {
> > > - xe_mmio_write32(to_gt(i915), reg.reg, val);
> > > + struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> > > +
> > > + xe_mmio_write32(to_gt(i915), reg, val);
> > > }
> > >
> > > static inline int
> > > --
> > > 2.40.1
> > >
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-xe] [PATCH 3/7] drm/xe: Use media base for GMD_ID access
2023-05-05 17:05 ` Rodrigo Vivi
@ 2023-05-05 20:19 ` Lucas De Marchi
0 siblings, 0 replies; 27+ messages in thread
From: Lucas De Marchi @ 2023-05-05 20:19 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe
On Fri, May 05, 2023 at 01:05:18PM -0400, Rodrigo Vivi wrote:
>On Mon, May 01, 2023 at 08:07:28AM -0700, Lucas De Marchi wrote:
>> On Sun, Apr 30, 2023 at 07:47:38PM +0200, Michal Wajdeczko wrote:
>> >
>> >
>> > On 29.04.2023 08:23, Lucas De Marchi wrote:
>> > > Instead of adding a hardcoded base, define GMD_ID() with a base
>> > > argument and use it in all places.
>> > >
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +++-
>> > > drivers/gpu/drm/xe/xe_pci.c | 9 +++++----
>> > > 2 files changed, 8 insertions(+), 5 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > > index 4d87f1fe010d..da7b6d2c7e01 100644
>> > > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > > @@ -8,6 +8,8 @@
>> > >
>> > > #include "regs/xe_reg_defs.h"
>> > >
>> > > +#define MTL_MEDIA_GT_BASE 0x380000
>> >
>> > maybe for completeness (and to avoid using anonymous 0 offset in other
>> > places) we should define also:
>> >
>> > #define GRAPHICS_GT_BASE 0x0
>>
>> there are very vew places in the driver that would care about the base.
>> Today the base is automatically applied for anything using xe_mmio_,
>> just like we have it automatically applied in intel_uncore for i915.
>> So, we really don't want to change each register to receive base as
>> param.
>
>I'm with Michal here. I had the same thought when reviewing and just read
>his comment afterwards. Although it is rarely used it would be good
>to avoid later confusion.
rather than changing this to bring the final XE_REG define to the
header, I think I will just leave it as is and drop this patch.
Just rebased the series and end result looks ok
Lucas De Marchi
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2023-05-05 20:19 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-29 6:23 [Intel-xe] [PATCH 0/7] Convert xe_mmio to struct xe_reg Lucas De Marchi
2023-04-29 6:23 ` [Intel-xe] [PATCH 1/7] fixup! drm/xe: Drop gen afixes from registers Lucas De Marchi
2023-05-05 16:55 ` Rodrigo Vivi
2023-04-29 6:23 ` [Intel-xe] [PATCH 2/7] drm/xe/guc: Handle RCU_MODE as masked from definition Lucas De Marchi
2023-05-05 16:55 ` Rodrigo Vivi
2023-05-05 17:08 ` Lucas De Marchi
2023-05-05 18:17 ` Rodrigo Vivi
2023-04-29 6:23 ` [Intel-xe] [PATCH 3/7] drm/xe: Use media base for GMD_ID access Lucas De Marchi
2023-04-30 17:47 ` Michal Wajdeczko
2023-05-01 15:07 ` Lucas De Marchi
2023-05-05 17:05 ` Rodrigo Vivi
2023-05-05 20:19 ` Lucas De Marchi
2023-04-29 6:23 ` [Intel-xe] [PATCH 4/7] drm/xe/mmio: Use struct xe_reg Lucas De Marchi
2023-05-05 16:57 ` Rodrigo Vivi
2023-05-05 19:26 ` Lucas De Marchi
2023-04-29 6:23 ` [Intel-xe] [PATCH 5/7] fixup! drm/xe/display: Implement display support Lucas De Marchi
2023-05-05 16:59 ` Rodrigo Vivi
2023-05-05 19:29 ` Lucas De Marchi
2023-05-05 19:47 ` Rodrigo Vivi
2023-04-29 6:23 ` [Intel-xe] [PATCH 6/7] drm/xe: Rename reg field to addr Lucas De Marchi
2023-05-05 17:00 ` Rodrigo Vivi
2023-04-29 6:23 ` [Intel-xe] [PATCH 7/7] drm/xe: Fix indent in xe_hw_engine_print_state() Lucas De Marchi
2023-05-05 17:01 ` Rodrigo Vivi
2023-04-29 6:27 ` [Intel-xe] ✓ CI.Patch_applied: success for Convert xe_mmio to struct xe_reg Patchwork
2023-04-29 6:28 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
2023-04-29 6:32 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-04-29 6:58 ` [Intel-xe] ○ CI.BAT: info " Patchwork
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