From: Jing Zhang <jingzhangos@google.com> To: KVM <kvm@vger.kernel.org>, KVMARM <kvmarm@lists.linux.dev>, ARMLinux <linux-arm-kernel@lists.infradead.org>, Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@google.com> Cc: Will Deacon <will@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>, James Morse <james.morse@arm.com>, Alexandru Elisei <alexandru.elisei@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Fuad Tabba <tabba@google.com>, Reiji Watanabe <reijiw@google.com>, Raghavendra Rao Ananta <rananta@google.com>, Jing Zhang <jingzhangos@google.com> Subject: [PATCH v8 0/6] Support writable CPU ID registers from userspace Date: Wed, 3 May 2023 17:16:12 +0000 [thread overview] Message-ID: <20230503171618.2020461-1-jingzhangos@google.com> (raw) This patchset refactors/adds code to support writable per guest CPU ID feature registers. Part of the code/ideas are from https://lore.kernel.org/all/20220419065544.3616948-1-reijiw@google.com . No functional change is intended in this patchset. With the new CPU ID feature registers infrastructure, only writtings of ID_AA64PFR0_EL1.[CSV2|CSV3], ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon are allowed as KVM does before. Writable (Configurable) per guest CPU ID feature registers are useful for creating/migrating guest on ARM CPUs with different kinds of features. This patchset uses kvm->arch.config_lock from Oliver's lock inversion fixes at https://lore.kernel.org/linux-arm-kernel/20230327164747.2466958-1-oliver.upton@linux.dev/ --- * v7 -> v8 - Move idregs table sanity check to kvm_sys_reg_table_init. - Only allow userspace writing before VM running. - No lock is hold for guest access to idregs. - Addressed some other comments from Reiji and Oliver. * v6 -> v7 - Rebased to v6.3-rc7. - Add helpers for idregs read/write. - Guard all idregs reads/writes. - Add code to fix features' safe value type which is different for KVM than for the host. * v5 -> v6 - Rebased to v6.3-rc5. - Reuse struct sys_reg_desc's reset() callback and field val for KVM. sanitisation function and writable mask instead of creating a new data structure for idregs. - Use get_arm64_ftr_reg() instead of exposing idregs ftr_bits array. * v4 -> v5 - Rebased to 2fad20ae05cb (kvmarm/next) Merge branch kvm-arm64/selftest/misc-6,4 into kvmarm-master/next - Use kvm->arch.config_lock to guard update to multiple VM scope idregs to avoid lock inversion - Add back IDREG() macro for idregs access - Refactor struct id_reg_desc by using existing infrastructure. - Addressed many other comments from Marc. * v3 -> v4 - Remove IDREG() macro for ID reg access, use simple array access instead - Rename kvm_arm_read_id_reg_with_encoding() to kvm_arm_read_id_reg() - Save perfmon value in ID_DFR0_EL1 instead of pmuver - Update perfmon in ID_DFR0_EL1 and pmuver in ID_AA64DFR0_EL1 atomically - Remove kvm_vcpu_has_pmu() in macro kvm_pmu_is_3p5() - Improve ID register sanity checking in kvm_arm_check_idreg_table() * v2 -> v3 - Rebased to 96a4627dbbd4 (kvmarm/next) Merge tag ' https://github.com/oupton/linux tags/kvmarm-6.3' from into kvmarm-master/next - Add id registere emulation entry point function emulate_id_reg - Fix consistency for ID_AA64DFR0_EL1.PMUVer and ID_DFR0_EL1.PerfMon - Improve the checking for id register table by ensuring that every entry has the correct id register encoding. - Addressed other comments from Reiji and Marc. * v1 -> v2 - Rebase to 7121a2e1d107 (kvmarm/next) Merge branch kvm-arm64/nv-prefix into kvmarm/next - Address writing issue for PMUVer [1] https://lore.kernel.org/all/20230201025048.205820-1-jingzhangos@google.com [2] https://lore.kernel.org/all/20230212215830.2975485-1-jingzhangos@google.com [3] https://lore.kernel.org/all/20230228062246.1222387-1-jingzhangos@google.com [4] https://lore.kernel.org/all/20230317050637.766317-1-jingzhangos@google.com [5] https://lore.kernel.org/all/20230402183735.3011540-1-jingzhangos@google.com [6] https://lore.kernel.org/all/20230404035344.4043856-1-jingzhangos@google.com [7] https://lore.kernel.org/all/20230424234704.2571444-1-jingzhangos@google.com --- Jing Zhang (6): KVM: arm64: Move CPU ID feature registers emulation into a separate file KVM: arm64: Save ID registers' sanitized value per guest KVM: arm64: Use per guest ID register for ID_AA64PFR0_EL1.[CSV2|CSV3] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer KVM: arm64: Reuse fields of sys_reg_desc for idreg KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 arch/arm64/include/asm/cpufeature.h | 1 + arch/arm64/include/asm/kvm_host.h | 33 +- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/arm.c | 24 +- arch/arm64/kvm/id_regs.c | 717 ++++++++++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 534 ++++----------------- arch/arm64/kvm/sys_regs.h | 28 +- include/kvm/arm_pmu.h | 5 +- 9 files changed, 864 insertions(+), 482 deletions(-) create mode 100644 arch/arm64/kvm/id_regs.c base-commit: 6a8f57ae2eb07ab39a6f0ccad60c760743051026 -- 2.40.1.495.gc816e09b53d-goog
WARNING: multiple messages have this Message-ID (diff)
From: Jing Zhang <jingzhangos@google.com> To: KVM <kvm@vger.kernel.org>, KVMARM <kvmarm@lists.linux.dev>, ARMLinux <linux-arm-kernel@lists.infradead.org>, Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@google.com> Cc: Will Deacon <will@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>, James Morse <james.morse@arm.com>, Alexandru Elisei <alexandru.elisei@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Fuad Tabba <tabba@google.com>, Reiji Watanabe <reijiw@google.com>, Raghavendra Rao Ananta <rananta@google.com>, Jing Zhang <jingzhangos@google.com> Subject: [PATCH v8 0/6] Support writable CPU ID registers from userspace Date: Wed, 3 May 2023 17:16:12 +0000 [thread overview] Message-ID: <20230503171618.2020461-1-jingzhangos@google.com> (raw) This patchset refactors/adds code to support writable per guest CPU ID feature registers. Part of the code/ideas are from https://lore.kernel.org/all/20220419065544.3616948-1-reijiw@google.com . No functional change is intended in this patchset. With the new CPU ID feature registers infrastructure, only writtings of ID_AA64PFR0_EL1.[CSV2|CSV3], ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon are allowed as KVM does before. Writable (Configurable) per guest CPU ID feature registers are useful for creating/migrating guest on ARM CPUs with different kinds of features. This patchset uses kvm->arch.config_lock from Oliver's lock inversion fixes at https://lore.kernel.org/linux-arm-kernel/20230327164747.2466958-1-oliver.upton@linux.dev/ --- * v7 -> v8 - Move idregs table sanity check to kvm_sys_reg_table_init. - Only allow userspace writing before VM running. - No lock is hold for guest access to idregs. - Addressed some other comments from Reiji and Oliver. * v6 -> v7 - Rebased to v6.3-rc7. - Add helpers for idregs read/write. - Guard all idregs reads/writes. - Add code to fix features' safe value type which is different for KVM than for the host. * v5 -> v6 - Rebased to v6.3-rc5. - Reuse struct sys_reg_desc's reset() callback and field val for KVM. sanitisation function and writable mask instead of creating a new data structure for idregs. - Use get_arm64_ftr_reg() instead of exposing idregs ftr_bits array. * v4 -> v5 - Rebased to 2fad20ae05cb (kvmarm/next) Merge branch kvm-arm64/selftest/misc-6,4 into kvmarm-master/next - Use kvm->arch.config_lock to guard update to multiple VM scope idregs to avoid lock inversion - Add back IDREG() macro for idregs access - Refactor struct id_reg_desc by using existing infrastructure. - Addressed many other comments from Marc. * v3 -> v4 - Remove IDREG() macro for ID reg access, use simple array access instead - Rename kvm_arm_read_id_reg_with_encoding() to kvm_arm_read_id_reg() - Save perfmon value in ID_DFR0_EL1 instead of pmuver - Update perfmon in ID_DFR0_EL1 and pmuver in ID_AA64DFR0_EL1 atomically - Remove kvm_vcpu_has_pmu() in macro kvm_pmu_is_3p5() - Improve ID register sanity checking in kvm_arm_check_idreg_table() * v2 -> v3 - Rebased to 96a4627dbbd4 (kvmarm/next) Merge tag ' https://github.com/oupton/linux tags/kvmarm-6.3' from into kvmarm-master/next - Add id registere emulation entry point function emulate_id_reg - Fix consistency for ID_AA64DFR0_EL1.PMUVer and ID_DFR0_EL1.PerfMon - Improve the checking for id register table by ensuring that every entry has the correct id register encoding. - Addressed other comments from Reiji and Marc. * v1 -> v2 - Rebase to 7121a2e1d107 (kvmarm/next) Merge branch kvm-arm64/nv-prefix into kvmarm/next - Address writing issue for PMUVer [1] https://lore.kernel.org/all/20230201025048.205820-1-jingzhangos@google.com [2] https://lore.kernel.org/all/20230212215830.2975485-1-jingzhangos@google.com [3] https://lore.kernel.org/all/20230228062246.1222387-1-jingzhangos@google.com [4] https://lore.kernel.org/all/20230317050637.766317-1-jingzhangos@google.com [5] https://lore.kernel.org/all/20230402183735.3011540-1-jingzhangos@google.com [6] https://lore.kernel.org/all/20230404035344.4043856-1-jingzhangos@google.com [7] https://lore.kernel.org/all/20230424234704.2571444-1-jingzhangos@google.com --- Jing Zhang (6): KVM: arm64: Move CPU ID feature registers emulation into a separate file KVM: arm64: Save ID registers' sanitized value per guest KVM: arm64: Use per guest ID register for ID_AA64PFR0_EL1.[CSV2|CSV3] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer KVM: arm64: Reuse fields of sys_reg_desc for idreg KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 arch/arm64/include/asm/cpufeature.h | 1 + arch/arm64/include/asm/kvm_host.h | 33 +- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/arm.c | 24 +- arch/arm64/kvm/id_regs.c | 717 ++++++++++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 534 ++++----------------- arch/arm64/kvm/sys_regs.h | 28 +- include/kvm/arm_pmu.h | 5 +- 9 files changed, 864 insertions(+), 482 deletions(-) create mode 100644 arch/arm64/kvm/id_regs.c base-commit: 6a8f57ae2eb07ab39a6f0ccad60c760743051026 -- 2.40.1.495.gc816e09b53d-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2023-05-03 17:16 UTC|newest] Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-03 17:16 Jing Zhang [this message] 2023-05-03 17:16 ` [PATCH v8 0/6] Support writable CPU ID registers from userspace Jing Zhang 2023-05-03 17:16 ` [PATCH v8 1/6] KVM: arm64: Move CPU ID feature registers emulation into a separate file Jing Zhang 2023-05-03 17:16 ` Jing Zhang 2023-05-16 16:11 ` Marc Zyngier 2023-05-16 16:11 ` Marc Zyngier 2023-05-16 19:14 ` Jing Zhang 2023-05-16 19:14 ` Jing Zhang 2023-05-03 17:16 ` [PATCH v8 2/6] KVM: arm64: Save ID registers' sanitized value per guest Jing Zhang 2023-05-03 17:16 ` Jing Zhang 2023-05-17 7:41 ` Marc Zyngier 2023-05-17 7:41 ` Marc Zyngier 2023-05-17 16:28 ` Jing Zhang 2023-05-17 16:28 ` Jing Zhang 2023-05-03 17:16 ` [PATCH v8 3/6] KVM: arm64: Use per guest ID register for ID_AA64PFR0_EL1.[CSV2|CSV3] Jing Zhang 2023-05-03 17:16 ` Jing Zhang 2023-05-03 23:43 ` kernel test robot 2023-05-03 23:43 ` kernel test robot 2023-05-03 17:16 ` [PATCH v8 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer Jing Zhang 2023-05-03 17:16 ` Jing Zhang 2023-05-03 17:16 ` [PATCH v8 5/6] KVM: arm64: Reuse fields of sys_reg_desc for idreg Jing Zhang 2023-05-03 17:16 ` Jing Zhang 2023-05-16 10:26 ` Cornelia Huck 2023-05-16 10:26 ` Cornelia Huck 2023-05-16 19:10 ` Jing Zhang 2023-05-16 19:10 ` Jing Zhang 2023-05-03 17:16 ` [PATCH v8 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 Jing Zhang 2023-05-03 17:16 ` Jing Zhang 2023-05-17 22:00 ` Jitindar Singh, Suraj 2023-05-17 22:00 ` Jitindar Singh, Suraj 2023-05-17 22:55 ` Jing Zhang 2023-05-17 22:55 ` Jing Zhang 2023-05-18 21:08 ` Jitindar Singh, Suraj 2023-05-18 21:08 ` Jitindar Singh, Suraj 2023-05-19 9:16 ` Marc Zyngier 2023-05-19 9:16 ` Marc Zyngier 2023-05-19 23:04 ` Jitindar Singh, Suraj 2023-05-19 23:04 ` Jitindar Singh, Suraj 2023-05-20 8:45 ` Marc Zyngier 2023-05-20 8:45 ` Marc Zyngier 2023-05-19 23:25 ` Suraj Jitindar Singh 2023-05-19 23:25 ` Suraj Jitindar Singh 2023-05-16 10:37 ` [PATCH v8 0/6] Support writable CPU ID registers from userspace Shameerali Kolothum Thodi 2023-05-16 10:37 ` Shameerali Kolothum Thodi 2023-05-16 11:01 ` Marc Zyngier 2023-05-16 11:01 ` Marc Zyngier 2023-05-16 11:11 ` Shameerali Kolothum Thodi 2023-05-16 11:11 ` Shameerali Kolothum Thodi 2023-05-16 11:55 ` Cornelia Huck 2023-05-16 11:55 ` Cornelia Huck 2023-05-16 13:11 ` Marc Zyngier 2023-05-16 13:11 ` Marc Zyngier 2023-05-16 13:44 ` Shameerali Kolothum Thodi 2023-05-16 13:44 ` Shameerali Kolothum Thodi 2023-05-16 14:21 ` Cornelia Huck 2023-05-16 14:21 ` Cornelia Huck 2023-05-16 14:19 ` Cornelia Huck 2023-05-16 14:19 ` Cornelia Huck 2023-05-16 16:01 ` Marc Zyngier 2023-05-16 16:01 ` Marc Zyngier 2023-05-17 15:36 ` Cornelia Huck 2023-05-17 15:36 ` Cornelia Huck 2023-05-17 15:53 ` Marc Zyngier 2023-05-17 15:53 ` Marc Zyngier 2023-05-16 16:31 ` Oliver Upton 2023-05-16 16:31 ` Oliver Upton 2023-05-16 16:44 ` Marc Zyngier 2023-05-16 16:44 ` Marc Zyngier 2023-05-16 16:57 ` Oliver Upton 2023-05-16 16:57 ` Oliver Upton
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