[djiang:cxl-qtg 21/28] drivers/cxl/core/port.c:1954:6: warning: no previous prototype for 'combine_coordinates'

[djiang:cxl-qtg 21/28] drivers/cxl/core/port.c:1954:6: warning: no previous prototype for 'combine_coordinates'

[kernel test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git cxl-qtg
head:   c09d294a320a41a687ff2881bc080bf7d9ee5ce2
commit: 46b815fc52e80858ee81a840739850c6bd9bc78d [21/28] cxl: Add helper function that calculate performance data for downstream ports
config: ia64-allyesconfig (https://download.01.org/0day-ci/archive/20230505/202305050735.96PeJzZO-lkp@intel.com/config)
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git/commit/?id=46b815fc52e80858ee81a840739850c6bd9bc78d
        git remote add djiang https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git
        git fetch --no-tags djiang cxl-qtg
        git checkout 46b815fc52e80858ee81a840739850c6bd9bc78d
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/cxl/core/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305050735.96PeJzZO-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/cxl/core/port.c:1954:6: warning: no previous prototype for 'combine_coordinates' [-Wmissing-prototypes]
    1954 | void combine_coordinates(struct access_coordinate *c1, struct access_coordinate *c2)
         |      ^~~~~~~~~~~~~~~~~~~
--
>> drivers/cxl/core/port.c:1979: warning: expecting prototype for cxl_port_get_perf_coordinates(). Prototype was for cxl_endpoint_get_perf_coordinates() instead


vim +/combine_coordinates +1954 drivers/cxl/core/port.c

  1953	
> 1954	void combine_coordinates(struct access_coordinate *c1, struct access_coordinate *c2)
  1955	{
  1956			if (c2->write_bandwidth)
  1957				c1->write_bandwidth = min_t(unsigned int,
  1958							    c1->write_bandwidth,
  1959							    c2->write_bandwidth);
  1960			c1->write_latency += c2->write_latency;
  1961	
  1962			if (c2->read_bandwidth)
  1963				c1->read_bandwidth = min_t(unsigned int,
  1964							   c1->read_bandwidth,
  1965							   c2->read_bandwidth);
  1966			c1->read_latency += c2->read_latency;
  1967	}
  1968	
  1969	/**
  1970	 * cxl_port_get_perf_coordinates - Retrieve performance numbers stored in dports
  1971	 *				   of CXL path
  1972	 * @port: endpoint cxl_port
  1973	 * @coord: output performance data
  1974	 *
  1975	 * Return: errno on failure, 0 on success.
  1976	 */
  1977	int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
  1978					      struct access_coordinate *coord)
> 1979	{
  1980		struct access_coordinate c = {
  1981			.read_bandwidth = UINT_MAX,
  1982			.write_bandwidth = UINT_MAX,
  1983		};
  1984		struct cxl_port *iter = port;
  1985		struct cxl_dport *dport;
  1986		struct pci_dev *pdev;
  1987		unsigned int bw;
  1988	
  1989		if (!is_cxl_endpoint(port))
  1990			return -EINVAL;
  1991	
  1992		dport = iter->parent_dport;
  1993		while (iter && !is_cxl_root(iter)) {
  1994			combine_coordinates(&c, &dport->coord);
  1995			c.write_latency += dport->link_latency;
  1996			c.read_latency += dport->link_latency;
  1997	
  1998			if (dport->genport_coord)
  1999				combine_coordinates(&c, dport->genport_coord);
  2000	
  2001			iter = to_cxl_port(iter->dev.parent);
  2002			dport = iter->parent_dport;
  2003		}
  2004	
  2005		/* Get the calculated PCI paths bandwidth */
  2006		pdev = to_pci_dev(port->uport->parent);
  2007		bw = pcie_bandwidth_available(pdev, NULL, NULL, NULL);
  2008		if (bw == 0)
  2009			return -ENXIO;
  2010		bw /= BITS_PER_BYTE;
  2011	
  2012		c.write_bandwidth = min_t(unsigned int, c.write_bandwidth, bw);
  2013		c.read_bandwidth = min_t(unsigned int, c.read_bandwidth, bw);
  2014	
  2015		*coord = c;
  2016	
  2017		return 0;
  2018	}
  2019	EXPORT_SYMBOL_NS_GPL(cxl_endpoint_get_perf_coordinates, CXL);
  2020	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests