[Intel-gfx] [PATCH 0/2] C20 Computed HDMI TMDS pixel clocks

[Intel-gfx] [PATCH 0/2] C20 Computed HDMI TMDS pixel clocks

[Clint Taylor]

Use computed C20 HDMI TMDS pixel clocks to support 25.175MHz to
594000MHz modes. Add 16 Bit mask operators to support C20 phy
programming.

BSPEC: 64568
Cc: Imre Deak <imre.deak@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>  

Clint Taylor (2):
  drm/i915: Add 16bit register/mask operators
  drm/i915/hdmi: C20 computed PLL frequencies

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 89 +++++++++++++++++--
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 53 +++++++++++
 drivers/gpu/drm/i915/i915_reg_defs.h          | 49 ++++++++++
 3 files changed, 185 insertions(+), 6 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH 1/2] drm/i915: Add 16bit register/mask operators

[Clint Taylor]

Add the support macros to define/extract bits as 16bits.

Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
 drivers/gpu/drm/i915/i915_reg_defs.h | 49 ++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index 622d603080f9..eb273f3ce3eb 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -143,6 +143,55 @@
  */
 #define REG_FIELD_GET64(__mask, __val)	((u64)FIELD_GET(__mask, __val))
 
+/**
+ * REG_BIT16() - Prepare a u16 bit value
+ * @__n: 0-based bit number
+ *
+ * Local wrapper for BIT() to force u16, with compile time
+ * checks.
+ *
+ * @return: Value with bit @__n set.
+ */
+#define REG_BIT16(__n)                                                   \
+	((u16)(BIT(__n) +                                                \
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&         \
+				 ((__n) < 0 || (__n) > 15))))
+
+/**
+ * REG_GENMASK16() - Prepare a continuous u8 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u16, with compile time
+ * checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK16(__high, __low)                                     \
+	((u16)(GENMASK(__high, __low) +                                  \
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&      \
+				 __is_constexpr(__low) &&               \
+				 ((__low) < 0 || (__high) > 15 || (__low) > (__high)))))
+
+/**
+ * REG_FIELD_PREP16() - Prepare a u16 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to put in the field
+ *
+ * Local copy of FIELD_PREP16() to generate an integer constant
+ * expression, force u8 and for consistency with
+ * REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16().
+ *
+ * @return: @__val masked and shifted into the field defined by @__mask.
+ */
+#define REG_FIELD_PREP16(__mask, __val)                                          \
+	((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +      \
+	       BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +             \
+	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) +          \
+	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+
+
 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
 #define _MASKED_FIELD(mask, value) ({					   \
 	if (__builtin_constant_p(mask))					   \
-- 
2.25.1

[Intel-gfx] [PATCH 2/2] drm/i915/hdmi: C20 computed PLL frequencies

[Clint Taylor]

Use algorithm to generate HDMI C20 PLL clock frequencies.

BSPEC: 64568
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 89 +++++++++++++++++--
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 53 +++++++++++
 2 files changed, 136 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index d94127e7448b..fb5599ffca81 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3,6 +3,8 @@
  * Copyright © 2023 Intel Corporation
  */
 
+#include <linux/log2.h>
+#include <linux/math64.h>
 #include "i915_reg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
@@ -1901,6 +1903,74 @@ void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
 			    i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
 }
 
+static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state)
+{
+	u64 datarate;
+	u64 mpll_tx_clk_div;
+	u64 vco_freq_shift;
+	u64 vco_freq;
+	u64 multiplier;
+	u64 mpll_multiplier;
+	u64 mpll_fracn_quot;
+	u64 mpll_fracn_rem;
+	u8  mpllb_ana_freq_vco;
+	u8  mpll_div_multiplier;
+
+	if (pixel_clock < 25175 || pixel_clock > 600000)
+		return -EINVAL;
+
+	datarate = ((u64)pixel_clock * 1000) * 10;
+	mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, (u64)datarate));
+	vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, (u64)datarate));
+	vco_freq = (datarate << vco_freq_shift) >> 8;
+	multiplier = div64_u64((vco_freq << 28), (REFCLK_38_4_MHZ >> 4));
+	mpll_multiplier = 2 * (multiplier >> 32);
+
+	mpll_fracn_quot = (multiplier >> 16) & 0xFFFF;
+	mpll_fracn_rem  = multiplier & 0xFFFF;
+
+	mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)), datarate), 255);
+
+	if (vco_freq <= DATARATE_3000000000)
+		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_3;
+	else if (vco_freq <= DATARATE_3500000000)
+		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_2;
+	else if (vco_freq <= DATARATE_4000000000)
+		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_1;
+	else
+		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
+
+	pll_state->link_bit_rate	= pixel_clock;
+	pll_state->clock	= pixel_clock;
+	pll_state->tx[0]	= 0xbe88;
+	pll_state->tx[1]	= 0x9800;
+	pll_state->tx[2]	= 0x0000;
+	pll_state->cmn[0]	= 0x0500;
+	pll_state->cmn[1]	= 0x0005;
+	pll_state->cmn[2]	= 0x0000;
+	pll_state->cmn[3]	= 0x0000;
+	pll_state->mpllb[0]	= (MPLL_TX_CLK_DIV(mpll_tx_clk_div) |
+				   MPLL_MULTIPLIER(mpll_multiplier));
+	pll_state->mpllb[1]	= (CAL_DAC_CODE(CAL_DAC_CODE_31) |
+				   WORD_CLK_DIV |
+				   MPLL_DIV_MULTIPLIER(mpll_div_multiplier));
+	pll_state->mpllb[2]	= (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) |
+				   CP_PROP(CP_PROP_20) |
+				   CP_INT(CP_INT_6));
+	pll_state->mpllb[3]	= (V2I(V2I_2) |
+				   CP_PROP_GS(CP_PROP_GS_30) |
+				   CP_INT_GS(CP_INT_GS_28));
+	pll_state->mpllb[4]	= 0x0000;
+	pll_state->mpllb[5]	= 0x0000;
+	pll_state->mpllb[6]	= (C20_MPLLB_FRACEN | SSC_UP_SPREAD);
+	pll_state->mpllb[7]	= MPLL_FRACN_DEN;
+	pll_state->mpllb[8]	= mpll_fracn_quot;
+	pll_state->mpllb[9]	= mpll_fracn_rem;
+	pll_state->mpllb[10]	= HDMI_DIV(HDMI_DIV_1);
+
+	return 0;
+}
+
 static int intel_c20_phy_check_hdmi_link_rate(int clock)
 {
 	const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
@@ -1911,6 +1981,9 @@ static int intel_c20_phy_check_hdmi_link_rate(int clock)
 			return MODE_OK;
 	}
 
+	if (clock >= 25175 && clock <= 594000)
+		return MODE_OK;
+
 	return MODE_CLOCK_RANGE;
 }
 
@@ -1944,6 +2017,13 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 	const struct intel_c20pll_state * const *tables;
 	int i;
 
+	/* try computed C20 HDMI tables before using consolidated tables */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+		if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock,
+						    &crtc_state->cx0pll_state.c20) == 0)
+			return 0;
+	}
+
 	tables = intel_c20_pll_tables_get(crtc_state, encoder);
 	if (!tables)
 		return -EINVAL;
@@ -2093,13 +2173,10 @@ static u8 intel_c20_get_dp_rate(u32 clock)
 
 static u8 intel_c20_get_hdmi_rate(u32 clock)
 {
-	switch (clock) {
-	case 25175:
-	case 27000:
-	case 74250:
-	case 148500:
-	case 594000:
+	if ((clock >= 25175) && (clock <= 600000))
 		return 0;
+
+	switch (clock) {
 	case 166670: /* 3 Gbps */
 	case 333330: /* 6 Gbps */
 	case 666670: /* 12 Gbps */
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index ab9d1d983b88..cb5d1be2ba19 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -218,4 +218,57 @@
 
 #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
 
+/* C20 HDMI computed pll definitions */
+#define REFCLK_38_4_MHZ		38400000
+#define CLOCK_4999MHZ		4999999999
+#define CLOCK_9999MHZ		9999999999
+#define DATARATE_3000000000	3000000000
+#define DATARATE_3500000000	3500000000
+#define DATARATE_4000000000	4000000000
+#define MPLL_FRACN_DEN		0xFFFF
+
+#define SSC_UP_SPREAD		REG_BIT16(9)
+#define WORD_CLK_DIV		REG_BIT16(8)
+
+#define MPLL_TX_CLK_DIV(val)	REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val)
+#define MPLL_MULTIPLIER(val)	REG_FIELD_PREP16(C20_MULTIPLIER_MASK, val)
+
+#define MPLLB_ANA_FREQ_VCO_0	0
+#define MPLLB_ANA_FREQ_VCO_1	1
+#define MPLLB_ANA_FREQ_VCO_2	2
+#define MPLLB_ANA_FREQ_VCO_3	3
+#define MPLLB_ANA_FREQ_VCO_MASK	REG_GENMASK16(15, 14)
+#define MPLLB_ANA_FREQ_VCO(val)	REG_FIELD_PREP16(MPLLB_ANA_FREQ_VCO_MASK, val)
+
+#define MPLL_DIV_MULTIPLIER_MASK	REG_GENMASK16(7, 0)
+#define MPLL_DIV_MULTIPLIER(val)	REG_FIELD_PREP16(MPLL_DIV_MULTIPLIER_MASK, val)
+
+#define CAL_DAC_CODE_31		31
+#define CAL_DAC_CODE_MASK	REG_GENMASK16(14, 10)
+#define CAL_DAC_CODE(val)	REG_FIELD_PREP16(CAL_DAC_CODE_MASK, val)
+
+#define CP_INT_GS_28		28
+#define CP_INT_GS_MASK		REG_GENMASK16(6, 0)
+#define CP_INT_GS(val)		REG_FIELD_PREP16(CP_INT_GS_MASK, val)
+
+#define CP_PROP_GS_30		30
+#define CP_PROP_GS_MASK		REG_GENMASK16(13, 7)
+#define CP_PROP_GS(val)		REG_FIELD_PREP16(CP_PROP_GS_MASK, val)
+
+#define CP_INT_6		6
+#define CP_INT_MASK		REG_GENMASK16(6, 0)
+#define CP_INT(val)		REG_FIELD_PREP16(CP_INT_MASK, val)
+
+#define CP_PROP_20		20
+#define CP_PROP_MASK		REG_GENMASK16(13, 7)
+#define CP_PROP(val)		REG_FIELD_PREP16(CP_PROP_MASK, val)
+
+#define V2I_2			2
+#define V2I_MASK		REG_GENMASK16(15, 14)
+#define V2I(val)		REG_FIELD_PREP16(V2I_MASK, val)
+
+#define HDMI_DIV_1		1
+#define HDMI_DIV_MASK		REG_GENMASK16(2, 0)
+#define HDMI_DIV(val)		REG_FIELD_PREP16(HDMI_DIV_MASK, val)
+
 #endif /* __INTEL_CX0_REG_DEFS_H__ */
-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for C20 Computed HDMI TMDS pixel clocks

[Patchwork]

== Series Details ==

Series: C20 Computed HDMI TMDS pixel clocks
URL   : https://patchwork.freedesktop.org/series/117399/
State : warning

== Summary ==

Error: dim checkpatch failed
25766d718057 drm/i915: Add 16bit register/mask operators
-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__n' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:155:
+#define REG_BIT16(__n)                                                   \
+	((u16)(BIT(__n) +                                                \
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&         \
+				 ((__n) < 0 || (__n) > 15))))

-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:170:
+#define REG_GENMASK16(__high, __low)                                     \
+	((u16)(GENMASK(__high, __low) +                                  \
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&      \
+				 __is_constexpr(__low) &&               \
+				 ((__low) < 0 || (__high) > 15 || (__low) > (__high)))))

-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:170:
+#define REG_GENMASK16(__high, __low)                                     \
+	((u16)(GENMASK(__high, __low) +                                  \
+	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&      \
+				 __is_constexpr(__low) &&               \
+				 ((__low) < 0 || (__high) > 15 || (__low) > (__high)))))

-:59: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects?
#59: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:187:
+#define REG_FIELD_PREP16(__mask, __val)                                          \
+	((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +      \
+	       BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +             \
+	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) +          \
+	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))

-:59: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects?
#59: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:187:
+#define REG_FIELD_PREP16(__mask, __val)                                          \
+	((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +      \
+	       BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +             \
+	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) +          \
+	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))

-:64: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#64: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:192:
+	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))

-:66: CHECK:LINE_SPACING: Please don't use multiple blank lines
#66: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:194:
+
+

total: 0 errors, 1 warnings, 6 checks, 55 lines checked
3d5e5a7f1c8d drm/i915/hdmi: C20 computed PLL frequencies
-:58: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#58: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1932:
+	mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)), datarate), 255);

-:137: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'clock >= 25175'
#137: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2176:
+	if ((clock >= 25175) && (clock <= 600000))

-:137: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'clock <= 600000'
#137: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2176:
+	if ((clock >= 25175) && (clock <= 600000))

total: 0 errors, 1 warnings, 2 checks, 177 lines checked

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for C20 Computed HDMI TMDS pixel clocks

[Patchwork]

== Series Details ==

Series: C20 Computed HDMI TMDS pixel clocks
URL   : https://patchwork.freedesktop.org/series/117399/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for C20 Computed HDMI TMDS pixel clocks

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5013 bytes --]

== Series Details ==

Series: C20 Computed HDMI TMDS pixel clocks
URL   : https://patchwork.freedesktop.org/series/117399/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13114 -> Patchwork_117399v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/index.html

Participating hosts (40 -> 38)
------------------------------

  Missing    (2): fi-snb-2520m bat-mtlp-6 

Known issues
------------

  Here are the changes found in Patchwork_117399v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - bat-rpls-1:         NOTRUN -> [ABORT][1] ([i915#6687] / [i915#7978] / [i915#8407])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_selftest@live@migrate:
    - bat-adlp-6:         [PASS][2] -> [DMESG-FAIL][3] ([i915#7699] / [i915#7913])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/bat-adlp-6/igt@i915_selftest@live@migrate.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/bat-adlp-6/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@requests:
    - bat-rpls-2:         [PASS][4] -> [ABORT][5] ([i915#4983] / [i915#7913])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/bat-rpls-2/igt@i915_selftest@live@requests.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/bat-rpls-2/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@slpc:
    - bat-rpls-1:         NOTRUN -> [DMESG-WARN][6] ([i915#6367])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/bat-rpls-1/igt@i915_selftest@live@slpc.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - bat-adlp-6:         NOTRUN -> [SKIP][7] ([i915#7828])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/bat-adlp-6/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
    - bat-jsl-3:          NOTRUN -> [SKIP][8] ([i915#7828])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/bat-jsl-3/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@hangcheck:
    - bat-adlp-6:         [ABORT][9] ([i915#7677] / [i915#7913]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/bat-adlp-6/igt@i915_selftest@live@hangcheck.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/bat-adlp-6/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@requests:
    - bat-rpls-1:         [ABORT][11] ([i915#4983] / [i915#7911] / [i915#7920]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/bat-rpls-1/igt@i915_selftest@live@requests.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/bat-rpls-1/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@slpc:
    - {bat-mtlp-8}:       [DMESG-WARN][13] ([i915#6367]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/bat-mtlp-8/igt@i915_selftest@live@slpc.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/bat-mtlp-8/igt@i915_selftest@live@slpc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
  [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
  [i915#8379]: https://gitlab.freedesktop.org/drm/intel/issues/8379
  [i915#8407]: https://gitlab.freedesktop.org/drm/intel/issues/8407


Build changes
-------------

  * Linux: CI_DRM_13114 -> Patchwork_117399v1

  CI-20190529: 20190529
  CI_DRM_13114: b4d6f70062cd04a8fdb9872828bcbe4767a4f833 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7281: 9e9cd7e69a393b7cce8fc12fce409eb59817dd7e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_117399v1: b4d6f70062cd04a8fdb9872828bcbe4767a4f833 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

8d70ffe86f16 drm/i915/hdmi: C20 computed PLL frequencies
d6ae5e3e6695 drm/i915: Add 16bit register/mask operators

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/index.html

[-- Attachment #2: Type: text/html, Size: 6034 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for C20 Computed HDMI TMDS pixel clocks

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10822 bytes --]

== Series Details ==

Series: C20 Computed HDMI TMDS pixel clocks
URL   : https://patchwork.freedesktop.org/series/117399/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13114_full -> Patchwork_117399v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_117399v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@process:
    - shard-snb:          NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-snb4/igt@gem_ctx_persistence@process.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [PASS][2] -> [FAIL][3] ([i915#2842])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          [PASS][4] -> [ABORT][5] ([i915#5566])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-glk7/igt@gen9_exec_parse@allowed-single.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-glk1/igt@gen9_exec_parse@allowed-single.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
    - shard-snb:          NOTRUN -> [SKIP][6] ([fdo#109271]) +110 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-snb4/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html

  * igt@perf@stress-open-close@0-rcs0:
    - shard-glk:          [PASS][7] -> [ABORT][8] ([i915#5213] / [i915#7941])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-glk9/igt@perf@stress-open-close@0-rcs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-glk3/igt@perf@stress-open-close@0-rcs0.html

  
#### Possible fixes ####

  * igt@gem_barrier_race@remote-request@rcs0:
    - {shard-tglu}:       [ABORT][9] ([i915#8211] / [i915#8234]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-tglu-9/igt@gem_barrier_race@remote-request@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-tglu-8/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-tglu}:       [FAIL][11] ([i915#6268]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-tglu-10/igt@gem_ctx_exec@basic-nohangcheck.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-tglu-7/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_freq@sysfs:
    - {shard-dg1}:        [FAIL][13] ([i915#6786]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-dg1-15/igt@gem_ctx_freq@sysfs.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-dg1-14/igt@gem_ctx_freq@sysfs.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - {shard-rkl}:        [FAIL][15] ([i915#2842]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-rkl-3/igt@gem_exec_fair@basic-none@vecs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-rkl-6/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-apl:          [FAIL][17] ([i915#2842]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-apl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_suspend@basic-s4-devices@lmem0:
    - {shard-dg1}:        [ABORT][19] ([i915#7975] / [i915#8213]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-dg1-18/igt@gem_exec_suspend@basic-s4-devices@lmem0.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
    - shard-snb:          [ABORT][21] ([i915#5161]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-snb2/igt@gem_mmap_gtt@fault-concurrent-y.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-snb4/igt@gem_mmap_gtt@fault-concurrent-y.html

  * igt@i915_pm_dc@dc9-dpms:
    - {shard-tglu}:       [SKIP][23] ([i915#4281]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-tglu-6/igt@i915_pm_dc@dc9-dpms.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-tglu-10/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - {shard-rkl}:        [SKIP][25] ([i915#1397]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-rkl-4/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-snb:          [SKIP][27] ([fdo#109271]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-snb2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-snb1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_flip@flip-vs-suspend@b-vga1:
    - shard-snb:          [DMESG-WARN][29] ([i915#5090]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13114/shard-snb2/igt@kms_flip@flip-vs-suspend@b-vga1.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/shard-snb4/igt@kms_flip@flip-vs-suspend@b-vga1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#5090]: https://gitlab.freedesktop.org/drm/intel/issues/5090
  [i915#5161]: https://gitlab.freedesktop.org/drm/intel/issues/5161
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6786]: https://gitlab.freedesktop.org/drm/intel/issues/6786
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234


Build changes
-------------

  * Linux: CI_DRM_13114 -> Patchwork_117399v1

  CI-20190529: 20190529
  CI_DRM_13114: b4d6f70062cd04a8fdb9872828bcbe4767a4f833 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7281: 9e9cd7e69a393b7cce8fc12fce409eb59817dd7e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_117399v1: b4d6f70062cd04a8fdb9872828bcbe4767a4f833 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117399v1/index.html

[-- Attachment #2: Type: text/html, Size: 9157 bytes --]

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add 16bit register/mask operators

[Gustavo Sousa]

Quoting Clint Taylor (2023-05-05 15:46:39)
>Add the support macros to define/extract bits as 16bits.
>
>Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg_defs.h | 49 ++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
>index 622d603080f9..eb273f3ce3eb 100644
>--- a/drivers/gpu/drm/i915/i915_reg_defs.h
>+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
>@@ -143,6 +143,55 @@
>  */
> #define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
> 
>+/**
>+ * REG_BIT16() - Prepare a u16 bit value
>+ * @__n: 0-based bit number
>+ *
>+ * Local wrapper for BIT() to force u16, with compile time
>+ * checks.
>+ *
>+ * @return: Value with bit @__n set.
>+ */
>+#define REG_BIT16(__n)                                                   \
>+  ((u16)(BIT(__n) +                                                \
>+         BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&         \
>+                           ((__n) < 0 || (__n) > 15))))
>+
>+/**
>+ * REG_GENMASK16() - Prepare a continuous u8 bitmask
>+ * @__high: 0-based high bit
>+ * @__low: 0-based low bit
>+ *
>+ * Local wrapper for GENMASK() to force u16, with compile time
>+ * checks.
>+ *
>+ * @return: Continuous bitmask from @__high to @__low, inclusive.
>+ */
>+#define REG_GENMASK16(__high, __low)                                     \
>+  ((u16)(GENMASK(__high, __low) +                                  \
>+         BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&      \
>+                           __is_constexpr(__low) &&               \
>+                           ((__low) < 0 || (__high) > 15 || (__low) > (__high)))))
>+
>+/**
>+ * REG_FIELD_PREP16() - Prepare a u16 bitfield value
>+ * @__mask: shifted mask defining the field's length and position
>+ * @__val: value to put in the field
>+ *
>+ * Local copy of FIELD_PREP16() to generate an integer constant
>+ * expression, force u8 and for consistency with
>+ * REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16().
>+ *
>+ * @return: @__val masked and shifted into the field defined by @__mask.
>+ */
>+#define REG_FIELD_PREP16(__mask, __val)                                          \
>+  ((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +      \
>+         BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +             \
>+         BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) +          \
>+         BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
>+         BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
>+
>+

Nitpick: There is an extra blank line here.

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

> #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
> #define _MASKED_FIELD(mask, value) ({                                     \
>        if (__builtin_constant_p(mask))                                    \
>-- 
>2.25.1
>

Re: [Intel-gfx] [PATCH 2/2] drm/i915/hdmi: C20 computed PLL frequencies

[Gustavo Sousa]

Quoting Clint Taylor (2023-05-05 15:46:40)
>Use algorithm to generate HDMI C20 PLL clock frequencies.
>
>BSPEC: 64568
>Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>Cc: Mika Kahola <mika.kahola@intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 89 +++++++++++++++++--
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 53 +++++++++++
> 2 files changed, 136 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index d94127e7448b..fb5599ffca81 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -3,6 +3,8 @@
>  * Copyright © 2023 Intel Corporation
>  */
> 
>+#include <linux/log2.h>
>+#include <linux/math64.h>
> #include "i915_reg.h"
> #include "intel_cx0_phy.h"
> #include "intel_cx0_phy_regs.h"
>@@ -1901,6 +1903,74 @@ void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
>                            i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> }
> 
>+static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state)
>+{
>+  u64 datarate;
>+  u64 mpll_tx_clk_div;
>+  u64 vco_freq_shift;
>+  u64 vco_freq;
>+  u64 multiplier;
>+  u64 mpll_multiplier;
>+  u64 mpll_fracn_quot;
>+  u64 mpll_fracn_rem;
>+  u8  mpllb_ana_freq_vco;
>+  u8  mpll_div_multiplier;
>+
>+  if (pixel_clock < 25175 || pixel_clock > 600000)
>+          return -EINVAL;
>+
>+  datarate = ((u64)pixel_clock * 1000) * 10;
>+  mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, (u64)datarate));
>+  vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, (u64)datarate));
>+  vco_freq = (datarate << vco_freq_shift) >> 8;
>+  multiplier = div64_u64((vco_freq << 28), (REFCLK_38_4_MHZ >> 4));
>+  mpll_multiplier = 2 * (multiplier >> 32);
>+
>+  mpll_fracn_quot = (multiplier >> 16) & 0xFFFF;
>+  mpll_fracn_rem  = multiplier & 0xFFFF;
>+
>+  mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)), datarate), 255);
>+
>+  if (vco_freq <= DATARATE_3000000000)
>+          mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_3;
>+  else if (vco_freq <= DATARATE_3500000000)
>+          mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_2;
>+  else if (vco_freq <= DATARATE_4000000000)
>+          mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_1;
>+  else
>+          mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
>+
>+  pll_state->link_bit_rate        = pixel_clock;
>+  pll_state->clock        = pixel_clock;
>+  pll_state->tx[0]        = 0xbe88;
>+  pll_state->tx[1]        = 0x9800;
>+  pll_state->tx[2]        = 0x0000;
>+  pll_state->cmn[0]       = 0x0500;
>+  pll_state->cmn[1]       = 0x0005;
>+  pll_state->cmn[2]       = 0x0000;
>+  pll_state->cmn[3]       = 0x0000;
>+  pll_state->mpllb[0]     = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) |
>+                             MPLL_MULTIPLIER(mpll_multiplier));
>+  pll_state->mpllb[1]     = (CAL_DAC_CODE(CAL_DAC_CODE_31) |
>+                             WORD_CLK_DIV |
>+                             MPLL_DIV_MULTIPLIER(mpll_div_multiplier));
>+  pll_state->mpllb[2]     = (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) |
>+                             CP_PROP(CP_PROP_20) |
>+                             CP_INT(CP_INT_6));
>+  pll_state->mpllb[3]     = (V2I(V2I_2) |
>+                             CP_PROP_GS(CP_PROP_GS_30) |
>+                             CP_INT_GS(CP_INT_GS_28));
>+  pll_state->mpllb[4]     = 0x0000;
>+  pll_state->mpllb[5]     = 0x0000;
>+  pll_state->mpllb[6]     = (C20_MPLLB_FRACEN | SSC_UP_SPREAD);
>+  pll_state->mpllb[7]     = MPLL_FRACN_DEN;
>+  pll_state->mpllb[8]     = mpll_fracn_quot;
>+  pll_state->mpllb[9]     = mpll_fracn_rem;
>+  pll_state->mpllb[10]    = HDMI_DIV(HDMI_DIV_1);
>+
>+  return 0;
>+}
>+
> static int intel_c20_phy_check_hdmi_link_rate(int clock)
> {
>        const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
>@@ -1911,6 +1981,9 @@ static int intel_c20_phy_check_hdmi_link_rate(int clock)
>                        return MODE_OK;
>        }
> 
>+  if (clock >= 25175 && clock <= 594000)
>+          return MODE_OK;
>+
>        return MODE_CLOCK_RANGE;
> }
> 
>@@ -1944,6 +2017,13 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
>        const struct intel_c20pll_state * const *tables;
>        int i;
> 
>+  /* try computed C20 HDMI tables before using consolidated tables */
>+  if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
>+          if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock,
>+                                              &crtc_state->cx0pll_state.c20) == 0)
>+                  return 0;
>+  }
>+
>        tables = intel_c20_pll_tables_get(crtc_state, encoder);
>        if (!tables)
>                return -EINVAL;
>@@ -2093,13 +2173,10 @@ static u8 intel_c20_get_dp_rate(u32 clock)
> 
> static u8 intel_c20_get_hdmi_rate(u32 clock)
> {
>-  switch (clock) {
>-  case 25175:
>-  case 27000:
>-  case 74250:
>-  case 148500:
>-  case 594000:
>+  if ((clock >= 25175) && (clock <= 600000))
>                return 0;
>+
>+  switch (clock) {
>        case 166670: /* 3 Gbps */
>        case 333330: /* 6 Gbps */
>        case 666670: /* 12 Gbps */
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>index ab9d1d983b88..cb5d1be2ba19 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>@@ -218,4 +218,57 @@
> 
> #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
> 
>+/* C20 HDMI computed pll definitions */
>+#define REFCLK_38_4_MHZ           38400000
>+#define CLOCK_4999MHZ             4999999999
>+#define CLOCK_9999MHZ             9999999999
>+#define DATARATE_3000000000       3000000000
>+#define DATARATE_3500000000       3500000000
>+#define DATARATE_4000000000       4000000000
>+#define MPLL_FRACN_DEN            0xFFFF
>+
>+#define SSC_UP_SPREAD             REG_BIT16(9)
>+#define WORD_CLK_DIV              REG_BIT16(8)
>+
>+#define MPLL_TX_CLK_DIV(val)      REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val)
>+#define MPLL_MULTIPLIER(val)      REG_FIELD_PREP16(C20_MULTIPLIER_MASK, val)
>+
>+#define MPLLB_ANA_FREQ_VCO_0      0
>+#define MPLLB_ANA_FREQ_VCO_1      1
>+#define MPLLB_ANA_FREQ_VCO_2      2
>+#define MPLLB_ANA_FREQ_VCO_3      3
>+#define MPLLB_ANA_FREQ_VCO_MASK   REG_GENMASK16(15, 14)
>+#define MPLLB_ANA_FREQ_VCO(val)   REG_FIELD_PREP16(MPLLB_ANA_FREQ_VCO_MASK, val)
>+
>+#define MPLL_DIV_MULTIPLIER_MASK  REG_GENMASK16(7, 0)
>+#define MPLL_DIV_MULTIPLIER(val)  REG_FIELD_PREP16(MPLL_DIV_MULTIPLIER_MASK, val)
>+
>+#define CAL_DAC_CODE_31           31
>+#define CAL_DAC_CODE_MASK REG_GENMASK16(14, 10)
>+#define CAL_DAC_CODE(val) REG_FIELD_PREP16(CAL_DAC_CODE_MASK, val)
>+
>+#define CP_INT_GS_28              28
>+#define CP_INT_GS_MASK            REG_GENMASK16(6, 0)
>+#define CP_INT_GS(val)            REG_FIELD_PREP16(CP_INT_GS_MASK, val)
>+
>+#define CP_PROP_GS_30             30
>+#define CP_PROP_GS_MASK           REG_GENMASK16(13, 7)
>+#define CP_PROP_GS(val)           REG_FIELD_PREP16(CP_PROP_GS_MASK, val)
>+
>+#define CP_INT_6          6
>+#define CP_INT_MASK               REG_GENMASK16(6, 0)
>+#define CP_INT(val)               REG_FIELD_PREP16(CP_INT_MASK, val)
>+
>+#define CP_PROP_20                20
>+#define CP_PROP_MASK              REG_GENMASK16(13, 7)
>+#define CP_PROP(val)              REG_FIELD_PREP16(CP_PROP_MASK, val)
>+
>+#define V2I_2                     2
>+#define V2I_MASK          REG_GENMASK16(15, 14)
>+#define V2I(val)          REG_FIELD_PREP16(V2I_MASK, val)
>+
>+#define HDMI_DIV_1                1
>+#define HDMI_DIV_MASK             REG_GENMASK16(2, 0)
>+#define HDMI_DIV(val)             REG_FIELD_PREP16(HDMI_DIV_MASK, val)
>+
> #endif /* __INTEL_CX0_REG_DEFS_H__ */
>-- 
>2.25.1
>