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* [djiang:cxl-qtg 22/28] drivers/cxl/port.c:88 cxl_port_perf_data_calculate() error: we previously assumed 'cxl_root->ops' could be null (see line 88)
@ 2023-05-05 18:47 kernel test robot
  0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2023-05-05 18:47 UTC (permalink / raw)
  To: oe-kbuild; +Cc: lkp, Dan Carpenter

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
TO: Dave Jiang <dave.jiang@intel.com>

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git cxl-qtg
head:   4cc79fc6093484664713b47ccd4b4cff326bca86
commit: 90a255f34829f50adb9fbfcd8e32444b188074e3 [22/28] cxl: Compute the entire CXL path latency and bandwidth data
:::::: branch date: 2 hours ago
:::::: commit date: 18 hours ago
config: i386-randconfig-m021 (https://download.01.org/0day-ci/archive/20230506/202305060238.eVFtMQO6-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-12) 11.3.0

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Link: https://lore.kernel.org/r/202305060238.eVFtMQO6-lkp@intel.com/

smatch warnings:
drivers/cxl/port.c:88 cxl_port_perf_data_calculate() error: we previously assumed 'cxl_root->ops' could be null (see line 88)

vim +88 drivers/cxl/port.c

f249841f3973f0 Dave Jiang 2023-04-24   69  
90a255f34829f5 Dave Jiang 2022-12-05   70  static int cxl_port_perf_data_calculate(struct cxl_port *port,
90a255f34829f5 Dave Jiang 2022-12-05   71  					struct list_head *dsmas_list)
90a255f34829f5 Dave Jiang 2022-12-05   72  {
90a255f34829f5 Dave Jiang 2022-12-05   73  	struct access_coordinate c;
90a255f34829f5 Dave Jiang 2022-12-05   74  	struct qtg_dsm_input input;
90a255f34829f5 Dave Jiang 2022-12-05   75  	struct cxl_port *root_port;
90a255f34829f5 Dave Jiang 2022-12-05   76  	struct cxl_root *cxl_root;
90a255f34829f5 Dave Jiang 2022-12-05   77  	struct dsmas_entry *dent;
90a255f34829f5 Dave Jiang 2022-12-05   78  	int rc, qos_class;
90a255f34829f5 Dave Jiang 2022-12-05   79  
90a255f34829f5 Dave Jiang 2022-12-05   80  	rc = cxl_endpoint_get_perf_coordinates(port, &c);
90a255f34829f5 Dave Jiang 2022-12-05   81  	if (rc) {
90a255f34829f5 Dave Jiang 2022-12-05   82  		dev_dbg(&port->dev, "Failed to retrieve perf coordinates.\n");
90a255f34829f5 Dave Jiang 2022-12-05   83  		return rc;
90a255f34829f5 Dave Jiang 2022-12-05   84  	}
90a255f34829f5 Dave Jiang 2022-12-05   85  
90a255f34829f5 Dave Jiang 2022-12-05   86  	root_port = find_cxl_root(port);
90a255f34829f5 Dave Jiang 2022-12-05   87  	cxl_root = to_cxl_root(root_port);
90a255f34829f5 Dave Jiang 2022-12-05  @88  	if (!cxl_root->ops && !cxl_root->ops->get_qos_class)
90a255f34829f5 Dave Jiang 2022-12-05   89  		return -EOPNOTSUPP;
90a255f34829f5 Dave Jiang 2022-12-05   90  
90a255f34829f5 Dave Jiang 2022-12-05   91  	list_for_each_entry(dent, dsmas_list, list) {
90a255f34829f5 Dave Jiang 2022-12-05   92  		dent->coord.read_latency = dent->coord.read_latency +
90a255f34829f5 Dave Jiang 2022-12-05   93  					   c.read_latency;
90a255f34829f5 Dave Jiang 2022-12-05   94  		dent->coord.write_latency = dent->coord.write_latency +
90a255f34829f5 Dave Jiang 2022-12-05   95  					    c.write_latency;
90a255f34829f5 Dave Jiang 2022-12-05   96  		dent->coord.read_bandwidth = min_t(int, c.read_bandwidth,
90a255f34829f5 Dave Jiang 2022-12-05   97  						   dent->coord.read_bandwidth);
90a255f34829f5 Dave Jiang 2022-12-05   98  		dent->coord.write_bandwidth = min_t(int, c.write_bandwidth,
90a255f34829f5 Dave Jiang 2022-12-05   99  						    dent->coord.write_bandwidth);
90a255f34829f5 Dave Jiang 2022-12-05  100  
90a255f34829f5 Dave Jiang 2022-12-05  101  		input.rd_lat = cpu_to_le32(dent->coord.read_latency);
90a255f34829f5 Dave Jiang 2022-12-05  102  		input.wr_lat = cpu_to_le32(dent->coord.write_latency);
90a255f34829f5 Dave Jiang 2022-12-05  103  		input.rd_bw = cpu_to_le32(dent->coord.read_bandwidth);
90a255f34829f5 Dave Jiang 2022-12-05  104  		input.wr_bw = cpu_to_le32(dent->coord.write_bandwidth);
90a255f34829f5 Dave Jiang 2022-12-05  105  
90a255f34829f5 Dave Jiang 2022-12-05  106  		qos_class = cxl_root->ops->get_qos_class(root_port, &input);
90a255f34829f5 Dave Jiang 2022-12-05  107  		if (qos_class < 0)
90a255f34829f5 Dave Jiang 2022-12-05  108  			continue;
90a255f34829f5 Dave Jiang 2022-12-05  109  
90a255f34829f5 Dave Jiang 2022-12-05  110  		dent->qos_class = qos_class;
90a255f34829f5 Dave Jiang 2022-12-05  111  	}
90a255f34829f5 Dave Jiang 2022-12-05  112  
90a255f34829f5 Dave Jiang 2022-12-05  113  	return 0;
90a255f34829f5 Dave Jiang 2022-12-05  114  }
90a255f34829f5 Dave Jiang 2022-12-05  115  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests

^ permalink raw reply	[flat|nested] 2+ messages in thread
* [djiang:cxl-qtg 22/28] drivers/cxl/port.c:88 cxl_port_perf_data_calculate() error: we previously assumed 'cxl_root->ops' could be null (see line 88)
@ 2023-05-05 20:33 Dan Carpenter
  0 siblings, 0 replies; 2+ messages in thread
From: Dan Carpenter @ 2023-05-05 20:33 UTC (permalink / raw)
  To: oe-kbuild, Dave Jiang; +Cc: lkp, oe-kbuild-all

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git cxl-qtg
head:   4cc79fc6093484664713b47ccd4b4cff326bca86
commit: 90a255f34829f50adb9fbfcd8e32444b188074e3 [22/28] cxl: Compute the entire CXL path latency and bandwidth data
config: i386-randconfig-m021 (https://download.01.org/0day-ci/archive/20230506/202305060238.eVFtMQO6-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-12) 11.3.0

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Link: https://lore.kernel.org/r/202305060238.eVFtMQO6-lkp@intel.com/

smatch warnings:
drivers/cxl/port.c:88 cxl_port_perf_data_calculate() error: we previously assumed 'cxl_root->ops' could be null (see line 88)

vim +88 drivers/cxl/port.c

90a255f34829f5 Dave Jiang 2022-12-05   70  static int cxl_port_perf_data_calculate(struct cxl_port *port,
90a255f34829f5 Dave Jiang 2022-12-05   71  					struct list_head *dsmas_list)
90a255f34829f5 Dave Jiang 2022-12-05   72  {
90a255f34829f5 Dave Jiang 2022-12-05   73  	struct access_coordinate c;
90a255f34829f5 Dave Jiang 2022-12-05   74  	struct qtg_dsm_input input;
90a255f34829f5 Dave Jiang 2022-12-05   75  	struct cxl_port *root_port;
90a255f34829f5 Dave Jiang 2022-12-05   76  	struct cxl_root *cxl_root;
90a255f34829f5 Dave Jiang 2022-12-05   77  	struct dsmas_entry *dent;
90a255f34829f5 Dave Jiang 2022-12-05   78  	int rc, qos_class;
90a255f34829f5 Dave Jiang 2022-12-05   79  
90a255f34829f5 Dave Jiang 2022-12-05   80  	rc = cxl_endpoint_get_perf_coordinates(port, &c);
90a255f34829f5 Dave Jiang 2022-12-05   81  	if (rc) {
90a255f34829f5 Dave Jiang 2022-12-05   82  		dev_dbg(&port->dev, "Failed to retrieve perf coordinates.\n");
90a255f34829f5 Dave Jiang 2022-12-05   83  		return rc;
90a255f34829f5 Dave Jiang 2022-12-05   84  	}
90a255f34829f5 Dave Jiang 2022-12-05   85  
90a255f34829f5 Dave Jiang 2022-12-05   86  	root_port = find_cxl_root(port);
90a255f34829f5 Dave Jiang 2022-12-05   87  	cxl_root = to_cxl_root(root_port);
90a255f34829f5 Dave Jiang 2022-12-05  @88  	if (!cxl_root->ops && !cxl_root->ops->get_qos_class)
                                                     ^^^^^^^^^^^^^
Should this probably be || instead of &&.

90a255f34829f5 Dave Jiang 2022-12-05   89  		return -EOPNOTSUPP;
90a255f34829f5 Dave Jiang 2022-12-05   90  
90a255f34829f5 Dave Jiang 2022-12-05   91  	list_for_each_entry(dent, dsmas_list, list) {
90a255f34829f5 Dave Jiang 2022-12-05   92  		dent->coord.read_latency = dent->coord.read_latency +
90a255f34829f5 Dave Jiang 2022-12-05   93  					   c.read_latency;
90a255f34829f5 Dave Jiang 2022-12-05   94  		dent->coord.write_latency = dent->coord.write_latency +
90a255f34829f5 Dave Jiang 2022-12-05   95  					    c.write_latency;
90a255f34829f5 Dave Jiang 2022-12-05   96  		dent->coord.read_bandwidth = min_t(int, c.read_bandwidth,
90a255f34829f5 Dave Jiang 2022-12-05   97  						   dent->coord.read_bandwidth);
90a255f34829f5 Dave Jiang 2022-12-05   98  		dent->coord.write_bandwidth = min_t(int, c.write_bandwidth,
90a255f34829f5 Dave Jiang 2022-12-05   99  						    dent->coord.write_bandwidth);
90a255f34829f5 Dave Jiang 2022-12-05  100  
90a255f34829f5 Dave Jiang 2022-12-05  101  		input.rd_lat = cpu_to_le32(dent->coord.read_latency);
90a255f34829f5 Dave Jiang 2022-12-05  102  		input.wr_lat = cpu_to_le32(dent->coord.write_latency);
90a255f34829f5 Dave Jiang 2022-12-05  103  		input.rd_bw = cpu_to_le32(dent->coord.read_bandwidth);
90a255f34829f5 Dave Jiang 2022-12-05  104  		input.wr_bw = cpu_to_le32(dent->coord.write_bandwidth);
90a255f34829f5 Dave Jiang 2022-12-05  105  
90a255f34829f5 Dave Jiang 2022-12-05  106  		qos_class = cxl_root->ops->get_qos_class(root_port, &input);
90a255f34829f5 Dave Jiang 2022-12-05  107  		if (qos_class < 0)
90a255f34829f5 Dave Jiang 2022-12-05  108  			continue;
90a255f34829f5 Dave Jiang 2022-12-05  109  
90a255f34829f5 Dave Jiang 2022-12-05  110  		dent->qos_class = qos_class;
90a255f34829f5 Dave Jiang 2022-12-05  111  	}
90a255f34829f5 Dave Jiang 2022-12-05  112  
90a255f34829f5 Dave Jiang 2022-12-05  113  	return 0;
90a255f34829f5 Dave Jiang 2022-12-05  114  }

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests


^ permalink raw reply	[flat|nested] 2+ messages in thread
end of thread, other threads:[~2023-05-05 20:33 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-05 18:47 [djiang:cxl-qtg 22/28] drivers/cxl/port.c:88 cxl_port_perf_data_calculate() error: we previously assumed 'cxl_root->ops' could be null (see line 88) kernel test robot
2023-05-05 20:33 Dan Carpenter

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