* [PATCH v2 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe
@ 2023-05-09 18:25 ` Evan Green
0 siblings, 0 replies; 26+ messages in thread
From: Evan Green @ 2023-05-09 18:25 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Evan Green, Albert Ou, Andrew Bresticker, Andrew Jones,
Anup Patel, Celeste Liu, Conor Dooley, Heiko Stuebner,
Jisheng Zhang, Jonathan Corbet, Palmer Dabbelt, Paul Walmsley,
Sunil V L, linux-doc, linux-kernel, linux-riscv
This change detects the presence of Zba, Zbb, and Zbs extensions and exports
them per-hart to userspace via the hwprobe mechanism. Glibc can then use
these in setting up hwcaps-based library search paths.
There's a little bit of extra housekeeping here: the first change adds
Zba and Zbs to the set of extensions the kernel recognizes, and the second
change starts tracking ISA features per-hart (in addition to the ANDed
mask of features across all harts which the kernel uses to make
decisions). Now that we track the ISA information per-hart, we could
even fix up /proc/cpuinfo to accurately report extension per-hart,
though I've left that out of this series for now.
Changes in v2:
- Add Zbs as well
- Add blank line before if in riscv_fill_hwcap() (Conor)
- Fixed typo s/supporte/supported/ (Conor)
- Fixed copypasta s/IMA_ZBB/EXT_ZBB/ (Conor)
- Added Zbs
Evan Green (3):
RISC-V: Add Zba, Zbs extension probing
RISC-V: Track ISA extensions per hart
RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
Documentation/riscv/hwprobe.rst | 10 ++++++
arch/riscv/include/asm/cpufeature.h | 10 ++++++
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/include/uapi/asm/hwprobe.h | 3 ++
arch/riscv/kernel/cpu.c | 2 ++
arch/riscv/kernel/cpufeature.c | 20 +++++++----
arch/riscv/kernel/sys_riscv.c | 48 +++++++++++++++++++++++----
7 files changed, 82 insertions(+), 13 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe
@ 2023-05-09 18:25 ` Evan Green
0 siblings, 0 replies; 26+ messages in thread
From: Evan Green @ 2023-05-09 18:25 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Anup Patel, Albert Ou, Jonathan Corbet, Andrew Bresticker,
linux-doc, linux-kernel, Conor Dooley, Evan Green, Celeste Liu,
Jisheng Zhang, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Heiko Stuebner, Andrew Jones
This change detects the presence of Zba, Zbb, and Zbs extensions and exports
them per-hart to userspace via the hwprobe mechanism. Glibc can then use
these in setting up hwcaps-based library search paths.
There's a little bit of extra housekeeping here: the first change adds
Zba and Zbs to the set of extensions the kernel recognizes, and the second
change starts tracking ISA features per-hart (in addition to the ANDed
mask of features across all harts which the kernel uses to make
decisions). Now that we track the ISA information per-hart, we could
even fix up /proc/cpuinfo to accurately report extension per-hart,
though I've left that out of this series for now.
Changes in v2:
- Add Zbs as well
- Add blank line before if in riscv_fill_hwcap() (Conor)
- Fixed typo s/supporte/supported/ (Conor)
- Fixed copypasta s/IMA_ZBB/EXT_ZBB/ (Conor)
- Added Zbs
Evan Green (3):
RISC-V: Add Zba, Zbs extension probing
RISC-V: Track ISA extensions per hart
RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
Documentation/riscv/hwprobe.rst | 10 ++++++
arch/riscv/include/asm/cpufeature.h | 10 ++++++
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/include/uapi/asm/hwprobe.h | 3 ++
arch/riscv/kernel/cpu.c | 2 ++
arch/riscv/kernel/cpufeature.c | 20 +++++++----
arch/riscv/kernel/sys_riscv.c | 48 +++++++++++++++++++++++----
7 files changed, 82 insertions(+), 13 deletions(-)
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
2023-05-09 18:25 ` Evan Green
@ 2023-05-09 18:25 ` Evan Green
-1 siblings, 0 replies; 26+ messages in thread
From: Evan Green @ 2023-05-09 18:25 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Evan Green, Andrew Jones, Albert Ou, Anup Patel, Conor Dooley,
Heiko Stuebner, Jisheng Zhang, Palmer Dabbelt, Paul Walmsley,
Sunil V L, linux-kernel, linux-riscv
Add the Zba address bit manipulation extension and Zbs single bit
instructions extension into those the kernel is aware of and maintains
in its riscv_isa bitmap.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
Changes in v2:
- Add Zbs as well
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpu.c | 2 ++
arch/riscv/kernel/cpufeature.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index e0c40a4c63d5..6b2e8ff4638c 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -46,6 +46,8 @@
#define RISCV_ISA_EXT_ZICBOZ 34
#define RISCV_ISA_EXT_SMAIA 35
#define RISCV_ISA_EXT_SSAIA 36
+#define RISCV_ISA_EXT_ZBA 37
+#define RISCV_ISA_EXT_ZBS 38
#define RISCV_ISA_EXT_MAX 64
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c96aa56cf1c7..bd294364390d 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -184,7 +184,9 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
+ __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
+ __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index b1d6b7e4b829..a1954c83638f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -236,7 +236,9 @@ void __init riscv_fill_hwcap(void)
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
+ SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
+ SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
@ 2023-05-09 18:25 ` Evan Green
0 siblings, 0 replies; 26+ messages in thread
From: Evan Green @ 2023-05-09 18:25 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Anup Patel, Albert Ou, linux-kernel, Conor Dooley, Evan Green,
Palmer Dabbelt, Jisheng Zhang, Paul Walmsley, linux-riscv,
Heiko Stuebner, Andrew Jones
Add the Zba address bit manipulation extension and Zbs single bit
instructions extension into those the kernel is aware of and maintains
in its riscv_isa bitmap.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
Changes in v2:
- Add Zbs as well
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpu.c | 2 ++
arch/riscv/kernel/cpufeature.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index e0c40a4c63d5..6b2e8ff4638c 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -46,6 +46,8 @@
#define RISCV_ISA_EXT_ZICBOZ 34
#define RISCV_ISA_EXT_SMAIA 35
#define RISCV_ISA_EXT_SSAIA 36
+#define RISCV_ISA_EXT_ZBA 37
+#define RISCV_ISA_EXT_ZBS 38
#define RISCV_ISA_EXT_MAX 64
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c96aa56cf1c7..bd294364390d 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -184,7 +184,9 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
+ __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
+ __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index b1d6b7e4b829..a1954c83638f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -236,7 +236,9 @@ void __init riscv_fill_hwcap(void)
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
+ SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
+ SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 2/3] RISC-V: Track ISA extensions per hart
2023-05-09 18:25 ` Evan Green
@ 2023-05-09 18:25 ` Evan Green
-1 siblings, 0 replies; 26+ messages in thread
From: Evan Green @ 2023-05-09 18:25 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Evan Green, Andrew Jones, Conor Dooley, Albert Ou, Anup Patel,
Heiko Stuebner, Jisheng Zhang, Palmer Dabbelt, Paul Walmsley,
linux-kernel, linux-riscv
The kernel maintains a mask of ISA extensions ANDed together across all
harts. Let's also keep a bitmap of ISA extensions for each CPU. Although
the kernel is currently unlikely to enable a feature that exists only on
some CPUs, we want the ability to report asymmetric CPU extensions
accurately to usermode.
Note that riscv_fill_hwcaps() runs before the per_cpu_offsets are built,
which is why I've used a [NR_CPUS] array rather than per_cpu() data.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
Changes in v2:
- Add blank line before if in riscv_fill_hwcap() (Conor)
arch/riscv/include/asm/cpufeature.h | 10 ++++++++++
arch/riscv/kernel/cpufeature.c | 18 ++++++++++++------
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 808d5403f2ac..23fed53b8815 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -6,6 +6,9 @@
#ifndef _ASM_CPUFEATURE_H
#define _ASM_CPUFEATURE_H
+#include <linux/bitmap.h>
+#include <asm/hwcap.h>
+
/*
* These are probed via a device_initcall(), via either the SBI or directly
* from the corresponding CSRs.
@@ -16,8 +19,15 @@ struct riscv_cpuinfo {
unsigned long mimpid;
};
+struct riscv_isainfo {
+ DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
+};
+
DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
DECLARE_PER_CPU(long, misaligned_access_speed);
+/* Per-cpu ISA extensions. */
+extern struct riscv_isainfo hart_isa[NR_CPUS];
+
#endif
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a1954c83638f..e8b7b4b20bb5 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -26,6 +26,9 @@ unsigned long elf_hwcap __read_mostly;
/* Host ISA bitmap */
static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
+/* Per-cpu ISA extensions. */
+struct riscv_isainfo hart_isa[NR_CPUS];
+
/* Performance information */
DEFINE_PER_CPU(long, misaligned_access_speed);
@@ -113,14 +116,18 @@ void __init riscv_fill_hwcap(void)
bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
for_each_of_cpu_node(node) {
+ struct riscv_isainfo *isainfo;
unsigned long this_hwcap = 0;
- DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
const char *temp;
+ unsigned int cpu_id;
rc = riscv_of_processor_hartid(node, &hartid);
if (rc < 0)
continue;
+ cpu_id = riscv_hartid_to_cpuid(hartid);
+ isainfo = &hart_isa[cpu_id];
+
if (of_property_read_string(node, "riscv,isa", &isa)) {
pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
continue;
@@ -137,7 +144,6 @@ void __init riscv_fill_hwcap(void)
/* The riscv,isa DT property must start with rv64 or rv32 */
if (temp == isa)
continue;
- bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
for (; *isa; ++isa) {
const char *ext = isa++;
const char *ext_end = isa;
@@ -215,7 +221,7 @@ void __init riscv_fill_hwcap(void)
if ((ext_end - ext == sizeof(name) - 1) && \
!memcmp(ext, name, sizeof(name) - 1) && \
riscv_isa_extension_check(bit)) \
- set_bit(bit, this_isa); \
+ set_bit(bit, isainfo->isa); \
} while (false) \
if (unlikely(ext_err))
@@ -225,7 +231,7 @@ void __init riscv_fill_hwcap(void)
if (riscv_isa_extension_check(nr)) {
this_hwcap |= isa2hwcap[nr];
- set_bit(nr, this_isa);
+ set_bit(nr, isainfo->isa);
}
} else {
/* sorted alphabetically */
@@ -257,9 +263,9 @@ void __init riscv_fill_hwcap(void)
elf_hwcap = this_hwcap;
if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
- bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+ bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
else
- bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+ bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
}
/* We don't support systems with F but without D, so mask those out
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 2/3] RISC-V: Track ISA extensions per hart
@ 2023-05-09 18:25 ` Evan Green
0 siblings, 0 replies; 26+ messages in thread
From: Evan Green @ 2023-05-09 18:25 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Evan Green, Andrew Jones, Conor Dooley, Albert Ou, Anup Patel,
Heiko Stuebner, Jisheng Zhang, Palmer Dabbelt, Paul Walmsley,
linux-kernel, linux-riscv
The kernel maintains a mask of ISA extensions ANDed together across all
harts. Let's also keep a bitmap of ISA extensions for each CPU. Although
the kernel is currently unlikely to enable a feature that exists only on
some CPUs, we want the ability to report asymmetric CPU extensions
accurately to usermode.
Note that riscv_fill_hwcaps() runs before the per_cpu_offsets are built,
which is why I've used a [NR_CPUS] array rather than per_cpu() data.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
Changes in v2:
- Add blank line before if in riscv_fill_hwcap() (Conor)
arch/riscv/include/asm/cpufeature.h | 10 ++++++++++
arch/riscv/kernel/cpufeature.c | 18 ++++++++++++------
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 808d5403f2ac..23fed53b8815 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -6,6 +6,9 @@
#ifndef _ASM_CPUFEATURE_H
#define _ASM_CPUFEATURE_H
+#include <linux/bitmap.h>
+#include <asm/hwcap.h>
+
/*
* These are probed via a device_initcall(), via either the SBI or directly
* from the corresponding CSRs.
@@ -16,8 +19,15 @@ struct riscv_cpuinfo {
unsigned long mimpid;
};
+struct riscv_isainfo {
+ DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
+};
+
DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
DECLARE_PER_CPU(long, misaligned_access_speed);
+/* Per-cpu ISA extensions. */
+extern struct riscv_isainfo hart_isa[NR_CPUS];
+
#endif
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a1954c83638f..e8b7b4b20bb5 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -26,6 +26,9 @@ unsigned long elf_hwcap __read_mostly;
/* Host ISA bitmap */
static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
+/* Per-cpu ISA extensions. */
+struct riscv_isainfo hart_isa[NR_CPUS];
+
/* Performance information */
DEFINE_PER_CPU(long, misaligned_access_speed);
@@ -113,14 +116,18 @@ void __init riscv_fill_hwcap(void)
bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
for_each_of_cpu_node(node) {
+ struct riscv_isainfo *isainfo;
unsigned long this_hwcap = 0;
- DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
const char *temp;
+ unsigned int cpu_id;
rc = riscv_of_processor_hartid(node, &hartid);
if (rc < 0)
continue;
+ cpu_id = riscv_hartid_to_cpuid(hartid);
+ isainfo = &hart_isa[cpu_id];
+
if (of_property_read_string(node, "riscv,isa", &isa)) {
pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
continue;
@@ -137,7 +144,6 @@ void __init riscv_fill_hwcap(void)
/* The riscv,isa DT property must start with rv64 or rv32 */
if (temp == isa)
continue;
- bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
for (; *isa; ++isa) {
const char *ext = isa++;
const char *ext_end = isa;
@@ -215,7 +221,7 @@ void __init riscv_fill_hwcap(void)
if ((ext_end - ext == sizeof(name) - 1) && \
!memcmp(ext, name, sizeof(name) - 1) && \
riscv_isa_extension_check(bit)) \
- set_bit(bit, this_isa); \
+ set_bit(bit, isainfo->isa); \
} while (false) \
if (unlikely(ext_err))
@@ -225,7 +231,7 @@ void __init riscv_fill_hwcap(void)
if (riscv_isa_extension_check(nr)) {
this_hwcap |= isa2hwcap[nr];
- set_bit(nr, this_isa);
+ set_bit(nr, isainfo->isa);
}
} else {
/* sorted alphabetically */
@@ -257,9 +263,9 @@ void __init riscv_fill_hwcap(void)
elf_hwcap = this_hwcap;
if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
- bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+ bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
else
- bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+ bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
}
/* We don't support systems with F but without D, so mask those out
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
2023-05-09 18:25 ` Evan Green
@ 2023-05-09 18:25 ` Evan Green
-1 siblings, 0 replies; 26+ messages in thread
From: Evan Green @ 2023-05-09 18:25 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Evan Green, Andrew Jones, Albert Ou, Andrew Bresticker,
Celeste Liu, Conor Dooley, Heiko Stuebner, Jonathan Corbet,
Palmer Dabbelt, Paul Walmsley, linux-doc, linux-kernel,
linux-riscv
Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
These are accurately reported per CPU.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
Changes in v2:
- Fixed typo s/supporte/supported/ (Conor)
- Fixed copypasta s/IMA_ZBB/EXT_ZBB/ (Conor)
- Added Zbs
Documentation/riscv/hwprobe.rst | 10 ++++++
arch/riscv/include/uapi/asm/hwprobe.h | 3 ++
arch/riscv/kernel/sys_riscv.c | 48 +++++++++++++++++++++++----
3 files changed, 54 insertions(+), 7 deletions(-)
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index 9f0dd62dcb5d..fb25670ef0e5 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -64,6 +64,16 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
by version 2.2 of the RISC-V ISA manual.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
+ supported, as defined in version 1.0 of the Bit-Manipulation ISA
+ extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined
+ in version 1.0 of the Bit-Manipulation ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
+ in version 1.0 of the Bit-Manipulation ISA extensions.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 8d745a4ad8a2..853f8f6d9a42 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -25,6 +25,9 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
#define RISCV_HWPROBE_IMA_FD (1 << 0)
#define RISCV_HWPROBE_IMA_C (1 << 1)
+#define RISCV_HWPROBE_EXT_ZBA (1 << 2)
+#define RISCV_HWPROBE_EXT_ZBB (1 << 3)
+#define RISCV_HWPROBE_EXT_ZBS (1 << 4)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 5db29683ebee..fe655db19ab4 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -121,6 +121,46 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair,
pair->value = id;
}
+static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
+ const struct cpumask *cpus)
+{
+ int cpu;
+ u64 missing = 0;
+
+ pair->value = 0;
+ if (has_fpu())
+ pair->value |= RISCV_HWPROBE_IMA_FD;
+
+ if (riscv_isa_extension_available(NULL, c))
+ pair->value |= RISCV_HWPROBE_IMA_C;
+
+ /*
+ * Loop through and record extensions that 1) anyone has, and 2) anyone
+ * doesn't have.
+ */
+ for_each_cpu(cpu, cpus) {
+ struct riscv_isainfo *isainfo = &hart_isa[cpu];
+
+ if (riscv_isa_extension_available(isainfo->isa, ZBA))
+ pair->value |= RISCV_HWPROBE_EXT_ZBA;
+ else
+ missing |= RISCV_HWPROBE_EXT_ZBA;
+
+ if (riscv_isa_extension_available(isainfo->isa, ZBB))
+ pair->value |= RISCV_HWPROBE_EXT_ZBB;
+ else
+ missing |= RISCV_HWPROBE_EXT_ZBB;
+
+ if (riscv_isa_extension_available(isainfo->isa, ZBS))
+ pair->value |= RISCV_HWPROBE_EXT_ZBS;
+ else
+ missing |= RISCV_HWPROBE_EXT_ZBS;
+ }
+
+ /* Now turn off reporting features if any CPU is missing it. */
+ pair->value &= ~missing;
+}
+
static u64 hwprobe_misaligned(const struct cpumask *cpus)
{
int cpu;
@@ -164,13 +204,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
break;
case RISCV_HWPROBE_KEY_IMA_EXT_0:
- pair->value = 0;
- if (has_fpu())
- pair->value |= RISCV_HWPROBE_IMA_FD;
-
- if (riscv_isa_extension_available(NULL, c))
- pair->value |= RISCV_HWPROBE_IMA_C;
-
+ hwprobe_isa_ext0(pair, cpus);
break;
case RISCV_HWPROBE_KEY_CPUPERF_0:
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
@ 2023-05-09 18:25 ` Evan Green
0 siblings, 0 replies; 26+ messages in thread
From: Evan Green @ 2023-05-09 18:25 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Evan Green, Andrew Jones, Albert Ou, Andrew Bresticker,
Celeste Liu, Conor Dooley, Heiko Stuebner, Jonathan Corbet,
Palmer Dabbelt, Paul Walmsley, linux-doc, linux-kernel,
linux-riscv
Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
These are accurately reported per CPU.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
Changes in v2:
- Fixed typo s/supporte/supported/ (Conor)
- Fixed copypasta s/IMA_ZBB/EXT_ZBB/ (Conor)
- Added Zbs
Documentation/riscv/hwprobe.rst | 10 ++++++
arch/riscv/include/uapi/asm/hwprobe.h | 3 ++
arch/riscv/kernel/sys_riscv.c | 48 +++++++++++++++++++++++----
3 files changed, 54 insertions(+), 7 deletions(-)
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index 9f0dd62dcb5d..fb25670ef0e5 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -64,6 +64,16 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
by version 2.2 of the RISC-V ISA manual.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
+ supported, as defined in version 1.0 of the Bit-Manipulation ISA
+ extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined
+ in version 1.0 of the Bit-Manipulation ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
+ in version 1.0 of the Bit-Manipulation ISA extensions.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 8d745a4ad8a2..853f8f6d9a42 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -25,6 +25,9 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
#define RISCV_HWPROBE_IMA_FD (1 << 0)
#define RISCV_HWPROBE_IMA_C (1 << 1)
+#define RISCV_HWPROBE_EXT_ZBA (1 << 2)
+#define RISCV_HWPROBE_EXT_ZBB (1 << 3)
+#define RISCV_HWPROBE_EXT_ZBS (1 << 4)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 5db29683ebee..fe655db19ab4 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -121,6 +121,46 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair,
pair->value = id;
}
+static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
+ const struct cpumask *cpus)
+{
+ int cpu;
+ u64 missing = 0;
+
+ pair->value = 0;
+ if (has_fpu())
+ pair->value |= RISCV_HWPROBE_IMA_FD;
+
+ if (riscv_isa_extension_available(NULL, c))
+ pair->value |= RISCV_HWPROBE_IMA_C;
+
+ /*
+ * Loop through and record extensions that 1) anyone has, and 2) anyone
+ * doesn't have.
+ */
+ for_each_cpu(cpu, cpus) {
+ struct riscv_isainfo *isainfo = &hart_isa[cpu];
+
+ if (riscv_isa_extension_available(isainfo->isa, ZBA))
+ pair->value |= RISCV_HWPROBE_EXT_ZBA;
+ else
+ missing |= RISCV_HWPROBE_EXT_ZBA;
+
+ if (riscv_isa_extension_available(isainfo->isa, ZBB))
+ pair->value |= RISCV_HWPROBE_EXT_ZBB;
+ else
+ missing |= RISCV_HWPROBE_EXT_ZBB;
+
+ if (riscv_isa_extension_available(isainfo->isa, ZBS))
+ pair->value |= RISCV_HWPROBE_EXT_ZBS;
+ else
+ missing |= RISCV_HWPROBE_EXT_ZBS;
+ }
+
+ /* Now turn off reporting features if any CPU is missing it. */
+ pair->value &= ~missing;
+}
+
static u64 hwprobe_misaligned(const struct cpumask *cpus)
{
int cpu;
@@ -164,13 +204,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
break;
case RISCV_HWPROBE_KEY_IMA_EXT_0:
- pair->value = 0;
- if (has_fpu())
- pair->value |= RISCV_HWPROBE_IMA_FD;
-
- if (riscv_isa_extension_available(NULL, c))
- pair->value |= RISCV_HWPROBE_IMA_C;
-
+ hwprobe_isa_ext0(pair, cpus);
break;
case RISCV_HWPROBE_KEY_CPUPERF_0:
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
2023-05-09 18:25 ` Evan Green
@ 2023-05-09 18:29 ` Conor Dooley
-1 siblings, 0 replies; 26+ messages in thread
From: Conor Dooley @ 2023-05-09 18:29 UTC (permalink / raw)
To: Evan Green
Cc: Palmer Dabbelt, Andrew Jones, Albert Ou, Anup Patel,
Conor Dooley, Heiko Stuebner, Jisheng Zhang, Palmer Dabbelt,
Paul Walmsley, Sunil V L, linux-kernel, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 2897 bytes --]
On Tue, May 09, 2023 at 11:25:01AM -0700, Evan Green wrote:
> Add the Zba address bit manipulation extension and Zbs single bit
> instructions extension into those the kernel is aware of and maintains
> in its riscv_isa bitmap.
>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Given you added the lads, rather than ignoring them due to the Zbs
change, I think you forgot my R-b from v1?
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
>
> ---
>
> Changes in v2:
> - Add Zbs as well
>
> arch/riscv/include/asm/hwcap.h | 2 ++
> arch/riscv/kernel/cpu.c | 2 ++
> arch/riscv/kernel/cpufeature.c | 2 ++
> 3 files changed, 6 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index e0c40a4c63d5..6b2e8ff4638c 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -46,6 +46,8 @@
> #define RISCV_ISA_EXT_ZICBOZ 34
> #define RISCV_ISA_EXT_SMAIA 35
> #define RISCV_ISA_EXT_SSAIA 36
> +#define RISCV_ISA_EXT_ZBA 37
> +#define RISCV_ISA_EXT_ZBS 38
>
> #define RISCV_ISA_EXT_MAX 64
Heh, gonna start getting tight on bits here soonish :)
> #define RISCV_ISA_EXT_NAME_LEN_MAX 32
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index c96aa56cf1c7..bd294364390d 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -184,7 +184,9 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
> __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index b1d6b7e4b829..a1954c83638f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -236,7 +236,9 @@ void __init riscv_fill_hwcap(void)
> SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
> SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
> SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
> + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
> SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
> + SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
> SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
> SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
> SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
@ 2023-05-09 18:29 ` Conor Dooley
0 siblings, 0 replies; 26+ messages in thread
From: Conor Dooley @ 2023-05-09 18:29 UTC (permalink / raw)
To: Evan Green
Cc: Anup Patel, Albert Ou, linux-kernel, Palmer Dabbelt,
Conor Dooley, Palmer Dabbelt, Jisheng Zhang, Paul Walmsley,
linux-riscv, Heiko Stuebner, Andrew Jones
[-- Attachment #1.1: Type: text/plain, Size: 2897 bytes --]
On Tue, May 09, 2023 at 11:25:01AM -0700, Evan Green wrote:
> Add the Zba address bit manipulation extension and Zbs single bit
> instructions extension into those the kernel is aware of and maintains
> in its riscv_isa bitmap.
>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Given you added the lads, rather than ignoring them due to the Zbs
change, I think you forgot my R-b from v1?
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
>
> ---
>
> Changes in v2:
> - Add Zbs as well
>
> arch/riscv/include/asm/hwcap.h | 2 ++
> arch/riscv/kernel/cpu.c | 2 ++
> arch/riscv/kernel/cpufeature.c | 2 ++
> 3 files changed, 6 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index e0c40a4c63d5..6b2e8ff4638c 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -46,6 +46,8 @@
> #define RISCV_ISA_EXT_ZICBOZ 34
> #define RISCV_ISA_EXT_SMAIA 35
> #define RISCV_ISA_EXT_SSAIA 36
> +#define RISCV_ISA_EXT_ZBA 37
> +#define RISCV_ISA_EXT_ZBS 38
>
> #define RISCV_ISA_EXT_MAX 64
Heh, gonna start getting tight on bits here soonish :)
> #define RISCV_ISA_EXT_NAME_LEN_MAX 32
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index c96aa56cf1c7..bd294364390d 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -184,7 +184,9 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
> __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index b1d6b7e4b829..a1954c83638f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -236,7 +236,9 @@ void __init riscv_fill_hwcap(void)
> SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
> SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
> SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
> + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
> SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
> + SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
> SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
> SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
> SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
> --
> 2.25.1
>
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
2023-05-09 18:25 ` Evan Green
@ 2023-05-09 18:33 ` Conor Dooley
-1 siblings, 0 replies; 26+ messages in thread
From: Conor Dooley @ 2023-05-09 18:33 UTC (permalink / raw)
To: Evan Green
Cc: Palmer Dabbelt, Andrew Jones, Albert Ou, Andrew Bresticker,
Celeste Liu, Conor Dooley, Heiko Stuebner, Jonathan Corbet,
Palmer Dabbelt, Paul Walmsley, linux-doc, linux-kernel,
linux-riscv
[-- Attachment #1: Type: text/plain, Size: 502 bytes --]
On Tue, May 09, 2023 at 11:25:03AM -0700, Evan Green wrote:
> + if (riscv_isa_extension_available(isainfo->isa, ZBA))
> + pair->value |= RISCV_HWPROBE_EXT_ZBA;
> + else
> + missing |= RISCV_HWPROBE_EXT_ZBA;
Part of me wonders if we should just have a macro for this, since it's
just boilerplate w/ the only "variable" being the extension name.
Just a thought, and we'll have plenty more cracks at changing things
here, so:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
@ 2023-05-09 18:33 ` Conor Dooley
0 siblings, 0 replies; 26+ messages in thread
From: Conor Dooley @ 2023-05-09 18:33 UTC (permalink / raw)
To: Evan Green
Cc: Palmer Dabbelt, Andrew Jones, Albert Ou, Andrew Bresticker,
Celeste Liu, Conor Dooley, Heiko Stuebner, Jonathan Corbet,
Palmer Dabbelt, Paul Walmsley, linux-doc, linux-kernel,
linux-riscv
[-- Attachment #1.1: Type: text/plain, Size: 502 bytes --]
On Tue, May 09, 2023 at 11:25:03AM -0700, Evan Green wrote:
> + if (riscv_isa_extension_available(isainfo->isa, ZBA))
> + pair->value |= RISCV_HWPROBE_EXT_ZBA;
> + else
> + missing |= RISCV_HWPROBE_EXT_ZBA;
Part of me wonders if we should just have a macro for this, since it's
just boilerplate w/ the only "variable" being the extension name.
Just a thought, and we'll have plenty more cracks at changing things
here, so:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
2023-05-09 18:29 ` Conor Dooley
@ 2023-05-09 18:34 ` Evan Green
-1 siblings, 0 replies; 26+ messages in thread
From: Evan Green @ 2023-05-09 18:34 UTC (permalink / raw)
To: Conor Dooley
Cc: Palmer Dabbelt, Andrew Jones, Albert Ou, Anup Patel,
Conor Dooley, Heiko Stuebner, Jisheng Zhang, Palmer Dabbelt,
Paul Walmsley, Sunil V L, linux-kernel, linux-riscv
On Tue, May 9, 2023 at 11:29 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, May 09, 2023 at 11:25:01AM -0700, Evan Green wrote:
> > Add the Zba address bit manipulation extension and Zbs single bit
> > instructions extension into those the kernel is aware of and maintains
> > in its riscv_isa bitmap.
> >
> > Signed-off-by: Evan Green <evan@rivosinc.com>
> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> > Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Given you added the lads, rather than ignoring them due to the Zbs
> change, I think you forgot my R-b from v1?
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Whoops, yes I did. Sorry about that, and thanks for the review!
>
> Cheers,
> Conor.
>
> >
> > ---
> >
> > Changes in v2:
> > - Add Zbs as well
> >
> > arch/riscv/include/asm/hwcap.h | 2 ++
> > arch/riscv/kernel/cpu.c | 2 ++
> > arch/riscv/kernel/cpufeature.c | 2 ++
> > 3 files changed, 6 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index e0c40a4c63d5..6b2e8ff4638c 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -46,6 +46,8 @@
> > #define RISCV_ISA_EXT_ZICBOZ 34
> > #define RISCV_ISA_EXT_SMAIA 35
> > #define RISCV_ISA_EXT_SSAIA 36
> > +#define RISCV_ISA_EXT_ZBA 37
> > +#define RISCV_ISA_EXT_ZBS 38
> >
> > #define RISCV_ISA_EXT_MAX 64
>
> Heh, gonna start getting tight on bits here soonish :)
Yeah they're flying in, I had to update mine since SMAIA swooshed in.
-Evan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
@ 2023-05-09 18:34 ` Evan Green
0 siblings, 0 replies; 26+ messages in thread
From: Evan Green @ 2023-05-09 18:34 UTC (permalink / raw)
To: Conor Dooley
Cc: Anup Patel, Albert Ou, linux-kernel, Palmer Dabbelt,
Conor Dooley, Palmer Dabbelt, Jisheng Zhang, Paul Walmsley,
linux-riscv, Heiko Stuebner, Andrew Jones
On Tue, May 9, 2023 at 11:29 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, May 09, 2023 at 11:25:01AM -0700, Evan Green wrote:
> > Add the Zba address bit manipulation extension and Zbs single bit
> > instructions extension into those the kernel is aware of and maintains
> > in its riscv_isa bitmap.
> >
> > Signed-off-by: Evan Green <evan@rivosinc.com>
> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> > Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Given you added the lads, rather than ignoring them due to the Zbs
> change, I think you forgot my R-b from v1?
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Whoops, yes I did. Sorry about that, and thanks for the review!
>
> Cheers,
> Conor.
>
> >
> > ---
> >
> > Changes in v2:
> > - Add Zbs as well
> >
> > arch/riscv/include/asm/hwcap.h | 2 ++
> > arch/riscv/kernel/cpu.c | 2 ++
> > arch/riscv/kernel/cpufeature.c | 2 ++
> > 3 files changed, 6 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index e0c40a4c63d5..6b2e8ff4638c 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -46,6 +46,8 @@
> > #define RISCV_ISA_EXT_ZICBOZ 34
> > #define RISCV_ISA_EXT_SMAIA 35
> > #define RISCV_ISA_EXT_SSAIA 36
> > +#define RISCV_ISA_EXT_ZBA 37
> > +#define RISCV_ISA_EXT_ZBS 38
> >
> > #define RISCV_ISA_EXT_MAX 64
>
> Heh, gonna start getting tight on bits here soonish :)
Yeah they're flying in, I had to update mine since SMAIA swooshed in.
-Evan
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
2023-05-09 18:25 ` Evan Green
@ 2023-05-10 14:45 ` Heiko Stübner
-1 siblings, 0 replies; 26+ messages in thread
From: Heiko Stübner @ 2023-05-10 14:45 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Cc: Anup Patel, Albert Ou, linux-kernel, Conor Dooley, Evan Green,
Palmer Dabbelt, Jisheng Zhang, Paul Walmsley, linux-riscv,
Andrew Jones, Evan Green
Am Dienstag, 9. Mai 2023, 20:25:01 CEST schrieb Evan Green:
> Add the Zba address bit manipulation extension and Zbs single bit
> instructions extension into those the kernel is aware of and maintains
> in its riscv_isa bitmap.
>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
@ 2023-05-10 14:45 ` Heiko Stübner
0 siblings, 0 replies; 26+ messages in thread
From: Heiko Stübner @ 2023-05-10 14:45 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Cc: Anup Patel, Albert Ou, linux-kernel, Conor Dooley, Evan Green,
Palmer Dabbelt, Jisheng Zhang, Paul Walmsley, linux-riscv,
Andrew Jones, Evan Green
Am Dienstag, 9. Mai 2023, 20:25:01 CEST schrieb Evan Green:
> Add the Zba address bit manipulation extension and Zbs single bit
> instructions extension into those the kernel is aware of and maintains
> in its riscv_isa bitmap.
>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
2023-05-09 18:25 ` Evan Green
@ 2023-05-10 14:47 ` Heiko Stübner
-1 siblings, 0 replies; 26+ messages in thread
From: Heiko Stübner @ 2023-05-10 14:47 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Cc: Evan Green, Andrew Jones, Albert Ou, Andrew Bresticker,
Celeste Liu, Conor Dooley, Jonathan Corbet, Palmer Dabbelt,
Paul Walmsley, linux-doc, linux-kernel, linux-riscv, Evan Green
Am Dienstag, 9. Mai 2023, 20:25:03 CEST schrieb Evan Green:
> Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
> These are accurately reported per CPU.
>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
though a part of me wonders, what happened to Zbc ;-)
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
@ 2023-05-10 14:47 ` Heiko Stübner
0 siblings, 0 replies; 26+ messages in thread
From: Heiko Stübner @ 2023-05-10 14:47 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Cc: Evan Green, Andrew Jones, Albert Ou, Andrew Bresticker,
Celeste Liu, Conor Dooley, Jonathan Corbet, Palmer Dabbelt,
Paul Walmsley, linux-doc, linux-kernel, linux-riscv, Evan Green
Am Dienstag, 9. Mai 2023, 20:25:03 CEST schrieb Evan Green:
> Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
> These are accurately reported per CPU.
>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
though a part of me wonders, what happened to Zbc ;-)
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe
2023-05-09 18:25 ` Evan Green
@ 2023-06-19 22:07 ` Palmer Dabbelt
-1 siblings, 0 replies; 26+ messages in thread
From: Palmer Dabbelt @ 2023-06-19 22:07 UTC (permalink / raw)
To: Evan Green
Cc: Albert Ou, Andrew Bresticker, Andrew Jones, Anup Patel,
Celeste Liu, Conor Dooley, Heiko Stuebner, Jisheng Zhang,
Jonathan Corbet, Palmer Dabbelt, Paul Walmsley, Sunil V L,
linux-doc, linux-kernel, linux-riscv
On Tue, 09 May 2023 11:25:00 -0700, Evan Green wrote:
> This change detects the presence of Zba, Zbb, and Zbs extensions and exports
> them per-hart to userspace via the hwprobe mechanism. Glibc can then use
> these in setting up hwcaps-based library search paths.
>
> There's a little bit of extra housekeeping here: the first change adds
> Zba and Zbs to the set of extensions the kernel recognizes, and the second
> change starts tracking ISA features per-hart (in addition to the ANDed
> mask of features across all harts which the kernel uses to make
> decisions). Now that we track the ISA information per-hart, we could
> even fix up /proc/cpuinfo to accurately report extension per-hart,
> though I've left that out of this series for now.
>
> [...]
Applied, thanks!
[1/3] RISC-V: Add Zba, Zbs extension probing
https://git.kernel.org/palmer/c/c6699baf1064
[2/3] RISC-V: Track ISA extensions per hart
https://git.kernel.org/palmer/c/82e9c66e81c8
[3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
https://git.kernel.org/palmer/c/c0baf321038d
Best regards,
--
Palmer Dabbelt <palmer@rivosinc.com>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe
@ 2023-06-19 22:07 ` Palmer Dabbelt
0 siblings, 0 replies; 26+ messages in thread
From: Palmer Dabbelt @ 2023-06-19 22:07 UTC (permalink / raw)
To: Evan Green
Cc: Anup Patel, Albert Ou, Jonathan Corbet, Andrew Bresticker,
linux-doc, linux-kernel, Conor Dooley, Celeste Liu,
Jisheng Zhang, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Heiko Stuebner, Andrew Jones
On Tue, 09 May 2023 11:25:00 -0700, Evan Green wrote:
> This change detects the presence of Zba, Zbb, and Zbs extensions and exports
> them per-hart to userspace via the hwprobe mechanism. Glibc can then use
> these in setting up hwcaps-based library search paths.
>
> There's a little bit of extra housekeeping here: the first change adds
> Zba and Zbs to the set of extensions the kernel recognizes, and the second
> change starts tracking ISA features per-hart (in addition to the ANDed
> mask of features across all harts which the kernel uses to make
> decisions). Now that we track the ISA information per-hart, we could
> even fix up /proc/cpuinfo to accurately report extension per-hart,
> though I've left that out of this series for now.
>
> [...]
Applied, thanks!
[1/3] RISC-V: Add Zba, Zbs extension probing
https://git.kernel.org/palmer/c/c6699baf1064
[2/3] RISC-V: Track ISA extensions per hart
https://git.kernel.org/palmer/c/82e9c66e81c8
[3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
https://git.kernel.org/palmer/c/c0baf321038d
Best regards,
--
Palmer Dabbelt <palmer@rivosinc.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
2023-05-10 14:45 ` Heiko Stübner
@ 2023-06-19 23:44 ` Palmer Dabbelt
-1 siblings, 0 replies; 26+ messages in thread
From: Palmer Dabbelt @ 2023-06-19 23:44 UTC (permalink / raw)
To: heiko
Cc: linux-riscv, apatel, aou, linux-kernel, Conor Dooley, Evan Green,
jszhang, Paul Walmsley, linux-riscv, ajones, Evan Green
On Wed, 10 May 2023 07:45:50 PDT (-0700), heiko@sntech.de wrote:
> Am Dienstag, 9. Mai 2023, 20:25:01 CEST schrieb Evan Green:
>> Add the Zba address bit manipulation extension and Zbs single bit
>> instructions extension into those the kernel is aware of and maintains
>> in its riscv_isa bitmap.
>>
>> Signed-off-by: Evan Green <evan@rivosinc.com>
>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Just FYI: b4 is giving me this
NOTE: some trailers ignored due to from/email mismatches:
! Trailer: Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Msg From: Heiko Stübner <heiko@sntech.de>
NOTE: Rerun with -S to apply them anyway
I added it. No big deal on my end, I also send email from random addresses
that are different from my trailers. It's just the first time I remember b4
saying something.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
@ 2023-06-19 23:44 ` Palmer Dabbelt
0 siblings, 0 replies; 26+ messages in thread
From: Palmer Dabbelt @ 2023-06-19 23:44 UTC (permalink / raw)
To: heiko
Cc: linux-riscv, apatel, aou, linux-kernel, Conor Dooley, Evan Green,
jszhang, Paul Walmsley, linux-riscv, ajones, Evan Green
On Wed, 10 May 2023 07:45:50 PDT (-0700), heiko@sntech.de wrote:
> Am Dienstag, 9. Mai 2023, 20:25:01 CEST schrieb Evan Green:
>> Add the Zba address bit manipulation extension and Zbs single bit
>> instructions extension into those the kernel is aware of and maintains
>> in its riscv_isa bitmap.
>>
>> Signed-off-by: Evan Green <evan@rivosinc.com>
>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Just FYI: b4 is giving me this
NOTE: some trailers ignored due to from/email mismatches:
! Trailer: Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Msg From: Heiko Stübner <heiko@sntech.de>
NOTE: Rerun with -S to apply them anyway
I added it. No big deal on my end, I also send email from random addresses
that are different from my trailers. It's just the first time I remember b4
saying something.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
2023-05-10 14:47 ` Heiko Stübner
@ 2023-06-19 23:55 ` Palmer Dabbelt
-1 siblings, 0 replies; 26+ messages in thread
From: Palmer Dabbelt @ 2023-06-19 23:55 UTC (permalink / raw)
To: heiko
Cc: linux-riscv, Evan Green, ajones, aou, abrestic, coelacanthus,
Conor Dooley, corbet, Paul Walmsley, linux-doc, linux-kernel,
linux-riscv, Evan Green
On Wed, 10 May 2023 07:47:54 PDT (-0700), heiko@sntech.de wrote:
> Am Dienstag, 9. Mai 2023, 20:25:03 CEST schrieb Evan Green:
>> Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
>> These are accurately reported per CPU.
>>
>> Signed-off-by: Evan Green <evan@rivosinc.com>
>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
This one too.
> though a part of me wonders, what happened to Zbc ;-)
I think we all just keep forgetting about it as this round of HW has
missed out on it. If you care enough to send a patch I'm happy to pick
it up ;)
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
@ 2023-06-19 23:55 ` Palmer Dabbelt
0 siblings, 0 replies; 26+ messages in thread
From: Palmer Dabbelt @ 2023-06-19 23:55 UTC (permalink / raw)
To: heiko
Cc: linux-riscv, Evan Green, ajones, aou, abrestic, coelacanthus,
Conor Dooley, corbet, Paul Walmsley, linux-doc, linux-kernel,
linux-riscv, Evan Green
On Wed, 10 May 2023 07:47:54 PDT (-0700), heiko@sntech.de wrote:
> Am Dienstag, 9. Mai 2023, 20:25:03 CEST schrieb Evan Green:
>> Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
>> These are accurately reported per CPU.
>>
>> Signed-off-by: Evan Green <evan@rivosinc.com>
>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
This one too.
> though a part of me wonders, what happened to Zbc ;-)
I think we all just keep forgetting about it as this round of HW has
missed out on it. If you care enough to send a patch I'm happy to pick
it up ;)
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe
2023-05-09 18:25 ` Evan Green
@ 2023-06-20 1:00 ` patchwork-bot+linux-riscv
-1 siblings, 0 replies; 26+ messages in thread
From: patchwork-bot+linux-riscv @ 2023-06-20 1:00 UTC (permalink / raw)
To: Evan Green
Cc: linux-riscv, palmer, apatel, aou, corbet, abrestic, linux-doc,
linux-kernel, conor.dooley, coelacanthus, jszhang, paul.walmsley,
palmer, heiko.stuebner, ajones
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Tue, 9 May 2023 11:25:00 -0700 you wrote:
> This change detects the presence of Zba, Zbb, and Zbs extensions and exports
> them per-hart to userspace via the hwprobe mechanism. Glibc can then use
> these in setting up hwcaps-based library search paths.
>
> There's a little bit of extra housekeeping here: the first change adds
> Zba and Zbs to the set of extensions the kernel recognizes, and the second
> change starts tracking ISA features per-hart (in addition to the ANDed
> mask of features across all harts which the kernel uses to make
> decisions). Now that we track the ISA information per-hart, we could
> even fix up /proc/cpuinfo to accurately report extension per-hart,
> though I've left that out of this series for now.
>
> [...]
Here is the summary with links:
- [v2,1/3] RISC-V: Add Zba, Zbs extension probing
https://git.kernel.org/riscv/c/c6699baf1064
- [v2,2/3] RISC-V: Track ISA extensions per hart
https://git.kernel.org/riscv/c/82e9c66e81c8
- [v2,3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
https://git.kernel.org/riscv/c/c0baf321038d
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe
@ 2023-06-20 1:00 ` patchwork-bot+linux-riscv
0 siblings, 0 replies; 26+ messages in thread
From: patchwork-bot+linux-riscv @ 2023-06-20 1:00 UTC (permalink / raw)
To: Evan Green
Cc: linux-riscv, palmer, apatel, aou, corbet, abrestic, linux-doc,
linux-kernel, conor.dooley, coelacanthus, jszhang, paul.walmsley,
palmer, heiko.stuebner, ajones
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Tue, 9 May 2023 11:25:00 -0700 you wrote:
> This change detects the presence of Zba, Zbb, and Zbs extensions and exports
> them per-hart to userspace via the hwprobe mechanism. Glibc can then use
> these in setting up hwcaps-based library search paths.
>
> There's a little bit of extra housekeeping here: the first change adds
> Zba and Zbs to the set of extensions the kernel recognizes, and the second
> change starts tracking ISA features per-hart (in addition to the ANDed
> mask of features across all harts which the kernel uses to make
> decisions). Now that we track the ISA information per-hart, we could
> even fix up /proc/cpuinfo to accurately report extension per-hart,
> though I've left that out of this series for now.
>
> [...]
Here is the summary with links:
- [v2,1/3] RISC-V: Add Zba, Zbs extension probing
https://git.kernel.org/riscv/c/c6699baf1064
- [v2,2/3] RISC-V: Track ISA extensions per hart
https://git.kernel.org/riscv/c/82e9c66e81c8
- [v2,3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
https://git.kernel.org/riscv/c/c0baf321038d
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2023-06-20 1:00 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-09 18:25 [PATCH v2 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Evan Green
2023-05-09 18:25 ` Evan Green
2023-05-09 18:25 ` [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing Evan Green
2023-05-09 18:25 ` Evan Green
2023-05-09 18:29 ` Conor Dooley
2023-05-09 18:29 ` Conor Dooley
2023-05-09 18:34 ` Evan Green
2023-05-09 18:34 ` Evan Green
2023-05-10 14:45 ` Heiko Stübner
2023-05-10 14:45 ` Heiko Stübner
2023-06-19 23:44 ` Palmer Dabbelt
2023-06-19 23:44 ` Palmer Dabbelt
2023-05-09 18:25 ` [PATCH v2 2/3] RISC-V: Track ISA extensions per hart Evan Green
2023-05-09 18:25 ` Evan Green
2023-05-09 18:25 ` [PATCH v2 3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs Evan Green
2023-05-09 18:25 ` Evan Green
2023-05-09 18:33 ` Conor Dooley
2023-05-09 18:33 ` Conor Dooley
2023-05-10 14:47 ` Heiko Stübner
2023-05-10 14:47 ` Heiko Stübner
2023-06-19 23:55 ` Palmer Dabbelt
2023-06-19 23:55 ` Palmer Dabbelt
2023-06-19 22:07 ` [PATCH v2 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Palmer Dabbelt
2023-06-19 22:07 ` Palmer Dabbelt
2023-06-20 1:00 ` patchwork-bot+linux-riscv
2023-06-20 1:00 ` patchwork-bot+linux-riscv
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