[PATCH 0/4] Add Video Clock Controller driver for SM8550

[PATCH 0/4] Add Video Clock Controller driver for SM8550

[Jagadeesh Kona]

Add bindings, driver and DT node for video clock controller on SM8550.
Also, add support for lucid ole pll ops.

Jagadeesh Kona (3):
  dt-bindings: clock: qcom: Add SM8550 video clock controller
  clk: qcom: videocc-sm8550: Add video clock controller driver for
    SM8550
  arm64: dts: qcom: sm8550: Add video clock controller

Taniya Das (1):
  clk: qcom: clk-alpha-pll: Add support for lucid ole pll ops

 .../bindings/clock/qcom,sm8550-videocc.yaml   |  77 +++
 arch/arm64/boot/dts/qcom/sm8550.dtsi          |  12 +
 drivers/clk/qcom/Kconfig                      |  10 +
 drivers/clk/qcom/Makefile                     |   1 +
 drivers/clk/qcom/clk-alpha-pll.c              |   2 +
 drivers/clk/qcom/clk-alpha-pll.h              |   4 +
 drivers/clk/qcom/videocc-sm8550.c             | 468 ++++++++++++++++++
 .../dt-bindings/clock/qcom,sm8550-videocc.h   |  38 ++
 8 files changed, 612 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml
 create mode 100644 drivers/clk/qcom/videocc-sm8550.c
 create mode 100644 include/dt-bindings/clock/qcom,sm8550-videocc.h

-- 
2.25.1

[PATCH 1/4] clk: qcom: clk-alpha-pll: Add support for lucid ole pll ops

[Jagadeesh Kona]

From: Taniya Das <quic_tdas@quicinc.com>

Add support for lucid ole pll ops to configure and control the
lucid ole pll. The lucid ole pll has an additional test control
register which is required to be programmed, add support to
program the same.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
 drivers/clk/qcom/clk-alpha-pll.c | 2 ++
 drivers/clk/qcom/clk-alpha-pll.h | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index b9f6535a7ba7..f81c7c561352 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -55,6 +55,7 @@
 #define PLL_TEST_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
 #define PLL_TEST_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
 #define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
+#define PLL_TEST_CTL_U2(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
 #define PLL_STATUS(p)		((p)->offset + (p)->regs[PLL_OFF_STATUS])
 #define PLL_OPMODE(p)		((p)->offset + (p)->regs[PLL_OFF_OPMODE])
 #define PLL_FRAC(p)		((p)->offset + (p)->regs[PLL_OFF_FRAC])
@@ -2096,6 +2097,7 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
 	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
+	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
 
 	/* Disable PLL output */
 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index d07b17186b90..4d9b6d5b7062 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -125,6 +125,7 @@ struct alpha_pll_config {
 	u32 test_ctl_val;
 	u32 test_ctl_hi_val;
 	u32 test_ctl_hi1_val;
+	u32 test_ctl_hi2_val;
 	u32 main_output_mask;
 	u32 aux_output_mask;
 	u32 aux2_output_mask;
@@ -171,6 +172,7 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
 
 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
+#define clk_alpha_pll_lucid_ole_ops clk_alpha_pll_lucid_evo_ops
 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
 #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
@@ -196,6 +198,8 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 			     const struct alpha_pll_config *config);
 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 				 const struct alpha_pll_config *config);
+#define clk_lucid_ole_pll_configure(pll, regmap, config) \
+			clk_lucid_evo_pll_configure(pll, regmap, config)
 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 				  const struct alpha_pll_config *config);
 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
-- 
2.25.1

[PATCH 2/4] dt-bindings: clock: qcom: Add SM8550 video clock controller

[Jagadeesh Kona]

Add device tree bindings for the video clock controller on Qualcomm
SM8550 platform.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 .../bindings/clock/qcom,sm8550-videocc.yaml   | 77 +++++++++++++++++++
 .../dt-bindings/clock/qcom,sm8550-videocc.h   | 38 +++++++++
 2 files changed, 115 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml
 create mode 100644 include/dt-bindings/clock/qcom,sm8550-videocc.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml
new file mode 100644
index 000000000000..107af5e9af89
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8550-videocc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Video Clock & Reset Controller on SM8550
+
+maintainers:
+  - Jagadeesh Kona <quic_jkona@quicinc.com>
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm video clock control module provides the clocks, resets and power
+  domains on SM8550.
+
+  See also:: include/dt-bindings/clock/qcom,videocc-sm8550.h
+
+properties:
+  compatible:
+    const: qcom,sm8550-videocc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Video AHB clock from GCC
+
+  power-domains:
+    maxItems: 1
+    description:
+      MMCX power domain.
+
+  required-opps:
+    maxItems: 1
+    description:
+      A phandle to an OPP node describing required MMCX performance point.
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - power-domains
+  - required-opps
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+    videocc: clock-controller@aaf0000 {
+      compatible = "qcom,sm8550-videocc";
+      reg = <0x0aaf0000 0x10000>;
+      clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>;
+      power-domains = <&rpmhpd SM8550_MMCX>;
+      required-opps = <&rpmhpd_opp_low_svs>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/clock/qcom,sm8550-videocc.h b/include/dt-bindings/clock/qcom,sm8550-videocc.h
new file mode 100644
index 000000000000..ee5efb5be9a8
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8550-videocc.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8550_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8550_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_PLL0						0
+#define VIDEO_CC_PLL1						1
+#define VIDEO_CC_MVS0_CLK					2
+#define VIDEO_CC_MVS0_CLK_SRC					3
+#define VIDEO_CC_MVS0_DIV_CLK_SRC				4
+#define VIDEO_CC_MVS0C_CLK					5
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC				6
+#define VIDEO_CC_MVS1_CLK					7
+#define VIDEO_CC_MVS1_CLK_SRC					8
+#define VIDEO_CC_MVS1_DIV_CLK_SRC				9
+#define VIDEO_CC_MVS1C_CLK					10
+#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC				11
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0C_GDSC					0
+#define VIDEO_CC_MVS0_GDSC					1
+#define VIDEO_CC_MVS1C_GDSC					2
+#define VIDEO_CC_MVS1_GDSC					3
+
+/* VIDEO_CC resets */
+#define CVP_VIDEO_CC_INTERFACE_BCR				0
+#define CVP_VIDEO_CC_MVS0_BCR					1
+#define CVP_VIDEO_CC_MVS0C_BCR					2
+#define CVP_VIDEO_CC_MVS1_BCR					3
+#define CVP_VIDEO_CC_MVS1C_BCR					4
+#define VIDEO_CC_MVS0C_CLK_ARES					5
+#define VIDEO_CC_MVS1C_CLK_ARES					6
+
+#endif
-- 
2.25.1

[PATCH 3/4] clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550

[Jagadeesh Kona]

Add support for the video clock controller for video clients to be able
to request for videocc clocks on SM8550 platform.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 drivers/clk/qcom/Kconfig          |  10 +
 drivers/clk/qcom/Makefile         |   1 +
 drivers/clk/qcom/videocc-sm8550.c | 468 ++++++++++++++++++++++++++++++
 3 files changed, 479 insertions(+)
 create mode 100644 drivers/clk/qcom/videocc-sm8550.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 12be3e2371b3..6bb9b4aff047 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -925,6 +925,16 @@ config SM_VIDEOCC_8250
 	  Say Y if you want to support video devices and functionality such as
 	  video encode and decode.
 
+config SM_VIDEOCC_8550
+	tristate "SM8550 Video Clock Controller"
+	select SM_GCC_8550
+	select QCOM_GDSC
+	help
+	  Support for the video clock controller on Qualcomm Technologies, Inc.
+	  SM8550 devices.
+	  Say Y if you want to support video devices and functionality such as
+	  video encode/decode.
+
 config SPMI_PMIC_CLKDIV
 	tristate "SPMI PMIC clkdiv Support"
 	depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 9ff4c373ad95..f0b95fc217aa 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -127,6 +127,7 @@ obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
 obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
 obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
 obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
+obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
new file mode 100644
index 000000000000..10e4b2725ddf
--- /dev/null
+++ b/drivers/clk/qcom/videocc-sm8550.c
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,sm8550-videocc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+	DT_BI_TCXO,
+};
+
+enum {
+	P_BI_TCXO,
+	P_VIDEO_CC_PLL0_OUT_MAIN,
+	P_VIDEO_CC_PLL1_OUT_MAIN,
+};
+
+static const struct pll_vco lucid_ole_vco[] = {
+	{ 249600000, 2300000000, 0 },
+};
+
+static const struct alpha_pll_config video_cc_pll0_config = {
+	.l = 0x44000025,
+	.alpha = 0x8000,
+	.config_ctl_val = 0x20485699,
+	.config_ctl_hi_val = 0x00182261,
+	.config_ctl_hi1_val = 0x82aa299c,
+	.test_ctl_val = 0x00000000,
+	.test_ctl_hi_val = 0x00000003,
+	.test_ctl_hi1_val = 0x00009000,
+	.test_ctl_hi2_val = 0x00000034,
+	.user_ctl_val = 0x00000000,
+	.user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll video_cc_pll0 = {
+	.offset = 0x0,
+	.vco_table = lucid_ole_vco,
+	.num_vco = ARRAY_SIZE(lucid_ole_vco),
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "video_cc_pll0",
+			.parent_data = &(const struct clk_parent_data) {
+				.index = DT_BI_TCXO,
+			},
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_lucid_ole_ops,
+		},
+	},
+};
+
+static const struct alpha_pll_config video_cc_pll1_config = {
+	.l = 0x44000036,
+	.alpha = 0xb000,
+	.config_ctl_val = 0x20485699,
+	.config_ctl_hi_val = 0x00182261,
+	.config_ctl_hi1_val = 0x82aa299c,
+	.test_ctl_val = 0x00000000,
+	.test_ctl_hi_val = 0x00000003,
+	.test_ctl_hi1_val = 0x00009000,
+	.test_ctl_hi2_val = 0x00000034,
+	.user_ctl_val = 0x00000000,
+	.user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll video_cc_pll1 = {
+	.offset = 0x1000,
+	.vco_table = lucid_ole_vco,
+	.num_vco = ARRAY_SIZE(lucid_ole_vco),
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "video_cc_pll1",
+			.parent_data = &(const struct clk_parent_data) {
+				.index = DT_BI_TCXO,
+			},
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_lucid_ole_ops,
+		},
+	},
+};
+
+static const struct parent_map video_cc_parent_map_0[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_0[] = {
+	{ .index = DT_BI_TCXO },
+	{ .hw = &video_cc_pll0.clkr.hw },
+};
+
+static const struct parent_map video_cc_parent_map_1[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_1[] = {
+	{ .index = DT_BI_TCXO },
+	{ .hw = &video_cc_pll1.clkr.hw },
+};
+
+static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
+	F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 video_cc_mvs0_clk_src = {
+	.cmd_rcgr = 0x8000,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = video_cc_parent_map_0,
+	.freq_tbl = ftbl_video_cc_mvs0_clk_src,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "video_cc_mvs0_clk_src",
+		.parent_data = video_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_rcg2_shared_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
+	F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
+	F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
+	F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
+	F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 video_cc_mvs1_clk_src = {
+	.cmd_rcgr = 0x8018,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = video_cc_parent_map_1,
+	.freq_tbl = ftbl_video_cc_mvs1_clk_src,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "video_cc_mvs1_clk_src",
+		.parent_data = video_cc_parent_data_1,
+		.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_rcg2_shared_ops,
+	},
+};
+
+static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
+	.reg = 0x80c4,
+	.shift = 0,
+	.width = 4,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "video_cc_mvs0_div_clk_src",
+		.parent_hws = (const struct clk_hw*[]) {
+			&video_cc_mvs0_clk_src.clkr.hw,
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_regmap_div_ro_ops,
+	},
+};
+
+static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
+	.reg = 0x8070,
+	.shift = 0,
+	.width = 4,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "video_cc_mvs0c_div2_div_clk_src",
+		.parent_hws = (const struct clk_hw*[]) {
+			&video_cc_mvs0_clk_src.clkr.hw,
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_regmap_div_ro_ops,
+	},
+};
+
+static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
+	.reg = 0x80ec,
+	.shift = 0,
+	.width = 4,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "video_cc_mvs1_div_clk_src",
+		.parent_hws = (const struct clk_hw*[]) {
+			&video_cc_mvs1_clk_src.clkr.hw,
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_regmap_div_ro_ops,
+	},
+};
+
+static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
+	.reg = 0x809c,
+	.shift = 0,
+	.width = 4,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "video_cc_mvs1c_div2_div_clk_src",
+		.parent_hws = (const struct clk_hw*[]) {
+			&video_cc_mvs1_clk_src.clkr.hw,
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_regmap_div_ro_ops,
+	},
+};
+
+static struct clk_branch video_cc_mvs0_clk = {
+	.halt_reg = 0x80b8,
+	.halt_check = BRANCH_HALT_SKIP,
+	.hwcg_reg = 0x80b8,
+	.hwcg_bit = 1,
+	.clkr = {
+		.enable_reg = 0x80b8,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "video_cc_mvs0_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&video_cc_mvs0_div_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_mvs0c_clk = {
+	.halt_reg = 0x8064,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x8064,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "video_cc_mvs0c_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_mvs1_clk = {
+	.halt_reg = 0x80e0,
+	.halt_check = BRANCH_HALT_SKIP,
+	.hwcg_reg = 0x80e0,
+	.hwcg_bit = 1,
+	.clkr = {
+		.enable_reg = 0x80e0,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "video_cc_mvs1_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&video_cc_mvs1_div_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch video_cc_mvs1c_clk = {
+	.halt_reg = 0x8090,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x8090,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "video_cc_mvs1c_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct gdsc video_cc_mvs0c_gdsc = {
+	.gdscr = 0x804c,
+	.en_rest_wait_val = 0x2,
+	.en_few_wait_val = 0x2,
+	.clk_dis_wait_val = 0x6,
+	.pd = {
+		.name = "video_cc_mvs0c_gdsc",
+	},
+	.pwrsts = PWRSTS_OFF_ON,
+	.flags = RETAIN_FF_ENABLE,
+};
+
+static struct gdsc video_cc_mvs0_gdsc = {
+	.gdscr = 0x80a4,
+	.en_rest_wait_val = 0x2,
+	.en_few_wait_val = 0x2,
+	.clk_dis_wait_val = 0x6,
+	.pd = {
+		.name = "video_cc_mvs0_gdsc",
+	},
+	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &video_cc_mvs0c_gdsc.pd,
+	.flags = RETAIN_FF_ENABLE | HW_CTRL,
+};
+
+static struct gdsc video_cc_mvs1c_gdsc = {
+	.gdscr = 0x8078,
+	.en_rest_wait_val = 0x2,
+	.en_few_wait_val = 0x2,
+	.clk_dis_wait_val = 0x6,
+	.pd = {
+		.name = "video_cc_mvs1c_gdsc",
+	},
+	.pwrsts = PWRSTS_OFF_ON,
+	.flags = RETAIN_FF_ENABLE,
+};
+
+static struct gdsc video_cc_mvs1_gdsc = {
+	.gdscr = 0x80cc,
+	.en_rest_wait_val = 0x2,
+	.en_few_wait_val = 0x2,
+	.clk_dis_wait_val = 0x6,
+	.pd = {
+		.name = "video_cc_mvs1_gdsc",
+	},
+	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &video_cc_mvs1c_gdsc.pd,
+	.flags = RETAIN_FF_ENABLE | HW_CTRL,
+};
+
+static struct clk_regmap *video_cc_sm8550_clocks[] = {
+	[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
+	[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
+	[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
+	[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
+	[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
+	[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
+	[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
+	[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
+	[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
+	[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
+	[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
+	[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
+};
+
+static struct gdsc *video_cc_sm8550_gdscs[] = {
+	[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
+	[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
+	[VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
+	[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
+};
+
+static const struct qcom_reset_map video_cc_sm8550_resets[] = {
+	[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
+	[CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
+	[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
+	[CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
+	[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
+	[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
+	[VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
+};
+
+static const struct regmap_config video_cc_sm8550_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x9f4c,
+	.fast_io = true,
+};
+
+static struct qcom_cc_desc video_cc_sm8550_desc = {
+	.config = &video_cc_sm8550_regmap_config,
+	.clks = video_cc_sm8550_clocks,
+	.num_clks = ARRAY_SIZE(video_cc_sm8550_clocks),
+	.resets = video_cc_sm8550_resets,
+	.num_resets = ARRAY_SIZE(video_cc_sm8550_resets),
+	.gdscs = video_cc_sm8550_gdscs,
+	.num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs),
+};
+
+static const struct of_device_id video_cc_sm8550_match_table[] = {
+	{ .compatible = "qcom,sm8550-videocc" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
+
+static int video_cc_sm8550_probe(struct platform_device *pdev)
+{
+	struct regmap *regmap;
+	int ret;
+
+	ret = devm_pm_runtime_enable(&pdev->dev);
+	if (ret)
+		return ret;
+
+	ret = pm_runtime_resume_and_get(&pdev->dev);
+	if (ret)
+		return ret;
+
+	regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc);
+	if (IS_ERR(regmap)) {
+		pm_runtime_put(&pdev->dev);
+		return PTR_ERR(regmap);
+	}
+
+	clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
+	clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
+
+	/*
+	 * Keep clocks always enabled:
+	 *	video_cc_ahb_clk
+	 *	video_cc_sleep_clk
+	 *	video_cc_xo_clk
+	 */
+	regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
+	regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0));
+	regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
+
+	ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
+
+	pm_runtime_put(&pdev->dev);
+
+	return ret;
+}
+
+static struct platform_driver video_cc_sm8550_driver = {
+	.probe = video_cc_sm8550_probe,
+	.driver = {
+		.name = "video_cc-sm8550",
+		.of_match_table = video_cc_sm8550_match_table,
+	},
+};
+
+static int __init video_cc_sm8550_init(void)
+{
+	return platform_driver_register(&video_cc_sm8550_driver);
+}
+subsys_initcall(video_cc_sm8550_init);
+
+static void __exit video_cc_sm8550_exit(void)
+{
+	platform_driver_unregister(&video_cc_sm8550_driver);
+}
+module_exit(video_cc_sm8550_exit);
+
+MODULE_DESCRIPTION("QTI VIDEO_CC SM8550 Driver");
+MODULE_LICENSE("GPL");
-- 
2.25.1

[PATCH 4/4] arm64: dts: qcom: sm8550: Add video clock controller

[Jagadeesh Kona]

Add device node for video clock controller on Qualcomm SM8550 platform.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 6e9bad8f6f33..e67e7c69dae6 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
+#include <dt-bindings/clock/qcom,sm8550-videocc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -759,6 +760,17 @@ gcc: clock-controller@100000 {
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 		};
 
+		videocc: clock-controller@aaf0000 {
+			compatible = "qcom,sm8550-videocc";
+			reg = <0 0x0aaf0000 0 0x10000>;
+			clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>;
+			power-domains = <&rpmhpd SM8550_MMCX>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		ipcc: mailbox@408000 {
 			compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
 			reg = <0 0x00408000 0 0x1000>;
-- 
2.25.1

Re: [PATCH 3/4] clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550

[Dmitry Baryshkov]

On Tue, 9 May 2023 at 19:14, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>
> Add support for the video clock controller for video clients to be able
> to request for videocc clocks on SM8550 platform.
>
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  drivers/clk/qcom/Kconfig          |  10 +
>  drivers/clk/qcom/Makefile         |   1 +
>  drivers/clk/qcom/videocc-sm8550.c | 468 ++++++++++++++++++++++++++++++
>  3 files changed, 479 insertions(+)
>  create mode 100644 drivers/clk/qcom/videocc-sm8550.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 12be3e2371b3..6bb9b4aff047 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -925,6 +925,16 @@ config SM_VIDEOCC_8250
>           Say Y if you want to support video devices and functionality such as
>           video encode and decode.
>
> +config SM_VIDEOCC_8550
> +       tristate "SM8550 Video Clock Controller"
> +       select SM_GCC_8550
> +       select QCOM_GDSC
> +       help
> +         Support for the video clock controller on Qualcomm Technologies, Inc.
> +         SM8550 devices.
> +         Say Y if you want to support video devices and functionality such as
> +         video encode/decode.
> +
>  config SPMI_PMIC_CLKDIV
>         tristate "SPMI PMIC clkdiv Support"
>         depends on SPMI || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 9ff4c373ad95..f0b95fc217aa 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -127,6 +127,7 @@ obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
>  obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
>  obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
>  obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
> +obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o
>  obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
>  obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
>  obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
> diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
> new file mode 100644
> index 000000000000..10e4b2725ddf
> --- /dev/null
> +++ b/drivers/clk/qcom/videocc-sm8550.c
> @@ -0,0 +1,468 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,sm8550-videocc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "common.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> +       DT_BI_TCXO,

Any additional handling for gcc_video_ahb clk? It doesn't seem to be
used as a parent. Probably you intended to use it as a pm_clk?

> +};
> +
> +enum {
> +       P_BI_TCXO,
> +       P_VIDEO_CC_PLL0_OUT_MAIN,
> +       P_VIDEO_CC_PLL1_OUT_MAIN,
> +};
> +
> +static const struct pll_vco lucid_ole_vco[] = {
> +       { 249600000, 2300000000, 0 },
> +};
> +
> +static const struct alpha_pll_config video_cc_pll0_config = {
> +       .l = 0x44000025,
> +       .alpha = 0x8000,
> +       .config_ctl_val = 0x20485699,
> +       .config_ctl_hi_val = 0x00182261,
> +       .config_ctl_hi1_val = 0x82aa299c,
> +       .test_ctl_val = 0x00000000,
> +       .test_ctl_hi_val = 0x00000003,
> +       .test_ctl_hi1_val = 0x00009000,
> +       .test_ctl_hi2_val = 0x00000034,
> +       .user_ctl_val = 0x00000000,
> +       .user_ctl_hi_val = 0x00000005,
> +};
> +
> +static struct clk_alpha_pll video_cc_pll0 = {
> +       .offset = 0x0,
> +       .vco_table = lucid_ole_vco,
> +       .num_vco = ARRAY_SIZE(lucid_ole_vco),
> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> +       .clkr = {
> +               .hw.init = &(const struct clk_init_data) {
> +                       .name = "video_cc_pll0",
> +                       .parent_data = &(const struct clk_parent_data) {
> +                               .index = DT_BI_TCXO,
> +                       },
> +                       .num_parents = 1,
> +                       .ops = &clk_alpha_pll_lucid_ole_ops,
> +               },
> +       },
> +};
> +
> +static const struct alpha_pll_config video_cc_pll1_config = {
> +       .l = 0x44000036,
> +       .alpha = 0xb000,
> +       .config_ctl_val = 0x20485699,
> +       .config_ctl_hi_val = 0x00182261,
> +       .config_ctl_hi1_val = 0x82aa299c,
> +       .test_ctl_val = 0x00000000,
> +       .test_ctl_hi_val = 0x00000003,
> +       .test_ctl_hi1_val = 0x00009000,
> +       .test_ctl_hi2_val = 0x00000034,
> +       .user_ctl_val = 0x00000000,
> +       .user_ctl_hi_val = 0x00000005,
> +};
> +
> +static struct clk_alpha_pll video_cc_pll1 = {
> +       .offset = 0x1000,
> +       .vco_table = lucid_ole_vco,
> +       .num_vco = ARRAY_SIZE(lucid_ole_vco),
> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> +       .clkr = {
> +               .hw.init = &(const struct clk_init_data) {
> +                       .name = "video_cc_pll1",
> +                       .parent_data = &(const struct clk_parent_data) {
> +                               .index = DT_BI_TCXO,
> +                       },
> +                       .num_parents = 1,
> +                       .ops = &clk_alpha_pll_lucid_ole_ops,
> +               },
> +       },
> +};
> +
> +static const struct parent_map video_cc_parent_map_0[] = {
> +       { P_BI_TCXO, 0 },
> +       { P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
> +};
> +
> +static const struct clk_parent_data video_cc_parent_data_0[] = {
> +       { .index = DT_BI_TCXO },
> +       { .hw = &video_cc_pll0.clkr.hw },
> +};
> +
> +static const struct parent_map video_cc_parent_map_1[] = {
> +       { P_BI_TCXO, 0 },
> +       { P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
> +};
> +
> +static const struct clk_parent_data video_cc_parent_data_1[] = {
> +       { .index = DT_BI_TCXO },
> +       { .hw = &video_cc_pll1.clkr.hw },
> +};
> +
> +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
> +       F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
> +       F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
> +       F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
> +       F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
> +       F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
> +       { }
> +};
> +
> +static struct clk_rcg2 video_cc_mvs0_clk_src = {
> +       .cmd_rcgr = 0x8000,
> +       .mnd_width = 0,
> +       .hid_width = 5,
> +       .parent_map = video_cc_parent_map_0,
> +       .freq_tbl = ftbl_video_cc_mvs0_clk_src,
> +       .clkr.hw.init = &(const struct clk_init_data) {
> +               .name = "video_cc_mvs0_clk_src",
> +               .parent_data = video_cc_parent_data_0,
> +               .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
> +               .flags = CLK_SET_RATE_PARENT,
> +               .ops = &clk_rcg2_shared_ops,
> +       },
> +};
> +
> +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
> +       F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
> +       F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
> +       F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
> +       F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
> +       { }
> +};
> +
> +static struct clk_rcg2 video_cc_mvs1_clk_src = {
> +       .cmd_rcgr = 0x8018,
> +       .mnd_width = 0,
> +       .hid_width = 5,
> +       .parent_map = video_cc_parent_map_1,
> +       .freq_tbl = ftbl_video_cc_mvs1_clk_src,
> +       .clkr.hw.init = &(const struct clk_init_data) {
> +               .name = "video_cc_mvs1_clk_src",
> +               .parent_data = video_cc_parent_data_1,
> +               .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
> +               .flags = CLK_SET_RATE_PARENT,
> +               .ops = &clk_rcg2_shared_ops,
> +       },
> +};
> +
> +static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
> +       .reg = 0x80c4,
> +       .shift = 0,
> +       .width = 4,
> +       .clkr.hw.init = &(const struct clk_init_data) {
> +               .name = "video_cc_mvs0_div_clk_src",
> +               .parent_hws = (const struct clk_hw*[]) {
> +                       &video_cc_mvs0_clk_src.clkr.hw,
> +               },
> +               .num_parents = 1,
> +               .flags = CLK_SET_RATE_PARENT,
> +               .ops = &clk_regmap_div_ro_ops,
> +       },
> +};
> +
> +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
> +       .reg = 0x8070,
> +       .shift = 0,
> +       .width = 4,
> +       .clkr.hw.init = &(const struct clk_init_data) {
> +               .name = "video_cc_mvs0c_div2_div_clk_src",
> +               .parent_hws = (const struct clk_hw*[]) {
> +                       &video_cc_mvs0_clk_src.clkr.hw,
> +               },
> +               .num_parents = 1,
> +               .flags = CLK_SET_RATE_PARENT,
> +               .ops = &clk_regmap_div_ro_ops,
> +       },
> +};
> +
> +static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
> +       .reg = 0x80ec,
> +       .shift = 0,
> +       .width = 4,
> +       .clkr.hw.init = &(const struct clk_init_data) {
> +               .name = "video_cc_mvs1_div_clk_src",
> +               .parent_hws = (const struct clk_hw*[]) {
> +                       &video_cc_mvs1_clk_src.clkr.hw,
> +               },
> +               .num_parents = 1,
> +               .flags = CLK_SET_RATE_PARENT,
> +               .ops = &clk_regmap_div_ro_ops,
> +       },
> +};
> +
> +static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
> +       .reg = 0x809c,
> +       .shift = 0,
> +       .width = 4,
> +       .clkr.hw.init = &(const struct clk_init_data) {
> +               .name = "video_cc_mvs1c_div2_div_clk_src",
> +               .parent_hws = (const struct clk_hw*[]) {
> +                       &video_cc_mvs1_clk_src.clkr.hw,
> +               },
> +               .num_parents = 1,
> +               .flags = CLK_SET_RATE_PARENT,
> +               .ops = &clk_regmap_div_ro_ops,
> +       },
> +};
> +
> +static struct clk_branch video_cc_mvs0_clk = {
> +       .halt_reg = 0x80b8,
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .hwcg_reg = 0x80b8,
> +       .hwcg_bit = 1,
> +       .clkr = {
> +               .enable_reg = 0x80b8,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(const struct clk_init_data) {
> +                       .name = "video_cc_mvs0_clk",
> +                       .parent_hws = (const struct clk_hw*[]) {
> +                               &video_cc_mvs0_div_clk_src.clkr.hw,
> +                       },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch video_cc_mvs0c_clk = {
> +       .halt_reg = 0x8064,
> +       .halt_check = BRANCH_HALT,
> +       .clkr = {
> +               .enable_reg = 0x8064,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(const struct clk_init_data) {
> +                       .name = "video_cc_mvs0c_clk",
> +                       .parent_hws = (const struct clk_hw*[]) {
> +                               &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
> +                       },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch video_cc_mvs1_clk = {
> +       .halt_reg = 0x80e0,
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .hwcg_reg = 0x80e0,
> +       .hwcg_bit = 1,
> +       .clkr = {
> +               .enable_reg = 0x80e0,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(const struct clk_init_data) {
> +                       .name = "video_cc_mvs1_clk",
> +                       .parent_hws = (const struct clk_hw*[]) {
> +                               &video_cc_mvs1_div_clk_src.clkr.hw,
> +                       },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch video_cc_mvs1c_clk = {
> +       .halt_reg = 0x8090,
> +       .halt_check = BRANCH_HALT,
> +       .clkr = {
> +               .enable_reg = 0x8090,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(const struct clk_init_data) {
> +                       .name = "video_cc_mvs1c_clk",
> +                       .parent_hws = (const struct clk_hw*[]) {
> +                               &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
> +                       },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct gdsc video_cc_mvs0c_gdsc = {
> +       .gdscr = 0x804c,
> +       .en_rest_wait_val = 0x2,
> +       .en_few_wait_val = 0x2,
> +       .clk_dis_wait_val = 0x6,
> +       .pd = {
> +               .name = "video_cc_mvs0c_gdsc",
> +       },
> +       .pwrsts = PWRSTS_OFF_ON,
> +       .flags = RETAIN_FF_ENABLE,
> +};
> +
> +static struct gdsc video_cc_mvs0_gdsc = {
> +       .gdscr = 0x80a4,
> +       .en_rest_wait_val = 0x2,
> +       .en_few_wait_val = 0x2,
> +       .clk_dis_wait_val = 0x6,
> +       .pd = {
> +               .name = "video_cc_mvs0_gdsc",
> +       },
> +       .pwrsts = PWRSTS_OFF_ON,
> +       .parent = &video_cc_mvs0c_gdsc.pd,
> +       .flags = RETAIN_FF_ENABLE | HW_CTRL,
> +};
> +
> +static struct gdsc video_cc_mvs1c_gdsc = {
> +       .gdscr = 0x8078,
> +       .en_rest_wait_val = 0x2,
> +       .en_few_wait_val = 0x2,
> +       .clk_dis_wait_val = 0x6,
> +       .pd = {
> +               .name = "video_cc_mvs1c_gdsc",
> +       },
> +       .pwrsts = PWRSTS_OFF_ON,
> +       .flags = RETAIN_FF_ENABLE,
> +};
> +
> +static struct gdsc video_cc_mvs1_gdsc = {
> +       .gdscr = 0x80cc,
> +       .en_rest_wait_val = 0x2,
> +       .en_few_wait_val = 0x2,
> +       .clk_dis_wait_val = 0x6,
> +       .pd = {
> +               .name = "video_cc_mvs1_gdsc",
> +       },
> +       .pwrsts = PWRSTS_OFF_ON,
> +       .parent = &video_cc_mvs1c_gdsc.pd,
> +       .flags = RETAIN_FF_ENABLE | HW_CTRL,
> +};
> +
> +static struct clk_regmap *video_cc_sm8550_clocks[] = {
> +       [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
> +       [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
> +       [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
> +       [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
> +       [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
> +       [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
> +       [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
> +       [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
> +       [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
> +       [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
> +       [VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
> +       [VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
> +};
> +
> +static struct gdsc *video_cc_sm8550_gdscs[] = {
> +       [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
> +       [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
> +       [VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
> +       [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
> +};
> +
> +static const struct qcom_reset_map video_cc_sm8550_resets[] = {
> +       [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
> +       [CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
> +       [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
> +       [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
> +       [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },

Please rename them to start with the VIDEO_CC prefix.

> +       [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
> +       [VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
> +};
> +
> +static const struct regmap_config video_cc_sm8550_regmap_config = {
> +       .reg_bits = 32,
> +       .reg_stride = 4,
> +       .val_bits = 32,
> +       .max_register = 0x9f4c,
> +       .fast_io = true,
> +};
> +
> +static struct qcom_cc_desc video_cc_sm8550_desc = {
> +       .config = &video_cc_sm8550_regmap_config,
> +       .clks = video_cc_sm8550_clocks,
> +       .num_clks = ARRAY_SIZE(video_cc_sm8550_clocks),
> +       .resets = video_cc_sm8550_resets,
> +       .num_resets = ARRAY_SIZE(video_cc_sm8550_resets),
> +       .gdscs = video_cc_sm8550_gdscs,
> +       .num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs),
> +};
> +
> +static const struct of_device_id video_cc_sm8550_match_table[] = {
> +       { .compatible = "qcom,sm8550-videocc" },
> +       { }
> +};
> +MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
> +
> +static int video_cc_sm8550_probe(struct platform_device *pdev)
> +{
> +       struct regmap *regmap;
> +       int ret;
> +
> +       ret = devm_pm_runtime_enable(&pdev->dev);
> +       if (ret)
> +               return ret;
> +
> +       ret = pm_runtime_resume_and_get(&pdev->dev);
> +       if (ret)
> +               return ret;
> +
> +       regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc);
> +       if (IS_ERR(regmap)) {
> +               pm_runtime_put(&pdev->dev);
> +               return PTR_ERR(regmap);
> +       }
> +
> +       clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
> +       clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
> +
> +       /*
> +        * Keep clocks always enabled:
> +        *      video_cc_ahb_clk
> +        *      video_cc_sleep_clk
> +        *      video_cc_xo_clk
> +        */
> +       regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
> +       regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0));
> +       regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
> +
> +       ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
> +
> +       pm_runtime_put(&pdev->dev);
> +
> +       return ret;
> +}
> +
> +static struct platform_driver video_cc_sm8550_driver = {
> +       .probe = video_cc_sm8550_probe,
> +       .driver = {
> +               .name = "video_cc-sm8550",
> +               .of_match_table = video_cc_sm8550_match_table,
> +       },
> +};
> +
> +static int __init video_cc_sm8550_init(void)
> +{
> +       return platform_driver_register(&video_cc_sm8550_driver);
> +}
> +subsys_initcall(video_cc_sm8550_init);

module_platform_driver() instead? There is no need to register videocc
at the subsys level.

> +
> +static void __exit video_cc_sm8550_exit(void)
> +{
> +       platform_driver_unregister(&video_cc_sm8550_driver);
> +}
> +module_exit(video_cc_sm8550_exit);
> +
> +MODULE_DESCRIPTION("QTI VIDEO_CC SM8550 Driver");
> +MODULE_LICENSE("GPL");

-- 
With best wishes
Dmitry

Re: [PATCH 1/4] clk: qcom: clk-alpha-pll: Add support for lucid ole pll ops

[Konrad Dybcio]

On 9.05.2023 18:12, Jagadeesh Kona wrote:
> From: Taniya Das <quic_tdas@quicinc.com>
> 
> Add support for lucid ole pll ops to configure and control the
> lucid ole pll. The lucid ole pll has an additional test control
> register which is required to be programmed, add support to
> program the same.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> ---
Isn't this commit "write to PLL_TEST_CTL_U2 on LUCID_EVO" instead?

Meaninglessly duplicating ops does not seem useful.

Konrad
>  drivers/clk/qcom/clk-alpha-pll.c | 2 ++
>  drivers/clk/qcom/clk-alpha-pll.h | 4 ++++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index b9f6535a7ba7..f81c7c561352 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -55,6 +55,7 @@
>  #define PLL_TEST_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
>  #define PLL_TEST_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
>  #define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
> +#define PLL_TEST_CTL_U2(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
>  #define PLL_STATUS(p)		((p)->offset + (p)->regs[PLL_OFF_STATUS])
>  #define PLL_OPMODE(p)		((p)->offset + (p)->regs[PLL_OFF_OPMODE])
>  #define PLL_FRAC(p)		((p)->offset + (p)->regs[PLL_OFF_FRAC])
> @@ -2096,6 +2097,7 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
>  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
>  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
>  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
> +	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
>  
>  	/* Disable PLL output */
>  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index d07b17186b90..4d9b6d5b7062 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -125,6 +125,7 @@ struct alpha_pll_config {
>  	u32 test_ctl_val;
>  	u32 test_ctl_hi_val;
>  	u32 test_ctl_hi1_val;
> +	u32 test_ctl_hi2_val;
>  	u32 main_output_mask;
>  	u32 aux_output_mask;
>  	u32 aux2_output_mask;
> @@ -171,6 +172,7 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
>  #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
>  
>  extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
> +#define clk_alpha_pll_lucid_ole_ops clk_alpha_pll_lucid_evo_ops
>  extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
>  #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
>  extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
> @@ -196,6 +198,8 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>  			     const struct alpha_pll_config *config);
>  void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>  				 const struct alpha_pll_config *config);
> +#define clk_lucid_ole_pll_configure(pll, regmap, config) \
> +			clk_lucid_evo_pll_configure(pll, regmap, config)
>  void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>  				  const struct alpha_pll_config *config);
>  void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

Re: [PATCH 2/4] dt-bindings: clock: qcom: Add SM8550 video clock controller

[Krzysztof Kozlowski]

On 09/05/2023 18:12, Jagadeesh Kona wrote:
> Add device tree bindings for the video clock controller on Qualcomm
> SM8550 platform.
> 
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  .../bindings/clock/qcom,sm8550-videocc.yaml   | 77 +++++++++++++++++++
>  .../dt-bindings/clock/qcom,sm8550-videocc.h   | 38 +++++++++
>  2 files changed, 115 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml
>  create mode 100644 include/dt-bindings/clock/qcom,sm8550-videocc.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml
> new file mode 100644
> index 000000000000..107af5e9af89
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm8550-videocc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Video Clock & Reset Controller on SM8550
> +
> +maintainers:
> +  - Jagadeesh Kona <quic_jkona@quicinc.com>
> +  - Taniya Das <quic_tdas@quicinc.com>
> +
> +description: |
> +  Qualcomm video clock control module provides the clocks, resets and power
> +  domains on SM8550.
> +
> +  See also:: include/dt-bindings/clock/qcom,videocc-sm8550.h
> +
> +properties:
> +  compatible:
> +    const: qcom,sm8550-videocc

Nope, looks 100% the same as sm8450, put it there.

https://lore.kernel.org/all/20230509172148.7627-2-quic_tdas@quicinc.com/

Best regards,
Krzysztof

Re: [PATCH 4/4] arm64: dts: qcom: sm8550: Add video clock controller

[Konrad Dybcio]

On 9.05.2023 18:12, Jagadeesh Kona wrote:
> Add device node for video clock controller on Qualcomm SM8550 platform.
> 
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 6e9bad8f6f33..e67e7c69dae6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -7,6 +7,7 @@
>  #include <dt-bindings/clock/qcom,sm8550-gcc.h>
>  #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
>  #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
> +#include <dt-bindings/clock/qcom,sm8550-videocc.h>
>  #include <dt-bindings/dma/qcom-gpi.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -759,6 +760,17 @@ gcc: clock-controller@100000 {
>  				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>  		};
>  
> +		videocc: clock-controller@aaf0000 {
This node should be moved down. Nodes with unit addresses
should be sorted alphanumerically.

> +			compatible = "qcom,sm8550-videocc";
> +			reg = <0 0x0aaf0000 0 0x10000>;
> +			clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>;
One per line, please

Also, any reason the XO clock does not come from RPMhCC?

Konrad
> +			power-domains = <&rpmhpd SM8550_MMCX>;
> +			required-opps = <&rpmhpd_opp_low_svs>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>  		ipcc: mailbox@408000 {
>  			compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
>  			reg = <0 0x00408000 0 0x1000>;

Re: [PATCH 4/4] arm64: dts: qcom: sm8550: Add video clock controller

[Dmitry Baryshkov]

On Mon, 15 May 2023 at 15:28, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 9.05.2023 18:12, Jagadeesh Kona wrote:
> > Add device node for video clock controller on Qualcomm SM8550 platform.
> >
> > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> > Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> > ---
> >  arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > index 6e9bad8f6f33..e67e7c69dae6 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > @@ -7,6 +7,7 @@
> >  #include <dt-bindings/clock/qcom,sm8550-gcc.h>
> >  #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
> >  #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
> > +#include <dt-bindings/clock/qcom,sm8550-videocc.h>
> >  #include <dt-bindings/dma/qcom-gpi.h>
> >  #include <dt-bindings/gpio/gpio.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -759,6 +760,17 @@ gcc: clock-controller@100000 {
> >                                <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> >               };
> >
> > +             videocc: clock-controller@aaf0000 {
> This node should be moved down. Nodes with unit addresses
> should be sorted alphanumerically.
>
> > +                     compatible = "qcom,sm8550-videocc";
> > +                     reg = <0 0x0aaf0000 0 0x10000>;
> > +                     clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>;
> One per line, please
>
> Also, any reason the XO clock does not come from RPMhCC?

bi_tcxo_div_2 is an RPMhCC clock with the fixed divider.

>
> Konrad
> > +                     power-domains = <&rpmhpd SM8550_MMCX>;
> > +                     required-opps = <&rpmhpd_opp_low_svs>;
> > +                     #clock-cells = <1>;
> > +                     #reset-cells = <1>;
> > +                     #power-domain-cells = <1>;
> > +             };
> > +
> >               ipcc: mailbox@408000 {
> >                       compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
> >                       reg = <0 0x00408000 0 0x1000>;



-- 
With best wishes
Dmitry

Re: [PATCH 4/4] arm64: dts: qcom: sm8550: Add video clock controller

[Konrad Dybcio]

On 15.05.2023 14:57, Dmitry Baryshkov wrote:
> On Mon, 15 May 2023 at 15:28, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>>
>>
>> On 9.05.2023 18:12, Jagadeesh Kona wrote:
>>> Add device node for video clock controller on Qualcomm SM8550 platform.
>>>
>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++
>>>  1 file changed, 12 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>> index 6e9bad8f6f33..e67e7c69dae6 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>> @@ -7,6 +7,7 @@
>>>  #include <dt-bindings/clock/qcom,sm8550-gcc.h>
>>>  #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
>>>  #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
>>> +#include <dt-bindings/clock/qcom,sm8550-videocc.h>
>>>  #include <dt-bindings/dma/qcom-gpi.h>
>>>  #include <dt-bindings/gpio/gpio.h>
>>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> @@ -759,6 +760,17 @@ gcc: clock-controller@100000 {
>>>                                <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>>>               };
>>>
>>> +             videocc: clock-controller@aaf0000 {
>> This node should be moved down. Nodes with unit addresses
>> should be sorted alphanumerically.
>>
>>> +                     compatible = "qcom,sm8550-videocc";
>>> +                     reg = <0 0x0aaf0000 0 0x10000>;
>>> +                     clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>;
>> One per line, please
>>
>> Also, any reason the XO clock does not come from RPMhCC?
> 
> bi_tcxo_div_2 is an RPMhCC clock with the fixed divider.
Hm, I don't see it neither on -next or in this patchset..

Konrad
> 
>>
>> Konrad
>>> +                     power-domains = <&rpmhpd SM8550_MMCX>;
>>> +                     required-opps = <&rpmhpd_opp_low_svs>;
>>> +                     #clock-cells = <1>;
>>> +                     #reset-cells = <1>;
>>> +                     #power-domain-cells = <1>;
>>> +             };
>>> +
>>>               ipcc: mailbox@408000 {
>>>                       compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
>>>                       reg = <0 0x00408000 0 0x1000>;
> 
> 
> 

Re: [PATCH 4/4] arm64: dts: qcom: sm8550: Add video clock controller

[Dmitry Baryshkov]

On Mon, 15 May 2023 at 16:08, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 15.05.2023 14:57, Dmitry Baryshkov wrote:
> > On Mon, 15 May 2023 at 15:28, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
> >>
> >>
> >>
> >> On 9.05.2023 18:12, Jagadeesh Kona wrote:
> >>> Add device node for video clock controller on Qualcomm SM8550 platform.
> >>>
> >>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> >>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> >>> ---
> >>>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++
> >>>  1 file changed, 12 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> >>> index 6e9bad8f6f33..e67e7c69dae6 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> >>> @@ -7,6 +7,7 @@
> >>>  #include <dt-bindings/clock/qcom,sm8550-gcc.h>
> >>>  #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
> >>>  #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
> >>> +#include <dt-bindings/clock/qcom,sm8550-videocc.h>
> >>>  #include <dt-bindings/dma/qcom-gpi.h>
> >>>  #include <dt-bindings/gpio/gpio.h>
> >>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>> @@ -759,6 +760,17 @@ gcc: clock-controller@100000 {
> >>>                                <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> >>>               };
> >>>
> >>> +             videocc: clock-controller@aaf0000 {
> >> This node should be moved down. Nodes with unit addresses
> >> should be sorted alphanumerically.
> >>
> >>> +                     compatible = "qcom,sm8550-videocc";
> >>> +                     reg = <0 0x0aaf0000 0 0x10000>;
> >>> +                     clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>;
> >> One per line, please
> >>
> >> Also, any reason the XO clock does not come from RPMhCC?
> >
> > bi_tcxo_div_2 is an RPMhCC clock with the fixed divider.
> Hm, I don't see it neither on -next or in this patchset..

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/qcom/sm8550.dtsi?h=next-20230515#n41

-- 
With best wishes
Dmitry

Re: [PATCH 4/4] arm64: dts: qcom: sm8550: Add video clock controller

[Jagadeesh Kona]

Hi,

Thanks Konrad for your review!

On 5/15/2023 5:58 PM, Konrad Dybcio wrote:
> 
> 
> On 9.05.2023 18:12, Jagadeesh Kona wrote:
>> Add device node for video clock controller on Qualcomm SM8550 platform.
>>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> index 6e9bad8f6f33..e67e7c69dae6 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> @@ -7,6 +7,7 @@
>>   #include <dt-bindings/clock/qcom,sm8550-gcc.h>
>>   #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
>>   #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
>> +#include <dt-bindings/clock/qcom,sm8550-videocc.h>
>>   #include <dt-bindings/dma/qcom-gpi.h>
>>   #include <dt-bindings/gpio/gpio.h>
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>> @@ -759,6 +760,17 @@ gcc: clock-controller@100000 {
>>   				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>>   		};
>>   
>> +		videocc: clock-controller@aaf0000 {
> This node should be moved down. Nodes with unit addresses
> should be sorted alphanumerically.
> 
Sure, will update in the next series.

>> +			compatible = "qcom,sm8550-videocc";
>> +			reg = <0 0x0aaf0000 0 0x10000>;
>> +			clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>;
> One per line, please
> 
Okay

> Also, any reason the XO clock does not come from RPMhCC?
> 
> Konrad
>> +			power-domains = <&rpmhpd SM8550_MMCX>;
>> +			required-opps = <&rpmhpd_opp_low_svs>;
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +			#power-domain-cells = <1>;
>> +		};
>> +
>>   		ipcc: mailbox@408000 {
>>   			compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
>>   			reg = <0 0x00408000 0 0x1000>;

Thanks & Regards,
Jagadeesh

Re: [PATCH 2/4] dt-bindings: clock: qcom: Add SM8550 video clock controller

[Jagadeesh Kona]

Hi,

Thanks Krzysztof for your review!

On 5/10/2023 12:43 PM, Krzysztof Kozlowski wrote:
> On 09/05/2023 18:12, Jagadeesh Kona wrote:
>> Add device tree bindings for the video clock controller on Qualcomm
>> SM8550 platform.
>>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>>   .../bindings/clock/qcom,sm8550-videocc.yaml   | 77 +++++++++++++++++++
>>   .../dt-bindings/clock/qcom,sm8550-videocc.h   | 38 +++++++++
>>   2 files changed, 115 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml
>>   create mode 100644 include/dt-bindings/clock/qcom,sm8550-videocc.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml
>> new file mode 100644
>> index 000000000000..107af5e9af89
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml
>> @@ -0,0 +1,77 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,sm8550-videocc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Video Clock & Reset Controller on SM8550
>> +
>> +maintainers:
>> +  - Jagadeesh Kona <quic_jkona@quicinc.com>
>> +  - Taniya Das <quic_tdas@quicinc.com>
>> +
>> +description: |
>> +  Qualcomm video clock control module provides the clocks, resets and power
>> +  domains on SM8550.
>> +
>> +  See also:: include/dt-bindings/clock/qcom,videocc-sm8550.h
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,sm8550-videocc
> 
> Nope, looks 100% the same as sm8450, put it there.
> 
> https://lore.kernel.org/all/20230509172148.7627-2-quic_tdas@quicinc.com/
> 
Yes, will take care of this in next series.

> Best regards,
> Krzysztof
> 

Thanks & Regards,
Jagadeesh

Re: [PATCH 1/4] clk: qcom: clk-alpha-pll: Add support for lucid ole pll ops

[Jagadeesh Kona]

Hi,

Thanks Konrad for your review!

On 5/10/2023 1:36 AM, Konrad Dybcio wrote:
> 
> 
> On 9.05.2023 18:12, Jagadeesh Kona wrote:
>> From: Taniya Das <quic_tdas@quicinc.com>
>>
>> Add support for lucid ole pll ops to configure and control the
>> lucid ole pll. The lucid ole pll has an additional test control
>> register which is required to be programmed, add support to
>> program the same.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> ---
> Isn't this commit "write to PLL_TEST_CTL_U2 on LUCID_EVO" instead?
> 
> Meaninglessly duplicating ops does not seem useful.
> 
> Konrad

Though we are reusing same ops for EVO and OLE, PLL_TEST_CTL_U2 register 
programming is applicable only to OLE PLL type. And PLL type is useful 
to properly refer respective hardware datasheets. Hence added separate 
ops for OLE PLL type.


>>   drivers/clk/qcom/clk-alpha-pll.c | 2 ++
>>   drivers/clk/qcom/clk-alpha-pll.h | 4 ++++
>>   2 files changed, 6 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>> index b9f6535a7ba7..f81c7c561352 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -55,6 +55,7 @@
>>   #define PLL_TEST_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
>>   #define PLL_TEST_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
>>   #define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
>> +#define PLL_TEST_CTL_U2(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
>>   #define PLL_STATUS(p)		((p)->offset + (p)->regs[PLL_OFF_STATUS])
>>   #define PLL_OPMODE(p)		((p)->offset + (p)->regs[PLL_OFF_OPMODE])
>>   #define PLL_FRAC(p)		((p)->offset + (p)->regs[PLL_OFF_FRAC])
>> @@ -2096,6 +2097,7 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
>>   	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
>>   	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
>>   	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
>> +	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
>>   
>>   	/* Disable PLL output */
>>   	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
>> index d07b17186b90..4d9b6d5b7062 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.h
>> +++ b/drivers/clk/qcom/clk-alpha-pll.h
>> @@ -125,6 +125,7 @@ struct alpha_pll_config {
>>   	u32 test_ctl_val;
>>   	u32 test_ctl_hi_val;
>>   	u32 test_ctl_hi1_val;
>> +	u32 test_ctl_hi2_val;
>>   	u32 main_output_mask;
>>   	u32 aux_output_mask;
>>   	u32 aux2_output_mask;
>> @@ -171,6 +172,7 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
>>   #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
>>   
>>   extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
>> +#define clk_alpha_pll_lucid_ole_ops clk_alpha_pll_lucid_evo_ops
>>   extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
>>   #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
>>   extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
>> @@ -196,6 +198,8 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>>   			     const struct alpha_pll_config *config);
>>   void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>>   				 const struct alpha_pll_config *config);
>> +#define clk_lucid_ole_pll_configure(pll, regmap, config) \
>> +			clk_lucid_evo_pll_configure(pll, regmap, config)
>>   void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>>   				  const struct alpha_pll_config *config);
>>   void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

Thanks & Regards,
Jagadeesh

Re: [PATCH 1/4] clk: qcom: clk-alpha-pll: Add support for lucid ole pll ops

[Konrad Dybcio]

On 19.05.2023 14:49, Jagadeesh Kona wrote:
> Hi,
> 
> Thanks Konrad for your review!
> 
> On 5/10/2023 1:36 AM, Konrad Dybcio wrote:
>>
>>
>> On 9.05.2023 18:12, Jagadeesh Kona wrote:
>>> From: Taniya Das <quic_tdas@quicinc.com>
>>>
>>> Add support for lucid ole pll ops to configure and control the
>>> lucid ole pll. The lucid ole pll has an additional test control
>>> register which is required to be programmed, add support to
>>> program the same.
>>>
>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>>> ---
>> Isn't this commit "write to PLL_TEST_CTL_U2 on LUCID_EVO" instead?
>>
>> Meaninglessly duplicating ops does not seem useful.
>>
>> Konrad
> 
> Though we are reusing same ops for EVO and OLE, PLL_TEST_CTL_U2 register programming is applicable only to OLE PLL type.
Well, your patch makes it unconditional (modulo programmer error) so
I think that makes little sense.. A comment would be enough, imo.

Konrad
And PLL type is useful to properly refer respective hardware datasheets. Hence added separate ops for OLE PLL type.
> 
> 
>>>   drivers/clk/qcom/clk-alpha-pll.c | 2 ++
>>>   drivers/clk/qcom/clk-alpha-pll.h | 4 ++++
>>>   2 files changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>>> index b9f6535a7ba7..f81c7c561352 100644
>>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>>> @@ -55,6 +55,7 @@
>>>   #define PLL_TEST_CTL(p)        ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
>>>   #define PLL_TEST_CTL_U(p)    ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
>>>   #define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
>>> +#define PLL_TEST_CTL_U2(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
>>>   #define PLL_STATUS(p)        ((p)->offset + (p)->regs[PLL_OFF_STATUS])
>>>   #define PLL_OPMODE(p)        ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
>>>   #define PLL_FRAC(p)        ((p)->offset + (p)->regs[PLL_OFF_FRAC])
>>> @@ -2096,6 +2097,7 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
>>>       clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
>>>       clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
>>>       clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
>>> +    clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
>>>         /* Disable PLL output */
>>>       regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
>>> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
>>> index d07b17186b90..4d9b6d5b7062 100644
>>> --- a/drivers/clk/qcom/clk-alpha-pll.h
>>> +++ b/drivers/clk/qcom/clk-alpha-pll.h
>>> @@ -125,6 +125,7 @@ struct alpha_pll_config {
>>>       u32 test_ctl_val;
>>>       u32 test_ctl_hi_val;
>>>       u32 test_ctl_hi1_val;
>>> +    u32 test_ctl_hi2_val;
>>>       u32 main_output_mask;
>>>       u32 aux_output_mask;
>>>       u32 aux2_output_mask;
>>> @@ -171,6 +172,7 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
>>>   #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
>>>     extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
>>> +#define clk_alpha_pll_lucid_ole_ops clk_alpha_pll_lucid_evo_ops
>>>   extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
>>>   #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
>>>   extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
>>> @@ -196,6 +198,8 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>>>                    const struct alpha_pll_config *config);
>>>   void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>>>                    const struct alpha_pll_config *config);
>>> +#define clk_lucid_ole_pll_configure(pll, regmap, config) \
>>> +            clk_lucid_evo_pll_configure(pll, regmap, config)
>>>   void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>>>                     const struct alpha_pll_config *config);
>>>   void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> 
> Thanks & Regards,
> Jagadeesh

Re: [PATCH 3/4] clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550

[Jagadeesh Kona]

Hi Dmitry,

Thanks for your review!

On 5/9/2023 10:45 PM, Dmitry Baryshkov wrote:
> On Tue, 9 May 2023 at 19:14, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>>
>> Add support for the video clock controller for video clients to be able
>> to request for videocc clocks on SM8550 platform.
>>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>>   drivers/clk/qcom/Kconfig          |  10 +
>>   drivers/clk/qcom/Makefile         |   1 +
>>   drivers/clk/qcom/videocc-sm8550.c | 468 ++++++++++++++++++++++++++++++
>>   3 files changed, 479 insertions(+)
>>   create mode 100644 drivers/clk/qcom/videocc-sm8550.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 12be3e2371b3..6bb9b4aff047 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -925,6 +925,16 @@ config SM_VIDEOCC_8250
>>            Say Y if you want to support video devices and functionality such as
>>            video encode and decode.
>>
>> +config SM_VIDEOCC_8550
>> +       tristate "SM8550 Video Clock Controller"
>> +       select SM_GCC_8550
>> +       select QCOM_GDSC
>> +       help
>> +         Support for the video clock controller on Qualcomm Technologies, Inc.
>> +         SM8550 devices.
>> +         Say Y if you want to support video devices and functionality such as
>> +         video encode/decode.
>> +
>>   config SPMI_PMIC_CLKDIV
>>          tristate "SPMI PMIC clkdiv Support"
>>          depends on SPMI || COMPILE_TEST
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index 9ff4c373ad95..f0b95fc217aa 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -127,6 +127,7 @@ obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
>>   obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
>>   obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
>>   obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
>> +obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o
>>   obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
>>   obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
>>   obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
>> diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
>> new file mode 100644
>> index 000000000000..10e4b2725ddf
>> --- /dev/null
>> +++ b/drivers/clk/qcom/videocc-sm8550.c
>> @@ -0,0 +1,468 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <dt-bindings/clock/qcom,sm8550-videocc.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "clk-regmap-divider.h"
>> +#include "common.h"
>> +#include "gdsc.h"
>> +#include "reset.h"
>> +
>> +enum {
>> +       DT_BI_TCXO,
> 
> Any additional handling for gcc_video_ahb clk? It doesn't seem to be
> used as a parent. Probably you intended to use it as a pm_clk?
> Yes it is a pm_clk, but no additional handling is required from driver side.

>> +};
>> +
>> +enum {
>> +       P_BI_TCXO,
>> +       P_VIDEO_CC_PLL0_OUT_MAIN,
>> +       P_VIDEO_CC_PLL1_OUT_MAIN,
>> +};
[skipped]

>> +static struct clk_regmap *video_cc_sm8550_clocks[] = {
>> +       [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
>> +       [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
>> +       [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
>> +       [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
>> +       [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
>> +       [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
>> +       [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
>> +       [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
>> +       [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
>> +       [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
>> +       [VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
>> +       [VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
>> +};
>> +
>> +static struct gdsc *video_cc_sm8550_gdscs[] = {
>> +       [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
>> +       [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
>> +       [VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
>> +       [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
>> +};
>> +
>> +static const struct qcom_reset_map video_cc_sm8550_resets[] = {
>> +       [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
>> +       [CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
>> +       [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
>> +       [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
>> +       [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
> 
> Please rename them to start with the VIDEO_CC prefix.
> 
These names are coming from hardware plan and clients will
refer to hardware plan for these names. So we would like to
keep the names intact same as from hardware plan.

>> +       [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
>> +       [VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
>> +};
>> +
>> +static const struct regmap_config video_cc_sm8550_regmap_config = {
>> +       .reg_bits = 32,
>> +       .reg_stride = 4,
>> +       .val_bits = 32,
>> +       .max_register = 0x9f4c,
>> +       .fast_io = true,
>> +};
>> +
>> +static struct qcom_cc_desc video_cc_sm8550_desc = {
>> +       .config = &video_cc_sm8550_regmap_config,
>> +       .clks = video_cc_sm8550_clocks,
>> +       .num_clks = ARRAY_SIZE(video_cc_sm8550_clocks),
>> +       .resets = video_cc_sm8550_resets,
>> +       .num_resets = ARRAY_SIZE(video_cc_sm8550_resets),
>> +       .gdscs = video_cc_sm8550_gdscs,
>> +       .num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs),
>> +};
>> +
>> +static const struct of_device_id video_cc_sm8550_match_table[] = {
>> +       { .compatible = "qcom,sm8550-videocc" },
>> +       { }
>> +};
>> +MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
>> +
>> +static int video_cc_sm8550_probe(struct platform_device *pdev)
>> +{
>> +       struct regmap *regmap;
>> +       int ret;
>> +
>> +       ret = devm_pm_runtime_enable(&pdev->dev);
>> +       if (ret)
>> +               return ret;
>> +
>> +       ret = pm_runtime_resume_and_get(&pdev->dev);
>> +       if (ret)
>> +               return ret;
>> +
>> +       regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc);
>> +       if (IS_ERR(regmap)) {
>> +               pm_runtime_put(&pdev->dev);
>> +               return PTR_ERR(regmap);
>> +       }
>> +
>> +       clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
>> +       clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
>> +
>> +       /*
>> +        * Keep clocks always enabled:
>> +        *      video_cc_ahb_clk
>> +        *      video_cc_sleep_clk
>> +        *      video_cc_xo_clk
>> +        */
>> +       regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
>> +       regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0));
>> +       regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
>> +
>> +       ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
>> +
>> +       pm_runtime_put(&pdev->dev);
>> +
>> +       return ret;
>> +}
>> +
>> +static struct platform_driver video_cc_sm8550_driver = {
>> +       .probe = video_cc_sm8550_probe,
>> +       .driver = {
>> +               .name = "video_cc-sm8550",
>> +               .of_match_table = video_cc_sm8550_match_table,
>> +       },
>> +};
>> +
>> +static int __init video_cc_sm8550_init(void)
>> +{
>> +       return platform_driver_register(&video_cc_sm8550_driver);
>> +}
>> +subsys_initcall(video_cc_sm8550_init);
> 
> module_platform_driver() instead? There is no need to register videocc
> at the subsys level.
> 
We need to evaluate and validate if module_platform_driver works for us 
in all scenarios. We will post a cleanup patch once we conclude 
module_platform_driver works for us in all cases.

Thanks & Regards,
Jagadeesh

Re: [PATCH 1/4] clk: qcom: clk-alpha-pll: Add support for lucid ole pll ops

[Jagadeesh Kona]

Hi Konrad,

Thanks for your review!

On 5/19/2023 6:39 PM, Konrad Dybcio wrote:
> 
> 
> On 19.05.2023 14:49, Jagadeesh Kona wrote:
>> Hi,
>>
>> Thanks Konrad for your review!
>>
>> On 5/10/2023 1:36 AM, Konrad Dybcio wrote:
>>>
>>>
>>> On 9.05.2023 18:12, Jagadeesh Kona wrote:
>>>> From: Taniya Das <quic_tdas@quicinc.com>
>>>>
>>>> Add support for lucid ole pll ops to configure and control the
>>>> lucid ole pll. The lucid ole pll has an additional test control
>>>> register which is required to be programmed, add support to
>>>> program the same.
>>>>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>>>> ---
>>> Isn't this commit "write to PLL_TEST_CTL_U2 on LUCID_EVO" instead?
>>>
>>> Meaninglessly duplicating ops does not seem useful.
>>>
>>> Konrad
>>
>> Though we are reusing same ops for EVO and OLE, PLL_TEST_CTL_U2 register programming is applicable only to OLE PLL type.
> Well, your patch makes it unconditional (modulo programmer error) so
> I think that makes little sense.. A comment would be enough, imo.
> 
> Konrad
Yes, will remove the duplicate definitions and will reuse the existing ops.

> And PLL type is useful to properly refer respective hardware datasheets. Hence added separate ops for OLE PLL type.
>>

Thanks & Regards,
Jagadeesh