* [Intel-gfx] [PATCH] drm/i915: Use REG_BIT() & co. for AUX CH registers
@ 2023-05-09 17:14 Ville Syrjala
2023-05-09 19:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Ville Syrjala @ 2023-05-09 17:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Modernize the DP AUX CH register definitions with REG_BIT() & co.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 35 +++++------
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 62 ++++++++++---------
drivers/gpu/drm/i915/gvt/edid.c | 10 +--
3 files changed, 52 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index abf77ba76972..25e36bdc4adb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -161,14 +161,14 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
return DP_AUX_CH_CTL_SEND_BUSY |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_INTERRUPT |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- timeout |
- DP_AUX_CH_CTL_RECEIVE_ERROR |
- (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- (g4x_dp_aux_precharge_len() << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
- (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_INTERRUPT |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ timeout |
+ DP_AUX_CH_CTL_RECEIVE_ERROR |
+ DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) |
+ DP_AUX_CH_CTL_PRECHARGE_2US(g4x_dp_aux_precharge_len()) |
+ DP_AUX_CH_CTL_BIT_CLOCK_2X(aux_clock_divider);
}
static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
@@ -185,14 +185,14 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
* ICL+: 4ms
*/
ret = DP_AUX_CH_CTL_SEND_BUSY |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_INTERRUPT |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_TIME_OUT_MAX |
- DP_AUX_CH_CTL_RECEIVE_ERROR |
- (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len()) |
- DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len());
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_INTERRUPT |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_TIME_OUT_MAX |
+ DP_AUX_CH_CTL_RECEIVE_ERROR |
+ DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) |
+ DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len()) |
+ DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len());
if (intel_tc_port_in_tbt_alt_mode(dig_port))
ret |= DP_AUX_CH_CTL_TBT_IO;
@@ -378,8 +378,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
}
/* Unload any bytes sent back from the other side */
- recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
- DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
+ recv_bytes = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, status);
/*
* By BSpec: "Message sizes of 0 or >20 are not allowed."
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
index 5702f318d537..5185345277c7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
@@ -50,35 +50,37 @@
_XELPDP_USBC3_AUX_CH_DATA1, \
_XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
-#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
-#define DP_AUX_CH_CTL_DONE (1 << 30)
-#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
-#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
-#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
-#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
-#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
-#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
-#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
-#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
-#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19)
-#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18)
-#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
-#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
-#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
-#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
-#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
-#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
-#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
-#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
-#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
-#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
-#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
-#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
-#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
-#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
-#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
-#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
+#define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
+#define DP_AUX_CH_CTL_DONE REG_BIT(30)
+#define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
+#define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28)
+
+#define DP_AUX_CH_CTL_TIME_OUT_MASK REG_GENMASK(27, 26)
+#define DP_AUX_CH_CTL_TIME_OUT_400us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 0)
+#define DP_AUX_CH_CTL_TIME_OUT_600us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 1)
+#define DP_AUX_CH_CTL_TIME_OUT_800us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 2)
+#define DP_AUX_CH_CTL_TIME_OUT_MAX REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 3) /* Varies per platform */
+#define DP_AUX_CH_CTL_RECEIVE_ERROR REG_BIT(25)
+#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK REG_GENMASK(24, 20)
+#define DP_AUX_CH_CTL_MESSAGE_SIZE(x) REG_FIELD_PREP(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, (x))
+#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK REG_GENMASK(19, 16) /* pre-skl */
+#define DP_AUX_CH_CTL_PRECHARGE_2US(x) REG_FIELD_PREP(DP_AUX_CH_CTL_PRECHARGE_2US_MASK, (x))
+#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) /* mtl+ */
+#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) /* mtl+ */
+#define DP_AUX_CH_CTL_AUX_AKSV_SELECT REG_BIT(15)
+#define DP_AUX_CH_CTL_MANCHESTER_TEST REG_BIT(14) /* pre-hsw */
+#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL REG_BIT(14) /* skl+ */
+#define DP_AUX_CH_CTL_SYNC_TEST REG_BIT(13) /* pre-hsw */
+#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL REG_BIT(13) /* skl+ */
+#define DP_AUX_CH_CTL_DEGLITCH_TEST REG_BIT(12) /* pre-hsw */
+#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL REG_BIT(12) /* skl+ */
+#define DP_AUX_CH_CTL_PRECHARGE_TEST REG_BIT(11) /* pre-hsw */
+#define DP_AUX_CH_CTL_TBT_IO REG_BIT(11) /* icl+ */
+#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK REG_GENMASK(10, 0) /* pre-skl */
+#define DP_AUX_CH_CTL_BIT_CLOCK_2X(x) REG_FIELD_PREP(DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK, (x))
+#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK REG_GENMASK(9, 5) /* skl+ */
+#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK, (c) - 1)
+#define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
+#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
#endif /* __INTEL_DP_AUX_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 7c49a3d673a5..2a0438f12a14 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -463,10 +463,6 @@ static inline int get_aux_ch_reg(unsigned int offset)
return reg;
}
-#define AUX_CTL_MSG_LENGTH(reg) \
- ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \
- DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT)
-
/**
* intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
* @vgpu: a vGPU
@@ -495,7 +491,8 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
return;
}
- msg_length = AUX_CTL_MSG_LENGTH(value);
+ msg_length = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, reg);
+
// check the msg in DATA register.
msg = vgpu_vreg(vgpu, offset + 4);
addr = (msg >> 8) & 0xffff;
@@ -510,8 +507,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1);
vgpu_vreg(vgpu, offset) =
DP_AUX_CH_CTL_DONE |
- ((ret_msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) &
- DP_AUX_CH_CTL_MESSAGE_SIZE_MASK);
+ DP_AUX_CH_CTL_MESSAGE_SIZE(ret_msg_size);
if (msg_length == 3) {
if (!(op & GVT_AUX_I2C_MOT)) {
--
2.39.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Use REG_BIT() & co. for AUX CH registers
2023-05-09 17:14 [Intel-gfx] [PATCH] drm/i915: Use REG_BIT() & co. for AUX CH registers Ville Syrjala
@ 2023-05-09 19:27 ` Patchwork
2023-05-09 19:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-05-09 19:27 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Use REG_BIT() & co. for AUX CH registers
URL : https://patchwork.freedesktop.org/series/117533/
State : warning
== Summary ==
Error: dim checkpatch failed
7101057c8957 drm/i915: Use REG_BIT() & co. for AUX CH registers
-:120: WARNING:LONG_LINE_COMMENT: line length of 120 exceeds 100 columns
#120: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_regs.h:62:
+#define DP_AUX_CH_CTL_TIME_OUT_MAX REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 3) /* Varies per platform */
-:125: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#125: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_regs.h:67:
+#define DP_AUX_CH_CTL_PRECHARGE_2US(x) REG_FIELD_PREP(DP_AUX_CH_CTL_PRECHARGE_2US_MASK, (x))
-:140: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#140: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_regs.h:82:
+#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK, (c) - 1)
-:142: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#142: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_regs.h:84:
+#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
total: 0 errors, 4 warnings, 0 checks, 148 lines checked
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use REG_BIT() & co. for AUX CH registers
2023-05-09 17:14 [Intel-gfx] [PATCH] drm/i915: Use REG_BIT() & co. for AUX CH registers Ville Syrjala
2023-05-09 19:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2023-05-09 19:41 ` Patchwork
2023-05-09 22:14 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-05-11 5:40 ` [Intel-gfx] [PATCH] " Hogander, Jouni
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-05-09 19:41 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5818 bytes --]
== Series Details ==
Series: drm/i915: Use REG_BIT() & co. for AUX CH registers
URL : https://patchwork.freedesktop.org/series/117533/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13128 -> Patchwork_117533v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/index.html
Participating hosts (40 -> 39)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_117533v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html
* igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][2] ([i915#7077])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/bat-rplp-1/igt@i915_pm_backlight@basic-brightness@edp-1.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@mman:
- bat-rpls-2: NOTRUN -> [TIMEOUT][5] ([i915#6794] / [i915#7392])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/bat-rpls-2/igt@i915_selftest@live@mman.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][6] -> [ABORT][7] ([i915#4983] / [i915#7461] / [i915#7953] / [i915#8347] / [i915#8384])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/bat-rpls-1/igt@i915_selftest@live@reset.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][8] ([i915#6687])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-cfl-8109u: NOTRUN -> [SKIP][9] ([fdo#109271]) +18 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/fi-cfl-8109u/igt@kms_chamelium_frames@hdmi-crc-fast.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- bat-rpls-2: [ABORT][10] ([i915#4983] / [i915#7913]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/bat-rpls-2/igt@i915_selftest@live@requests.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@kms_busy@basic@modeset:
- fi-cfl-8109u: [INCOMPLETE][12] -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/fi-cfl-8109u/igt@kms_busy@basic@modeset.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/fi-cfl-8109u/igt@kms_busy@basic@modeset.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [FAIL][14] ([i915#7932]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
#### Warnings ####
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [ABORT][16] -> [SKIP][17] ([i915#3555] / [i915#4579])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
Build changes
-------------
* Linux: CI_DRM_13128 -> Patchwork_117533v1
CI-20190529: 20190529
CI_DRM_13128: 31e3463b0edba64934bfd9e8fdbebeab1676d3eb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7283: ce51f53938690f581b315fa045d41155a5c6ecd3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117533v1: 31e3463b0edba64934bfd9e8fdbebeab1676d3eb @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
9b4963fe683f drm/i915: Use REG_BIT() & co. for AUX CH registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/index.html
[-- Attachment #2: Type: text/html, Size: 6815 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Use REG_BIT() & co. for AUX CH registers
2023-05-09 17:14 [Intel-gfx] [PATCH] drm/i915: Use REG_BIT() & co. for AUX CH registers Ville Syrjala
2023-05-09 19:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-05-09 19:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-05-09 22:14 ` Patchwork
2023-05-11 5:40 ` [Intel-gfx] [PATCH] " Hogander, Jouni
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-05-09 22:14 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10882 bytes --]
== Series Details ==
Series: drm/i915: Use REG_BIT() & co. for AUX CH registers
URL : https://patchwork.freedesktop.org/series/117533/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13128_full -> Patchwork_117533v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_117533v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_117533v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_117533v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-apl7/igt@gem_workarounds@suspend-resume.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-apl6/igt@gem_workarounds@suspend-resume.html
Known issues
------------
Here are the changes found in Patchwork_117533v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][3] -> [ABORT][4] ([i915#7461] / [i915#8211])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-glk2/igt@gem_barrier_race@remote-request@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-glk5/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-snb: [PASS][5] -> [DMESG-FAIL][6] ([i915#8295])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-snb2/igt@gem_ppgtt@blt-vs-render-ctxn.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][7] -> [ABORT][8] ([i915#5566])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-apl4/igt@gen9_exec_parse@allowed-single.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-apl7/igt@gen9_exec_parse@allowed-single.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#3886]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-apl2/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271]) +11 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-apl2/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs.html
* igt@kms_content_protection@lic@pipe-a-dp-1:
- shard-apl: NOTRUN -> [TIMEOUT][11] ([i915#7173])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-apl2/igt@kms_content_protection@lic@pipe-a-dp-1.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2346])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#658])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-apl2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@perf@stress-open-close@0-rcs0:
- shard-apl: [PASS][15] -> [ABORT][16] ([i915#5213])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-apl2/igt@perf@stress-open-close@0-rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-apl3/igt@perf@stress-open-close@0-rcs0.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}: [FAIL][17] ([i915#2842]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-rkl-2/igt@gem_exec_fair@basic-none@bcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-rkl-4/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][19] ([i915#2842]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
- {shard-tglu}: [FAIL][21] ([i915#2842]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-tglu-7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}: [DMESG-WARN][23] ([i915#4936] / [i915#5493]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-rkl}: [SKIP][25] ([i915#1397]) -> [PASS][26] +3 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-rkl-2/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][27] ([i915#2346]) -> [PASS][28] +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][29] ([i915#2122]) -> [PASS][30] +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-apl: [ABORT][31] -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-apl1/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-apl2/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
* igt@prime_self_import@reimport-vs-gem_close-race:
- {shard-dg1}: [FAIL][33] ([i915#7951]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13128/shard-dg1-17/igt@prime_self_import@reimport-vs-gem_close-race.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/shard-dg1-17/igt@prime_self_import@reimport-vs-gem_close-race.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7951]: https://gitlab.freedesktop.org/drm/intel/issues/7951
[i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8295]: https://gitlab.freedesktop.org/drm/intel/issues/8295
Build changes
-------------
* Linux: CI_DRM_13128 -> Patchwork_117533v1
CI-20190529: 20190529
CI_DRM_13128: 31e3463b0edba64934bfd9e8fdbebeab1676d3eb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7283: ce51f53938690f581b315fa045d41155a5c6ecd3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117533v1: 31e3463b0edba64934bfd9e8fdbebeab1676d3eb @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117533v1/index.html
[-- Attachment #2: Type: text/html, Size: 10940 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Use REG_BIT() & co. for AUX CH registers
2023-05-09 17:14 [Intel-gfx] [PATCH] drm/i915: Use REG_BIT() & co. for AUX CH registers Ville Syrjala
` (2 preceding siblings ...)
2023-05-09 22:14 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-05-11 5:40 ` Hogander, Jouni
3 siblings, 0 replies; 5+ messages in thread
From: Hogander, Jouni @ 2023-05-11 5:40 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Tue, 2023-05-09 at 20:14 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Modernize the DP AUX CH register definitions with REG_BIT() & co.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
>
> ---
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 35 +++++------
> .../gpu/drm/i915/display/intel_dp_aux_regs.h | 62 ++++++++++-------
> --
> drivers/gpu/drm/i915/gvt/edid.c | 10 +--
> 3 files changed, 52 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index abf77ba76972..25e36bdc4adb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -161,14 +161,14 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp
> *intel_dp,
> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
>
> return DP_AUX_CH_CTL_SEND_BUSY |
> - DP_AUX_CH_CTL_DONE |
> - DP_AUX_CH_CTL_INTERRUPT |
> - DP_AUX_CH_CTL_TIME_OUT_ERROR |
> - timeout |
> - DP_AUX_CH_CTL_RECEIVE_ERROR |
> - (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> - (g4x_dp_aux_precharge_len() <<
> DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
> - (aux_clock_divider <<
> DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
> + DP_AUX_CH_CTL_DONE |
> + DP_AUX_CH_CTL_INTERRUPT |
> + DP_AUX_CH_CTL_TIME_OUT_ERROR |
> + timeout |
> + DP_AUX_CH_CTL_RECEIVE_ERROR |
> + DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) |
> + DP_AUX_CH_CTL_PRECHARGE_2US(g4x_dp_aux_precharge_len(
> )) |
> + DP_AUX_CH_CTL_BIT_CLOCK_2X(aux_clock_divider);
> }
>
> static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> @@ -185,14 +185,14 @@ static u32 skl_get_aux_send_ctl(struct intel_dp
> *intel_dp,
> * ICL+: 4ms
> */
> ret = DP_AUX_CH_CTL_SEND_BUSY |
> - DP_AUX_CH_CTL_DONE |
> - DP_AUX_CH_CTL_INTERRUPT |
> - DP_AUX_CH_CTL_TIME_OUT_ERROR |
> - DP_AUX_CH_CTL_TIME_OUT_MAX |
> - DP_AUX_CH_CTL_RECEIVE_ERROR |
> - (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> -
> DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len()) |
> - DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len());
> + DP_AUX_CH_CTL_DONE |
> + DP_AUX_CH_CTL_INTERRUPT |
> + DP_AUX_CH_CTL_TIME_OUT_ERROR |
> + DP_AUX_CH_CTL_TIME_OUT_MAX |
> + DP_AUX_CH_CTL_RECEIVE_ERROR |
> + DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) |
> + DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_
> len()) |
> + DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len())
> ;
>
> if (intel_tc_port_in_tbt_alt_mode(dig_port))
> ret |= DP_AUX_CH_CTL_TBT_IO;
> @@ -378,8 +378,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> }
>
> /* Unload any bytes sent back from the other side */
> - recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
> - DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
> + recv_bytes = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK,
> status);
>
> /*
> * By BSpec: "Message sizes of 0 or >20 are not allowed."
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> index 5702f318d537..5185345277c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> @@ -50,35 +50,37 @@
>
> _XELPDP_USBC3_AUX_CH_DATA1, \
>
> _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
>
> -#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
> -#define DP_AUX_CH_CTL_DONE (1 << 30)
> -#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
> -#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
> -#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
> -#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
> -#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
> -#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per
> platform */
> -#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
> -#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
> -#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
> -#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
> -#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19)
> -#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18)
> -#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
> -#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
> -#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
> -#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
> -#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
> -#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
> -#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
> -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
> -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
> -#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
> -#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
> -#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
> -#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
> -#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
> -#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
> -#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
> +#define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
> +#define DP_AUX_CH_CTL_DONE REG_BIT(30)
> +#define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
> +#define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28)
> +
> +#define DP_AUX_CH_CTL_TIME_OUT_MASK REG_GENMASK(27, 26)
> +#define
> DP_AUX_CH_CTL_TIME_OUT_400us REG_FIELD_PREP(DP_AUX_CH_CTL_TIM
> E_OUT_MASK, 0)
> +#define
> DP_AUX_CH_CTL_TIME_OUT_600us REG_FIELD_PREP(DP_AUX_CH_CTL_TIM
> E_OUT_MASK, 1)
> +#define
> DP_AUX_CH_CTL_TIME_OUT_800us REG_FIELD_PREP(DP_AUX_CH_CTL_TIM
> E_OUT_MASK, 2)
> +#define
> DP_AUX_CH_CTL_TIME_OUT_MAX REG_FIELD_PREP(DP_AUX_CH_CTL_TIM
> E_OUT_MASK, 3) /* Varies per platform */
> +#define DP_AUX_CH_CTL_RECEIVE_ERROR REG_BIT(25)
> +#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK REG_GENMASK(24, 20)
> +#define
> DP_AUX_CH_CTL_MESSAGE_SIZE(x) REG_FIELD_PREP(DP_AUX_CH
> _CTL_MESSAGE_SIZE_MASK, (x))
> +#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK REG_GENMASK(19, 16)
> /* pre-skl */
> +#define
> DP_AUX_CH_CTL_PRECHARGE_2US(x) REG_FIELD_PREP(DP_AUX_CH_CTL_PRE
> CHARGE_2US_MASK, (x))
> +#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) /* mtl+
> */
> +#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) /* mtl+
> */
> +#define DP_AUX_CH_CTL_AUX_AKSV_SELECT REG_BIT(15)
> +#define DP_AUX_CH_CTL_MANCHESTER_TEST REG_BIT(14)
> /* pre-hsw */
> +#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL REG_BIT(14) /* skl+
> */
> +#define DP_AUX_CH_CTL_SYNC_TEST REG_BIT(13) /* pre-
> hsw */
> +#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL REG_BIT(13) /* skl+
> */
> +#define DP_AUX_CH_CTL_DEGLITCH_TEST REG_BIT(12) /* pre-
> hsw */
> +#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL REG_BIT(12) /* skl+
> */
> +#define DP_AUX_CH_CTL_PRECHARGE_TEST REG_BIT(11) /* pre-
> hsw */
> +#define DP_AUX_CH_CTL_TBT_IO REG_BIT(11) /* icl+
> */
> +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK REG_GENMASK(10, 0) /*
> pre-skl */
> +#define
> DP_AUX_CH_CTL_BIT_CLOCK_2X(x) REG_FIELD_PREP(DP_AUX_CH
> _CTL_BIT_CLOCK_2X_MASK, (x))
> +#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK REG_GENMASK(9, 5) /*
> skl+ */
> +#define
> DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_FW_
> SYNC_PULSE_SKL_MASK, (c) - 1)
> +#define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /*
> skl+ */
> +#define
> DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYN
> C_PULSE_SKL_MASK, (c) - 1)
>
> #endif /* __INTEL_DP_AUX_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/gvt/edid.c
> b/drivers/gpu/drm/i915/gvt/edid.c
> index 7c49a3d673a5..2a0438f12a14 100644
> --- a/drivers/gpu/drm/i915/gvt/edid.c
> +++ b/drivers/gpu/drm/i915/gvt/edid.c
> @@ -463,10 +463,6 @@ static inline int get_aux_ch_reg(unsigned int
> offset)
> return reg;
> }
>
> -#define AUX_CTL_MSG_LENGTH(reg) \
> - ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \
> - DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT)
> -
> /**
> * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register
> write
> * @vgpu: a vGPU
> @@ -495,7 +491,8 @@ void intel_gvt_i2c_handle_aux_ch_write(struct
> intel_vgpu *vgpu,
> return;
> }
>
> - msg_length = AUX_CTL_MSG_LENGTH(value);
> + msg_length = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK,
> reg);
> +
> // check the msg in DATA register.
> msg = vgpu_vreg(vgpu, offset + 4);
> addr = (msg >> 8) & 0xffff;
> @@ -510,8 +507,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct
> intel_vgpu *vgpu,
> ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1);
> vgpu_vreg(vgpu, offset) =
> DP_AUX_CH_CTL_DONE |
> - ((ret_msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) &
> - DP_AUX_CH_CTL_MESSAGE_SIZE_MASK);
> + DP_AUX_CH_CTL_MESSAGE_SIZE(ret_msg_size);
>
> if (msg_length == 3) {
> if (!(op & GVT_AUX_I2C_MOT)) {
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-05-11 5:40 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-09 17:14 [Intel-gfx] [PATCH] drm/i915: Use REG_BIT() & co. for AUX CH registers Ville Syrjala
2023-05-09 19:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-05-09 19:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-05-09 22:14 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-05-11 5:40 ` [Intel-gfx] [PATCH] " Hogander, Jouni
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