* [PATCH v3 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
@ 2023-05-09 19:10 ` Fabio Estevam
0 siblings, 0 replies; 6+ messages in thread
From: Fabio Estevam @ 2023-05-09 19:10 UTC (permalink / raw)
To: neil.armstrong
Cc: dri-devel, robh+dt, krzysztof.kozlowski+dt, devicetree, jagan,
Fabio Estevam
From: Fabio Estevam <festevam@denx.de>
The Samsung DSIM IP block allows the inversion of the clock and
data lanes.
Add an optional property called 'lane-polarities' that describes the
polarities of the MIPI DSI clock and data lanes.
This property is useful for properly describing the hardware when the
board designer decided to switch the polarities of the MIPI DSI
clock and/or data lanes.
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Changes since v2:
- Use video-interfaces.yaml (Rob).
.../display/bridge/samsung,mipi-dsim.yaml | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
index e841659e20cd..dad6d06fbdd9 100644
--- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -105,6 +105,35 @@ properties:
DSI output port node to the panel or the next bridge
in the chain.
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ oneOf:
+ - minItems: 1
+ maxItems: 4
+ uniqueItems: true
+ items:
+ enum: [ 1, 2, 3, 4 ]
+ description:
+ See ../../media/video-interfaces.yaml for details.
+
+ lane-polarities:
+ minItems: 1
+ maxItems: 5
+ items:
+ enum: [ 0, 1 ]
+ description:
+ See ../../media/video-interfaces.yaml for details.
+ The Samsung MIPI DSI IP requires that all the data lanes have
+ the same polarity.
+
+ dependencies:
+ lane-polarities: [data-lanes]
+
required:
- clock-names
- clocks
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
@ 2023-05-09 19:10 ` Fabio Estevam
0 siblings, 0 replies; 6+ messages in thread
From: Fabio Estevam @ 2023-05-09 19:10 UTC (permalink / raw)
To: neil.armstrong
Cc: devicetree, Fabio Estevam, dri-devel, robh+dt, jagan,
krzysztof.kozlowski+dt
From: Fabio Estevam <festevam@denx.de>
The Samsung DSIM IP block allows the inversion of the clock and
data lanes.
Add an optional property called 'lane-polarities' that describes the
polarities of the MIPI DSI clock and data lanes.
This property is useful for properly describing the hardware when the
board designer decided to switch the polarities of the MIPI DSI
clock and/or data lanes.
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Changes since v2:
- Use video-interfaces.yaml (Rob).
.../display/bridge/samsung,mipi-dsim.yaml | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
index e841659e20cd..dad6d06fbdd9 100644
--- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -105,6 +105,35 @@ properties:
DSI output port node to the panel or the next bridge
in the chain.
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ oneOf:
+ - minItems: 1
+ maxItems: 4
+ uniqueItems: true
+ items:
+ enum: [ 1, 2, 3, 4 ]
+ description:
+ See ../../media/video-interfaces.yaml for details.
+
+ lane-polarities:
+ minItems: 1
+ maxItems: 5
+ items:
+ enum: [ 0, 1 ]
+ description:
+ See ../../media/video-interfaces.yaml for details.
+ The Samsung MIPI DSI IP requires that all the data lanes have
+ the same polarity.
+
+ dependencies:
+ lane-polarities: [data-lanes]
+
required:
- clock-names
- clocks
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/2] drm: bridge: samsung-dsim: Implement support for clock/data polarity swap
2023-05-09 19:10 ` Fabio Estevam
@ 2023-05-09 19:10 ` Fabio Estevam
-1 siblings, 0 replies; 6+ messages in thread
From: Fabio Estevam @ 2023-05-09 19:10 UTC (permalink / raw)
To: neil.armstrong
Cc: dri-devel, robh+dt, krzysztof.kozlowski+dt, devicetree, jagan,
Marek Vasut, Fabio Estevam
From: Marek Vasut <marex@denx.de>
Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.
This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes since v2:
- None
drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++++++++++++++++++++++++++-
include/drm/bridge/samsung-dsim.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
/* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
#define DSIM_FREQ_BAND(x) ((x) << 24)
#define DSIM_PLL_EN BIT(23)
#define DSIM_PLL_P(x, offset) ((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
reg |= DSIM_FREQ_BAND(band);
}
+ if (dsi->swap_dn_dp_clk)
+ reg |= DSIM_PLL_DPDNSWAP_CLK;
+ if (dsi->swap_dn_dp_data)
+ reg |= DSIM_PLL_DPDNSWAP_DAT;
+
samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
- int ret;
+ u32 lane_polarities[5] = { 0 };
+ struct device_node *endpoint;
+ int i, nr_lanes, ret;
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
&dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
if (ret < 0)
return ret;
+ endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+ nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+ if (nr_lanes > 0 && nr_lanes <= 4) {
+ /* Polarity 0 is clock lane, 1..4 are data lanes. */
+ of_property_read_u32_array(endpoint, "lane-polarities",
+ lane_polarities, nr_lanes + 1);
+ for (i = 1; i <= nr_lanes; i++) {
+ if (lane_polarities[1] != lane_polarities[i])
+ DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
+ }
+ if (lane_polarities[0])
+ dsi->swap_dn_dp_clk = true;
+ if (lane_polarities[1])
+ dsi->swap_dn_dp_data = true;
+ }
+
return 0;
}
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
u32 mode_flags;
u32 format;
+ bool swap_dn_dp_clk;
+ bool swap_dn_dp_data;
int state;
struct drm_property *brightness;
struct completion completed;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/2] drm: bridge: samsung-dsim: Implement support for clock/data polarity swap
@ 2023-05-09 19:10 ` Fabio Estevam
0 siblings, 0 replies; 6+ messages in thread
From: Fabio Estevam @ 2023-05-09 19:10 UTC (permalink / raw)
To: neil.armstrong
Cc: Marek Vasut, devicetree, Fabio Estevam, dri-devel, robh+dt,
jagan, krzysztof.kozlowski+dt
From: Marek Vasut <marex@denx.de>
Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.
This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes since v2:
- None
drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++++++++++++++++++++++++++-
include/drm/bridge/samsung-dsim.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
/* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
#define DSIM_FREQ_BAND(x) ((x) << 24)
#define DSIM_PLL_EN BIT(23)
#define DSIM_PLL_P(x, offset) ((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
reg |= DSIM_FREQ_BAND(band);
}
+ if (dsi->swap_dn_dp_clk)
+ reg |= DSIM_PLL_DPDNSWAP_CLK;
+ if (dsi->swap_dn_dp_data)
+ reg |= DSIM_PLL_DPDNSWAP_DAT;
+
samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
- int ret;
+ u32 lane_polarities[5] = { 0 };
+ struct device_node *endpoint;
+ int i, nr_lanes, ret;
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
&dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
if (ret < 0)
return ret;
+ endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+ nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+ if (nr_lanes > 0 && nr_lanes <= 4) {
+ /* Polarity 0 is clock lane, 1..4 are data lanes. */
+ of_property_read_u32_array(endpoint, "lane-polarities",
+ lane_polarities, nr_lanes + 1);
+ for (i = 1; i <= nr_lanes; i++) {
+ if (lane_polarities[1] != lane_polarities[i])
+ DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
+ }
+ if (lane_polarities[0])
+ dsi->swap_dn_dp_clk = true;
+ if (lane_polarities[1])
+ dsi->swap_dn_dp_data = true;
+ }
+
return 0;
}
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
u32 mode_flags;
u32 format;
+ bool swap_dn_dp_clk;
+ bool swap_dn_dp_data;
int state;
struct drm_property *brightness;
struct completion completed;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
2023-05-09 19:10 ` Fabio Estevam
@ 2023-05-14 10:05 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2023-05-14 10:05 UTC (permalink / raw)
To: Fabio Estevam, neil.armstrong
Cc: dri-devel, robh+dt, krzysztof.kozlowski+dt, devicetree, jagan,
Fabio Estevam
On 09/05/2023 21:10, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
>
> The Samsung DSIM IP block allows the inversion of the clock and
> data lanes.
>
> Add an optional property called 'lane-polarities' that describes the
> polarities of the MIPI DSI clock and data lanes.
>
> This property is useful for properly describing the hardware when the
> board designer decided to switch the polarities of the MIPI DSI
> clock and/or data lanes.
>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---
> Changes since v2:
> - Use video-interfaces.yaml (Rob).
>
> .../display/bridge/samsung,mipi-dsim.yaml | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
> index e841659e20cd..dad6d06fbdd9 100644
> --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
> @@ -105,6 +105,35 @@ properties:
> DSI output port node to the panel or the next bridge
> in the chain.
>
> + properties:
> + endpoint:
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + oneOf:
Drop oneOf, no need for it.
> + - minItems: 1
> + maxItems: 4
> + uniqueItems: true
> + items:
> + enum: [ 1, 2, 3, 4 ]
> + description:
> + See ../../media/video-interfaces.yaml for details.
Drop description, it's obvious.
> +
> + lane-polarities:
> + minItems: 1
> + maxItems: 5
> + items:
> + enum: [ 0, 1 ]
Drop items, it's already in video-interfaces.
> + description:
> + See ../../media/video-interfaces.yaml for details.
Drop this piece.
> + The Samsung MIPI DSI IP requires that all the data lanes have
> + the same polarity.
> +
> + dependencies:
> + lane-polarities: [data-lanes]
> +
> required:
> - clock-names
> - clocks
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
@ 2023-05-14 10:05 ` Krzysztof Kozlowski
0 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2023-05-14 10:05 UTC (permalink / raw)
To: Fabio Estevam, neil.armstrong
Cc: devicetree, Fabio Estevam, dri-devel, robh+dt, jagan,
krzysztof.kozlowski+dt
On 09/05/2023 21:10, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
>
> The Samsung DSIM IP block allows the inversion of the clock and
> data lanes.
>
> Add an optional property called 'lane-polarities' that describes the
> polarities of the MIPI DSI clock and data lanes.
>
> This property is useful for properly describing the hardware when the
> board designer decided to switch the polarities of the MIPI DSI
> clock and/or data lanes.
>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---
> Changes since v2:
> - Use video-interfaces.yaml (Rob).
>
> .../display/bridge/samsung,mipi-dsim.yaml | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
> index e841659e20cd..dad6d06fbdd9 100644
> --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
> @@ -105,6 +105,35 @@ properties:
> DSI output port node to the panel or the next bridge
> in the chain.
>
> + properties:
> + endpoint:
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + oneOf:
Drop oneOf, no need for it.
> + - minItems: 1
> + maxItems: 4
> + uniqueItems: true
> + items:
> + enum: [ 1, 2, 3, 4 ]
> + description:
> + See ../../media/video-interfaces.yaml for details.
Drop description, it's obvious.
> +
> + lane-polarities:
> + minItems: 1
> + maxItems: 5
> + items:
> + enum: [ 0, 1 ]
Drop items, it's already in video-interfaces.
> + description:
> + See ../../media/video-interfaces.yaml for details.
Drop this piece.
> + The Samsung MIPI DSI IP requires that all the data lanes have
> + the same polarity.
> +
> + dependencies:
> + lane-polarities: [data-lanes]
> +
> required:
> - clock-names
> - clocks
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-05-14 10:05 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-09 19:10 [PATCH v3 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities' Fabio Estevam
2023-05-09 19:10 ` Fabio Estevam
2023-05-09 19:10 ` [PATCH v3 2/2] drm: bridge: samsung-dsim: Implement support for clock/data polarity swap Fabio Estevam
2023-05-09 19:10 ` Fabio Estevam
2023-05-14 10:05 ` [PATCH v3 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities' Krzysztof Kozlowski
2023-05-14 10:05 ` Krzysztof Kozlowski
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.