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* [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-08 18:16 ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Palmer Dabbelt, Paul Walmsley, Heiko Stuebner,
	Andrew Jones, Sunil V L, Yangyu Chen, devicetree

From: Conor Dooley <conor.dooley@microchip.com>

Yo,

So here's some bits that I have been poking at on top of the recent bits
of ISA string parser work:
https://lore.kernel.org/linux-riscv/20230504-divisive-unsavory-5a2ff0c3c2d1@spud/

TL;DR is that I do not trust the riscv,isa property to carry sufficient
information to not cause us problems in the future.

Note that this is a very very early RFC, and the implementation etc is
intended to be *demonstrative* rather than acceptable.

Problem
=======

I've been kinda triggered by the whole "Zicsr and Zifencei are not part
of i" thing, where the dt-binding was defined prior to that split and
thus `i` means `zicsr_zifencei` without a real way to differentiate
between the two. From a Linux kernel point of view, it's "fine" because
we require require Zicsr and Zifencei, so a system without them will not
get far enough along for this problem to even manifest - but that's just
the example that we already have in front of us & we don't know what
might be done in the future when it comes to backwards-compatilibty
issues.

Yes you might say, expand the dt-binding to allow the version numbers,
as the Linux kernel's parser already supports strings containing the
version number (although it just ignores them). But that may not be the
case for any other consumer of the riscv,isa property - and such an
expansion of the dt-binding may actually cause them problems. A valid
parser for the current dt-binding may very well fall over if it is
expanded to allow free-form numbering.

Secondly, it is not realistic to maintain a list of every possible
version that someone may insert for every extension to do an explicit
comparison, nor can we rely on RVI interpreting "backwards compatible"
in a way that means software intended for the older version will still
run. (Or for that matter, can we rely on vendors *at all*).
If we could rely on that, then we could at least read "x2p2" and realise
that we can fall back to "x2p0", but I don't think we have that luxury.

The other thought I had was that perhaps some software may choose not to
implement version x.y.0 of an extension and only support x.z.0, z > y
for some reason. We'd want to refuse that extension if the extension is
found, but the version is not listed as being something compatible with
x.z.0, and while the ISA spec does say that the default assumption is
2p0 for unversioned extensions in its current form, I struggle to
extrapolate that to extensions not currently part of the unpriv spec,
but rather defined on their own.

Proposal
========

Instead, I propose a per-extension key/value property, for example
riscv,isa-extension-v = "v1.0.0"
in the style of compatible strings - so the value is not what hardware
implements, but rather the minimum-known version for which the
programming model is compatible.
Until something comes along that is not compatible with v1.0.0 that we
want to support in the kernel, no new keys need to be added to the
kernel, just changes to the dt-binding.

The binding for it is currently set up so that either you need to
be compatible version with v1.0.0, or add a special case. Although
v1.0.0 in this case is just a placeholder number, it could be v2.0.0 or
any other number. It could even be "initial" to something like that, to
match against whatever the first released spec version is.

	As an aside, the dt-binding doesn't actually work properly for
	enforcement etc at present, but I wanted to get some feedback
	before going too far down the rabbit hole there.

This method gives us the implemented version -> compatible version "for
free", as it is done by the creator of the DT, rather than software
running on the platform.
We can hopefully be strict about what people are inserting version wise,
using dt-validate, rather than it being pot-luck as to what gets filled in,
if anything.
I'm very reluctant to add more complexity to the property, and therefore
parsers, when a key-value type interface is more easily used with
standard OF functions - of_property_present(), of_property_read_string()
etc to use the Linux kernel's examples.

Another benefit of this approach is that we, by way of the dt-binding,
control the meaning of the versions.
If a vendor decides to release something using Xfoo, but provides no
version information, we can then assign one ourselves in case Xfoo in
their next SoC is not quite the same. Something similar came up this
morning, talking with Heiko about the TH1520, and how to explain the
meaning of "_xfoo" properties in "riscv,isa". The ISA spec documentation
is pointed to by the binding for that, but vendor properties are
obviously not described there. At the expensive of bloating the binding
file, the proposed scheme would provide a way to stably document vendor
properties.

I guess I am trying to design in some flexibility rather than two years
down the line realise that the isa string is a source of problems, and
have to try and retrofit something in.

I would like to encourage people to populate their DT with every
extension under the sun that they support, even if software doesn't use
it right now (look at the starfive folk that didn't add the bitmanip
until told to) so that if/when it is used in the future these boards
will pick up the support automagically.

ACPI
====

This whole proposal is written for a pre-ACPI world, and I have yet to
give any thought to how such a key-value interface would work there.
I'm not really sure how to deal with that, given they have some ECR
process yada yada, but thoughts on that side of things would be very
much appreciated.

Why x.y.z rather than x.y per the ISA specs?
============================================

I said the same, Palmer wanted x.y.z. For example, the T-HEAD vector stuff
is 0.7.1 & he cited an example (that now eludes me) of a breaking change
in an extension between 1.0 and 1.0.1. God knows how vendors will choose
to version things, so having the extra level is likely advantageous.

Other stuff
===========

The code here is very much in an RFC state. I tested it on an Icicle kit
as a PoC - and it does work, but I have not even remotely tested it
sufficiently.

The dt-binding changes need to be worked on as they do not actually
enforce anything!

I've intentionally only send this to the linux lists, despite this
having wider impact, as it is in a very early state & there's no point
involving all & sundry if the idea is hated.
If it is not universally derided, I will send the binding patches to
various other lists also.

What do I hate about this?
==========================

I fear bloat in the dt-binding and devicetrees as properties are added
mostly. Depending on what I have to do to get enforcement with
dt-validate, a complicated binding is also a concern.

Suggestions etc very much welcome :)

Cheers,
Conor.

CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Conor Dooley <conor+dt@kernel.org>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Heiko Stuebner <heiko@sntech.de>
CC: Andrew Jones <ajones@ventanamicro.com>
CC: Sunil V L <sunilvl@ventanamicro.com>
CC: Yangyu Chen <cyy@cyyself.name>
CC: devicetree@vger.kernel.org
CC: linux-riscv@lists.infradead.org

Conor Dooley (6):
  dt-bindings: riscv: clarify what an unversioned extension means
  dt-bindings: riscv: add riscv,isa-extension-* property and
    incompatible example
  RISC-V: deprecate riscv,isa & replace it with per-extension properties
  RISC-V: add support for riscv,isa-base property
  RISC-V: drop a needless check in print_isa_ext()
  riscv: dts: microchip: use new riscv,isa-extension-* properties for
    mpfs

 .../devicetree/bindings/riscv/cpus.yaml       |  64 +++++-
 arch/riscv/boot/dts/microchip/mpfs.dtsi       |  42 +++-
 arch/riscv/include/asm/hwcap.h                |  29 ++-
 arch/riscv/kernel/cpu.c                       | 124 +++---------
 arch/riscv/kernel/cpufeature.c                | 188 +++++++++++++++---
 5 files changed, 316 insertions(+), 131 deletions(-)

-- 
2.39.2


^ permalink raw reply	[flat|nested] 56+ messages in thread

* [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-08 18:16 ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: devicetree, Conor Dooley, Heiko Stuebner, conor, Yangyu Chen,
	Conor Dooley, Rob Herring, Palmer Dabbelt, Krzysztof Kozlowski,
	Paul Walmsley, Andrew Jones

From: Conor Dooley <conor.dooley@microchip.com>

Yo,

So here's some bits that I have been poking at on top of the recent bits
of ISA string parser work:
https://lore.kernel.org/linux-riscv/20230504-divisive-unsavory-5a2ff0c3c2d1@spud/

TL;DR is that I do not trust the riscv,isa property to carry sufficient
information to not cause us problems in the future.

Note that this is a very very early RFC, and the implementation etc is
intended to be *demonstrative* rather than acceptable.

Problem
=======

I've been kinda triggered by the whole "Zicsr and Zifencei are not part
of i" thing, where the dt-binding was defined prior to that split and
thus `i` means `zicsr_zifencei` without a real way to differentiate
between the two. From a Linux kernel point of view, it's "fine" because
we require require Zicsr and Zifencei, so a system without them will not
get far enough along for this problem to even manifest - but that's just
the example that we already have in front of us & we don't know what
might be done in the future when it comes to backwards-compatilibty
issues.

Yes you might say, expand the dt-binding to allow the version numbers,
as the Linux kernel's parser already supports strings containing the
version number (although it just ignores them). But that may not be the
case for any other consumer of the riscv,isa property - and such an
expansion of the dt-binding may actually cause them problems. A valid
parser for the current dt-binding may very well fall over if it is
expanded to allow free-form numbering.

Secondly, it is not realistic to maintain a list of every possible
version that someone may insert for every extension to do an explicit
comparison, nor can we rely on RVI interpreting "backwards compatible"
in a way that means software intended for the older version will still
run. (Or for that matter, can we rely on vendors *at all*).
If we could rely on that, then we could at least read "x2p2" and realise
that we can fall back to "x2p0", but I don't think we have that luxury.

The other thought I had was that perhaps some software may choose not to
implement version x.y.0 of an extension and only support x.z.0, z > y
for some reason. We'd want to refuse that extension if the extension is
found, but the version is not listed as being something compatible with
x.z.0, and while the ISA spec does say that the default assumption is
2p0 for unversioned extensions in its current form, I struggle to
extrapolate that to extensions not currently part of the unpriv spec,
but rather defined on their own.

Proposal
========

Instead, I propose a per-extension key/value property, for example
riscv,isa-extension-v = "v1.0.0"
in the style of compatible strings - so the value is not what hardware
implements, but rather the minimum-known version for which the
programming model is compatible.
Until something comes along that is not compatible with v1.0.0 that we
want to support in the kernel, no new keys need to be added to the
kernel, just changes to the dt-binding.

The binding for it is currently set up so that either you need to
be compatible version with v1.0.0, or add a special case. Although
v1.0.0 in this case is just a placeholder number, it could be v2.0.0 or
any other number. It could even be "initial" to something like that, to
match against whatever the first released spec version is.

	As an aside, the dt-binding doesn't actually work properly for
	enforcement etc at present, but I wanted to get some feedback
	before going too far down the rabbit hole there.

This method gives us the implemented version -> compatible version "for
free", as it is done by the creator of the DT, rather than software
running on the platform.
We can hopefully be strict about what people are inserting version wise,
using dt-validate, rather than it being pot-luck as to what gets filled in,
if anything.
I'm very reluctant to add more complexity to the property, and therefore
parsers, when a key-value type interface is more easily used with
standard OF functions - of_property_present(), of_property_read_string()
etc to use the Linux kernel's examples.

Another benefit of this approach is that we, by way of the dt-binding,
control the meaning of the versions.
If a vendor decides to release something using Xfoo, but provides no
version information, we can then assign one ourselves in case Xfoo in
their next SoC is not quite the same. Something similar came up this
morning, talking with Heiko about the TH1520, and how to explain the
meaning of "_xfoo" properties in "riscv,isa". The ISA spec documentation
is pointed to by the binding for that, but vendor properties are
obviously not described there. At the expensive of bloating the binding
file, the proposed scheme would provide a way to stably document vendor
properties.

I guess I am trying to design in some flexibility rather than two years
down the line realise that the isa string is a source of problems, and
have to try and retrofit something in.

I would like to encourage people to populate their DT with every
extension under the sun that they support, even if software doesn't use
it right now (look at the starfive folk that didn't add the bitmanip
until told to) so that if/when it is used in the future these boards
will pick up the support automagically.

ACPI
====

This whole proposal is written for a pre-ACPI world, and I have yet to
give any thought to how such a key-value interface would work there.
I'm not really sure how to deal with that, given they have some ECR
process yada yada, but thoughts on that side of things would be very
much appreciated.

Why x.y.z rather than x.y per the ISA specs?
============================================

I said the same, Palmer wanted x.y.z. For example, the T-HEAD vector stuff
is 0.7.1 & he cited an example (that now eludes me) of a breaking change
in an extension between 1.0 and 1.0.1. God knows how vendors will choose
to version things, so having the extra level is likely advantageous.

Other stuff
===========

The code here is very much in an RFC state. I tested it on an Icicle kit
as a PoC - and it does work, but I have not even remotely tested it
sufficiently.

The dt-binding changes need to be worked on as they do not actually
enforce anything!

I've intentionally only send this to the linux lists, despite this
having wider impact, as it is in a very early state & there's no point
involving all & sundry if the idea is hated.
If it is not universally derided, I will send the binding patches to
various other lists also.

What do I hate about this?
==========================

I fear bloat in the dt-binding and devicetrees as properties are added
mostly. Depending on what I have to do to get enforcement with
dt-validate, a complicated binding is also a concern.

Suggestions etc very much welcome :)

Cheers,
Conor.

CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Conor Dooley <conor+dt@kernel.org>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Heiko Stuebner <heiko@sntech.de>
CC: Andrew Jones <ajones@ventanamicro.com>
CC: Sunil V L <sunilvl@ventanamicro.com>
CC: Yangyu Chen <cyy@cyyself.name>
CC: devicetree@vger.kernel.org
CC: linux-riscv@lists.infradead.org

Conor Dooley (6):
  dt-bindings: riscv: clarify what an unversioned extension means
  dt-bindings: riscv: add riscv,isa-extension-* property and
    incompatible example
  RISC-V: deprecate riscv,isa & replace it with per-extension properties
  RISC-V: add support for riscv,isa-base property
  RISC-V: drop a needless check in print_isa_ext()
  riscv: dts: microchip: use new riscv,isa-extension-* properties for
    mpfs

 .../devicetree/bindings/riscv/cpus.yaml       |  64 +++++-
 arch/riscv/boot/dts/microchip/mpfs.dtsi       |  42 +++-
 arch/riscv/include/asm/hwcap.h                |  29 ++-
 arch/riscv/kernel/cpu.c                       | 124 +++---------
 arch/riscv/kernel/cpufeature.c                | 188 +++++++++++++++---
 5 files changed, 316 insertions(+), 131 deletions(-)

-- 
2.39.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* [RFC 1/6] dt-bindings: riscv: clarify what an unversioned extension means
  2023-05-08 18:16 ` Conor Dooley
@ 2023-05-08 18:16   ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Palmer Dabbelt, Paul Walmsley, Heiko Stuebner,
	Andrew Jones, Sunil V L, Yangyu Chen, devicetree

From: Conor Dooley <conor.dooley@microchip.com>

C'est la vie, the spec folks reserve the ability to make incompatible
changes between major versions of an extension. Their idea of backwards
compatibility appears driven by the hardware perspective - it's
backwards compatible if a later version is a subset of the existing
extension. IOW, if you supported `x` in vN, you still support `x` in
vN+1.
However in software terms, code that was built for the vN's `x`
extension may not work with the new definition.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index db5253a2a74a..405915b04d69 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -91,6 +91,9 @@ properties:
       Notably, riscv,isa was defined prior to the creation of the
       Zicsr and Zifencei extensions and thus "i" implies
       "zicsr_zifencei".
+      For the sake of backwards compatibility, an unversioned
+      extension means that the hart/platform is capable of
+      supporting version 1.0.0 of the extension.
 
       While the isa strings in ISA specification are case
       insensitive, letters in the riscv,isa string must be all
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 1/6] dt-bindings: riscv: clarify what an unversioned extension means
@ 2023-05-08 18:16   ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: devicetree, Conor Dooley, Heiko Stuebner, conor, Yangyu Chen,
	Conor Dooley, Rob Herring, Palmer Dabbelt, Krzysztof Kozlowski,
	Paul Walmsley, Andrew Jones

From: Conor Dooley <conor.dooley@microchip.com>

C'est la vie, the spec folks reserve the ability to make incompatible
changes between major versions of an extension. Their idea of backwards
compatibility appears driven by the hardware perspective - it's
backwards compatible if a later version is a subset of the existing
extension. IOW, if you supported `x` in vN, you still support `x` in
vN+1.
However in software terms, code that was built for the vN's `x`
extension may not work with the new definition.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index db5253a2a74a..405915b04d69 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -91,6 +91,9 @@ properties:
       Notably, riscv,isa was defined prior to the creation of the
       Zicsr and Zifencei extensions and thus "i" implies
       "zicsr_zifencei".
+      For the sake of backwards compatibility, an unversioned
+      extension means that the hart/platform is capable of
+      supporting version 1.0.0 of the extension.
 
       While the isa strings in ISA specification are case
       insensitive, letters in the riscv,isa string must be all
-- 
2.39.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 2/6] dt-bindings: riscv: add riscv,isa-extension-* property and incompatible example
  2023-05-08 18:16 ` Conor Dooley
@ 2023-05-08 18:16   ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Palmer Dabbelt, Paul Walmsley, Heiko Stuebner,
	Andrew Jones, Sunil V L, Yangyu Chen, devicetree

From: Conor Dooley <conor.dooley@microchip.com>

This dt-binding is illustrative *only*, it doesn't yet do what I want it
to do in terms of enforcement etc. I am yet to figure out exactly how to
wrangle the binding such that the individual properties have more
generous versions than the generic pattern property.
This binding *will* generate errors, and needs rework before it can
seriously be considered.
Nevertheless, it should demonstrate how I intend such a property be
used.

Not-signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/riscv/cpus.yaml       | 61 ++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 405915b04d69..cccb3b2ae23d 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -100,6 +100,15 @@ properties:
       lowercase.
     $ref: "/schemas/types.yaml#/definitions/string"
     pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
+    deprecated: true
+
+  riscv,isa-base:
+    description:
+      Identifies the base ISA supported by a hart.
+    $ref: "/schemas/types.yaml#/definitions/string"
+    enum:
+      - rv32i
+      - rv64i
 
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
@@ -136,8 +145,32 @@ properties:
       DMIPS/MHz, relative to highest capacity-dmips-mhz
       in the system.
 
+  riscv,isa-extension-v:
+    description: RISC-V Vector extension
+    $ref: "/schemas/types.yaml#/definitions/string"
+    oneOf:
+      - const: v1.0.0
+        description: the original incarnation
+      - const: v1.0.1
+        description: backwards compat was broken here
+
+patternProperties:
+  "^riscv,isa-extension-*":
+    description:
+      Catch-all property for ISA extensions that do not need any special
+      handling, and of which all known versions are compatible with their
+      original revision.
+    $ref: "/schemas/types.yaml#/definitions/string"
+    enum:
+      - v1.0.0
+
+oneOf:
+  - required:
+      - riscv,isa-base
+  - required:
+      - riscv,isa
+
 required:
-  - riscv,isa
   - interrupt-controller
 
 additionalProperties: true
@@ -208,4 +241,30 @@ examples:
                 };
         };
     };
+
+  - |
+    // Example 3: Extension specification
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        cpu@0 {
+                device_type = "cpu";
+                reg = <0>;
+                compatible = "riscv";
+                riscv,isa-base = "rv64i";
+                riscv,isa-extension-i = "v1.0.0";
+                riscv,isa-extension-m = "v1.0.0";
+                riscv,isa-extension-a = "v1.0.0";
+                riscv,isa-extension-f = "v1.0.0";
+                riscv,isa-extension-d = "v1.0.0";
+                riscv,isa-extension-c = "v2.0.0";
+                riscv,isa-extension-v = "v1.0.1";
+                mmu-type = "riscv,sv48";
+                interrupt-controller {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        compatible = "riscv,cpu-intc";
+                };
+        };
+    };
 ...
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 2/6] dt-bindings: riscv: add riscv,isa-extension-* property and incompatible example
@ 2023-05-08 18:16   ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: devicetree, Conor Dooley, Heiko Stuebner, conor, Yangyu Chen,
	Conor Dooley, Rob Herring, Palmer Dabbelt, Krzysztof Kozlowski,
	Paul Walmsley, Andrew Jones

From: Conor Dooley <conor.dooley@microchip.com>

This dt-binding is illustrative *only*, it doesn't yet do what I want it
to do in terms of enforcement etc. I am yet to figure out exactly how to
wrangle the binding such that the individual properties have more
generous versions than the generic pattern property.
This binding *will* generate errors, and needs rework before it can
seriously be considered.
Nevertheless, it should demonstrate how I intend such a property be
used.

Not-signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/riscv/cpus.yaml       | 61 ++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 405915b04d69..cccb3b2ae23d 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -100,6 +100,15 @@ properties:
       lowercase.
     $ref: "/schemas/types.yaml#/definitions/string"
     pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
+    deprecated: true
+
+  riscv,isa-base:
+    description:
+      Identifies the base ISA supported by a hart.
+    $ref: "/schemas/types.yaml#/definitions/string"
+    enum:
+      - rv32i
+      - rv64i
 
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
@@ -136,8 +145,32 @@ properties:
       DMIPS/MHz, relative to highest capacity-dmips-mhz
       in the system.
 
+  riscv,isa-extension-v:
+    description: RISC-V Vector extension
+    $ref: "/schemas/types.yaml#/definitions/string"
+    oneOf:
+      - const: v1.0.0
+        description: the original incarnation
+      - const: v1.0.1
+        description: backwards compat was broken here
+
+patternProperties:
+  "^riscv,isa-extension-*":
+    description:
+      Catch-all property for ISA extensions that do not need any special
+      handling, and of which all known versions are compatible with their
+      original revision.
+    $ref: "/schemas/types.yaml#/definitions/string"
+    enum:
+      - v1.0.0
+
+oneOf:
+  - required:
+      - riscv,isa-base
+  - required:
+      - riscv,isa
+
 required:
-  - riscv,isa
   - interrupt-controller
 
 additionalProperties: true
@@ -208,4 +241,30 @@ examples:
                 };
         };
     };
+
+  - |
+    // Example 3: Extension specification
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        cpu@0 {
+                device_type = "cpu";
+                reg = <0>;
+                compatible = "riscv";
+                riscv,isa-base = "rv64i";
+                riscv,isa-extension-i = "v1.0.0";
+                riscv,isa-extension-m = "v1.0.0";
+                riscv,isa-extension-a = "v1.0.0";
+                riscv,isa-extension-f = "v1.0.0";
+                riscv,isa-extension-d = "v1.0.0";
+                riscv,isa-extension-c = "v2.0.0";
+                riscv,isa-extension-v = "v1.0.1";
+                mmu-type = "riscv,sv48";
+                interrupt-controller {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        compatible = "riscv,cpu-intc";
+                };
+        };
+    };
 ...
-- 
2.39.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 3/6] RISC-V: deprecate riscv,isa & replace it with per-extension properties
  2023-05-08 18:16 ` Conor Dooley
@ 2023-05-08 18:16   ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Palmer Dabbelt, Paul Walmsley, Heiko Stuebner,
	Andrew Jones, Sunil V L, Yangyu Chen, devicetree

From: Conor Dooley <conor.dooley@microchip.com>

riscv,isa is a bit of a problem-in-waiting, as we don't have control
over what the extensions mean. Give us the ability to define what the
versions of an extension mean, and provide a compatible-like interface
for a dts to specify which known-version of an extension a hart is
compatible with.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/include/asm/hwcap.h |  25 +++++-
 arch/riscv/kernel/cpufeature.c | 147 +++++++++++++++++++++++++++------
 2 files changed, 146 insertions(+), 26 deletions(-)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index aa61031f7923..f963a7a82ce1 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -14,15 +14,20 @@
 #include <uapi/asm/hwcap.h>
 
 #define RISCV_ISA_EXT_a		('a' - 'a')
+#define RISCV_ISA_EXT_b		('b' - 'a')
 #define RISCV_ISA_EXT_c		('c' - 'a')
 #define RISCV_ISA_EXT_d		('d' - 'a')
 #define RISCV_ISA_EXT_f		('f' - 'a')
 #define RISCV_ISA_EXT_h		('h' - 'a')
 #define RISCV_ISA_EXT_i		('i' - 'a')
+#define RISCV_ISA_EXT_j		('j' - 'a')
+#define RISCV_ISA_EXT_k		('k' - 'a')
 #define RISCV_ISA_EXT_m		('m' - 'a')
+#define RISCV_ISA_EXT_p		('p' - 'a')
+#define RISCV_ISA_EXT_q		('q' - 'a')
 #define RISCV_ISA_EXT_s		('s' - 'a')
 #define RISCV_ISA_EXT_u		('u' - 'a')
-
+#define RISCV_ISA_EXT_v		('v' - 'a')
 /*
  * These macros represent the logical IDs of each multi-letter RISC-V ISA
  * extension and are used in the ISA bitmap. The logical IDs start from
@@ -61,6 +66,24 @@ struct riscv_isa_ext_data {
 	unsigned int isa_ext_id;
 };
 
+struct riscv_isa_extension {
+	const u64 key;
+	const char *name;
+	const char *version;
+	const char *prop_name;
+	const bool multi_letter;
+};
+
+#define RISCV_ISA_EXT_CFG(_name, _key, _version, _multi) {	\
+	.name = #_name,						\
+	.prop_name = "riscv,isa-extension-" #_name,		\
+	.key = _key,						\
+	.version = _version,					\
+	.multi_letter = _multi,					\
+}
+
+extern const struct riscv_isa_extension riscv_isa_extensions[];
+
 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
 
 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 92f0e7b78eef..1ead76adf60f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -93,12 +93,39 @@ static bool riscv_isa_extension_check(int id)
 	return true;
 }
 
-void __init riscv_fill_hwcap(void)
+const struct riscv_isa_extension riscv_isa_extensions[] = {
+	RISCV_ISA_EXT_CFG(i, RISCV_ISA_EXT_i, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(m, RISCV_ISA_EXT_m, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(a, RISCV_ISA_EXT_a, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(f, RISCV_ISA_EXT_f, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(d, RISCV_ISA_EXT_d, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(q, RISCV_ISA_EXT_q, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(c, RISCV_ISA_EXT_c, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(b, RISCV_ISA_EXT_b, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(k, RISCV_ISA_EXT_k, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(j, RISCV_ISA_EXT_j, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(p, RISCV_ISA_EXT_p, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(v, RISCV_ISA_EXT_v, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(h, RISCV_ISA_EXT_h, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(zicbom, RISCV_ISA_EXT_ZICBOM, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(zicboz, RISCV_ISA_EXT_ZICBOZ, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(zicsr, RISCV_ISA_EXT_ZICSR, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(zifencei, RISCV_ISA_EXT_ZIFENCEI, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(zbb, RISCV_ISA_EXT_ZBB, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(sscofpmf, RISCV_ISA_EXT_SSCOFPMF, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(sstc, RISCV_ISA_EXT_SSTC, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(svinval, RISCV_ISA_EXT_SVINVAL, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(svnapot, RISCV_ISA_EXT_SVNAPOT, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(svpbmt, RISCV_ISA_EXT_SVPBMT, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG("", RISCV_ISA_EXT_MAX, "", false),
+};
+
+static void __init riscv_fill_hwcap_isa_string(void)
 {
 	struct device_node *node;
 	const char *isa;
-	char print_str[NUM_ALPHA_EXTS + 1];
-	int i, j, rc;
+	int rc;
 	unsigned long isa2hwcap[26] = {0};
 	unsigned int cpu;
 
@@ -109,13 +136,12 @@ void __init riscv_fill_hwcap(void)
 	isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
 	isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
 
-	elf_hwcap = 0;
-
-	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
+	pr_info("Falling back to reading hwcap from deprecated riscv,isa\n");
 
 	for_each_possible_cpu(cpu) {
 		unsigned long this_hwcap = 0;
 		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
+		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
 
 		node = of_cpu_device_node_get(cpu);
 		if (!node) {
@@ -138,7 +164,6 @@ void __init riscv_fill_hwcap(void)
 		 */
 		isa += 4;
 
-		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
 		while (*isa) {
 			const char *ext = isa++;
 			const char *ext_end = isa;
@@ -278,26 +303,77 @@ void __init riscv_fill_hwcap(void)
 					set_bit(nr, this_isa);
 				}
 			} else {
-				/* sorted alphabetically */
-				SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
-				SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
-				SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
-				SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
-				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
-				SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
-				SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
-				SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
-				SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
+				for (int i = 0; i < ARRAY_SIZE(riscv_isa_extensions); i++)
+					SET_ISA_EXT_MAP(riscv_isa_extensions[i].name, riscv_isa_extensions[i].key);
 			}
 #undef SET_ISA_EXT_MAP
 		}
 
-		/*
-		 * Linux requires Zicsr & Zifencei, so we may as well always
-		 * set them.
-		 */
-		set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa);
-		set_bit(RISCV_ISA_EXT_ZICSR, this_isa);
+	/*
+	 * Linux requires Zicsr & Zifencei, so we may as well always
+	 * set them.
+	 */
+	set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa);
+	set_bit(RISCV_ISA_EXT_ZICSR, this_isa);
+
+	/*
+	 * All "okay" hart should have same isa. Set HWCAP based on
+	 * common capabilities of every "okay" hart, in case they don't
+	 * have.
+	 */
+	if (elf_hwcap)
+		elf_hwcap &= this_hwcap;
+	else
+		elf_hwcap = this_hwcap;
+
+	if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
+		bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+	else
+		bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+	}
+}
+
+static bool __init riscv_fill_hwcap_new(void)
+{
+	struct device_node *node;
+	bool detected;
+	unsigned long isa2hwcap[26] = {0};
+	unsigned int cpu;
+
+	isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
+	isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
+	isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
+	isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
+	isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
+	isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
+
+	for_each_possible_cpu(cpu) {
+		unsigned long this_hwcap = 0;
+		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
+
+		node = of_cpu_device_node_get(cpu);
+		if (!node) {
+			pr_warn("Unable to find cpu node\n");
+			continue;
+		}
+
+		for (int k = 0; k < ARRAY_SIZE(riscv_isa_extensions) - 1; k++) {
+			const char *tmp;
+
+			of_property_read_string(node, riscv_isa_extensions[k].prop_name, &tmp);
+			if (!tmp)
+				continue;
+
+			detected = true;
+
+			if (riscv_isa_extension_check(riscv_isa_extensions[k].key) &&
+			    !strcmp(riscv_isa_extensions[k].version, tmp)) {
+				if (!riscv_isa_extensions[k].multi_letter)
+					this_hwcap |= isa2hwcap[riscv_isa_extensions[k].key];
+
+				set_bit(riscv_isa_extensions[k].key, this_isa);
+			}
+		}
 
 		/*
 		 * All "okay" hart should have same isa. Set HWCAP based on
@@ -315,8 +391,29 @@ void __init riscv_fill_hwcap(void)
 			bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
 	}
 
-	/* We don't support systems with F but without D, so mask those out
-	 * here. */
+	return detected;
+}
+
+void __init riscv_fill_hwcap(void)
+{
+	char print_str[NUM_ALPHA_EXTS + 1];
+	int i, j;
+
+	elf_hwcap = 0;
+
+	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
+
+	/*
+	 * Since old dtbs must continue to work just as well/badly as they ever
+	 * did, fall back to the isa string if the new method doesn't work.
+	 */
+	if (!riscv_fill_hwcap_new())
+		riscv_fill_hwcap_isa_string();
+
+	/*
+	 * We don't support systems with F but without D, so mask those out
+	 * here.
+	 */
 	if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
 		pr_info("This kernel does not support systems with F but not D\n");
 		elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 3/6] RISC-V: deprecate riscv,isa & replace it with per-extension properties
@ 2023-05-08 18:16   ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: devicetree, Conor Dooley, Heiko Stuebner, conor, Yangyu Chen,
	Conor Dooley, Rob Herring, Palmer Dabbelt, Krzysztof Kozlowski,
	Paul Walmsley, Andrew Jones

From: Conor Dooley <conor.dooley@microchip.com>

riscv,isa is a bit of a problem-in-waiting, as we don't have control
over what the extensions mean. Give us the ability to define what the
versions of an extension mean, and provide a compatible-like interface
for a dts to specify which known-version of an extension a hart is
compatible with.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/include/asm/hwcap.h |  25 +++++-
 arch/riscv/kernel/cpufeature.c | 147 +++++++++++++++++++++++++++------
 2 files changed, 146 insertions(+), 26 deletions(-)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index aa61031f7923..f963a7a82ce1 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -14,15 +14,20 @@
 #include <uapi/asm/hwcap.h>
 
 #define RISCV_ISA_EXT_a		('a' - 'a')
+#define RISCV_ISA_EXT_b		('b' - 'a')
 #define RISCV_ISA_EXT_c		('c' - 'a')
 #define RISCV_ISA_EXT_d		('d' - 'a')
 #define RISCV_ISA_EXT_f		('f' - 'a')
 #define RISCV_ISA_EXT_h		('h' - 'a')
 #define RISCV_ISA_EXT_i		('i' - 'a')
+#define RISCV_ISA_EXT_j		('j' - 'a')
+#define RISCV_ISA_EXT_k		('k' - 'a')
 #define RISCV_ISA_EXT_m		('m' - 'a')
+#define RISCV_ISA_EXT_p		('p' - 'a')
+#define RISCV_ISA_EXT_q		('q' - 'a')
 #define RISCV_ISA_EXT_s		('s' - 'a')
 #define RISCV_ISA_EXT_u		('u' - 'a')
-
+#define RISCV_ISA_EXT_v		('v' - 'a')
 /*
  * These macros represent the logical IDs of each multi-letter RISC-V ISA
  * extension and are used in the ISA bitmap. The logical IDs start from
@@ -61,6 +66,24 @@ struct riscv_isa_ext_data {
 	unsigned int isa_ext_id;
 };
 
+struct riscv_isa_extension {
+	const u64 key;
+	const char *name;
+	const char *version;
+	const char *prop_name;
+	const bool multi_letter;
+};
+
+#define RISCV_ISA_EXT_CFG(_name, _key, _version, _multi) {	\
+	.name = #_name,						\
+	.prop_name = "riscv,isa-extension-" #_name,		\
+	.key = _key,						\
+	.version = _version,					\
+	.multi_letter = _multi,					\
+}
+
+extern const struct riscv_isa_extension riscv_isa_extensions[];
+
 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
 
 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 92f0e7b78eef..1ead76adf60f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -93,12 +93,39 @@ static bool riscv_isa_extension_check(int id)
 	return true;
 }
 
-void __init riscv_fill_hwcap(void)
+const struct riscv_isa_extension riscv_isa_extensions[] = {
+	RISCV_ISA_EXT_CFG(i, RISCV_ISA_EXT_i, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(m, RISCV_ISA_EXT_m, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(a, RISCV_ISA_EXT_a, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(f, RISCV_ISA_EXT_f, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(d, RISCV_ISA_EXT_d, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(q, RISCV_ISA_EXT_q, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(c, RISCV_ISA_EXT_c, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(b, RISCV_ISA_EXT_b, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(k, RISCV_ISA_EXT_k, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(j, RISCV_ISA_EXT_j, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(p, RISCV_ISA_EXT_p, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(v, RISCV_ISA_EXT_v, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(h, RISCV_ISA_EXT_h, "v1.0.0", false),
+	RISCV_ISA_EXT_CFG(zicbom, RISCV_ISA_EXT_ZICBOM, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(zicboz, RISCV_ISA_EXT_ZICBOZ, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(zicsr, RISCV_ISA_EXT_ZICSR, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(zifencei, RISCV_ISA_EXT_ZIFENCEI, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(zbb, RISCV_ISA_EXT_ZBB, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(sscofpmf, RISCV_ISA_EXT_SSCOFPMF, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(sstc, RISCV_ISA_EXT_SSTC, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(svinval, RISCV_ISA_EXT_SVINVAL, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(svnapot, RISCV_ISA_EXT_SVNAPOT, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG(svpbmt, RISCV_ISA_EXT_SVPBMT, "v1.0.0", true),
+	RISCV_ISA_EXT_CFG("", RISCV_ISA_EXT_MAX, "", false),
+};
+
+static void __init riscv_fill_hwcap_isa_string(void)
 {
 	struct device_node *node;
 	const char *isa;
-	char print_str[NUM_ALPHA_EXTS + 1];
-	int i, j, rc;
+	int rc;
 	unsigned long isa2hwcap[26] = {0};
 	unsigned int cpu;
 
@@ -109,13 +136,12 @@ void __init riscv_fill_hwcap(void)
 	isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
 	isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
 
-	elf_hwcap = 0;
-
-	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
+	pr_info("Falling back to reading hwcap from deprecated riscv,isa\n");
 
 	for_each_possible_cpu(cpu) {
 		unsigned long this_hwcap = 0;
 		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
+		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
 
 		node = of_cpu_device_node_get(cpu);
 		if (!node) {
@@ -138,7 +164,6 @@ void __init riscv_fill_hwcap(void)
 		 */
 		isa += 4;
 
-		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
 		while (*isa) {
 			const char *ext = isa++;
 			const char *ext_end = isa;
@@ -278,26 +303,77 @@ void __init riscv_fill_hwcap(void)
 					set_bit(nr, this_isa);
 				}
 			} else {
-				/* sorted alphabetically */
-				SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
-				SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
-				SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
-				SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
-				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
-				SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
-				SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
-				SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
-				SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
+				for (int i = 0; i < ARRAY_SIZE(riscv_isa_extensions); i++)
+					SET_ISA_EXT_MAP(riscv_isa_extensions[i].name, riscv_isa_extensions[i].key);
 			}
 #undef SET_ISA_EXT_MAP
 		}
 
-		/*
-		 * Linux requires Zicsr & Zifencei, so we may as well always
-		 * set them.
-		 */
-		set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa);
-		set_bit(RISCV_ISA_EXT_ZICSR, this_isa);
+	/*
+	 * Linux requires Zicsr & Zifencei, so we may as well always
+	 * set them.
+	 */
+	set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa);
+	set_bit(RISCV_ISA_EXT_ZICSR, this_isa);
+
+	/*
+	 * All "okay" hart should have same isa. Set HWCAP based on
+	 * common capabilities of every "okay" hart, in case they don't
+	 * have.
+	 */
+	if (elf_hwcap)
+		elf_hwcap &= this_hwcap;
+	else
+		elf_hwcap = this_hwcap;
+
+	if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
+		bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+	else
+		bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+	}
+}
+
+static bool __init riscv_fill_hwcap_new(void)
+{
+	struct device_node *node;
+	bool detected;
+	unsigned long isa2hwcap[26] = {0};
+	unsigned int cpu;
+
+	isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
+	isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
+	isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
+	isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
+	isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
+	isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
+
+	for_each_possible_cpu(cpu) {
+		unsigned long this_hwcap = 0;
+		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
+
+		node = of_cpu_device_node_get(cpu);
+		if (!node) {
+			pr_warn("Unable to find cpu node\n");
+			continue;
+		}
+
+		for (int k = 0; k < ARRAY_SIZE(riscv_isa_extensions) - 1; k++) {
+			const char *tmp;
+
+			of_property_read_string(node, riscv_isa_extensions[k].prop_name, &tmp);
+			if (!tmp)
+				continue;
+
+			detected = true;
+
+			if (riscv_isa_extension_check(riscv_isa_extensions[k].key) &&
+			    !strcmp(riscv_isa_extensions[k].version, tmp)) {
+				if (!riscv_isa_extensions[k].multi_letter)
+					this_hwcap |= isa2hwcap[riscv_isa_extensions[k].key];
+
+				set_bit(riscv_isa_extensions[k].key, this_isa);
+			}
+		}
 
 		/*
 		 * All "okay" hart should have same isa. Set HWCAP based on
@@ -315,8 +391,29 @@ void __init riscv_fill_hwcap(void)
 			bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
 	}
 
-	/* We don't support systems with F but without D, so mask those out
-	 * here. */
+	return detected;
+}
+
+void __init riscv_fill_hwcap(void)
+{
+	char print_str[NUM_ALPHA_EXTS + 1];
+	int i, j;
+
+	elf_hwcap = 0;
+
+	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
+
+	/*
+	 * Since old dtbs must continue to work just as well/badly as they ever
+	 * did, fall back to the isa string if the new method doesn't work.
+	 */
+	if (!riscv_fill_hwcap_new())
+		riscv_fill_hwcap_isa_string();
+
+	/*
+	 * We don't support systems with F but without D, so mask those out
+	 * here.
+	 */
 	if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
 		pr_info("This kernel does not support systems with F but not D\n");
 		elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
-- 
2.39.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 4/6] RISC-V: add support for riscv,isa-base property
  2023-05-08 18:16 ` Conor Dooley
@ 2023-05-08 18:16   ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Palmer Dabbelt, Paul Walmsley, Heiko Stuebner,
	Andrew Jones, Sunil V L, Yangyu Chen, devicetree

From: Conor Dooley <conor.dooley@microchip.com>

I'm not entirely sure if this is needed, but I felt we still needed a
mechanism for communicating the base ISA. Perhaps the i here should not
even be present, but a way to encode the bit-width is missing from my
key-value stuff. Very much open to suggestions on this aspect.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/include/asm/hwcap.h |   8 +--
 arch/riscv/kernel/cpu.c        | 119 +++++++++------------------------
 arch/riscv/kernel/cpufeature.c |  41 ++++++++++++
 3 files changed, 73 insertions(+), 95 deletions(-)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index f963a7a82ce1..cb4b3df0a5d5 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -59,13 +59,6 @@
 
 #include <linux/jump_label.h>
 
-struct riscv_isa_ext_data {
-	/* Name of the extension displayed to userspace via /proc/cpuinfo */
-	char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
-	/* The logical ISA extension ID */
-	unsigned int isa_ext_id;
-};
-
 struct riscv_isa_extension {
 	const u64 key;
 	const char *name;
@@ -83,6 +76,7 @@ struct riscv_isa_extension {
 }
 
 extern const struct riscv_isa_extension riscv_isa_extensions[];
+extern const size_t riscv_isa_extensions_count;
 
 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
 
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 0d5d580dca61..c29643dca0f7 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -59,8 +59,25 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
 		return -ENODEV;
 	}
 
+	if (of_property_read_string(node, "riscv,isa-base", &isa))
+		goto old_interface;
+
+	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5))
+		return -ENODEV;
+
+	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5))
+		return -ENODEV;
+
+	if (!of_property_present(node, "riscv,isa-extension-m") ||
+	    !of_property_present(node, "riscv,isa-extension-a"))
+		return -ENODEV;
+
+	return 0;
+
+old_interface:
 	if (of_property_read_string(node, "riscv,isa", &isa)) {
-		pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
+		pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
+			*hart);
 		return -ENODEV;
 	}
 
@@ -157,106 +174,33 @@ static int __init riscv_cpuinfo_init(void)
 arch_initcall(riscv_cpuinfo_init);
 
 #ifdef CONFIG_PROC_FS
-
-#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
-	{							\
-		.uprop = #UPROP,				\
-		.isa_ext_id = EXTID,				\
-	}
-
-/*
- * The canonical order of ISA extension names in the ISA string is defined in
- * chapter 27 of the unprivileged specification.
- *
- * Ordinarily, for in-kernel data structures, this order is unimportant but
- * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
- *
- * The specification uses vague wording, such as should, when it comes to
- * ordering, so for our purposes the following rules apply:
- *
- * 1. All multi-letter extensions must be separated from other extensions by an
- *    underscore.
- *
- * 2. Additional standard extensions (starting with 'Z') must be sorted after
- *    single-letter extensions and before any higher-privileged extensions.
-
- * 3. The first letter following the 'Z' conventionally indicates the most
- *    closely related alphabetical extension category, IMAFDQLCBKJTPVH.
- *    If multiple 'Z' extensions are named, they must be ordered first by
- *    category, then alphabetically within a category.
- *
- * 3. Standard supervisor-level extensions (starting with 'S') must be listed
- *    after standard unprivileged extensions.  If multiple supervisor-level
- *    extensions are listed, they must be ordered alphabetically.
- *
- * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
- *    after any lower-privileged, standard extensions.  If multiple
- *    machine-level extensions are listed, they must be ordered
- *    alphabetically.
- *
- * 5. Non-standard extensions (starting with 'X') must be listed after all
- *    standard extensions. If multiple non-standard extensions are listed, they
- *    must be ordered alphabetically.
- *
- * An example string following the order is:
- *    rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
- *
- * New entries to this struct should follow the ordering rules described above.
- */
-static struct riscv_isa_ext_data isa_ext_arr[] = {
-	__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
-	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
-	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
-	__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
-	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
-	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
-	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
-	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
-	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
-	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
-	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
-	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
-};
-
 static void print_isa_ext(struct seq_file *f)
 {
-	struct riscv_isa_ext_data *edata;
 	int i = 0, arr_sz;
 
-	arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
+	arr_sz = riscv_isa_extensions_count - 1;
 
 	/* No extension support available */
 	if (arr_sz <= 0)
 		return;
 
-	for (i = 0; i <= arr_sz; i++) {
-		edata = &isa_ext_arr[i];
-		if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
+	for (i = 0; i < arr_sz; i++) {
+		if (!__riscv_isa_extension_available(NULL, riscv_isa_extensions[i].key))
 			continue;
-		seq_printf(f, "_%s", edata->uprop);
+		if (riscv_isa_extensions[i].multi_letter)
+			seq_printf(f, "_");
+
+		seq_printf(f, "%s", riscv_isa_extensions[i].name);
 	}
 }
 
-/*
- * These are the only valid base (single letter) ISA extensions as per the spec.
- * It also specifies the canonical order in which it appears in the spec.
- * Some of the extension may just be a place holder for now (B, K, P, J).
- * This should be updated once corresponding extensions are ratified.
- */
-static const char base_riscv_exts[13] = "imafdqcbkjpvh";
-
-static void print_isa(struct seq_file *f, const char *isa)
+static void print_isa(struct seq_file *f)
 {
-	int i;
+	if (IS_ENABLED(CONFIG_64BIT))
+		seq_puts(f, "isa\t\t: rv64");
+	else
+		seq_puts(f, "isa\t\t: rv32");
 
-	seq_puts(f, "isa\t\t: ");
-	/* Print the rv[64/32] part */
-	seq_write(f, isa, 4);
-	for (i = 0; i < sizeof(base_riscv_exts); i++) {
-		if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
-			/* Print only enabled the base ISA extensions */
-			seq_write(f, &base_riscv_exts[i], 1);
-	}
 	print_isa_ext(f);
 	seq_puts(f, "\n");
 }
@@ -312,8 +256,7 @@ static int c_show(struct seq_file *m, void *v)
 
 	seq_printf(m, "processor\t: %lu\n", cpu_id);
 	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
-	if (!of_property_read_string(node, "riscv,isa", &isa))
-		print_isa(m, isa);
+	print_isa(m);
 	print_mmu(m);
 	if (!of_property_read_string(node, "compatible", &compat)
 	    && strcmp(compat, "riscv"))
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1ead76adf60f..d415a86a11e7 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -93,6 +93,45 @@ static bool riscv_isa_extension_check(int id)
 	return true;
 }
 
+/*
+ * The canonical order of ISA extension names in the ISA string is defined in
+ * chapter 27 of the unprivileged specification.
+ *
+ * Ordinarily, for in-kernel data structures, this order is unimportant but
+ * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
+ *
+ * The specification uses vague wording, such as should, when it comes to
+ * ordering, so for our purposes the following rules apply:
+ *
+ * 1. All multi-letter extensions must be separated from other extensions by an
+ *    underscore.
+ *
+ * 2. Additional standard extensions (starting with 'Z') must be sorted after
+ *    single-letter extensions and before any higher-privileged extensions.
+
+ * 3. The first letter following the 'Z' conventionally indicates the most
+ *    closely related alphabetical extension category, IMAFDQLCBKJTPVH.
+ *    If multiple 'Z' extensions are named, they must be ordered first by
+ *    category, then alphabetically within a category.
+ *
+ * 3. Standard supervisor-level extensions (starting with 'S') must be listed
+ *    after standard unprivileged extensions.  If multiple supervisor-level
+ *    extensions are listed, they must be ordered alphabetically.
+ *
+ * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
+ *    after any lower-privileged, standard extensions.  If multiple
+ *    machine-level extensions are listed, they must be ordered
+ *    alphabetically.
+ *
+ * 5. Non-standard extensions (starting with 'X') must be listed after all
+ *    standard extensions. If multiple non-standard extensions are listed, they
+ *    must be ordered alphabetically.
+ *
+ * An example string following the order is:
+ *    rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
+ *
+ * New entries to this struct should follow the ordering rules described above.
+ */
 const struct riscv_isa_extension riscv_isa_extensions[] = {
 	RISCV_ISA_EXT_CFG(i, RISCV_ISA_EXT_i, "v1.0.0", false),
 	RISCV_ISA_EXT_CFG(m, RISCV_ISA_EXT_m, "v1.0.0", false),
@@ -121,6 +160,8 @@ const struct riscv_isa_extension riscv_isa_extensions[] = {
 	RISCV_ISA_EXT_CFG("", RISCV_ISA_EXT_MAX, "", false),
 };
 
+const size_t riscv_isa_extensions_count = ARRAY_SIZE(riscv_isa_extensions);
+
 static void __init riscv_fill_hwcap_isa_string(void)
 {
 	struct device_node *node;
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 4/6] RISC-V: add support for riscv,isa-base property
@ 2023-05-08 18:16   ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: devicetree, Conor Dooley, Heiko Stuebner, conor, Yangyu Chen,
	Conor Dooley, Rob Herring, Palmer Dabbelt, Krzysztof Kozlowski,
	Paul Walmsley, Andrew Jones

From: Conor Dooley <conor.dooley@microchip.com>

I'm not entirely sure if this is needed, but I felt we still needed a
mechanism for communicating the base ISA. Perhaps the i here should not
even be present, but a way to encode the bit-width is missing from my
key-value stuff. Very much open to suggestions on this aspect.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/include/asm/hwcap.h |   8 +--
 arch/riscv/kernel/cpu.c        | 119 +++++++++------------------------
 arch/riscv/kernel/cpufeature.c |  41 ++++++++++++
 3 files changed, 73 insertions(+), 95 deletions(-)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index f963a7a82ce1..cb4b3df0a5d5 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -59,13 +59,6 @@
 
 #include <linux/jump_label.h>
 
-struct riscv_isa_ext_data {
-	/* Name of the extension displayed to userspace via /proc/cpuinfo */
-	char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
-	/* The logical ISA extension ID */
-	unsigned int isa_ext_id;
-};
-
 struct riscv_isa_extension {
 	const u64 key;
 	const char *name;
@@ -83,6 +76,7 @@ struct riscv_isa_extension {
 }
 
 extern const struct riscv_isa_extension riscv_isa_extensions[];
+extern const size_t riscv_isa_extensions_count;
 
 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
 
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 0d5d580dca61..c29643dca0f7 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -59,8 +59,25 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
 		return -ENODEV;
 	}
 
+	if (of_property_read_string(node, "riscv,isa-base", &isa))
+		goto old_interface;
+
+	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5))
+		return -ENODEV;
+
+	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5))
+		return -ENODEV;
+
+	if (!of_property_present(node, "riscv,isa-extension-m") ||
+	    !of_property_present(node, "riscv,isa-extension-a"))
+		return -ENODEV;
+
+	return 0;
+
+old_interface:
 	if (of_property_read_string(node, "riscv,isa", &isa)) {
-		pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
+		pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
+			*hart);
 		return -ENODEV;
 	}
 
@@ -157,106 +174,33 @@ static int __init riscv_cpuinfo_init(void)
 arch_initcall(riscv_cpuinfo_init);
 
 #ifdef CONFIG_PROC_FS
-
-#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
-	{							\
-		.uprop = #UPROP,				\
-		.isa_ext_id = EXTID,				\
-	}
-
-/*
- * The canonical order of ISA extension names in the ISA string is defined in
- * chapter 27 of the unprivileged specification.
- *
- * Ordinarily, for in-kernel data structures, this order is unimportant but
- * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
- *
- * The specification uses vague wording, such as should, when it comes to
- * ordering, so for our purposes the following rules apply:
- *
- * 1. All multi-letter extensions must be separated from other extensions by an
- *    underscore.
- *
- * 2. Additional standard extensions (starting with 'Z') must be sorted after
- *    single-letter extensions and before any higher-privileged extensions.
-
- * 3. The first letter following the 'Z' conventionally indicates the most
- *    closely related alphabetical extension category, IMAFDQLCBKJTPVH.
- *    If multiple 'Z' extensions are named, they must be ordered first by
- *    category, then alphabetically within a category.
- *
- * 3. Standard supervisor-level extensions (starting with 'S') must be listed
- *    after standard unprivileged extensions.  If multiple supervisor-level
- *    extensions are listed, they must be ordered alphabetically.
- *
- * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
- *    after any lower-privileged, standard extensions.  If multiple
- *    machine-level extensions are listed, they must be ordered
- *    alphabetically.
- *
- * 5. Non-standard extensions (starting with 'X') must be listed after all
- *    standard extensions. If multiple non-standard extensions are listed, they
- *    must be ordered alphabetically.
- *
- * An example string following the order is:
- *    rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
- *
- * New entries to this struct should follow the ordering rules described above.
- */
-static struct riscv_isa_ext_data isa_ext_arr[] = {
-	__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
-	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
-	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
-	__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
-	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
-	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
-	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
-	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
-	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
-	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
-	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
-	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
-};
-
 static void print_isa_ext(struct seq_file *f)
 {
-	struct riscv_isa_ext_data *edata;
 	int i = 0, arr_sz;
 
-	arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
+	arr_sz = riscv_isa_extensions_count - 1;
 
 	/* No extension support available */
 	if (arr_sz <= 0)
 		return;
 
-	for (i = 0; i <= arr_sz; i++) {
-		edata = &isa_ext_arr[i];
-		if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
+	for (i = 0; i < arr_sz; i++) {
+		if (!__riscv_isa_extension_available(NULL, riscv_isa_extensions[i].key))
 			continue;
-		seq_printf(f, "_%s", edata->uprop);
+		if (riscv_isa_extensions[i].multi_letter)
+			seq_printf(f, "_");
+
+		seq_printf(f, "%s", riscv_isa_extensions[i].name);
 	}
 }
 
-/*
- * These are the only valid base (single letter) ISA extensions as per the spec.
- * It also specifies the canonical order in which it appears in the spec.
- * Some of the extension may just be a place holder for now (B, K, P, J).
- * This should be updated once corresponding extensions are ratified.
- */
-static const char base_riscv_exts[13] = "imafdqcbkjpvh";
-
-static void print_isa(struct seq_file *f, const char *isa)
+static void print_isa(struct seq_file *f)
 {
-	int i;
+	if (IS_ENABLED(CONFIG_64BIT))
+		seq_puts(f, "isa\t\t: rv64");
+	else
+		seq_puts(f, "isa\t\t: rv32");
 
-	seq_puts(f, "isa\t\t: ");
-	/* Print the rv[64/32] part */
-	seq_write(f, isa, 4);
-	for (i = 0; i < sizeof(base_riscv_exts); i++) {
-		if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
-			/* Print only enabled the base ISA extensions */
-			seq_write(f, &base_riscv_exts[i], 1);
-	}
 	print_isa_ext(f);
 	seq_puts(f, "\n");
 }
@@ -312,8 +256,7 @@ static int c_show(struct seq_file *m, void *v)
 
 	seq_printf(m, "processor\t: %lu\n", cpu_id);
 	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
-	if (!of_property_read_string(node, "riscv,isa", &isa))
-		print_isa(m, isa);
+	print_isa(m);
 	print_mmu(m);
 	if (!of_property_read_string(node, "compatible", &compat)
 	    && strcmp(compat, "riscv"))
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1ead76adf60f..d415a86a11e7 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -93,6 +93,45 @@ static bool riscv_isa_extension_check(int id)
 	return true;
 }
 
+/*
+ * The canonical order of ISA extension names in the ISA string is defined in
+ * chapter 27 of the unprivileged specification.
+ *
+ * Ordinarily, for in-kernel data structures, this order is unimportant but
+ * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
+ *
+ * The specification uses vague wording, such as should, when it comes to
+ * ordering, so for our purposes the following rules apply:
+ *
+ * 1. All multi-letter extensions must be separated from other extensions by an
+ *    underscore.
+ *
+ * 2. Additional standard extensions (starting with 'Z') must be sorted after
+ *    single-letter extensions and before any higher-privileged extensions.
+
+ * 3. The first letter following the 'Z' conventionally indicates the most
+ *    closely related alphabetical extension category, IMAFDQLCBKJTPVH.
+ *    If multiple 'Z' extensions are named, they must be ordered first by
+ *    category, then alphabetically within a category.
+ *
+ * 3. Standard supervisor-level extensions (starting with 'S') must be listed
+ *    after standard unprivileged extensions.  If multiple supervisor-level
+ *    extensions are listed, they must be ordered alphabetically.
+ *
+ * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
+ *    after any lower-privileged, standard extensions.  If multiple
+ *    machine-level extensions are listed, they must be ordered
+ *    alphabetically.
+ *
+ * 5. Non-standard extensions (starting with 'X') must be listed after all
+ *    standard extensions. If multiple non-standard extensions are listed, they
+ *    must be ordered alphabetically.
+ *
+ * An example string following the order is:
+ *    rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
+ *
+ * New entries to this struct should follow the ordering rules described above.
+ */
 const struct riscv_isa_extension riscv_isa_extensions[] = {
 	RISCV_ISA_EXT_CFG(i, RISCV_ISA_EXT_i, "v1.0.0", false),
 	RISCV_ISA_EXT_CFG(m, RISCV_ISA_EXT_m, "v1.0.0", false),
@@ -121,6 +160,8 @@ const struct riscv_isa_extension riscv_isa_extensions[] = {
 	RISCV_ISA_EXT_CFG("", RISCV_ISA_EXT_MAX, "", false),
 };
 
+const size_t riscv_isa_extensions_count = ARRAY_SIZE(riscv_isa_extensions);
+
 static void __init riscv_fill_hwcap_isa_string(void)
 {
 	struct device_node *node;
-- 
2.39.2


_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 5/6] RISC-V: drop a needless check in print_isa_ext()
  2023-05-08 18:16 ` Conor Dooley
@ 2023-05-08 18:16   ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Palmer Dabbelt, Paul Walmsley, Heiko Stuebner,
	Andrew Jones, Sunil V L, Yangyu Chen, devicetree

From: Conor Dooley <conor.dooley@microchip.com>

There'll always be elements in the array, even if none of the
optional bits of support are built into the kernel.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/kernel/cpu.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c29643dca0f7..bc32207b7d86 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -176,15 +176,8 @@ arch_initcall(riscv_cpuinfo_init);
 #ifdef CONFIG_PROC_FS
 static void print_isa_ext(struct seq_file *f)
 {
-	int i = 0, arr_sz;
 
-	arr_sz = riscv_isa_extensions_count - 1;
-
-	/* No extension support available */
-	if (arr_sz <= 0)
-		return;
-
-	for (i = 0; i < arr_sz; i++) {
+	for (int i = 0; i < riscv_isa_extensions_count - 1; i++) {
 		if (!__riscv_isa_extension_available(NULL, riscv_isa_extensions[i].key))
 			continue;
 		if (riscv_isa_extensions[i].multi_letter)
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 5/6] RISC-V: drop a needless check in print_isa_ext()
@ 2023-05-08 18:16   ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: devicetree, Conor Dooley, Heiko Stuebner, conor, Yangyu Chen,
	Conor Dooley, Rob Herring, Palmer Dabbelt, Krzysztof Kozlowski,
	Paul Walmsley, Andrew Jones

From: Conor Dooley <conor.dooley@microchip.com>

There'll always be elements in the array, even if none of the
optional bits of support are built into the kernel.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/kernel/cpu.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c29643dca0f7..bc32207b7d86 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -176,15 +176,8 @@ arch_initcall(riscv_cpuinfo_init);
 #ifdef CONFIG_PROC_FS
 static void print_isa_ext(struct seq_file *f)
 {
-	int i = 0, arr_sz;
 
-	arr_sz = riscv_isa_extensions_count - 1;
-
-	/* No extension support available */
-	if (arr_sz <= 0)
-		return;
-
-	for (i = 0; i < arr_sz; i++) {
+	for (int i = 0; i < riscv_isa_extensions_count - 1; i++) {
 		if (!__riscv_isa_extension_available(NULL, riscv_isa_extensions[i].key))
 			continue;
 		if (riscv_isa_extensions[i].multi_letter)
-- 
2.39.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 6/6] riscv: dts: microchip: use new riscv,isa-extension-* properties for mpfs
  2023-05-08 18:16 ` Conor Dooley
@ 2023-05-08 18:16   ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Palmer Dabbelt, Paul Walmsley, Heiko Stuebner,
	Andrew Jones, Sunil V L, Yangyu Chen, devicetree

From: Conor Dooley <conor.dooley@microchip.com>

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 42 ++++++++++++++++++++++---
 1 file changed, 37 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 104504352e99..53efb5e03c64 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -21,7 +21,11 @@ cpu0: cpu@0 {
 			i-cache-sets = <128>;
 			i-cache-size = <16384>;
 			reg = <0>;
-			riscv,isa = "rv64imac";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			status = "disabled";
 
@@ -47,7 +51,14 @@ cpu1: cpu@1 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <1>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
@@ -75,7 +86,14 @@ cpu2: cpu@2 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <2>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
@@ -103,7 +121,14 @@ cpu3: cpu@3 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <3>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
@@ -131,7 +156,14 @@ cpu4: cpu@4 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <4>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 56+ messages in thread

* [RFC 6/6] riscv: dts: microchip: use new riscv,isa-extension-* properties for mpfs
@ 2023-05-08 18:16   ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-08 18:16 UTC (permalink / raw)
  To: linux-riscv
  Cc: devicetree, Conor Dooley, Heiko Stuebner, conor, Yangyu Chen,
	Conor Dooley, Rob Herring, Palmer Dabbelt, Krzysztof Kozlowski,
	Paul Walmsley, Andrew Jones

From: Conor Dooley <conor.dooley@microchip.com>

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 42 ++++++++++++++++++++++---
 1 file changed, 37 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 104504352e99..53efb5e03c64 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -21,7 +21,11 @@ cpu0: cpu@0 {
 			i-cache-sets = <128>;
 			i-cache-size = <16384>;
 			reg = <0>;
-			riscv,isa = "rv64imac";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			status = "disabled";
 
@@ -47,7 +51,14 @@ cpu1: cpu@1 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <1>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
@@ -75,7 +86,14 @@ cpu2: cpu@2 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <2>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
@@ -103,7 +121,14 @@ cpu3: cpu@3 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <3>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
@@ -131,7 +156,14 @@ cpu4: cpu@4 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			reg = <4>;
-			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extension-i = "v1.0.0";
+			riscv,isa-extension-m = "v1.0.0";
+			riscv,isa-extension-a = "v1.0.0";
+			riscv,isa-extension-f = "v1.0.0";
+			riscv,isa-extension-d = "v1.0.0";
+			riscv,isa-extension-c = "v1.0.0";
+			riscv,isa-extension-zicsr = "v1.0.0";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;
-- 
2.39.2


_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-08 18:16 ` Conor Dooley
@ 2023-05-11 21:27   ` Atish Patra
  -1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2023-05-11 21:27 UTC (permalink / raw)
  To: Conor Dooley
  Cc: linux-riscv, devicetree, Conor Dooley, Heiko Stuebner,
	Yangyu Chen, Conor Dooley, Rob Herring, Palmer Dabbelt,
	Krzysztof Kozlowski, Paul Walmsley, Andrew Jones

On Mon, May 8, 2023 at 11:20 AM Conor Dooley <conor@kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Yo,
>
> So here's some bits that I have been poking at on top of the recent bits
> of ISA string parser work:
> https://lore.kernel.org/linux-riscv/20230504-divisive-unsavory-5a2ff0c3c2d1@spud/
>
> TL;DR is that I do not trust the riscv,isa property to carry sufficient
> information to not cause us problems in the future.
>
> Note that this is a very very early RFC, and the implementation etc is
> intended to be *demonstrative* rather than acceptable.
>
> Problem
> =======
>
> I've been kinda triggered by the whole "Zicsr and Zifencei are not part
> of i" thing, where the dt-binding was defined prior to that split and
> thus `i` means `zicsr_zifencei` without a real way to differentiate
> between the two. From a Linux kernel point of view, it's "fine" because
> we require require Zicsr and Zifencei, so a system without them will not
> get far enough along for this problem to even manifest - but that's just
> the example that we already have in front of us & we don't know what
> might be done in the future when it comes to backwards-compatilibty
> issues.
>
> Yes you might say, expand the dt-binding to allow the version numbers,
> as the Linux kernel's parser already supports strings containing the
> version number (although it just ignores them). But that may not be the
> case for any other consumer of the riscv,isa property - and such an
> expansion of the dt-binding may actually cause them problems. A valid
> parser for the current dt-binding may very well fall over if it is
> expanded to allow free-form numbering.
>
> Secondly, it is not realistic to maintain a list of every possible
> version that someone may insert for every extension to do an explicit
> comparison, nor can we rely on RVI interpreting "backwards compatible"
> in a way that means software intended for the older version will still
> run. (Or for that matter, can we rely on vendors *at all*).
> If we could rely on that, then we could at least read "x2p2" and realise
> that we can fall back to "x2p0", but I don't think we have that luxury.
>
> The other thought I had was that perhaps some software may choose not to
> implement version x.y.0 of an extension and only support x.z.0, z > y
> for some reason. We'd want to refuse that extension if the extension is
> found, but the version is not listed as being something compatible with
> x.z.0, and while the ISA spec does say that the default assumption is
> 2p0 for unversioned extensions in its current form, I struggle to
> extrapolate that to extensions not currently part of the unpriv spec,
> but rather defined on their own.
>

That's a fair point. However, any new RVI ISA extension will only have v1.0
as per my knowledge. Any new feature will have to be part of a
different extension.
At least that was the plan discussed last year.

https://github.com/riscv/riscv-isa-manual/issues/781#issuecomment-983222655

Are you aware of any discussion that changes this ?

> Proposal
> ========
>
> Instead, I propose a per-extension key/value property, for example
> riscv,isa-extension-v = "v1.0.0"
> in the style of compatible strings - so the value is not what hardware
> implements, but rather the minimum-known version for which the
> programming model is compatible.
> Until something comes along that is not compatible with v1.0.0 that we
> want to support in the kernel, no new keys need to be added to the
> kernel, just changes to the dt-binding.
>
> The binding for it is currently set up so that either you need to
> be compatible version with v1.0.0, or add a special case. Although
> v1.0.0 in this case is just a placeholder number, it could be v2.0.0 or
> any other number. It could even be "initial" to something like that, to
> match against whatever the first released spec version is.
>
>         As an aside, the dt-binding doesn't actually work properly for
>         enforcement etc at present, but I wanted to get some feedback
>         before going too far down the rabbit hole there.
>
> This method gives us the implemented version -> compatible version "for
> free", as it is done by the creator of the DT, rather than software
> running on the platform.
> We can hopefully be strict about what people are inserting version wise,
> using dt-validate, rather than it being pot-luck as to what gets filled in,
> if anything.
> I'm very reluctant to add more complexity to the property, and therefore
> parsers, when a key-value type interface is more easily used with
> standard OF functions - of_property_present(), of_property_read_string()
> etc to use the Linux kernel's examples.
>
> Another benefit of this approach is that we, by way of the dt-binding,
> control the meaning of the versions.
> If a vendor decides to release something using Xfoo, but provides no
> version information, we can then assign one ourselves in case Xfoo in
> their next SoC is not quite the same. Something similar came up this
> morning, talking with Heiko about the TH1520, and how to explain the
> meaning of "_xfoo" properties in "riscv,isa". The ISA spec documentation
> is pointed to by the binding for that, but vendor properties are
> obviously not described there. At the expensive of bloating the binding
> file, the proposed scheme would provide a way to stably document vendor
> properties.
>
> I guess I am trying to design in some flexibility rather than two years
> down the line realise that the isa string is a source of problems, and
> have to try and retrofit something in.
>
> I would like to encourage people to populate their DT with every
> extension under the sun that they support, even if software doesn't use
> it right now (look at the starfive folk that didn't add the bitmanip
> until told to) so that if/when it is used in the future these boards
> will pick up the support automagically.
>
> ACPI
> ====
>
> This whole proposal is written for a pre-ACPI world, and I have yet to
> give any thought to how such a key-value interface would work there.
> I'm not really sure how to deal with that, given they have some ECR
> process yada yada, but thoughts on that side of things would be very
> much appreciated.
>
> Why x.y.z rather than x.y per the ISA specs?
> ============================================
>
> I said the same, Palmer wanted x.y.z. For example, the T-HEAD vector stuff
> is 0.7.1 & he cited an example (that now eludes me) of a breaking change
> in an extension between 1.0 and 1.0.1. God knows how vendors will choose
> to version things, so having the extra level is likely advantageous.
>
> Other stuff
> ===========
>
> The code here is very much in an RFC state. I tested it on an Icicle kit
> as a PoC - and it does work, but I have not even remotely tested it
> sufficiently.
>
> The dt-binding changes need to be worked on as they do not actually
> enforce anything!
>
> I've intentionally only send this to the linux lists, despite this
> having wider impact, as it is in a very early state & there's no point
> involving all & sundry if the idea is hated.
> If it is not universally derided, I will send the binding patches to
> various other lists also.
>
> What do I hate about this?
> ==========================
>
> I fear bloat in the dt-binding and devicetrees as properties are added
> mostly. Depending on what I have to do to get enforcement with
> dt-validate, a complicated binding is also a concern.
>
> Suggestions etc very much welcome :)
>
> Cheers,
> Conor.
>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> CC: Conor Dooley <conor+dt@kernel.org>
> CC: Palmer Dabbelt <palmer@dabbelt.com>
> CC: Paul Walmsley <paul.walmsley@sifive.com>
> CC: Heiko Stuebner <heiko@sntech.de>
> CC: Andrew Jones <ajones@ventanamicro.com>
> CC: Sunil V L <sunilvl@ventanamicro.com>
> CC: Yangyu Chen <cyy@cyyself.name>
> CC: devicetree@vger.kernel.org
> CC: linux-riscv@lists.infradead.org
>
> Conor Dooley (6):
>   dt-bindings: riscv: clarify what an unversioned extension means
>   dt-bindings: riscv: add riscv,isa-extension-* property and
>     incompatible example
>   RISC-V: deprecate riscv,isa & replace it with per-extension properties
>   RISC-V: add support for riscv,isa-base property
>   RISC-V: drop a needless check in print_isa_ext()
>   riscv: dts: microchip: use new riscv,isa-extension-* properties for
>     mpfs
>
>  .../devicetree/bindings/riscv/cpus.yaml       |  64 +++++-
>  arch/riscv/boot/dts/microchip/mpfs.dtsi       |  42 +++-
>  arch/riscv/include/asm/hwcap.h                |  29 ++-
>  arch/riscv/kernel/cpu.c                       | 124 +++---------
>  arch/riscv/kernel/cpufeature.c                | 188 +++++++++++++++---
>  5 files changed, 316 insertions(+), 131 deletions(-)
>
> --
> 2.39.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv



-- 
Regards,
Atish

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-11 21:27   ` Atish Patra
  0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2023-05-11 21:27 UTC (permalink / raw)
  To: Conor Dooley
  Cc: linux-riscv, devicetree, Conor Dooley, Heiko Stuebner,
	Yangyu Chen, Conor Dooley, Rob Herring, Palmer Dabbelt,
	Krzysztof Kozlowski, Paul Walmsley, Andrew Jones

On Mon, May 8, 2023 at 11:20 AM Conor Dooley <conor@kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Yo,
>
> So here's some bits that I have been poking at on top of the recent bits
> of ISA string parser work:
> https://lore.kernel.org/linux-riscv/20230504-divisive-unsavory-5a2ff0c3c2d1@spud/
>
> TL;DR is that I do not trust the riscv,isa property to carry sufficient
> information to not cause us problems in the future.
>
> Note that this is a very very early RFC, and the implementation etc is
> intended to be *demonstrative* rather than acceptable.
>
> Problem
> =======
>
> I've been kinda triggered by the whole "Zicsr and Zifencei are not part
> of i" thing, where the dt-binding was defined prior to that split and
> thus `i` means `zicsr_zifencei` without a real way to differentiate
> between the two. From a Linux kernel point of view, it's "fine" because
> we require require Zicsr and Zifencei, so a system without them will not
> get far enough along for this problem to even manifest - but that's just
> the example that we already have in front of us & we don't know what
> might be done in the future when it comes to backwards-compatilibty
> issues.
>
> Yes you might say, expand the dt-binding to allow the version numbers,
> as the Linux kernel's parser already supports strings containing the
> version number (although it just ignores them). But that may not be the
> case for any other consumer of the riscv,isa property - and such an
> expansion of the dt-binding may actually cause them problems. A valid
> parser for the current dt-binding may very well fall over if it is
> expanded to allow free-form numbering.
>
> Secondly, it is not realistic to maintain a list of every possible
> version that someone may insert for every extension to do an explicit
> comparison, nor can we rely on RVI interpreting "backwards compatible"
> in a way that means software intended for the older version will still
> run. (Or for that matter, can we rely on vendors *at all*).
> If we could rely on that, then we could at least read "x2p2" and realise
> that we can fall back to "x2p0", but I don't think we have that luxury.
>
> The other thought I had was that perhaps some software may choose not to
> implement version x.y.0 of an extension and only support x.z.0, z > y
> for some reason. We'd want to refuse that extension if the extension is
> found, but the version is not listed as being something compatible with
> x.z.0, and while the ISA spec does say that the default assumption is
> 2p0 for unversioned extensions in its current form, I struggle to
> extrapolate that to extensions not currently part of the unpriv spec,
> but rather defined on their own.
>

That's a fair point. However, any new RVI ISA extension will only have v1.0
as per my knowledge. Any new feature will have to be part of a
different extension.
At least that was the plan discussed last year.

https://github.com/riscv/riscv-isa-manual/issues/781#issuecomment-983222655

Are you aware of any discussion that changes this ?

> Proposal
> ========
>
> Instead, I propose a per-extension key/value property, for example
> riscv,isa-extension-v = "v1.0.0"
> in the style of compatible strings - so the value is not what hardware
> implements, but rather the minimum-known version for which the
> programming model is compatible.
> Until something comes along that is not compatible with v1.0.0 that we
> want to support in the kernel, no new keys need to be added to the
> kernel, just changes to the dt-binding.
>
> The binding for it is currently set up so that either you need to
> be compatible version with v1.0.0, or add a special case. Although
> v1.0.0 in this case is just a placeholder number, it could be v2.0.0 or
> any other number. It could even be "initial" to something like that, to
> match against whatever the first released spec version is.
>
>         As an aside, the dt-binding doesn't actually work properly for
>         enforcement etc at present, but I wanted to get some feedback
>         before going too far down the rabbit hole there.
>
> This method gives us the implemented version -> compatible version "for
> free", as it is done by the creator of the DT, rather than software
> running on the platform.
> We can hopefully be strict about what people are inserting version wise,
> using dt-validate, rather than it being pot-luck as to what gets filled in,
> if anything.
> I'm very reluctant to add more complexity to the property, and therefore
> parsers, when a key-value type interface is more easily used with
> standard OF functions - of_property_present(), of_property_read_string()
> etc to use the Linux kernel's examples.
>
> Another benefit of this approach is that we, by way of the dt-binding,
> control the meaning of the versions.
> If a vendor decides to release something using Xfoo, but provides no
> version information, we can then assign one ourselves in case Xfoo in
> their next SoC is not quite the same. Something similar came up this
> morning, talking with Heiko about the TH1520, and how to explain the
> meaning of "_xfoo" properties in "riscv,isa". The ISA spec documentation
> is pointed to by the binding for that, but vendor properties are
> obviously not described there. At the expensive of bloating the binding
> file, the proposed scheme would provide a way to stably document vendor
> properties.
>
> I guess I am trying to design in some flexibility rather than two years
> down the line realise that the isa string is a source of problems, and
> have to try and retrofit something in.
>
> I would like to encourage people to populate their DT with every
> extension under the sun that they support, even if software doesn't use
> it right now (look at the starfive folk that didn't add the bitmanip
> until told to) so that if/when it is used in the future these boards
> will pick up the support automagically.
>
> ACPI
> ====
>
> This whole proposal is written for a pre-ACPI world, and I have yet to
> give any thought to how such a key-value interface would work there.
> I'm not really sure how to deal with that, given they have some ECR
> process yada yada, but thoughts on that side of things would be very
> much appreciated.
>
> Why x.y.z rather than x.y per the ISA specs?
> ============================================
>
> I said the same, Palmer wanted x.y.z. For example, the T-HEAD vector stuff
> is 0.7.1 & he cited an example (that now eludes me) of a breaking change
> in an extension between 1.0 and 1.0.1. God knows how vendors will choose
> to version things, so having the extra level is likely advantageous.
>
> Other stuff
> ===========
>
> The code here is very much in an RFC state. I tested it on an Icicle kit
> as a PoC - and it does work, but I have not even remotely tested it
> sufficiently.
>
> The dt-binding changes need to be worked on as they do not actually
> enforce anything!
>
> I've intentionally only send this to the linux lists, despite this
> having wider impact, as it is in a very early state & there's no point
> involving all & sundry if the idea is hated.
> If it is not universally derided, I will send the binding patches to
> various other lists also.
>
> What do I hate about this?
> ==========================
>
> I fear bloat in the dt-binding and devicetrees as properties are added
> mostly. Depending on what I have to do to get enforcement with
> dt-validate, a complicated binding is also a concern.
>
> Suggestions etc very much welcome :)
>
> Cheers,
> Conor.
>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> CC: Conor Dooley <conor+dt@kernel.org>
> CC: Palmer Dabbelt <palmer@dabbelt.com>
> CC: Paul Walmsley <paul.walmsley@sifive.com>
> CC: Heiko Stuebner <heiko@sntech.de>
> CC: Andrew Jones <ajones@ventanamicro.com>
> CC: Sunil V L <sunilvl@ventanamicro.com>
> CC: Yangyu Chen <cyy@cyyself.name>
> CC: devicetree@vger.kernel.org
> CC: linux-riscv@lists.infradead.org
>
> Conor Dooley (6):
>   dt-bindings: riscv: clarify what an unversioned extension means
>   dt-bindings: riscv: add riscv,isa-extension-* property and
>     incompatible example
>   RISC-V: deprecate riscv,isa & replace it with per-extension properties
>   RISC-V: add support for riscv,isa-base property
>   RISC-V: drop a needless check in print_isa_ext()
>   riscv: dts: microchip: use new riscv,isa-extension-* properties for
>     mpfs
>
>  .../devicetree/bindings/riscv/cpus.yaml       |  64 +++++-
>  arch/riscv/boot/dts/microchip/mpfs.dtsi       |  42 +++-
>  arch/riscv/include/asm/hwcap.h                |  29 ++-
>  arch/riscv/kernel/cpu.c                       | 124 +++---------
>  arch/riscv/kernel/cpufeature.c                | 188 +++++++++++++++---
>  5 files changed, 316 insertions(+), 131 deletions(-)
>
> --
> 2.39.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv



-- 
Regards,
Atish

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-11 21:27   ` Atish Patra
@ 2023-05-11 21:47     ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-11 21:47 UTC (permalink / raw)
  To: Atish Patra
  Cc: linux-riscv, devicetree, Conor Dooley, Heiko Stuebner,
	Yangyu Chen, Conor Dooley, Rob Herring, Palmer Dabbelt,
	Krzysztof Kozlowski, Paul Walmsley, Andrew Jones

[-- Attachment #1: Type: text/plain, Size: 1676 bytes --]

On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:

> > The other thought I had was that perhaps some software may choose not to
> > implement version x.y.0 of an extension and only support x.z.0, z > y
> > for some reason. We'd want to refuse that extension if the extension is
> > found, but the version is not listed as being something compatible with
> > x.z.0, and while the ISA spec does say that the default assumption is
> > 2p0 for unversioned extensions in its current form, I struggle to
> > extrapolate that to extensions not currently part of the unpriv spec,
> > but rather defined on their own.
> >
> 
> That's a fair point. However, any new RVI ISA extension will only have v1.0
> as per my knowledge. Any new feature will have to be part of a
> different extension.
> At least that was the plan discussed last year.

That's more than last year at this point, and nothing has changed in the
documentation! Talk's cheap, ehh?

> https://github.com/riscv/riscv-isa-manual/issues/781#issuecomment-983222655
> 
> Are you aware of any discussion that changes this ?

It's called "trust issues". I am far less worried about the addition of
new features though than the removal of existing ones.
Part of me fears for fence.i-less systems for example, but there would
be other ways to bodge around the mess if it comes to pass.
If we are *sure* that no extensions will modify features additively or
subtractively, then this may not be needed at all & I can avoid having
to bend dt-validate to my will.
We have no guarantees for vendor extensions on that front either,
they're free to do what they like w.r.t. versioning, no?

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-11 21:47     ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-11 21:47 UTC (permalink / raw)
  To: Atish Patra
  Cc: linux-riscv, devicetree, Conor Dooley, Heiko Stuebner,
	Yangyu Chen, Conor Dooley, Rob Herring, Palmer Dabbelt,
	Krzysztof Kozlowski, Paul Walmsley, Andrew Jones


[-- Attachment #1.1: Type: text/plain, Size: 1676 bytes --]

On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:

> > The other thought I had was that perhaps some software may choose not to
> > implement version x.y.0 of an extension and only support x.z.0, z > y
> > for some reason. We'd want to refuse that extension if the extension is
> > found, but the version is not listed as being something compatible with
> > x.z.0, and while the ISA spec does say that the default assumption is
> > 2p0 for unversioned extensions in its current form, I struggle to
> > extrapolate that to extensions not currently part of the unpriv spec,
> > but rather defined on their own.
> >
> 
> That's a fair point. However, any new RVI ISA extension will only have v1.0
> as per my knowledge. Any new feature will have to be part of a
> different extension.
> At least that was the plan discussed last year.

That's more than last year at this point, and nothing has changed in the
documentation! Talk's cheap, ehh?

> https://github.com/riscv/riscv-isa-manual/issues/781#issuecomment-983222655
> 
> Are you aware of any discussion that changes this ?

It's called "trust issues". I am far less worried about the addition of
new features though than the removal of existing ones.
Part of me fears for fence.i-less systems for example, but there would
be other ways to bodge around the mess if it comes to pass.
If we are *sure* that no extensions will modify features additively or
subtractively, then this may not be needed at all & I can avoid having
to bend dt-validate to my will.
We have no guarantees for vendor extensions on that front either,
they're free to do what they like w.r.t. versioning, no?

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-11 21:47     ` Conor Dooley
@ 2023-05-11 22:34       ` Atish Patra
  -1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2023-05-11 22:34 UTC (permalink / raw)
  To: Conor Dooley
  Cc: linux-riscv, devicetree, Conor Dooley, Heiko Stuebner,
	Yangyu Chen, Conor Dooley, Rob Herring, Palmer Dabbelt,
	Krzysztof Kozlowski, Paul Walmsley, Andrew Jones

On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
>
> > > The other thought I had was that perhaps some software may choose not to
> > > implement version x.y.0 of an extension and only support x.z.0, z > y
> > > for some reason. We'd want to refuse that extension if the extension is
> > > found, but the version is not listed as being something compatible with
> > > x.z.0, and while the ISA spec does say that the default assumption is
> > > 2p0 for unversioned extensions in its current form, I struggle to
> > > extrapolate that to extensions not currently part of the unpriv spec,
> > > but rather defined on their own.
> > >
> >
> > That's a fair point. However, any new RVI ISA extension will only have v1.0
> > as per my knowledge. Any new feature will have to be part of a
> > different extension.
> > At least that was the plan discussed last year.
>
> That's more than last year at this point, and nothing has changed in the
> documentation! Talk's cheap, ehh?
>

Yup. I will poke RVI folks to check if it still is the plan or changed !!

> > https://github.com/riscv/riscv-isa-manual/issues/781#issuecomment-983222655
> >
> > Are you aware of any discussion that changes this ?
>
> It's called "trust issues". I am far less worried about the addition of
> new features though than the removal of existing ones.
> Part of me fears for fence.i-less systems for example, but there would
> be other ways to bodge around the mess if it comes to pass.
> If we are *sure* that no extensions will modify features additively or
> subtractively, then this may not be needed at all & I can avoid having
> to bend dt-validate to my will.

Fair enough. Let's get some clarification first from RVI. It must be
documented in unpriv
spec. Otherwise, there is no point of promise :)

> We have no guarantees for vendor extensions on that front either,
> they're free to do what they like w.r.t. versioning, no?

Vendor extensions are wild west. Who knows what scheme they will use.
We will likely have a vendor specific string parsing logic. They can do whatever
in that to figure out the version if they require it.

-- 
Regards,
Atish

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-11 22:34       ` Atish Patra
  0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2023-05-11 22:34 UTC (permalink / raw)
  To: Conor Dooley
  Cc: linux-riscv, devicetree, Conor Dooley, Heiko Stuebner,
	Yangyu Chen, Conor Dooley, Rob Herring, Palmer Dabbelt,
	Krzysztof Kozlowski, Paul Walmsley, Andrew Jones

On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
>
> > > The other thought I had was that perhaps some software may choose not to
> > > implement version x.y.0 of an extension and only support x.z.0, z > y
> > > for some reason. We'd want to refuse that extension if the extension is
> > > found, but the version is not listed as being something compatible with
> > > x.z.0, and while the ISA spec does say that the default assumption is
> > > 2p0 for unversioned extensions in its current form, I struggle to
> > > extrapolate that to extensions not currently part of the unpriv spec,
> > > but rather defined on their own.
> > >
> >
> > That's a fair point. However, any new RVI ISA extension will only have v1.0
> > as per my knowledge. Any new feature will have to be part of a
> > different extension.
> > At least that was the plan discussed last year.
>
> That's more than last year at this point, and nothing has changed in the
> documentation! Talk's cheap, ehh?
>

Yup. I will poke RVI folks to check if it still is the plan or changed !!

> > https://github.com/riscv/riscv-isa-manual/issues/781#issuecomment-983222655
> >
> > Are you aware of any discussion that changes this ?
>
> It's called "trust issues". I am far less worried about the addition of
> new features though than the removal of existing ones.
> Part of me fears for fence.i-less systems for example, but there would
> be other ways to bodge around the mess if it comes to pass.
> If we are *sure* that no extensions will modify features additively or
> subtractively, then this may not be needed at all & I can avoid having
> to bend dt-validate to my will.

Fair enough. Let's get some clarification first from RVI. It must be
documented in unpriv
spec. Otherwise, there is no point of promise :)

> We have no guarantees for vendor extensions on that front either,
> they're free to do what they like w.r.t. versioning, no?

Vendor extensions are wild west. Who knows what scheme they will use.
We will likely have a vendor specific string parsing logic. They can do whatever
in that to figure out the version if they require it.

-- 
Regards,
Atish

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-11 22:34       ` Atish Patra
@ 2023-05-11 22:38         ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-11 22:38 UTC (permalink / raw)
  To: Atish Patra
  Cc: linux-riscv, devicetree, Conor Dooley, Heiko Stuebner,
	Yangyu Chen, Conor Dooley, Rob Herring, Palmer Dabbelt,
	Krzysztof Kozlowski, Paul Walmsley, Andrew Jones


[-- Attachment #1.1: Type: text/plain, Size: 581 bytes --]

On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:

> > That's more than last year at this point, and nothing has changed in the
> > documentation! Talk's cheap, ehh?
> >
> 
> Yup. I will poke RVI folks to check if it still is the plan or changed !!

Sounds good, thanks!

> We will likely have a vendor specific string parsing logic.

Complicating the parsing logic is the exact sort of crap that I want
to avoid.

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-11 22:38         ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-11 22:38 UTC (permalink / raw)
  To: Atish Patra
  Cc: linux-riscv, devicetree, Conor Dooley, Heiko Stuebner,
	Yangyu Chen, Conor Dooley, Rob Herring, Palmer Dabbelt,
	Krzysztof Kozlowski, Paul Walmsley, Andrew Jones

[-- Attachment #1: Type: text/plain, Size: 581 bytes --]

On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:

> > That's more than last year at this point, and nothing has changed in the
> > documentation! Talk's cheap, ehh?
> >
> 
> Yup. I will poke RVI folks to check if it still is the plan or changed !!

Sounds good, thanks!

> We will likely have a vendor specific string parsing logic.

Complicating the parsing logic is the exact sort of crap that I want
to avoid.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-11 22:38         ` Conor Dooley
@ 2023-05-12 18:01           ` Palmer Dabbelt
  -1 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2023-05-12 18:01 UTC (permalink / raw)
  To: Conor Dooley
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones

On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
>> On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
>> > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
>
>> > That's more than last year at this point, and nothing has changed in the
>> > documentation! Talk's cheap, ehh?
>> >
>> 
>> Yup. I will poke RVI folks to check if it still is the plan or changed !!
>
> Sounds good, thanks!
>
>> We will likely have a vendor specific string parsing logic.
>
> Complicating the parsing logic is the exact sort of crap that I want
> to avoid.

Ya, I think we're reallly overcomplicating things with the ISA strings.  
Let's just deprecate them and move to something that doesn't need all 
the bespoke string parsing.

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-12 18:01           ` Palmer Dabbelt
  0 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2023-05-12 18:01 UTC (permalink / raw)
  To: Conor Dooley
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones

On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
>> On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
>> > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
>
>> > That's more than last year at this point, and nothing has changed in the
>> > documentation! Talk's cheap, ehh?
>> >
>> 
>> Yup. I will poke RVI folks to check if it still is the plan or changed !!
>
> Sounds good, thanks!
>
>> We will likely have a vendor specific string parsing logic.
>
> Complicating the parsing logic is the exact sort of crap that I want
> to avoid.

Ya, I think we're reallly overcomplicating things with the ISA strings.  
Let's just deprecate them and move to something that doesn't need all 
the bespoke string parsing.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-11 21:27   ` Atish Patra
@ 2023-05-12 18:08     ` Palmer Dabbelt
  -1 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2023-05-12 18:08 UTC (permalink / raw)
  To: atishp
  Cc: Conor Dooley, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones

On Thu, 11 May 2023 14:27:44 PDT (-0700), atishp@atishpatra.org wrote:
> On Mon, May 8, 2023 at 11:20 AM Conor Dooley <conor@kernel.org> wrote:
>>
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> Yo,
>>
>> So here's some bits that I have been poking at on top of the recent bits
>> of ISA string parser work:
>> https://lore.kernel.org/linux-riscv/20230504-divisive-unsavory-5a2ff0c3c2d1@spud/
>>
>> TL;DR is that I do not trust the riscv,isa property to carry sufficient
>> information to not cause us problems in the future.
>>
>> Note that this is a very very early RFC, and the implementation etc is
>> intended to be *demonstrative* rather than acceptable.
>>
>> Problem
>> =======
>>
>> I've been kinda triggered by the whole "Zicsr and Zifencei are not part
>> of i" thing, where the dt-binding was defined prior to that split and
>> thus `i` means `zicsr_zifencei` without a real way to differentiate
>> between the two. From a Linux kernel point of view, it's "fine" because
>> we require require Zicsr and Zifencei, so a system without them will not
>> get far enough along for this problem to even manifest - but that's just
>> the example that we already have in front of us & we don't know what
>> might be done in the future when it comes to backwards-compatilibty
>> issues.
>>
>> Yes you might say, expand the dt-binding to allow the version numbers,
>> as the Linux kernel's parser already supports strings containing the
>> version number (although it just ignores them). But that may not be the
>> case for any other consumer of the riscv,isa property - and such an
>> expansion of the dt-binding may actually cause them problems. A valid
>> parser for the current dt-binding may very well fall over if it is
>> expanded to allow free-form numbering.
>>
>> Secondly, it is not realistic to maintain a list of every possible
>> version that someone may insert for every extension to do an explicit
>> comparison, nor can we rely on RVI interpreting "backwards compatible"
>> in a way that means software intended for the older version will still
>> run. (Or for that matter, can we rely on vendors *at all*).
>> If we could rely on that, then we could at least read "x2p2" and realise
>> that we can fall back to "x2p0", but I don't think we have that luxury.
>>
>> The other thought I had was that perhaps some software may choose not to
>> implement version x.y.0 of an extension and only support x.z.0, z > y
>> for some reason. We'd want to refuse that extension if the extension is
>> found, but the version is not listed as being something compatible with
>> x.z.0, and while the ISA spec does say that the default assumption is
>> 2p0 for unversioned extensions in its current form, I struggle to
>> extrapolate that to extensions not currently part of the unpriv spec,
>> but rather defined on their own.
>>
>
> That's a fair point. However, any new RVI ISA extension will only have v1.0
> as per my knowledge. Any new feature will have to be part of a
> different extension.
> At least that was the plan discussed last year.
>
> https://github.com/riscv/riscv-isa-manual/issues/781#issuecomment-983222655
>
> Are you aware of any discussion that changes this ?

That comment was made in November 2021.  The recently ratified list 
<https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions> has a 
bunch in November that I'm going to skip, but since then there's been:

* Zmmul: ratified at version 2.0
* Zawrs: ratified at version 1.01
* Ztso: ratified at version 1.0
* RV32E/RV64E: ratified at version 2.0
* Zicntr: ratified without a version
* Zihpm: ratified without a version
* Zc*: ratified at version 1.0 (which is newer than v1.0.1, v1.0.2, 
  v1.0.3, and v1.0.3-1).

So I think it doesn't really matter what some comment in a github issues 
says, there's still no consistent versioning scheme for the extensions.  

>
>> Proposal
>> ========
>>
>> Instead, I propose a per-extension key/value property, for example
>> riscv,isa-extension-v = "v1.0.0"
>> in the style of compatible strings - so the value is not what hardware
>> implements, but rather the minimum-known version for which the
>> programming model is compatible.
>> Until something comes along that is not compatible with v1.0.0 that we
>> want to support in the kernel, no new keys need to be added to the
>> kernel, just changes to the dt-binding.
>>
>> The binding for it is currently set up so that either you need to
>> be compatible version with v1.0.0, or add a special case. Although
>> v1.0.0 in this case is just a placeholder number, it could be v2.0.0 or
>> any other number. It could even be "initial" to something like that, to
>> match against whatever the first released spec version is.
>>
>>         As an aside, the dt-binding doesn't actually work properly for
>>         enforcement etc at present, but I wanted to get some feedback
>>         before going too far down the rabbit hole there.
>>
>> This method gives us the implemented version -> compatible version "for
>> free", as it is done by the creator of the DT, rather than software
>> running on the platform.
>> We can hopefully be strict about what people are inserting version wise,
>> using dt-validate, rather than it being pot-luck as to what gets filled in,
>> if anything.
>> I'm very reluctant to add more complexity to the property, and therefore
>> parsers, when a key-value type interface is more easily used with
>> standard OF functions - of_property_present(), of_property_read_string()
>> etc to use the Linux kernel's examples.
>>
>> Another benefit of this approach is that we, by way of the dt-binding,
>> control the meaning of the versions.
>> If a vendor decides to release something using Xfoo, but provides no
>> version information, we can then assign one ourselves in case Xfoo in
>> their next SoC is not quite the same. Something similar came up this
>> morning, talking with Heiko about the TH1520, and how to explain the
>> meaning of "_xfoo" properties in "riscv,isa". The ISA spec documentation
>> is pointed to by the binding for that, but vendor properties are
>> obviously not described there. At the expensive of bloating the binding
>> file, the proposed scheme would provide a way to stably document vendor
>> properties.
>>
>> I guess I am trying to design in some flexibility rather than two years
>> down the line realise that the isa string is a source of problems, and
>> have to try and retrofit something in.
>>
>> I would like to encourage people to populate their DT with every
>> extension under the sun that they support, even if software doesn't use
>> it right now (look at the starfive folk that didn't add the bitmanip
>> until told to) so that if/when it is used in the future these boards
>> will pick up the support automagically.
>>
>> ACPI
>> ====
>>
>> This whole proposal is written for a pre-ACPI world, and I have yet to
>> give any thought to how such a key-value interface would work there.
>> I'm not really sure how to deal with that, given they have some ECR
>> process yada yada, but thoughts on that side of things would be very
>> much appreciated.
>>
>> Why x.y.z rather than x.y per the ISA specs?
>> ============================================
>>
>> I said the same, Palmer wanted x.y.z. For example, the T-HEAD vector stuff
>> is 0.7.1 & he cited an example (that now eludes me) of a breaking change
>> in an extension between 1.0 and 1.0.1. God knows how vendors will choose
>> to version things, so having the extra level is likely advantageous.
>>
>> Other stuff
>> ===========
>>
>> The code here is very much in an RFC state. I tested it on an Icicle kit
>> as a PoC - and it does work, but I have not even remotely tested it
>> sufficiently.
>>
>> The dt-binding changes need to be worked on as they do not actually
>> enforce anything!
>>
>> I've intentionally only send this to the linux lists, despite this
>> having wider impact, as it is in a very early state & there's no point
>> involving all & sundry if the idea is hated.
>> If it is not universally derided, I will send the binding patches to
>> various other lists also.
>>
>> What do I hate about this?
>> ==========================
>>
>> I fear bloat in the dt-binding and devicetrees as properties are added
>> mostly. Depending on what I have to do to get enforcement with
>> dt-validate, a complicated binding is also a concern.
>>
>> Suggestions etc very much welcome :)
>>
>> Cheers,
>> Conor.
>>
>> CC: Rob Herring <robh+dt@kernel.org>
>> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
>> CC: Conor Dooley <conor+dt@kernel.org>
>> CC: Palmer Dabbelt <palmer@dabbelt.com>
>> CC: Paul Walmsley <paul.walmsley@sifive.com>
>> CC: Heiko Stuebner <heiko@sntech.de>
>> CC: Andrew Jones <ajones@ventanamicro.com>
>> CC: Sunil V L <sunilvl@ventanamicro.com>
>> CC: Yangyu Chen <cyy@cyyself.name>
>> CC: devicetree@vger.kernel.org
>> CC: linux-riscv@lists.infradead.org
>>
>> Conor Dooley (6):
>>   dt-bindings: riscv: clarify what an unversioned extension means
>>   dt-bindings: riscv: add riscv,isa-extension-* property and
>>     incompatible example
>>   RISC-V: deprecate riscv,isa & replace it with per-extension properties
>>   RISC-V: add support for riscv,isa-base property
>>   RISC-V: drop a needless check in print_isa_ext()
>>   riscv: dts: microchip: use new riscv,isa-extension-* properties for
>>     mpfs
>>
>>  .../devicetree/bindings/riscv/cpus.yaml       |  64 +++++-
>>  arch/riscv/boot/dts/microchip/mpfs.dtsi       |  42 +++-
>>  arch/riscv/include/asm/hwcap.h                |  29 ++-
>>  arch/riscv/kernel/cpu.c                       | 124 +++---------
>>  arch/riscv/kernel/cpufeature.c                | 188 +++++++++++++++---
>>  5 files changed, 316 insertions(+), 131 deletions(-)
>>
>> --
>> 2.39.2
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
>
> -- 
> Regards,
> Atish

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-12 18:08     ` Palmer Dabbelt
  0 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2023-05-12 18:08 UTC (permalink / raw)
  To: atishp
  Cc: Conor Dooley, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones

On Thu, 11 May 2023 14:27:44 PDT (-0700), atishp@atishpatra.org wrote:
> On Mon, May 8, 2023 at 11:20 AM Conor Dooley <conor@kernel.org> wrote:
>>
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> Yo,
>>
>> So here's some bits that I have been poking at on top of the recent bits
>> of ISA string parser work:
>> https://lore.kernel.org/linux-riscv/20230504-divisive-unsavory-5a2ff0c3c2d1@spud/
>>
>> TL;DR is that I do not trust the riscv,isa property to carry sufficient
>> information to not cause us problems in the future.
>>
>> Note that this is a very very early RFC, and the implementation etc is
>> intended to be *demonstrative* rather than acceptable.
>>
>> Problem
>> =======
>>
>> I've been kinda triggered by the whole "Zicsr and Zifencei are not part
>> of i" thing, where the dt-binding was defined prior to that split and
>> thus `i` means `zicsr_zifencei` without a real way to differentiate
>> between the two. From a Linux kernel point of view, it's "fine" because
>> we require require Zicsr and Zifencei, so a system without them will not
>> get far enough along for this problem to even manifest - but that's just
>> the example that we already have in front of us & we don't know what
>> might be done in the future when it comes to backwards-compatilibty
>> issues.
>>
>> Yes you might say, expand the dt-binding to allow the version numbers,
>> as the Linux kernel's parser already supports strings containing the
>> version number (although it just ignores them). But that may not be the
>> case for any other consumer of the riscv,isa property - and such an
>> expansion of the dt-binding may actually cause them problems. A valid
>> parser for the current dt-binding may very well fall over if it is
>> expanded to allow free-form numbering.
>>
>> Secondly, it is not realistic to maintain a list of every possible
>> version that someone may insert for every extension to do an explicit
>> comparison, nor can we rely on RVI interpreting "backwards compatible"
>> in a way that means software intended for the older version will still
>> run. (Or for that matter, can we rely on vendors *at all*).
>> If we could rely on that, then we could at least read "x2p2" and realise
>> that we can fall back to "x2p0", but I don't think we have that luxury.
>>
>> The other thought I had was that perhaps some software may choose not to
>> implement version x.y.0 of an extension and only support x.z.0, z > y
>> for some reason. We'd want to refuse that extension if the extension is
>> found, but the version is not listed as being something compatible with
>> x.z.0, and while the ISA spec does say that the default assumption is
>> 2p0 for unversioned extensions in its current form, I struggle to
>> extrapolate that to extensions not currently part of the unpriv spec,
>> but rather defined on their own.
>>
>
> That's a fair point. However, any new RVI ISA extension will only have v1.0
> as per my knowledge. Any new feature will have to be part of a
> different extension.
> At least that was the plan discussed last year.
>
> https://github.com/riscv/riscv-isa-manual/issues/781#issuecomment-983222655
>
> Are you aware of any discussion that changes this ?

That comment was made in November 2021.  The recently ratified list 
<https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions> has a 
bunch in November that I'm going to skip, but since then there's been:

* Zmmul: ratified at version 2.0
* Zawrs: ratified at version 1.01
* Ztso: ratified at version 1.0
* RV32E/RV64E: ratified at version 2.0
* Zicntr: ratified without a version
* Zihpm: ratified without a version
* Zc*: ratified at version 1.0 (which is newer than v1.0.1, v1.0.2, 
  v1.0.3, and v1.0.3-1).

So I think it doesn't really matter what some comment in a github issues 
says, there's still no consistent versioning scheme for the extensions.  

>
>> Proposal
>> ========
>>
>> Instead, I propose a per-extension key/value property, for example
>> riscv,isa-extension-v = "v1.0.0"
>> in the style of compatible strings - so the value is not what hardware
>> implements, but rather the minimum-known version for which the
>> programming model is compatible.
>> Until something comes along that is not compatible with v1.0.0 that we
>> want to support in the kernel, no new keys need to be added to the
>> kernel, just changes to the dt-binding.
>>
>> The binding for it is currently set up so that either you need to
>> be compatible version with v1.0.0, or add a special case. Although
>> v1.0.0 in this case is just a placeholder number, it could be v2.0.0 or
>> any other number. It could even be "initial" to something like that, to
>> match against whatever the first released spec version is.
>>
>>         As an aside, the dt-binding doesn't actually work properly for
>>         enforcement etc at present, but I wanted to get some feedback
>>         before going too far down the rabbit hole there.
>>
>> This method gives us the implemented version -> compatible version "for
>> free", as it is done by the creator of the DT, rather than software
>> running on the platform.
>> We can hopefully be strict about what people are inserting version wise,
>> using dt-validate, rather than it being pot-luck as to what gets filled in,
>> if anything.
>> I'm very reluctant to add more complexity to the property, and therefore
>> parsers, when a key-value type interface is more easily used with
>> standard OF functions - of_property_present(), of_property_read_string()
>> etc to use the Linux kernel's examples.
>>
>> Another benefit of this approach is that we, by way of the dt-binding,
>> control the meaning of the versions.
>> If a vendor decides to release something using Xfoo, but provides no
>> version information, we can then assign one ourselves in case Xfoo in
>> their next SoC is not quite the same. Something similar came up this
>> morning, talking with Heiko about the TH1520, and how to explain the
>> meaning of "_xfoo" properties in "riscv,isa". The ISA spec documentation
>> is pointed to by the binding for that, but vendor properties are
>> obviously not described there. At the expensive of bloating the binding
>> file, the proposed scheme would provide a way to stably document vendor
>> properties.
>>
>> I guess I am trying to design in some flexibility rather than two years
>> down the line realise that the isa string is a source of problems, and
>> have to try and retrofit something in.
>>
>> I would like to encourage people to populate their DT with every
>> extension under the sun that they support, even if software doesn't use
>> it right now (look at the starfive folk that didn't add the bitmanip
>> until told to) so that if/when it is used in the future these boards
>> will pick up the support automagically.
>>
>> ACPI
>> ====
>>
>> This whole proposal is written for a pre-ACPI world, and I have yet to
>> give any thought to how such a key-value interface would work there.
>> I'm not really sure how to deal with that, given they have some ECR
>> process yada yada, but thoughts on that side of things would be very
>> much appreciated.
>>
>> Why x.y.z rather than x.y per the ISA specs?
>> ============================================
>>
>> I said the same, Palmer wanted x.y.z. For example, the T-HEAD vector stuff
>> is 0.7.1 & he cited an example (that now eludes me) of a breaking change
>> in an extension between 1.0 and 1.0.1. God knows how vendors will choose
>> to version things, so having the extra level is likely advantageous.
>>
>> Other stuff
>> ===========
>>
>> The code here is very much in an RFC state. I tested it on an Icicle kit
>> as a PoC - and it does work, but I have not even remotely tested it
>> sufficiently.
>>
>> The dt-binding changes need to be worked on as they do not actually
>> enforce anything!
>>
>> I've intentionally only send this to the linux lists, despite this
>> having wider impact, as it is in a very early state & there's no point
>> involving all & sundry if the idea is hated.
>> If it is not universally derided, I will send the binding patches to
>> various other lists also.
>>
>> What do I hate about this?
>> ==========================
>>
>> I fear bloat in the dt-binding and devicetrees as properties are added
>> mostly. Depending on what I have to do to get enforcement with
>> dt-validate, a complicated binding is also a concern.
>>
>> Suggestions etc very much welcome :)
>>
>> Cheers,
>> Conor.
>>
>> CC: Rob Herring <robh+dt@kernel.org>
>> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
>> CC: Conor Dooley <conor+dt@kernel.org>
>> CC: Palmer Dabbelt <palmer@dabbelt.com>
>> CC: Paul Walmsley <paul.walmsley@sifive.com>
>> CC: Heiko Stuebner <heiko@sntech.de>
>> CC: Andrew Jones <ajones@ventanamicro.com>
>> CC: Sunil V L <sunilvl@ventanamicro.com>
>> CC: Yangyu Chen <cyy@cyyself.name>
>> CC: devicetree@vger.kernel.org
>> CC: linux-riscv@lists.infradead.org
>>
>> Conor Dooley (6):
>>   dt-bindings: riscv: clarify what an unversioned extension means
>>   dt-bindings: riscv: add riscv,isa-extension-* property and
>>     incompatible example
>>   RISC-V: deprecate riscv,isa & replace it with per-extension properties
>>   RISC-V: add support for riscv,isa-base property
>>   RISC-V: drop a needless check in print_isa_ext()
>>   riscv: dts: microchip: use new riscv,isa-extension-* properties for
>>     mpfs
>>
>>  .../devicetree/bindings/riscv/cpus.yaml       |  64 +++++-
>>  arch/riscv/boot/dts/microchip/mpfs.dtsi       |  42 +++-
>>  arch/riscv/include/asm/hwcap.h                |  29 ++-
>>  arch/riscv/kernel/cpu.c                       | 124 +++---------
>>  arch/riscv/kernel/cpufeature.c                | 188 +++++++++++++++---
>>  5 files changed, 316 insertions(+), 131 deletions(-)
>>
>> --
>> 2.39.2
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
>
> -- 
> Regards,
> Atish

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-12 18:01           ` Palmer Dabbelt
@ 2023-05-12 19:40             ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-12 19:40 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones

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On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > 
> > > > That's more than last year at this point, and nothing has changed in the
> > > > documentation! Talk's cheap, ehh?
> > > >
> > > 
> > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > 
> > Sounds good, thanks!

There has been some movement on that front, shall see where it goes
:upsidedown_smile:

> > > We will likely have a vendor specific string parsing logic.
> > 
> > Complicating the parsing logic is the exact sort of crap that I want
> > to avoid.
> 
> Ya, I think we're reallly overcomplicating things with the ISA strings.
> Let's just deprecate them and move to something that doesn't need all the
> bespoke string parsing.

Versioning aside, although that removes a large part of the motivation,
the interface becomes quite nice:
of_property_present(node, "riscv,isa-extension-zicbom")

That also gives us the ability to define what supported vendor
extensions actually mean in a dt-binding, which to me is a big win in
terms of the aforementioned "wild west".

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^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-12 19:40             ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-12 19:40 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones


[-- Attachment #1.1: Type: text/plain, Size: 1391 bytes --]

On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > 
> > > > That's more than last year at this point, and nothing has changed in the
> > > > documentation! Talk's cheap, ehh?
> > > >
> > > 
> > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > 
> > Sounds good, thanks!

There has been some movement on that front, shall see where it goes
:upsidedown_smile:

> > > We will likely have a vendor specific string parsing logic.
> > 
> > Complicating the parsing logic is the exact sort of crap that I want
> > to avoid.
> 
> Ya, I think we're reallly overcomplicating things with the ISA strings.
> Let's just deprecate them and move to something that doesn't need all the
> bespoke string parsing.

Versioning aside, although that removes a large part of the motivation,
the interface becomes quite nice:
of_property_present(node, "riscv,isa-extension-zicbom")

That also gives us the ability to define what supported vendor
extensions actually mean in a dt-binding, which to me is a big win in
terms of the aforementioned "wild west".

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-12 19:40             ` Conor Dooley
@ 2023-05-12 22:05               ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-12 22:05 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, Krste Asanovic, Andrew Waterman, Greg Favor,
	Mark Himelstein, Philipp Tomsich

[-- Attachment #1: Type: text/plain, Size: 3398 bytes --]

+CC Greg, Mark, Krste, Philipp, Andrew,

(this is LKML now, no top posting or html replies)

On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > 
> > > > > That's more than last year at this point, and nothing has changed in the
> > > > > documentation! Talk's cheap, ehh?
> > > > >
> > > > 
> > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > > 
> > > Sounds good, thanks!
> 
> There has been some movement on that front, shall see where it goes
> :upsidedown_smile:

There's been some off-list discussion prompted by Atish with some of the
RVI spec folk, from which the upshot __appears__ to be an understanding
that using version numbering to indicate removal of ISA features is a bad
idea.
I'm hoping that this results in the enshrinement of this in the ISA
specs, so that we have something concrete to point to as the basis for
not needing to handle version numbering. 
Certainly that'd be great for ACPI and remove concerns there.

> > > > We will likely have a vendor specific string parsing logic.
> > > 
> > > Complicating the parsing logic is the exact sort of crap that I want
> > > to avoid.
> > 
> > Ya, I think we're reallly overcomplicating things with the ISA strings.
> > Let's just deprecate them and move to something that doesn't need all the
> > bespoke string parsing.
> 
> Versioning aside, although that removes a large part of the motivation,
> the interface becomes quite nice:
> of_property_present(node, "riscv,isa-extension-zicbom")

My current feeling is that, rather than introducing a key-value type of
property, adding boolean properties for extensions is the way to go
here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
of the base extensions (and thus the removal of some features...).
Starting again with a new property would allow us to define extensions
as per their ratified state, rather than the intermediate & incompatible
states that we have currently got with "riscv,isa".
Such a model does rely on the strengthening of the wording in the
specification.

This had the advantage of being, as I mention above, even easier to
parse in software than the key-value pair business - but also is
trivially implemented in a dt-binding. What I have been trying to do
with the validation of the key-value stuff does not appear to be readily
doable!

(Another drawback that has come to mind is that we have no way to
validate whether mutually exclusive extensions have been added with
"riscv,isa")

> That also gives us the ability to define what supported vendor
> extensions actually mean in a dt-binding, which to me is a big win in
> terms of the aforementioned "wild west".

Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
and my feeling is that "riscv,isa" is not a mechanism where we can
easily handle meanings - especially for vendor stuff where there is
otherwise no centralised location for _xfoo -> feature mappings.

Cheers,
Conor.

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^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-12 22:05               ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-12 22:05 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, Krste Asanovic, Andrew Waterman, Greg Favor,
	Mark Himelstein, Philipp Tomsich


[-- Attachment #1.1: Type: text/plain, Size: 3398 bytes --]

+CC Greg, Mark, Krste, Philipp, Andrew,

(this is LKML now, no top posting or html replies)

On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > 
> > > > > That's more than last year at this point, and nothing has changed in the
> > > > > documentation! Talk's cheap, ehh?
> > > > >
> > > > 
> > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > > 
> > > Sounds good, thanks!
> 
> There has been some movement on that front, shall see where it goes
> :upsidedown_smile:

There's been some off-list discussion prompted by Atish with some of the
RVI spec folk, from which the upshot __appears__ to be an understanding
that using version numbering to indicate removal of ISA features is a bad
idea.
I'm hoping that this results in the enshrinement of this in the ISA
specs, so that we have something concrete to point to as the basis for
not needing to handle version numbering. 
Certainly that'd be great for ACPI and remove concerns there.

> > > > We will likely have a vendor specific string parsing logic.
> > > 
> > > Complicating the parsing logic is the exact sort of crap that I want
> > > to avoid.
> > 
> > Ya, I think we're reallly overcomplicating things with the ISA strings.
> > Let's just deprecate them and move to something that doesn't need all the
> > bespoke string parsing.
> 
> Versioning aside, although that removes a large part of the motivation,
> the interface becomes quite nice:
> of_property_present(node, "riscv,isa-extension-zicbom")

My current feeling is that, rather than introducing a key-value type of
property, adding boolean properties for extensions is the way to go
here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
of the base extensions (and thus the removal of some features...).
Starting again with a new property would allow us to define extensions
as per their ratified state, rather than the intermediate & incompatible
states that we have currently got with "riscv,isa".
Such a model does rely on the strengthening of the wording in the
specification.

This had the advantage of being, as I mention above, even easier to
parse in software than the key-value pair business - but also is
trivially implemented in a dt-binding. What I have been trying to do
with the validation of the key-value stuff does not appear to be readily
doable!

(Another drawback that has come to mind is that we have no way to
validate whether mutually exclusive extensions have been added with
"riscv,isa")

> That also gives us the ability to define what supported vendor
> extensions actually mean in a dt-binding, which to me is a big win in
> terms of the aforementioned "wild west".

Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
and my feeling is that "riscv,isa" is not a mechanism where we can
easily handle meanings - especially for vendor stuff where there is
otherwise no centralised location for _xfoo -> feature mappings.

Cheers,
Conor.

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-12 22:05               ` Conor Dooley
@ 2023-05-12 23:20                 ` Atish Patra
  -1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2023-05-12 23:20 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Palmer Dabbelt, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, Krste Asanovic, Andrew Waterman, Greg Favor,
	Mark Himelstein, Philipp Tomsich

On Fri, May 12, 2023 at 3:05 PM Conor Dooley <conor@kernel.org> wrote:
>
> +CC Greg, Mark, Krste, Philipp, Andrew,
>
> (this is LKML now, no top posting or html replies)
>
> On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > >
> > > > > > That's more than last year at this point, and nothing has changed in the
> > > > > > documentation! Talk's cheap, ehh?
> > > > > >
> > > > >
> > > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > > >
> > > > Sounds good, thanks!
> >
> > There has been some movement on that front, shall see where it goes
> > :upsidedown_smile:
>
> There's been some off-list discussion prompted by Atish with some of the
> RVI spec folk, from which the upshot __appears__ to be an understanding
> that using version numbering to indicate removal of ISA features is a bad
> idea.
> I'm hoping that this results in the enshrinement of this in the ISA
> specs, so that we have something concrete to point to as the basis for
> not needing to handle version numbering.
> Certainly that'd be great for ACPI and remove concerns there.
>
> > > > > We will likely have a vendor specific string parsing logic.
> > > >
> > > > Complicating the parsing logic is the exact sort of crap that I want
> > > > to avoid.
> > >
> > > Ya, I think we're reallly overcomplicating things with the ISA strings.
> > > Let's just deprecate them and move to something that doesn't need all the
> > > bespoke string parsing.
> >
> > Versioning aside, although that removes a large part of the motivation,
> > the interface becomes quite nice:
> > of_property_present(node, "riscv,isa-extension-zicbom")
>
> My current feeling is that, rather than introducing a key-value type of
> property, adding boolean properties for extensions is the way to go
> here. The "riscv,isa" part of the DT ABI pre-dates even the ratification

The only problem with boolean properties is you lose the ability to
add extra information
about an ISA extension in case we require it. One of the examples is
CMO extensions.
The current riscv,isa string parsing scheme that doesn't have
infrastructure to do that either.

We had some related discussions in the past about how to extend the
key-value pair to include
that value.

https://lore.kernel.org/lkml/CAOnJCUKgt1+SVXTBmGChJf74JrsqeqACXbjQAXnhFALkXhPFew@mail.gmail.com/

> of the base extensions (and thus the removal of some features...).
> Starting again with a new property would allow us to define extensions
> as per their ratified state, rather than the intermediate & incompatible
> states that we have currently got with "riscv,isa".
> Such a model does rely on the strengthening of the wording in the
> specification.
>
> This had the advantage of being, as I mention above, even easier to
> parse in software than the key-value pair business - but also is
> trivially implemented in a dt-binding. What I have been trying to do
> with the validation of the key-value stuff does not appear to be readily
> doable!
>
> (Another drawback that has come to mind is that we have no way to
> validate whether mutually exclusive extensions have been added with
> "riscv,isa")
>
> > That also gives us the ability to define what supported vendor
> > extensions actually mean in a dt-binding, which to me is a big win in
> > terms of the aforementioned "wild west".
>
> Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
> and my feeling is that "riscv,isa" is not a mechanism where we can
> easily handle meanings - especially for vendor stuff where there is
> otherwise no centralised location for _xfoo -> feature mappings.
>
> Cheers,
> Conor.



-- 
Regards,
Atish

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-12 23:20                 ` Atish Patra
  0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2023-05-12 23:20 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Palmer Dabbelt, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, Krste Asanovic, Andrew Waterman, Greg Favor,
	Mark Himelstein, Philipp Tomsich

On Fri, May 12, 2023 at 3:05 PM Conor Dooley <conor@kernel.org> wrote:
>
> +CC Greg, Mark, Krste, Philipp, Andrew,
>
> (this is LKML now, no top posting or html replies)
>
> On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > >
> > > > > > That's more than last year at this point, and nothing has changed in the
> > > > > > documentation! Talk's cheap, ehh?
> > > > > >
> > > > >
> > > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > > >
> > > > Sounds good, thanks!
> >
> > There has been some movement on that front, shall see where it goes
> > :upsidedown_smile:
>
> There's been some off-list discussion prompted by Atish with some of the
> RVI spec folk, from which the upshot __appears__ to be an understanding
> that using version numbering to indicate removal of ISA features is a bad
> idea.
> I'm hoping that this results in the enshrinement of this in the ISA
> specs, so that we have something concrete to point to as the basis for
> not needing to handle version numbering.
> Certainly that'd be great for ACPI and remove concerns there.
>
> > > > > We will likely have a vendor specific string parsing logic.
> > > >
> > > > Complicating the parsing logic is the exact sort of crap that I want
> > > > to avoid.
> > >
> > > Ya, I think we're reallly overcomplicating things with the ISA strings.
> > > Let's just deprecate them and move to something that doesn't need all the
> > > bespoke string parsing.
> >
> > Versioning aside, although that removes a large part of the motivation,
> > the interface becomes quite nice:
> > of_property_present(node, "riscv,isa-extension-zicbom")
>
> My current feeling is that, rather than introducing a key-value type of
> property, adding boolean properties for extensions is the way to go
> here. The "riscv,isa" part of the DT ABI pre-dates even the ratification

The only problem with boolean properties is you lose the ability to
add extra information
about an ISA extension in case we require it. One of the examples is
CMO extensions.
The current riscv,isa string parsing scheme that doesn't have
infrastructure to do that either.

We had some related discussions in the past about how to extend the
key-value pair to include
that value.

https://lore.kernel.org/lkml/CAOnJCUKgt1+SVXTBmGChJf74JrsqeqACXbjQAXnhFALkXhPFew@mail.gmail.com/

> of the base extensions (and thus the removal of some features...).
> Starting again with a new property would allow us to define extensions
> as per their ratified state, rather than the intermediate & incompatible
> states that we have currently got with "riscv,isa".
> Such a model does rely on the strengthening of the wording in the
> specification.
>
> This had the advantage of being, as I mention above, even easier to
> parse in software than the key-value pair business - but also is
> trivially implemented in a dt-binding. What I have been trying to do
> with the validation of the key-value stuff does not appear to be readily
> doable!
>
> (Another drawback that has come to mind is that we have no way to
> validate whether mutually exclusive extensions have been added with
> "riscv,isa")
>
> > That also gives us the ability to define what supported vendor
> > extensions actually mean in a dt-binding, which to me is a big win in
> > terms of the aforementioned "wild west".
>
> Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
> and my feeling is that "riscv,isa" is not a mechanism where we can
> easily handle meanings - especially for vendor stuff where there is
> otherwise no centralised location for _xfoo -> feature mappings.
>
> Cheers,
> Conor.



-- 
Regards,
Atish

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-12 23:20                 ` Atish Patra
@ 2023-05-12 23:52                   ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-12 23:52 UTC (permalink / raw)
  To: Atish Patra
  Cc: Palmer Dabbelt, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, Krste Asanovic, Andrew Waterman, Greg Favor,
	Mark Himelstein, Philipp Tomsich


[-- Attachment #1.1: Type: text/plain, Size: 6693 bytes --]

On Fri, May 12, 2023 at 04:20:43PM -0700, Atish Patra wrote:
> On Fri, May 12, 2023 at 3:05 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > +CC Greg, Mark, Krste, Philipp, Andrew,
> >
> > (this is LKML now, no top posting or html replies)
> >
> > On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> > > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > > >
> > > > > > > That's more than last year at this point, and nothing has changed in the
> > > > > > > documentation! Talk's cheap, ehh?
> > > > > > >
> > > > > >
> > > > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > > > >
> > > > > Sounds good, thanks!
> > >
> > > There has been some movement on that front, shall see where it goes
> > > :upsidedown_smile:
> >
> > There's been some off-list discussion prompted by Atish with some of the
> > RVI spec folk, from which the upshot __appears__ to be an understanding
> > that using version numbering to indicate removal of ISA features is a bad
> > idea.
> > I'm hoping that this results in the enshrinement of this in the ISA
> > specs, so that we have something concrete to point to as the basis for
> > not needing to handle version numbering.
> > Certainly that'd be great for ACPI and remove concerns there.
> >
> > > > > > We will likely have a vendor specific string parsing logic.
> > > > >
> > > > > Complicating the parsing logic is the exact sort of crap that I want
> > > > > to avoid.
> > > >
> > > > Ya, I think we're reallly overcomplicating things with the ISA strings.
> > > > Let's just deprecate them and move to something that doesn't need all the
> > > > bespoke string parsing.
> > >
> > > Versioning aside, although that removes a large part of the motivation,
> > > the interface becomes quite nice:
> > > of_property_present(node, "riscv,isa-extension-zicbom")
> >
> > My current feeling is that, rather than introducing a key-value type of
> > property, adding boolean properties for extensions is the way to go
> > here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
> 
> The only problem with boolean properties is you lose the ability to
> add extra information
> about an ISA extension in case we require it. One of the examples is
> CMO extensions.
> The current riscv,isa string parsing scheme that doesn't have
> infrastructure to do that either.

I think that is a different problem entirely. Every extension has
totally different requirements for what information needs to be passed
via DT/ACPI to the kernel (or onwards to userspace).
I'm not sure whether creating child nodes for these things makes sense,
rather than the current scheme of having "riscv,cbom-block-size" etc.
Both are much of a muchness to me, and we have already set out on the
path of inserting these properties at the cpu node level.
I don't see all that much benefit of deviating from that course ¯\_(ツ)_/¯

However, if you consider it a *presence* test, rather than specifically
a boolean property, the probing strategy remains the same for both
cases, and it is in the enablement stage that that aspect comes into
play.
For the sake of this discussion, the probing/detection strategy is what
I think is important to consider, IOW do we replace "riscv,isa" at all,
and whether it is a child node or boolean property is an implementation
detail.
By removing the value, I meant removing the extension version, since
that will no longer be needed.

> We had some related discussions in the past about how to extend the
> key-value pair to include
> that value.
> 
> https://lore.kernel.org/lkml/CAOnJCUKgt1+SVXTBmGChJf74JrsqeqACXbjQAXnhFALkXhPFew@mail.gmail.com/

Yeah, I had done some looking back at the previous lots of changes for
these things while trying to redo the comments on the existing parser.
I do dislike that scheme, with the

| mmu {
| 	riscv,isa-ext-foo;
| };

way of doing things, as the different node types need to be individually
probed for.
In a scheme where the riscv,isa-ext-foo properties are moved up to the
cpu node, possibly as child nodes containing extension specific
properties, doing presence detection is uniform across extension types:

| for (int k = 0; k < ARRAY_SIZE(riscv_isa_extensions) - 1; k++) {
| 	const char *tmp;
| 
| 	/*
| 	 * I need to double check that of_property_present() works for
| 	 * children and "regular" properties.
| 	 */
| 	ret = of_property_present(node, riscv_isa_extensions[k].prop_name);
| 
| 	if (ret && riscv_isa_extension_check(riscv_isa_extensions[k].key)) {
| 		if (!riscv_isa_extensions[k].multi_letter)
| 			this_hwcap |= isa2hwcap[riscv_isa_extensions[k].key];
| 
| 		set_bit(riscv_isa_extensions[k].key, this_isa);
| 	}
| }

LMK if I missed another proposal in those threads (they mostly seemed
focused on /proc/cpuinfo), but the lack of a unified probe/detection
mechanism in the scheme I did see suggested put me off.

Thanks,
Conor.

> > of the base extensions (and thus the removal of some features...).
> > Starting again with a new property would allow us to define extensions
> > as per their ratified state, rather than the intermediate & incompatible
> > states that we have currently got with "riscv,isa".
> > Such a model does rely on the strengthening of the wording in the
> > specification.
> >
> > This had the advantage of being, as I mention above, even easier to
> > parse in software than the key-value pair business - but also is
> > trivially implemented in a dt-binding. What I have been trying to do
> > with the validation of the key-value stuff does not appear to be readily
> > doable!
> >
> > (Another drawback that has come to mind is that we have no way to
> > validate whether mutually exclusive extensions have been added with
> > "riscv,isa")
> >
> > > That also gives us the ability to define what supported vendor
> > > extensions actually mean in a dt-binding, which to me is a big win in
> > > terms of the aforementioned "wild west".
> >
> > Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
> > and my feeling is that "riscv,isa" is not a mechanism where we can
> > easily handle meanings - especially for vendor stuff where there is
> > otherwise no centralised location for _xfoo -> feature mappings.


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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-12 23:52                   ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-12 23:52 UTC (permalink / raw)
  To: Atish Patra
  Cc: Palmer Dabbelt, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, Krste Asanovic, Andrew Waterman, Greg Favor,
	Mark Himelstein, Philipp Tomsich

[-- Attachment #1: Type: text/plain, Size: 6693 bytes --]

On Fri, May 12, 2023 at 04:20:43PM -0700, Atish Patra wrote:
> On Fri, May 12, 2023 at 3:05 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > +CC Greg, Mark, Krste, Philipp, Andrew,
> >
> > (this is LKML now, no top posting or html replies)
> >
> > On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> > > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > > >
> > > > > > > That's more than last year at this point, and nothing has changed in the
> > > > > > > documentation! Talk's cheap, ehh?
> > > > > > >
> > > > > >
> > > > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > > > >
> > > > > Sounds good, thanks!
> > >
> > > There has been some movement on that front, shall see where it goes
> > > :upsidedown_smile:
> >
> > There's been some off-list discussion prompted by Atish with some of the
> > RVI spec folk, from which the upshot __appears__ to be an understanding
> > that using version numbering to indicate removal of ISA features is a bad
> > idea.
> > I'm hoping that this results in the enshrinement of this in the ISA
> > specs, so that we have something concrete to point to as the basis for
> > not needing to handle version numbering.
> > Certainly that'd be great for ACPI and remove concerns there.
> >
> > > > > > We will likely have a vendor specific string parsing logic.
> > > > >
> > > > > Complicating the parsing logic is the exact sort of crap that I want
> > > > > to avoid.
> > > >
> > > > Ya, I think we're reallly overcomplicating things with the ISA strings.
> > > > Let's just deprecate them and move to something that doesn't need all the
> > > > bespoke string parsing.
> > >
> > > Versioning aside, although that removes a large part of the motivation,
> > > the interface becomes quite nice:
> > > of_property_present(node, "riscv,isa-extension-zicbom")
> >
> > My current feeling is that, rather than introducing a key-value type of
> > property, adding boolean properties for extensions is the way to go
> > here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
> 
> The only problem with boolean properties is you lose the ability to
> add extra information
> about an ISA extension in case we require it. One of the examples is
> CMO extensions.
> The current riscv,isa string parsing scheme that doesn't have
> infrastructure to do that either.

I think that is a different problem entirely. Every extension has
totally different requirements for what information needs to be passed
via DT/ACPI to the kernel (or onwards to userspace).
I'm not sure whether creating child nodes for these things makes sense,
rather than the current scheme of having "riscv,cbom-block-size" etc.
Both are much of a muchness to me, and we have already set out on the
path of inserting these properties at the cpu node level.
I don't see all that much benefit of deviating from that course ¯\_(ツ)_/¯

However, if you consider it a *presence* test, rather than specifically
a boolean property, the probing strategy remains the same for both
cases, and it is in the enablement stage that that aspect comes into
play.
For the sake of this discussion, the probing/detection strategy is what
I think is important to consider, IOW do we replace "riscv,isa" at all,
and whether it is a child node or boolean property is an implementation
detail.
By removing the value, I meant removing the extension version, since
that will no longer be needed.

> We had some related discussions in the past about how to extend the
> key-value pair to include
> that value.
> 
> https://lore.kernel.org/lkml/CAOnJCUKgt1+SVXTBmGChJf74JrsqeqACXbjQAXnhFALkXhPFew@mail.gmail.com/

Yeah, I had done some looking back at the previous lots of changes for
these things while trying to redo the comments on the existing parser.
I do dislike that scheme, with the

| mmu {
| 	riscv,isa-ext-foo;
| };

way of doing things, as the different node types need to be individually
probed for.
In a scheme where the riscv,isa-ext-foo properties are moved up to the
cpu node, possibly as child nodes containing extension specific
properties, doing presence detection is uniform across extension types:

| for (int k = 0; k < ARRAY_SIZE(riscv_isa_extensions) - 1; k++) {
| 	const char *tmp;
| 
| 	/*
| 	 * I need to double check that of_property_present() works for
| 	 * children and "regular" properties.
| 	 */
| 	ret = of_property_present(node, riscv_isa_extensions[k].prop_name);
| 
| 	if (ret && riscv_isa_extension_check(riscv_isa_extensions[k].key)) {
| 		if (!riscv_isa_extensions[k].multi_letter)
| 			this_hwcap |= isa2hwcap[riscv_isa_extensions[k].key];
| 
| 		set_bit(riscv_isa_extensions[k].key, this_isa);
| 	}
| }

LMK if I missed another proposal in those threads (they mostly seemed
focused on /proc/cpuinfo), but the lack of a unified probe/detection
mechanism in the scheme I did see suggested put me off.

Thanks,
Conor.

> > of the base extensions (and thus the removal of some features...).
> > Starting again with a new property would allow us to define extensions
> > as per their ratified state, rather than the intermediate & incompatible
> > states that we have currently got with "riscv,isa".
> > Such a model does rely on the strengthening of the wording in the
> > specification.
> >
> > This had the advantage of being, as I mention above, even easier to
> > parse in software than the key-value pair business - but also is
> > trivially implemented in a dt-binding. What I have been trying to do
> > with the validation of the key-value stuff does not appear to be readily
> > doable!
> >
> > (Another drawback that has come to mind is that we have no way to
> > validate whether mutually exclusive extensions have been added with
> > "riscv,isa")
> >
> > > That also gives us the ability to define what supported vendor
> > > extensions actually mean in a dt-binding, which to me is a big win in
> > > terms of the aforementioned "wild west".
> >
> > Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
> > and my feeling is that "riscv,isa" is not a mechanism where we can
> > easily handle meanings - especially for vendor stuff where there is
> > otherwise no centralised location for _xfoo -> feature mappings.


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^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-12 22:05               ` Conor Dooley
@ 2023-05-12 23:55                 ` Palmer Dabbelt
  -1 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2023-05-12 23:55 UTC (permalink / raw)
  To: Conor Dooley
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, krste, Andrew Waterman, gfavor, markhimelstein,
	philipp.tomsich

On Fri, 12 May 2023 15:05:24 PDT (-0700), Conor Dooley wrote:
> +CC Greg, Mark, Krste, Philipp, Andrew,
>
> (this is LKML now, no top posting or html replies)
>
> On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
>> On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
>> > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
>> > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
>> > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
>> > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
>> > > 
>> > > > > That's more than last year at this point, and nothing has changed in the
>> > > > > documentation! Talk's cheap, ehh?
>> > > > >
>> > > > 
>> > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
>> > > 
>> > > Sounds good, thanks!
>> 
>> There has been some movement on that front, shall see where it goes
>> :upsidedown_smile:
>
> There's been some off-list discussion prompted by Atish with some of the
> RVI spec folk, from which the upshot __appears__ to be an understanding
> that using version numbering to indicate removal of ISA features is a bad
> idea.
> I'm hoping that this results in the enshrinement of this in the ISA
> specs, so that we have something concrete to point to as the basis for
> not needing to handle version numbering. 
> Certainly that'd be great for ACPI and remove concerns there.
>
>> > > > We will likely have a vendor specific string parsing logic.
>> > > 
>> > > Complicating the parsing logic is the exact sort of crap that I want
>> > > to avoid.
>> > 
>> > Ya, I think we're reallly overcomplicating things with the ISA strings.
>> > Let's just deprecate them and move to something that doesn't need all the
>> > bespoke string parsing.
>> 
>> Versioning aside, although that removes a large part of the motivation,
>> the interface becomes quite nice:
>> of_property_present(node, "riscv,isa-extension-zicbom")
>
> My current feeling is that, rather than introducing a key-value type of
> property, adding boolean properties for extensions is the way to go
> here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
> of the base extensions (and thus the removal of some features...).
> Starting again with a new property would allow us to define extensions
> as per their ratified state, rather than the intermediate & incompatible
> states that we have currently got with "riscv,isa".
> Such a model does rely on the strengthening of the wording in the
> specification.

IMO the important part is that we encode an exact version (or commit if 
they're going to stop doing versions) of the spec in the DT.  We've 
gotten burned enough times by just trying to point at the latest spec 
and trusting that compatibility will be handled in the specs, in 
practice that doesn't work.

Given how inconsistent the RISC-V version schemes have been, we really 
can't assign any semantic meaning to version numbers.  So I don't think 
it matters all that much if we encode this as

    riscv,$SPEC = ["v1.0", "v1.1"]

or

    riscv,$SPEC = true // with the binding saying v1.0 or $SHA...
    riscv,$SPEC-1.1 = true // with the binding saying v1.1 or $SHA...

Since we can't ascribe any meaning to those version numbers there's 
nothing to parse in them, so it's just going to plumb into some lookup 
table in the kernel either way.  The important part is just that we 
document exactly what spec version we're encoding, as that way we can 
avoid getting burned by these changes again in the future.

> This had the advantage of being, as I mention above, even easier to
> parse in software than the key-value pair business - but also is
> trivially implemented in a dt-binding. What I have been trying to do
> with the validation of the key-value stuff does not appear to be readily
> doable!

IMO that's the most important deciding factor on how these should be 
encoded.  We're not tracking the ISA string any more, so it doesn't 
matter how closely those line up.  We do have a chance to actually 
validate the interface, though, which was a big problem with the ISA 
strings.

From talking it sounds like the form you're proposing is easier to 
encode in dt-schema than what I'd proposed.  I didn't look at dt-schema 
at all before thinking up the interface, so you're probably right ;).

Assuming that's the case it seems like the way to go as for as I'm 
concerned.

> (Another drawback that has come to mind is that we have no way to
> validate whether mutually exclusive extensions have been added with
> "riscv,isa")
>
>> That also gives us the ability to define what supported vendor
>> extensions actually mean in a dt-binding, which to me is a big win in
>> terms of the aforementioned "wild west".
>
> Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
> and my feeling is that "riscv,isa" is not a mechanism where we can
> easily handle meanings - especially for vendor stuff where there is
> otherwise no centralised location for _xfoo -> feature mappings.

IMO there's not any fundamental difference: it's not like the standard 
extensions have any meaningful naming/versioning scheme, so it's still 
all just lookup tables.

We do get the same benefits from schema validation that we'd get for 
standard extensions, though.  That's probably a way bigger win for 
vendor extensions, as it'll close a big loophole in our DT validation 
right now where users can cram arbitrary stuff into "riscv,isa" and then 
we have to just deal with it.

> Cheers,
> Conor.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-12 23:55                 ` Palmer Dabbelt
  0 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2023-05-12 23:55 UTC (permalink / raw)
  To: Conor Dooley
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, krste, Andrew Waterman, gfavor, markhimelstein,
	philipp.tomsich

On Fri, 12 May 2023 15:05:24 PDT (-0700), Conor Dooley wrote:
> +CC Greg, Mark, Krste, Philipp, Andrew,
>
> (this is LKML now, no top posting or html replies)
>
> On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
>> On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
>> > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
>> > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
>> > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
>> > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
>> > > 
>> > > > > That's more than last year at this point, and nothing has changed in the
>> > > > > documentation! Talk's cheap, ehh?
>> > > > >
>> > > > 
>> > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
>> > > 
>> > > Sounds good, thanks!
>> 
>> There has been some movement on that front, shall see where it goes
>> :upsidedown_smile:
>
> There's been some off-list discussion prompted by Atish with some of the
> RVI spec folk, from which the upshot __appears__ to be an understanding
> that using version numbering to indicate removal of ISA features is a bad
> idea.
> I'm hoping that this results in the enshrinement of this in the ISA
> specs, so that we have something concrete to point to as the basis for
> not needing to handle version numbering. 
> Certainly that'd be great for ACPI and remove concerns there.
>
>> > > > We will likely have a vendor specific string parsing logic.
>> > > 
>> > > Complicating the parsing logic is the exact sort of crap that I want
>> > > to avoid.
>> > 
>> > Ya, I think we're reallly overcomplicating things with the ISA strings.
>> > Let's just deprecate them and move to something that doesn't need all the
>> > bespoke string parsing.
>> 
>> Versioning aside, although that removes a large part of the motivation,
>> the interface becomes quite nice:
>> of_property_present(node, "riscv,isa-extension-zicbom")
>
> My current feeling is that, rather than introducing a key-value type of
> property, adding boolean properties for extensions is the way to go
> here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
> of the base extensions (and thus the removal of some features...).
> Starting again with a new property would allow us to define extensions
> as per their ratified state, rather than the intermediate & incompatible
> states that we have currently got with "riscv,isa".
> Such a model does rely on the strengthening of the wording in the
> specification.

IMO the important part is that we encode an exact version (or commit if 
they're going to stop doing versions) of the spec in the DT.  We've 
gotten burned enough times by just trying to point at the latest spec 
and trusting that compatibility will be handled in the specs, in 
practice that doesn't work.

Given how inconsistent the RISC-V version schemes have been, we really 
can't assign any semantic meaning to version numbers.  So I don't think 
it matters all that much if we encode this as

    riscv,$SPEC = ["v1.0", "v1.1"]

or

    riscv,$SPEC = true // with the binding saying v1.0 or $SHA...
    riscv,$SPEC-1.1 = true // with the binding saying v1.1 or $SHA...

Since we can't ascribe any meaning to those version numbers there's 
nothing to parse in them, so it's just going to plumb into some lookup 
table in the kernel either way.  The important part is just that we 
document exactly what spec version we're encoding, as that way we can 
avoid getting burned by these changes again in the future.

> This had the advantage of being, as I mention above, even easier to
> parse in software than the key-value pair business - but also is
> trivially implemented in a dt-binding. What I have been trying to do
> with the validation of the key-value stuff does not appear to be readily
> doable!

IMO that's the most important deciding factor on how these should be 
encoded.  We're not tracking the ISA string any more, so it doesn't 
matter how closely those line up.  We do have a chance to actually 
validate the interface, though, which was a big problem with the ISA 
strings.

From talking it sounds like the form you're proposing is easier to 
encode in dt-schema than what I'd proposed.  I didn't look at dt-schema 
at all before thinking up the interface, so you're probably right ;).

Assuming that's the case it seems like the way to go as for as I'm 
concerned.

> (Another drawback that has come to mind is that we have no way to
> validate whether mutually exclusive extensions have been added with
> "riscv,isa")
>
>> That also gives us the ability to define what supported vendor
>> extensions actually mean in a dt-binding, which to me is a big win in
>> terms of the aforementioned "wild west".
>
> Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
> and my feeling is that "riscv,isa" is not a mechanism where we can
> easily handle meanings - especially for vendor stuff where there is
> otherwise no centralised location for _xfoo -> feature mappings.

IMO there's not any fundamental difference: it's not like the standard 
extensions have any meaningful naming/versioning scheme, so it's still 
all just lookup tables.

We do get the same benefits from schema validation that we'd get for 
standard extensions, though.  That's probably a way bigger win for 
vendor extensions, as it'll close a big loophole in our DT validation 
right now where users can cram arbitrary stuff into "riscv,isa" and then 
we have to just deal with it.

> Cheers,
> Conor.

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-12 23:55                 ` Palmer Dabbelt
@ 2023-05-13  0:09                   ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-13  0:09 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, krste, Andrew Waterman, gfavor, markhimelstein,
	philipp.tomsich

[-- Attachment #1: Type: text/plain, Size: 7205 bytes --]

On Fri, May 12, 2023 at 04:55:50PM -0700, Palmer Dabbelt wrote:
> On Fri, 12 May 2023 15:05:24 PDT (-0700), Conor Dooley wrote:
> > +CC Greg, Mark, Krste, Philipp, Andrew,
> > 
> > (this is LKML now, no top posting or html replies)
> > 
> > On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> > > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > > > > > > > That's more than last year at this point, and nothing
> > > has changed in the
> > > > > > > documentation! Talk's cheap, ehh?
> > > > > > >
> > > > > > > > > Yup. I will poke RVI folks to check if it still is the
> > > plan or changed !!
> > > > > > > Sounds good, thanks!
> > > 
> > > There has been some movement on that front, shall see where it goes
> > > :upsidedown_smile:
> > 
> > There's been some off-list discussion prompted by Atish with some of the
> > RVI spec folk, from which the upshot __appears__ to be an understanding
> > that using version numbering to indicate removal of ISA features is a bad
> > idea.
> > I'm hoping that this results in the enshrinement of this in the ISA
> > specs, so that we have something concrete to point to as the basis for
> > not needing to handle version numbering. Certainly that'd be great for
> > ACPI and remove concerns there.
> > 
> > > > > > We will likely have a vendor specific string parsing logic.
> > > > > > > Complicating the parsing logic is the exact sort of crap
> > > that I want
> > > > > to avoid.
> > > > > Ya, I think we're reallly overcomplicating things with the ISA
> > > strings.
> > > > Let's just deprecate them and move to something that doesn't need all the
> > > > bespoke string parsing.
> > > 
> > > Versioning aside, although that removes a large part of the motivation,
> > > the interface becomes quite nice:
> > > of_property_present(node, "riscv,isa-extension-zicbom")
> > 
> > My current feeling is that, rather than introducing a key-value type of
> > property, adding boolean properties for extensions is the way to go
> > here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
> > of the base extensions (and thus the removal of some features...).
> > Starting again with a new property would allow us to define extensions
> > as per their ratified state, rather than the intermediate & incompatible
> > states that we have currently got with "riscv,isa".
> > Such a model does rely on the strengthening of the wording in the
> > specification.
> 
> IMO the important part is that we encode an exact version (or commit if
> they're going to stop doing versions) of the spec in the DT.  We've gotten
> burned enough times by just trying to point at the latest spec and trusting
> that compatibility will be handled in the specs, in practice that doesn't
> work.
> 
> Given how inconsistent the RISC-V version schemes have been, we really can't
> assign any semantic meaning to version numbers.  So I don't think it matters
> all that much if we encode this as
> 
>    riscv,$SPEC = ["v1.0", "v1.1"]
> 
> or
> 
>    riscv,$SPEC = true // with the binding saying v1.0 or $SHA...
>    riscv,$SPEC-1.1 = true // with the binding saying v1.1 or $SHA...
> 
> Since we can't ascribe any meaning to those version numbers there's nothing
> to parse in them, so it's just going to plumb into some lookup table in the
> kernel either way.  The important part is just that we document exactly what
> spec version we're encoding, as that way we can avoid getting burned by
> these changes again in the future.

What I was envisioning was something like:

property:
  riscv,isa-extension-i:
    description:
      This hart implements I, as per version 20191213 of the unpriv
      spec.

If you don't implement that, then don't populate it. If you do, and
things break, you keep both pieces.

The current:

  riscv,isa:
    description:
      Identifies the specific RISC-V instruction set architecture
      supported by the hart.  These are documented in the RISC-V
      User-Level ISA document, available from
      https://riscv.org/specifications/

Is, IMO, utterly unhelpful. My recent addition:

      Due to revisions of the ISA specification, some deviations
      have arisen over time.
      Notably, riscv,isa was defined prior to the creation of the
      Zicsr and Zifencei extensions and thus "i" implies
      "zicsr_zifencei".

Is accurate, but is a symptom of the problem rather than a solution.

> > This had the advantage of being, as I mention above, even easier to
> > parse in software than the key-value pair business - but also is
> > trivially implemented in a dt-binding. What I have been trying to do
> > with the validation of the key-value stuff does not appear to be readily
> > doable!
> 
> IMO that's the most important deciding factor on how these should be
> encoded.  We're not tracking the ISA string any more, so it doesn't matter
> how closely those line up.  We do have a chance to actually validate the
> interface, though, which was a big problem with the ISA strings.
> 
> From talking it sounds like the form you're proposing is easier to encode in
> dt-schema than what I'd proposed.  I didn't look at dt-schema at all before
> thinking up the interface, so you're probably right ;).
> 
> Assuming that's the case it seems like the way to go as for as I'm
> concerned.
> 
> > (Another drawback that has come to mind is that we have no way to
> > validate whether mutually exclusive extensions have been added with
> > "riscv,isa")
> > 
> > > That also gives us the ability to define what supported vendor
> > > extensions actually mean in a dt-binding, which to me is a big win in
> > > terms of the aforementioned "wild west".
> > 
> > Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
> > and my feeling is that "riscv,isa" is not a mechanism where we can
> > easily handle meanings - especially for vendor stuff where there is
> > otherwise no centralised location for _xfoo -> feature mappings.
> 
> IMO there's not any fundamental difference: it's not like the standard
> extensions have any meaningful naming/versioning scheme, so it's still all
> just lookup tables.
> 
> We do get the same benefits from schema validation that we'd get for
> standard extensions, though.  That's probably a way bigger win for vendor
> extensions, as it'll close a big loophole in our DT validation right now
> where users can cram arbitrary stuff into "riscv,isa" and then we have to
> just deal with it.

TL;DR appears to be that I should revise this in a way that functions
in a way that is compatible with dt-schema & send a non-RFC version of
this that also CCs the likes of QEMU, U-Boot & the BSD folk.
I'll give it a wee bit for the RVI lads to figure out what they are
doing.

Thanks,
Conor.

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^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-13  0:09                   ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-13  0:09 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, krste, Andrew Waterman, gfavor, markhimelstein,
	philipp.tomsich


[-- Attachment #1.1: Type: text/plain, Size: 7205 bytes --]

On Fri, May 12, 2023 at 04:55:50PM -0700, Palmer Dabbelt wrote:
> On Fri, 12 May 2023 15:05:24 PDT (-0700), Conor Dooley wrote:
> > +CC Greg, Mark, Krste, Philipp, Andrew,
> > 
> > (this is LKML now, no top posting or html replies)
> > 
> > On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> > > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > > > > > > > That's more than last year at this point, and nothing
> > > has changed in the
> > > > > > > documentation! Talk's cheap, ehh?
> > > > > > >
> > > > > > > > > Yup. I will poke RVI folks to check if it still is the
> > > plan or changed !!
> > > > > > > Sounds good, thanks!
> > > 
> > > There has been some movement on that front, shall see where it goes
> > > :upsidedown_smile:
> > 
> > There's been some off-list discussion prompted by Atish with some of the
> > RVI spec folk, from which the upshot __appears__ to be an understanding
> > that using version numbering to indicate removal of ISA features is a bad
> > idea.
> > I'm hoping that this results in the enshrinement of this in the ISA
> > specs, so that we have something concrete to point to as the basis for
> > not needing to handle version numbering. Certainly that'd be great for
> > ACPI and remove concerns there.
> > 
> > > > > > We will likely have a vendor specific string parsing logic.
> > > > > > > Complicating the parsing logic is the exact sort of crap
> > > that I want
> > > > > to avoid.
> > > > > Ya, I think we're reallly overcomplicating things with the ISA
> > > strings.
> > > > Let's just deprecate them and move to something that doesn't need all the
> > > > bespoke string parsing.
> > > 
> > > Versioning aside, although that removes a large part of the motivation,
> > > the interface becomes quite nice:
> > > of_property_present(node, "riscv,isa-extension-zicbom")
> > 
> > My current feeling is that, rather than introducing a key-value type of
> > property, adding boolean properties for extensions is the way to go
> > here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
> > of the base extensions (and thus the removal of some features...).
> > Starting again with a new property would allow us to define extensions
> > as per their ratified state, rather than the intermediate & incompatible
> > states that we have currently got with "riscv,isa".
> > Such a model does rely on the strengthening of the wording in the
> > specification.
> 
> IMO the important part is that we encode an exact version (or commit if
> they're going to stop doing versions) of the spec in the DT.  We've gotten
> burned enough times by just trying to point at the latest spec and trusting
> that compatibility will be handled in the specs, in practice that doesn't
> work.
> 
> Given how inconsistent the RISC-V version schemes have been, we really can't
> assign any semantic meaning to version numbers.  So I don't think it matters
> all that much if we encode this as
> 
>    riscv,$SPEC = ["v1.0", "v1.1"]
> 
> or
> 
>    riscv,$SPEC = true // with the binding saying v1.0 or $SHA...
>    riscv,$SPEC-1.1 = true // with the binding saying v1.1 or $SHA...
> 
> Since we can't ascribe any meaning to those version numbers there's nothing
> to parse in them, so it's just going to plumb into some lookup table in the
> kernel either way.  The important part is just that we document exactly what
> spec version we're encoding, as that way we can avoid getting burned by
> these changes again in the future.

What I was envisioning was something like:

property:
  riscv,isa-extension-i:
    description:
      This hart implements I, as per version 20191213 of the unpriv
      spec.

If you don't implement that, then don't populate it. If you do, and
things break, you keep both pieces.

The current:

  riscv,isa:
    description:
      Identifies the specific RISC-V instruction set architecture
      supported by the hart.  These are documented in the RISC-V
      User-Level ISA document, available from
      https://riscv.org/specifications/

Is, IMO, utterly unhelpful. My recent addition:

      Due to revisions of the ISA specification, some deviations
      have arisen over time.
      Notably, riscv,isa was defined prior to the creation of the
      Zicsr and Zifencei extensions and thus "i" implies
      "zicsr_zifencei".

Is accurate, but is a symptom of the problem rather than a solution.

> > This had the advantage of being, as I mention above, even easier to
> > parse in software than the key-value pair business - but also is
> > trivially implemented in a dt-binding. What I have been trying to do
> > with the validation of the key-value stuff does not appear to be readily
> > doable!
> 
> IMO that's the most important deciding factor on how these should be
> encoded.  We're not tracking the ISA string any more, so it doesn't matter
> how closely those line up.  We do have a chance to actually validate the
> interface, though, which was a big problem with the ISA strings.
> 
> From talking it sounds like the form you're proposing is easier to encode in
> dt-schema than what I'd proposed.  I didn't look at dt-schema at all before
> thinking up the interface, so you're probably right ;).
> 
> Assuming that's the case it seems like the way to go as for as I'm
> concerned.
> 
> > (Another drawback that has come to mind is that we have no way to
> > validate whether mutually exclusive extensions have been added with
> > "riscv,isa")
> > 
> > > That also gives us the ability to define what supported vendor
> > > extensions actually mean in a dt-binding, which to me is a big win in
> > > terms of the aforementioned "wild west".
> > 
> > Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
> > and my feeling is that "riscv,isa" is not a mechanism where we can
> > easily handle meanings - especially for vendor stuff where there is
> > otherwise no centralised location for _xfoo -> feature mappings.
> 
> IMO there's not any fundamental difference: it's not like the standard
> extensions have any meaningful naming/versioning scheme, so it's still all
> just lookup tables.
> 
> We do get the same benefits from schema validation that we'd get for
> standard extensions, though.  That's probably a way bigger win for vendor
> extensions, as it'll close a big loophole in our DT validation right now
> where users can cram arbitrary stuff into "riscv,isa" and then we have to
> just deal with it.

TL;DR appears to be that I should revise this in a way that functions
in a way that is compatible with dt-schema & send a non-RFC version of
this that also CCs the likes of QEMU, U-Boot & the BSD folk.
I'll give it a wee bit for the RVI lads to figure out what they are
doing.

Thanks,
Conor.

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-13  0:09                   ` Conor Dooley
@ 2023-05-13  0:38                     ` Palmer Dabbelt
  -1 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2023-05-13  0:38 UTC (permalink / raw)
  To: Conor Dooley
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, krste, Andrew Waterman, gfavor, markhimelstein,
	philipp.tomsich

On Fri, 12 May 2023 17:09:00 PDT (-0700), Conor Dooley wrote:
> On Fri, May 12, 2023 at 04:55:50PM -0700, Palmer Dabbelt wrote:
>> On Fri, 12 May 2023 15:05:24 PDT (-0700), Conor Dooley wrote:
>> > +CC Greg, Mark, Krste, Philipp, Andrew,
>> > 
>> > (this is LKML now, no top posting or html replies)
>> > 
>> > On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
>> > > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
>> > > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
>> > > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
>> > > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
>> > > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
>> > > > > > > > > That's more than last year at this point, and nothing
>> > > has changed in the
>> > > > > > > documentation! Talk's cheap, ehh?
>> > > > > > >
>> > > > > > > > > Yup. I will poke RVI folks to check if it still is the
>> > > plan or changed !!
>> > > > > > > Sounds good, thanks!
>> > > 
>> > > There has been some movement on that front, shall see where it goes
>> > > :upsidedown_smile:
>> > 
>> > There's been some off-list discussion prompted by Atish with some of the
>> > RVI spec folk, from which the upshot __appears__ to be an understanding
>> > that using version numbering to indicate removal of ISA features is a bad
>> > idea.
>> > I'm hoping that this results in the enshrinement of this in the ISA
>> > specs, so that we have something concrete to point to as the basis for
>> > not needing to handle version numbering. Certainly that'd be great for
>> > ACPI and remove concerns there.
>> > 
>> > > > > > We will likely have a vendor specific string parsing logic.
>> > > > > > > Complicating the parsing logic is the exact sort of crap
>> > > that I want
>> > > > > to avoid.
>> > > > > Ya, I think we're reallly overcomplicating things with the ISA
>> > > strings.
>> > > > Let's just deprecate them and move to something that doesn't need all the
>> > > > bespoke string parsing.
>> > > 
>> > > Versioning aside, although that removes a large part of the motivation,
>> > > the interface becomes quite nice:
>> > > of_property_present(node, "riscv,isa-extension-zicbom")
>> > 
>> > My current feeling is that, rather than introducing a key-value type of
>> > property, adding boolean properties for extensions is the way to go
>> > here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
>> > of the base extensions (and thus the removal of some features...).
>> > Starting again with a new property would allow us to define extensions
>> > as per their ratified state, rather than the intermediate & incompatible
>> > states that we have currently got with "riscv,isa".
>> > Such a model does rely on the strengthening of the wording in the
>> > specification.
>> 
>> IMO the important part is that we encode an exact version (or commit if
>> they're going to stop doing versions) of the spec in the DT.  We've gotten
>> burned enough times by just trying to point at the latest spec and trusting
>> that compatibility will be handled in the specs, in practice that doesn't
>> work.
>> 
>> Given how inconsistent the RISC-V version schemes have been, we really can't
>> assign any semantic meaning to version numbers.  So I don't think it matters
>> all that much if we encode this as
>> 
>>    riscv,$SPEC = ["v1.0", "v1.1"]
>> 
>> or
>> 
>>    riscv,$SPEC = true // with the binding saying v1.0 or $SHA...
>>    riscv,$SPEC-1.1 = true // with the binding saying v1.1 or $SHA...
>> 
>> Since we can't ascribe any meaning to those version numbers there's nothing
>> to parse in them, so it's just going to plumb into some lookup table in the
>> kernel either way.  The important part is just that we document exactly what
>> spec version we're encoding, as that way we can avoid getting burned by
>> these changes again in the future.
>
> What I was envisioning was something like:
>
> property:
>   riscv,isa-extension-i:
>     description:
>       This hart implements I, as per version 20191213 of the unpriv
>       spec.
>
> If you don't implement that, then don't populate it. If you do, and
> things break, you keep both pieces.

That seems reasonable to me, I guess the "true" was entirely redundant 
there.  I don't think that makes much of a difference in the rest of the 
discussion, it's just a bit cleaner in the encoding.

> The current:
>
>   riscv,isa:
>     description:
>       Identifies the specific RISC-V instruction set architecture
>       supported by the hart.  These are documented in the RISC-V
>       User-Level ISA document, available from
>       https://riscv.org/specifications/
>
> Is, IMO, utterly unhelpful. My recent addition:
>
>       Due to revisions of the ISA specification, some deviations
>       have arisen over time.
>       Notably, riscv,isa was defined prior to the creation of the
>       Zicsr and Zifencei extensions and thus "i" implies
>       "zicsr_zifencei".
>
> Is accurate, but is a symptom of the problem rather than a solution.

Ya, it's like the GCC docs that say "this is like an ISA string, but 
different".  Good to note, but not that helpful for users.  Though I 
suppose the fact that we can never seem to document how ISA strings work 
is a pretty good sign they're not a good interface...

>> > This had the advantage of being, as I mention above, even easier to
>> > parse in software than the key-value pair business - but also is
>> > trivially implemented in a dt-binding. What I have been trying to do
>> > with the validation of the key-value stuff does not appear to be readily
>> > doable!
>> 
>> IMO that's the most important deciding factor on how these should be
>> encoded.  We're not tracking the ISA string any more, so it doesn't matter
>> how closely those line up.  We do have a chance to actually validate the
>> interface, though, which was a big problem with the ISA strings.
>> 
>> From talking it sounds like the form you're proposing is easier to encode in
>> dt-schema than what I'd proposed.  I didn't look at dt-schema at all before
>> thinking up the interface, so you're probably right ;).
>> 
>> Assuming that's the case it seems like the way to go as for as I'm
>> concerned.
>> 
>> > (Another drawback that has come to mind is that we have no way to
>> > validate whether mutually exclusive extensions have been added with
>> > "riscv,isa")
>> > 
>> > > That also gives us the ability to define what supported vendor
>> > > extensions actually mean in a dt-binding, which to me is a big win in
>> > > terms of the aforementioned "wild west".
>> > 
>> > Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
>> > and my feeling is that "riscv,isa" is not a mechanism where we can
>> > easily handle meanings - especially for vendor stuff where there is
>> > otherwise no centralised location for _xfoo -> feature mappings.
>> 
>> IMO there's not any fundamental difference: it's not like the standard
>> extensions have any meaningful naming/versioning scheme, so it's still all
>> just lookup tables.
>> 
>> We do get the same benefits from schema validation that we'd get for
>> standard extensions, though.  That's probably a way bigger win for vendor
>> extensions, as it'll close a big loophole in our DT validation right now
>> where users can cram arbitrary stuff into "riscv,isa" and then we have to
>> just deal with it.
>
> TL;DR appears to be that I should revise this in a way that functions
> in a way that is compatible with dt-schema & send a non-RFC version of
> this that also CCs the likes of QEMU, U-Boot & the BSD folk.

Sounds good, thanks for picking this up.

> I'll give it a wee bit for the RVI lads to figure out what they are
> doing.
>
> Thanks,
> Conor.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-13  0:38                     ` Palmer Dabbelt
  0 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2023-05-13  0:38 UTC (permalink / raw)
  To: Conor Dooley
  Cc: atishp, linux-riscv, devicetree, conor+dt, heiko, cyy,
	Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley,
	ajones, krste, Andrew Waterman, gfavor, markhimelstein,
	philipp.tomsich

On Fri, 12 May 2023 17:09:00 PDT (-0700), Conor Dooley wrote:
> On Fri, May 12, 2023 at 04:55:50PM -0700, Palmer Dabbelt wrote:
>> On Fri, 12 May 2023 15:05:24 PDT (-0700), Conor Dooley wrote:
>> > +CC Greg, Mark, Krste, Philipp, Andrew,
>> > 
>> > (this is LKML now, no top posting or html replies)
>> > 
>> > On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
>> > > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
>> > > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
>> > > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
>> > > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
>> > > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
>> > > > > > > > > That's more than last year at this point, and nothing
>> > > has changed in the
>> > > > > > > documentation! Talk's cheap, ehh?
>> > > > > > >
>> > > > > > > > > Yup. I will poke RVI folks to check if it still is the
>> > > plan or changed !!
>> > > > > > > Sounds good, thanks!
>> > > 
>> > > There has been some movement on that front, shall see where it goes
>> > > :upsidedown_smile:
>> > 
>> > There's been some off-list discussion prompted by Atish with some of the
>> > RVI spec folk, from which the upshot __appears__ to be an understanding
>> > that using version numbering to indicate removal of ISA features is a bad
>> > idea.
>> > I'm hoping that this results in the enshrinement of this in the ISA
>> > specs, so that we have something concrete to point to as the basis for
>> > not needing to handle version numbering. Certainly that'd be great for
>> > ACPI and remove concerns there.
>> > 
>> > > > > > We will likely have a vendor specific string parsing logic.
>> > > > > > > Complicating the parsing logic is the exact sort of crap
>> > > that I want
>> > > > > to avoid.
>> > > > > Ya, I think we're reallly overcomplicating things with the ISA
>> > > strings.
>> > > > Let's just deprecate them and move to something that doesn't need all the
>> > > > bespoke string parsing.
>> > > 
>> > > Versioning aside, although that removes a large part of the motivation,
>> > > the interface becomes quite nice:
>> > > of_property_present(node, "riscv,isa-extension-zicbom")
>> > 
>> > My current feeling is that, rather than introducing a key-value type of
>> > property, adding boolean properties for extensions is the way to go
>> > here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
>> > of the base extensions (and thus the removal of some features...).
>> > Starting again with a new property would allow us to define extensions
>> > as per their ratified state, rather than the intermediate & incompatible
>> > states that we have currently got with "riscv,isa".
>> > Such a model does rely on the strengthening of the wording in the
>> > specification.
>> 
>> IMO the important part is that we encode an exact version (or commit if
>> they're going to stop doing versions) of the spec in the DT.  We've gotten
>> burned enough times by just trying to point at the latest spec and trusting
>> that compatibility will be handled in the specs, in practice that doesn't
>> work.
>> 
>> Given how inconsistent the RISC-V version schemes have been, we really can't
>> assign any semantic meaning to version numbers.  So I don't think it matters
>> all that much if we encode this as
>> 
>>    riscv,$SPEC = ["v1.0", "v1.1"]
>> 
>> or
>> 
>>    riscv,$SPEC = true // with the binding saying v1.0 or $SHA...
>>    riscv,$SPEC-1.1 = true // with the binding saying v1.1 or $SHA...
>> 
>> Since we can't ascribe any meaning to those version numbers there's nothing
>> to parse in them, so it's just going to plumb into some lookup table in the
>> kernel either way.  The important part is just that we document exactly what
>> spec version we're encoding, as that way we can avoid getting burned by
>> these changes again in the future.
>
> What I was envisioning was something like:
>
> property:
>   riscv,isa-extension-i:
>     description:
>       This hart implements I, as per version 20191213 of the unpriv
>       spec.
>
> If you don't implement that, then don't populate it. If you do, and
> things break, you keep both pieces.

That seems reasonable to me, I guess the "true" was entirely redundant 
there.  I don't think that makes much of a difference in the rest of the 
discussion, it's just a bit cleaner in the encoding.

> The current:
>
>   riscv,isa:
>     description:
>       Identifies the specific RISC-V instruction set architecture
>       supported by the hart.  These are documented in the RISC-V
>       User-Level ISA document, available from
>       https://riscv.org/specifications/
>
> Is, IMO, utterly unhelpful. My recent addition:
>
>       Due to revisions of the ISA specification, some deviations
>       have arisen over time.
>       Notably, riscv,isa was defined prior to the creation of the
>       Zicsr and Zifencei extensions and thus "i" implies
>       "zicsr_zifencei".
>
> Is accurate, but is a symptom of the problem rather than a solution.

Ya, it's like the GCC docs that say "this is like an ISA string, but 
different".  Good to note, but not that helpful for users.  Though I 
suppose the fact that we can never seem to document how ISA strings work 
is a pretty good sign they're not a good interface...

>> > This had the advantage of being, as I mention above, even easier to
>> > parse in software than the key-value pair business - but also is
>> > trivially implemented in a dt-binding. What I have been trying to do
>> > with the validation of the key-value stuff does not appear to be readily
>> > doable!
>> 
>> IMO that's the most important deciding factor on how these should be
>> encoded.  We're not tracking the ISA string any more, so it doesn't matter
>> how closely those line up.  We do have a chance to actually validate the
>> interface, though, which was a big problem with the ISA strings.
>> 
>> From talking it sounds like the form you're proposing is easier to encode in
>> dt-schema than what I'd proposed.  I didn't look at dt-schema at all before
>> thinking up the interface, so you're probably right ;).
>> 
>> Assuming that's the case it seems like the way to go as for as I'm
>> concerned.
>> 
>> > (Another drawback that has come to mind is that we have no way to
>> > validate whether mutually exclusive extensions have been added with
>> > "riscv,isa")
>> > 
>> > > That also gives us the ability to define what supported vendor
>> > > extensions actually mean in a dt-binding, which to me is a big win in
>> > > terms of the aforementioned "wild west".
>> > 
>> > Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
>> > and my feeling is that "riscv,isa" is not a mechanism where we can
>> > easily handle meanings - especially for vendor stuff where there is
>> > otherwise no centralised location for _xfoo -> feature mappings.
>> 
>> IMO there's not any fundamental difference: it's not like the standard
>> extensions have any meaningful naming/versioning scheme, so it's still all
>> just lookup tables.
>> 
>> We do get the same benefits from schema validation that we'd get for
>> standard extensions, though.  That's probably a way bigger win for vendor
>> extensions, as it'll close a big loophole in our DT validation right now
>> where users can cram arbitrary stuff into "riscv,isa" and then we have to
>> just deal with it.
>
> TL;DR appears to be that I should revise this in a way that functions
> in a way that is compatible with dt-schema & send a non-RFC version of
> this that also CCs the likes of QEMU, U-Boot & the BSD folk.

Sounds good, thanks for picking this up.

> I'll give it a wee bit for the RVI lads to figure out what they are
> doing.
>
> Thanks,
> Conor.

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-12 22:05               ` Conor Dooley
@ 2023-05-13  7:47                 ` Anup Patel
  -1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2023-05-13  7:47 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Palmer Dabbelt, atishp, linux-riscv, devicetree, conor+dt, heiko,
	cyy, Conor Dooley, robh+dt, krzysztof.kozlowski+dt,
	Paul Walmsley, ajones, Krste Asanovic, Andrew Waterman,
	Greg Favor, Mark Himelstein, Philipp Tomsich, Sunil V L

On Sat, May 13, 2023 at 3:35 AM Conor Dooley <conor@kernel.org> wrote:
>
> +CC Greg, Mark, Krste, Philipp, Andrew,
>
> (this is LKML now, no top posting or html replies)
>
> On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > >
> > > > > > That's more than last year at this point, and nothing has changed in the
> > > > > > documentation! Talk's cheap, ehh?
> > > > > >
> > > > >
> > > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > > >
> > > > Sounds good, thanks!
> >
> > There has been some movement on that front, shall see where it goes
> > :upsidedown_smile:
>
> There's been some off-list discussion prompted by Atish with some of the
> RVI spec folk, from which the upshot __appears__ to be an understanding
> that using version numbering to indicate removal of ISA features is a bad
> idea.
> I'm hoping that this results in the enshrinement of this in the ISA
> specs, so that we have something concrete to point to as the basis for
> not needing to handle version numbering.
> Certainly that'd be great for ACPI and remove concerns there.
>
> > > > > We will likely have a vendor specific string parsing logic.
> > > >
> > > > Complicating the parsing logic is the exact sort of crap that I want
> > > > to avoid.
> > >
> > > Ya, I think we're reallly overcomplicating things with the ISA strings.
> > > Let's just deprecate them and move to something that doesn't need all the
> > > bespoke string parsing.
> >
> > Versioning aside, although that removes a large part of the motivation,
> > the interface becomes quite nice:
> > of_property_present(node, "riscv,isa-extension-zicbom")
>
> My current feeling is that, rather than introducing a key-value type of
> property, adding boolean properties for extensions is the way to go
> here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
> of the base extensions (and thus the removal of some features...).
> Starting again with a new property would allow us to define extensions
> as per their ratified state, rather than the intermediate & incompatible
> states that we have currently got with "riscv,isa".
> Such a model does rely on the strengthening of the wording in the
> specification.

ISA string parsed for both DT and ACPI.

For ACPI, moving to a per-extension bit in a bitmap and defining
a new bit with every ISA extension will be very very inconvenient
for updating the ACPI specs. We should continue the ISA string
parsing at least for ACPI.

For DT, users can either use "riscv,isa" DT property or use boolean
DT properties.

>
> This had the advantage of being, as I mention above, even easier to
> parse in software than the key-value pair business - but also is
> trivially implemented in a dt-binding. What I have been trying to do
> with the validation of the key-value stuff does not appear to be readily
> doable!
>
> (Another drawback that has come to mind is that we have no way to
> validate whether mutually exclusive extensions have been added with
> "riscv,isa")
>
> > That also gives us the ability to define what supported vendor
> > extensions actually mean in a dt-binding, which to me is a big win in
> > terms of the aforementioned "wild west".
>
> Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
> and my feeling is that "riscv,isa" is not a mechanism where we can
> easily handle meanings - especially for vendor stuff where there is
> otherwise no centralised location for _xfoo -> feature mappings.
>
> Cheers,
> Conor.

Regards,
Anup

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-13  7:47                 ` Anup Patel
  0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2023-05-13  7:47 UTC (permalink / raw)
  To: Conor Dooley
  Cc: devicetree, conor+dt, heiko, Paul Walmsley, Greg Favor,
	Philipp Tomsich, Andrew Waterman, cyy, Conor Dooley, robh+dt,
	Palmer Dabbelt, krzysztof.kozlowski+dt, atishp, Krste Asanovic,
	linux-riscv, Mark Himelstein, ajones

On Sat, May 13, 2023 at 3:35 AM Conor Dooley <conor@kernel.org> wrote:
>
> +CC Greg, Mark, Krste, Philipp, Andrew,
>
> (this is LKML now, no top posting or html replies)
>
> On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > >
> > > > > > That's more than last year at this point, and nothing has changed in the
> > > > > > documentation! Talk's cheap, ehh?
> > > > > >
> > > > >
> > > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > > >
> > > > Sounds good, thanks!
> >
> > There has been some movement on that front, shall see where it goes
> > :upsidedown_smile:
>
> There's been some off-list discussion prompted by Atish with some of the
> RVI spec folk, from which the upshot __appears__ to be an understanding
> that using version numbering to indicate removal of ISA features is a bad
> idea.
> I'm hoping that this results in the enshrinement of this in the ISA
> specs, so that we have something concrete to point to as the basis for
> not needing to handle version numbering.
> Certainly that'd be great for ACPI and remove concerns there.
>
> > > > > We will likely have a vendor specific string parsing logic.
> > > >
> > > > Complicating the parsing logic is the exact sort of crap that I want
> > > > to avoid.
> > >
> > > Ya, I think we're reallly overcomplicating things with the ISA strings.
> > > Let's just deprecate them and move to something that doesn't need all the
> > > bespoke string parsing.
> >
> > Versioning aside, although that removes a large part of the motivation,
> > the interface becomes quite nice:
> > of_property_present(node, "riscv,isa-extension-zicbom")
>
> My current feeling is that, rather than introducing a key-value type of
> property, adding boolean properties for extensions is the way to go
> here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
> of the base extensions (and thus the removal of some features...).
> Starting again with a new property would allow us to define extensions
> as per their ratified state, rather than the intermediate & incompatible
> states that we have currently got with "riscv,isa".
> Such a model does rely on the strengthening of the wording in the
> specification.

ISA string parsed for both DT and ACPI.

For ACPI, moving to a per-extension bit in a bitmap and defining
a new bit with every ISA extension will be very very inconvenient
for updating the ACPI specs. We should continue the ISA string
parsing at least for ACPI.

For DT, users can either use "riscv,isa" DT property or use boolean
DT properties.

>
> This had the advantage of being, as I mention above, even easier to
> parse in software than the key-value pair business - but also is
> trivially implemented in a dt-binding. What I have been trying to do
> with the validation of the key-value stuff does not appear to be readily
> doable!
>
> (Another drawback that has come to mind is that we have no way to
> validate whether mutually exclusive extensions have been added with
> "riscv,isa")
>
> > That also gives us the ability to define what supported vendor
> > extensions actually mean in a dt-binding, which to me is a big win in
> > terms of the aforementioned "wild west".
>
> Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
> and my feeling is that "riscv,isa" is not a mechanism where we can
> easily handle meanings - especially for vendor stuff where there is
> otherwise no centralised location for _xfoo -> feature mappings.
>
> Cheers,
> Conor.

Regards,
Anup

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 1/6] dt-bindings: riscv: clarify what an unversioned extension means
  2023-05-08 18:16   ` Conor Dooley
@ 2023-05-13 17:46     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 56+ messages in thread
From: Krzysztof Kozlowski @ 2023-05-13 17:46 UTC (permalink / raw)
  To: Conor Dooley, linux-riscv
  Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Palmer Dabbelt, Paul Walmsley, Heiko Stuebner, Andrew Jones,
	Sunil V L, Yangyu Chen, devicetree

On 08/05/2023 20:16, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> C'est la vie, the spec folks reserve the ability to make incompatible
> changes between major versions of an extension. Their idea of backwards
> compatibility appears driven by the hardware perspective - it's
> backwards compatible if a later version is a subset of the existing
> extension. IOW, if you supported `x` in vN, you still support `x` in
> vN+1.
> However in software terms, code that was built for the vN's `x`
> extension may not work with the new definition.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 1/6] dt-bindings: riscv: clarify what an unversioned extension means
@ 2023-05-13 17:46     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 56+ messages in thread
From: Krzysztof Kozlowski @ 2023-05-13 17:46 UTC (permalink / raw)
  To: Conor Dooley, linux-riscv
  Cc: devicetree, Conor Dooley, Heiko Stuebner, Yangyu Chen,
	Conor Dooley, Rob Herring, Palmer Dabbelt, Krzysztof Kozlowski,
	Paul Walmsley, Andrew Jones

On 08/05/2023 20:16, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> C'est la vie, the spec folks reserve the ability to make incompatible
> changes between major versions of an extension. Their idea of backwards
> compatibility appears driven by the hardware perspective - it's
> backwards compatible if a later version is a subset of the existing
> extension. IOW, if you supported `x` in vN, you still support `x` in
> vN+1.
> However in software terms, code that was built for the vN's `x`
> extension may not work with the new definition.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 2/6] dt-bindings: riscv: add riscv,isa-extension-* property and incompatible example
  2023-05-08 18:16   ` Conor Dooley
@ 2023-05-13 17:50     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 56+ messages in thread
From: Krzysztof Kozlowski @ 2023-05-13 17:50 UTC (permalink / raw)
  To: Conor Dooley, linux-riscv
  Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Palmer Dabbelt, Paul Walmsley, Heiko Stuebner, Andrew Jones,
	Sunil V L, Yangyu Chen, devicetree

On 08/05/2023 20:16, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> This dt-binding is illustrative *only*, it doesn't yet do what I want it
> to do in terms of enforcement etc. I am yet to figure out exactly how to
> wrangle the binding such that the individual properties have more
> generous versions than the generic pattern property.
> This binding *will* generate errors, and needs rework before it can
> seriously be considered.
> Nevertheless, it should demonstrate how I intend such a property be
> used.
> 
> Not-signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/riscv/cpus.yaml       | 61 ++++++++++++++++++-
>  1 file changed, 60 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 405915b04d69..cccb3b2ae23d 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -100,6 +100,15 @@ properties:
>        lowercase.
>      $ref: "/schemas/types.yaml#/definitions/string"
>      pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
> +    deprecated: true
> +
> +  riscv,isa-base:
> +    description:
> +      Identifies the base ISA supported by a hart.
> +    $ref: "/schemas/types.yaml#/definitions/string"

Drop quotes.

> +    enum:
> +      - rv32i
> +      - rv64i
>  
>    # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
>    timebase-frequency: false
> @@ -136,8 +145,32 @@ properties:
>        DMIPS/MHz, relative to highest capacity-dmips-mhz
>        in the system.
>  
> +  riscv,isa-extension-v:
> +    description: RISC-V Vector extension
> +    $ref: "/schemas/types.yaml#/definitions/string"

Drop quotes.

> +    oneOf:
> +      - const: v1.0.0
> +        description: the original incarnation
> +      - const: v1.0.1
> +        description: backwards compat was broken here
> +
> +patternProperties:
> +  "^riscv,isa-extension-*":

Are all these -i/-m/-a extensions obvious/known to RISC-V folks? I have
no clue what's this, so the question is: do they need some explanation
in the bindings?

> +    description:
> +      Catch-all property for ISA extensions that do not need any special
> +      handling, and of which all known versions are compatible with their
> +      original revision.
> +    $ref: "/schemas/types.yaml#/definitions/string"

Drop quotes.

> +    enum:
> +      - v1.0.0

Your example should not validate here... you have there v2.0.0 and v1.0.1

> +
> +oneOf:
> +  - required:
> +      - riscv,isa-base
> +  - required:
> +      - riscv,isa
> +
>  required:
> -  - riscv,isa
>    - interrupt-controller
>  
>  additionalProperties: true
> @@ -208,4 +241,30 @@ examples:
>                  };
>          };
>      };
> +
> +  - |
> +    // Example 3: Extension specification
> +    cpus {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        cpu@0 {
> +                device_type = "cpu";
> +                reg = <0>;
> +                compatible = "riscv";
> +                riscv,isa-base = "rv64i";
> +                riscv,isa-extension-i = "v1.0.0";
> +                riscv,isa-extension-m = "v1.0.0";
> +                riscv,isa-extension-a = "v1.0.0";
> +                riscv,isa-extension-f = "v1.0.0";
> +                riscv,isa-extension-d = "v1.0.0";
> +                riscv,isa-extension-c = "v2.0.0";
> +                riscv,isa-extension-v = "v1.0.1";
> +                mmu-type = "riscv,sv48";
> +                interrupt-controller {
> +                        #interrupt-cells = <1>;
> +                        interrupt-controller;
> +                        compatible = "riscv,cpu-intc";
> +                };
> +        };
> +    };
>  ...

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 2/6] dt-bindings: riscv: add riscv,isa-extension-* property and incompatible example
@ 2023-05-13 17:50     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 56+ messages in thread
From: Krzysztof Kozlowski @ 2023-05-13 17:50 UTC (permalink / raw)
  To: Conor Dooley, linux-riscv
  Cc: devicetree, Conor Dooley, Heiko Stuebner, Yangyu Chen,
	Conor Dooley, Rob Herring, Palmer Dabbelt, Krzysztof Kozlowski,
	Paul Walmsley, Andrew Jones

On 08/05/2023 20:16, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> This dt-binding is illustrative *only*, it doesn't yet do what I want it
> to do in terms of enforcement etc. I am yet to figure out exactly how to
> wrangle the binding such that the individual properties have more
> generous versions than the generic pattern property.
> This binding *will* generate errors, and needs rework before it can
> seriously be considered.
> Nevertheless, it should demonstrate how I intend such a property be
> used.
> 
> Not-signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/riscv/cpus.yaml       | 61 ++++++++++++++++++-
>  1 file changed, 60 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 405915b04d69..cccb3b2ae23d 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -100,6 +100,15 @@ properties:
>        lowercase.
>      $ref: "/schemas/types.yaml#/definitions/string"
>      pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
> +    deprecated: true
> +
> +  riscv,isa-base:
> +    description:
> +      Identifies the base ISA supported by a hart.
> +    $ref: "/schemas/types.yaml#/definitions/string"

Drop quotes.

> +    enum:
> +      - rv32i
> +      - rv64i
>  
>    # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
>    timebase-frequency: false
> @@ -136,8 +145,32 @@ properties:
>        DMIPS/MHz, relative to highest capacity-dmips-mhz
>        in the system.
>  
> +  riscv,isa-extension-v:
> +    description: RISC-V Vector extension
> +    $ref: "/schemas/types.yaml#/definitions/string"

Drop quotes.

> +    oneOf:
> +      - const: v1.0.0
> +        description: the original incarnation
> +      - const: v1.0.1
> +        description: backwards compat was broken here
> +
> +patternProperties:
> +  "^riscv,isa-extension-*":

Are all these -i/-m/-a extensions obvious/known to RISC-V folks? I have
no clue what's this, so the question is: do they need some explanation
in the bindings?

> +    description:
> +      Catch-all property for ISA extensions that do not need any special
> +      handling, and of which all known versions are compatible with their
> +      original revision.
> +    $ref: "/schemas/types.yaml#/definitions/string"

Drop quotes.

> +    enum:
> +      - v1.0.0

Your example should not validate here... you have there v2.0.0 and v1.0.1

> +
> +oneOf:
> +  - required:
> +      - riscv,isa-base
> +  - required:
> +      - riscv,isa
> +
>  required:
> -  - riscv,isa
>    - interrupt-controller
>  
>  additionalProperties: true
> @@ -208,4 +241,30 @@ examples:
>                  };
>          };
>      };
> +
> +  - |
> +    // Example 3: Extension specification
> +    cpus {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        cpu@0 {
> +                device_type = "cpu";
> +                reg = <0>;
> +                compatible = "riscv";
> +                riscv,isa-base = "rv64i";
> +                riscv,isa-extension-i = "v1.0.0";
> +                riscv,isa-extension-m = "v1.0.0";
> +                riscv,isa-extension-a = "v1.0.0";
> +                riscv,isa-extension-f = "v1.0.0";
> +                riscv,isa-extension-d = "v1.0.0";
> +                riscv,isa-extension-c = "v2.0.0";
> +                riscv,isa-extension-v = "v1.0.1";
> +                mmu-type = "riscv,sv48";
> +                interrupt-controller {
> +                        #interrupt-cells = <1>;
> +                        interrupt-controller;
> +                        compatible = "riscv,cpu-intc";
> +                };
> +        };
> +    };
>  ...

Best regards,
Krzysztof


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 2/6] dt-bindings: riscv: add riscv,isa-extension-* property and incompatible example
  2023-05-13 17:50     ` Krzysztof Kozlowski
@ 2023-05-13 18:00       ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-13 18:00 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: devicetree, Conor Dooley, Heiko Stuebner, Yangyu Chen,
	Conor Dooley, Rob Herring, Palmer Dabbelt, Krzysztof Kozlowski,
	Paul Walmsley, linux-riscv, Andrew Jones


[-- Attachment #1.1: Type: text/plain, Size: 2308 bytes --]

On Sat, May 13, 2023 at 07:50:22PM +0200, Krzysztof Kozlowski wrote:
> On 08/05/2023 20:16, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> > 
> > This dt-binding is illustrative *only*, it doesn't yet do what I want it
> > to do in terms of enforcement etc. I am yet to figure out exactly how to
> > wrangle the binding such that the individual properties have more
> > generous versions than the generic pattern property.
> > This binding *will* generate errors, and needs rework before it can
> > seriously be considered.
> > Nevertheless, it should demonstrate how I intend such a property be
> > used.

> > +    oneOf:
> > +      - const: v1.0.0
> > +        description: the original incarnation
> > +      - const: v1.0.1
> > +        description: backwards compat was broken here
> > +
> > +patternProperties:
> > +  "^riscv,isa-extension-*":
> 
> Are all these -i/-m/-a extensions obvious/known to RISC-V folks? I have
> no clue what's this, so the question is: do they need some explanation
> in the bindings?

Yes, these should be well known. In the same way that "neon" should mean
something to someone doing arm64. Nevertheless, the plan is to drop the
string side of this entirely & actually document the meaning of -i/-m/-a
etc.

> > +    description:
> > +      Catch-all property for ISA extensions that do not need any special
> > +      handling, and of which all known versions are compatible with their
> > +      original revision.
> > +    $ref: "/schemas/types.yaml#/definitions/string"
> 
> Drop quotes.
> 
> > +    enum:
> > +      - v1.0.0
> 
> Your example should not validate here... you have there v2.0.0 and v1.0.1

As noted in the commit message, this is illustrative only & cannot work.
There doesn't appear to be a way to make the patternProperty fallback
more specific than the explicitly defined properties.
I wanted to get something out for initial thoughts before trying to do
further wrangling, lest it be a complete waste of time.
Consensus seems to be that versions are a thing of the past and that
property-presence based probing is a better idea. See the discussion
on the cover for that.
It does conveniently mean that all this complexity can be thrown in the
bin.

Cheers,
Conor.

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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 2/6] dt-bindings: riscv: add riscv,isa-extension-* property and incompatible example
@ 2023-05-13 18:00       ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-13 18:00 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: linux-riscv, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Palmer Dabbelt, Paul Walmsley, Heiko Stuebner,
	Andrew Jones, Sunil V L, Yangyu Chen, devicetree

[-- Attachment #1: Type: text/plain, Size: 2308 bytes --]

On Sat, May 13, 2023 at 07:50:22PM +0200, Krzysztof Kozlowski wrote:
> On 08/05/2023 20:16, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> > 
> > This dt-binding is illustrative *only*, it doesn't yet do what I want it
> > to do in terms of enforcement etc. I am yet to figure out exactly how to
> > wrangle the binding such that the individual properties have more
> > generous versions than the generic pattern property.
> > This binding *will* generate errors, and needs rework before it can
> > seriously be considered.
> > Nevertheless, it should demonstrate how I intend such a property be
> > used.

> > +    oneOf:
> > +      - const: v1.0.0
> > +        description: the original incarnation
> > +      - const: v1.0.1
> > +        description: backwards compat was broken here
> > +
> > +patternProperties:
> > +  "^riscv,isa-extension-*":
> 
> Are all these -i/-m/-a extensions obvious/known to RISC-V folks? I have
> no clue what's this, so the question is: do they need some explanation
> in the bindings?

Yes, these should be well known. In the same way that "neon" should mean
something to someone doing arm64. Nevertheless, the plan is to drop the
string side of this entirely & actually document the meaning of -i/-m/-a
etc.

> > +    description:
> > +      Catch-all property for ISA extensions that do not need any special
> > +      handling, and of which all known versions are compatible with their
> > +      original revision.
> > +    $ref: "/schemas/types.yaml#/definitions/string"
> 
> Drop quotes.
> 
> > +    enum:
> > +      - v1.0.0
> 
> Your example should not validate here... you have there v2.0.0 and v1.0.1

As noted in the commit message, this is illustrative only & cannot work.
There doesn't appear to be a way to make the patternProperty fallback
more specific than the explicitly defined properties.
I wanted to get something out for initial thoughts before trying to do
further wrangling, lest it be a complete waste of time.
Consensus seems to be that versions are a thing of the past and that
property-presence based probing is a better idea. See the discussion
on the cover for that.
It does conveniently mean that all this complexity can be thrown in the
bin.

Cheers,
Conor.

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-13  7:47                 ` Anup Patel
@ 2023-05-13 21:34                   ` Jessica Clarke
  -1 siblings, 0 replies; 56+ messages in thread
From: Jessica Clarke @ 2023-05-13 21:34 UTC (permalink / raw)
  To: Anup Patel
  Cc: Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	conor+dt, Heiko Stübner, Paul Walmsley, Greg Favor,
	Philipp Tomsich, Andrew Waterman, cyy, Conor Dooley, Rob Herring,
	Palmer Dabbelt, Krzysztof Kozlowski, Atish Patra, Krste Asanovic,
	linux-riscv, Mark Himelstein, Andrew Jones

On 13 May 2023, at 08:47, Anup Patel <apatel@ventanamicro.com> wrote:
> 
> On Sat, May 13, 2023 at 3:35 AM Conor Dooley <conor@kernel.org> wrote:
>> 
>> +CC Greg, Mark, Krste, Philipp, Andrew,
>> 
>> (this is LKML now, no top posting or html replies)
>> 
>> On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
>>> On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
>>>> On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
>>>>> On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
>>>>>> On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
>>>>>>> On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
>>>>> 
>>>>>>> That's more than last year at this point, and nothing has changed in the
>>>>>>> documentation! Talk's cheap, ehh?
>>>>>>> 
>>>>>> 
>>>>>> Yup. I will poke RVI folks to check if it still is the plan or changed !!
>>>>> 
>>>>> Sounds good, thanks!
>>> 
>>> There has been some movement on that front, shall see where it goes
>>> :upsidedown_smile:
>> 
>> There's been some off-list discussion prompted by Atish with some of the
>> RVI spec folk, from which the upshot __appears__ to be an understanding
>> that using version numbering to indicate removal of ISA features is a bad
>> idea.
>> I'm hoping that this results in the enshrinement of this in the ISA
>> specs, so that we have something concrete to point to as the basis for
>> not needing to handle version numbering.
>> Certainly that'd be great for ACPI and remove concerns there.
>> 
>>>>>> We will likely have a vendor specific string parsing logic.
>>>>> 
>>>>> Complicating the parsing logic is the exact sort of crap that I want
>>>>> to avoid.
>>>> 
>>>> Ya, I think we're reallly overcomplicating things with the ISA strings.
>>>> Let's just deprecate them and move to something that doesn't need all the
>>>> bespoke string parsing.
>>> 
>>> Versioning aside, although that removes a large part of the motivation,
>>> the interface becomes quite nice:
>>> of_property_present(node, "riscv,isa-extension-zicbom")
>> 
>> My current feeling is that, rather than introducing a key-value type of
>> property, adding boolean properties for extensions is the way to go
>> here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
>> of the base extensions (and thus the removal of some features...).
>> Starting again with a new property would allow us to define extensions
>> as per their ratified state, rather than the intermediate & incompatible
>> states that we have currently got with "riscv,isa".
>> Such a model does rely on the strengthening of the wording in the
>> specification.
> 
> ISA string parsed for both DT and ACPI.
> 
> For ACPI, moving to a per-extension bit in a bitmap and defining
> a new bit with every ISA extension will be very very inconvenient
> for updating the ACPI specs. We should continue the ISA string
> parsing at least for ACPI.
> 
> For DT, users can either use "riscv,isa" DT property or use boolean
> DT properties.

Can we please not gratuitously have two ways of doing the same thing.

I say this as a non-Linux OS that has to deal with whatever Linux
decides to do with device trees. It is a total nuisance when you flip
flop on things and we have to follow suit. Please consider the breakage
very carefully.

Jess

>> This had the advantage of being, as I mention above, even easier to
>> parse in software than the key-value pair business - but also is
>> trivially implemented in a dt-binding. What I have been trying to do
>> with the validation of the key-value stuff does not appear to be readily
>> doable!
>> 
>> (Another drawback that has come to mind is that we have no way to
>> validate whether mutually exclusive extensions have been added with
>> "riscv,isa")
>> 
>>> That also gives us the ability to define what supported vendor
>>> extensions actually mean in a dt-binding, which to me is a big win in
>>> terms of the aforementioned "wild west".
>> 
>> Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
>> and my feeling is that "riscv,isa" is not a mechanism where we can
>> easily handle meanings - especially for vendor stuff where there is
>> otherwise no centralised location for _xfoo -> feature mappings.
>> 
>> Cheers,
>> Conor.
> 
> Regards,
> Anup
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv



^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-13 21:34                   ` Jessica Clarke
  0 siblings, 0 replies; 56+ messages in thread
From: Jessica Clarke @ 2023-05-13 21:34 UTC (permalink / raw)
  To: Anup Patel
  Cc: Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	conor+dt, Heiko Stübner, Paul Walmsley, Greg Favor,
	Philipp Tomsich, Andrew Waterman, cyy, Conor Dooley, Rob Herring,
	Palmer Dabbelt, Krzysztof Kozlowski, Atish Patra, Krste Asanovic,
	linux-riscv, Mark Himelstein, Andrew Jones

On 13 May 2023, at 08:47, Anup Patel <apatel@ventanamicro.com> wrote:
> 
> On Sat, May 13, 2023 at 3:35 AM Conor Dooley <conor@kernel.org> wrote:
>> 
>> +CC Greg, Mark, Krste, Philipp, Andrew,
>> 
>> (this is LKML now, no top posting or html replies)
>> 
>> On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
>>> On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
>>>> On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
>>>>> On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
>>>>>> On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
>>>>>>> On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
>>>>> 
>>>>>>> That's more than last year at this point, and nothing has changed in the
>>>>>>> documentation! Talk's cheap, ehh?
>>>>>>> 
>>>>>> 
>>>>>> Yup. I will poke RVI folks to check if it still is the plan or changed !!
>>>>> 
>>>>> Sounds good, thanks!
>>> 
>>> There has been some movement on that front, shall see where it goes
>>> :upsidedown_smile:
>> 
>> There's been some off-list discussion prompted by Atish with some of the
>> RVI spec folk, from which the upshot __appears__ to be an understanding
>> that using version numbering to indicate removal of ISA features is a bad
>> idea.
>> I'm hoping that this results in the enshrinement of this in the ISA
>> specs, so that we have something concrete to point to as the basis for
>> not needing to handle version numbering.
>> Certainly that'd be great for ACPI and remove concerns there.
>> 
>>>>>> We will likely have a vendor specific string parsing logic.
>>>>> 
>>>>> Complicating the parsing logic is the exact sort of crap that I want
>>>>> to avoid.
>>>> 
>>>> Ya, I think we're reallly overcomplicating things with the ISA strings.
>>>> Let's just deprecate them and move to something that doesn't need all the
>>>> bespoke string parsing.
>>> 
>>> Versioning aside, although that removes a large part of the motivation,
>>> the interface becomes quite nice:
>>> of_property_present(node, "riscv,isa-extension-zicbom")
>> 
>> My current feeling is that, rather than introducing a key-value type of
>> property, adding boolean properties for extensions is the way to go
>> here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
>> of the base extensions (and thus the removal of some features...).
>> Starting again with a new property would allow us to define extensions
>> as per their ratified state, rather than the intermediate & incompatible
>> states that we have currently got with "riscv,isa".
>> Such a model does rely on the strengthening of the wording in the
>> specification.
> 
> ISA string parsed for both DT and ACPI.
> 
> For ACPI, moving to a per-extension bit in a bitmap and defining
> a new bit with every ISA extension will be very very inconvenient
> for updating the ACPI specs. We should continue the ISA string
> parsing at least for ACPI.
> 
> For DT, users can either use "riscv,isa" DT property or use boolean
> DT properties.

Can we please not gratuitously have two ways of doing the same thing.

I say this as a non-Linux OS that has to deal with whatever Linux
decides to do with device trees. It is a total nuisance when you flip
flop on things and we have to follow suit. Please consider the breakage
very carefully.

Jess

>> This had the advantage of being, as I mention above, even easier to
>> parse in software than the key-value pair business - but also is
>> trivially implemented in a dt-binding. What I have been trying to do
>> with the validation of the key-value stuff does not appear to be readily
>> doable!
>> 
>> (Another drawback that has come to mind is that we have no way to
>> validate whether mutually exclusive extensions have been added with
>> "riscv,isa")
>> 
>>> That also gives us the ability to define what supported vendor
>>> extensions actually mean in a dt-binding, which to me is a big win in
>>> terms of the aforementioned "wild west".
>> 
>> Vendor extensions etc are oft quoted as one of the strengths of RISC-V,
>> and my feeling is that "riscv,isa" is not a mechanism where we can
>> easily handle meanings - especially for vendor stuff where there is
>> otherwise no centralised location for _xfoo -> feature mappings.
>> 
>> Cheers,
>> Conor.
> 
> Regards,
> Anup
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv



_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-13 21:34                   ` Jessica Clarke
@ 2023-05-13 21:54                     ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-13 21:54 UTC (permalink / raw)
  To: Jessica Clarke
  Cc: Anup Patel,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	conor+dt, Heiko Stübner, Paul Walmsley, Greg Favor,
	Philipp Tomsich, Andrew Waterman, cyy, Conor Dooley, Rob Herring,
	Palmer Dabbelt, Krzysztof Kozlowski, Atish Patra, Krste Asanovic,
	linux-riscv, Mark Himelstein, Andrew Jones

[-- Attachment #1: Type: text/plain, Size: 1231 bytes --]

On Sat, May 13, 2023 at 10:34:15PM +0100, Jessica Clarke wrote:
> On 13 May 2023, at 08:47, Anup Patel <apatel@ventanamicro.com> wrote:

> > For DT, users can either use "riscv,isa" DT property or use boolean
> > DT properties.
> 
> Can we please not gratuitously have two ways of doing the same thing.

My intention, iff this goes ahead, is to deprecate that property, not
have some 'you can use "riscv,isa" or boolean, whichever you choose'
situation.
Obviously for backwards compatibility reasons parsing it as a fallback
would have be kept in Linux, so in theory a DT based Linux system "can
use either". It would be up to other platforms to decide whether they
would also like to do such a thing.

> I say this as a non-Linux OS that has to deal with whatever Linux
> decides to do with device trees. It is a total nuisance when you flip
> flop on things and we have to follow suit. Please consider the breakage
> very carefully.

I think I said it in my cover & in a later message, that I sent it here
only for first thoughts and my intention is to "send a non-RFC version
of this that also CCs the likes of QEMU, U-Boot & the BSD folk".
It's clearly not something that could be done unilaterally.


[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-13 21:54                     ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-13 21:54 UTC (permalink / raw)
  To: Jessica Clarke
  Cc: Anup Patel,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	conor+dt, Heiko Stübner, Paul Walmsley, Greg Favor,
	Philipp Tomsich, Andrew Waterman, cyy, Conor Dooley, Rob Herring,
	Palmer Dabbelt, Krzysztof Kozlowski, Atish Patra, Krste Asanovic,
	linux-riscv, Mark Himelstein, Andrew Jones


[-- Attachment #1.1: Type: text/plain, Size: 1231 bytes --]

On Sat, May 13, 2023 at 10:34:15PM +0100, Jessica Clarke wrote:
> On 13 May 2023, at 08:47, Anup Patel <apatel@ventanamicro.com> wrote:

> > For DT, users can either use "riscv,isa" DT property or use boolean
> > DT properties.
> 
> Can we please not gratuitously have two ways of doing the same thing.

My intention, iff this goes ahead, is to deprecate that property, not
have some 'you can use "riscv,isa" or boolean, whichever you choose'
situation.
Obviously for backwards compatibility reasons parsing it as a fallback
would have be kept in Linux, so in theory a DT based Linux system "can
use either". It would be up to other platforms to decide whether they
would also like to do such a thing.

> I say this as a non-Linux OS that has to deal with whatever Linux
> decides to do with device trees. It is a total nuisance when you flip
> flop on things and we have to follow suit. Please consider the breakage
> very carefully.

I think I said it in my cover & in a later message, that I sent it here
only for first thoughts and my intention is to "send a non-RFC version
of this that also CCs the likes of QEMU, U-Boot & the BSD folk".
It's clearly not something that could be done unilaterally.


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^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-13  7:47                 ` Anup Patel
@ 2023-05-15  4:38                   ` Sunil V L
  -1 siblings, 0 replies; 56+ messages in thread
From: Sunil V L @ 2023-05-15  4:38 UTC (permalink / raw)
  To: Anup Patel
  Cc: Conor Dooley, Palmer Dabbelt, atishp, linux-riscv, devicetree,
	conor+dt, heiko, cyy, Conor Dooley, robh+dt,
	krzysztof.kozlowski+dt, Paul Walmsley, ajones, Krste Asanovic,
	Andrew Waterman, Greg Favor, Mark Himelstein, Philipp Tomsich

On Sat, May 13, 2023 at 01:17:03PM +0530, Anup Patel wrote:
> On Sat, May 13, 2023 at 3:35 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > +CC Greg, Mark, Krste, Philipp, Andrew,
> >
> > (this is LKML now, no top posting or html replies)
> >
> > On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> > > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > > >
> > > > > > > That's more than last year at this point, and nothing has changed in the
> > > > > > > documentation! Talk's cheap, ehh?
> > > > > > >
> > > > > >
> > > > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > > > >
> > > > > Sounds good, thanks!
> > >
> > > There has been some movement on that front, shall see where it goes
> > > :upsidedown_smile:
> >
> > There's been some off-list discussion prompted by Atish with some of the
> > RVI spec folk, from which the upshot __appears__ to be an understanding
> > that using version numbering to indicate removal of ISA features is a bad
> > idea.
> > I'm hoping that this results in the enshrinement of this in the ISA
> > specs, so that we have something concrete to point to as the basis for
> > not needing to handle version numbering.
> > Certainly that'd be great for ACPI and remove concerns there.
> >
> > > > > > We will likely have a vendor specific string parsing logic.
> > > > >
> > > > > Complicating the parsing logic is the exact sort of crap that I want
> > > > > to avoid.
> > > >
> > > > Ya, I think we're reallly overcomplicating things with the ISA strings.
> > > > Let's just deprecate them and move to something that doesn't need all the
> > > > bespoke string parsing.
> > >
> > > Versioning aside, although that removes a large part of the motivation,
> > > the interface becomes quite nice:
> > > of_property_present(node, "riscv,isa-extension-zicbom")
> >
> > My current feeling is that, rather than introducing a key-value type of
> > property, adding boolean properties for extensions is the way to go
> > here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
> > of the base extensions (and thus the removal of some features...).
> > Starting again with a new property would allow us to define extensions
> > as per their ratified state, rather than the intermediate & incompatible
> > states that we have currently got with "riscv,isa".
> > Such a model does rely on the strengthening of the wording in the
> > specification.
> 
> ISA string parsed for both DT and ACPI.
> 
> For ACPI, moving to a per-extension bit in a bitmap and defining
> a new bit with every ISA extension will be very very inconvenient
> for updating the ACPI specs. We should continue the ISA string
> parsing at least for ACPI.
> 
> For DT, users can either use "riscv,isa" DT property or use boolean
> DT properties.
> 
From ACPI perspective, the format better be backed by unpriv (or any
other) spec from RVI considering it is a standard across OSs and to
avoid any maintenance issues.

Thanks,
Sunil

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-15  4:38                   ` Sunil V L
  0 siblings, 0 replies; 56+ messages in thread
From: Sunil V L @ 2023-05-15  4:38 UTC (permalink / raw)
  To: Anup Patel
  Cc: Conor Dooley, Palmer Dabbelt, atishp, linux-riscv, devicetree,
	conor+dt, heiko, cyy, Conor Dooley, robh+dt,
	krzysztof.kozlowski+dt, Paul Walmsley, ajones, Krste Asanovic,
	Andrew Waterman, Greg Favor, Mark Himelstein, Philipp Tomsich

On Sat, May 13, 2023 at 01:17:03PM +0530, Anup Patel wrote:
> On Sat, May 13, 2023 at 3:35 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > +CC Greg, Mark, Krste, Philipp, Andrew,
> >
> > (this is LKML now, no top posting or html replies)
> >
> > On Fri, May 12, 2023 at 08:40:10PM +0100, Conor Dooley wrote:
> > > On Fri, May 12, 2023 at 11:01:09AM -0700, Palmer Dabbelt wrote:
> > > > On Thu, 11 May 2023 15:38:10 PDT (-0700), Conor Dooley wrote:
> > > > > On Thu, May 11, 2023 at 03:34:24PM -0700, Atish Patra wrote:
> > > > > > On Thu, May 11, 2023 at 2:47 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > > On Thu, May 11, 2023 at 02:27:44PM -0700, Atish Patra wrote:
> > > > >
> > > > > > > That's more than last year at this point, and nothing has changed in the
> > > > > > > documentation! Talk's cheap, ehh?
> > > > > > >
> > > > > >
> > > > > > Yup. I will poke RVI folks to check if it still is the plan or changed !!
> > > > >
> > > > > Sounds good, thanks!
> > >
> > > There has been some movement on that front, shall see where it goes
> > > :upsidedown_smile:
> >
> > There's been some off-list discussion prompted by Atish with some of the
> > RVI spec folk, from which the upshot __appears__ to be an understanding
> > that using version numbering to indicate removal of ISA features is a bad
> > idea.
> > I'm hoping that this results in the enshrinement of this in the ISA
> > specs, so that we have something concrete to point to as the basis for
> > not needing to handle version numbering.
> > Certainly that'd be great for ACPI and remove concerns there.
> >
> > > > > > We will likely have a vendor specific string parsing logic.
> > > > >
> > > > > Complicating the parsing logic is the exact sort of crap that I want
> > > > > to avoid.
> > > >
> > > > Ya, I think we're reallly overcomplicating things with the ISA strings.
> > > > Let's just deprecate them and move to something that doesn't need all the
> > > > bespoke string parsing.
> > >
> > > Versioning aside, although that removes a large part of the motivation,
> > > the interface becomes quite nice:
> > > of_property_present(node, "riscv,isa-extension-zicbom")
> >
> > My current feeling is that, rather than introducing a key-value type of
> > property, adding boolean properties for extensions is the way to go
> > here. The "riscv,isa" part of the DT ABI pre-dates even the ratification
> > of the base extensions (and thus the removal of some features...).
> > Starting again with a new property would allow us to define extensions
> > as per their ratified state, rather than the intermediate & incompatible
> > states that we have currently got with "riscv,isa".
> > Such a model does rely on the strengthening of the wording in the
> > specification.
> 
> ISA string parsed for both DT and ACPI.
> 
> For ACPI, moving to a per-extension bit in a bitmap and defining
> a new bit with every ISA extension will be very very inconvenient
> for updating the ACPI specs. We should continue the ISA string
> parsing at least for ACPI.
> 
> For DT, users can either use "riscv,isa" DT property or use boolean
> DT properties.
> 
From ACPI perspective, the format better be backed by unpriv (or any
other) spec from RVI considering it is a standard across OSs and to
avoid any maintenance issues.

Thanks,
Sunil

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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
  2023-05-15  4:38                   ` Sunil V L
@ 2023-05-15  7:52                     ` Conor Dooley
  -1 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-15  7:52 UTC (permalink / raw)
  To: Sunil V L
  Cc: Anup Patel, Conor Dooley, Palmer Dabbelt, atishp, linux-riscv,
	devicetree, conor+dt, heiko, cyy, robh+dt,
	krzysztof.kozlowski+dt, Paul Walmsley, ajones, Krste Asanovic,
	Andrew Waterman, Greg Favor, Mark Himelstein, Philipp Tomsich

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On Mon, May 15, 2023 at 10:08:35AM +0530, Sunil V L wrote:
> On Sat, May 13, 2023 at 01:17:03PM +0530, Anup Patel wrote:

> > ISA string parsed for both DT and ACPI.
> > 
> > For ACPI, moving to a per-extension bit in a bitmap and defining
> > a new bit with every ISA extension will be very very inconvenient
> > for updating the ACPI specs. We should continue the ISA string
> > parsing at least for ACPI.
> > 
> > For DT, users can either use "riscv,isa" DT property or use boolean
> > DT properties.
> > 
> From ACPI perspective, the format better be backed by unpriv (or any
> other) spec from RVI considering it is a standard across OSs and to
> avoid any maintenance issues.

DT is also used across multiple OSes, I am not sure what your point is
here.
The problem, for DT in particular, is defining __which__ version of the
unpriv spec meaning is derived from, not whether to use definitions from
the specifications.

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^ permalink raw reply	[flat|nested] 56+ messages in thread

* Re: [RFC 0/6] Deprecate riscv,isa DT property?
@ 2023-05-15  7:52                     ` Conor Dooley
  0 siblings, 0 replies; 56+ messages in thread
From: Conor Dooley @ 2023-05-15  7:52 UTC (permalink / raw)
  To: Sunil V L
  Cc: Anup Patel, Conor Dooley, Palmer Dabbelt, atishp, linux-riscv,
	devicetree, conor+dt, heiko, cyy, robh+dt,
	krzysztof.kozlowski+dt, Paul Walmsley, ajones, Krste Asanovic,
	Andrew Waterman, Greg Favor, Mark Himelstein, Philipp Tomsich


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On Mon, May 15, 2023 at 10:08:35AM +0530, Sunil V L wrote:
> On Sat, May 13, 2023 at 01:17:03PM +0530, Anup Patel wrote:

> > ISA string parsed for both DT and ACPI.
> > 
> > For ACPI, moving to a per-extension bit in a bitmap and defining
> > a new bit with every ISA extension will be very very inconvenient
> > for updating the ACPI specs. We should continue the ISA string
> > parsing at least for ACPI.
> > 
> > For DT, users can either use "riscv,isa" DT property or use boolean
> > DT properties.
> > 
> From ACPI perspective, the format better be backed by unpriv (or any
> other) spec from RVI considering it is a standard across OSs and to
> avoid any maintenance issues.

DT is also used across multiple OSes, I am not sure what your point is
here.
The problem, for DT in particular, is defining __which__ version of the
unpriv spec meaning is derived from, not whether to use definitions from
the specifications.

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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 56+ messages in thread

end of thread, other threads:[~2023-05-15  7:53 UTC | newest]

Thread overview: 56+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-08 18:16 [RFC 0/6] Deprecate riscv,isa DT property? Conor Dooley
2023-05-08 18:16 ` Conor Dooley
2023-05-08 18:16 ` [RFC 1/6] dt-bindings: riscv: clarify what an unversioned extension means Conor Dooley
2023-05-08 18:16   ` Conor Dooley
2023-05-13 17:46   ` Krzysztof Kozlowski
2023-05-13 17:46     ` Krzysztof Kozlowski
2023-05-08 18:16 ` [RFC 2/6] dt-bindings: riscv: add riscv,isa-extension-* property and incompatible example Conor Dooley
2023-05-08 18:16   ` Conor Dooley
2023-05-13 17:50   ` Krzysztof Kozlowski
2023-05-13 17:50     ` Krzysztof Kozlowski
2023-05-13 18:00     ` Conor Dooley
2023-05-13 18:00       ` Conor Dooley
2023-05-08 18:16 ` [RFC 3/6] RISC-V: deprecate riscv,isa & replace it with per-extension properties Conor Dooley
2023-05-08 18:16   ` Conor Dooley
2023-05-08 18:16 ` [RFC 4/6] RISC-V: add support for riscv,isa-base property Conor Dooley
2023-05-08 18:16   ` Conor Dooley
2023-05-08 18:16 ` [RFC 5/6] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-05-08 18:16   ` Conor Dooley
2023-05-08 18:16 ` [RFC 6/6] riscv: dts: microchip: use new riscv,isa-extension-* properties for mpfs Conor Dooley
2023-05-08 18:16   ` Conor Dooley
2023-05-11 21:27 ` [RFC 0/6] Deprecate riscv,isa DT property? Atish Patra
2023-05-11 21:27   ` Atish Patra
2023-05-11 21:47   ` Conor Dooley
2023-05-11 21:47     ` Conor Dooley
2023-05-11 22:34     ` Atish Patra
2023-05-11 22:34       ` Atish Patra
2023-05-11 22:38       ` Conor Dooley
2023-05-11 22:38         ` Conor Dooley
2023-05-12 18:01         ` Palmer Dabbelt
2023-05-12 18:01           ` Palmer Dabbelt
2023-05-12 19:40           ` Conor Dooley
2023-05-12 19:40             ` Conor Dooley
2023-05-12 22:05             ` Conor Dooley
2023-05-12 22:05               ` Conor Dooley
2023-05-12 23:20               ` Atish Patra
2023-05-12 23:20                 ` Atish Patra
2023-05-12 23:52                 ` Conor Dooley
2023-05-12 23:52                   ` Conor Dooley
2023-05-12 23:55               ` Palmer Dabbelt
2023-05-12 23:55                 ` Palmer Dabbelt
2023-05-13  0:09                 ` Conor Dooley
2023-05-13  0:09                   ` Conor Dooley
2023-05-13  0:38                   ` Palmer Dabbelt
2023-05-13  0:38                     ` Palmer Dabbelt
2023-05-13  7:47               ` Anup Patel
2023-05-13  7:47                 ` Anup Patel
2023-05-13 21:34                 ` Jessica Clarke
2023-05-13 21:34                   ` Jessica Clarke
2023-05-13 21:54                   ` Conor Dooley
2023-05-13 21:54                     ` Conor Dooley
2023-05-15  4:38                 ` Sunil V L
2023-05-15  4:38                   ` Sunil V L
2023-05-15  7:52                   ` Conor Dooley
2023-05-15  7:52                     ` Conor Dooley
2023-05-12 18:08   ` Palmer Dabbelt
2023-05-12 18:08     ` Palmer Dabbelt

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