[djiang:cxl-qtg 23/30] drivers/cxl/core/port.c:1980: warning: expecting prototype for cxl_port_get_perf_coordinates(). Prototype was for cxl_endpoint_get_perf_coordinates() instead

[djiang:cxl-qtg 23/30] drivers/cxl/core/port.c:1980: warning: expecting prototype for cxl_port_get_perf_coordinates(). Prototype was for cxl_endpoint_get_perf_coordinates() instead

[kernel test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git cxl-qtg
head:   fd35584ec7147f575dcdc65239bc8ac7fe340ab4
commit: 996858467895f703eccabdc4f84188fe2344e230 [23/30] cxl: Add helper function that calculate performance data for downstream ports
config: arc-randconfig-r014-20230511 (https://download.01.org/0day-ci/archive/20230512/202305120930.6k11Br3C-lkp@intel.com/config)
compiler: arc-elf-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git/commit/?id=996858467895f703eccabdc4f84188fe2344e230
        git remote add djiang https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git
        git fetch --no-tags djiang cxl-qtg
        git checkout 996858467895f703eccabdc4f84188fe2344e230
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arc olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arc SHELL=/bin/bash drivers/cxl/core/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305120930.6k11Br3C-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/cxl/core/port.c:1980: warning: expecting prototype for cxl_port_get_perf_coordinates(). Prototype was for cxl_endpoint_get_perf_coordinates() instead


vim +1980 drivers/cxl/core/port.c

  1969	
  1970	/**
  1971	 * cxl_port_get_perf_coordinates - Retrieve performance numbers stored in dports
  1972	 *				   of CXL path
  1973	 * @port: endpoint cxl_port
  1974	 * @coord: output performance data
  1975	 *
  1976	 * Return: errno on failure, 0 on success.
  1977	 */
  1978	int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
  1979					      struct access_coordinate *coord)
> 1980	{
  1981		struct access_coordinate c = {
  1982			.read_bandwidth = UINT_MAX,
  1983			.write_bandwidth = UINT_MAX,
  1984		};
  1985		struct cxl_port *iter = port;
  1986		struct cxl_dport *dport;
  1987		struct pci_dev *pdev;
  1988		unsigned int bw;
  1989	
  1990		if (!is_cxl_endpoint(port))
  1991			return -EINVAL;
  1992	
  1993		dport = iter->parent_dport;
  1994		while (iter && !is_cxl_root(iter)) {
  1995			combine_coordinates(&c, &dport->coord);
  1996			c.write_latency += dport->link_latency;
  1997			c.read_latency += dport->link_latency;
  1998	
  1999			if (dport->genport_coord)
  2000				combine_coordinates(&c, dport->genport_coord);
  2001	
  2002			iter = to_cxl_port(iter->dev.parent);
  2003			dport = iter->parent_dport;
  2004		}
  2005	
  2006		/* Get the calculated PCI paths bandwidth */
  2007		pdev = to_pci_dev(port->uport->parent);
  2008		bw = pcie_bandwidth_available(pdev, NULL, NULL, NULL);
  2009		if (bw == 0)
  2010			return -ENXIO;
  2011		bw /= BITS_PER_BYTE;
  2012	
  2013		c.write_bandwidth = min_t(unsigned int, c.write_bandwidth, bw);
  2014		c.read_bandwidth = min_t(unsigned int, c.read_bandwidth, bw);
  2015	
  2016		*coord = c;
  2017	
  2018		return 0;
  2019	}
  2020	EXPORT_SYMBOL_NS_GPL(cxl_endpoint_get_perf_coordinates, CXL);
  2021	

-- 
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https://github.com/intel/lkp-tests