* [PATCH 01/10] drm/amdgpu: add GFX RAS common function
@ 2023-05-12 21:43 Alex Deucher
2023-05-12 21:43 ` [PATCH 02/10] drm/amdgpu: add RAS status query for gfx_v9_4_3 Alex Deucher
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Alex Deucher @ 2023-05-12 21:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tao Zhou, Hawking Zhang
From: Tao Zhou <tao.zhou1@amd.com>
The common function can help reduce redundant code.
v2: remove xcp operation, only need to do RAS operations for all
instances.
v3: remove check for GFX RAS support, will be checked in higher level.
add amdgpu prefix for the function name.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 19 +++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 ++++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 2ebf5c6f4ff7..7b072413e576 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -878,6 +878,25 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
return 0;
}
+void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
+ void *ras_error_status,
+ void (*func)(struct amdgpu_device *adev, void *ras_error_status,
+ int xcc_id))
+{
+ int i;
+ int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
+ uint32_t xcc_mask = GENMASK(num_xcc - 1, 0);
+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+
+ if (err_data) {
+ err_data->ue_count = 0;
+ err_data->ce_count = 0;
+ }
+
+ for_each_inst(i, xcc_mask)
+ func(adev, ras_error_status, i);
+}
+
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
{
signed long r, cnt = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index ba5f417146d3..f07117d8959b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -496,6 +496,10 @@ int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);
int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev);
void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev);
+void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
+ void *ras_error_status,
+ void (*func)(struct amdgpu_device *adev, void *ras_error_status,
+ int xcc_id));
static inline const char *amdgpu_gfx_compute_mode_desc(int mode)
{
--
2.40.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 02/10] drm/amdgpu: add RAS status query for gfx_v9_4_3
2023-05-12 21:43 [PATCH 01/10] drm/amdgpu: add GFX RAS common function Alex Deucher
@ 2023-05-12 21:43 ` Alex Deucher
2023-05-12 21:43 ` [PATCH 03/10] drm/amdgpu: add RAS status reset " Alex Deucher
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Alex Deucher @ 2023-05-12 21:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tao Zhou, Hawking Zhang
From: Tao Zhou <tao.zhou1@amd.com>
Query GFX RAS status.
v2: remove xcp operation.
v3: change instance from 0 to xcc_id for register access.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 75 +++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 6cde05421a10..f178e3f565e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2980,6 +2980,81 @@ static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
}
}
+static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = {
+ SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16
+};
+
+static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev,
+ int xcc_id)
+{
+ uint32_t i, j;
+ uint32_t reg_value;
+
+ mutex_lock(&adev->grbm_idx_mutex);
+
+ for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) {
+ for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) {
+ gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id);
+ reg_value = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
+ regGCEA_ERR_STATUS);
+ if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
+ REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
+ REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
+ dev_warn(adev->dev,
+ "GCEA err detected at instance: %d, status: 0x%x!\n",
+ j, reg_value);
+ }
+ /* clear after read */
+ reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,
+ CLEAR_ERROR_STATUS, 0x1);
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS,
+ reg_value);
+ }
+ }
+
+ gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
+ xcc_id);
+ mutex_unlock(&adev->grbm_idx_mutex);
+}
+
+static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev,
+ int xcc_id)
+{
+ uint32_t data;
+
+ data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS);
+ if (data) {
+ dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data);
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3);
+ }
+
+ data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS);
+ if (data) {
+ dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data);
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3);
+ }
+
+ data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
+ regVML2_WALKER_MEM_ECC_STATUS);
+ if (data) {
+ dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data);
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS,
+ 0x3);
+ }
+}
+
+static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev,
+ void *ras_error_status, int xcc_id)
+{
+ gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id);
+ gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id);
+}
+
+static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev)
+{
+ amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status);
+}
+
static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
.name = "gfx_v9_4_3",
.early_init = gfx_v9_4_3_early_init,
--
2.40.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 03/10] drm/amdgpu: add RAS status reset for gfx_v9_4_3
2023-05-12 21:43 [PATCH 01/10] drm/amdgpu: add GFX RAS common function Alex Deucher
2023-05-12 21:43 ` [PATCH 02/10] drm/amdgpu: add RAS status query for gfx_v9_4_3 Alex Deucher
@ 2023-05-12 21:43 ` Alex Deucher
2023-05-12 21:43 ` [PATCH 04/10] drm/amdgpu: Add gc v9_4_3 ras error status registers Alex Deucher
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Alex Deucher @ 2023-05-12 21:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tao Zhou, Hawking Zhang
From: Tao Zhou <tao.zhou1@amd.com>
Reset GFX RAS status registers.
v2: fix typo in title.
remove xcp operation.
v3: change instance from 0 to xcc_id for register access.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 41 +++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index f178e3f565e9..e6069d081f71 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -3050,11 +3050,52 @@ static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev,
gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id);
}
+static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev,
+ int xcc_id)
+{
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3);
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3);
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3);
+}
+
+static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev,
+ int xcc_id)
+{
+ uint32_t i, j;
+ uint32_t value;
+
+ mutex_lock(&adev->grbm_idx_mutex);
+ for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) {
+ for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) {
+ gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id);
+ value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS);
+ value = REG_SET_FIELD(value, GCEA_ERR_STATUS,
+ CLEAR_ERROR_STATUS, 0x1);
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, value);
+ }
+ }
+ gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
+ xcc_id);
+ mutex_unlock(&adev->grbm_idx_mutex);
+}
+
+static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev,
+ void *ras_error_status, int xcc_id)
+{
+ gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id);
+ gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id);
+}
+
static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev)
{
amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status);
}
+static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev)
+{
+ amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status);
+}
+
static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
.name = "gfx_v9_4_3",
.early_init = gfx_v9_4_3_early_init,
--
2.40.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 04/10] drm/amdgpu: Add gc v9_4_3 ras error status registers
2023-05-12 21:43 [PATCH 01/10] drm/amdgpu: add GFX RAS common function Alex Deucher
2023-05-12 21:43 ` [PATCH 02/10] drm/amdgpu: add RAS status query for gfx_v9_4_3 Alex Deucher
2023-05-12 21:43 ` [PATCH 03/10] drm/amdgpu: add RAS status reset " Alex Deucher
@ 2023-05-12 21:43 ` Alex Deucher
2023-05-12 21:43 ` [PATCH 05/10] drm/amdgpu: add RAS definitions for GFX Alex Deucher
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Alex Deucher @ 2023-05-12 21:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tao Zhou, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
GC v9_4_3 introduces UE|CE_ERR_STATUS_LO|HI to log
hardware errors
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../amd/include/asic_reg/gc/gc_9_4_3_offset.h | 192 +++
.../include/asic_reg/gc/gc_9_4_3_sh_mask.h | 1112 +++++++++++++++++
2 files changed, 1304 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
index 3100de8b3881..393963502b7a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
@@ -705,6 +705,46 @@
#define regSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0
#define regSQC_DCACHE_UTCL1_STATUS 0x03d8
#define regSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0
+#define regSQC_UE_EDC_LO 0x03d9
+#define regSQC_UE_EDC_LO_BASE_IDX 0
+#define regSQC_UE_EDC_HI 0x03da
+#define regSQC_UE_EDC_HI_BASE_IDX 0
+#define regSQC_CE_EDC_LO 0x03db
+#define regSQC_CE_EDC_LO_BASE_IDX 0
+#define regSQC_CE_EDC_HI 0x03dc
+#define regSQC_CE_EDC_HI_BASE_IDX 0
+#define regSQ_UE_ERR_STATUS_LO 0x03dd
+#define regSQ_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regSQ_UE_ERR_STATUS_HI 0x03de
+#define regSQ_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regSQ_CE_ERR_STATUS_LO 0x03df
+#define regSQ_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regSQ_CE_ERR_STATUS_HI 0x03e0
+#define regSQ_CE_ERR_STATUS_HI_BASE_IDX 0
+#define regLDS_UE_ERR_STATUS_LO 0x03e1
+#define regLDS_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regLDS_UE_ERR_STATUS_HI 0x03e2
+#define regLDS_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regLDS_CE_ERR_STATUS_LO 0x03e3
+#define regLDS_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regLDS_CE_ERR_STATUS_HI 0x03e4
+#define regLDS_CE_ERR_STATUS_HI_BASE_IDX 0
+#define regSP0_UE_ERR_STATUS_LO 0x03e5
+#define regSP0_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regSP0_UE_ERR_STATUS_HI 0x03e6
+#define regSP0_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regSP0_CE_ERR_STATUS_LO 0x03e7
+#define regSP0_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regSP0_CE_ERR_STATUS_HI 0x03e8
+#define regSP0_CE_ERR_STATUS_HI_BASE_IDX 0
+#define regSP1_UE_ERR_STATUS_LO 0x03e9
+#define regSP1_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regSP1_UE_ERR_STATUS_HI 0x03ea
+#define regSP1_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regSP1_CE_ERR_STATUS_LO 0x03eb
+#define regSP1_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regSP1_CE_ERR_STATUS_HI 0x03ec
+#define regSP1_CE_ERR_STATUS_HI_BASE_IDX 0
// addressBlock: xcd0_gc_shsdec
@@ -727,6 +767,14 @@
#define regSPI_DSM_CNTL2_BASE_IDX 0
#define regSPI_EDC_CNT 0x0445
#define regSPI_EDC_CNT_BASE_IDX 0
+#define regSPI_UE_ERR_STATUS_LO 0x0446
+#define regSPI_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regSPI_UE_ERR_STATUS_HI 0x0447
+#define regSPI_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regSPI_CE_ERR_STATUS_LO 0x0448
+#define regSPI_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regSPI_CE_ERR_STATUS_HI 0x0449
+#define regSPI_CE_ERR_STATUS_HI_BASE_IDX 0
#define regSPI_DEBUG_BUSY 0x0450
#define regSPI_DEBUG_BUSY_BASE_IDX 0
#define regSPI_CONFIG_PS_CU_EN 0x0452
@@ -871,6 +919,14 @@
#define regTD_STATUS_BASE_IDX 0
#define regTD_POWER_CNTL 0x052a
#define regTD_POWER_CNTL_BASE_IDX 0
+#define regTD_UE_EDC_LO 0x052b
+#define regTD_UE_EDC_LO_BASE_IDX 0
+#define regTD_UE_EDC_HI 0x052c
+#define regTD_UE_EDC_HI_BASE_IDX 0
+#define regTD_CE_EDC_LO 0x052d
+#define regTD_CE_EDC_LO_BASE_IDX 0
+#define regTD_CE_EDC_HI 0x052e
+#define regTD_CE_EDC_HI_BASE_IDX 0
#define regTD_DSM_CNTL 0x052f
#define regTD_DSM_CNTL_BASE_IDX 0
#define regTD_DSM_CNTL2 0x0530
@@ -893,6 +949,14 @@
#define regTA_DSM_CNTL_BASE_IDX 0
#define regTA_DSM_CNTL2 0x0585
#define regTA_DSM_CNTL2_BASE_IDX 0
+#define regTA_UE_EDC_LO 0x0587
+#define regTA_UE_EDC_LO_BASE_IDX 0
+#define regTA_UE_EDC_HI 0x0588
+#define regTA_UE_EDC_HI_BASE_IDX 0
+#define regTA_CE_EDC_LO 0x0589
+#define regTA_CE_EDC_LO_BASE_IDX 0
+#define regTA_CE_EDC_HI 0x058a
+#define regTA_CE_EDC_HI_BASE_IDX 0
// addressBlock: xcd0_gc_gdsdec
@@ -923,6 +987,14 @@
#define regGDS_DSM_CNTL2_BASE_IDX 0
#define regGDS_WD_GDS_CSB 0x05ce
#define regGDS_WD_GDS_CSB_BASE_IDX 0
+#define regGDS_UE_ERR_STATUS_LO 0x05cf
+#define regGDS_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regGDS_UE_ERR_STATUS_HI 0x05d0
+#define regGDS_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regGDS_CE_ERR_STATUS_LO 0x05d1
+#define regGDS_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regGDS_CE_ERR_STATUS_HI 0x05d2
+#define regGDS_CE_ERR_STATUS_HI_BASE_IDX 0
// addressBlock: xcd0_gc_rbdec
@@ -1243,6 +1315,10 @@
#define regGCEA_MAM_CTRL_BASE_IDX 0
#define regGCEA_MAM_CTRL2 0x0702
#define regGCEA_MAM_CTRL2_BASE_IDX 0
+#define regGCEA_UE_ERR_STATUS_LO 0x0706
+#define regGCEA_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regGCEA_UE_ERR_STATUS_HI 0x0707
+#define regGCEA_UE_ERR_STATUS_HI_BASE_IDX 0
#define regGCEA_DSM_CNTL 0x0708
#define regGCEA_DSM_CNTL_BASE_IDX 0
#define regGCEA_DSM_CNTLA 0x0709
@@ -1277,6 +1353,10 @@
#define regGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0
#define regGCEA_SDP_BACKDOOR_MISCCREDITS 0x0719
#define regGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0
+#define regGCEA_CE_ERR_STATUS_LO 0x071b
+#define regGCEA_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regGCEA_CE_ERR_STATUS_HI 0x071d
+#define regGCEA_CE_ERR_STATUS_HI_BASE_IDX 0
#define regGCEA_SDP_ENABLE 0x071f
#define regGCEA_SDP_ENABLE_BASE_IDX 0
@@ -1389,6 +1469,14 @@
#define regATC_L2_CNTL4_BASE_IDX 0
#define regATC_L2_MM_GROUP_RT_CLASSES 0x0816
#define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
+#define regATC_L2_UE_ERR_STATUS_LO 0x081a
+#define regATC_L2_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regATC_L2_UE_ERR_STATUS_HI 0x081b
+#define regATC_L2_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regATC_L2_CE_ERR_STATUS_LO 0x081c
+#define regATC_L2_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regATC_L2_CE_ERR_STATUS_HI 0x081d
+#define regATC_L2_CE_ERR_STATUS_HI_BASE_IDX 0
// addressBlock: xcd0_gc_utcl2_vml2pfdec
@@ -1475,6 +1563,30 @@
#define regUTCL2_EDC_MODE_BASE_IDX 0
#define regUTCL2_EDC_CONFIG 0x084c
#define regUTCL2_EDC_CONFIG_BASE_IDX 0
+#define regVML2_UE_ERR_STATUS_LO 0x084d
+#define regVML2_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regVML2_WALKER_UE_ERR_STATUS_LO 0x084e
+#define regVML2_WALKER_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regUTCL2_UE_ERR_STATUS_LO 0x084f
+#define regUTCL2_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regVML2_UE_ERR_STATUS_HI 0x0850
+#define regVML2_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regVML2_WALKER_UE_ERR_STATUS_HI 0x0851
+#define regVML2_WALKER_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regUTCL2_UE_ERR_STATUS_HI 0x0852
+#define regUTCL2_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regVML2_CE_ERR_STATUS_LO 0x0853
+#define regVML2_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regVML2_WALKER_CE_ERR_STATUS_LO 0x0854
+#define regVML2_WALKER_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regUTCL2_CE_ERR_STATUS_LO 0x0855
+#define regUTCL2_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regVML2_CE_ERR_STATUS_HI 0x0856
+#define regVML2_CE_ERR_STATUS_HI_BASE_IDX 0
+#define regVML2_WALKER_CE_ERR_STATUS_HI 0x0857
+#define regVML2_WALKER_CE_ERR_STATUS_HI_BASE_IDX 0
+#define regUTCL2_CE_ERR_STATUS_HI 0x0858
+#define regUTCL2_CE_ERR_STATUS_HI_BASE_IDX 0
// addressBlock: xcd0_gc_utcl2_vml2vcdec
@@ -2011,6 +2123,22 @@
#define regTC_CFG_L1_VOLATILE_BASE_IDX 0
#define regTC_CFG_L2_VOLATILE 0x0b23
#define regTC_CFG_L2_VOLATILE_BASE_IDX 0
+#define regTCP_UE_EDC_HI_REG 0x0b54
+#define regTCP_UE_EDC_HI_REG_BASE_IDX 0
+#define regTCP_UE_EDC_LO_REG 0x0b55
+#define regTCP_UE_EDC_LO_REG_BASE_IDX 0
+#define regTCP_CE_EDC_HI_REG 0x0b56
+#define regTCP_CE_EDC_HI_REG_BASE_IDX 0
+#define regTCP_CE_EDC_LO_REG 0x0b57
+#define regTCP_CE_EDC_LO_REG_BASE_IDX 0
+#define regTCI_UE_EDC_HI_REG 0x0b58
+#define regTCI_UE_EDC_HI_REG_BASE_IDX 0
+#define regTCI_UE_EDC_LO_REG 0x0b59
+#define regTCI_UE_EDC_LO_REG_BASE_IDX 0
+#define regTCI_CE_EDC_HI_REG 0x0b5a
+#define regTCI_CE_EDC_HI_REG_BASE_IDX 0
+#define regTCI_CE_EDC_LO_REG 0x0b5b
+#define regTCI_CE_EDC_LO_REG_BASE_IDX 0
#define regTCI_MISC 0x0b5c
#define regTCI_MISC_BASE_IDX 0
#define regTCI_CNTL_3 0x0b5d
@@ -2061,6 +2189,26 @@
#define regTCX_DSM_CNTL_BASE_IDX 0
#define regTCX_DSM_CNTL2 0x0bc8
#define regTCX_DSM_CNTL2_BASE_IDX 0
+#define regTCA_UE_ERR_STATUS_LO 0x0bc9
+#define regTCA_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regTCA_UE_ERR_STATUS_HI 0x0bca
+#define regTCA_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regTCX_UE_ERR_STATUS_LO 0x0bcb
+#define regTCX_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regTCX_UE_ERR_STATUS_HI 0x0bcc
+#define regTCX_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regTCX_CE_ERR_STATUS_LO 0x0bcd
+#define regTCX_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regTCX_CE_ERR_STATUS_HI 0x0bce
+#define regTCX_CE_ERR_STATUS_HI_BASE_IDX 0
+#define regTCC_UE_ERR_STATUS_LO 0x0bcf
+#define regTCC_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regTCC_UE_ERR_STATUS_HI 0x0bd0
+#define regTCC_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regTCC_CE_ERR_STATUS_LO 0x0bd1
+#define regTCC_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regTCC_CE_ERR_STATUS_HI 0x0bd2
+#define regTCC_CE_ERR_STATUS_HI_BASE_IDX 0
// addressBlock: xcd0_gc_shdec
@@ -2905,6 +3053,30 @@
#define regCP_MEC2_F32_INT_DIS_BASE_IDX 0
#define regCP_VMID_STATUS 0x10bf
#define regCP_VMID_STATUS_BASE_IDX 0
+#define regCPC_UE_ERR_STATUS_LO 0x10e0
+#define regCPC_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regCPC_UE_ERR_STATUS_HI 0x10e1
+#define regCPC_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regCPC_CE_ERR_STATUS_LO 0x10e2
+#define regCPC_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regCPC_CE_ERR_STATUS_HI 0x10e3
+#define regCPC_CE_ERR_STATUS_HI_BASE_IDX 0
+#define regCPF_UE_ERR_STATUS_LO 0x10e4
+#define regCPF_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regCPF_UE_ERR_STATUS_HI 0x10e5
+#define regCPF_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regCPF_CE_ERR_STATUS_LO 0x10e6
+#define regCPF_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regCPF_CE_ERR_STATUS_HI 0x10e7
+#define regCPF_CE_ERR_STATUS_HI_BASE_IDX 0
+#define regCPG_UE_ERR_STATUS_LO 0x10e8
+#define regCPG_UE_ERR_STATUS_LO_BASE_IDX 0
+#define regCPG_UE_ERR_STATUS_HI 0x10e9
+#define regCPG_UE_ERR_STATUS_HI_BASE_IDX 0
+#define regCPG_CE_ERR_STATUS_LO 0x10ea
+#define regCPG_CE_ERR_STATUS_LO_BASE_IDX 0
+#define regCPG_CE_ERR_STATUS_HI 0x10eb
+#define regCPG_CE_ERR_STATUS_HI_BASE_IDX 0
// addressBlock: xcd0_gc_cppdec2
@@ -5364,6 +5536,18 @@
#define regSPI_WAVE_LIMIT_CNTL 0x2443
#define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1
+// addressBlock: xcd0_gc_gccanedec
+// base address: 0x33d00
+#define regGC_CANE_ERR_STATUS 0x2f4d
+#define regGC_CANE_ERR_STATUS_BASE_IDX 1
+#define regGC_CANE_UE_ERR_STATUS_LO 0x2f4e
+#define regGC_CANE_UE_ERR_STATUS_LO_BASE_IDX 1
+#define regGC_CANE_UE_ERR_STATUS_HI 0x2f4f
+#define regGC_CANE_UE_ERR_STATUS_HI_BASE_IDX 1
+#define regGC_CANE_CE_ERR_STATUS_LO 0x2f50
+#define regGC_CANE_CE_ERR_STATUS_LO_BASE_IDX 1
+#define regGC_CANE_CE_ERR_STATUS_HI 0x2f51
+#define regGC_CANE_CE_ERR_STATUS_HI_BASE_IDX 1
// addressBlock: xcd0_gc_perfddec
// base address: 0x34000
@@ -6583,6 +6767,10 @@
#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1
#define regRLC_CPG_STAT_INVAL 0x4d09
#define regRLC_CPG_STAT_INVAL_BASE_IDX 1
+#define regRLC_UE_ERR_STATUS_LOW 0x4d40
+#define regRLC_UE_ERR_STATUS_LOW_BASE_IDX 1
+#define regRLC_UE_ERR_STATUS_HIGH 0x4d41
+#define regRLC_UE_ERR_STATUS_HIGH_BASE_IDX 1
#define regRLC_DSM_CNTL 0x4d42
#define regRLC_DSM_CNTL_BASE_IDX 1
#define regRLC_DSM_CNTLA 0x4d43
@@ -6591,6 +6779,10 @@
#define regRLC_DSM_CNTL2_BASE_IDX 1
#define regRLC_DSM_CNTL2A 0x4d45
#define regRLC_DSM_CNTL2A_BASE_IDX 1
+#define regRLC_CE_ERR_STATUS_LOW 0x4d49
+#define regRLC_CE_ERR_STATUS_LOW_BASE_IDX 1
+#define regRLC_CE_ERR_STATUS_HIGH 0x4d4a
+#define regRLC_CE_ERR_STATUS_HIGH_BASE_IDX 1
#define regRLC_RLCV_SPARE_INT 0x4f30
#define regRLC_RLCV_SPARE_INT_BASE_IDX 1
#define regRLC_SMU_CLK_REQ 0x4f97
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h
index 84a75b58347f..2bd9f3f1026f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h
@@ -4129,6 +4129,240 @@
#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+//SQC_UE_EDC_LO
+#define SQC_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0
+#define SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1
+#define SQC_UE_EDC_LO__ADDRESS__SHIFT 0x2
+#define SQC_UE_EDC_LO__MEM_ID__SHIFT 0x18
+#define SQC_UE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L
+#define SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L
+#define SQC_UE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL
+#define SQC_UE_EDC_LO__MEM_ID_MASK 0xFF000000L
+//SQC_UE_EDC_HI
+#define SQC_UE_EDC_HI__ECC__SHIFT 0x0
+#define SQC_UE_EDC_HI__PARITY__SHIFT 0x1
+#define SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define SQC_UE_EDC_HI__ERR_INFO__SHIFT 0x3
+#define SQC_UE_EDC_HI__UE_CNT__SHIFT 0x17
+#define SQC_UE_EDC_HI__FED_CNT__SHIFT 0x1a
+#define SQC_UE_EDC_HI__ECC_MASK 0x00000001L
+#define SQC_UE_EDC_HI__PARITY_MASK 0x00000002L
+#define SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define SQC_UE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L
+#define SQC_UE_EDC_HI__UE_CNT_MASK 0x03800000L
+#define SQC_UE_EDC_HI__FED_CNT_MASK 0x1C000000L
+//SQC_CE_EDC_LO
+#define SQC_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0
+#define SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1
+#define SQC_CE_EDC_LO__ADDRESS__SHIFT 0x2
+#define SQC_CE_EDC_LO__MEM_ID__SHIFT 0x18
+#define SQC_CE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L
+#define SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L
+#define SQC_CE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL
+#define SQC_CE_EDC_LO__MEM_ID_MASK 0xFF000000L
+//SQC_CE_EDC_HI
+#define SQC_CE_EDC_HI__ECC__SHIFT 0x0
+#define SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define SQC_CE_EDC_HI__ERR_INFO__SHIFT 0x3
+#define SQC_CE_EDC_HI__CE_CNT__SHIFT 0x17
+#define SQC_CE_EDC_HI__POSION__SHIFT 0x1a
+#define SQC_CE_EDC_HI__ECC_MASK 0x00000001L
+#define SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define SQC_CE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L
+#define SQC_CE_EDC_HI__CE_CNT_MASK 0x03800000L
+#define SQC_CE_EDC_HI__POSION_MASK 0x04000000L
+//SQ_UE_ERR_STATUS_LO
+#define SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define SQ_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define SQ_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define SQ_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define SQ_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//SQ_UE_ERR_STATUS_HI
+#define SQ_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define SQ_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define SQ_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define SQ_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define SQ_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define SQ_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define SQ_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define SQ_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define SQ_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define SQ_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define SQ_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define SQ_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//SQ_CE_ERR_STATUS_LO
+#define SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define SQ_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define SQ_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define SQ_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define SQ_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//SQ_CE_ERR_STATUS_HI
+#define SQ_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define SQ_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define SQ_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define SQ_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define SQ_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define SQ_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define SQ_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define SQ_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define SQ_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define SQ_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define SQ_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define SQ_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
+//LDS_UE_ERR_STATUS_LO
+#define LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define LDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define LDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define LDS_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define LDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//LDS_UE_ERR_STATUS_HI
+#define LDS_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define LDS_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define LDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define LDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define LDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define LDS_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define LDS_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define LDS_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define LDS_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define LDS_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define LDS_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define LDS_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//LDS_CE_ERR_STATUS_LO
+#define LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define LDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define LDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define LDS_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define LDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//LDS_CE_ERR_STATUS_HI
+#define LDS_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define LDS_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define LDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define LDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define LDS_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define LDS_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define LDS_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define LDS_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define LDS_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define LDS_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define LDS_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define LDS_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
+//SP0_UE_ERR_STATUS_LO
+#define SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define SP0_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define SP0_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define SP0_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define SP0_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//SP0_UE_ERR_STATUS_HI
+#define SP0_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define SP0_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define SP0_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define SP0_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define SP0_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define SP0_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define SP0_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define SP0_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define SP0_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define SP0_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define SP0_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define SP0_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//SP0_CE_ERR_STATUS_LO
+#define SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define SP0_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define SP0_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define SP0_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define SP0_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//SP0_CE_ERR_STATUS_HI
+#define SP0_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define SP0_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define SP0_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define SP0_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define SP0_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define SP0_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define SP0_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define SP0_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define SP0_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define SP0_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define SP0_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define SP0_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
+//SP1_UE_ERR_STATUS_LO
+#define SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define SP1_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define SP1_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define SP1_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define SP1_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//SP1_UE_ERR_STATUS_HI
+#define SP1_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define SP1_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define SP1_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define SP1_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define SP1_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define SP1_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define SP1_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define SP1_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define SP1_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define SP1_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define SP1_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define SP1_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//SP1_CE_ERR_STATUS_LO
+#define SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define SP1_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define SP1_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define SP1_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define SP1_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//SP1_CE_ERR_STATUS_HI
+#define SP1_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define SP1_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define SP1_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define SP1_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define SP1_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define SP1_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define SP1_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define SP1_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define SP1_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define SP1_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define SP1_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define SP1_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
// addressBlock: xcd0_gc_shsdec
@@ -4235,6 +4469,54 @@
#define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK 0x00030000L
#define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK 0x000C0000L
#define SPI_EDC_CNT__UNUSED_MASK 0xFFF00000L
+//SPI_UE_ERR_STATUS_LO
+#define SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define SPI_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define SPI_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define SPI_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define SPI_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//SPI_UE_ERR_STATUS_HI
+#define SPI_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define SPI_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define SPI_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define SPI_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define SPI_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define SPI_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define SPI_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define SPI_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define SPI_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define SPI_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define SPI_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define SPI_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//SPI_CE_ERR_STATUS_LO
+#define SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define SPI_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define SPI_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define SPI_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define SPI_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//SPI_CE_ERR_STATUS_HI
+#define SPI_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define SPI_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define SPI_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define SPI_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define SPI_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define SPI_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define SPI_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define SPI_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define SPI_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define SPI_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define SPI_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define SPI_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
//SPI_DEBUG_BUSY
#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x0
#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x1
@@ -4622,6 +4904,48 @@
#define TD_POWER_CNTL__MGCG_OUTPUTSTAGE_MASK 0x00000002L
#define TD_POWER_CNTL__MID0_THREAD_DATA_MASK 0x00000004L
#define TD_POWER_CNTL__MID2_ACCUM_DATA_MASK 0x00000008L
+//TD_UE_EDC_LO
+#define TD_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0
+#define TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1
+#define TD_UE_EDC_LO__ADDRESS__SHIFT 0x2
+#define TD_UE_EDC_LO__MEM_ID__SHIFT 0x18
+#define TD_UE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L
+#define TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L
+#define TD_UE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL
+#define TD_UE_EDC_LO__MEM_ID_MASK 0xFF000000L
+//TD_UE_EDC_HI
+#define TD_UE_EDC_HI__ECC__SHIFT 0x0
+#define TD_UE_EDC_HI__PARITY__SHIFT 0x1
+#define TD_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define TD_UE_EDC_HI__ERR_INFO__SHIFT 0x3
+#define TD_UE_EDC_HI__UE_CNT__SHIFT 0x17
+#define TD_UE_EDC_HI__FED_CNT__SHIFT 0x1a
+#define TD_UE_EDC_HI__ECC_MASK 0x00000001L
+#define TD_UE_EDC_HI__PARITY_MASK 0x00000002L
+#define TD_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TD_UE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L
+#define TD_UE_EDC_HI__UE_CNT_MASK 0x03800000L
+#define TD_UE_EDC_HI__FED_CNT_MASK 0x1C000000L
+//TD_CE_EDC_LO
+#define TD_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0
+#define TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1
+#define TD_CE_EDC_LO__ADDRESS__SHIFT 0x2
+#define TD_CE_EDC_LO__MEM_ID__SHIFT 0x18
+#define TD_CE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L
+#define TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L
+#define TD_CE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL
+#define TD_CE_EDC_LO__MEM_ID_MASK 0xFF000000L
+//TD_CE_EDC_HI
+#define TD_CE_EDC_HI__ECC__SHIFT 0x0
+#define TD_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define TD_CE_EDC_HI__ERR_INFO__SHIFT 0x3
+#define TD_CE_EDC_HI__CE_CNT__SHIFT 0x17
+#define TD_CE_EDC_HI__POISON__SHIFT 0x1a
+#define TD_CE_EDC_HI__ECC_MASK 0x00000001L
+#define TD_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TD_CE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L
+#define TD_CE_EDC_HI__CE_CNT_MASK 0x03800000L
+#define TD_CE_EDC_HI__POISON_MASK 0x04000000L
//TD_DSM_CNTL
#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
@@ -4771,6 +5095,48 @@
#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT_MASK 0x000C0000L
#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY_MASK 0x00100000L
#define TA_DSM_CNTL2__TA_INJECT_DELAY_MASK 0xFC000000L
+//TA_UE_EDC_LO
+#define TA_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0
+#define TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1
+#define TA_UE_EDC_LO__ADDRESS__SHIFT 0x2
+#define TA_UE_EDC_LO__MEM_ID__SHIFT 0x18
+#define TA_UE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L
+#define TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L
+#define TA_UE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL
+#define TA_UE_EDC_LO__MEM_ID_MASK 0xFF000000L
+//TA_UE_EDC_HI
+#define TA_UE_EDC_HI__ECC__SHIFT 0x0
+#define TA_UE_EDC_HI__PARITY__SHIFT 0x1
+#define TA_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define TA_UE_EDC_HI__ERR_INFO__SHIFT 0x3
+#define TA_UE_EDC_HI__UE_CNT__SHIFT 0x17
+#define TA_UE_EDC_HI__FED_CNT__SHIFT 0x1a
+#define TA_UE_EDC_HI__ECC_MASK 0x00000001L
+#define TA_UE_EDC_HI__PARITY_MASK 0x00000002L
+#define TA_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TA_UE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L
+#define TA_UE_EDC_HI__UE_CNT_MASK 0x03800000L
+#define TA_UE_EDC_HI__FED_CNT_MASK 0x1C000000L
+//TA_CE_EDC_LO
+#define TA_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0
+#define TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1
+#define TA_CE_EDC_LO__ADDRESS__SHIFT 0x2
+#define TA_CE_EDC_LO__MEM_ID__SHIFT 0x18
+#define TA_CE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L
+#define TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L
+#define TA_CE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL
+#define TA_CE_EDC_LO__MEM_ID_MASK 0xFF000000L
+//TA_CE_EDC_HI
+#define TA_CE_EDC_HI__ECC__SHIFT 0x0
+#define TA_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define TA_CE_EDC_HI__ERR_INFO__SHIFT 0x3
+#define TA_CE_EDC_HI__CE_CNT__SHIFT 0x17
+#define TA_CE_EDC_HI__POISON__SHIFT 0x1a
+#define TA_CE_EDC_HI__ECC_MASK 0x00000001L
+#define TA_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TA_CE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L
+#define TA_CE_EDC_HI__CE_CNT_MASK 0x03800000L
+#define TA_CE_EDC_HI__POISON_MASK 0x04000000L
// addressBlock: xcd0_gc_gdsdec
@@ -5015,6 +5381,54 @@
#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
+//GDS_UE_ERR_STATUS_LO
+#define GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define GDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define GDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define GDS_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define GDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//GDS_UE_ERR_STATUS_HI
+#define GDS_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define GDS_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define GDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define GDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define GDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define GDS_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define GDS_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define GDS_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define GDS_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define GDS_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define GDS_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define GDS_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//GDS_CE_ERR_STATUS_LO
+#define GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define GDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define GDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define GDS_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define GDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//GDS_CE_ERR_STATUS_HI
+#define GDS_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define GDS_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define GDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define GDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define GDS_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define GDS_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define GDS_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define GDS_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define GDS_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define GDS_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define GDS_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define GDS_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
// addressBlock: xcd0_gc_rbdec
@@ -7370,6 +7784,30 @@
#define GCEA_MAM_CTRL2__ARAM_FLUSH_NOALLOC_MASK 0x00000040L
#define GCEA_MAM_CTRL2__RESERVED_FIELD_MASK 0x00FFFF80L
#define GCEA_MAM_CTRL2__ADDR_HI_MASK 0xFF000000L
+//GCEA_UE_ERR_STATUS_LO
+#define GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0
+#define GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define GCEA_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define GCEA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L
+#define GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define GCEA_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define GCEA_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//GCEA_UE_ERR_STATUS_HI
+#define GCEA_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define GCEA_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define GCEA_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define GCEA_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define GCEA_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d
+#define GCEA_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define GCEA_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define GCEA_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define GCEA_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define GCEA_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L
//GCEA_DSM_CNTL
#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
@@ -7745,6 +8183,30 @@
#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L
#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L
#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L
+//GCEA_CE_ERR_STATUS_LO
+#define GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0
+#define GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define GCEA_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define GCEA_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L
+#define GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define GCEA_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define GCEA_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//GCEA_CE_ERR_STATUS_HI
+#define GCEA_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1
+#define GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define GCEA_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define GCEA_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define GCEA_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b
+#define GCEA_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L
+#define GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define GCEA_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define GCEA_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define GCEA_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L
//GCEA_SDP_ENABLE
#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0
#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L
@@ -8440,6 +8902,54 @@
//ATC_L2_MM_GROUP_RT_CLASSES
#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0
#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL
+//ATC_L2_UE_ERR_STATUS_LO
+#define ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//ATC_L2_UE_ERR_STATUS_HI
+#define ATC_L2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define ATC_L2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define ATC_L2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define ATC_L2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define ATC_L2_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define ATC_L2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define ATC_L2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define ATC_L2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define ATC_L2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define ATC_L2_UE_ERR_STATUS_HI__RESERVED_MASK 0x60000000L
+//ATC_L2_CE_ERR_STATUS_LO
+#define ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//ATC_L2_CE_ERR_STATUS_HI
+#define ATC_L2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define ATC_L2_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define ATC_L2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define ATC_L2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define ATC_L2_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define ATC_L2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define ATC_L2_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define ATC_L2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define ATC_L2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define ATC_L2_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
// addressBlock: xcd0_gc_utcl2_vml2pfdec
@@ -8888,6 +9398,150 @@
#define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT 0x1
#define UTCL2_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L
#define UTCL2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+//VML2_UE_ERR_STATUS_LO
+#define VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define VML2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define VML2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define VML2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define VML2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//VML2_WALKER_UE_ERR_STATUS_LO
+#define VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//UTCL2_UE_ERR_STATUS_LO
+#define UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define UTCL2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define UTCL2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define UTCL2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define UTCL2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//VML2_UE_ERR_STATUS_HI
+#define VML2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define VML2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define VML2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define VML2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define VML2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define VML2_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define VML2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define VML2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define VML2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define VML2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define VML2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define VML2_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//VML2_WALKER_UE_ERR_STATUS_HI
+#define VML2_WALKER_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define VML2_WALKER_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define VML2_WALKER_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define VML2_WALKER_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define VML2_WALKER_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define VML2_WALKER_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//UTCL2_UE_ERR_STATUS_HI
+#define UTCL2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define UTCL2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define UTCL2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define UTCL2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define UTCL2_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define UTCL2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define UTCL2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define UTCL2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define UTCL2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define UTCL2_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//VML2_CE_ERR_STATUS_LO
+#define VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define VML2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define VML2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define VML2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define VML2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//VML2_WALKER_CE_ERR_STATUS_LO
+#define VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//UTCL2_CE_ERR_STATUS_LO
+#define UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define UTCL2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define UTCL2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define UTCL2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define UTCL2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//VML2_CE_ERR_STATUS_HI
+#define VML2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define VML2_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define VML2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define VML2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define VML2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define VML2_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define VML2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define VML2_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define VML2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define VML2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define VML2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define VML2_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
+//VML2_WALKER_CE_ERR_STATUS_HI
+#define VML2_WALKER_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define VML2_WALKER_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define VML2_WALKER_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define VML2_WALKER_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define VML2_WALKER_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define VML2_WALKER_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define VML2_WALKER_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define VML2_WALKER_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
+//UTCL2_CE_ERR_STATUS_HI
+#define UTCL2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define UTCL2_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define UTCL2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define UTCL2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define UTCL2_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define UTCL2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define UTCL2_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define UTCL2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define UTCL2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define UTCL2_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
// addressBlock: xcd0_gc_utcl2_vml2vcdec
@@ -11139,6 +11793,98 @@
//TC_CFG_L2_VOLATILE
#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL
+//TCP_UE_EDC_HI_REG
+#define TCP_UE_EDC_HI_REG__ECC__SHIFT 0x0
+#define TCP_UE_EDC_HI_REG__PARITY__SHIFT 0x1
+#define TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define TCP_UE_EDC_HI_REG__ERR_INFO__SHIFT 0x3
+#define TCP_UE_EDC_HI_REG__UE_CNT__SHIFT 0x17
+#define TCP_UE_EDC_HI_REG__FED_CNT__SHIFT 0x1a
+#define TCP_UE_EDC_HI_REG__RESERVED__SHIFT 0x1d
+#define TCP_UE_EDC_HI_REG__ECC_MASK 0x00000001L
+#define TCP_UE_EDC_HI_REG__PARITY_MASK 0x00000002L
+#define TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TCP_UE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L
+#define TCP_UE_EDC_HI_REG__UE_CNT_MASK 0x03800000L
+#define TCP_UE_EDC_HI_REG__FED_CNT_MASK 0x1C000000L
+#define TCP_UE_EDC_HI_REG__RESERVED_MASK 0xE0000000L
+//TCP_UE_EDC_LO_REG
+#define TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0
+#define TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1
+#define TCP_UE_EDC_LO_REG__ADDRESS__SHIFT 0x2
+#define TCP_UE_EDC_LO_REG__MEM_ID__SHIFT 0x18
+#define TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L
+#define TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L
+#define TCP_UE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL
+#define TCP_UE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L
+//TCP_CE_EDC_HI_REG
+#define TCP_CE_EDC_HI_REG__ECC__SHIFT 0x0
+#define TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define TCP_CE_EDC_HI_REG__ERR_INFO__SHIFT 0x3
+#define TCP_CE_EDC_HI_REG__CE_CNT__SHIFT 0x17
+#define TCP_CE_EDC_HI_REG__POISON__SHIFT 0x1a
+#define TCP_CE_EDC_HI_REG__RESERVED__SHIFT 0x1b
+#define TCP_CE_EDC_HI_REG__ECC_MASK 0x00000001L
+#define TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TCP_CE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L
+#define TCP_CE_EDC_HI_REG__CE_CNT_MASK 0x03800000L
+#define TCP_CE_EDC_HI_REG__POISON_MASK 0x04000000L
+#define TCP_CE_EDC_HI_REG__RESERVED_MASK 0xF8000000L
+//TCP_CE_EDC_LO_REG
+#define TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0
+#define TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1
+#define TCP_CE_EDC_LO_REG__ADDRESS__SHIFT 0x2
+#define TCP_CE_EDC_LO_REG__MEM_ID__SHIFT 0x18
+#define TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L
+#define TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L
+#define TCP_CE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL
+#define TCP_CE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L
+//TCI_UE_EDC_HI_REG
+#define TCI_UE_EDC_HI_REG__ECC__SHIFT 0x0
+#define TCI_UE_EDC_HI_REG__PARITY__SHIFT 0x1
+#define TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define TCI_UE_EDC_HI_REG__ERR_INFO__SHIFT 0x3
+#define TCI_UE_EDC_HI_REG__UE_CNT__SHIFT 0x17
+#define TCI_UE_EDC_HI_REG__FED_CNT__SHIFT 0x1a
+#define TCI_UE_EDC_HI_REG__RESERVED__SHIFT 0x1d
+#define TCI_UE_EDC_HI_REG__ECC_MASK 0x00000001L
+#define TCI_UE_EDC_HI_REG__PARITY_MASK 0x00000002L
+#define TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TCI_UE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L
+#define TCI_UE_EDC_HI_REG__UE_CNT_MASK 0x03800000L
+#define TCI_UE_EDC_HI_REG__FED_CNT_MASK 0x1C000000L
+#define TCI_UE_EDC_HI_REG__RESERVED_MASK 0xE0000000L
+//TCI_UE_EDC_LO_REG
+#define TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0
+#define TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1
+#define TCI_UE_EDC_LO_REG__ADDRESS__SHIFT 0x2
+#define TCI_UE_EDC_LO_REG__MEM_ID__SHIFT 0x18
+#define TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L
+#define TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L
+#define TCI_UE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL
+#define TCI_UE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L
+//TCI_CE_EDC_HI_REG
+#define TCI_CE_EDC_HI_REG__ECC__SHIFT 0x0
+#define TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define TCI_CE_EDC_HI_REG__ERR_INFO__SHIFT 0x3
+#define TCI_CE_EDC_HI_REG__CE_CNT__SHIFT 0x17
+#define TCI_CE_EDC_HI_REG__POISON__SHIFT 0x1a
+#define TCI_CE_EDC_HI_REG__RESERVED__SHIFT 0x1b
+#define TCI_CE_EDC_HI_REG__ECC_MASK 0x00000001L
+#define TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TCI_CE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L
+#define TCI_CE_EDC_HI_REG__CE_CNT_MASK 0x03800000L
+#define TCI_CE_EDC_HI_REG__POISON_MASK 0x04000000L
+#define TCI_CE_EDC_HI_REG__RESERVED_MASK 0xF8000000L
+//TCI_CE_EDC_LO_REG
+#define TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0
+#define TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1
+#define TCI_CE_EDC_LO_REG__ADDRESS__SHIFT 0x2
+#define TCI_CE_EDC_LO_REG__MEM_ID__SHIFT 0x18
+#define TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L
+#define TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L
+#define TCI_CE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL
+#define TCI_CE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L
//TCI_MISC
#define TCI_MISC__FGCG_REPEATER_DISABLE__SHIFT 0x0
#define TCI_MISC__LEGACY_MGCG_DISABLE__SHIFT 0x1
@@ -11560,6 +12306,112 @@
#define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY_MASK 0x00000004L
#define TCX_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//TCA_UE_ERR_STATUS_LO
+#define TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define TCA_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define TCA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define TCA_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define TCA_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//TCA_UE_ERR_STATUS_HI
+#define TCA_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define TCA_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2
+#define TCA_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3
+#define TCA_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define TCA_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define TCA_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define TCA_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TCA_UE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L
+#define TCA_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define TCA_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+//TCX_UE_ERR_STATUS_LO
+#define TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define TCX_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define TCX_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define TCX_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define TCX_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//TCX_UE_ERR_STATUS_HI
+#define TCX_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define TCX_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2
+#define TCX_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3
+#define TCX_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define TCX_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define TCX_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define TCX_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TCX_UE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L
+#define TCX_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define TCX_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+//TCX_CE_ERR_STATUS_LO
+#define TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define TCX_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define TCX_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define TCX_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define TCX_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//TCX_CE_ERR_STATUS_HI
+#define TCX_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2
+#define TCX_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3
+#define TCX_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define TCX_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define TCX_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TCX_CE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L
+#define TCX_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define TCX_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+//TCC_UE_ERR_STATUS_LO
+#define TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define TCC_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define TCC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define TCC_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define TCC_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//TCC_UE_ERR_STATUS_HI
+#define TCC_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define TCC_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2
+#define TCC_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3
+#define TCC_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define TCC_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define TCC_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define TCC_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TCC_UE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L
+#define TCC_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define TCC_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+//TCC_CE_ERR_STATUS_LO
+#define TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define TCC_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define TCC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define TCC_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define TCC_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//TCC_CE_ERR_STATUS_HI
+#define TCC_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2
+#define TCC_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3
+#define TCC_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define TCC_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define TCC_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L
+#define TCC_CE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L
+#define TCC_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define TCC_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
// addressBlock: xcd0_gc_shdec
@@ -14384,6 +15236,150 @@
#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL
#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L
+//CPC_UE_ERR_STATUS_LO
+#define CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define CPC_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define CPC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define CPC_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define CPC_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//CPC_UE_ERR_STATUS_HI
+#define CPC_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define CPC_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define CPC_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define CPC_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define CPC_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define CPC_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define CPC_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define CPC_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define CPC_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define CPC_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define CPC_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define CPC_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//CPC_CE_ERR_STATUS_LO
+#define CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define CPC_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define CPC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define CPC_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define CPC_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//CPC_CE_ERR_STATUS_HI
+#define CPC_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define CPC_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define CPC_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define CPC_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define CPC_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define CPC_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define CPC_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define CPC_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define CPC_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define CPC_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define CPC_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define CPC_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
+//CPF_UE_ERR_STATUS_LO
+#define CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define CPF_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define CPF_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define CPF_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define CPF_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//CPF_UE_ERR_STATUS_HI
+#define CPF_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define CPF_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define CPF_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define CPF_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define CPF_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define CPF_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define CPF_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define CPF_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define CPF_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define CPF_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define CPF_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define CPF_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//CPF_CE_ERR_STATUS_LO
+#define CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define CPF_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define CPF_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define CPF_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define CPF_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//CPF_CE_ERR_STATUS_HI
+#define CPF_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define CPF_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define CPF_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define CPF_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define CPF_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define CPF_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define CPF_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define CPF_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define CPF_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define CPF_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define CPF_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define CPF_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
+//CPG_UE_ERR_STATUS_LO
+#define CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define CPG_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define CPG_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define CPG_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define CPG_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//CPG_UE_ERR_STATUS_HI
+#define CPG_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define CPG_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define CPG_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define CPG_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define CPG_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define CPG_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
+#define CPG_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define CPG_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define CPG_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define CPG_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define CPG_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+#define CPG_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
+//CPG_CE_ERR_STATUS_LO
+#define CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define CPG_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define CPG_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define CPG_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define CPG_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//CPG_CE_ERR_STATUS_HI
+#define CPG_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define CPG_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1
+#define CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define CPG_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define CPG_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define CPG_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define CPG_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b
+#define CPG_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define CPG_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L
+#define CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define CPG_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define CPG_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define CPG_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
+#define CPG_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L
// addressBlock: xcd0_gc_cppdec2
@@ -22764,6 +23760,74 @@
#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L
#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L
+// addressBlock: xcd0_gc_gccanedec
+//GC_CANE_ERR_STATUS
+#define GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS__SHIFT 0x0
+#define GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS__SHIFT 0x4
+#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS__SHIFT 0x8
+#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define GC_CANE_ERR_STATUS__SDPS_DAT_ERROR__SHIFT 0xb
+#define GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR__SHIFT 0xc
+#define GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xd
+#define GC_CANE_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xe
+#define GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR__SHIFT 0xf
+#define GC_CANE_ERR_STATUS__FUE_FLAG__SHIFT 0x10
+#define GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0x11
+#define GC_CANE_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x12
+#define GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS_MASK 0x0000000FL
+#define GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS_MASK 0x000000F0L
+#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS_MASK 0x00000300L
+#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define GC_CANE_ERR_STATUS__SDPS_DAT_ERROR_MASK 0x00000800L
+#define GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR_MASK 0x00001000L
+#define GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00002000L
+#define GC_CANE_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00004000L
+#define GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR_MASK 0x00008000L
+#define GC_CANE_ERR_STATUS__FUE_FLAG_MASK 0x00010000L
+#define GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00020000L
+#define GC_CANE_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00040000L
+//GC_CANE_UE_ERR_STATUS_LO
+#define GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//GC_CANE_UE_ERR_STATUS_HI
+#define GC_CANE_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define GC_CANE_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
+#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define GC_CANE_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
+#define GC_CANE_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
+#define GC_CANE_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define GC_CANE_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
+#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define GC_CANE_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
+#define GC_CANE_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
+//GC_CANE_CE_ERR_STATUS_LO
+#define GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
+#define GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
+#define GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
+#define GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
+//GC_CANE_CE_ERR_STATUS_HI
+#define GC_CANE_CE_ERR_STATUS_HI__ECC__SHIFT 0x0
+#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
+#define GC_CANE_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17
+#define GC_CANE_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a
+#define GC_CANE_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L
+#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
+#define GC_CANE_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L
+#define GC_CANE_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L
// addressBlock: xcd0_gc_perfddec
//CPG_PERFCOUNTER1_LO
@@ -26471,6 +27535,30 @@
//RLC_CPG_STAT_INVAL
#define RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT 0x0
#define RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK 0x00000001L
+//RLC_UE_ERR_STATUS_LOW
+#define RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define RLC_UE_ERR_STATUS_LOW__ADDRESS__SHIFT 0x2
+#define RLC_UE_ERR_STATUS_LOW__MEMORY_ID__SHIFT 0x18
+#define RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define RLC_UE_ERR_STATUS_LOW__ADDRESS_MASK 0x00FFFFFCL
+#define RLC_UE_ERR_STATUS_LOW__MEMORY_ID_MASK 0xFF000000L
+//RLC_UE_ERR_STATUS_HIGH
+#define RLC_UE_ERR_STATUS_HIGH__ECC__SHIFT 0x0
+#define RLC_UE_ERR_STATUS_HIGH__PARITY__SHIFT 0x1
+#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO__SHIFT 0x3
+#define RLC_UE_ERR_STATUS_HIGH__UE_CNT__SHIFT 0x17
+#define RLC_UE_ERR_STATUS_HIGH__FED_CNT__SHIFT 0x1a
+#define RLC_UE_ERR_STATUS_HIGH__RESERVED__SHIFT 0x1d
+#define RLC_UE_ERR_STATUS_HIGH__ECC_MASK 0x00000001L
+#define RLC_UE_ERR_STATUS_HIGH__PARITY_MASK 0x00000002L
+#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_MASK 0x007FFFF8L
+#define RLC_UE_ERR_STATUS_HIGH__UE_CNT_MASK 0x03800000L
+#define RLC_UE_ERR_STATUS_HIGH__FED_CNT_MASK 0x1C000000L
+#define RLC_UE_ERR_STATUS_HIGH__RESERVED_MASK 0xE0000000L
//RLC_DSM_CNTL
#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
@@ -26573,6 +27661,30 @@
#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
+//RLC_CE_ERR_STATUS_LOW
+#define RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT 0x0
+#define RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT 0x1
+#define RLC_CE_ERR_STATUS_LOW__ADDRESS__SHIFT 0x2
+#define RLC_CE_ERR_STATUS_LOW__MEMORY_ID__SHIFT 0x18
+#define RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
+#define RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK 0x00000002L
+#define RLC_CE_ERR_STATUS_LOW__ADDRESS_MASK 0x00FFFFFCL
+#define RLC_CE_ERR_STATUS_LOW__MEMORY_ID_MASK 0xFF000000L
+//RLC_CE_ERR_STATUS_HIGH
+#define RLC_CE_ERR_STATUS_HIGH__ECC__SHIFT 0x0
+#define RLC_CE_ERR_STATUS_HIGH__OTHER__SHIFT 0x1
+#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT 0x2
+#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO__SHIFT 0x3
+#define RLC_CE_ERR_STATUS_HIGH__CE_CNT__SHIFT 0x17
+#define RLC_CE_ERR_STATUS_HIGH__POISON__SHIFT 0x1a
+#define RLC_CE_ERR_STATUS_HIGH__RESERVED__SHIFT 0x1b
+#define RLC_CE_ERR_STATUS_HIGH__ECC_MASK 0x00000001L
+#define RLC_CE_ERR_STATUS_HIGH__OTHER_MASK 0x00000002L
+#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK 0x00000004L
+#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_MASK 0x007FFFF8L
+#define RLC_CE_ERR_STATUS_HIGH__CE_CNT_MASK 0x03800000L
+#define RLC_CE_ERR_STATUS_HIGH__POISON_MASK 0x04000000L
+#define RLC_CE_ERR_STATUS_HIGH__RESERVED_MASK 0xF8000000L
//RLC_RLCV_SPARE_INT
#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0
#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1
--
2.40.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 05/10] drm/amdgpu: add RAS definitions for GFX
2023-05-12 21:43 [PATCH 01/10] drm/amdgpu: add GFX RAS common function Alex Deucher
` (2 preceding siblings ...)
2023-05-12 21:43 ` [PATCH 04/10] drm/amdgpu: Add gc v9_4_3 ras error status registers Alex Deucher
@ 2023-05-12 21:43 ` Alex Deucher
2023-05-12 21:43 ` [PATCH 06/10] drm/amdgpu: add RAS error count definitions for gfx_v9_4_3 Alex Deucher
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Alex Deucher @ 2023-05-12 21:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tao Zhou, Hawking Zhang
From: Tao Zhou <tao.zhou1@amd.com>
Add common GFX RAS definitions.
v2: remove instance from amdgpu_gfx_ras_reg_entry,
amdgpu_ras_err_status_reg_entry has already defined it.
v3: remove memory id definitions from amdgpu_gfx.h, they are
related to IP version.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 39 +++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index f07117d8959b..7422db02aeda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -75,6 +75,32 @@ enum amdgpu_pkg_type {
AMDGPU_PKG_TYPE_UNKNOWN,
};
+enum amdgpu_gfx_ras_mem_id_type {
+ AMDGPU_GFX_CP_MEM = 0,
+ AMDGPU_GFX_GCEA_MEM,
+ AMDGPU_GFX_GC_CANE_MEM,
+ AMDGPU_GFX_GCUTCL2_MEM,
+ AMDGPU_GFX_GDS_MEM,
+ AMDGPU_GFX_LDS_MEM,
+ AMDGPU_GFX_RLC_MEM,
+ AMDGPU_GFX_SP_MEM,
+ AMDGPU_GFX_SPI_MEM,
+ AMDGPU_GFX_SQC_MEM,
+ AMDGPU_GFX_SQ_MEM,
+ AMDGPU_GFX_TA_MEM,
+ AMDGPU_GFX_TCC_MEM,
+ AMDGPU_GFX_TCA_MEM,
+ AMDGPU_GFX_TCI_MEM,
+ AMDGPU_GFX_TCP_MEM,
+ AMDGPU_GFX_TD_MEM,
+ AMDGPU_GFX_TCX_MEM,
+ AMDGPU_GFX_ATC_L2_MEM,
+ AMDGPU_GFX_UTCL2_MEM,
+ AMDGPU_GFX_VML2_MEM,
+ AMDGPU_GFX_VML2_WALKER_MEM,
+ AMDGPU_GFX_MEM_TYPE_NUM
+};
+
struct amdgpu_mec {
struct amdgpu_bo *hpd_eop_obj;
u64 hpd_eop_gpu_addr;
@@ -412,6 +438,19 @@ struct amdgpu_gfx {
struct mutex partition_mutex;
};
+struct amdgpu_gfx_ras_reg_entry {
+ struct amdgpu_ras_err_status_reg_entry reg_entry;
+ enum amdgpu_gfx_ras_mem_id_type mem_id_type;
+ uint32_t se_num;
+};
+
+struct amdgpu_gfx_ras_mem_id_entry {
+ const struct amdgpu_ras_memory_id_entry *mem_id_ent;
+ uint32_t size;
+};
+
+#define AMDGPU_GFX_MEMID_ENT(x) {(x), ARRAY_SIZE(x)},
+
#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))
--
2.40.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 06/10] drm/amdgpu: add RAS error count definitions for gfx_v9_4_3
2023-05-12 21:43 [PATCH 01/10] drm/amdgpu: add GFX RAS common function Alex Deucher
` (3 preceding siblings ...)
2023-05-12 21:43 ` [PATCH 05/10] drm/amdgpu: add RAS definitions for GFX Alex Deucher
@ 2023-05-12 21:43 ` Alex Deucher
2023-05-12 21:43 ` [PATCH 07/10] drm/amdgpu: add RAS error count query " Alex Deucher
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Alex Deucher @ 2023-05-12 21:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tao Zhou, Hawking Zhang
From: Tao Zhou <tao.zhou1@amd.com>
Prepare for the query of GFX RAS ce/ue count.
v2: remove xcp operation.
only select_se_sh when instance number is more than 1.
v3: add more CE/UE registsers to query list.
add check for se_num before select_se_sh.
change instance from 0 to xcc_id for register access.
v4: move gfx memory id definitions to gfx_v9_4_3.
v5: create a dedicated patch for adding error count query function.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 740 ++++++++++++++++++++++++
1 file changed, 740 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index e6069d081f71..188b4d9a2cbb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2980,6 +2980,746 @@ static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
}
}
+enum amdgpu_gfx_cp_ras_mem_id {
+ AMDGPU_GFX_CP_MEM1 = 1,
+ AMDGPU_GFX_CP_MEM2,
+ AMDGPU_GFX_CP_MEM3,
+ AMDGPU_GFX_CP_MEM4,
+ AMDGPU_GFX_CP_MEM5,
+};
+
+enum amdgpu_gfx_gcea_ras_mem_id {
+ AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4,
+ AMDGPU_GFX_GCEA_IORD_CMDMEM,
+ AMDGPU_GFX_GCEA_GMIWR_CMDMEM,
+ AMDGPU_GFX_GCEA_GMIRD_CMDMEM,
+ AMDGPU_GFX_GCEA_DRAMWR_CMDMEM,
+ AMDGPU_GFX_GCEA_DRAMRD_CMDMEM,
+ AMDGPU_GFX_GCEA_MAM_DMEM0,
+ AMDGPU_GFX_GCEA_MAM_DMEM1,
+ AMDGPU_GFX_GCEA_MAM_DMEM2,
+ AMDGPU_GFX_GCEA_MAM_DMEM3,
+ AMDGPU_GFX_GCEA_MAM_AMEM0,
+ AMDGPU_GFX_GCEA_MAM_AMEM1,
+ AMDGPU_GFX_GCEA_MAM_AMEM2,
+ AMDGPU_GFX_GCEA_MAM_AMEM3,
+ AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER,
+ AMDGPU_GFX_GCEA_WRET_TAGMEM,
+ AMDGPU_GFX_GCEA_RRET_TAGMEM,
+ AMDGPU_GFX_GCEA_IOWR_DATAMEM,
+ AMDGPU_GFX_GCEA_GMIWR_DATAMEM,
+ AMDGPU_GFX_GCEA_DRAM_DATAMEM,
+};
+
+enum amdgpu_gfx_gc_cane_ras_mem_id {
+ AMDGPU_GFX_GC_CANE_MEM0 = 0,
+};
+
+enum amdgpu_gfx_gcutcl2_ras_mem_id {
+ AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160,
+};
+
+enum amdgpu_gfx_gds_ras_mem_id {
+ AMDGPU_GFX_GDS_MEM0 = 0,
+};
+
+enum amdgpu_gfx_lds_ras_mem_id {
+ AMDGPU_GFX_LDS_BANK0 = 0,
+ AMDGPU_GFX_LDS_BANK1,
+ AMDGPU_GFX_LDS_BANK2,
+ AMDGPU_GFX_LDS_BANK3,
+ AMDGPU_GFX_LDS_BANK4,
+ AMDGPU_GFX_LDS_BANK5,
+ AMDGPU_GFX_LDS_BANK6,
+ AMDGPU_GFX_LDS_BANK7,
+ AMDGPU_GFX_LDS_BANK8,
+ AMDGPU_GFX_LDS_BANK9,
+ AMDGPU_GFX_LDS_BANK10,
+ AMDGPU_GFX_LDS_BANK11,
+ AMDGPU_GFX_LDS_BANK12,
+ AMDGPU_GFX_LDS_BANK13,
+ AMDGPU_GFX_LDS_BANK14,
+ AMDGPU_GFX_LDS_BANK15,
+ AMDGPU_GFX_LDS_BANK16,
+ AMDGPU_GFX_LDS_BANK17,
+ AMDGPU_GFX_LDS_BANK18,
+ AMDGPU_GFX_LDS_BANK19,
+ AMDGPU_GFX_LDS_BANK20,
+ AMDGPU_GFX_LDS_BANK21,
+ AMDGPU_GFX_LDS_BANK22,
+ AMDGPU_GFX_LDS_BANK23,
+ AMDGPU_GFX_LDS_BANK24,
+ AMDGPU_GFX_LDS_BANK25,
+ AMDGPU_GFX_LDS_BANK26,
+ AMDGPU_GFX_LDS_BANK27,
+ AMDGPU_GFX_LDS_BANK28,
+ AMDGPU_GFX_LDS_BANK29,
+ AMDGPU_GFX_LDS_BANK30,
+ AMDGPU_GFX_LDS_BANK31,
+ AMDGPU_GFX_LDS_SP_BUFFER_A,
+ AMDGPU_GFX_LDS_SP_BUFFER_B,
+};
+
+enum amdgpu_gfx_rlc_ras_mem_id {
+ AMDGPU_GFX_RLC_GPMF32 = 1,
+ AMDGPU_GFX_RLC_RLCVF32,
+ AMDGPU_GFX_RLC_SCRATCH,
+ AMDGPU_GFX_RLC_SRM_ARAM,
+ AMDGPU_GFX_RLC_SRM_DRAM,
+ AMDGPU_GFX_RLC_TCTAG,
+ AMDGPU_GFX_RLC_SPM_SE,
+ AMDGPU_GFX_RLC_SPM_GRBMT,
+};
+
+enum amdgpu_gfx_sp_ras_mem_id {
+ AMDGPU_GFX_SP_SIMDID0 = 0,
+};
+
+enum amdgpu_gfx_spi_ras_mem_id {
+ AMDGPU_GFX_SPI_MEM0 = 0,
+ AMDGPU_GFX_SPI_MEM1,
+ AMDGPU_GFX_SPI_MEM2,
+ AMDGPU_GFX_SPI_MEM3,
+};
+
+enum amdgpu_gfx_sqc_ras_mem_id {
+ AMDGPU_GFX_SQC_INST_CACHE_A = 100,
+ AMDGPU_GFX_SQC_INST_CACHE_B = 101,
+ AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102,
+ AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103,
+ AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104,
+ AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105,
+ AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106,
+ AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107,
+ AMDGPU_GFX_SQC_DATA_CACHE_A = 200,
+ AMDGPU_GFX_SQC_DATA_CACHE_B = 201,
+ AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202,
+ AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203,
+ AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204,
+ AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205,
+ AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206,
+ AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207,
+ AMDGPU_GFX_SQC_DIRTY_BIT_A = 208,
+ AMDGPU_GFX_SQC_DIRTY_BIT_B = 209,
+ AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210,
+ AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211,
+ AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212,
+ AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213,
+ AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108,
+};
+
+enum amdgpu_gfx_sq_ras_mem_id {
+ AMDGPU_GFX_SQ_SGPR_MEM0 = 0,
+ AMDGPU_GFX_SQ_SGPR_MEM1,
+ AMDGPU_GFX_SQ_SGPR_MEM2,
+ AMDGPU_GFX_SQ_SGPR_MEM3,
+};
+
+enum amdgpu_gfx_ta_ras_mem_id {
+ AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1,
+ AMDGPU_GFX_TA_FS_AFIFO_RAM_HI,
+ AMDGPU_GFX_TA_FS_CFIFO_RAM,
+ AMDGPU_GFX_TA_FSX_LFIFO,
+ AMDGPU_GFX_TA_FS_DFIFO_RAM,
+};
+
+enum amdgpu_gfx_tcc_ras_mem_id {
+ AMDGPU_GFX_TCC_MEM1 = 1,
+};
+
+enum amdgpu_gfx_tca_ras_mem_id {
+ AMDGPU_GFX_TCA_MEM1 = 1,
+};
+
+enum amdgpu_gfx_tci_ras_mem_id {
+ AMDGPU_GFX_TCIW_MEM = 1,
+};
+
+enum amdgpu_gfx_tcp_ras_mem_id {
+ AMDGPU_GFX_TCP_LFIFO0 = 1,
+ AMDGPU_GFX_TCP_SET0BANK0_RAM,
+ AMDGPU_GFX_TCP_SET0BANK1_RAM,
+ AMDGPU_GFX_TCP_SET0BANK2_RAM,
+ AMDGPU_GFX_TCP_SET0BANK3_RAM,
+ AMDGPU_GFX_TCP_SET1BANK0_RAM,
+ AMDGPU_GFX_TCP_SET1BANK1_RAM,
+ AMDGPU_GFX_TCP_SET1BANK2_RAM,
+ AMDGPU_GFX_TCP_SET1BANK3_RAM,
+ AMDGPU_GFX_TCP_SET2BANK0_RAM,
+ AMDGPU_GFX_TCP_SET2BANK1_RAM,
+ AMDGPU_GFX_TCP_SET2BANK2_RAM,
+ AMDGPU_GFX_TCP_SET2BANK3_RAM,
+ AMDGPU_GFX_TCP_SET3BANK0_RAM,
+ AMDGPU_GFX_TCP_SET3BANK1_RAM,
+ AMDGPU_GFX_TCP_SET3BANK2_RAM,
+ AMDGPU_GFX_TCP_SET3BANK3_RAM,
+ AMDGPU_GFX_TCP_VM_FIFO,
+ AMDGPU_GFX_TCP_DB_TAGRAM0,
+ AMDGPU_GFX_TCP_DB_TAGRAM1,
+ AMDGPU_GFX_TCP_DB_TAGRAM2,
+ AMDGPU_GFX_TCP_DB_TAGRAM3,
+ AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0,
+ AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1,
+ AMDGPU_GFX_TCP_CMD_FIFO,
+};
+
+enum amdgpu_gfx_td_ras_mem_id {
+ AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1,
+ AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM,
+ AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM,
+};
+
+enum amdgpu_gfx_tcx_ras_mem_id {
+ AMDGPU_GFX_TCX_FIFOD0 = 0,
+ AMDGPU_GFX_TCX_FIFOD1,
+ AMDGPU_GFX_TCX_FIFOD2,
+ AMDGPU_GFX_TCX_FIFOD3,
+ AMDGPU_GFX_TCX_FIFOD4,
+ AMDGPU_GFX_TCX_FIFOD5,
+ AMDGPU_GFX_TCX_FIFOD6,
+ AMDGPU_GFX_TCX_FIFOD7,
+ AMDGPU_GFX_TCX_FIFOB0,
+ AMDGPU_GFX_TCX_FIFOB1,
+ AMDGPU_GFX_TCX_FIFOB2,
+ AMDGPU_GFX_TCX_FIFOB3,
+ AMDGPU_GFX_TCX_FIFOB4,
+ AMDGPU_GFX_TCX_FIFOB5,
+ AMDGPU_GFX_TCX_FIFOB6,
+ AMDGPU_GFX_TCX_FIFOB7,
+ AMDGPU_GFX_TCX_FIFOA0,
+ AMDGPU_GFX_TCX_FIFOA1,
+ AMDGPU_GFX_TCX_FIFOA2,
+ AMDGPU_GFX_TCX_FIFOA3,
+ AMDGPU_GFX_TCX_FIFOA4,
+ AMDGPU_GFX_TCX_FIFOA5,
+ AMDGPU_GFX_TCX_FIFOA6,
+ AMDGPU_GFX_TCX_FIFOA7,
+ AMDGPU_GFX_TCX_CFIFO0,
+ AMDGPU_GFX_TCX_CFIFO1,
+ AMDGPU_GFX_TCX_CFIFO2,
+ AMDGPU_GFX_TCX_CFIFO3,
+ AMDGPU_GFX_TCX_CFIFO4,
+ AMDGPU_GFX_TCX_CFIFO5,
+ AMDGPU_GFX_TCX_CFIFO6,
+ AMDGPU_GFX_TCX_CFIFO7,
+ AMDGPU_GFX_TCX_FIFO_ACKB0,
+ AMDGPU_GFX_TCX_FIFO_ACKB1,
+ AMDGPU_GFX_TCX_FIFO_ACKB2,
+ AMDGPU_GFX_TCX_FIFO_ACKB3,
+ AMDGPU_GFX_TCX_FIFO_ACKB4,
+ AMDGPU_GFX_TCX_FIFO_ACKB5,
+ AMDGPU_GFX_TCX_FIFO_ACKB6,
+ AMDGPU_GFX_TCX_FIFO_ACKB7,
+ AMDGPU_GFX_TCX_FIFO_ACKD0,
+ AMDGPU_GFX_TCX_FIFO_ACKD1,
+ AMDGPU_GFX_TCX_FIFO_ACKD2,
+ AMDGPU_GFX_TCX_FIFO_ACKD3,
+ AMDGPU_GFX_TCX_FIFO_ACKD4,
+ AMDGPU_GFX_TCX_FIFO_ACKD5,
+ AMDGPU_GFX_TCX_FIFO_ACKD6,
+ AMDGPU_GFX_TCX_FIFO_ACKD7,
+ AMDGPU_GFX_TCX_DST_FIFOA0,
+ AMDGPU_GFX_TCX_DST_FIFOA1,
+ AMDGPU_GFX_TCX_DST_FIFOA2,
+ AMDGPU_GFX_TCX_DST_FIFOA3,
+ AMDGPU_GFX_TCX_DST_FIFOA4,
+ AMDGPU_GFX_TCX_DST_FIFOA5,
+ AMDGPU_GFX_TCX_DST_FIFOA6,
+ AMDGPU_GFX_TCX_DST_FIFOA7,
+ AMDGPU_GFX_TCX_DST_FIFOB0,
+ AMDGPU_GFX_TCX_DST_FIFOB1,
+ AMDGPU_GFX_TCX_DST_FIFOB2,
+ AMDGPU_GFX_TCX_DST_FIFOB3,
+ AMDGPU_GFX_TCX_DST_FIFOB4,
+ AMDGPU_GFX_TCX_DST_FIFOB5,
+ AMDGPU_GFX_TCX_DST_FIFOB6,
+ AMDGPU_GFX_TCX_DST_FIFOB7,
+ AMDGPU_GFX_TCX_DST_FIFOD0,
+ AMDGPU_GFX_TCX_DST_FIFOD1,
+ AMDGPU_GFX_TCX_DST_FIFOD2,
+ AMDGPU_GFX_TCX_DST_FIFOD3,
+ AMDGPU_GFX_TCX_DST_FIFOD4,
+ AMDGPU_GFX_TCX_DST_FIFOD5,
+ AMDGPU_GFX_TCX_DST_FIFOD6,
+ AMDGPU_GFX_TCX_DST_FIFOD7,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKB0,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKB1,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKB2,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKB3,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKB4,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKB5,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKB6,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKB7,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKD0,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKD1,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKD2,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKD3,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKD4,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKD5,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKD6,
+ AMDGPU_GFX_TCX_DST_FIFO_ACKD7,
+};
+
+enum amdgpu_gfx_atc_l2_ras_mem_id {
+ AMDGPU_GFX_ATC_L2_MEM0 = 0,
+};
+
+enum amdgpu_gfx_utcl2_ras_mem_id {
+ AMDGPU_GFX_UTCL2_MEM0 = 0,
+};
+
+enum amdgpu_gfx_vml2_ras_mem_id {
+ AMDGPU_GFX_VML2_MEM0 = 0,
+};
+
+enum amdgpu_gfx_vml2_walker_ras_mem_id {
+ AMDGPU_GFX_VML2_WALKER_MEM0 = 0,
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = {
+ {AMDGPU_GFX_CP_MEM1, "CP_MEM1"},
+ {AMDGPU_GFX_CP_MEM2, "CP_MEM2"},
+ {AMDGPU_GFX_CP_MEM3, "CP_MEM3"},
+ {AMDGPU_GFX_CP_MEM4, "CP_MEM4"},
+ {AMDGPU_GFX_CP_MEM5, "CP_MEM5"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = {
+ {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"},
+ {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"},
+ {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"},
+ {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"},
+ {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"},
+ {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"},
+ {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"},
+ {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"},
+ {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"},
+ {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"},
+ {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"},
+ {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"},
+ {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"},
+ {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"},
+ {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"},
+ {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"},
+ {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"},
+ {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"},
+ {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"},
+ {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = {
+ {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = {
+ {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = {
+ {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = {
+ {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"},
+ {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"},
+ {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"},
+ {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"},
+ {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"},
+ {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"},
+ {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"},
+ {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"},
+ {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"},
+ {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"},
+ {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"},
+ {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"},
+ {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"},
+ {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"},
+ {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"},
+ {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"},
+ {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"},
+ {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"},
+ {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"},
+ {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"},
+ {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"},
+ {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"},
+ {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"},
+ {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"},
+ {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"},
+ {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"},
+ {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"},
+ {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"},
+ {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"},
+ {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"},
+ {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"},
+ {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"},
+ {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"},
+ {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = {
+ {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"},
+ {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"},
+ {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"},
+ {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"},
+ {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"},
+ {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"},
+ {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"},
+ {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = {
+ {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = {
+ {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"},
+ {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"},
+ {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"},
+ {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = {
+ {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"},
+ {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"},
+ {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"},
+ {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"},
+ {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"},
+ {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"},
+ {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"},
+ {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"},
+ {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"},
+ {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"},
+ {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"},
+ {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"},
+ {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"},
+ {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"},
+ {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"},
+ {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"},
+ {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"},
+ {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"},
+ {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"},
+ {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"},
+ {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"},
+ {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"},
+ {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = {
+ {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"},
+ {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"},
+ {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"},
+ {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = {
+ {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"},
+ {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"},
+ {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"},
+ {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"},
+ {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = {
+ {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = {
+ {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = {
+ {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = {
+ {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"},
+ {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"},
+ {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"},
+ {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"},
+ {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"},
+ {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"},
+ {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"},
+ {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"},
+ {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"},
+ {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"},
+ {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"},
+ {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"},
+ {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"},
+ {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"},
+ {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"},
+ {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"},
+ {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"},
+ {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"},
+ {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"},
+ {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"},
+ {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"},
+ {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"},
+ {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"},
+ {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"},
+ {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = {
+ {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"},
+ {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"},
+ {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = {
+ {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"},
+ {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"},
+ {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"},
+ {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"},
+ {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"},
+ {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"},
+ {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"},
+ {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"},
+ {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"},
+ {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"},
+ {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"},
+ {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"},
+ {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"},
+ {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"},
+ {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"},
+ {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"},
+ {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"},
+ {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"},
+ {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"},
+ {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"},
+ {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"},
+ {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"},
+ {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"},
+ {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"},
+ {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"},
+ {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"},
+ {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"},
+ {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"},
+ {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"},
+ {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"},
+ {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"},
+ {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"},
+ {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"},
+ {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"},
+ {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"},
+ {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"},
+ {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"},
+ {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"},
+ {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"},
+ {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"},
+ {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"},
+ {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"},
+ {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"},
+ {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"},
+ {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"},
+ {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"},
+ {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"},
+ {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"},
+ {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"},
+ {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"},
+ {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"},
+ {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"},
+ {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"},
+ {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"},
+ {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"},
+ {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"},
+ {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"},
+ {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"},
+ {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"},
+ {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"},
+ {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"},
+ {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"},
+ {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"},
+ {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"},
+ {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"},
+ {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"},
+ {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"},
+ {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"},
+ {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"},
+ {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"},
+ {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"},
+ {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"},
+ {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = {
+ {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = {
+ {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = {
+ {AMDGPU_GFX_VML2_MEM, "VML2_MEM"},
+};
+
+static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = {
+ {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"},
+};
+
+static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = {
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list)
+ AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list)
+};
+
+static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = {
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
+ AMDGPU_GFX_RLC_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
+ AMDGPU_GFX_CP_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
+ AMDGPU_GFX_CP_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
+ AMDGPU_GFX_CP_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
+ AMDGPU_GFX_GDS_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
+ AMDGPU_GFX_GC_CANE_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
+ AMDGPU_GFX_SPI_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
+ AMDGPU_GFX_SP_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
+ AMDGPU_GFX_SP_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
+ AMDGPU_GFX_SQ_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI),
+ 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
+ AMDGPU_GFX_SQC_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI),
+ 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
+ AMDGPU_GFX_TCX_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI),
+ 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
+ AMDGPU_GFX_TCC_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
+ AMDGPU_GFX_TA_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG),
+ 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
+ AMDGPU_GFX_TCI_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
+ AMDGPU_GFX_TCP_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
+ AMDGPU_GFX_TD_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI),
+ 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
+ AMDGPU_GFX_GCEA_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
+ AMDGPU_GFX_LDS_MEM, 1},
+};
+
+static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = {
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
+ AMDGPU_GFX_RLC_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
+ AMDGPU_GFX_CP_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
+ AMDGPU_GFX_CP_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
+ AMDGPU_GFX_CP_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
+ AMDGPU_GFX_GDS_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
+ AMDGPU_GFX_GC_CANE_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI),
+ 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
+ AMDGPU_GFX_SPI_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
+ AMDGPU_GFX_SP_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
+ AMDGPU_GFX_SP_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
+ AMDGPU_GFX_SQ_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI),
+ 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
+ AMDGPU_GFX_SQC_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI),
+ 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
+ AMDGPU_GFX_TCX_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI),
+ 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
+ AMDGPU_GFX_TCC_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
+ AMDGPU_GFX_TA_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG),
+ 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
+ AMDGPU_GFX_TCI_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
+ AMDGPU_GFX_TCP_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
+ AMDGPU_GFX_TD_MEM, 8},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI),
+ 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"},
+ AMDGPU_GFX_TCA_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI),
+ 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
+ AMDGPU_GFX_GCEA_MEM, 1},
+ {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI),
+ 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
+ AMDGPU_GFX_LDS_MEM, 1},
+};
+
static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = {
SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16
};
--
2.40.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 07/10] drm/amdgpu: add RAS error count query for gfx_v9_4_3
2023-05-12 21:43 [PATCH 01/10] drm/amdgpu: add GFX RAS common function Alex Deucher
` (4 preceding siblings ...)
2023-05-12 21:43 ` [PATCH 06/10] drm/amdgpu: add RAS error count definitions for gfx_v9_4_3 Alex Deucher
@ 2023-05-12 21:43 ` Alex Deucher
2023-05-12 21:43 ` [PATCH 08/10] drm/amdgpu: add RAS error count reset " Alex Deucher
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Alex Deucher @ 2023-05-12 21:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tao Zhou, Hawking Zhang
From: Tao Zhou <tao.zhou1@amd.com>
Query GFX RAS ce/ue count.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 56 +++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 188b4d9a2cbb..bfd041ba51d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -3724,6 +3724,55 @@ static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = {
SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16
};
+static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,
+ void *ras_error_status, int xcc_id)
+{
+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+ unsigned long ce_count = 0, ue_count = 0;
+ uint32_t i, j, k;
+
+ mutex_lock(&adev->grbm_idx_mutex);
+
+ for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
+ for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
+ for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
+ /* no need to select if instance number is 1 */
+ if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
+ gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
+ gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
+
+ amdgpu_ras_inst_query_ras_error_count(adev,
+ &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
+ 1,
+ gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent,
+ gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size,
+ GET_INST(GC, xcc_id),
+ AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE,
+ &ce_count);
+
+ amdgpu_ras_inst_query_ras_error_count(adev,
+ &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
+ 1,
+ gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent,
+ gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size,
+ GET_INST(GC, xcc_id),
+ AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
+ &ue_count);
+ }
+ }
+ }
+
+ gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
+ xcc_id);
+ mutex_unlock(&adev->grbm_idx_mutex);
+
+ /* the caller should make sure initialize value of
+ * err_data->ue_count and err_data->ce_count
+ */
+ err_data->ce_count += ce_count;
+ err_data->ue_count += ue_count;
+}
+
static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev,
int xcc_id)
{
@@ -3826,6 +3875,13 @@ static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev,
gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id);
}
+static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev,
+ void *ras_error_status)
+{
+ amdgpu_gfx_ras_error_func(adev, ras_error_status,
+ gfx_v9_4_3_inst_query_ras_err_count);
+}
+
static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev)
{
amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status);
--
2.40.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 08/10] drm/amdgpu: add RAS error count reset for gfx_v9_4_3
2023-05-12 21:43 [PATCH 01/10] drm/amdgpu: add GFX RAS common function Alex Deucher
` (5 preceding siblings ...)
2023-05-12 21:43 ` [PATCH 07/10] drm/amdgpu: add RAS error count query " Alex Deucher
@ 2023-05-12 21:43 ` Alex Deucher
2023-05-12 21:43 ` [PATCH 09/10] drm/amdgpu: add sq timeout status functions " Alex Deucher
2023-05-12 21:43 ` [PATCH 10/10] drm/amdgpu: initialize RAS " Alex Deucher
8 siblings, 0 replies; 10+ messages in thread
From: Alex Deucher @ 2023-05-12 21:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tao Zhou, Hawking Zhang
From: Tao Zhou <tao.zhou1@amd.com>
Add GFX RAS error count reset function.
v2: remove xcp operation.
only select_se_sh when instance number is more than 1.
v3: add check for se_num before select_se_sh.
change instance from 0 to xcc_id for register access.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 38 +++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index bfd041ba51d6..ac5270d5eff4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -3773,6 +3773,39 @@ static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,
err_data->ue_count += ue_count;
}
+static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,
+ void *ras_error_status, int xcc_id)
+{
+ uint32_t i, j, k;
+
+ mutex_lock(&adev->grbm_idx_mutex);
+
+ for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
+ for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
+ for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
+ /* no need to select if instance number is 1 */
+ if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
+ gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
+ gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
+
+ amdgpu_ras_inst_reset_ras_error_count(adev,
+ &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
+ 1,
+ GET_INST(GC, xcc_id));
+
+ amdgpu_ras_inst_reset_ras_error_count(adev,
+ &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
+ 1,
+ GET_INST(GC, xcc_id));
+ }
+ }
+ }
+
+ gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
+ xcc_id);
+ mutex_unlock(&adev->grbm_idx_mutex);
+}
+
static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev,
int xcc_id)
{
@@ -3882,6 +3915,11 @@ static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev,
gfx_v9_4_3_inst_query_ras_err_count);
}
+static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev)
+{
+ amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count);
+}
+
static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev)
{
amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status);
--
2.40.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 09/10] drm/amdgpu: add sq timeout status functions for gfx_v9_4_3
2023-05-12 21:43 [PATCH 01/10] drm/amdgpu: add GFX RAS common function Alex Deucher
` (6 preceding siblings ...)
2023-05-12 21:43 ` [PATCH 08/10] drm/amdgpu: add RAS error count reset " Alex Deucher
@ 2023-05-12 21:43 ` Alex Deucher
2023-05-12 21:43 ` [PATCH 10/10] drm/amdgpu: initialize RAS " Alex Deucher
8 siblings, 0 replies; 10+ messages in thread
From: Alex Deucher @ 2023-05-12 21:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tao Zhou, Hawking Zhang
From: Tao Zhou <tao.zhou1@amd.com>
Query and reset sq timeout status.
v2: change instance from 0 to xcc_id for register access.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 98 +++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index ac5270d5eff4..5bd2f40a817e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -3865,11 +3865,87 @@ static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev,
}
}
+static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev,
+ uint32_t status, int xcc_id)
+{
+ struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
+ uint32_t i, simd, wave;
+ uint32_t wave_status;
+ uint32_t wave_pc_lo, wave_pc_hi;
+ uint32_t wave_exec_lo, wave_exec_hi;
+ uint32_t wave_inst_dw0, wave_inst_dw1;
+ uint32_t wave_ib_sts;
+
+ for (i = 0; i < 32; i++) {
+ if (!((i << 1) & status))
+ continue;
+
+ simd = i / cu_info->max_waves_per_simd;
+ wave = i % cu_info->max_waves_per_simd;
+
+ wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);
+ wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);
+ wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);
+ wave_exec_lo =
+ wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);
+ wave_exec_hi =
+ wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);
+ wave_inst_dw0 =
+ wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);
+ wave_inst_dw1 =
+ wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);
+ wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);
+
+ dev_info(
+ adev->dev,
+ "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n",
+ simd, wave, wave_status,
+ ((uint64_t)wave_pc_hi << 32 | wave_pc_lo),
+ ((uint64_t)wave_exec_hi << 32 | wave_exec_lo),
+ ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0),
+ wave_ib_sts);
+ }
+}
+
+static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev,
+ int xcc_id)
+{
+ uint32_t se_idx, sh_idx, cu_idx;
+ uint32_t status;
+
+ mutex_lock(&adev->grbm_idx_mutex);
+ for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) {
+ for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) {
+ for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) {
+ gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,
+ cu_idx, xcc_id);
+ status = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
+ regSQ_TIMEOUT_STATUS);
+ if (status != 0) {
+ dev_info(
+ adev->dev,
+ "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n",
+ se_idx, sh_idx, cu_idx);
+ gfx_v9_4_3_log_cu_timeout_status(
+ adev, status, xcc_id);
+ }
+ /* clear old status */
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id),
+ regSQ_TIMEOUT_STATUS, 0);
+ }
+ }
+ }
+ gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
+ xcc_id);
+ mutex_unlock(&adev->grbm_idx_mutex);
+}
+
static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev,
void *ras_error_status, int xcc_id)
{
gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id);
gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id);
+ gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id);
}
static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev,
@@ -3901,11 +3977,33 @@ static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev,
mutex_unlock(&adev->grbm_idx_mutex);
}
+static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev,
+ int xcc_id)
+{
+ uint32_t se_idx, sh_idx, cu_idx;
+
+ mutex_lock(&adev->grbm_idx_mutex);
+ for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) {
+ for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) {
+ for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) {
+ gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,
+ cu_idx, xcc_id);
+ WREG32_SOC15(GC, GET_INST(GC, xcc_id),
+ regSQ_TIMEOUT_STATUS, 0);
+ }
+ }
+ }
+ gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
+ xcc_id);
+ mutex_unlock(&adev->grbm_idx_mutex);
+}
+
static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev,
void *ras_error_status, int xcc_id)
{
gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id);
gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id);
+ gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id);
}
static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev,
--
2.40.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 10/10] drm/amdgpu: initialize RAS for gfx_v9_4_3
2023-05-12 21:43 [PATCH 01/10] drm/amdgpu: add GFX RAS common function Alex Deucher
` (7 preceding siblings ...)
2023-05-12 21:43 ` [PATCH 09/10] drm/amdgpu: add sq timeout status functions " Alex Deucher
@ 2023-05-12 21:43 ` Alex Deucher
8 siblings, 0 replies; 10+ messages in thread
From: Alex Deucher @ 2023-05-12 21:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tao Zhou, Hawking Zhang
From: Tao Zhou <tao.zhou1@amd.com>
Register GFX RAS functions and initialize GFX RAS.
v2: remove xcp operations.
v3: reuse the return value of gfx_ras_sw_init.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 5bd2f40a817e..e5cfb3adb3b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -47,6 +47,8 @@ MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
#define GFX9_MEC_HPD_SIZE 4096
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
+struct amdgpu_gfx_ras gfx_v9_4_3_ras;
+
static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev);
static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev);
@@ -659,6 +661,7 @@ static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
u32 gb_addr_config;
adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
+ adev->gfx.ras = &gfx_v9_4_3_ras;
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 4, 3):
@@ -845,7 +848,7 @@ static int gfx_v9_4_3_sw_init(void *handle)
if (r)
return r;
- return 0;
+ return amdgpu_gfx_ras_sw_init(adev);
}
static int gfx_v9_4_3_sw_fini(void *handle)
@@ -4342,3 +4345,16 @@ struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = {
.suspend = &gfx_v9_4_3_xcp_suspend,
.resume = &gfx_v9_4_3_xcp_resume
};
+
+struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = {
+ .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count,
+ .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count,
+ .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status,
+ .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status,
+};
+
+struct amdgpu_gfx_ras gfx_v9_4_3_ras = {
+ .ras_block = {
+ .hw_ops = &gfx_v9_4_3_ras_ops,
+ },
+};
--
2.40.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-05-12 21:44 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-12 21:43 [PATCH 01/10] drm/amdgpu: add GFX RAS common function Alex Deucher
2023-05-12 21:43 ` [PATCH 02/10] drm/amdgpu: add RAS status query for gfx_v9_4_3 Alex Deucher
2023-05-12 21:43 ` [PATCH 03/10] drm/amdgpu: add RAS status reset " Alex Deucher
2023-05-12 21:43 ` [PATCH 04/10] drm/amdgpu: Add gc v9_4_3 ras error status registers Alex Deucher
2023-05-12 21:43 ` [PATCH 05/10] drm/amdgpu: add RAS definitions for GFX Alex Deucher
2023-05-12 21:43 ` [PATCH 06/10] drm/amdgpu: add RAS error count definitions for gfx_v9_4_3 Alex Deucher
2023-05-12 21:43 ` [PATCH 07/10] drm/amdgpu: add RAS error count query " Alex Deucher
2023-05-12 21:43 ` [PATCH 08/10] drm/amdgpu: add RAS error count reset " Alex Deucher
2023-05-12 21:43 ` [PATCH 09/10] drm/amdgpu: add sq timeout status functions " Alex Deucher
2023-05-12 21:43 ` [PATCH 10/10] drm/amdgpu: initialize RAS " Alex Deucher
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