[PATCH 0/4] hw/mips/loongson3_virt: Wire up loongarch_ipi device

[PATCH 0/4] hw/mips/loongson3_virt: Wire up loongarch_ipi device

[Jiaxun Yang]

Hi all,

This series wires up loongarch_ipi device for loongson3-virt,
which is required for SMP support.

We also add a new test for loongson3-virt for acceptance harness.

Thanks
- Jiaxun

Jiaxun Yang (4):
  hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
  hw/intc/loongarch_ipi: Guard LoongArch only features with ifdef
  hw/mips/loongson3_virt: Wire up loongarch_ipi device
  tests/avocado: Add boot_linux_console test for loongson3-virt

 hw/intc/loongarch_ipi.c             | 26 ++++++++++++++--
 hw/mips/Kconfig                     |  1 +
 hw/mips/loongson3_bootp.c           |  2 --
 hw/mips/loongson3_bootp.h           |  3 ++
 hw/mips/loongson3_virt.c            | 20 +++++++++++--
 include/hw/intc/loongarch_ipi.h     |  4 ++-
 tests/avocado/boot_linux_console.py | 46 +++++++++++++++++++++++++++++
 7 files changed, 94 insertions(+), 8 deletions(-)

-- 
2.39.2 (Apple Git-143)

[PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Jiaxun Yang]

As per "Loongson 3A5000/3B5000 Processor Reference Manual",
Loongson 3A5000's IPI implementation have 4 mailboxes per
core.

However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
percpu device"), the number of IPI mailboxes was reduced to
one, which mismatches actual hardware.

It won't affect LoongArch based system as LoongArch boot code
only uses the first mailbox, however MIPS based Loongson boot
code uses all 4 mailboxes.

Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/intc/loongarch_ipi.c         | 6 +++---
 include/hw/intc/loongarch_ipi.h | 4 +++-
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index d6ab91721ea1..3e453816524e 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -238,14 +238,14 @@ static void loongarch_ipi_init(Object *obj)
 
 static const VMStateDescription vmstate_ipi_core = {
     .name = "ipi-single",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(status, IPICore),
         VMSTATE_UINT32(en, IPICore),
         VMSTATE_UINT32(set, IPICore),
         VMSTATE_UINT32(clear, IPICore),
-        VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
+        VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
         VMSTATE_END_OF_LIST()
     }
 };
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
index 664e050b926e..6c6194786e80 100644
--- a/include/hw/intc/loongarch_ipi.h
+++ b/include/hw/intc/loongarch_ipi.h
@@ -28,6 +28,8 @@
 #define MAIL_SEND_OFFSET      0
 #define ANY_SEND_OFFSET       (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
 
+#define IPI_MBX_NUM           4
+
 #define TYPE_LOONGARCH_IPI "loongarch_ipi"
 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
 
@@ -37,7 +39,7 @@ typedef struct IPICore {
     uint32_t set;
     uint32_t clear;
     /* 64bit buf divide into 2 32bit buf */
-    uint32_t buf[2];
+    uint32_t buf[IPI_MBX_NUM * 2];
     qemu_irq irq;
 } IPICore;
 
-- 
2.39.2 (Apple Git-143)

[PATCH 2/4] hw/intc/loongarch_ipi: Guard LoongArch only features with ifdef

[Jiaxun Yang]

IOCSR based send features are tied to LoongArch's CPU implmentation,
ifdef them for LoongArch only so we can build loongarch_ipi on MIPS.

Note that Loongson-3A4000 have IOCSR as well, so we may implement
those features for MIPS in future.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/intc/loongarch_ipi.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index 3e453816524e..895a2ee96e1e 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -50,6 +50,7 @@ static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
     return ret;
 }
 
+#ifdef TARGET_LOONGARCH64
 static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
 {
     int i, mask = 0, data = 0;
@@ -140,6 +141,25 @@ static void any_send(uint64_t val)
     env = &cpu->env;
     send_ipi_data(env, val, addr);
 }
+#else
+static void ipi_send(uint64_t val)
+{
+    qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n",
+                    __func__, val);
+}
+
+static void mail_send(uint64_t val)
+{
+    qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n",
+                    __func__, val);
+}
+
+static void any_send(uint64_t val)
+{
+    qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n",
+                    __func__, val);
+}
+#endif
 
 static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
                                  unsigned size)
-- 
2.39.2 (Apple Git-143)

[PATCH 3/4] hw/mips/loongson3_virt: Wire up loongarch_ipi device

[Jiaxun Yang]

Wire up loongarch_ipi device for loongson3_virt machine, so we
can have SMP support for TCG backend as well.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/mips/Kconfig           |  1 +
 hw/mips/loongson3_bootp.c |  2 --
 hw/mips/loongson3_bootp.h |  3 +++
 hw/mips/loongson3_virt.c  | 20 ++++++++++++++++++--
 4 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
index da3a37e215ec..7cb6c1def16c 100644
--- a/hw/mips/Kconfig
+++ b/hw/mips/Kconfig
@@ -40,6 +40,7 @@ config LOONGSON3V
     imply QXL if SPICE
     select SERIAL
     select GOLDFISH_RTC
+    select LOONGARCH_IPI
     select LOONGSON_LIOINTC
     select PCI_DEVICES
     select PCI_EXPRESS_GENERIC_BRIDGE
diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c
index f99af229327a..474d3556b2e5 100644
--- a/hw/mips/loongson3_bootp.c
+++ b/hw/mips/loongson3_bootp.c
@@ -25,8 +25,6 @@
 #include "hw/boards.h"
 #include "hw/mips/loongson3_bootp.h"
 
-#define LOONGSON3_CORE_PER_NODE 4
-
 static void init_cpu_info(void *g_cpuinfo, uint64_t cpu_freq)
 {
     struct efi_cpuinfo_loongson *c = g_cpuinfo;
diff --git a/hw/mips/loongson3_bootp.h b/hw/mips/loongson3_bootp.h
index d525ab745a69..55f98858a5f4 100644
--- a/hw/mips/loongson3_bootp.h
+++ b/hw/mips/loongson3_bootp.h
@@ -200,6 +200,8 @@ struct boot_params {
     struct efi_reset_system_t reset_system;
 };
 
+#define LOONGSON3_CORE_PER_NODE 4
+
 /* Overall MMIO & Memory layout */
 enum {
     VIRT_LOWMEM,
@@ -211,6 +213,7 @@ enum {
     VIRT_BIOS_ROM,
     VIRT_UART,
     VIRT_LIOINTC,
+    VIRT_IPI,
     VIRT_PCIE_MMIO,
     VIRT_HIGHMEM
 };
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index 25534288dd81..a57245012598 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -38,6 +38,7 @@
 #include "hw/mips/loongson3_bootp.h"
 #include "hw/misc/unimp.h"
 #include "hw/intc/i8259.h"
+#include "hw/intc/loongarch_ipi.h"
 #include "hw/loader.h"
 #include "hw/isa/superio.h"
 #include "hw/pci/msi.h"
@@ -76,6 +77,7 @@ const MemMapEntry virt_memmap[] = {
     [VIRT_PCIE_ECAM] =   { 0x1a000000,     0x2000000 },
     [VIRT_BIOS_ROM] =    { 0x1fc00000,      0x200000 },
     [VIRT_UART] =        { 0x1fe001e0,           0x8 },
+    [VIRT_IPI] =         { 0x3ff01000,         0x400 },
     [VIRT_LIOINTC] =     { 0x3ff01400,          0x64 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
     [VIRT_HIGHMEM] =     { 0x80000000,           0x0 }, /* Variable */
@@ -529,6 +531,8 @@ static void mips_loongson3_virt_init(MachineState *machine)
     clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ);
 
     for (i = 0; i < machine->smp.cpus; i++) {
+        int node = i / LOONGSON3_CORE_PER_NODE;
+        int core = i % LOONGSON3_CORE_PER_NODE;
         int ip;
 
         /* init CPUs */
@@ -539,12 +543,24 @@ static void mips_loongson3_virt_init(MachineState *machine)
         cpu_mips_clock_init(cpu);
         qemu_register_reset(main_cpu_reset, cpu);
 
-        if (i >= 4) {
+        /* IPI controller is in kernel for KVM */
+        if (!kvm_enabled()) {
+            DeviceState *ipi;
+
+            hwaddr base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base;
+            base += core * 0x100;
+            ipi = qdev_new(TYPE_LOONGARCH_IPI);
+            sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
+            qdev_connect_gpio_out(ipi, 0, cpu->env.irq[6]);
+            sysbus_mmio_map(SYS_BUS_DEVICE(ipi), 0, base);
+        }
+
+        if (node > 0) {
             continue; /* Only node-0 can be connected to LIOINTC */
         }
 
         for (ip = 0; ip < 4 ; ip++) {
-            int pin = i * 4 + ip;
+            int pin = core * LOONGSON3_CORE_PER_NODE + ip;
             sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
                                pin, cpu->env.irq[ip + 2]);
         }
-- 
2.39.2 (Apple Git-143)

[PATCH 4/4] tests/avocado: Add boot_linux_console test for loongson3-virt

[Jiaxun Yang]

Test loongson3-virt machine againt debian kernel and cpio rootfs.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 tests/avocado/boot_linux_console.py | 46 +++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index c0675809e641..fdb479448e47 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -191,6 +191,52 @@ def test_mips64el_fuloong2e(self):
         console_pattern = 'Kernel command line: %s' % kernel_command_line
         self.wait_for_console_pattern(console_pattern)
 
+    def test_mips64el_loongson3_virt_cpio(self):
+        """
+        :avocado: tags=arch:mips64el
+        :avocado: tags=endian:little
+        :avocado: tags=machine:loongson3-virt
+        :avocado: tags=cpu:Loongson-3A1000
+        :avocado: tags=device:liointc
+        :avocado: tags=device:loongarch_ipi
+        :avocado: tags=device:goldfish_rtc
+        """
+        deb_url = ('http://snapshot.debian.org/archive/debian/'
+                   '20230501T024743Z/pool/main/l/linux/'
+                   'linux-image-5.10.0-22-loongson-3_5.10.178-3_mips64el.deb')
+        deb_hash = 'af4fcc721b727df0bef31057325e4cc02725ae0c'
+        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+        kernel_path = self.extract_from_deb(deb_path,
+                                        '/boot/vmlinuz-5.10.0-22-loongson-3')
+        initrd_url = ('https://github.com/groeck/linux-build-test/'
+                      'raw/8584a59e/rootfs/'
+                      'mipsel64/rootfs.mipsel64r1.cpio.gz')
+        initrd_hash = '1dbb8a396e916847325284dbe2151167'
+        initrd_path_gz = self.fetch_asset(initrd_url, algorithm='md5',
+                                          asset_hash=initrd_hash)
+        initrd_path = self.workdir + "rootfs.cpio"
+        archive.gzip_uncompress(initrd_path_gz, initrd_path)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE
+                               + 'console=ttyS0,115200 '
+                               + 'rdinit=/sbin/init noreboot')
+        self.vm.add_args('-kernel', kernel_path,
+                         '-initrd', initrd_path,
+                         '-append', kernel_command_line,
+                         '-no-reboot')
+        self.vm.launch()
+        wait_for_console_pattern(self, 'Boot successful.')
+
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                                'ICT Loongson-3')
+        exec_command_and_wait_for_pattern(self, 'uname -a',
+                                                '5.10.0-22-loongson-3')
+        exec_command_and_wait_for_pattern(self, 'reboot',
+                                                'reboot: Restarting system')
+        # Wait for VM to shut down gracefully
+        self.vm.wait()
+
     def test_mips_malta_cpio(self):
         """
         :avocado: tags=arch:mips
-- 
2.39.2 (Apple Git-143)

Re: [PATCH 2/4] hw/intc/loongarch_ipi: Guard LoongArch only features with ifdef

[Song Gao]

Hi,

在 2023/5/21 下午6:23, Jiaxun Yang 写道:
> IOCSR based send features are tied to LoongArch's CPU implmentation,
> ifdef them for LoongArch only so we can build loongarch_ipi on MIPS.
>
> Note that Loongson-3A4000 have IOCSR as well, so we may implement
> those features for MIPS in future.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   hw/intc/loongarch_ipi.c | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
>
> diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
> index 3e453816524e..895a2ee96e1e 100644
> --- a/hw/intc/loongarch_ipi.c
> +++ b/hw/intc/loongarch_ipi.c
> @@ -50,6 +50,7 @@ static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
>       return ret;
>   }
>   
> +#ifdef TARGET_LOONGARCH64

How about adding one or three properties to LoongArchIPI?
and set these properties when starting the device.

This patch conflicts with patch [1], will it affect your patch?

[1]: 
https://patchew.org/QEMU/20230518014115.117869-1-gaosong@loongson.cn/20230518014115.117869-3-gaosong@loongson.cn/

Thanks.
Song Gao
>   static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
>   {
>       int i, mask = 0, data = 0;
> @@ -140,6 +141,25 @@ static void any_send(uint64_t val)
>       env = &cpu->env;
>       send_ipi_data(env, val, addr);
>   }
> +#else
> +static void ipi_send(uint64_t val)
> +{
> +    qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n",
> +                    __func__, val);
> +}
> +
> +static void mail_send(uint64_t val)
> +{
> +    qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n",
> +                    __func__, val);
> +}
> +
> +static void any_send(uint64_t val)
> +{
> +    qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n",
> +                    __func__, val);
> +}
> +#endif
>   
>   static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
>                                    unsigned size)

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Huacai Chen]

Hi, Jiaxun,

Rename loongarch_ipi to loongson_ipi? It will be shared by both MIPS
and LoongArch in your series.


Huacai

On Sun, May 21, 2023 at 6:24 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
> Loongson 3A5000's IPI implementation have 4 mailboxes per
> core.
>
> However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
> percpu device"), the number of IPI mailboxes was reduced to
> one, which mismatches actual hardware.
>
> It won't affect LoongArch based system as LoongArch boot code
> only uses the first mailbox, however MIPS based Loongson boot
> code uses all 4 mailboxes.
>
> Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  hw/intc/loongarch_ipi.c         | 6 +++---
>  include/hw/intc/loongarch_ipi.h | 4 +++-
>  2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
> index d6ab91721ea1..3e453816524e 100644
> --- a/hw/intc/loongarch_ipi.c
> +++ b/hw/intc/loongarch_ipi.c
> @@ -238,14 +238,14 @@ static void loongarch_ipi_init(Object *obj)
>
>  static const VMStateDescription vmstate_ipi_core = {
>      .name = "ipi-single",
> -    .version_id = 1,
> -    .minimum_version_id = 1,
> +    .version_id = 2,
> +    .minimum_version_id = 2,
>      .fields = (VMStateField[]) {
>          VMSTATE_UINT32(status, IPICore),
>          VMSTATE_UINT32(en, IPICore),
>          VMSTATE_UINT32(set, IPICore),
>          VMSTATE_UINT32(clear, IPICore),
> -        VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
> +        VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
>          VMSTATE_END_OF_LIST()
>      }
>  };
> diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
> index 664e050b926e..6c6194786e80 100644
> --- a/include/hw/intc/loongarch_ipi.h
> +++ b/include/hw/intc/loongarch_ipi.h
> @@ -28,6 +28,8 @@
>  #define MAIL_SEND_OFFSET      0
>  #define ANY_SEND_OFFSET       (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
>
> +#define IPI_MBX_NUM           4
> +
>  #define TYPE_LOONGARCH_IPI "loongarch_ipi"
>  OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
>
> @@ -37,7 +39,7 @@ typedef struct IPICore {
>      uint32_t set;
>      uint32_t clear;
>      /* 64bit buf divide into 2 32bit buf */
> -    uint32_t buf[2];
> +    uint32_t buf[IPI_MBX_NUM * 2];
>      qemu_irq irq;
>  } IPICore;
>
> --
> 2.39.2 (Apple Git-143)
>

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Jiaxun Yang]

> 2023年5月22日 04:52，Huacai Chen <chenhuacai@kernel.org> 写道：
> 
> Hi, Jiaxun,
> 
> Rename loongarch_ipi to loongson_ipi? It will be shared by both MIPS
> and LoongArch in your series.

Hi Huacai,

Thanks for the point, what’s the opinion from LoongArch mainatiners?

Or perhaps rename it as loong_ipi to reflect the nature that it’s shared
by MIPS based Loongson and LoongArch based Loongson?

Thanks
- Jiaxun

> 
> 
> Huacai
> 
> On Sun, May 21, 2023 at 6:24 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>> 
>> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
>> Loongson 3A5000's IPI implementation have 4 mailboxes per
>> core.
>> 
>> However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
>> percpu device"), the number of IPI mailboxes was reduced to
>> one, which mismatches actual hardware.
>> 
>> It won't affect LoongArch based system as LoongArch boot code
>> only uses the first mailbox, however MIPS based Loongson boot
>> code uses all 4 mailboxes.
>> 
>> Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>> hw/intc/loongarch_ipi.c         | 6 +++---
>> include/hw/intc/loongarch_ipi.h | 4 +++-
>> 2 files changed, 6 insertions(+), 4 deletions(-)
>> 
>> diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
>> index d6ab91721ea1..3e453816524e 100644
>> --- a/hw/intc/loongarch_ipi.c
>> +++ b/hw/intc/loongarch_ipi.c
>> @@ -238,14 +238,14 @@ static void loongarch_ipi_init(Object *obj)
>> 
>> static const VMStateDescription vmstate_ipi_core = {
>>     .name = "ipi-single",
>> -    .version_id = 1,
>> -    .minimum_version_id = 1,
>> +    .version_id = 2,
>> +    .minimum_version_id = 2,
>>     .fields = (VMStateField[]) {
>>         VMSTATE_UINT32(status, IPICore),
>>         VMSTATE_UINT32(en, IPICore),
>>         VMSTATE_UINT32(set, IPICore),
>>         VMSTATE_UINT32(clear, IPICore),
>> -        VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
>> +        VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
>>         VMSTATE_END_OF_LIST()
>>     }
>> };
>> diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
>> index 664e050b926e..6c6194786e80 100644
>> --- a/include/hw/intc/loongarch_ipi.h
>> +++ b/include/hw/intc/loongarch_ipi.h
>> @@ -28,6 +28,8 @@
>> #define MAIL_SEND_OFFSET      0
>> #define ANY_SEND_OFFSET       (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
>> 
>> +#define IPI_MBX_NUM           4
>> +
>> #define TYPE_LOONGARCH_IPI "loongarch_ipi"
>> OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
>> 
>> @@ -37,7 +39,7 @@ typedef struct IPICore {
>>     uint32_t set;
>>     uint32_t clear;
>>     /* 64bit buf divide into 2 32bit buf */
>> -    uint32_t buf[2];
>> +    uint32_t buf[IPI_MBX_NUM * 2];
>>     qemu_irq irq;
>> } IPICore;
>> 
>> --
>> 2.39.2 (Apple Git-143)
>> 

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Philippe Mathieu-Daudé]

On 22/5/23 13:47, Jiaxun Yang wrote:
> 
> 
>> 2023年5月22日 04:52，Huacai Chen <chenhuacai@kernel.org> 写道：
>>
>> Hi, Jiaxun,
>>
>> Rename loongarch_ipi to loongson_ipi? It will be shared by both MIPS
>> and LoongArch in your series.
> 
> Hi Huacai,
> 
> Thanks for the point, what’s the opinion from LoongArch mainatiners?
> 
> Or perhaps rename it as loong_ipi to reflect the nature that it’s shared
> by MIPS based Loongson and LoongArch based Loongson?

I'm not a LoongArch maintainer, but a model named "loong_ipi" makes
sense to me.

Please add it to the two Virt machine sections in MAINTAINERS.

> Thanks
> - Jiaxun
> 
>>
>>
>> Huacai

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Song Gao]

在 2023/5/22 下午9:44, Philippe Mathieu-Daudé 写道:
> On 22/5/23 13:47, Jiaxun Yang wrote:
>>
>>
>>> 2023年5月22日 04:52，Huacai Chen <chenhuacai@kernel.org> 写道：
>>>
>>> Hi, Jiaxun,
>>>
>>> Rename loongarch_ipi to loongson_ipi? It will be shared by both MIPS
>>> and LoongArch in your series.
>>
>> Hi Huacai,
>>
>> Thanks for the point, what’s the opinion from LoongArch mainatiners?
>>
>> Or perhaps rename it as loong_ipi to reflect the nature that it’s shared
>> by MIPS based Loongson and LoongArch based Loongson?
>
> I'm not a LoongArch maintainer, but a model named "loong_ipi" makes
> sense to me.
>
> Please add it to the two Virt machine sections in MAINTAINERS.
>
'loonggson_ipi' is better, qemu doesn't have naming with 'loong' as prefix.

And  patch2 should not use macros. Some attributes should be added to 
distinguish between MIPS and LongArch.

All references to loongarch_ipi should also be changed.

Thanks.
Song Gao

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Jiaxun Yang]

> 2023年5月23日 02:25，Song Gao <gaosong@loongson.cn> 写道：
> 
> 
> 
> 在 2023/5/22 下午9:44, Philippe Mathieu-Daudé 写道:
>> On 22/5/23 13:47, Jiaxun Yang wrote:
>>> 
>>> 
>>>> 2023年5月22日 04:52，Huacai Chen <chenhuacai@kernel.org> 写道：
>>>> 
>>>> Hi, Jiaxun,
>>>> 
>>>> Rename loongarch_ipi to loongson_ipi? It will be shared by both MIPS
>>>> and LoongArch in your series.
>>> 
>>> Hi Huacai,
>>> 
>>> Thanks for the point, what’s the opinion from LoongArch mainatiners?
>>> 
>>> Or perhaps rename it as loong_ipi to reflect the nature that it’s shared
>>> by MIPS based Loongson and LoongArch based Loongson?
>> 
>> I'm not a LoongArch maintainer, but a model named "loong_ipi" makes
>> sense to me.
>> 
>> Please add it to the two Virt machine sections in MAINTAINERS.

Hi Song,

>> 
> 'loonggson_ipi' is better, qemu doesn't have naming with 'loong' as prefix.

Thanks, I’ll take looongson_ipi then.

> 
> And  patch2 should not use macros. Some attributes should be added to distinguish between MIPS and LongArch.

By attribute do you mean property? If so I don’t see any necessity, the IP block
Is totally the same on MIPS and LoongArch. I’m guarding them out because
We have different way to get IOCSR address space on MIPS, which is due
to be implemented.

I can further abstract out a function to get IOCSR address space. But still,
I think the best way to differ those two architecture is using TARGET_* macros,
as it doesn’t make much sense to have unused code for another architecture
compiled.

> 
> All references to loongarch_ipi should also be changed.
Sure.

Thanks
- Jiaxun

> 
> Thanks.
> Song Gao

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Song Gao]

在 2023/5/23 上午11:22, Jiaxun Yang 写道:
>
>> 2023年5月23日 02:25，Song Gao <gaosong@loongson.cn> 写道：
>>
>>
>>
>> 在 2023/5/22 下午9:44, Philippe Mathieu-Daudé 写道:
>>> On 22/5/23 13:47, Jiaxun Yang wrote:
>>>>
>>>>> 2023年5月22日 04:52，Huacai Chen <chenhuacai@kernel.org> 写道：
>>>>>
>>>>> Hi, Jiaxun,
>>>>>
>>>>> Rename loongarch_ipi to loongson_ipi? It will be shared by both MIPS
>>>>> and LoongArch in your series.
>>>> Hi Huacai,
>>>>
>>>> Thanks for the point, what’s the opinion from LoongArch mainatiners?
>>>>
>>>> Or perhaps rename it as loong_ipi to reflect the nature that it’s shared
>>>> by MIPS based Loongson and LoongArch based Loongson?
>>> I'm not a LoongArch maintainer, but a model named "loong_ipi" makes
>>> sense to me.
>>>
>>> Please add it to the two Virt machine sections in MAINTAINERS.
> Hi Song,
>
>> 'loonggson_ipi' is better, qemu doesn't have naming with 'loong' as prefix.
> Thanks, I’ll take looongson_ipi then.
>
>> And  patch2 should not use macros. Some attributes should be added to distinguish between MIPS and LongArch.
> By attribute do you mean property?
Yes.
> If so I don’t see any necessity, the IP block
> Is totally the same on MIPS and LoongArch. I’m guarding them out because
> We have different way to get IOCSR address space on MIPS, which is due
> to be implemented.
>
> I can further abstract out a function to get IOCSR address space. But still,
> I think the best way to differ those two architecture is using TARGET_* macros,
> as it doesn’t make much sense to have unused code for another architecture
> compiled.
Most of the code in hw/intc or hw/ uses property to distinguish between 
different devices,  not TARGE_* macro.

I still think it is better to use property.

Thanks.
Song Gao
>> All references to loongarch_ipi should also be changed.
> Sure.
>
> Thanks
> - Jiaxun

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Jiaxun Yang]

> 2023年5月23日 11:01，Song Gao <gaosong@loongson.cn> 写道：
> 
> 
> 
> 在 2023/5/23 上午11:22, Jiaxun Yang 写道:
[...]
>> 
>>> 
>> Is totally the same on MIPS and LoongArch. I’m guarding them out because
>> We have different way to get IOCSR address space on MIPS, which is due
>> to be implemented.
>> 
>> I can further abstract out a function to get IOCSR address space. But still,
>> I think the best way to differ those two architecture is using TARGET_* macros,
>> as it doesn’t make much sense to have unused code for another architecture
>> compiled.
> Most of the code in hw/intc or hw/ uses property to distinguish between different devices,  not TARGE_* macro.

They are the *same* device, with different way to handle IOCSR address space.

Another problem is casting CPUState with LOONGARCH_CPU() is something invalid on
MIPS, vice-versa. We are potentially introducing a security issue here.

I know nobody have done something like this before, but not necessarily to be a bad idea.

I’ll introduce something like:

+#ifdef TARGET_LOONGARCH64
+static inline void *AddressSpace get_iocsr_as(int cpuid)
+{
+    CPUState *cs = qemu_get_cpu(cpuid);
+    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+
+    return &cpu->env.address_space_iocsr;
+}
+#endif
+
+#ifdef TARGET_MIPS64
+static inline void *AddressSpace get_iocsr_as(int cpuid)
+{
+    CPUState *cs = qemu_get_cpu(cpuid);
+    MIPSCPU *cpu = MIPS_CPU(cs);
+
+    return &cpu->env.iocsr.as;
+}
+#endif

Thanks
- Jiaxun

> 
> I still think it is better to use property.
> 
> Thanks.
> Song Gao
>>> All references to loongarch_ipi should also be changed.
>> Sure.
>> 
>> Thanks
>> - Jiaxun
> 

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Philippe Mathieu-Daudé]

On 23/5/23 13:18, Jiaxun Yang wrote:
> 
> 
>> 2023年5月23日 11:01，Song Gao <gaosong@loongson.cn> 写道：
>>
>>
>>
>> 在 2023/5/23 上午11:22, Jiaxun Yang 写道:
> [...]
>>>
>>>>
>>> Is totally the same on MIPS and LoongArch. I’m guarding them out because
>>> We have different way to get IOCSR address space on MIPS, which is due
>>> to be implemented.
>>>
>>> I can further abstract out a function to get IOCSR address space. But still,
>>> I think the best way to differ those two architecture is using TARGET_* macros,
>>> as it doesn’t make much sense to have unused code for another architecture
>>> compiled.
>> Most of the code in hw/intc or hw/ uses property to distinguish between different devices,  not TARGE_* macro.
> 
> They are the *same* device, with different way to handle IOCSR address space.
> 
> Another problem is casting CPUState with LOONGARCH_CPU() is something invalid on
> MIPS, vice-versa. We are potentially introducing a security issue here.
> 
> I know nobody have done something like this before, but not necessarily to be a bad idea.
> 
> I’ll introduce something like:
> 
> +#ifdef TARGET_LOONGARCH64
> +static inline void *AddressSpace get_iocsr_as(int cpuid)
> +{
> +    CPUState *cs = qemu_get_cpu(cpuid);
> +    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> +
> +    return &cpu->env.address_space_iocsr;
> +}
> +#endif
> +
> +#ifdef TARGET_MIPS64
> +static inline void *AddressSpace get_iocsr_as(int cpuid)
> +{
> +    CPUState *cs = qemu_get_cpu(cpuid);
> +    MIPSCPU *cpu = MIPS_CPU(cs);
> +
> +    return &cpu->env.iocsr.as;
> +}
> +#endif

Introduce a QOM interface that provides a get_iocsr_as() implementation.

See for example how TYPE_IDAU_INTERFACE works.

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Peter Maydell]

On Sun, 21 May 2023 at 11:24, Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
> Loongson 3A5000's IPI implementation have 4 mailboxes per
> core.
>
> However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
> percpu device"), the number of IPI mailboxes was reduced to
> one, which mismatches actual hardware.
>
> It won't affect LoongArch based system as LoongArch boot code
> only uses the first mailbox, however MIPS based Loongson boot
> code uses all 4 mailboxes.
>
> Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  hw/intc/loongarch_ipi.c         | 6 +++---
>  include/hw/intc/loongarch_ipi.h | 4 +++-
>  2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
> index d6ab91721ea1..3e453816524e 100644
> --- a/hw/intc/loongarch_ipi.c
> +++ b/hw/intc/loongarch_ipi.c
> @@ -238,14 +238,14 @@ static void loongarch_ipi_init(Object *obj)
>
>  static const VMStateDescription vmstate_ipi_core = {
>      .name = "ipi-single",
> -    .version_id = 1,
> -    .minimum_version_id = 1,
> +    .version_id = 2,
> +    .minimum_version_id = 2,
>      .fields = (VMStateField[]) {
>          VMSTATE_UINT32(status, IPICore),
>          VMSTATE_UINT32(en, IPICore),
>          VMSTATE_UINT32(set, IPICore),
>          VMSTATE_UINT32(clear, IPICore),
> -        VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
> +        VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
>          VMSTATE_END_OF_LIST()
>      }
>  };
> diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
> index 664e050b926e..6c6194786e80 100644
> --- a/include/hw/intc/loongarch_ipi.h
> +++ b/include/hw/intc/loongarch_ipi.h
> @@ -28,6 +28,8 @@
>  #define MAIL_SEND_OFFSET      0
>  #define ANY_SEND_OFFSET       (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
>
> +#define IPI_MBX_NUM           4
> +
>  #define TYPE_LOONGARCH_IPI "loongarch_ipi"
>  OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
>
> @@ -37,7 +39,7 @@ typedef struct IPICore {
>      uint32_t set;
>      uint32_t clear;
>      /* 64bit buf divide into 2 32bit buf */
> -    uint32_t buf[2];
> +    uint32_t buf[IPI_MBX_NUM * 2];
>      qemu_irq irq;
>  } IPICore;

In particular, this fixes Coverity issues CID 1512452 and 1512453,
where Coverity notices that the code in loongarch_ipi_writel() and
loongarch_ipi_readl() reads off the end of the too-short buf[].

thanks
-- PMM

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Jiaxun Yang]

> 2023年6月3日 01:28，Peter Maydell <peter.maydell@linaro.org> 写道：
> 
> On Sun, 21 May 2023 at 11:24, Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>> 
>> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
>> Loongson 3A5000's IPI implementation have 4 mailboxes per
>> core.
>> 
>> However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
>> percpu device"), the number of IPI mailboxes was reduced to
>> one, which mismatches actual hardware.
>> 
>> It won't affect LoongArch based system as LoongArch boot code
>> only uses the first mailbox, however MIPS based Loongson boot
>> code uses all 4 mailboxes.
>> 
>> Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>> hw/intc/loongarch_ipi.c         | 6 +++---
>> include/hw/intc/loongarch_ipi.h | 4 +++-
>> 2 files changed, 6 insertions(+), 4 deletions(-)
>> 
>> diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
>> index d6ab91721ea1..3e453816524e 100644
>> --- a/hw/intc/loongarch_ipi.c
>> +++ b/hw/intc/loongarch_ipi.c
>> @@ -238,14 +238,14 @@ static void loongarch_ipi_init(Object *obj)
>> 
>> static const VMStateDescription vmstate_ipi_core = {
>>     .name = "ipi-single",
>> -    .version_id = 1,
>> -    .minimum_version_id = 1,
>> +    .version_id = 2,
>> +    .minimum_version_id = 2,
>>     .fields = (VMStateField[]) {
>>         VMSTATE_UINT32(status, IPICore),
>>         VMSTATE_UINT32(en, IPICore),
>>         VMSTATE_UINT32(set, IPICore),
>>         VMSTATE_UINT32(clear, IPICore),
>> -        VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
>> +        VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
>>         VMSTATE_END_OF_LIST()
>>     }
>> };
>> diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
>> index 664e050b926e..6c6194786e80 100644
>> --- a/include/hw/intc/loongarch_ipi.h
>> +++ b/include/hw/intc/loongarch_ipi.h
>> @@ -28,6 +28,8 @@
>> #define MAIL_SEND_OFFSET      0
>> #define ANY_SEND_OFFSET       (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
>> 
>> +#define IPI_MBX_NUM           4
>> +
>> #define TYPE_LOONGARCH_IPI "loongarch_ipi"
>> OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
>> 
>> @@ -37,7 +39,7 @@ typedef struct IPICore {
>>     uint32_t set;
>>     uint32_t clear;
>>     /* 64bit buf divide into 2 32bit buf */
>> -    uint32_t buf[2];
>> +    uint32_t buf[IPI_MBX_NUM * 2];
>>     qemu_irq irq;
>> } IPICore;
> 
> In particular, this fixes Coverity issues CID 1512452 and 1512453,
> where Coverity notices that the code in loongarch_ipi_writel() and
> loongarch_ipi_readl() reads off the end of the too-short buf[].

LoongArch maintainers, do you mind to take this patch while I’m refactoring
rest of the series?

Thanks
Jiaxun

> 
> thanks
> -- PMM

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Song Gao]

在 2023/6/3 下午3:06, Jiaxun Yang 写道:
>
>> 2023年6月3日 01:28，Peter Maydell <peter.maydell@linaro.org> 写道：
>>
>> On Sun, 21 May 2023 at 11:24, Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>>> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
>>> Loongson 3A5000's IPI implementation have 4 mailboxes per
>>> core.
>>>
>>> However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
>>> percpu device"), the number of IPI mailboxes was reduced to
>>> one, which mismatches actual hardware.
>>>
>>> It won't affect LoongArch based system as LoongArch boot code
>>> only uses the first mailbox, however MIPS based Loongson boot
>>> code uses all 4 mailboxes.
>>>
>>> Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
>>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>> ---
>>> hw/intc/loongarch_ipi.c         | 6 +++---
>>> include/hw/intc/loongarch_ipi.h | 4 +++-
>>> 2 files changed, 6 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
>>> index d6ab91721ea1..3e453816524e 100644
>>> --- a/hw/intc/loongarch_ipi.c
>>> +++ b/hw/intc/loongarch_ipi.c
>>> @@ -238,14 +238,14 @@ static void loongarch_ipi_init(Object *obj)
>>>
>>> static const VMStateDescription vmstate_ipi_core = {
>>>      .name = "ipi-single",
>>> -    .version_id = 1,
>>> -    .minimum_version_id = 1,
>>> +    .version_id = 2,
>>> +    .minimum_version_id = 2,
>>>      .fields = (VMStateField[]) {
>>>          VMSTATE_UINT32(status, IPICore),
>>>          VMSTATE_UINT32(en, IPICore),
>>>          VMSTATE_UINT32(set, IPICore),
>>>          VMSTATE_UINT32(clear, IPICore),
>>> -        VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
>>> +        VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
>>>          VMSTATE_END_OF_LIST()
>>>      }
>>> };
>>> diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
>>> index 664e050b926e..6c6194786e80 100644
>>> --- a/include/hw/intc/loongarch_ipi.h
>>> +++ b/include/hw/intc/loongarch_ipi.h
>>> @@ -28,6 +28,8 @@
>>> #define MAIL_SEND_OFFSET      0
>>> #define ANY_SEND_OFFSET       (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
>>>
>>> +#define IPI_MBX_NUM           4
>>> +
>>> #define TYPE_LOONGARCH_IPI "loongarch_ipi"
>>> OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
>>>
>>> @@ -37,7 +39,7 @@ typedef struct IPICore {
>>>      uint32_t set;
>>>      uint32_t clear;
>>>      /* 64bit buf divide into 2 32bit buf */
>>> -    uint32_t buf[2];
>>> +    uint32_t buf[IPI_MBX_NUM * 2];
>>>      qemu_irq irq;
>>> } IPICore;
>> In particular, this fixes Coverity issues CID 1512452 and 1512453,
>> where Coverity notices that the code in loongarch_ipi_writel() and
>> loongarch_ipi_readl() reads off the end of the too-short buf[].
> LoongArch maintainers, do you mind to take this patch while I’m refactoring
> rest of the series?
I don't mind.

Thanks.
Song Gao

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[bibo, mao]

在 2023/5/23 21:07, Philippe Mathieu-Daudé 写道:
> On 23/5/23 13:18, Jiaxun Yang wrote:
>>
>>
>>> 2023年5月23日 11:01，Song Gao <gaosong@loongson.cn> 写道：
>>>
>>>
>>>
>>> 在 2023/5/23 上午11:22, Jiaxun Yang 写道:
>> [...]
>>>>
>>>>>
>>>> Is totally the same on MIPS and LoongArch. I’m guarding them out because
>>>> We have different way to get IOCSR address space on MIPS, which is due
>>>> to be implemented.
>>>>
>>>> I can further abstract out a function to get IOCSR address space. But still,
>>>> I think the best way to differ those two architecture is using TARGET_* macros,
>>>> as it doesn’t make much sense to have unused code for another architecture
>>>> compiled.
>>> Most of the code in hw/intc or hw/ uses property to distinguish between different devices,  not TARGE_* macro.
>>
>> They are the *same* device, with different way to handle IOCSR address space.
>>
>> Another problem is casting CPUState with LOONGARCH_CPU() is something invalid on
>> MIPS, vice-versa. We are potentially introducing a security issue here.
>>
>> I know nobody have done something like this before, but not necessarily to be a bad idea.
>>
>> I’ll introduce something like:
>>
>> +#ifdef TARGET_LOONGARCH64
>> +static inline void *AddressSpace get_iocsr_as(int cpuid)
>> +{
>> +    CPUState *cs = qemu_get_cpu(cpuid);
>> +    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
>> +
>> +    return &cpu->env.address_space_iocsr;
>> +}
>> +#endif
>> +
>> +#ifdef TARGET_MIPS64
>> +static inline void *AddressSpace get_iocsr_as(int cpuid)
>> +{
>> +    CPUState *cs = qemu_get_cpu(cpuid);
>> +    MIPSCPU *cpu = MIPS_CPU(cs);
>> +
>> +    return &cpu->env.iocsr.as;
>> +}
>> +#endif
> 
> Introduce a QOM interface that provides a get_iocsr_as() implementation.
> 
> See for example how TYPE_IDAU_INTERFACE works.
another simple method, rename loongarch_ipi.c with loong_ipi_common.c, adding extra two 
files loongarch_ipi.c and loongson_ipi.c inheriting from loong_ipi_common.c

Regards
Bibo, Mao

Re: [PATCH 1/4] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

[Song Gao]

在 2023/5/21 下午6:23, Jiaxun Yang 写道:
> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
> Loongson 3A5000's IPI implementation have 4 mailboxes per
> core.
>
> However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
> percpu device"), the number of IPI mailboxes was reduced to
> one, which mismatches actual hardware.
>
> It won't affect LoongArch based system as LoongArch boot code
> only uses the first mailbox, however MIPS based Loongson boot
> code uses all 4 mailboxes.
>
> Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   hw/intc/loongarch_ipi.c         | 6 +++---
>   include/hw/intc/loongarch_ipi.h | 4 +++-
>   2 files changed, 6 insertions(+), 4 deletions(-)
Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao
> diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
> index d6ab91721ea1..3e453816524e 100644
> --- a/hw/intc/loongarch_ipi.c
> +++ b/hw/intc/loongarch_ipi.c
> @@ -238,14 +238,14 @@ static void loongarch_ipi_init(Object *obj)
>   
>   static const VMStateDescription vmstate_ipi_core = {
>       .name = "ipi-single",
> -    .version_id = 1,
> -    .minimum_version_id = 1,
> +    .version_id = 2,
> +    .minimum_version_id = 2,
>       .fields = (VMStateField[]) {
>           VMSTATE_UINT32(status, IPICore),
>           VMSTATE_UINT32(en, IPICore),
>           VMSTATE_UINT32(set, IPICore),
>           VMSTATE_UINT32(clear, IPICore),
> -        VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
> +        VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
>           VMSTATE_END_OF_LIST()
>       }
>   };
> diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
> index 664e050b926e..6c6194786e80 100644
> --- a/include/hw/intc/loongarch_ipi.h
> +++ b/include/hw/intc/loongarch_ipi.h
> @@ -28,6 +28,8 @@
>   #define MAIL_SEND_OFFSET      0
>   #define ANY_SEND_OFFSET       (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
>   
> +#define IPI_MBX_NUM           4
> +
>   #define TYPE_LOONGARCH_IPI "loongarch_ipi"
>   OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
>   
> @@ -37,7 +39,7 @@ typedef struct IPICore {
>       uint32_t set;
>       uint32_t clear;
>       /* 64bit buf divide into 2 32bit buf */
> -    uint32_t buf[2];
> +    uint32_t buf[IPI_MBX_NUM * 2];
>       qemu_irq irq;
>   } IPICore;
>