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From: Shazad Hussain <quic_shazhuss@quicinc.com>
To: <agross@kernel.org>, <andersson@kernel.org>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>
Cc: <konrad.dybcio@linaro.org>,
	Shazad Hussain <quic_shazhuss@quicinc.com>,
	<linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH v1 4/5] arm64: dts: qcom: sa8775p: add uart5 and uart9 nodes
Date: Fri, 26 May 2023 19:01:20 +0530	[thread overview]
Message-ID: <20230526133122.16443-5-quic_shazhuss@quicinc.com> (raw)
In-Reply-To: <20230526133122.16443-1-quic_shazhuss@quicinc.com>

Add remaining uart5 and uart9 nodes for UART bus present on sa8775p
SoC.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 30 +++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 5c7b838d239a..b130136acffe 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -1083,6 +1083,21 @@
 				power-domains = <&rpmhpd SA8775P_CX>;
 				status = "disabled";
 			};
+
+			uart5: serial@994000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x994000 0x0 0x4000>;
+				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
 		};
 
 		qupv3_id_1: geniqup@ac0000 {
@@ -1223,6 +1238,21 @@
 				status = "disabled";
 			};
 
+			uart9: serial@a88000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
+
 			i2c10: i2c@a8c000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0xa8c000 0x0 0x4000>;
-- 
2.17.1


  parent reply	other threads:[~2023-05-26 13:32 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-26 13:31 [PATCH v1 0/5] dts: qcom: sa8775p: add missing qup id's, i2c, Shazad Hussain
2023-05-26 13:31 ` [PATCH v1 1/5] arm64: dts: qcom: sa8775p: add the QUPv3 #0 and #3 node Shazad Hussain
2023-05-26 13:31 ` [PATCH v1 2/5] arm64: dts: qcom: sa8775p: add missing i2c nodes Shazad Hussain
2023-05-26 13:31 ` [PATCH v1 3/5] arm64: dts: qcom: sa8775p: add missing spi nodes Shazad Hussain
2023-05-26 13:31 ` Shazad Hussain [this message]
2023-05-26 13:31 ` [PATCH v1 5/5] arm64: dts: qcom: sa8775p-ride: enable i2c11 Shazad Hussain
2023-05-27  4:00 ` [PATCH v1 0/5] dts: qcom: sa8775p: add missing qup id's, i2c, Bjorn Andersson

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