* [PATCH 1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL
@ 2023-05-26 19:08 Robert Marko
2023-05-26 19:08 ` [PATCH 2/2] clk: qcom: ipq6018: fix networking resets Robert Marko
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Robert Marko @ 2023-05-26 19:08 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd,
linux-arm-msm, linux-clk, linux-kernel
Cc: Robert Marko
Update the UBI32 alpha PLL config to the latest values from the downstream
QCA 5.4 kernel.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/clk/qcom/gcc-ipq6018.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index 350ead66914ca..abd97b939850f 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -4149,15 +4149,20 @@ static struct clk_branch gcc_dcc_clk = {
static const struct alpha_pll_config ubi32_pll_config = {
.l = 0x3e,
- .alpha = 0x57,
+ .alpha = 0x6667,
.config_ctl_val = 0x240d6aa8,
.config_ctl_hi_val = 0x3c2,
+ .config_ctl_val = 0x240d4828,
+ .config_ctl_hi_val = 0x6,
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.pre_div_val = 0x0,
.pre_div_mask = BIT(12),
.post_div_val = 0x0,
.post_div_mask = GENMASK(9, 8),
+ .alpha_en_mask = BIT(24),
+ .test_ctl_val = 0x1C0000C0,
+ .test_ctl_hi_val = 0x4000,
};
static const struct alpha_pll_config nss_crypto_pll_config = {
--
2.40.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] clk: qcom: ipq6018: fix networking resets
2023-05-26 19:08 [PATCH 1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL Robert Marko
@ 2023-05-26 19:08 ` Robert Marko
2023-05-26 20:52 ` Konrad Dybcio
2023-05-26 20:51 ` [PATCH 1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL Konrad Dybcio
2023-05-27 1:07 ` (subset) " Bjorn Andersson
2 siblings, 1 reply; 6+ messages in thread
From: Robert Marko @ 2023-05-26 19:08 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd,
linux-arm-msm, linux-clk, linux-kernel
Cc: Robert Marko
Networking resets in IPQ6018 all use bitmask as they require multiple
bits to be set and cleared instead of a single bit.
So, current networking resets have the same register and bit 0 set which
is clearly incorrect.
Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/clk/qcom/gcc-ipq6018.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index abd97b939850f..b8310f29a8ff4 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -4520,24 +4520,24 @@ static const struct qcom_reset_map gcc_ipq6018_resets[] = {
[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
- [GCC_PPE_FULL_RESET] = { 0x68014, 0 },
- [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 },
+ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
+ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
- [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 },
+ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
- [GCC_EDMA_HW_RESET] = { 0x68014, 0 },
- [GCC_NSSPORT1_RESET] = { 0x68014, 0 },
- [GCC_NSSPORT2_RESET] = { 0x68014, 0 },
- [GCC_NSSPORT3_RESET] = { 0x68014, 0 },
- [GCC_NSSPORT4_RESET] = { 0x68014, 0 },
- [GCC_NSSPORT5_RESET] = { 0x68014, 0 },
- [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 },
- [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 },
- [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 },
- [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 },
- [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 },
- [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 },
- [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 },
+ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
+ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
+ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
+ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
+ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
+ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
+ [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
+ [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
+ [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
+ [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
+ [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
+ [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
+ [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
[GCC_LPASS_BCR] = {0x1F000, 0},
[GCC_UBI32_TBU_BCR] = {0x65000, 0},
[GCC_LPASS_TBU_BCR] = {0x6C000, 0},
--
2.40.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL
2023-05-26 19:08 [PATCH 1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL Robert Marko
2023-05-26 19:08 ` [PATCH 2/2] clk: qcom: ipq6018: fix networking resets Robert Marko
@ 2023-05-26 20:51 ` Konrad Dybcio
2023-05-27 1:07 ` (subset) " Bjorn Andersson
2 siblings, 0 replies; 6+ messages in thread
From: Konrad Dybcio @ 2023-05-26 20:51 UTC (permalink / raw)
To: Robert Marko, andersson, agross, mturquette, sboyd,
linux-arm-msm, linux-clk, linux-kernel
On 26.05.2023 21:08, Robert Marko wrote:
> Update the UBI32 alpha PLL config to the latest values from the downstream
> QCA 5.4 kernel.
>
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
> drivers/clk/qcom/gcc-ipq6018.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> index 350ead66914ca..abd97b939850f 100644
> --- a/drivers/clk/qcom/gcc-ipq6018.c
> +++ b/drivers/clk/qcom/gcc-ipq6018.c
> @@ -4149,15 +4149,20 @@ static struct clk_branch gcc_dcc_clk = {
>
> static const struct alpha_pll_config ubi32_pll_config = {
> .l = 0x3e,
> - .alpha = 0x57,
> + .alpha = 0x6667,
> .config_ctl_val = 0x240d6aa8,
> .config_ctl_hi_val = 0x3c2,
> + .config_ctl_val = 0x240d4828,
> + .config_ctl_hi_val = 0x6,
> .main_output_mask = BIT(0),
> .aux_output_mask = BIT(1),
> .pre_div_val = 0x0,
> .pre_div_mask = BIT(12),
> .post_div_val = 0x0,
> .post_div_mask = GENMASK(9, 8),
> + .alpha_en_mask = BIT(24),
> + .test_ctl_val = 0x1C0000C0,
Please use lowercase hex.
Konrad
> + .test_ctl_hi_val = 0x4000,
> };
>
> static const struct alpha_pll_config nss_crypto_pll_config = {
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] clk: qcom: ipq6018: fix networking resets
2023-05-26 19:08 ` [PATCH 2/2] clk: qcom: ipq6018: fix networking resets Robert Marko
@ 2023-05-26 20:52 ` Konrad Dybcio
2023-05-26 20:53 ` Robert Marko
0 siblings, 1 reply; 6+ messages in thread
From: Konrad Dybcio @ 2023-05-26 20:52 UTC (permalink / raw)
To: Robert Marko, andersson, agross, mturquette, sboyd,
linux-arm-msm, linux-clk, linux-kernel
On 26.05.2023 21:08, Robert Marko wrote:
> Networking resets in IPQ6018 all use bitmask as they require multiple
> bits to be set and cleared instead of a single bit.
>
> So, current networking resets have the same register and bit 0 set which
> is clearly incorrect.
>
> Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
> drivers/clk/qcom/gcc-ipq6018.c | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> index abd97b939850f..b8310f29a8ff4 100644
> --- a/drivers/clk/qcom/gcc-ipq6018.c
> +++ b/drivers/clk/qcom/gcc-ipq6018.c
> @@ -4520,24 +4520,24 @@ static const struct qcom_reset_map gcc_ipq6018_resets[] = {
> [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
> [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
> [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
> - [GCC_PPE_FULL_RESET] = { 0x68014, 0 },
> - [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 },
> + [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
GENMASK / GENMASK|GENMASK / GENMASK|BIT?
Konrad
> + [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
> [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
> - [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 },
> + [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
> [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
> - [GCC_EDMA_HW_RESET] = { 0x68014, 0 },
> - [GCC_NSSPORT1_RESET] = { 0x68014, 0 },
> - [GCC_NSSPORT2_RESET] = { 0x68014, 0 },
> - [GCC_NSSPORT3_RESET] = { 0x68014, 0 },
> - [GCC_NSSPORT4_RESET] = { 0x68014, 0 },
> - [GCC_NSSPORT5_RESET] = { 0x68014, 0 },
> - [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 },
> - [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 },
> - [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 },
> - [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 },
> - [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 },
> - [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 },
> - [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 },
> + [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
> + [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
> + [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
> + [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
> + [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
> + [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
> + [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
> + [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
> + [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
> + [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
> + [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
> + [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
> + [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
> [GCC_LPASS_BCR] = {0x1F000, 0},
> [GCC_UBI32_TBU_BCR] = {0x65000, 0},
> [GCC_LPASS_TBU_BCR] = {0x6C000, 0},
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] clk: qcom: ipq6018: fix networking resets
2023-05-26 20:52 ` Konrad Dybcio
@ 2023-05-26 20:53 ` Robert Marko
0 siblings, 0 replies; 6+ messages in thread
From: Robert Marko @ 2023-05-26 20:53 UTC (permalink / raw)
To: Konrad Dybcio
Cc: andersson, agross, mturquette, sboyd, linux-arm-msm, linux-clk,
linux-kernel
On Fri, 26 May 2023 at 22:52, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 26.05.2023 21:08, Robert Marko wrote:
> > Networking resets in IPQ6018 all use bitmask as they require multiple
> > bits to be set and cleared instead of a single bit.
> >
> > So, current networking resets have the same register and bit 0 set which
> > is clearly incorrect.
> >
> > Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
> > Signed-off-by: Robert Marko <robimarko@gmail.com>
> > ---
> > drivers/clk/qcom/gcc-ipq6018.c | 32 ++++++++++++++++----------------
> > 1 file changed, 16 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> > index abd97b939850f..b8310f29a8ff4 100644
> > --- a/drivers/clk/qcom/gcc-ipq6018.c
> > +++ b/drivers/clk/qcom/gcc-ipq6018.c
> > @@ -4520,24 +4520,24 @@ static const struct qcom_reset_map gcc_ipq6018_resets[] = {
> > [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
> > [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
> > [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
> > - [GCC_PPE_FULL_RESET] = { 0x68014, 0 },
> > - [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 },
> > + [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
> GENMASK / GENMASK|GENMASK / GENMASK|BIT?
That would explain why I did not send it before, its been on the TODO
list to reverse
the QCA magic values like I did for IPQ8074.
Will do it for v2, thanks.
Regards,
Robert
>
> Konrad
> > + [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
> > [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
> > - [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 },
> > + [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
> > [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
> > - [GCC_EDMA_HW_RESET] = { 0x68014, 0 },
> > - [GCC_NSSPORT1_RESET] = { 0x68014, 0 },
> > - [GCC_NSSPORT2_RESET] = { 0x68014, 0 },
> > - [GCC_NSSPORT3_RESET] = { 0x68014, 0 },
> > - [GCC_NSSPORT4_RESET] = { 0x68014, 0 },
> > - [GCC_NSSPORT5_RESET] = { 0x68014, 0 },
> > - [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 },
> > - [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 },
> > - [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 },
> > - [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 },
> > - [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 },
> > - [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 },
> > - [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 },
> > + [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
> > + [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
> > + [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
> > + [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
> > + [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
> > + [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
> > + [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
> > + [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
> > + [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
> > + [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
> > + [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
> > + [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
> > + [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
> > [GCC_LPASS_BCR] = {0x1F000, 0},
> > [GCC_UBI32_TBU_BCR] = {0x65000, 0},
> > [GCC_LPASS_TBU_BCR] = {0x6C000, 0},
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: (subset) [PATCH 1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL
2023-05-26 19:08 [PATCH 1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL Robert Marko
2023-05-26 19:08 ` [PATCH 2/2] clk: qcom: ipq6018: fix networking resets Robert Marko
2023-05-26 20:51 ` [PATCH 1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL Konrad Dybcio
@ 2023-05-27 1:07 ` Bjorn Andersson
2 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2023-05-27 1:07 UTC (permalink / raw)
To: linux-clk, agross, Robert Marko, linux-kernel, konrad.dybcio,
linux-arm-msm, mturquette, sboyd
On Fri, 26 May 2023 21:08:54 +0200, Robert Marko wrote:
> Update the UBI32 alpha PLL config to the latest values from the downstream
> QCA 5.4 kernel.
>
>
Applied, thanks!
[1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL
commit: f4f0c8acee0e41c5fbae7a7ad06087668ddce0d6
[2/2] clk: qcom: ipq6018: fix networking resets
commit: 349b5bed539b491b7894a5186a895751fd8ba6c7
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-05-27 1:04 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-26 19:08 [PATCH 1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL Robert Marko
2023-05-26 19:08 ` [PATCH 2/2] clk: qcom: ipq6018: fix networking resets Robert Marko
2023-05-26 20:52 ` Konrad Dybcio
2023-05-26 20:53 ` Robert Marko
2023-05-26 20:51 ` [PATCH 1/2] clk: qcom: gcc-ipq6018: update UBI32 PLL Konrad Dybcio
2023-05-27 1:07 ` (subset) " Bjorn Andersson
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