* [Intel-xe] [PATCH v2 00/30] Separate GT and tile
@ 2023-05-19 23:17 Matt Roper
2023-05-19 23:17 ` [Intel-xe] [PATCH v2 01/30] drm/xe/mtl: Disable media GT Matt Roper
` (32 more replies)
0 siblings, 33 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:17 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Rodrigo Vivi, matthew.d.roper, Nirmoy Das
A 'tile' is not the same thing as a 'GT.' For historical reasons, i915
attempted to use a single 'struct intel_gt' to represent both concepts,
although this design hasn't worked out terribly well. For Xe we have
the opportunity to design the driver in a way that more accurately
reflects the real hardware behavior.
Different vendors use the term "tile" a bit differently, but in the
Intel world, a 'tile' is pretty close to what most people would think of
as being a complete GPU. When multiple GPUs are placed behind a single
PCI device, that's what we refer to as a "multi-tile device." In such
cases, pretty much all hardware is replicated per-tile, although certain
responsibilities like PCI communication, reporting of interrupts to the
OS, etc. are handled solely by the "root tile." A multi-tile platform
takes care of tying the tiles together in a way such that interrupt
notifications from remote tiles are forwarded to the root tile, the
per-tile vram is combined into a single address space, etc.
In contrast, a "GT" (which officially stands for "Graphics Technology")
is the subset of a GPU/tile that is responsible for implementing
graphics and/or media operations. The GT is where a lot of the driver
implementation happens since it's where the hardware engines, the
execution units, and the GuC all reside.
Historically most Intel devices were single-tile devices that contained
a single GT. PVC is currently the only released Intel platform built on
a multi-tile design (i.e., multiple GPUs behind a single PCI device);
each PVC tile only has a single GT. In contrast, platforms like MTL
that have separate chips for render and media IP are still only a single
logical GPU, but the graphics and media IP blocks are exposed each
exposed as a separate GT within that single GPU. This is important from
a software perspective because multi-GT platforms like MTL only
replicate a subset of the GPU hardware and behave differently than
multi-tile platforms like PVC where nearly everything is replicated.
This series separates tiles from GTs in a manner that more closely
matches the hardware behavior. We now consider a PCI device (xe_device)
to contain one or more tiles (struct xe_tile). Each tile will contain
one or two GTs (struct xe_gt). Although we don't have any platforms yet
that are multi-tile *and* contain more than one GT per tile, that may
change in the future. This driver redesign splits functionality as
follows:
Per-tile functionality (shared by all GTs within the tile):
- Complete 4MB MMIO space (containing SGunit/SoC registers, GT
registers, display registers, etc.)
- Global GTT
- VRAM (if discrete)
- Interrupt flows
- Migration context
- kernel batchbuffer pool
- Primary GT
- Media GT (if media version >= 13)
Per-GT functionality:
- GuC
- Hardware engines
- Programmable hardware units (subslices, EUs)
- GSI subset of registers (multiple copies of these registers reside
within the complete MMIO space provided by the tile, but at different
offsets --- 0 for render, 0x380000 for media)
- Multicast register steering
- TLBs to cache page table translations
- Reset capability
- Low-level power management (e.g., C6)
- Clock frequency
- MOCS and PAT programming
At the moment I've left USM / pagefault handling at the GT level,
although I'm not familiar enough with that specific feature to know
whether it's truly correct or not.
The first patch in this series temporarily drops MTL media GT support.
The driver doesn't load properly on MTL today, largely due to the
mishandling of GT vs tile; dropping support completely allows us to more
easily make the necessary driver redesign required. The media GT is
re-enabled (properly this time) near the end of the series and this
allows the driver to load successfully without error on MTL for the
first time. There are still issues when submitting workloads to MTL
after driver load (i.e., CAT errors), but those seem to be a separate
platform-specific issues unrelated to the GT/tile work in this series
that will need to be debugged and fixed separately.
This series leaves a few open questions and FIXME's:
- Unlike i915, the Xe driver has chosen to expose GTs to userspace
rather than keeping them a hidden implementation detail. With the
separation of xe_tile and xe_gt, we need to decide whether we also
want to expose tiles (in addition to GTs), whether we want to _only_
expose tiles (and keep the primary vs media GT separation a hidden
internal detail), or something else.
- How should GTs be numbered? Today it's straightforward --- PVC
assigns GT IDs 0 and 1 to the primary GT of each tile. MTL assigns
GT IDs 0 and 1 to the primary and media GTs of its sole tile. But if
we have a platform in the future that has multiple tiles _and_
multiple GTs per tile, how should we handle the numbering in that
case?
- Xe (mis)design used xe_gt as the target of all MMIO operations (i.e.,
xe_mmio_*()). This really doesn't make sense, especially since
there's a lot of MMIO accesses that are completely unrelated to GT
(i.e., sgunit registers, display registers, etc.). i915 used
'intel_uncore' as the MMIO target, although that wasn't really an
accurate reflection of the hardware either. What we really want is
something that combines the MMIO register space (stored in the tile)
with the GSI offset (stored in the GT). My current plan is to
introduce an "xe_mmio_view" (name may change) in a future series that
will serve as a target for register operations. There will be
sensible APIs to obtain an xe_mmio_view appropriate to the type of
register access being performed (and that will also be able to do
some range sanity checking in debug drivers to help catch misuse).
That's a somewhat large/invasive change, so I'm saving that for a
follow-up series after this one is completed.
v2:
- Fix kunit test build
- Add kerneldoc narrative about multi-tile design
- Undo accidental squashing of GGTT and VRAM patches
- Improved comments and commit message explanations in a few places.
- Move display changes to fixup! patches
- Rebase onto latest drm-xe-next codebase
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Michael J. Ruhl <michael.j.ruhl@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Matt Roper (30):
drm/xe/mtl: Disable media GT
drm/xe: Introduce xe_tile
drm/xe: Add backpointer from gt to tile
drm/xe: Add for_each_tile iterator
drm/xe: Move register MMIO into xe_tile
fixup! drm/xe/display: Implement display support
drm/xe: Move GGTT from GT to tile
fixup! drm/xe/display: Implement display support
drm/xe: Move VRAM from GT to tile
fixup! drm/xe/display: Implement display support
drm/xe: Memory allocations are tile-based, not GT-based
fixup! drm/xe/display: Implement display support
drm/xe: Move migration from GT to tile
drm/xe: Clarify 'gt' retrieval for primary tile
drm/xe: Drop vram_id
drm/xe: Drop extra_gts[] declarations and XE_GT_TYPE_REMOTE
drm/xe: Allocate GT dynamically
drm/xe: Add media GT to tile
drm/xe: Move display IRQ postinstall out of GT function
drm/xe: Interrupts are delivered per-tile, not per-GT
drm/xe/irq: Handle ASLE backlight interrupts at same time as display
drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt
mask
drm/xe/irq: Untangle postinstall functions
drm/xe: Replace xe_gt_irq_postinstall with xe_irq_enable_hwe
drm/xe: Invalidate TLB on all affected GTs during GGTT updates
drm/xe/tlb: Obtain forcewake when doing GGTT TLB invalidations
drm/xe: Allow GT looping and lookup on standalone media
drm/xe: Update query uapi to support standalone media
drm/xe: Reinstate media GT support
drm/xe: Add kerneldoc description of multi-tile devices
Documentation/gpu/xe/index.rst | 1 +
Documentation/gpu/xe/xe_tile.rst | 14 +
drivers/gpu/drm/i915/display/intel_dsb.c | 5 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 3 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 7 +-
drivers/gpu/drm/xe/Makefile | 1 +
.../drm/xe/compat-i915-headers/intel_uncore.h | 2 +-
drivers/gpu/drm/xe/display/ext/i915_irq.c | 2 +-
drivers/gpu/drm/xe/display/xe_fb_pin.c | 13 +-
drivers/gpu/drm/xe/display/xe_plane_initial.c | 8 +-
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 8 +
drivers/gpu/drm/xe/tests/xe_bo.c | 14 +-
drivers/gpu/drm/xe/tests/xe_migrate.c | 40 +-
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 6 +-
drivers/gpu/drm/xe/xe_bb.c | 5 +-
drivers/gpu/drm/xe/xe_bo.c | 104 ++---
drivers/gpu/drm/xe/xe_bo.h | 20 +-
drivers/gpu/drm/xe/xe_bo_evict.c | 22 +-
drivers/gpu/drm/xe/xe_bo_types.h | 4 +-
drivers/gpu/drm/xe/xe_device.c | 12 +-
drivers/gpu/drm/xe/xe_device.h | 51 ++-
drivers/gpu/drm/xe/xe_device_types.h | 107 ++++-
drivers/gpu/drm/xe/xe_engine.c | 2 +-
drivers/gpu/drm/xe/xe_ggtt.c | 45 +-
drivers/gpu/drm/xe/xe_ggtt.h | 6 +-
drivers/gpu/drm/xe/xe_ggtt_types.h | 2 +-
drivers/gpu/drm/xe/xe_gt.c | 143 +------
drivers/gpu/drm/xe/xe_gt.h | 8 +-
drivers/gpu/drm/xe/xe_gt_debugfs.c | 8 +-
drivers/gpu/drm/xe/xe_gt_pagefault.c | 16 +-
drivers/gpu/drm/xe/xe_gt_printk.h | 6 +-
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 4 +-
drivers/gpu/drm/xe/xe_gt_types.h | 87 ++--
drivers/gpu/drm/xe/xe_guc.c | 11 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 5 +-
drivers/gpu/drm/xe/xe_guc_ct.c | 5 +-
drivers/gpu/drm/xe/xe_guc_hwconfig.c | 5 +-
drivers/gpu/drm/xe/xe_guc_log.c | 6 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 5 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 6 +-
drivers/gpu/drm/xe/xe_irq.c | 389 +++++++++---------
drivers/gpu/drm/xe/xe_irq.h | 3 +-
drivers/gpu/drm/xe/xe_lrc.c | 13 +-
drivers/gpu/drm/xe/xe_lrc_types.h | 4 +-
drivers/gpu/drm/xe/xe_migrate.c | 76 ++--
drivers/gpu/drm/xe/xe_migrate.h | 9 +-
drivers/gpu/drm/xe/xe_mmio.c | 92 ++---
drivers/gpu/drm/xe/xe_mmio.h | 21 +-
drivers/gpu/drm/xe/xe_mocs.c | 14 +-
drivers/gpu/drm/xe/xe_pci.c | 86 ++--
drivers/gpu/drm/xe/xe_pt.c | 150 ++++---
drivers/gpu/drm/xe/xe_pt.h | 14 +-
drivers/gpu/drm/xe/xe_query.c | 32 +-
drivers/gpu/drm/xe/xe_res_cursor.h | 2 +-
drivers/gpu/drm/xe/xe_sa.c | 13 +-
drivers/gpu/drm/xe/xe_sa.h | 4 +-
drivers/gpu/drm/xe/xe_tile.c | 155 +++++++
drivers/gpu/drm/xe/xe_tile.h | 16 +
drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 4 +-
drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | 16 +-
drivers/gpu/drm/xe/xe_ttm_vram_mgr.h | 4 +-
drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h | 6 +-
drivers/gpu/drm/xe/xe_uc_fw.c | 5 +-
drivers/gpu/drm/xe/xe_vm.c | 156 ++++---
drivers/gpu/drm/xe/xe_vm.h | 2 +-
drivers/gpu/drm/xe/xe_vm_types.h | 22 +-
include/uapi/drm/xe_drm.h | 4 +-
67 files changed, 1182 insertions(+), 949 deletions(-)
create mode 100644 Documentation/gpu/xe/xe_tile.rst
create mode 100644 drivers/gpu/drm/xe/xe_tile.c
create mode 100644 drivers/gpu/drm/xe/xe_tile.h
--
2.40.0
^ permalink raw reply [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 01/30] drm/xe/mtl: Disable media GT
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
@ 2023-05-19 23:17 ` Matt Roper
2023-05-20 5:50 ` Lucas De Marchi
2023-05-19 23:17 ` [Intel-xe] [PATCH v2 02/30] drm/xe: Introduce xe_tile Matt Roper
` (31 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:17 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
Xe incorrectly conflates the concept of 'tile' and 'GT.' Since MTL's
media support is not yet functioning properly, let's just disable it
completely for now while we fix the fundamental driver design. Support
for media GTs on platforms like MTL will be re-added later.
v2:
- Drop some unrelated code cleanup that didn't belong in this patch.
(Lucas)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_mmio.c | 2 --
drivers/gpu/drm/xe/xe_pci.c | 13 +------------
2 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index c7fbb1cc1f64..4804616a3c44 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -301,8 +301,6 @@ static void xe_mmio_probe_tiles(struct xe_device *xe)
mtcfg = xe_mmio_read64(gt, XEHP_MTCFG_ADDR);
adj_tile_count = xe->info.tile_count =
REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
- if (xe->info.media_verx100 >= 1300)
- xe->info.tile_count *= 2;
drm_info(&xe->drm, "tile_count: %d, adj_tile_count %d\n",
xe->info.tile_count, adj_tile_count);
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index e789a50a1310..116569910e58 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -19,6 +19,7 @@
#include "xe_device.h"
#include "xe_display.h"
#include "xe_drv.h"
+#include "xe_gt.h"
#include "xe_macros.h"
#include "xe_module.h"
#include "xe_pci_types.h"
@@ -290,21 +291,11 @@ static const struct xe_device_desc pvc_desc = {
.extra_gts = pvc_gts,
};
-static const struct xe_gt_desc xelpmp_gts[] = {
- {
- .type = XE_GT_TYPE_MEDIA,
- .vram_id = 0,
- .mmio_adj_limit = 0x40000,
- .mmio_adj_offset = 0x380000,
- },
-};
-
static const struct xe_device_desc mtl_desc = {
/* .graphics and .media determined via GMD_ID */
.require_force_probe = true,
PLATFORM(XE_METEORLAKE),
.has_display = true,
- .extra_gts = xelpmp_gts,
};
#undef PLATFORM
@@ -552,8 +543,6 @@ static int xe_info_init(struct xe_device *xe,
* treats it as the number of GTs rather than just the number of tiles.
*/
xe->info.tile_count = 1 + graphics_desc->max_remote_tiles;
- if (MEDIA_VER(xe) >= 13)
- xe->info.tile_count++;
xe->info.subplatform = subplatform_desc ?
subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 02/30] drm/xe: Introduce xe_tile
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
2023-05-19 23:17 ` [Intel-xe] [PATCH v2 01/30] drm/xe/mtl: Disable media GT Matt Roper
@ 2023-05-19 23:17 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 03/30] drm/xe: Add backpointer from gt to tile Matt Roper
` (30 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:17 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
Create a new xe_tile structure to begin separating the concept of "tile"
from "GT." A tile is effectively a complete GPU, and a GT is just one
part of that. On platforms like MTL, there's only a single full GPU
(tile) which has its IP blocks provided by two GTs. In contrast, a
"multi-tile" platform like PVC is basically multiple complete GPUs
packed behind a single PCI device.
For now, just create xe_tile as a simple wrapper around xe_gt. The
items in xe_gt that are truly tied to the tile rather than the GT will
be moved in future patches. Support for multiple GTs per tile (i.e.,
the MTL standalone media case) will also be re-introduced in a future
patch.
v2:
- Fix kunit test build
- Move hunk from next patch to use local tile variable rather than
direct xe->tiles[id] accesses. (Lucas)
- Mention compute in kerneldoc. (Rodrigo)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/tests/xe_bo.c | 2 +-
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 6 ++--
drivers/gpu/drm/xe/xe_device.h | 11 +++++--
drivers/gpu/drm/xe/xe_device_types.h | 40 ++++++++++++++++++++++++--
drivers/gpu/drm/xe/xe_gt_types.h | 15 ++++++----
drivers/gpu/drm/xe/xe_mmio.c | 13 +++++----
drivers/gpu/drm/xe/xe_pci.c | 7 ++++-
drivers/gpu/drm/xe/xe_vm.c | 2 +-
drivers/gpu/drm/xe/xe_vm_types.h | 8 +++---
9 files changed, 78 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_bo.c b/drivers/gpu/drm/xe/tests/xe_bo.c
index 9bd381e5b7a6..6075f12a1962 100644
--- a/drivers/gpu/drm/xe/tests/xe_bo.c
+++ b/drivers/gpu/drm/xe/tests/xe_bo.c
@@ -174,7 +174,7 @@ static int evict_test_run_gt(struct xe_device *xe, struct xe_gt *gt, struct kuni
struct xe_bo *bo, *external;
unsigned int bo_flags = XE_BO_CREATE_USER_BIT |
XE_BO_CREATE_VRAM_IF_DGFX(gt);
- struct xe_vm *vm = xe_migrate_get_vm(xe->gt[0].migrate);
+ struct xe_vm *vm = xe_migrate_get_vm(xe_device_get_root_tile(xe)->primary_gt.migrate);
struct ww_acquire_ctx ww;
int err, i;
diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index 4b2aac5ccf28..7f8153df43ac 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -13,6 +13,7 @@
#include "regs/xe_gt_regs.h"
#include "regs/xe_reg_defs.h"
+#include "xe_device.h"
#include "xe_device_types.h"
#include "xe_pci_test.h"
#include "xe_reg_sr.h"
@@ -236,12 +237,13 @@ static void xe_rtp_process_tests(struct kunit *test)
{
const struct rtp_test_case *param = test->param_value;
struct xe_device *xe = test->priv;
- struct xe_reg_sr *reg_sr = &xe->gt[0].reg_sr;
+ struct xe_gt *gt = &xe_device_get_root_tile(xe)->primary_gt;
+ struct xe_reg_sr *reg_sr = >->reg_sr;
const struct xe_reg_sr_entry *sre, *sr_entry = NULL;
unsigned long idx, count = 0;
xe_reg_sr_init(reg_sr, "xe_rtp_tests", xe);
- xe_rtp_process(param->entries, reg_sr, &xe->gt[0], NULL);
+ xe_rtp_process(param->entries, reg_sr, gt, NULL);
xa_for_each(®_sr->xa, idx, sre) {
if (idx == param->expected_reg.addr)
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index cbae480a2092..f7acaf51a1fc 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -48,12 +48,17 @@ static inline struct xe_file *to_xe_file(const struct drm_file *file)
return file->driver_priv;
}
+static inline struct xe_tile *xe_device_get_root_tile(struct xe_device *xe)
+{
+ return &xe->tiles[0];
+}
+
static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
{
struct xe_gt *gt;
- XE_BUG_ON(gt_id > XE_MAX_GT);
- gt = xe->gt + gt_id;
+ XE_BUG_ON(gt_id > XE_MAX_TILES_PER_DEVICE);
+ gt = &xe->tiles[gt_id].primary_gt;
XE_BUG_ON(gt->info.id != gt_id);
XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
@@ -65,7 +70,7 @@ static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
*/
static inline struct xe_gt *to_gt(struct xe_device *xe)
{
- return xe->gt;
+ return &xe_device_get_root_tile(xe)->primary_gt;
}
static inline bool xe_device_guc_submission_enabled(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 77d1cc6514c4..11d973508d6c 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -35,7 +35,7 @@
#define XE_GT0 0
#define XE_GT1 1
-#define XE_MAX_GT (XE_GT1 + 1)
+#define XE_MAX_TILES_PER_DEVICE (XE_GT1 + 1)
#define XE_MAX_ASID (BIT(20))
@@ -49,6 +49,40 @@
(_xe)->info.step.graphics >= (min_step) && \
(_xe)->info.step.graphics < (max_step))
+#define tile_to_xe(tile__) \
+ _Generic(tile__, \
+ const struct xe_tile *: (const struct xe_device *)((tile__)->xe), \
+ struct xe_tile *: (tile__)->xe)
+
+/**
+ * struct xe_tile - hardware tile structure
+ *
+ * From a driver perspective, a "tile" is effectively a complete GPU, containing
+ * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM.
+ *
+ * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
+ * device and designate one "root" tile as being responsible for external PCI
+ * communication. PCI BAR0 exposes the GGTT and MMIO register space for each
+ * tile in a stacked layout, and PCI BAR2 exposes the local memory associated
+ * with each tile similarly. Device-wide interrupts can be enabled/disabled
+ * at the root tile, and the MSTR_TILE_INTR register will report which tiles
+ * have interrupts that need servicing.
+ */
+struct xe_tile {
+ /** @xe: Backpointer to tile's PCI device */
+ struct xe_device *xe;
+
+ /** @id: ID of the tile */
+ u8 id;
+
+ /**
+ * @primary_gt: Primary GT
+ */
+ struct xe_gt primary_gt;
+
+ /* TODO: Add media GT here */
+};
+
/**
* struct xe_device - Top level struct of XE device
*/
@@ -252,8 +286,8 @@ struct xe_device {
/** @ordered_wq: used to serialize compute mode resume */
struct workqueue_struct *ordered_wq;
- /** @gt: graphics tile */
- struct xe_gt gt[XE_MAX_GT];
+ /** @tiles: device tiles */
+ struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE];
/**
* @mem_access: keep track of memory access in the device, possibly
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 7c47d67aa8be..cac676353ac6 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -77,12 +77,17 @@ enum xe_steering_type {
};
/**
- * struct xe_gt - Top level struct of a graphics tile
+ * struct xe_gt - A "Graphics Technology" unit of the GPU
*
- * A graphics tile may be a physical split (duplicate pieces of silicon,
- * different GGTT + VRAM) or a virtual split (shared GGTT + VRAM). Either way
- * this structure encapsulates of everything a GT is (MMIO, VRAM, memory
- * management, microcontrols, and a hardware set of engines).
+ * A GT ("Graphics Technology") is the subset of a GPU primarily responsible
+ * for implementing the graphics, compute, and/or media IP. It encapsulates
+ * the hardware engines, programmable execution units, and GuC. Each GT has
+ * its own handling of power management (RC6+forcewake) and multicast register
+ * steering.
+ *
+ * A GPU/tile may have a single GT that supplies all graphics, compute, and
+ * media functionality, or the graphics/compute and media may be split into
+ * separate GTs within a tile.
*/
struct xe_gt {
/** @xe: backpointer to XE device */
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 4804616a3c44..254b4a63d901 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -399,6 +399,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct xe_device *xe = to_xe_device(dev);
+ struct xe_gt *gt = xe_device_get_gt(xe, 0);
struct drm_xe_mmio *args = data;
unsigned int bits_flag, bytes;
struct xe_reg reg;
@@ -440,7 +441,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
*/
reg = XE_REG(args->addr);
- xe_force_wake_get(gt_to_fw(&xe->gt[0]), XE_FORCEWAKE_ALL);
+ xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
if (args->flags & DRM_XE_MMIO_WRITE) {
switch (bits_flag) {
@@ -449,10 +450,10 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
ret = -EINVAL;
goto exit;
}
- xe_mmio_write32(to_gt(xe), reg, args->value);
+ xe_mmio_write32(gt, reg, args->value);
break;
case DRM_XE_MMIO_64BIT:
- xe_mmio_write64(to_gt(xe), reg, args->value);
+ xe_mmio_write64(gt, reg, args->value);
break;
default:
drm_dbg(&xe->drm, "Invalid MMIO bit size");
@@ -467,10 +468,10 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
if (args->flags & DRM_XE_MMIO_READ) {
switch (bits_flag) {
case DRM_XE_MMIO_32BIT:
- args->value = xe_mmio_read32(to_gt(xe), reg);
+ args->value = xe_mmio_read32(gt, reg);
break;
case DRM_XE_MMIO_64BIT:
- args->value = xe_mmio_read64(to_gt(xe), reg);
+ args->value = xe_mmio_read64(gt, reg);
break;
default:
drm_dbg(&xe->drm, "Invalid MMIO bit size");
@@ -482,7 +483,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
}
exit:
- xe_force_wake_put(gt_to_fw(&xe->gt[0]), XE_FORCEWAKE_ALL);
+ xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
return ret;
}
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 116569910e58..fc7984e4b40c 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -492,6 +492,7 @@ static int xe_info_init(struct xe_device *xe,
{
const struct xe_graphics_desc *graphics_desc = NULL;
const struct xe_media_desc *media_desc = NULL;
+ struct xe_tile *tile;
struct xe_gt *gt;
u8 id;
@@ -549,7 +550,11 @@ static int xe_info_init(struct xe_device *xe,
xe->info.step = xe_step_get(xe);
for (id = 0; id < xe->info.tile_count; ++id) {
- gt = xe->gt + id;
+ tile = &xe->tiles[id];
+ tile->xe = xe;
+ tile->id = id;
+
+ gt = &tile->primary_gt;
gt->info.id = id;
gt->xe = xe;
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index a0306526b269..b8fc30c3f370 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -3350,7 +3350,7 @@ int xe_vm_invalidate_vma(struct xe_vma *vma)
struct xe_device *xe = vma->vm->xe;
struct xe_gt *gt;
u32 gt_needs_invalidate = 0;
- int seqno[XE_MAX_GT];
+ int seqno[XE_MAX_TILES_PER_DEVICE];
u8 id;
int ret;
diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h
index fada7896867f..203ba9d946b8 100644
--- a/drivers/gpu/drm/xe/xe_vm_types.h
+++ b/drivers/gpu/drm/xe/xe_vm_types.h
@@ -159,7 +159,7 @@ struct xe_vm {
struct kref refcount;
/* engine used for (un)binding vma's */
- struct xe_engine *eng[XE_MAX_GT];
+ struct xe_engine *eng[XE_MAX_TILES_PER_DEVICE];
/** Protects @rebind_list and the page-table structures */
struct dma_resv resv;
@@ -167,9 +167,9 @@ struct xe_vm {
u64 size;
struct rb_root vmas;
- struct xe_pt *pt_root[XE_MAX_GT];
- struct xe_bo *scratch_bo[XE_MAX_GT];
- struct xe_pt *scratch_pt[XE_MAX_GT][XE_VM_MAX_LEVEL];
+ struct xe_pt *pt_root[XE_MAX_TILES_PER_DEVICE];
+ struct xe_bo *scratch_bo[XE_MAX_TILES_PER_DEVICE];
+ struct xe_pt *scratch_pt[XE_MAX_TILES_PER_DEVICE][XE_VM_MAX_LEVEL];
/** @flags: flags for this VM, statically setup a creation time */
#define XE_VM_FLAGS_64K BIT(0)
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 03/30] drm/xe: Add backpointer from gt to tile
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
2023-05-19 23:17 ` [Intel-xe] [PATCH v2 01/30] drm/xe/mtl: Disable media GT Matt Roper
2023-05-19 23:17 ` [Intel-xe] [PATCH v2 02/30] drm/xe: Introduce xe_tile Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 04/30] drm/xe: Add for_each_tile iterator Matt Roper
` (29 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
Rather than a backpointer to the xe_device, a GT should have a
backpointer to its tile (which can then be used to lookup the device if
necessary).
The gt_to_xe() helper macro (which moves from xe_gt.h to xe_gt_types.h)
can and should still be used to jump directly from an xe_gt to
xe_device.
v2:
- Fix kunit test build
- Move a couple changes to the previous patch. (Lucas)
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/tests/xe_bo.c | 2 +-
drivers/gpu/drm/xe/xe_bb.c | 2 +-
drivers/gpu/drm/xe/xe_gt.h | 5 -----
drivers/gpu/drm/xe/xe_gt_printk.h | 6 +++---
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 4 ++--
drivers/gpu/drm/xe/xe_gt_types.h | 14 ++++++++++++--
drivers/gpu/drm/xe/xe_mocs.c | 14 +++++++-------
drivers/gpu/drm/xe/xe_pci.c | 2 +-
drivers/gpu/drm/xe/xe_pt.c | 2 +-
9 files changed, 28 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_bo.c b/drivers/gpu/drm/xe/tests/xe_bo.c
index 6075f12a1962..8f3afdc6cca6 100644
--- a/drivers/gpu/drm/xe/tests/xe_bo.c
+++ b/drivers/gpu/drm/xe/tests/xe_bo.c
@@ -90,7 +90,7 @@ static int ccs_test_migrate(struct xe_gt *gt, struct xe_bo *bo,
}
/* Check last CCS value, or at least last value in page. */
- offset = xe_device_ccs_bytes(gt->xe, bo->size);
+ offset = xe_device_ccs_bytes(gt_to_xe(gt), bo->size);
offset = min_t(u32, offset, PAGE_SIZE) / sizeof(u64) - 1;
if (cpu_map[offset] != get_val) {
KUNIT_FAIL(test,
diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
index 3deb2d55f421..bf7c94b769d7 100644
--- a/drivers/gpu/drm/xe/xe_bb.c
+++ b/drivers/gpu/drm/xe/xe_bb.c
@@ -16,7 +16,7 @@
static int bb_prefetch(struct xe_gt *gt)
{
- struct xe_device *xe = gt->xe;
+ struct xe_device *xe = gt_to_xe(gt);
if (GRAPHICS_VERx100(xe) >= 1250 && !xe_gt_is_media_type(gt))
/*
diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
index 086369f7ee6d..f4e98f499b36 100644
--- a/drivers/gpu/drm/xe/xe_gt.h
+++ b/drivers/gpu/drm/xe/xe_gt.h
@@ -49,11 +49,6 @@ static inline bool xe_gt_is_media_type(struct xe_gt *gt)
return gt->info.type == XE_GT_TYPE_MEDIA;
}
-#define gt_to_xe(gt__) \
- _Generic(gt__, \
- const struct xe_gt *: (const struct xe_device *)((gt__)->xe), \
- struct xe_gt *: (gt__)->xe)
-
static inline bool xe_gt_is_usm_hwe(struct xe_gt *gt, struct xe_hw_engine *hwe)
{
struct xe_device *xe = gt_to_xe(gt);
diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h
index 0b801429cf1a..5991bcadd47e 100644
--- a/drivers/gpu/drm/xe/xe_gt_printk.h
+++ b/drivers/gpu/drm/xe/xe_gt_printk.h
@@ -11,7 +11,7 @@
#include "xe_device_types.h"
#define xe_gt_printk(_gt, _level, _fmt, ...) \
- drm_##_level(&(_gt)->xe->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+ drm_##_level(>_to_xe(_gt)->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
#define xe_gt_err(_gt, _fmt, ...) \
xe_gt_printk((_gt), err, _fmt, ##__VA_ARGS__)
@@ -32,10 +32,10 @@
xe_gt_printk((_gt), err_ratelimited, _fmt, ##__VA_ARGS__)
#define xe_gt_WARN(_gt, _condition, _fmt, ...) \
- drm_WARN(&(_gt)->xe->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+ drm_WARN(>_to_xe(_gt)->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
#define xe_gt_WARN_ONCE(_gt, _condition, _fmt, ...) \
- drm_WARN_ONCE(&(_gt)->xe->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+ drm_WARN_ONCE(>_to_xe(_gt)->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
#define xe_gt_WARN_ON(_gt, _condition) \
xe_gt_WARN((_gt), _condition, "%s(%s)", "gt_WARN_ON", __stringify(_condition))
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
index c815a42e2cdb..c9e8825c02aa 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
@@ -322,8 +322,8 @@ int xe_guc_tlb_invalidation_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
TLB_INVALIDATION_SEQNO_MAX;
if (!expected_seqno)
expected_seqno = 1;
- if (drm_WARN_ON(>->xe->drm, expected_seqno != msg[0])) {
- drm_err(>->xe->drm, "TLB expected_seqno(%d) != msg(%u)\n",
+ if (drm_WARN_ON(>_to_xe(gt)->drm, expected_seqno != msg[0])) {
+ drm_err(>_to_xe(gt)->drm, "TLB expected_seqno(%d) != msg(%u)\n",
expected_seqno, msg[0]);
}
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index cac676353ac6..2bc88696af77 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -76,6 +76,16 @@ enum xe_steering_type {
NUM_STEERING_TYPES
};
+#define gt_to_tile(gt__) \
+ _Generic(gt__, \
+ const struct xe_gt *: (const struct xe_tile *)((gt__)->tile), \
+ struct xe_gt *: (gt__)->tile)
+
+#define gt_to_xe(gt__) \
+ _Generic(gt__, \
+ const struct xe_gt *: (const struct xe_device *)(gt_to_tile(gt__)->xe), \
+ struct xe_gt *: gt_to_tile(gt__)->xe)
+
/**
* struct xe_gt - A "Graphics Technology" unit of the GPU
*
@@ -90,8 +100,8 @@ enum xe_steering_type {
* separate GTs within a tile.
*/
struct xe_gt {
- /** @xe: backpointer to XE device */
- struct xe_device *xe;
+ /** @tile: Backpointer to GT's tile */
+ struct xe_tile *tile;
/** @info: GT info */
struct {
diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index c7a9e733ef3b..86277ecb749b 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -472,7 +472,7 @@ static void __init_mocs_table(struct xe_gt *gt,
unsigned int i;
u32 mocs;
- mocs_dbg(>->xe->drm, "entries:%d\n", info->n_entries);
+ mocs_dbg(>_to_xe(gt)->drm, "entries:%d\n", info->n_entries);
drm_WARN_ONCE(&xe->drm, !info->unused_entries_index,
"Unused entries index should have been defined\n");
for (i = 0;
@@ -480,7 +480,7 @@ static void __init_mocs_table(struct xe_gt *gt,
i++) {
struct xe_reg reg = XE_REG(addr + i * 4);
- mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, reg.addr, mocs);
+ mocs_dbg(>_to_xe(gt)->drm, "%d 0x%x 0x%x\n", i, reg.addr, mocs);
xe_mmio_write32(gt, reg, mocs);
}
}
@@ -509,13 +509,13 @@ static void init_l3cc_table(struct xe_gt *gt,
unsigned int i;
u32 l3cc;
- mocs_dbg(>->xe->drm, "entries:%d\n", info->n_entries);
+ mocs_dbg(>_to_xe(gt)->drm, "entries:%d\n", info->n_entries);
for (i = 0;
i < (info->n_entries + 1) / 2 ?
(l3cc = l3cc_combine(get_entry_l3cc(info, 2 * i),
get_entry_l3cc(info, 2 * i + 1))), 1 : 0;
i++) {
- mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).addr,
+ mocs_dbg(>_to_xe(gt)->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).addr,
l3cc);
xe_mmio_write32(gt, LNCFCMOCS(i), l3cc);
}
@@ -525,7 +525,7 @@ void xe_mocs_init_early(struct xe_gt *gt)
{
struct xe_mocs_info table;
- get_mocs_settings(gt->xe, &table);
+ get_mocs_settings(gt_to_xe(gt), &table);
gt->mocs.uc_index = table.uc_index;
gt->mocs.wb_index = table.wb_index;
}
@@ -538,8 +538,8 @@ void xe_mocs_init(struct xe_gt *gt)
/*
* LLC and eDRAM control values are not applicable to dgfx
*/
- flags = get_mocs_settings(gt->xe, &table);
- mocs_dbg(>->xe->drm, "flag:0x%x\n", flags);
+ flags = get_mocs_settings(gt_to_xe(gt), &table);
+ mocs_dbg(>_to_xe(gt)->drm, "flag:0x%x\n", flags);
if (flags & HAS_GLOBAL_MOCS)
__init_mocs_table(gt, &table, GLOBAL_MOCS(0).addr);
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index fc7984e4b40c..1e1e401b25ae 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -556,7 +556,7 @@ static int xe_info_init(struct xe_device *xe,
gt = &tile->primary_gt;
gt->info.id = id;
- gt->xe = xe;
+ gt->tile = tile;
if (id == 0) {
gt->info.type = XE_GT_TYPE_MAIN;
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index f15282996c3b..61126cefe0b5 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -695,7 +695,7 @@ xe_pt_stage_bind_entry(struct xe_ptw *parent, pgoff_t offset,
* TODO: Suballocate the pt bo to avoid wasting a lot of
* memory.
*/
- if (GRAPHICS_VERx100(xe_walk->gt->xe) >= 1250 && level == 1 &&
+ if (GRAPHICS_VERx100(gt_to_xe(xe_walk->gt)) >= 1250 && level == 1 &&
covers && xe_pt_scan_64K(addr, next, xe_walk)) {
walk->shifts = xe_compact_pt_shifts;
flags |= XE_PDE_64K;
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 04/30] drm/xe: Add for_each_tile iterator
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (2 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 03/30] drm/xe: Add backpointer from gt to tile Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 05/30] drm/xe: Move register MMIO into xe_tile Matt Roper
` (28 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
As we start splitting tile handling out from GT handling, we'll need to
be able to iterate over tiles separately from GTs. This iterator will
be used in upcoming patches.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_device.h | 4 ++++
drivers/gpu/drm/xe/xe_pci.c | 3 +--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index f7acaf51a1fc..745dbb16d417 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -83,6 +83,10 @@ static inline void xe_device_guc_submission_disable(struct xe_device *xe)
xe->info.enable_guc = false;
}
+#define for_each_tile(tile__, xe__, id__) \
+ for ((id__) = 0; (id__) < (xe__)->info.tile_count; (id__++)) \
+ for_each_if ((tile__) = &(xe__)->tiles[(id__)])
+
#define for_each_gt(gt__, xe__, id__) \
for ((id__) = 0; (id__) < (xe__)->info.tile_count; (id__++)) \
for_each_if ((gt__) = xe_device_get_gt((xe__), (id__)))
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 1e1e401b25ae..0fb7ebb9653e 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -549,8 +549,7 @@ static int xe_info_init(struct xe_device *xe,
subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
xe->info.step = xe_step_get(xe);
- for (id = 0; id < xe->info.tile_count; ++id) {
- tile = &xe->tiles[id];
+ for_each_tile(tile, xe, id) {
tile->xe = xe;
tile->id = id;
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 05/30] drm/xe: Move register MMIO into xe_tile
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (3 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 04/30] drm/xe: Add for_each_tile iterator Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 06/30] fixup! drm/xe/display: Implement display support Matt Roper
` (27 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
Each tile has its own register region in the BAR, containing instances
of all registers for the platform. In contrast, the multiple GTs within
a tile share the same MMIO space; there's just a small subset of
registers (the GSI registers) which have multiple copies at different
offsets (0x0 for primary GT, 0x380000 for media GT). Move the register
MMIO region size/pointers to the tile structure, leaving just the GSI
offset information in the GT structure.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 16 ++++++++++++++++
drivers/gpu/drm/xe/xe_ggtt.c | 3 ++-
drivers/gpu/drm/xe/xe_gt_types.h | 9 +++------
drivers/gpu/drm/xe/xe_mmio.c | 26 ++++++++++++++------------
drivers/gpu/drm/xe/xe_mmio.h | 21 ++++++++++++++++-----
5 files changed, 51 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 11d973508d6c..ea7143c04db9 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -81,6 +81,22 @@ struct xe_tile {
struct xe_gt primary_gt;
/* TODO: Add media GT here */
+
+ /**
+ * @mmio: MMIO info for a tile.
+ *
+ * Each tile has its own 16MB space in BAR0, laid out as:
+ * * 0-4MB: registers
+ * * 4MB-8MB: reserved
+ * * 8MB-16MB: global GTT
+ */
+ struct {
+ /** @size: size of tile's MMIO space */
+ size_t size;
+
+ /** @regs: pointer to tile's MMIO space (starting with registers) */
+ void *regs;
+ } mmio;
};
/**
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 546240261e0a..200976da3dc1 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -93,6 +93,7 @@ static void ggtt_fini_noalloc(struct drm_device *drm, void *arg)
int xe_ggtt_init_noalloc(struct xe_gt *gt, struct xe_ggtt *ggtt)
{
struct xe_device *xe = gt_to_xe(gt);
+ struct xe_tile *tile = gt_to_tile(gt);
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
unsigned int gsm_size;
@@ -106,7 +107,7 @@ int xe_ggtt_init_noalloc(struct xe_gt *gt, struct xe_ggtt *ggtt)
return -ENOMEM;
}
- ggtt->gsm = gt->mmio.regs + SZ_8M;
+ ggtt->gsm = tile->mmio.regs + SZ_8M;
ggtt->size = (gsm_size / 8) * (u64) XE_PAGE_SIZE;
if (IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 2bc88696af77..6f4243443d04 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -124,14 +124,11 @@ struct xe_gt {
} info;
/**
- * @mmio: mmio info for GT, can be subset of the global device mmio
- * space
+ * @mmio: mmio info for GT. All GTs within a tile share the same
+ * register space, but have their own copy of GSI registers at a
+ * specific offset, as well as their own forcewake handling.
*/
struct {
- /** @size: size of MMIO space on GT */
- size_t size;
- /** @regs: pointer to MMIO space on GT */
- void *regs;
/** @fw: force wake for GT */
struct xe_force_wake fw;
/**
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 254b4a63d901..54fa1212fcd9 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -307,6 +307,7 @@ static void xe_mmio_probe_tiles(struct xe_device *xe)
if (xe->info.tile_count > 1) {
const int mmio_bar = 0;
+ struct xe_tile *tile;
size_t size;
void *regs;
@@ -320,11 +321,11 @@ static void xe_mmio_probe_tiles(struct xe_device *xe)
size = xe->mmio.size / adj_tile_count;
regs = xe->mmio.regs;
- for_each_gt(gt, xe, id) {
- if (id && !xe_gt_is_media_type(gt))
- regs += size;
- gt->mmio.size = size;
- gt->mmio.regs = regs;
+ for_each_tile(tile, xe, id) {
+ tile->mmio.size = size;
+ tile->mmio.regs = regs;
+
+ regs += size;
}
}
}
@@ -340,15 +341,16 @@ static void mmio_fini(struct drm_device *drm, void *arg)
int xe_mmio_init(struct xe_device *xe)
{
+ struct xe_tile *root_tile = xe_device_get_root_tile(xe);
struct xe_gt *gt = xe_device_get_gt(xe, 0);
const int mmio_bar = 0;
int err;
/*
- * Map the entire BAR, which includes registers (0-4MB), reserved space
- * (4MB-8MB), and GGTT (8MB-16MB). Other parts of the driver (GTs,
- * GGTTs) will derive the pointers they need from the mapping in the
- * device structure.
+ * Map the first 16MB of th BAR, which includes the registers (0-4MB),
+ * reserved space (4MB-8MB), and GGTT (8MB-16MB) for a single tile.
+ * This will get remapped later if we determine that we're running
+ * on a multi-tile system.
*/
xe->mmio.size = SZ_16M;
xe->mmio.regs = pci_iomap(to_pci_dev(xe->drm.dev), mmio_bar,
@@ -362,9 +364,9 @@ int xe_mmio_init(struct xe_device *xe)
if (err)
return err;
- /* 1 GT for now, 1 to 1 mapping, may change on multi-GT devices */
- gt->mmio.size = xe->mmio.size;
- gt->mmio.regs = xe->mmio.regs;
+ /* Setup first tile; other tiles (if present) will be setup later. */
+ root_tile->mmio.size = xe->mmio.size;
+ root_tile->mmio.regs = xe->mmio.regs;
/*
* The boot firmware initializes local memory and assesses its health.
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 1407f1189b0d..acf0b18f3111 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -10,6 +10,7 @@
#include <linux/io-64-nonatomic-lo-hi.h>
#include "regs/xe_reg_defs.h"
+#include "xe_device_types.h"
#include "xe_gt_types.h"
struct drm_device;
@@ -20,27 +21,33 @@ int xe_mmio_init(struct xe_device *xe);
static inline u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
{
+ struct xe_tile *tile = gt_to_tile(gt);
+
if (reg.addr < gt->mmio.adj_limit)
reg.addr += gt->mmio.adj_offset;
- return readb(gt->mmio.regs + reg.addr);
+ return readb(tile->mmio.regs + reg.addr);
}
static inline void xe_mmio_write32(struct xe_gt *gt,
struct xe_reg reg, u32 val)
{
+ struct xe_tile *tile = gt_to_tile(gt);
+
if (reg.addr < gt->mmio.adj_limit)
reg.addr += gt->mmio.adj_offset;
- writel(val, gt->mmio.regs + reg.addr);
+ writel(val, tile->mmio.regs + reg.addr);
}
static inline u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
{
+ struct xe_tile *tile = gt_to_tile(gt);
+
if (reg.addr < gt->mmio.adj_limit)
reg.addr += gt->mmio.adj_offset;
- return readl(gt->mmio.regs + reg.addr);
+ return readl(tile->mmio.regs + reg.addr);
}
static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,
@@ -58,18 +65,22 @@ static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,
static inline void xe_mmio_write64(struct xe_gt *gt,
struct xe_reg reg, u64 val)
{
+ struct xe_tile *tile = gt_to_tile(gt);
+
if (reg.addr < gt->mmio.adj_limit)
reg.addr += gt->mmio.adj_offset;
- writeq(val, gt->mmio.regs + reg.addr);
+ writeq(val, tile->mmio.regs + reg.addr);
}
static inline u64 xe_mmio_read64(struct xe_gt *gt, struct xe_reg reg)
{
+ struct xe_tile *tile = gt_to_tile(gt);
+
if (reg.addr < gt->mmio.adj_limit)
reg.addr += gt->mmio.adj_offset;
- return readq(gt->mmio.regs + reg.addr);
+ return readq(tile->mmio.regs + reg.addr);
}
static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 06/30] fixup! drm/xe/display: Implement display support
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (4 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 05/30] drm/xe: Move register MMIO into xe_tile Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-20 5:52 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 07/30] drm/xe: Move GGTT from GT to tile Matt Roper
` (26 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
---
drivers/gpu/drm/xe/display/ext/i915_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/display/ext/i915_irq.c b/drivers/gpu/drm/xe/display/ext/i915_irq.c
index a0f22bd52549..6235ff9dec36 100644
--- a/drivers/gpu/drm/xe/display/ext/i915_irq.c
+++ b/drivers/gpu/drm/xe/display/ext/i915_irq.c
@@ -670,7 +670,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
void gen11_display_irq_handler(struct drm_i915_private *i915)
{
- void __iomem * const regs = to_gt(i915)->mmio.regs;
+ void __iomem * const regs = xe_device_get_root_tile(i915)->mmio.regs;
const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
/*
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 07/30] drm/xe: Move GGTT from GT to tile
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (5 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 06/30] fixup! drm/xe/display: Implement display support Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-25 23:29 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 08/30] fixup! drm/xe/display: Implement display support Matt Roper
` (25 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
The GGTT exists at the tile level. When a tile contains multiple GTs,
they share the same GGTT.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_bo.c | 6 ++--
drivers/gpu/drm/xe/xe_bo_evict.c | 8 +++--
drivers/gpu/drm/xe/xe_device_types.h | 8 +++++
drivers/gpu/drm/xe/xe_ggtt.c | 30 ++++++++--------
drivers/gpu/drm/xe/xe_ggtt.h | 6 ++--
drivers/gpu/drm/xe/xe_ggtt_types.h | 2 +-
drivers/gpu/drm/xe/xe_gt.c | 10 +-----
drivers/gpu/drm/xe/xe_gt_debugfs.c | 2 +-
drivers/gpu/drm/xe/xe_gt_types.h | 3 --
drivers/gpu/drm/xe/xe_tile.c | 52 ++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_tile.h | 14 ++++++++
11 files changed, 104 insertions(+), 37 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_tile.c
create mode 100644 drivers/gpu/drm/xe/xe_tile.h
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index c82e995df779..ecc82fefdf4c 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -958,7 +958,7 @@ static void xe_ttm_bo_destroy(struct ttm_buffer_object *ttm_bo)
WARN_ON(!list_empty(&bo->vmas));
if (bo->ggtt_node.size)
- xe_ggtt_remove_bo(bo->gt->mem.ggtt, bo);
+ xe_ggtt_remove_bo(gt_to_tile(bo->gt)->mem.ggtt, bo);
if (bo->vm && xe_bo_is_user(bo))
xe_vm_put(bo->vm);
@@ -1235,10 +1235,10 @@ xe_bo_create_locked_range(struct xe_device *xe,
XE_BUG_ON(!gt);
if (flags & XE_BO_FIXED_PLACEMENT_BIT) {
- err = xe_ggtt_insert_bo_at(gt->mem.ggtt, bo,
+ err = xe_ggtt_insert_bo_at(gt_to_tile(gt)->mem.ggtt, bo,
start + bo->size, U64_MAX);
} else {
- err = xe_ggtt_insert_bo(gt->mem.ggtt, bo);
+ err = xe_ggtt_insert_bo(gt_to_tile(gt)->mem.ggtt, bo);
}
if (err)
goto err_unlock_put_bo;
diff --git a/drivers/gpu/drm/xe/xe_bo_evict.c b/drivers/gpu/drm/xe/xe_bo_evict.c
index 6642c5f52009..a72963c54bf3 100644
--- a/drivers/gpu/drm/xe/xe_bo_evict.c
+++ b/drivers/gpu/drm/xe/xe_bo_evict.c
@@ -149,9 +149,11 @@ int xe_bo_restore_kernel(struct xe_device *xe)
}
if (bo->flags & XE_BO_CREATE_GGTT_BIT) {
- mutex_lock(&bo->gt->mem.ggtt->lock);
- xe_ggtt_map_bo(bo->gt->mem.ggtt, bo);
- mutex_unlock(&bo->gt->mem.ggtt->lock);
+ struct xe_tile *tile = gt_to_tile(bo->gt);
+
+ mutex_lock(&tile->mem.ggtt->lock);
+ xe_ggtt_map_bo(tile->mem.ggtt, bo);
+ mutex_unlock(&tile->mem.ggtt->lock);
}
/*
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index ea7143c04db9..cb4d0c2ea184 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -54,6 +54,8 @@
const struct xe_tile *: (const struct xe_device *)((tile__)->xe), \
struct xe_tile *: (tile__)->xe)
+struct xe_ggtt;
+
/**
* struct xe_tile - hardware tile structure
*
@@ -97,6 +99,12 @@ struct xe_tile {
/** @regs: pointer to tile's MMIO space (starting with registers) */
void *regs;
} mmio;
+
+ /** @mem: memory management info for tile */
+ struct {
+ /** @ggtt: Global graphics translation table */
+ struct xe_ggtt *ggtt;
+ } mem;
};
/**
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 200976da3dc1..52d293d61cc0 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -90,24 +90,19 @@ static void ggtt_fini_noalloc(struct drm_device *drm, void *arg)
xe_bo_unpin_map_no_vm(ggtt->scratch);
}
-int xe_ggtt_init_noalloc(struct xe_gt *gt, struct xe_ggtt *ggtt)
+int xe_ggtt_init_noalloc(struct xe_ggtt *ggtt)
{
- struct xe_device *xe = gt_to_xe(gt);
- struct xe_tile *tile = gt_to_tile(gt);
+ struct xe_device *xe = tile_to_xe(ggtt->tile);
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
unsigned int gsm_size;
- XE_BUG_ON(xe_gt_is_media_type(gt));
-
- ggtt->gt = gt;
-
gsm_size = probe_gsm_size(pdev);
if (gsm_size == 0) {
drm_err(&xe->drm, "Hardware reported no preallocated GSM\n");
return -ENOMEM;
}
- ggtt->gsm = tile->mmio.regs + SZ_8M;
+ ggtt->gsm = ggtt->tile->mmio.regs + SZ_8M;
ggtt->size = (gsm_size / 8) * (u64) XE_PAGE_SIZE;
if (IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
@@ -147,13 +142,14 @@ static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
xe_ggtt_clear(ggtt, start, end - start);
- xe_ggtt_invalidate(ggtt->gt);
+ xe_ggtt_invalidate(ggtt);
mutex_unlock(&ggtt->lock);
}
-int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
+int xe_ggtt_init(struct xe_ggtt *ggtt)
{
- struct xe_device *xe = gt_to_xe(gt);
+ struct xe_device *xe = tile_to_xe(ggtt->tile);
+ struct xe_gt *gt = &ggtt->tile->primary_gt;
unsigned int flags;
int err;
@@ -193,8 +189,14 @@ int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
#define PVC_GUC_TLB_INV_DESC1 XE_REG(0xcf80)
#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
-void xe_ggtt_invalidate(struct xe_gt *gt)
+void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
{
+ /*
+ * TODO: Loop over each GT in tile once media GT support is
+ * re-added
+ */
+ struct xe_gt *gt = &ggtt->tile->primary_gt;
+
/* TODO: vfunc for GuC vs. non-GuC */
if (gt->uc.guc.submission_state.enabled) {
@@ -267,7 +269,7 @@ void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)
xe_ggtt_set_pte(ggtt, start + offset, pte);
}
- xe_ggtt_invalidate(ggtt->gt);
+ xe_ggtt_invalidate(ggtt);
}
static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,
@@ -318,7 +320,7 @@ void xe_ggtt_remove_node(struct xe_ggtt *ggtt, struct drm_mm_node *node)
drm_mm_remove_node(node);
node->size = 0;
- xe_ggtt_invalidate(ggtt->gt);
+ xe_ggtt_invalidate(ggtt);
mutex_unlock(&ggtt->lock);
}
diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
index 333947100504..205a6d058bbd 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.h
+++ b/drivers/gpu/drm/xe/xe_ggtt.h
@@ -12,9 +12,9 @@ struct drm_printer;
u64 xe_ggtt_pte_encode(struct xe_bo *bo, u64 bo_offset);
void xe_ggtt_set_pte(struct xe_ggtt *ggtt, u64 addr, u64 pte);
-void xe_ggtt_invalidate(struct xe_gt *gt);
-int xe_ggtt_init_noalloc(struct xe_gt *gt, struct xe_ggtt *ggtt);
-int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt);
+void xe_ggtt_invalidate(struct xe_ggtt *ggtt);
+int xe_ggtt_init_noalloc(struct xe_ggtt *ggtt);
+int xe_ggtt_init(struct xe_ggtt *ggtt);
void xe_ggtt_printk(struct xe_ggtt *ggtt, const char *prefix);
int xe_ggtt_insert_special_node(struct xe_ggtt *ggtt, struct drm_mm_node *node,
diff --git a/drivers/gpu/drm/xe/xe_ggtt_types.h b/drivers/gpu/drm/xe/xe_ggtt_types.h
index ea70aaef4b31..d34b3e733945 100644
--- a/drivers/gpu/drm/xe/xe_ggtt_types.h
+++ b/drivers/gpu/drm/xe/xe_ggtt_types.h
@@ -12,7 +12,7 @@ struct xe_bo;
struct xe_gt;
struct xe_ggtt {
- struct xe_gt *gt;
+ struct xe_tile *tile;
u64 size;
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 80d42c7c7cfa..1c58a9aff2cb 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -67,11 +67,6 @@ int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt)
XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
if (!xe_gt_is_media_type(gt)) {
- gt->mem.ggtt = drmm_kzalloc(drm, sizeof(*gt->mem.ggtt),
- GFP_KERNEL);
- if (!gt->mem.ggtt)
- return -ENOMEM;
-
gt->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*gt->mem.vram_mgr),
GFP_KERNEL);
if (!gt->mem.vram_mgr)
@@ -80,7 +75,6 @@ int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt)
} else {
struct xe_gt *full_gt = xe_find_full_gt(gt);
- gt->mem.ggtt = full_gt->mem.ggtt;
gt->mem.vram_mgr = full_gt->mem.vram_mgr;
}
@@ -348,8 +342,6 @@ int xe_gt_init_noalloc(struct xe_gt *gt)
if (err)
goto err_force_wake;
- err = xe_ggtt_init_noalloc(gt, gt->mem.ggtt);
-
err_force_wake:
err2 = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
XE_WARN_ON(err2);
@@ -370,7 +362,7 @@ static int gt_fw_domain_init(struct xe_gt *gt)
xe_pat_init(gt);
if (!xe_gt_is_media_type(gt)) {
- err = xe_ggtt_init(gt, gt->mem.ggtt);
+ err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt);
if (err)
goto err_force_wake;
}
diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
index 8bf441e850a0..a0f633109124 100644
--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
@@ -97,7 +97,7 @@ static int ggtt(struct seq_file *m, void *data)
struct xe_gt *gt = node_to_gt(m->private);
struct drm_printer p = drm_seq_file_printer(m);
- return xe_ggtt_dump(gt->mem.ggtt, &p);
+ return xe_ggtt_dump(gt_to_tile(gt)->mem.ggtt, &p);
}
static int register_save_restore(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 6f4243443d04..e910ec1b8dd3 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -14,7 +14,6 @@
#include "xe_uc_types.h"
struct xe_engine_ops;
-struct xe_ggtt;
struct xe_migrate;
struct xe_ring_ops;
struct xe_ttm_gtt_mgr;
@@ -174,8 +173,6 @@ struct xe_gt {
} vram;
/** @vram_mgr: VRAM TTM manager */
struct xe_ttm_vram_mgr *vram_mgr;
- /** @ggtt: Global graphics translation table */
- struct xe_ggtt *ggtt;
} mem;
/** @reset: state for GT resets */
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
new file mode 100644
index 000000000000..7ef594f301ca
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <drm/drm_managed.h>
+
+#include "xe_device.h"
+#include "xe_ggtt.h"
+#include "xe_tile.h"
+#include "xe_ttm_vram_mgr.h"
+
+/**
+ * xe_tile_alloc - Perform per-tile memory allocation
+ * @tile: Tile to perform allocations for
+ *
+ * Allocates various per-tile data structures using DRM-managed allocations.
+ * Does not touch the hardware.
+ *
+ * Returns -ENOMEM if allocations fail, otherwise 0.
+ */
+int xe_tile_alloc(struct xe_tile *tile)
+{
+ struct drm_device *drm = &tile_to_xe(tile)->drm;
+
+ tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt),
+ GFP_KERNEL);
+ if (!tile->mem.ggtt)
+ return -ENOMEM;
+ tile->mem.ggtt->tile = tile;
+
+ return 0;
+}
+
+/**
+ * xe_tile_init_noalloc - Init tile up to the point where allocations can happen.
+ * @tile: The tile to initialize.
+ *
+ * This function prepares the tile to allow memory allocations to VRAM, but is
+ * not allowed to allocate memory itself. This state is useful for display
+ * readout, because the inherited display framebuffer will otherwise be
+ * overwritten as it is usually put at the start of VRAM.
+ *
+ * Note that since this is tile initialization, it should not perform any
+ * GT-specific operations, and thus does not need to hold GT forcewake.
+ *
+ * Returns: 0 on success, negative error code on error.
+ */
+int xe_tile_init_noalloc(struct xe_tile *tile)
+{
+ return xe_ggtt_init_noalloc(tile->mem.ggtt);
+}
diff --git a/drivers/gpu/drm/xe/xe_tile.h b/drivers/gpu/drm/xe/xe_tile.h
new file mode 100644
index 000000000000..49b64d83ce91
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_tile.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __XE_TILE_H__
+#define __XE_TILE_H__
+
+struct xe_tile;
+
+int xe_tile_alloc(struct xe_tile *tile);
+int xe_tile_init_noalloc(struct xe_tile *tile);
+
+#endif
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 08/30] fixup! drm/xe/display: Implement display support
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (6 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 07/30] drm/xe: Move GGTT from GT to tile Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-25 23:30 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 09/30] drm/xe: Move VRAM from GT to tile Matt Roper
` (24 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 6 +++---
drivers/gpu/drm/xe/display/xe_plane_initial.c | 5 +++--
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index c7c4df18e439..27e4d29aa73d 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -123,7 +123,7 @@ static int __xe_pin_fb_vma_ggtt(struct intel_framebuffer *fb,
{
struct xe_bo *bo = intel_fb_obj(&fb->base);
struct xe_device *xe = to_xe_device(fb->base.dev);
- struct xe_ggtt *ggtt = to_gt(xe)->mem.ggtt;
+ struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
u32 align;
int ret;
@@ -173,7 +173,7 @@ static int __xe_pin_fb_vma_ggtt(struct intel_framebuffer *fb,
rot_info->plane[i].dst_stride);
}
- xe_ggtt_invalidate(to_gt(xe));
+ xe_ggtt_invalidate(ggtt);
out:
mutex_unlock(&ggtt->lock);
@@ -238,7 +238,7 @@ static struct i915_vma *__xe_pin_fb_vma(struct intel_framebuffer *fb,
static void __xe_unpin_fb_vma(struct i915_vma *vma)
{
struct xe_device *xe = to_xe_device(vma->bo->ttm.base.dev);
- struct xe_ggtt *ggtt = to_gt(xe)->mem.ggtt;
+ struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
if (vma->dpt)
xe_bo_unpin_map_no_vm(vma->dpt);
diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
index 34ae461865a7..41540b27775c 100644
--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
@@ -52,6 +52,7 @@ initial_plane_bo(struct xe_device *xe,
struct intel_initial_plane_config *plane_config)
{
struct xe_gt *gt0 = xe_device_get_gt(xe, 0);
+ struct xe_tile *tile0 = xe_device_get_root_tile(xe);
struct xe_bo *bo;
resource_size_t phys_base;
u32 base, size, flags;
@@ -64,7 +65,7 @@ initial_plane_bo(struct xe_device *xe,
base = round_down(plane_config->base, page_size);
if (IS_DGFX(xe)) {
- u64 __iomem *gte = gt0->mem.ggtt->gsm;
+ u64 __iomem *gte = tile0->mem.ggtt->gsm;
u64 pte;
gte += base / XE_PAGE_SIZE;
@@ -115,7 +116,7 @@ initial_plane_bo(struct xe_device *xe,
page_size);
size -= base;
- bo = xe_bo_create_pin_map_at(xe, gt0, NULL, size, phys_base,
+ bo = xe_bo_create_pin_map_at(xe, &tile0->primary_gt, NULL, size, phys_base,
ttm_bo_type_kernel, flags);
if (IS_ERR(bo)) {
drm_dbg(&xe->drm,
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 09/30] drm/xe: Move VRAM from GT to tile
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (7 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 08/30] fixup! drm/xe/display: Implement display support Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-26 21:11 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 10/30] fixup! drm/xe/display: Implement display support Matt Roper
` (23 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
On platforms with VRAM, the VRAM is associated with the tile, not the
GT.
v2:
- Unsquash the GGTT handling back into its own patch.
- Fix kunit test build
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/tests/xe_bo.c | 6 +-
drivers/gpu/drm/xe/xe_bo.c | 44 ++++++------
drivers/gpu/drm/xe/xe_bo.h | 4 +-
drivers/gpu/drm/xe/xe_device.c | 14 ++--
drivers/gpu/drm/xe/xe_device_types.h | 28 ++++++++
drivers/gpu/drm/xe/xe_gt.c | 83 ++--------------------
drivers/gpu/drm/xe/xe_gt_pagefault.c | 6 +-
drivers/gpu/drm/xe/xe_gt_types.h | 35 ---------
drivers/gpu/drm/xe/xe_irq.c | 2 +-
drivers/gpu/drm/xe/xe_mmio.c | 45 ++++++------
drivers/gpu/drm/xe/xe_pci.c | 2 -
drivers/gpu/drm/xe/xe_pt.c | 4 +-
drivers/gpu/drm/xe/xe_query.c | 4 +-
drivers/gpu/drm/xe/xe_res_cursor.h | 2 +-
drivers/gpu/drm/xe/xe_tile.c | 33 ++++++++-
drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | 16 ++---
drivers/gpu/drm/xe/xe_ttm_vram_mgr.h | 4 +-
drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h | 6 +-
19 files changed, 147 insertions(+), 192 deletions(-)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index cd1614b68734..94ed64be86e3 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -84,6 +84,7 @@ xe-y += xe_bb.o \
xe_sched_job.o \
xe_step.o \
xe_sync.o \
+ xe_tile.o \
xe_trace.o \
xe_ttm_sys_mgr.o \
xe_ttm_stolen_mgr.o \
diff --git a/drivers/gpu/drm/xe/tests/xe_bo.c b/drivers/gpu/drm/xe/tests/xe_bo.c
index 8f3afdc6cca6..6235a6c73a06 100644
--- a/drivers/gpu/drm/xe/tests/xe_bo.c
+++ b/drivers/gpu/drm/xe/tests/xe_bo.c
@@ -115,9 +115,9 @@ static void ccs_test_run_gt(struct xe_device *xe, struct xe_gt *gt,
int ret;
/* TODO: Sanity check */
- vram_bit = XE_BO_CREATE_VRAM0_BIT << gt->info.vram_id;
+ vram_bit = XE_BO_CREATE_VRAM0_BIT << gt_to_tile(gt)->id;
kunit_info(test, "Testing gt id %u vram id %u\n", gt->info.id,
- gt->info.vram_id);
+ gt_to_tile(gt)->id);
bo = xe_bo_create_locked(xe, NULL, NULL, SZ_1M, ttm_bo_type_device,
vram_bit);
@@ -179,7 +179,7 @@ static int evict_test_run_gt(struct xe_device *xe, struct xe_gt *gt, struct kuni
int err, i;
kunit_info(test, "Testing device %s gt id %u vram id %u\n",
- dev_name(xe->drm.dev), gt->info.id, gt->info.vram_id);
+ dev_name(xe->drm.dev), gt->info.id, gt_to_tile(gt)->id);
for (i = 0; i < 2; ++i) {
xe_vm_lock(vm, &ww, 0, false);
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index ecc82fefdf4c..5dbca5bbca8f 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -71,25 +71,25 @@ static bool xe_bo_is_user(struct xe_bo *bo)
return bo->flags & XE_BO_CREATE_USER_BIT;
}
-static struct xe_gt *
-mem_type_to_gt(struct xe_device *xe, u32 mem_type)
+static struct xe_tile *
+mem_type_to_tile(struct xe_device *xe, u32 mem_type)
{
XE_BUG_ON(mem_type != XE_PL_STOLEN && !mem_type_is_vram(mem_type));
- return xe_device_get_gt(xe, mem_type == XE_PL_STOLEN ? 0 : (mem_type - XE_PL_VRAM0));
+ return &xe->tiles[mem_type == XE_PL_STOLEN ? 0 : (mem_type - XE_PL_VRAM0)];
}
/**
- * xe_bo_to_gt() - Get a GT from a BO's memory location
+ * xe_bo_to_tile() - Get a tile from a BO's memory location
* @bo: The buffer object
*
- * Get a GT from a BO's memory location, should be called on BOs in VRAM only.
+ * Get a tile from a BO's memory location, should be called on BOs in VRAM only.
*
- * Return: xe_gt object which is closest to the BO
+ * Return: xe_tile object which is closest to the BO
*/
-struct xe_gt *xe_bo_to_gt(struct xe_bo *bo)
+struct xe_tile *xe_bo_to_tile(struct xe_bo *bo)
{
- return mem_type_to_gt(xe_bo_device(bo), bo->ttm.resource->mem_type);
+ return mem_type_to_tile(xe_bo_device(bo), bo->ttm.resource->mem_type);
}
static void try_add_system(struct xe_bo *bo, struct ttm_place *places,
@@ -109,9 +109,9 @@ static void try_add_system(struct xe_bo *bo, struct ttm_place *places,
static void add_vram(struct xe_device *xe, struct xe_bo *bo,
struct ttm_place *places, u32 bo_flags, u32 mem_type, u32 *c)
{
- struct xe_gt *gt = mem_type_to_gt(xe, mem_type);
+ struct xe_tile *tile = mem_type_to_tile(xe, mem_type);
- XE_BUG_ON(!gt->mem.vram.size);
+ XE_BUG_ON(!tile->mem.vram.size);
places[*c] = (struct ttm_place) {
.mem_type = mem_type,
@@ -356,7 +356,7 @@ static int xe_ttm_io_mem_reserve(struct ttm_device *bdev,
struct ttm_resource *mem)
{
struct xe_device *xe = ttm_to_xe_device(bdev);
- struct xe_gt *gt;
+ struct xe_tile *tile;
switch (mem->mem_type) {
case XE_PL_SYSTEM:
@@ -364,15 +364,15 @@ static int xe_ttm_io_mem_reserve(struct ttm_device *bdev,
return 0;
case XE_PL_VRAM0:
case XE_PL_VRAM1:
- gt = mem_type_to_gt(xe, mem->mem_type);
+ tile = mem_type_to_tile(xe, mem->mem_type);
mem->bus.offset = mem->start << PAGE_SHIFT;
- if (gt->mem.vram.mapping &&
+ if (tile->mem.vram.mapping &&
mem->placement & TTM_PL_FLAG_CONTIGUOUS)
- mem->bus.addr = (u8 *)gt->mem.vram.mapping +
+ mem->bus.addr = (u8 *)tile->mem.vram.mapping +
mem->bus.offset;
- mem->bus.offset += gt->mem.vram.io_start;
+ mem->bus.offset += tile->mem.vram.io_start;
mem->bus.is_iomem = true;
#if !defined(CONFIG_X86)
@@ -632,9 +632,9 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
if (bo->gt)
gt = bo->gt;
else if (resource_is_vram(new_mem))
- gt = mem_type_to_gt(xe, new_mem->mem_type);
+ gt = &mem_type_to_tile(xe, new_mem->mem_type)->primary_gt;
else if (resource_is_vram(old_mem))
- gt = mem_type_to_gt(xe, old_mem->mem_type);
+ gt = &mem_type_to_tile(xe, old_mem->mem_type)->primary_gt;
XE_BUG_ON(!gt);
XE_BUG_ON(!gt->migrate);
@@ -658,7 +658,7 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
/* Create a new VMAP once kernel BO back in VRAM */
if (!ret && resource_is_vram(new_mem)) {
- void *new_addr = gt->mem.vram.mapping +
+ void *new_addr = gt_to_tile(gt)->mem.vram.mapping +
(new_mem->start << PAGE_SHIFT);
if (XE_WARN_ON(new_mem->start == XE_BO_INVALID_OFFSET)) {
@@ -830,14 +830,14 @@ static unsigned long xe_ttm_io_mem_pfn(struct ttm_buffer_object *ttm_bo,
{
struct xe_device *xe = ttm_to_xe_device(ttm_bo->bdev);
struct xe_bo *bo = ttm_to_xe_bo(ttm_bo);
- struct xe_gt *gt = mem_type_to_gt(xe, ttm_bo->resource->mem_type);
+ struct xe_tile *tile = mem_type_to_tile(xe, ttm_bo->resource->mem_type);
struct xe_res_cursor cursor;
if (ttm_bo->resource->mem_type == XE_PL_STOLEN)
return xe_ttm_stolen_io_offset(bo, page_offset << PAGE_SHIFT) >> PAGE_SHIFT;
xe_res_first(ttm_bo->resource, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
- return (gt->mem.vram.io_start + cursor.start) >> PAGE_SHIFT;
+ return (tile->mem.vram.io_start + cursor.start) >> PAGE_SHIFT;
}
static void __xe_bo_vunmap(struct xe_bo *bo);
@@ -1338,12 +1338,12 @@ struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_gt *gt,
uint64_t vram_region_io_offset(struct ttm_resource *res)
{
struct xe_device *xe = ttm_to_xe_device(res->bo->bdev);
- struct xe_gt *gt = mem_type_to_gt(xe, res->mem_type);
+ struct xe_tile *tile = mem_type_to_tile(xe, res->mem_type);
if (res->mem_type == XE_PL_STOLEN)
return xe_ttm_stolen_gpu_offset(xe);
- return gt->mem.vram.io_start - xe->mem.vram.io_start;
+ return tile->mem.vram.io_start - xe->mem.vram.io_start;
}
/**
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index 7e111332c35a..7a79f3893260 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -22,7 +22,7 @@
/* -- */
#define XE_BO_CREATE_STOLEN_BIT BIT(4)
#define XE_BO_CREATE_VRAM_IF_DGFX(gt) \
- (IS_DGFX(gt_to_xe(gt)) ? XE_BO_CREATE_VRAM0_BIT << gt->info.vram_id : \
+ (IS_DGFX(gt_to_xe(gt)) ? XE_BO_CREATE_VRAM0_BIT << gt_to_tile(gt)->id : \
XE_BO_CREATE_SYSTEM_BIT)
#define XE_BO_CREATE_GGTT_BIT BIT(5)
#define XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT BIT(6)
@@ -107,7 +107,7 @@ struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_gt *gt,
int xe_bo_placement_for_flags(struct xe_device *xe, struct xe_bo *bo,
u32 bo_flags);
-struct xe_gt *xe_bo_to_gt(struct xe_bo *bo);
+struct xe_tile *xe_bo_to_tile(struct xe_bo *bo);
static inline struct xe_bo *ttm_to_xe_bo(const struct ttm_buffer_object *bo)
{
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index f7f6a6a97757..af165ad6f197 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -27,6 +27,7 @@
#include "xe_pcode.h"
#include "xe_pm.h"
#include "xe_query.h"
+#include "xe_tile.h"
#include "xe_ttm_stolen_mgr.h"
#include "xe_ttm_sys_mgr.h"
#include "xe_vm.h"
@@ -236,6 +237,7 @@ static void xe_device_sanitize(struct drm_device *drm, void *arg)
int xe_device_probe(struct xe_device *xe)
{
+ struct xe_tile *tile;
struct xe_gt *gt;
int err;
u8 id;
@@ -245,8 +247,12 @@ int xe_device_probe(struct xe_device *xe)
if (err)
return err;
- for_each_gt(gt, xe, id) {
- err = xe_gt_alloc(xe, gt);
+ for_each_tile(tile, xe, id) {
+ err = xe_tile_alloc(tile);
+ if (err)
+ return err;
+
+ err = xe_gt_alloc(xe, &tile->primary_gt);
if (err)
return err;
}
@@ -281,8 +287,8 @@ int xe_device_probe(struct xe_device *xe)
xe_ttm_sys_mgr_init(xe);
- for_each_gt(gt, xe, id) {
- err = xe_gt_init_noalloc(gt);
+ for_each_tile(tile, xe, id) {
+ err = xe_tile_init_noalloc(tile);
if (err)
goto err_irq_shutdown;
}
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index cb4d0c2ea184..e3fe47c13269 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -102,6 +102,34 @@ struct xe_tile {
/** @mem: memory management info for tile */
struct {
+ /**
+ * @vram: VRAM info for tile.
+ *
+ * Although VRAM is associated with a specific tile, it can
+ * still be accessed by all tiles' GTs.
+ */
+ struct {
+ /** @io_start: IO start address of this VRAM instance */
+ resource_size_t io_start;
+ /**
+ * @io_size: IO size of this VRAM instance
+ *
+ * This represents how much of this VRAM we can access
+ * via the CPU through the VRAM BAR. This can be smaller
+ * than @size, in which case only part of VRAM is CPU
+ * accessible (typically the first 256M). This
+ * configuration is known as small-bar.
+ */
+ resource_size_t io_size;
+ /** @size: size of VRAM. */
+ resource_size_t size;
+ /** @mapping: pointer to VRAM mappable space */
+ void *__iomem mapping;
+ } vram;
+
+ /** @vram_mgr: VRAM TTM manager */
+ struct xe_ttm_vram_mgr *vram_mgr;
+
/** @ggtt: Global graphics translation table */
struct xe_ggtt *ggtt;
} mem;
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 1c58a9aff2cb..ac6073a7fb59 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -37,7 +37,6 @@
#include "xe_ring_ops.h"
#include "xe_sa.h"
#include "xe_sched_job.h"
-#include "xe_ttm_vram_mgr.h"
#include "xe_tuning.h"
#include "xe_uc.h"
#include "xe_vm.h"
@@ -46,58 +45,23 @@
struct xe_gt *xe_find_full_gt(struct xe_gt *gt)
{
- struct xe_gt *search;
- u8 id;
-
- XE_BUG_ON(!xe_gt_is_media_type(gt));
-
- for_each_gt(search, gt_to_xe(gt), id) {
- if (search->info.vram_id == gt->info.vram_id)
- return search;
- }
-
- XE_BUG_ON("NOT POSSIBLE");
- return NULL;
+ /*
+ * FIXME: Media GTs are disabled at the moment. Once re-enabled,
+ * the proper handling here is to return the primary GT from the
+ * parameter GT's tile.
+ */
+ return gt;
}
int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt)
{
- struct drm_device *drm = &xe->drm;
-
XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
- if (!xe_gt_is_media_type(gt)) {
- gt->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*gt->mem.vram_mgr),
- GFP_KERNEL);
- if (!gt->mem.vram_mgr)
- return -ENOMEM;
-
- } else {
- struct xe_gt *full_gt = xe_find_full_gt(gt);
-
- gt->mem.vram_mgr = full_gt->mem.vram_mgr;
- }
-
gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", 0);
return 0;
}
-static int gt_ttm_mgr_init(struct xe_gt *gt)
-{
- struct xe_device *xe = gt_to_xe(gt);
- int err;
-
- if (gt->mem.vram.size) {
- err = xe_ttm_vram_mgr_init(gt, gt->mem.vram_mgr);
- if (err)
- return err;
- xe->info.mem_region_mask |= BIT(gt->info.vram_id) << 1;
- }
-
- return 0;
-}
-
void xe_gt_sanitize(struct xe_gt *gt)
{
/*
@@ -315,41 +279,6 @@ int xe_gt_init_early(struct xe_gt *gt)
return 0;
}
-/**
- * xe_gt_init_noalloc - Init GT up to the point where allocations can happen.
- * @gt: The GT to initialize.
- *
- * This function prepares the GT to allow memory allocations to VRAM, but is not
- * allowed to allocate memory itself. This state is useful for display readout,
- * because the inherited display framebuffer will otherwise be overwritten as it
- * is usually put at the start of VRAM.
- *
- * Returns: 0 on success, negative error code on error.
- */
-int xe_gt_init_noalloc(struct xe_gt *gt)
-{
- int err, err2;
-
- if (xe_gt_is_media_type(gt))
- return 0;
-
- xe_device_mem_access_get(gt_to_xe(gt));
- err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
- if (err)
- goto err;
-
- err = gt_ttm_mgr_init(gt);
- if (err)
- goto err_force_wake;
-
-err_force_wake:
- err2 = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
- XE_WARN_ON(err2);
- xe_device_mem_access_put(gt_to_xe(gt));
-err:
- return err;
-}
-
static int gt_fw_domain_init(struct xe_gt *gt)
{
int err, i;
diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c
index 1677640e1075..f4f3d95ae6b1 100644
--- a/drivers/gpu/drm/xe/xe_gt_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c
@@ -107,6 +107,7 @@ static struct xe_vma *lookup_vma(struct xe_vm *vm, u64 page_addr)
static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf)
{
struct xe_device *xe = gt_to_xe(gt);
+ struct xe_tile *tile = gt_to_tile(gt);
struct xe_vm *vm;
struct xe_vma *vma = NULL;
struct xe_bo *bo;
@@ -195,7 +196,7 @@ static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf)
}
/* Migrate to VRAM, move should invalidate the VMA first */
- ret = xe_bo_migrate(bo, XE_PL_VRAM0 + gt->info.vram_id);
+ ret = xe_bo_migrate(bo, XE_PL_VRAM0 + tile->id);
if (ret)
goto unlock_dma_resv;
} else if (bo) {
@@ -498,6 +499,7 @@ static struct xe_vma *get_acc_vma(struct xe_vm *vm, struct acc *acc)
static int handle_acc(struct xe_gt *gt, struct acc *acc)
{
struct xe_device *xe = gt_to_xe(gt);
+ struct xe_tile *tile = gt_to_tile(gt);
struct xe_vm *vm;
struct xe_vma *vma;
struct xe_bo *bo;
@@ -553,7 +555,7 @@ static int handle_acc(struct xe_gt *gt, struct acc *acc)
goto unlock_vm;
/* Migrate to VRAM, move should invalidate the VMA first */
- ret = xe_bo_migrate(bo, XE_PL_VRAM0 + gt->info.vram_id);
+ ret = xe_bo_migrate(bo, XE_PL_VRAM0 + tile->id);
if (only_needs_bo_lock(bo))
xe_bo_unlock(bo, &ww);
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index e910ec1b8dd3..fcea0dc150ed 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -16,8 +16,6 @@
struct xe_engine_ops;
struct xe_migrate;
struct xe_ring_ops;
-struct xe_ttm_gtt_mgr;
-struct xe_ttm_vram_mgr;
enum xe_gt_type {
XE_GT_TYPE_UNINITIALIZED,
@@ -108,8 +106,6 @@ struct xe_gt {
enum xe_gt_type type;
/** @id: id of GT */
u8 id;
- /** @vram: id of the VRAM for this GT */
- u8 vram_id;
/** @clock_freq: clock frequency */
u32 clock_freq;
/** @engine_mask: mask of engines present on GT */
@@ -144,37 +140,6 @@ struct xe_gt {
*/
struct xe_reg_sr reg_sr;
- /**
- * @mem: memory management info for GT, multiple GTs can point to same
- * objects (virtual split)
- */
- struct {
- /**
- * @vram: VRAM info for GT, multiple GTs can point to same info
- * (virtual split), can be subset of global device VRAM
- */
- struct {
- /** @io_start: IO start address of this VRAM instance */
- resource_size_t io_start;
- /**
- * @io_size: IO size of this VRAM instance
- *
- * This represents how much of this VRAM we can access
- * via the CPU through the VRAM BAR. This can be smaller
- * than @size, in which case only part of VRAM is CPU
- * accessible (typically the first 256M). This
- * configuration is known as small-bar.
- */
- resource_size_t io_size;
- /** @size: size of VRAM. */
- resource_size_t size;
- /** @mapping: pointer to VRAM mappable space */
- void *__iomem mapping;
- } vram;
- /** @vram_mgr: VRAM TTM manager */
- struct xe_ttm_vram_mgr *vram_mgr;
- } mem;
-
/** @reset: state for GT resets */
struct {
/**
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 5bf359c81cc5..5be31855d789 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -369,7 +369,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
}
for_each_gt(gt, xe, id) {
- if ((master_tile_ctl & DG1_MSTR_TILE(gt->info.vram_id)) == 0)
+ if ((master_tile_ctl & DG1_MSTR_TILE(gt_to_tile(gt)->id)) == 0)
continue;
if (!xe_gt_is_media_type(gt))
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 54fa1212fcd9..17b3a9880409 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -182,7 +182,7 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_si
int xe_mmio_probe_vram(struct xe_device *xe)
{
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
- struct xe_gt *gt;
+ struct xe_tile *tile;
u8 id;
u64 vram_size;
u64 original_size;
@@ -195,11 +195,11 @@ int xe_mmio_probe_vram(struct xe_device *xe)
xe->mem.vram.io_start = 0;
xe->mem.vram.io_size = 0;
- for_each_gt(gt, xe, id) {
- gt->mem.vram.mapping = 0;
- gt->mem.vram.size = 0;
- gt->mem.vram.io_start = 0;
- gt->mem.vram.io_size = 0;
+ for_each_tile(tile, xe, id) {
+ tile->mem.vram.mapping = 0;
+ tile->mem.vram.size = 0;
+ tile->mem.vram.io_start = 0;
+ tile->mem.vram.io_size = 0;
}
return 0;
}
@@ -209,7 +209,6 @@ int xe_mmio_probe_vram(struct xe_device *xe)
return -ENXIO;
}
- gt = xe_device_get_gt(xe, 0);
original_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
err = xe_mmio_total_vram_size(xe, &vram_size, &usable_size);
@@ -239,23 +238,19 @@ int xe_mmio_probe_vram(struct xe_device *xe)
u8 adj_tile_count = xe->info.tile_count;
resource_size_t size, io_start, io_size;
- for_each_gt(gt, xe, id)
- if (xe_gt_is_media_type(gt))
- --adj_tile_count;
-
XE_BUG_ON(!adj_tile_count);
size = xe->mem.vram.size / adj_tile_count;
io_start = xe->mem.vram.io_start;
io_size = xe->mem.vram.io_size;
- for_each_gt(gt, xe, id) {
- if (id && !xe_gt_is_media_type(gt)) {
+ for_each_tile(tile, xe, id) {
+ if (id) {
io_size -= min(io_size, size);
io_start += io_size;
}
- gt->mem.vram.size = size;
+ tile->mem.vram.size = size;
/*
* XXX: multi-tile small-bar might be wild. Hopefully
@@ -263,10 +258,10 @@ int xe_mmio_probe_vram(struct xe_device *xe)
* we care about.
*/
- gt->mem.vram.io_size = min(size, io_size);
+ tile->mem.vram.io_size = min(size, io_size);
if (io_size) {
- gt->mem.vram.io_start = io_start;
- gt->mem.vram.mapping = xe->mem.vram.mapping +
+ tile->mem.vram.io_start = io_start;
+ tile->mem.vram.mapping = xe->mem.vram.mapping +
(io_start - xe->mem.vram.io_start);
} else {
drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
@@ -274,16 +269,18 @@ int xe_mmio_probe_vram(struct xe_device *xe)
}
drm_info(&xe->drm, "VRAM[%u, %u]: %pa, %pa\n",
- id, gt->info.vram_id, >->mem.vram.io_start,
- >->mem.vram.size);
+ id, tile->id, &tile->mem.vram.io_start,
+ &tile->mem.vram.size);
}
} else {
- gt->mem.vram.size = xe->mem.vram.size;
- gt->mem.vram.io_start = xe->mem.vram.io_start;
- gt->mem.vram.io_size = xe->mem.vram.io_size;
- gt->mem.vram.mapping = xe->mem.vram.mapping;
+ tile = xe_device_get_root_tile(xe);
- drm_info(&xe->drm, "VRAM: %pa\n", >->mem.vram.size);
+ tile->mem.vram.size = xe->mem.vram.size;
+ tile->mem.vram.io_start = xe->mem.vram.io_start;
+ tile->mem.vram.io_size = xe->mem.vram.io_size;
+ tile->mem.vram.mapping = xe->mem.vram.mapping;
+
+ drm_info(&xe->drm, "VRAM: %pa\n", &tile->mem.vram.size);
}
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 0fb7ebb9653e..0269327b26e9 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -559,7 +559,6 @@ static int xe_info_init(struct xe_device *xe,
if (id == 0) {
gt->info.type = XE_GT_TYPE_MAIN;
- gt->info.vram_id = id;
gt->info.__engine_mask = graphics_desc->hw_engine_mask;
if (MEDIA_VER(xe) < 13 && media_desc)
@@ -569,7 +568,6 @@ static int xe_info_init(struct xe_device *xe,
gt->mmio.adj_offset = 0;
} else {
gt->info.type = desc->extra_gts[id - 1].type;
- gt->info.vram_id = desc->extra_gts[id - 1].vram_id;
gt->info.__engine_mask = (gt->info.type == XE_GT_TYPE_MEDIA) ?
media_desc->hw_engine_mask :
graphics_desc->hw_engine_mask;
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 61126cefe0b5..ad42a21c0e22 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -758,12 +758,12 @@ xe_pt_stage_bind(struct xe_gt *gt, struct xe_vma *vma,
int ret;
if (is_vram) {
- struct xe_gt *bo_gt = xe_bo_to_gt(bo);
+ struct xe_tile *bo_tile = xe_bo_to_tile(bo);
xe_walk.default_pte = XE_PPGTT_PTE_LM;
if (vma && vma->use_atomic_access_pte_bit)
xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
- xe_walk.dma_offset = bo_gt->mem.vram.io_start -
+ xe_walk.dma_offset = bo_tile->mem.vram.io_start -
gt_to_xe(gt)->mem.vram.io_start;
xe_walk.cache = XE_CACHE_WB;
} else {
diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index dd64ff0d2a57..c81652d7f4ec 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -182,7 +182,7 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query)
config->num_params = num_params;
config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID] =
xe->info.devid | (xe->info.revid << 16);
- if (to_gt(xe)->mem.vram.size)
+ if (xe_device_get_root_tile(xe)->mem.vram.size)
config->info[XE_QUERY_CONFIG_FLAGS] =
XE_QUERY_CONFIG_FLAGS_HAS_VRAM;
if (xe->info.enable_guc)
@@ -242,7 +242,7 @@ static int query_gts(struct xe_device *xe, struct drm_xe_device_query *query)
gts->gts[id].native_mem_regions = 0x1;
else
gts->gts[id].native_mem_regions =
- BIT(gt->info.vram_id) << 1;
+ BIT(gt_to_tile(gt)->id) << 1;
gts->gts[id].slow_mem_regions = xe->info.mem_region_mask ^
gts->gts[id].native_mem_regions;
}
diff --git a/drivers/gpu/drm/xe/xe_res_cursor.h b/drivers/gpu/drm/xe/xe_res_cursor.h
index 4e99fae26b4c..f2ba609712d3 100644
--- a/drivers/gpu/drm/xe/xe_res_cursor.h
+++ b/drivers/gpu/drm/xe/xe_res_cursor.h
@@ -53,7 +53,7 @@ static struct drm_buddy *xe_res_get_buddy(struct ttm_resource *res)
struct xe_device *xe = ttm_to_xe_device(res->bo->bdev);
if (res->mem_type != XE_PL_STOLEN) {
- return &xe_device_get_gt(xe, res->mem_type - XE_PL_VRAM0)->mem.vram_mgr->mm;
+ return &xe->tiles[res->mem_type - XE_PL_VRAM0].mem.vram_mgr->mm;
} else {
struct ttm_resource_manager *mgr =
ttm_manager_type(&xe->ttm, XE_PL_STOLEN);
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
index 7ef594f301ca..5530a6b6ef31 100644
--- a/drivers/gpu/drm/xe/xe_tile.c
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -29,6 +29,25 @@ int xe_tile_alloc(struct xe_tile *tile)
return -ENOMEM;
tile->mem.ggtt->tile = tile;
+ tile->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile->mem.vram_mgr), GFP_KERNEL);
+ if (!tile->mem.vram_mgr)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int tile_ttm_mgr_init(struct xe_tile *tile)
+{
+ struct xe_device *xe = tile_to_xe(tile);
+ int err;
+
+ if (tile->mem.vram.size) {
+ err = xe_ttm_vram_mgr_init(tile, tile->mem.vram_mgr);
+ if (err)
+ return err;
+ xe->info.mem_region_mask |= BIT(tile->id) << 1;
+ }
+
return 0;
}
@@ -48,5 +67,17 @@ int xe_tile_alloc(struct xe_tile *tile)
*/
int xe_tile_init_noalloc(struct xe_tile *tile)
{
- return xe_ggtt_init_noalloc(tile->mem.ggtt);
+ int err;
+
+ xe_device_mem_access_get(tile_to_xe(tile));
+
+ err = tile_ttm_mgr_init(tile);
+ if (err)
+ goto err_mem_access;
+
+ err = xe_ggtt_init_noalloc(tile->mem.ggtt);
+
+err_mem_access:
+ xe_device_mem_access_put(tile_to_xe(tile));
+ return err;
}
diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
index 73836b9b7fed..1a84abd35fcf 100644
--- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
@@ -353,16 +353,14 @@ int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct xe_ttm_vram_mgr *mgr,
return drmm_add_action_or_reset(&xe->drm, ttm_vram_mgr_fini, mgr);
}
-int xe_ttm_vram_mgr_init(struct xe_gt *gt, struct xe_ttm_vram_mgr *mgr)
+int xe_ttm_vram_mgr_init(struct xe_tile *tile, struct xe_ttm_vram_mgr *mgr)
{
- struct xe_device *xe = gt_to_xe(gt);
+ struct xe_device *xe = tile_to_xe(tile);
- XE_BUG_ON(xe_gt_is_media_type(gt));
+ mgr->tile = tile;
- mgr->gt = gt;
-
- return __xe_ttm_vram_mgr_init(xe, mgr, XE_PL_VRAM0 + gt->info.vram_id,
- gt->mem.vram.size, gt->mem.vram.io_size,
+ return __xe_ttm_vram_mgr_init(xe, mgr, XE_PL_VRAM0 + tile->id,
+ tile->mem.vram.size, tile->mem.vram.io_size,
PAGE_SIZE);
}
@@ -373,7 +371,7 @@ int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,
enum dma_data_direction dir,
struct sg_table **sgt)
{
- struct xe_gt *gt = xe_device_get_gt(xe, res->mem_type - XE_PL_VRAM0);
+ struct xe_tile *tile = &xe->tiles[res->mem_type - XE_PL_VRAM0];
struct xe_res_cursor cursor;
struct scatterlist *sg;
int num_entries = 0;
@@ -406,7 +404,7 @@ int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,
*/
xe_res_first(res, offset, length, &cursor);
for_each_sgtable_sg((*sgt), sg, i) {
- phys_addr_t phys = cursor.start + gt->mem.vram.io_start;
+ phys_addr_t phys = cursor.start + tile->mem.vram.io_start;
size_t size = cursor.size;
dma_addr_t addr;
diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
index 35e5367a79fb..6e1d6033d739 100644
--- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
+++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
@@ -10,12 +10,12 @@
enum dma_data_direction;
struct xe_device;
-struct xe_gt;
+struct xe_tile;
int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct xe_ttm_vram_mgr *mgr,
u32 mem_type, u64 size, u64 io_size,
u64 default_page_size);
-int xe_ttm_vram_mgr_init(struct xe_gt *gt, struct xe_ttm_vram_mgr *mgr);
+int xe_ttm_vram_mgr_init(struct xe_tile *tile, struct xe_ttm_vram_mgr *mgr);
int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,
struct ttm_resource *res,
u64 offset, u64 length,
diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h b/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
index 3d9417ff7434..48bb991c14a5 100644
--- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
+++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
@@ -9,7 +9,7 @@
#include <drm/drm_buddy.h>
#include <drm/ttm/ttm_device.h>
-struct xe_gt;
+struct xe_tile;
/**
* struct xe_ttm_vram_mgr - XE TTM VRAM manager
@@ -17,8 +17,8 @@ struct xe_gt;
* Manages placement of TTM resource in VRAM.
*/
struct xe_ttm_vram_mgr {
- /** @gt: Graphics tile which the VRAM belongs to */
- struct xe_gt *gt;
+ /** @tile: Tile which the VRAM belongs to */
+ struct xe_tile *tile;
/** @manager: Base TTM resource manager */
struct ttm_resource_manager manager;
/** @mm: DRM buddy allocator which manages the VRAM */
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 10/30] fixup! drm/xe/display: Implement display support
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (8 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 09/30] drm/xe: Move VRAM from GT to tile Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-26 21:12 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 11/30] drm/xe: Memory allocations are tile-based, not GT-based Matt Roper
` (22 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
---
drivers/gpu/drm/xe/display/xe_plane_initial.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
index 41540b27775c..39dd97acae08 100644
--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
@@ -51,7 +51,6 @@ static struct xe_bo *
initial_plane_bo(struct xe_device *xe,
struct intel_initial_plane_config *plane_config)
{
- struct xe_gt *gt0 = xe_device_get_gt(xe, 0);
struct xe_tile *tile0 = xe_device_get_root_tile(xe);
struct xe_bo *bo;
resource_size_t phys_base;
@@ -84,7 +83,7 @@ initial_plane_bo(struct xe_device *xe,
* We don't currently expect this to ever be placed in the
* stolen portion.
*/
- if (phys_base >= gt0->mem.vram.size) {
+ if (phys_base >= tile0->mem.vram.size) {
drm_err(&xe->drm,
"Initial plane programming using invalid range, phys_base=%pa\n",
&phys_base);
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 11/30] drm/xe: Memory allocations are tile-based, not GT-based
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (9 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 10/30] fixup! drm/xe/display: Implement display support Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 12/30] fixup! drm/xe/display: Implement display support Matt Roper
` (21 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
Since memory and address spaces are a tile concept rather than a GT
concept, we need to plumb tile-based handling through lots of
memory-related code.
Note that one remaining shortcoming here that will need to be addressed
before media GT support can be re-enabled is that although the address
space is shared between a tile's GTs, each GT caches the PTEs
independently in their own TLB and thus TLB invalidation should be
handled at the GT level.
v2:
- Fix kunit test build.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/tests/xe_bo.c | 2 +-
drivers/gpu/drm/xe/tests/xe_migrate.c | 21 ++--
drivers/gpu/drm/xe/xe_bb.c | 3 +-
drivers/gpu/drm/xe/xe_bo.c | 66 +++++------
drivers/gpu/drm/xe/xe_bo.h | 18 +--
drivers/gpu/drm/xe/xe_bo_evict.c | 2 +-
drivers/gpu/drm/xe/xe_bo_types.h | 4 +-
drivers/gpu/drm/xe/xe_device_types.h | 7 ++
drivers/gpu/drm/xe/xe_ggtt.c | 5 +-
drivers/gpu/drm/xe/xe_gt.c | 21 +---
drivers/gpu/drm/xe/xe_gt_debugfs.c | 6 +-
drivers/gpu/drm/xe/xe_gt_pagefault.c | 10 +-
drivers/gpu/drm/xe/xe_gt_types.h | 7 --
drivers/gpu/drm/xe/xe_guc_ads.c | 5 +-
drivers/gpu/drm/xe/xe_guc_ct.c | 5 +-
drivers/gpu/drm/xe/xe_guc_hwconfig.c | 5 +-
drivers/gpu/drm/xe/xe_guc_log.c | 6 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 5 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 5 +-
drivers/gpu/drm/xe/xe_lrc.c | 13 +--
drivers/gpu/drm/xe/xe_lrc_types.h | 4 +-
drivers/gpu/drm/xe/xe_migrate.c | 23 ++--
drivers/gpu/drm/xe/xe_migrate.h | 5 +-
drivers/gpu/drm/xe/xe_pt.c | 146 ++++++++++++-------------
drivers/gpu/drm/xe/xe_pt.h | 14 +--
drivers/gpu/drm/xe/xe_sa.c | 13 +--
drivers/gpu/drm/xe/xe_sa.h | 4 +-
drivers/gpu/drm/xe/xe_tile.c | 7 ++
drivers/gpu/drm/xe/xe_uc_fw.c | 5 +-
drivers/gpu/drm/xe/xe_vm.c | 152 +++++++++++++-------------
drivers/gpu/drm/xe/xe_vm.h | 2 +-
drivers/gpu/drm/xe/xe_vm_types.h | 12 +-
include/uapi/drm/xe_drm.h | 4 +-
33 files changed, 296 insertions(+), 311 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_bo.c b/drivers/gpu/drm/xe/tests/xe_bo.c
index 6235a6c73a06..f933e5df6c12 100644
--- a/drivers/gpu/drm/xe/tests/xe_bo.c
+++ b/drivers/gpu/drm/xe/tests/xe_bo.c
@@ -173,7 +173,7 @@ static int evict_test_run_gt(struct xe_device *xe, struct xe_gt *gt, struct kuni
{
struct xe_bo *bo, *external;
unsigned int bo_flags = XE_BO_CREATE_USER_BIT |
- XE_BO_CREATE_VRAM_IF_DGFX(gt);
+ XE_BO_CREATE_VRAM_IF_DGFX(gt_to_tile(gt));
struct xe_vm *vm = xe_migrate_get_vm(xe_device_get_root_tile(xe)->primary_gt.migrate);
struct ww_acquire_ctx ww;
int err, i;
diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c
index 0f4371ad1fd9..813ebb4832e7 100644
--- a/drivers/gpu/drm/xe/tests/xe_migrate.c
+++ b/drivers/gpu/drm/xe/tests/xe_migrate.c
@@ -63,7 +63,7 @@ static int run_sanity_job(struct xe_migrate *m, struct xe_device *xe,
static void
sanity_populate_cb(struct xe_migrate_pt_update *pt_update,
- struct xe_gt *gt, struct iosys_map *map, void *dst,
+ struct xe_tile *tile, struct iosys_map *map, void *dst,
u32 qword_ofs, u32 num_qwords,
const struct xe_vm_pgtable_update *update)
{
@@ -76,7 +76,7 @@ sanity_populate_cb(struct xe_migrate_pt_update *pt_update,
for (i = 0; i < num_qwords; i++) {
value = (qword_ofs + i - update->ofs) * 0x1111111111111111ULL;
if (map)
- xe_map_wr(gt_to_xe(gt), map, (qword_ofs + i) *
+ xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *
sizeof(u64), u64, value);
else
ptr[i] = value;
@@ -108,7 +108,7 @@ static void test_copy(struct xe_migrate *m, struct xe_bo *bo,
const char *str = big ? "Copying big bo" : "Copying small bo";
int err;
- struct xe_bo *sysmem = xe_bo_create_locked(xe, m->gt, NULL,
+ struct xe_bo *sysmem = xe_bo_create_locked(xe, gt_to_tile(m->gt), NULL,
bo->size,
ttm_bo_type_kernel,
XE_BO_CREATE_SYSTEM_BIT);
@@ -240,6 +240,7 @@ static void test_pt_update(struct xe_migrate *m, struct xe_bo *pt,
static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
{
struct xe_gt *gt = m->gt;
+ struct xe_tile *tile = gt_to_tile(m->gt);
struct xe_device *xe = gt_to_xe(gt);
struct xe_bo *pt, *bo = m->pt_bo, *big, *tiny;
struct xe_res_cursor src_it;
@@ -256,18 +257,18 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
return;
}
- big = xe_bo_create_pin_map(xe, m->gt, m->eng->vm, SZ_4M,
+ big = xe_bo_create_pin_map(xe, tile, m->eng->vm, SZ_4M,
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(m->gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_PINNED_BIT);
if (IS_ERR(big)) {
KUNIT_FAIL(test, "Failed to allocate bo: %li\n", PTR_ERR(big));
goto vunmap;
}
- pt = xe_bo_create_pin_map(xe, m->gt, m->eng->vm, XE_PAGE_SIZE,
+ pt = xe_bo_create_pin_map(xe, tile, m->eng->vm, XE_PAGE_SIZE,
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(m->gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_PINNED_BIT);
if (IS_ERR(pt)) {
KUNIT_FAIL(test, "Failed to allocate fake pt: %li\n",
@@ -275,10 +276,10 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
goto free_big;
}
- tiny = xe_bo_create_pin_map(xe, m->gt, m->eng->vm,
+ tiny = xe_bo_create_pin_map(xe, tile, m->eng->vm,
2 * SZ_4K,
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(m->gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_PINNED_BIT);
if (IS_ERR(tiny)) {
KUNIT_FAIL(test, "Failed to allocate fake pt: %li\n",
@@ -286,7 +287,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
goto free_pt;
}
- bb = xe_bb_new(m->gt, 32, xe->info.supports_usm);
+ bb = xe_bb_new(gt, 32, xe->info.supports_usm);
if (IS_ERR(bb)) {
KUNIT_FAIL(test, "Failed to create batchbuffer: %li\n",
PTR_ERR(bb));
diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
index bf7c94b769d7..f9b6b7adf99f 100644
--- a/drivers/gpu/drm/xe/xe_bb.c
+++ b/drivers/gpu/drm/xe/xe_bb.c
@@ -30,6 +30,7 @@ static int bb_prefetch(struct xe_gt *gt)
struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)
{
+ struct xe_tile *tile = gt_to_tile(gt);
struct xe_bb *bb = kmalloc(sizeof(*bb), GFP_KERNEL);
int err;
@@ -42,7 +43,7 @@ struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)
* space to accomodate the platform-specific hardware prefetch
* requirements.
*/
- bb->bo = xe_sa_bo_new(!usm ? gt->kernel_bb_pool : gt->usm.bb_pool,
+ bb->bo = xe_sa_bo_new(!usm ? tile->mem.kernel_bb_pool : gt->usm.bb_pool,
4 * (dwords + 1) + bb_prefetch(gt));
if (IS_ERR(bb->bo)) {
err = PTR_ERR(bb->bo);
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 5dbca5bbca8f..9d613fc5d309 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -452,7 +452,7 @@ static int xe_bo_trigger_rebind(struct xe_device *xe, struct xe_bo *bo,
}
xe_vm_assert_held(vm);
- if (list_empty(&vma->rebind_link) && vma->gt_present)
+ if (list_empty(&vma->rebind_link) && vma->tile_present)
list_add_tail(&vma->rebind_link, &vm->rebind_list);
if (vm_resv_locked)
@@ -559,7 +559,7 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
struct xe_bo *bo = ttm_to_xe_bo(ttm_bo);
struct ttm_resource *old_mem = ttm_bo->resource;
struct ttm_tt *ttm = ttm_bo->ttm;
- struct xe_gt *gt = NULL;
+ struct xe_tile *tile = NULL;
struct dma_fence *fence;
bool move_lacks_source;
bool needs_clear;
@@ -629,15 +629,15 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
goto out;
}
- if (bo->gt)
- gt = bo->gt;
+ if (bo->tile)
+ tile = bo->tile;
else if (resource_is_vram(new_mem))
- gt = &mem_type_to_tile(xe, new_mem->mem_type)->primary_gt;
+ tile = mem_type_to_tile(xe, new_mem->mem_type);
else if (resource_is_vram(old_mem))
- gt = &mem_type_to_tile(xe, old_mem->mem_type)->primary_gt;
+ tile = mem_type_to_tile(xe, old_mem->mem_type);
- XE_BUG_ON(!gt);
- XE_BUG_ON(!gt->migrate);
+ XE_BUG_ON(!tile);
+ XE_BUG_ON(!tile->primary_gt.migrate);
trace_xe_bo_move(bo);
xe_device_mem_access_get(xe);
@@ -658,7 +658,7 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
/* Create a new VMAP once kernel BO back in VRAM */
if (!ret && resource_is_vram(new_mem)) {
- void *new_addr = gt_to_tile(gt)->mem.vram.mapping +
+ void *new_addr = tile->mem.vram.mapping +
(new_mem->start << PAGE_SHIFT);
if (XE_WARN_ON(new_mem->start == XE_BO_INVALID_OFFSET)) {
@@ -675,9 +675,9 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
}
} else {
if (move_lacks_source)
- fence = xe_migrate_clear(gt->migrate, bo, new_mem);
+ fence = xe_migrate_clear(tile->primary_gt.migrate, bo, new_mem);
else
- fence = xe_migrate_copy(gt->migrate, bo, old_mem, new_mem);
+ fence = xe_migrate_copy(tile->primary_gt.migrate, bo, old_mem, new_mem);
if (IS_ERR(fence)) {
ret = PTR_ERR(fence);
xe_device_mem_access_put(xe);
@@ -958,7 +958,7 @@ static void xe_ttm_bo_destroy(struct ttm_buffer_object *ttm_bo)
WARN_ON(!list_empty(&bo->vmas));
if (bo->ggtt_node.size)
- xe_ggtt_remove_bo(gt_to_tile(bo->gt)->mem.ggtt, bo);
+ xe_ggtt_remove_bo(bo->tile->mem.ggtt, bo);
if (bo->vm && xe_bo_is_user(bo))
xe_vm_put(bo->vm);
@@ -1080,7 +1080,7 @@ void xe_bo_free(struct xe_bo *bo)
}
struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
- struct xe_gt *gt, struct dma_resv *resv,
+ struct xe_tile *tile, struct dma_resv *resv,
size_t size, enum ttm_bo_type type,
u32 flags)
{
@@ -1093,7 +1093,7 @@ struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
int err;
/* Only kernel objects should set GT */
- XE_BUG_ON(gt && type != ttm_bo_type_kernel);
+ XE_BUG_ON(tile && type != ttm_bo_type_kernel);
if (XE_WARN_ON(!size))
return ERR_PTR(-EINVAL);
@@ -1114,7 +1114,7 @@ struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
alignment = SZ_4K >> PAGE_SHIFT;
}
- bo->gt = gt;
+ bo->tile = tile;
bo->size = size;
bo->flags = flags;
bo->ttm.base.funcs = &xe_gem_object_funcs;
@@ -1196,7 +1196,7 @@ static int __xe_bo_fixed_placement(struct xe_device *xe,
struct xe_bo *
xe_bo_create_locked_range(struct xe_device *xe,
- struct xe_gt *gt, struct xe_vm *vm,
+ struct xe_tile *tile, struct xe_vm *vm,
size_t size, u64 start, u64 end,
enum ttm_bo_type type, u32 flags)
{
@@ -1219,7 +1219,7 @@ xe_bo_create_locked_range(struct xe_device *xe,
}
}
- bo = __xe_bo_create_locked(xe, bo, gt, vm ? &vm->resv : NULL, size,
+ bo = __xe_bo_create_locked(xe, bo, tile, vm ? &vm->resv : NULL, size,
type, flags);
if (IS_ERR(bo))
return bo;
@@ -1229,16 +1229,16 @@ xe_bo_create_locked_range(struct xe_device *xe,
bo->vm = vm;
if (bo->flags & XE_BO_CREATE_GGTT_BIT) {
- if (!gt && flags & XE_BO_CREATE_STOLEN_BIT)
- gt = xe_device_get_gt(xe, 0);
+ if (!tile && flags & XE_BO_CREATE_STOLEN_BIT)
+ tile = xe_device_get_root_tile(xe);
- XE_BUG_ON(!gt);
+ XE_BUG_ON(!tile);
if (flags & XE_BO_FIXED_PLACEMENT_BIT) {
- err = xe_ggtt_insert_bo_at(gt_to_tile(gt)->mem.ggtt, bo,
+ err = xe_ggtt_insert_bo_at(tile->mem.ggtt, bo,
start + bo->size, U64_MAX);
} else {
- err = xe_ggtt_insert_bo(gt_to_tile(gt)->mem.ggtt, bo);
+ err = xe_ggtt_insert_bo(tile->mem.ggtt, bo);
}
if (err)
goto err_unlock_put_bo;
@@ -1252,18 +1252,18 @@ xe_bo_create_locked_range(struct xe_device *xe,
return ERR_PTR(err);
}
-struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_gt *gt,
+struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size,
enum ttm_bo_type type, u32 flags)
{
- return xe_bo_create_locked_range(xe, gt, vm, size, 0, ~0ULL, type, flags);
+ return xe_bo_create_locked_range(xe, tile, vm, size, 0, ~0ULL, type, flags);
}
-struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_gt *gt,
+struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size,
enum ttm_bo_type type, u32 flags)
{
- struct xe_bo *bo = xe_bo_create_locked(xe, gt, vm, size, type, flags);
+ struct xe_bo *bo = xe_bo_create_locked(xe, tile, vm, size, type, flags);
if (!IS_ERR(bo))
xe_bo_unlock_vm_held(bo);
@@ -1271,7 +1271,7 @@ struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_gt *gt,
return bo;
}
-struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_gt *gt,
+struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm,
size_t size, u64 offset,
enum ttm_bo_type type, u32 flags)
@@ -1285,7 +1285,7 @@ struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_gt *gt,
xe_ttm_stolen_cpu_access_needs_ggtt(xe))
flags |= XE_BO_CREATE_GGTT_BIT;
- bo = xe_bo_create_locked_range(xe, gt, vm, size, start, end, type, flags);
+ bo = xe_bo_create_locked_range(xe, tile, vm, size, start, end, type, flags);
if (IS_ERR(bo))
return bo;
@@ -1309,18 +1309,18 @@ struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_gt *gt,
return ERR_PTR(err);
}
-struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_gt *gt,
+struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size,
enum ttm_bo_type type, u32 flags)
{
- return xe_bo_create_pin_map_at(xe, gt, vm, size, ~0ull, type, flags);
+ return xe_bo_create_pin_map_at(xe, tile, vm, size, ~0ull, type, flags);
}
-struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_gt *gt,
+struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,
const void *data, size_t size,
enum ttm_bo_type type, u32 flags)
{
- struct xe_bo *bo = xe_bo_create_pin_map(xe, gt, NULL,
+ struct xe_bo *bo = xe_bo_create_pin_map(xe, tile, NULL,
ALIGN(size, PAGE_SIZE),
type, flags);
if (IS_ERR(bo))
@@ -1949,7 +1949,7 @@ int xe_bo_dumb_create(struct drm_file *file_priv,
page_size);
bo = xe_bo_create(xe, NULL, NULL, args->size, ttm_bo_type_device,
- XE_BO_CREATE_VRAM_IF_DGFX(to_gt(xe)) |
+ XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
XE_BO_CREATE_USER_BIT | XE_BO_SCANOUT_BIT);
if (IS_ERR(bo))
return PTR_ERR(bo);
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index 7a79f3893260..ccb0fae2966e 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -21,8 +21,8 @@
XE_BO_CREATE_VRAM1_BIT)
/* -- */
#define XE_BO_CREATE_STOLEN_BIT BIT(4)
-#define XE_BO_CREATE_VRAM_IF_DGFX(gt) \
- (IS_DGFX(gt_to_xe(gt)) ? XE_BO_CREATE_VRAM0_BIT << gt_to_tile(gt)->id : \
+#define XE_BO_CREATE_VRAM_IF_DGFX(tile) \
+ (IS_DGFX(tile_to_xe(tile)) ? XE_BO_CREATE_VRAM0_BIT << (tile)->id : \
XE_BO_CREATE_SYSTEM_BIT)
#define XE_BO_CREATE_GGTT_BIT BIT(5)
#define XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT BIT(6)
@@ -80,27 +80,27 @@ struct xe_bo *xe_bo_alloc(void);
void xe_bo_free(struct xe_bo *bo);
struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
- struct xe_gt *gt, struct dma_resv *resv,
+ struct xe_tile *tile, struct dma_resv *resv,
size_t size, enum ttm_bo_type type,
u32 flags);
struct xe_bo *
xe_bo_create_locked_range(struct xe_device *xe,
- struct xe_gt *gt, struct xe_vm *vm,
+ struct xe_tile *tile, struct xe_vm *vm,
size_t size, u64 start, u64 end,
enum ttm_bo_type type, u32 flags);
-struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_gt *gt,
+struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size,
enum ttm_bo_type type, u32 flags);
-struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_gt *gt,
+struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size,
enum ttm_bo_type type, u32 flags);
-struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_gt *gt,
+struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size,
enum ttm_bo_type type, u32 flags);
-struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_gt *gt,
+struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size, u64 offset,
enum ttm_bo_type type, u32 flags);
-struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_gt *gt,
+struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,
const void *data, size_t size,
enum ttm_bo_type type, u32 flags);
diff --git a/drivers/gpu/drm/xe/xe_bo_evict.c b/drivers/gpu/drm/xe/xe_bo_evict.c
index a72963c54bf3..9226195bd560 100644
--- a/drivers/gpu/drm/xe/xe_bo_evict.c
+++ b/drivers/gpu/drm/xe/xe_bo_evict.c
@@ -149,7 +149,7 @@ int xe_bo_restore_kernel(struct xe_device *xe)
}
if (bo->flags & XE_BO_CREATE_GGTT_BIT) {
- struct xe_tile *tile = gt_to_tile(bo->gt);
+ struct xe_tile *tile = bo->tile;
mutex_lock(&tile->mem.ggtt->lock);
xe_ggtt_map_bo(tile->mem.ggtt, bo);
diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index 06de3330211d..f6ee920303af 100644
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -29,8 +29,8 @@ struct xe_bo {
u32 flags;
/** @vm: VM this BO is attached to, for extobj this will be NULL */
struct xe_vm *vm;
- /** @gt: GT this BO is attached to (kernel BO only) */
- struct xe_gt *gt;
+ /** @tile: Tile this BO is attached to (kernel BO only) */
+ struct xe_tile *tile;
/** @vmas: List of VMAs for this BO */
struct list_head vmas;
/** @placements: valid placements for this BO */
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index e3fe47c13269..e62ecccad605 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -132,6 +132,13 @@ struct xe_tile {
/** @ggtt: Global graphics translation table */
struct xe_ggtt *ggtt;
+
+ /**
+ * @kernel_bb_pool: Pool from which batchbuffers are allocated.
+ *
+ * Media GT shares a pool with its primary GT.
+ */
+ struct xe_sa_manager *kernel_bb_pool;
} mem;
};
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 52d293d61cc0..b11f22b68bb8 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -149,7 +149,6 @@ static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
int xe_ggtt_init(struct xe_ggtt *ggtt)
{
struct xe_device *xe = tile_to_xe(ggtt->tile);
- struct xe_gt *gt = &ggtt->tile->primary_gt;
unsigned int flags;
int err;
@@ -162,9 +161,9 @@ int xe_ggtt_init(struct xe_ggtt *ggtt)
if (ggtt->flags & XE_GGTT_FLAGS_64K)
flags |= XE_BO_CREATE_SYSTEM_BIT;
else
- flags |= XE_BO_CREATE_VRAM_IF_DGFX(gt);
+ flags |= XE_BO_CREATE_VRAM_IF_DGFX(ggtt->tile);
- ggtt->scratch = xe_bo_create_pin_map(xe, gt, NULL, XE_PAGE_SIZE,
+ ggtt->scratch = xe_bo_create_pin_map(xe, ggtt->tile, NULL, XE_PAGE_SIZE,
ttm_bo_type_kernel,
flags);
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index ac6073a7fb59..92407776f5f0 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -96,7 +96,7 @@ static int emit_nop_job(struct xe_gt *gt, struct xe_engine *e)
if (IS_ERR(bb))
return PTR_ERR(bb);
- batch_ofs = xe_bo_ggtt_addr(gt->kernel_bb_pool->bo);
+ batch_ofs = xe_bo_ggtt_addr(gt_to_tile(gt)->mem.kernel_bb_pool->bo);
job = xe_bb_create_wa_job(e, bb, batch_ofs);
if (IS_ERR(job)) {
xe_bb_free(bb, NULL);
@@ -145,7 +145,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_engine *e)
}
}
- batch_ofs = xe_bo_ggtt_addr(gt->kernel_bb_pool->bo);
+ batch_ofs = xe_bo_ggtt_addr(gt_to_tile(gt)->mem.kernel_bb_pool->bo);
job = xe_bb_create_wa_job(e, bb, batch_ofs);
if (IS_ERR(job)) {
xe_bb_free(bb, NULL);
@@ -365,31 +365,16 @@ static int all_fw_domain_init(struct xe_gt *gt)
goto err_force_wake;
if (!xe_gt_is_media_type(gt)) {
- gt->kernel_bb_pool = xe_sa_bo_manager_init(gt, SZ_1M, 16);
- if (IS_ERR(gt->kernel_bb_pool)) {
- err = PTR_ERR(gt->kernel_bb_pool);
- goto err_force_wake;
- }
-
/*
* USM has its only SA pool to non-block behind user operations
*/
if (gt_to_xe(gt)->info.supports_usm) {
- gt->usm.bb_pool = xe_sa_bo_manager_init(gt, SZ_1M, 16);
+ gt->usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt), SZ_1M, 16);
if (IS_ERR(gt->usm.bb_pool)) {
err = PTR_ERR(gt->usm.bb_pool);
goto err_force_wake;
}
}
- } else {
- struct xe_gt *full_gt = xe_find_full_gt(gt);
-
- /*
- * Media GT's kernel_bb_pool is only used while recording the
- * default context during GT init. The USM pool should never
- * be needed on the media GT.
- */
- gt->kernel_bb_pool = full_gt->kernel_bb_pool;
}
if (!xe_gt_is_media_type(gt)) {
diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
index a0f633109124..c9a2d5c565b0 100644
--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
@@ -63,11 +63,11 @@ static int force_reset(struct seq_file *m, void *data)
static int sa_info(struct seq_file *m, void *data)
{
- struct xe_gt *gt = node_to_gt(m->private);
+ struct xe_tile *tile = gt_to_tile(node_to_gt(m->private));
struct drm_printer p = drm_seq_file_printer(m);
- drm_suballoc_dump_debug_info(>->kernel_bb_pool->base, &p,
- gt->kernel_bb_pool->gpu_addr);
+ drm_suballoc_dump_debug_info(&tile->mem.kernel_bb_pool->base, &p,
+ tile->mem.kernel_bb_pool->gpu_addr);
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c
index f4f3d95ae6b1..1c2b23ae89cf 100644
--- a/drivers/gpu/drm/xe/xe_gt_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c
@@ -71,8 +71,8 @@ static bool access_is_atomic(enum access_type access_type)
static bool vma_is_valid(struct xe_gt *gt, struct xe_vma *vma)
{
- return BIT(gt->info.id) & vma->gt_present &&
- !(BIT(gt->info.id) & vma->usm.gt_invalidated);
+ return BIT(gt_to_tile(gt)->id) & vma->tile_present &&
+ !(BIT(gt->info.id) & vma->usm.tile_invalidated);
}
static bool vma_matches(struct xe_vma *vma, struct xe_vma *lookup)
@@ -208,8 +208,8 @@ static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf)
/* Bind VMA only to the GT that has faulted */
trace_xe_vma_pf_bind(vma);
- fence = __xe_pt_bind_vma(gt, vma, xe_gt_migrate_engine(gt), NULL, 0,
- vma->gt_present & BIT(gt->info.id));
+ fence = __xe_pt_bind_vma(tile, vma, xe_gt_migrate_engine(gt), NULL, 0,
+ vma->tile_present & BIT(tile->id));
if (IS_ERR(fence)) {
ret = PTR_ERR(fence);
goto unlock_dma_resv;
@@ -225,7 +225,7 @@ static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf)
if (xe_vma_is_userptr(vma))
ret = xe_vma_userptr_check_repin(vma);
- vma->usm.gt_invalidated &= ~BIT(gt->info.id);
+ vma->usm.tile_invalidated &= ~BIT(gt_to_tile(gt)->id);
unlock_dma_resv:
if (only_needs_bo_lock(bo))
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index fcea0dc150ed..ecca990183d0 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -278,13 +278,6 @@ struct xe_gt {
/** @hw_engines: hardware engines on the GT */
struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES];
- /**
- * @kernel_bb_pool: Pool from which batchbuffers are allocated.
- *
- * Media GT shares a pool with its primary GT.
- */
- struct xe_sa_manager *kernel_bb_pool;
-
/** @migrate: Migration helper for vram blits and clearing */
struct xe_migrate *migrate;
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 6d550d746909..dd69d097b920 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -273,16 +273,17 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
{
struct xe_device *xe = ads_to_xe(ads);
struct xe_gt *gt = ads_to_gt(ads);
+ struct xe_tile *tile = gt_to_tile(gt);
struct xe_bo *bo;
int err;
ads->golden_lrc_size = calculate_golden_lrc_size(ads);
ads->regset_size = calculate_regset_size(gt);
- bo = xe_bo_create_pin_map(xe, gt, NULL, guc_ads_size(ads) +
+ bo = xe_bo_create_pin_map(xe, tile, NULL, guc_ads_size(ads) +
MAX_GOLDEN_LRC_SIZE,
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(bo))
return PTR_ERR(bo);
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index e8c2edb1359d..d7993bcf6be0 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -130,6 +130,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
{
struct xe_device *xe = ct_to_xe(ct);
struct xe_gt *gt = ct_to_gt(ct);
+ struct xe_tile *tile = gt_to_tile(gt);
struct xe_bo *bo;
int err;
@@ -145,9 +146,9 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
primelockdep(ct);
- bo = xe_bo_create_pin_map(xe, gt, NULL, guc_ct_size(),
+ bo = xe_bo_create_pin_map(xe, tile, NULL, guc_ct_size(),
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(bo))
return PTR_ERR(bo);
diff --git a/drivers/gpu/drm/xe/xe_guc_hwconfig.c b/drivers/gpu/drm/xe/xe_guc_hwconfig.c
index a6982f323ed1..c8f875e970ab 100644
--- a/drivers/gpu/drm/xe/xe_guc_hwconfig.c
+++ b/drivers/gpu/drm/xe/xe_guc_hwconfig.c
@@ -70,6 +70,7 @@ int xe_guc_hwconfig_init(struct xe_guc *guc)
{
struct xe_device *xe = guc_to_xe(guc);
struct xe_gt *gt = guc_to_gt(guc);
+ struct xe_tile *tile = gt_to_tile(gt);
struct xe_bo *bo;
u32 size;
int err;
@@ -94,9 +95,9 @@ int xe_guc_hwconfig_init(struct xe_guc *guc)
if (!size)
return -EINVAL;
- bo = xe_bo_create_pin_map(xe, gt, NULL, PAGE_ALIGN(size),
+ bo = xe_bo_create_pin_map(xe, tile, NULL, PAGE_ALIGN(size),
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(bo))
return PTR_ERR(bo);
diff --git a/drivers/gpu/drm/xe/xe_guc_log.c b/drivers/gpu/drm/xe/xe_guc_log.c
index 9a7b5d5906c1..403aaafcaba6 100644
--- a/drivers/gpu/drm/xe/xe_guc_log.c
+++ b/drivers/gpu/drm/xe/xe_guc_log.c
@@ -87,13 +87,13 @@ static void guc_log_fini(struct drm_device *drm, void *arg)
int xe_guc_log_init(struct xe_guc_log *log)
{
struct xe_device *xe = log_to_xe(log);
- struct xe_gt *gt = log_to_gt(log);
+ struct xe_tile *tile = gt_to_tile(log_to_gt(log));
struct xe_bo *bo;
int err;
- bo = xe_bo_create_pin_map(xe, gt, NULL, guc_log_size(),
+ bo = xe_bo_create_pin_map(xe, tile, NULL, guc_log_size(),
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(bo))
return PTR_ERR(bo);
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index e799faa1c6b8..67faa9ee0006 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -888,6 +888,7 @@ static void pc_fini(struct drm_device *drm, void *arg)
int xe_guc_pc_init(struct xe_guc_pc *pc)
{
struct xe_gt *gt = pc_to_gt(pc);
+ struct xe_tile *tile = gt_to_tile(gt);
struct xe_device *xe = gt_to_xe(gt);
struct xe_bo *bo;
u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
@@ -895,9 +896,9 @@ int xe_guc_pc_init(struct xe_guc_pc *pc)
mutex_init(&pc->freq_lock);
- bo = xe_bo_create_pin_map(xe, gt, NULL, size,
+ bo = xe_bo_create_pin_map(xe, tile, NULL, size,
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(bo))
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 71ac4defb947..ab25513b753c 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -371,6 +371,7 @@ static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,
enum xe_hw_engine_id id)
{
struct xe_device *xe = gt_to_xe(gt);
+ struct xe_tile *tile = gt_to_tile(gt);
int err;
XE_BUG_ON(id >= ARRAY_SIZE(engine_infos) || !engine_infos[id].name);
@@ -379,8 +380,8 @@ static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,
xe_reg_sr_apply_mmio(&hwe->reg_sr, gt);
xe_reg_sr_apply_whitelist(&hwe->reg_whitelist, hwe->mmio_base, gt);
- hwe->hwsp = xe_bo_create_pin_map(xe, gt, NULL, SZ_4K, ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+ hwe->hwsp = xe_bo_create_pin_map(xe, tile, NULL, SZ_4K, ttm_bo_type_kernel,
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(hwe->hwsp)) {
err = PTR_ERR(hwe->hwsp);
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index ae605e7805de..8f25a38f36a5 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -592,7 +592,7 @@ static void *empty_lrc_data(struct xe_hw_engine *hwe)
static void xe_lrc_set_ppgtt(struct xe_lrc *lrc, struct xe_vm *vm)
{
- u64 desc = xe_vm_pdp4_descriptor(vm, lrc->full_gt);
+ u64 desc = xe_vm_pdp4_descriptor(vm, lrc->tile);
xe_lrc_write_ctx_reg(lrc, CTX_PDP0_UDW, upper_32_bits(desc));
xe_lrc_write_ctx_reg(lrc, CTX_PDP0_LDW, lower_32_bits(desc));
@@ -607,6 +607,7 @@ int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
struct xe_engine *e, struct xe_vm *vm, u32 ring_size)
{
struct xe_gt *gt = hwe->gt;
+ struct xe_tile *tile = gt_to_tile(gt);
struct xe_device *xe = gt_to_xe(gt);
struct iosys_map map;
void *init_data = NULL;
@@ -619,19 +620,15 @@ int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
* FIXME: Perma-pinning LRC as we don't yet support moving GGTT address
* via VM bind calls.
*/
- lrc->bo = xe_bo_create_pin_map(xe, hwe->gt, vm,
+ lrc->bo = xe_bo_create_pin_map(xe, tile, vm,
ring_size + xe_lrc_size(xe, hwe->class),
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(hwe->gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(lrc->bo))
return PTR_ERR(lrc->bo);
- if (xe_gt_is_media_type(hwe->gt))
- lrc->full_gt = xe_find_full_gt(hwe->gt);
- else
- lrc->full_gt = hwe->gt;
-
+ lrc->tile = gt_to_tile(hwe->gt);
lrc->ring.size = ring_size;
lrc->ring.tail = 0;
diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h b/drivers/gpu/drm/xe/xe_lrc_types.h
index 8fe08535873d..78220336062c 100644
--- a/drivers/gpu/drm/xe/xe_lrc_types.h
+++ b/drivers/gpu/drm/xe/xe_lrc_types.h
@@ -20,8 +20,8 @@ struct xe_lrc {
*/
struct xe_bo *bo;
- /** @full_gt: full GT which this LRC belongs to */
- struct xe_gt *full_gt;
+ /** @tile: tile which this LRC belongs to */
+ struct xe_tile *tile;
/** @flags: LRC flags */
u32 flags;
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index f40f47ccb76f..031a0bde5585 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -129,6 +129,7 @@ static u64 xe_migrate_vram_ofs(u64 addr)
static int xe_migrate_create_cleared_bo(struct xe_migrate *m, struct xe_vm *vm)
{
struct xe_gt *gt = m->gt;
+ struct xe_tile *tile = gt_to_tile(gt);
struct xe_device *xe = vm->xe;
size_t cleared_size;
u64 vram_addr;
@@ -139,9 +140,9 @@ static int xe_migrate_create_cleared_bo(struct xe_migrate *m, struct xe_vm *vm)
cleared_size = xe_device_ccs_bytes(xe, MAX_PREEMPTDISABLE_TRANSFER);
cleared_size = PAGE_ALIGN(cleared_size);
- m->cleared_bo = xe_bo_create_pin_map(xe, gt, vm, cleared_size,
+ m->cleared_bo = xe_bo_create_pin_map(xe, tile, vm, cleared_size,
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_PINNED_BIT);
if (IS_ERR(m->cleared_bo))
return PTR_ERR(m->cleared_bo);
@@ -161,7 +162,8 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
u32 map_ofs, level, i;
struct xe_device *xe = gt_to_xe(m->gt);
- struct xe_bo *bo, *batch = gt->kernel_bb_pool->bo;
+ struct xe_tile *tile = gt_to_tile(m->gt);
+ struct xe_bo *bo, *batch = tile->mem.kernel_bb_pool->bo;
u64 entry;
int ret;
@@ -175,10 +177,10 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
/* Need to be sure everything fits in the first PT, or create more */
XE_BUG_ON(m->batch_base_ofs + batch->size >= SZ_2M);
- bo = xe_bo_create_pin_map(vm->xe, m->gt, vm,
+ bo = xe_bo_create_pin_map(vm->xe, tile, vm,
num_entries * XE_PAGE_SIZE,
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(m->gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_PINNED_BIT);
if (IS_ERR(bo))
return PTR_ERR(bo);
@@ -964,7 +966,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
return fence;
}
-static void write_pgtable(struct xe_gt *gt, struct xe_bb *bb, u64 ppgtt_ofs,
+static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs,
const struct xe_vm_pgtable_update *update,
struct xe_migrate_pt_update *pt_update)
{
@@ -1003,7 +1005,7 @@ static void write_pgtable(struct xe_gt *gt, struct xe_bb *bb, u64 ppgtt_ofs,
(chunk * 2 + 1);
bb->cs[bb->len++] = lower_32_bits(addr);
bb->cs[bb->len++] = upper_32_bits(addr);
- ops->populate(pt_update, gt, NULL, bb->cs + bb->len, ofs, chunk,
+ ops->populate(pt_update, tile, NULL, bb->cs + bb->len, ofs, chunk,
update);
bb->len += chunk * 2;
@@ -1061,7 +1063,7 @@ xe_migrate_update_pgtables_cpu(struct xe_migrate *m,
for (i = 0; i < num_updates; i++) {
const struct xe_vm_pgtable_update *update = &updates[i];
- ops->populate(pt_update, m->gt, &update->pt_bo->vmap, NULL,
+ ops->populate(pt_update, gt_to_tile(m->gt), &update->pt_bo->vmap, NULL,
update->ofs, update->qwords, update);
}
@@ -1129,6 +1131,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
{
const struct xe_migrate_pt_update_ops *ops = pt_update->ops;
struct xe_gt *gt = m->gt;
+ struct xe_tile *tile = gt_to_tile(m->gt);
struct xe_device *xe = gt_to_xe(gt);
struct xe_sched_job *job;
struct dma_fence *fence;
@@ -1223,7 +1226,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
addr = xe_migrate_vm_addr(ppgtt_ofs, 0) +
(page_ofs / sizeof(u64)) * XE_PAGE_SIZE;
for (i = 0; i < num_updates; i++)
- write_pgtable(m->gt, bb, addr + i * XE_PAGE_SIZE,
+ write_pgtable(tile, bb, addr + i * XE_PAGE_SIZE,
&updates[i], pt_update);
} else {
/* phys pages, no preamble required */
@@ -1233,7 +1236,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
/* Preemption is enabled again by the ring ops. */
emit_arb_clear(bb);
for (i = 0; i < num_updates; i++)
- write_pgtable(m->gt, bb, 0, &updates[i], pt_update);
+ write_pgtable(tile, bb, 0, &updates[i], pt_update);
}
if (!eng)
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index 1ff6e0a90de5..e07b2a8845c0 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -19,6 +19,7 @@ struct xe_migrate;
struct xe_migrate_pt_update;
struct xe_sync_entry;
struct xe_pt;
+struct xe_tile;
struct xe_vm;
struct xe_vm_pgtable_update;
struct xe_vma;
@@ -31,7 +32,7 @@ struct xe_migrate_pt_update_ops {
/**
* @populate: Populate a command buffer or page-table with ptes.
* @pt_update: Embeddable callback argument.
- * @gt: The gt for the current operation.
+ * @tile: The tile for the current operation.
* @map: struct iosys_map into the memory to be populated.
* @pos: If @map is NULL, map into the memory to be populated.
* @ofs: qword offset into @map, unused if @map is NULL.
@@ -43,7 +44,7 @@ struct xe_migrate_pt_update_ops {
* page-tables with PTEs.
*/
void (*populate)(struct xe_migrate_pt_update *pt_update,
- struct xe_gt *gt, struct iosys_map *map,
+ struct xe_tile *tile, struct iosys_map *map,
void *pos, u32 ofs, u32 num_qwords,
const struct xe_vm_pgtable_update *update);
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index ad42a21c0e22..ea68e6b38133 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -165,12 +165,10 @@ u64 gen8_pte_encode(struct xe_vma *vma, struct xe_bo *bo,
return __gen8_pte_encode(pte, cache, flags, pt_level);
}
-static u64 __xe_pt_empty_pte(struct xe_gt *gt, struct xe_vm *vm,
+static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm,
unsigned int level)
{
- u8 id = gt->info.id;
-
- XE_BUG_ON(xe_gt_is_media_type(gt));
+ u8 id = tile->id;
if (!vm->scratch_bo[id])
return 0;
@@ -189,7 +187,7 @@ static u64 __xe_pt_empty_pte(struct xe_gt *gt, struct xe_vm *vm,
/**
* xe_pt_create() - Create a page-table.
* @vm: The vm to create for.
- * @gt: The gt to create for.
+ * @tile: The tile to create for.
* @level: The page-table level.
*
* Allocate and initialize a single struct xe_pt metadata structure. Also
@@ -201,7 +199,7 @@ static u64 __xe_pt_empty_pte(struct xe_gt *gt, struct xe_vm *vm,
* Return: A valid struct xe_pt pointer on success, Pointer error code on
* error.
*/
-struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_gt *gt,
+struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile,
unsigned int level)
{
struct xe_pt *pt;
@@ -215,9 +213,9 @@ struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_gt *gt,
if (!pt)
return ERR_PTR(-ENOMEM);
- bo = xe_bo_create_pin_map(vm->xe, gt, vm, SZ_4K,
+ bo = xe_bo_create_pin_map(vm->xe, tile, vm, SZ_4K,
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT |
XE_BO_CREATE_PINNED_BIT);
if (IS_ERR(bo)) {
@@ -240,30 +238,28 @@ struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_gt *gt,
/**
* xe_pt_populate_empty() - Populate a page-table bo with scratch- or zero
* entries.
- * @gt: The gt the scratch pagetable of which to use.
+ * @tile: The tile the scratch pagetable of which to use.
* @vm: The vm we populate for.
* @pt: The pagetable the bo of which to initialize.
*
- * Populate the page-table bo of @pt with entries pointing into the gt's
+ * Populate the page-table bo of @pt with entries pointing into the tile's
* scratch page-table tree if any. Otherwise populate with zeros.
*/
-void xe_pt_populate_empty(struct xe_gt *gt, struct xe_vm *vm,
+void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm,
struct xe_pt *pt)
{
struct iosys_map *map = &pt->bo->vmap;
u64 empty;
int i;
- XE_BUG_ON(xe_gt_is_media_type(gt));
-
- if (!vm->scratch_bo[gt->info.id]) {
+ if (!vm->scratch_bo[tile->id]) {
/*
* FIXME: Some memory is allocated already allocated to zero?
* Find out which memory that is and avoid this memset...
*/
xe_map_memset(vm->xe, map, 0, 0, SZ_4K);
} else {
- empty = __xe_pt_empty_pte(gt, vm, pt->level);
+ empty = __xe_pt_empty_pte(tile, vm, pt->level);
for (i = 0; i < XE_PDES; i++)
xe_pt_write(vm->xe, map, i, empty);
}
@@ -317,9 +313,9 @@ void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred)
/**
* xe_pt_create_scratch() - Setup a scratch memory pagetable tree for the
- * given gt and vm.
+ * given tile and vm.
* @xe: xe device.
- * @gt: gt to set up for.
+ * @tile: tile to set up for.
* @vm: vm to set up for.
*
* Sets up a pagetable tree with one page-table per level and a single
@@ -328,10 +324,10 @@ void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred)
*
* Return: 0 on success, negative error code on error.
*/
-int xe_pt_create_scratch(struct xe_device *xe, struct xe_gt *gt,
+int xe_pt_create_scratch(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm)
{
- u8 id = gt->info.id;
+ u8 id = tile->id;
unsigned int flags;
int i;
@@ -344,9 +340,9 @@ int xe_pt_create_scratch(struct xe_device *xe, struct xe_gt *gt,
if (vm->flags & XE_VM_FLAGS_64K)
flags |= XE_BO_CREATE_SYSTEM_BIT;
else
- flags |= XE_BO_CREATE_VRAM_IF_DGFX(gt);
+ flags |= XE_BO_CREATE_VRAM_IF_DGFX(tile);
- vm->scratch_bo[id] = xe_bo_create_pin_map(xe, gt, vm, SZ_4K,
+ vm->scratch_bo[id] = xe_bo_create_pin_map(xe, tile, vm, SZ_4K,
ttm_bo_type_kernel,
flags);
if (IS_ERR(vm->scratch_bo[id]))
@@ -356,11 +352,11 @@ int xe_pt_create_scratch(struct xe_device *xe, struct xe_gt *gt,
vm->scratch_bo[id]->size);
for (i = 0; i < vm->pt_root[id]->level; i++) {
- vm->scratch_pt[id][i] = xe_pt_create(vm, gt, i);
+ vm->scratch_pt[id][i] = xe_pt_create(vm, tile, i);
if (IS_ERR(vm->scratch_pt[id][i]))
return PTR_ERR(vm->scratch_pt[id][i]);
- xe_pt_populate_empty(gt, vm, vm->scratch_pt[id][i]);
+ xe_pt_populate_empty(tile, vm, vm->scratch_pt[id][i]);
}
return 0;
@@ -409,8 +405,8 @@ struct xe_pt_stage_bind_walk {
/* Input parameters for the walk */
/** @vm: The vm we're building for. */
struct xe_vm *vm;
- /** @gt: The gt we're building for. */
- struct xe_gt *gt;
+ /** @tile: The tile we're building for. */
+ struct xe_tile *tile;
/** @cache: Desired cache level for the ptes */
enum xe_cache_level cache;
/** @default_pte: PTE flag only template. No address is associated */
@@ -678,7 +674,7 @@ xe_pt_stage_bind_entry(struct xe_ptw *parent, pgoff_t offset,
if (covers || !*child) {
u64 flags = 0;
- xe_child = xe_pt_create(xe_walk->vm, xe_walk->gt, level - 1);
+ xe_child = xe_pt_create(xe_walk->vm, xe_walk->tile, level - 1);
if (IS_ERR(xe_child))
return PTR_ERR(xe_child);
@@ -686,7 +682,7 @@ xe_pt_stage_bind_entry(struct xe_ptw *parent, pgoff_t offset,
round_down(addr, 1ull << walk->shifts[level]));
if (!covers)
- xe_pt_populate_empty(xe_walk->gt, xe_walk->vm, xe_child);
+ xe_pt_populate_empty(xe_walk->tile, xe_walk->vm, xe_child);
*child = &xe_child->base;
@@ -695,7 +691,7 @@ xe_pt_stage_bind_entry(struct xe_ptw *parent, pgoff_t offset,
* TODO: Suballocate the pt bo to avoid wasting a lot of
* memory.
*/
- if (GRAPHICS_VERx100(gt_to_xe(xe_walk->gt)) >= 1250 && level == 1 &&
+ if (GRAPHICS_VERx100(tile_to_xe(xe_walk->tile)) >= 1250 && level == 1 &&
covers && xe_pt_scan_64K(addr, next, xe_walk)) {
walk->shifts = xe_compact_pt_shifts;
flags |= XE_PDE_64K;
@@ -718,7 +714,7 @@ static const struct xe_pt_walk_ops xe_pt_stage_bind_ops = {
/**
* xe_pt_stage_bind() - Build a disconnected page-table tree for a given address
* range.
- * @gt: The gt we're building for.
+ * @tile: The tile we're building for.
* @vma: The vma indicating the address range.
* @entries: Storage for the update entries used for connecting the tree to
* the main tree at commit time.
@@ -734,7 +730,7 @@ static const struct xe_pt_walk_ops xe_pt_stage_bind_ops = {
* Return 0 on success, negative error code on error.
*/
static int
-xe_pt_stage_bind(struct xe_gt *gt, struct xe_vma *vma,
+xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
struct xe_vm_pgtable_update *entries, u32 *num_entries)
{
struct xe_bo *bo = vma->bo;
@@ -747,14 +743,14 @@ xe_pt_stage_bind(struct xe_gt *gt, struct xe_vma *vma,
.max_level = XE_PT_HIGHEST_LEVEL,
},
.vm = vma->vm,
- .gt = gt,
+ .tile = tile,
.curs = &curs,
.va_curs_start = vma->start,
.pte_flags = vma->pte_flags,
.wupd.entries = entries,
.needs_64K = (vma->vm->flags & XE_VM_FLAGS_64K) && is_vram,
};
- struct xe_pt *pt = vma->vm->pt_root[gt->info.id];
+ struct xe_pt *pt = vma->vm->pt_root[tile->id];
int ret;
if (is_vram) {
@@ -764,7 +760,7 @@ xe_pt_stage_bind(struct xe_gt *gt, struct xe_vma *vma,
if (vma && vma->use_atomic_access_pte_bit)
xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
xe_walk.dma_offset = bo_tile->mem.vram.io_start -
- gt_to_xe(gt)->mem.vram.io_start;
+ tile_to_xe(tile)->mem.vram.io_start;
xe_walk.cache = XE_CACHE_WB;
} else {
if (!xe_vma_is_userptr(vma) && bo->flags & XE_BO_SCANOUT_BIT)
@@ -851,8 +847,8 @@ struct xe_pt_zap_ptes_walk {
struct xe_pt_walk base;
/* Input parameters for the walk */
- /** @gt: The gt we're building for */
- struct xe_gt *gt;
+ /** @tile: The tile we're building for */
+ struct xe_tile *tile;
/* Output */
/** @needs_invalidate: Whether we need to invalidate TLB*/
@@ -880,7 +876,7 @@ static int xe_pt_zap_ptes_entry(struct xe_ptw *parent, pgoff_t offset,
*/
if (xe_pt_nonshared_offsets(addr, next, --level, walk, action, &offset,
&end_offset)) {
- xe_map_memset(gt_to_xe(xe_walk->gt), &xe_child->bo->vmap,
+ xe_map_memset(tile_to_xe(xe_walk->tile), &xe_child->bo->vmap,
offset * sizeof(u64), 0,
(end_offset - offset) * sizeof(u64));
xe_walk->needs_invalidate = true;
@@ -895,7 +891,7 @@ static const struct xe_pt_walk_ops xe_pt_zap_ptes_ops = {
/**
* xe_pt_zap_ptes() - Zap (zero) gpu ptes of an address range
- * @gt: The gt we're zapping for.
+ * @tile: The tile we're zapping for.
* @vma: GPU VMA detailing address range.
*
* Eviction and Userptr invalidation needs to be able to zap the
@@ -909,7 +905,7 @@ static const struct xe_pt_walk_ops xe_pt_zap_ptes_ops = {
* Return: Whether ptes were actually updated and a TLB invalidation is
* required.
*/
-bool xe_pt_zap_ptes(struct xe_gt *gt, struct xe_vma *vma)
+bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma)
{
struct xe_pt_zap_ptes_walk xe_walk = {
.base = {
@@ -917,11 +913,11 @@ bool xe_pt_zap_ptes(struct xe_gt *gt, struct xe_vma *vma)
.shifts = xe_normal_pt_shifts,
.max_level = XE_PT_HIGHEST_LEVEL,
},
- .gt = gt,
+ .tile = tile,
};
- struct xe_pt *pt = vma->vm->pt_root[gt->info.id];
+ struct xe_pt *pt = vma->vm->pt_root[tile->id];
- if (!(vma->gt_present & BIT(gt->info.id)))
+ if (!(vma->tile_present & BIT(tile->id)))
return false;
(void)xe_pt_walk_shared(&pt->base, pt->level, vma->start, vma->end + 1,
@@ -931,7 +927,7 @@ bool xe_pt_zap_ptes(struct xe_gt *gt, struct xe_vma *vma)
}
static void
-xe_vm_populate_pgtable(struct xe_migrate_pt_update *pt_update, struct xe_gt *gt,
+xe_vm_populate_pgtable(struct xe_migrate_pt_update *pt_update, struct xe_tile *tile,
struct iosys_map *map, void *data,
u32 qword_ofs, u32 num_qwords,
const struct xe_vm_pgtable_update *update)
@@ -940,11 +936,9 @@ xe_vm_populate_pgtable(struct xe_migrate_pt_update *pt_update, struct xe_gt *gt,
u64 *ptr = data;
u32 i;
- XE_BUG_ON(xe_gt_is_media_type(gt));
-
for (i = 0; i < num_qwords; i++) {
if (map)
- xe_map_wr(gt_to_xe(gt), map, (qword_ofs + i) *
+ xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *
sizeof(u64), u64, ptes[i].pte);
else
ptr[i] = ptes[i].pte;
@@ -1018,14 +1012,14 @@ static void xe_pt_commit_bind(struct xe_vma *vma,
}
static int
-xe_pt_prepare_bind(struct xe_gt *gt, struct xe_vma *vma,
+xe_pt_prepare_bind(struct xe_tile *tile, struct xe_vma *vma,
struct xe_vm_pgtable_update *entries, u32 *num_entries,
bool rebind)
{
int err;
*num_entries = 0;
- err = xe_pt_stage_bind(gt, vma, entries, num_entries);
+ err = xe_pt_stage_bind(tile, vma, entries, num_entries);
if (!err)
BUG_ON(!*num_entries);
else /* abort! */
@@ -1252,7 +1246,7 @@ static int invalidation_fence_init(struct xe_gt *gt,
/**
* __xe_pt_bind_vma() - Build and connect a page-table tree for the vma
* address range.
- * @gt: The gt to bind for.
+ * @tile: The tile to bind for.
* @vma: The vma to bind.
* @e: The engine with which to do pipelined page-table updates.
* @syncs: Entries to sync on before binding the built tree to the live vm tree.
@@ -1272,7 +1266,7 @@ static int invalidation_fence_init(struct xe_gt *gt,
* on success, an error pointer on error.
*/
struct dma_fence *
-__xe_pt_bind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
+__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e,
struct xe_sync_entry *syncs, u32 num_syncs,
bool rebind)
{
@@ -1293,18 +1287,17 @@ __xe_pt_bind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
bind_pt_update.locked = false;
xe_bo_assert_held(vma->bo);
xe_vm_assert_held(vm);
- XE_BUG_ON(xe_gt_is_media_type(gt));
vm_dbg(&vma->vm->xe->drm,
"Preparing bind, with range [%llx...%llx) engine %p.\n",
vma->start, vma->end, e);
- err = xe_pt_prepare_bind(gt, vma, entries, &num_entries, rebind);
+ err = xe_pt_prepare_bind(tile, vma, entries, &num_entries, rebind);
if (err)
goto err;
XE_BUG_ON(num_entries > ARRAY_SIZE(entries));
- xe_vm_dbg_print_entries(gt_to_xe(gt), entries, num_entries);
+ xe_vm_dbg_print_entries(tile_to_xe(tile), entries, num_entries);
if (rebind && !xe_vm_no_dma_fences(vma->vm)) {
ifence = kzalloc(sizeof(*ifence), GFP_KERNEL);
@@ -1312,9 +1305,9 @@ __xe_pt_bind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
return ERR_PTR(-ENOMEM);
}
- fence = xe_migrate_update_pgtables(gt->migrate,
+ fence = xe_migrate_update_pgtables(tile->primary_gt.migrate,
vm, vma->bo,
- e ? e : vm->eng[gt->info.id],
+ e ? e : vm->eng[tile->id],
entries, num_entries,
syncs, num_syncs,
&bind_pt_update.base);
@@ -1323,7 +1316,7 @@ __xe_pt_bind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
/* TLB invalidation must be done before signaling rebind */
if (rebind && !xe_vm_no_dma_fences(vma->vm)) {
- int err = invalidation_fence_init(gt, ifence, fence,
+ int err = invalidation_fence_init(&tile->primary_gt, ifence, fence,
vma);
if (err) {
dma_fence_put(fence);
@@ -1346,7 +1339,7 @@ __xe_pt_bind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
bind_pt_update.locked ? &deferred : NULL);
/* This vma is live (again?) now */
- vma->gt_present |= BIT(gt->info.id);
+ vma->tile_present |= BIT(tile->id);
if (bind_pt_update.locked) {
vma->userptr.initial_bind = true;
@@ -1375,8 +1368,8 @@ struct xe_pt_stage_unbind_walk {
struct xe_pt_walk base;
/* Input parameters for the walk */
- /** @gt: The gt we're unbinding from. */
- struct xe_gt *gt;
+ /** @tile: The tile we're unbinding from. */
+ struct xe_tile *tile;
/**
* @modified_start: Walk range start, modified to include any
@@ -1481,7 +1474,7 @@ static const struct xe_pt_walk_ops xe_pt_stage_unbind_ops = {
/**
* xe_pt_stage_unbind() - Build page-table update structures for an unbind
* operation
- * @gt: The gt we're unbinding for.
+ * @tile: The tile we're unbinding for.
* @vma: The vma we're unbinding.
* @entries: Caller-provided storage for the update structures.
*
@@ -1492,7 +1485,7 @@ static const struct xe_pt_walk_ops xe_pt_stage_unbind_ops = {
*
* Return: The number of entries used.
*/
-static unsigned int xe_pt_stage_unbind(struct xe_gt *gt, struct xe_vma *vma,
+static unsigned int xe_pt_stage_unbind(struct xe_tile *tile, struct xe_vma *vma,
struct xe_vm_pgtable_update *entries)
{
struct xe_pt_stage_unbind_walk xe_walk = {
@@ -1501,12 +1494,12 @@ static unsigned int xe_pt_stage_unbind(struct xe_gt *gt, struct xe_vma *vma,
.shifts = xe_normal_pt_shifts,
.max_level = XE_PT_HIGHEST_LEVEL,
},
- .gt = gt,
+ .tile = tile,
.modified_start = vma->start,
.modified_end = vma->end + 1,
.wupd.entries = entries,
};
- struct xe_pt *pt = vma->vm->pt_root[gt->info.id];
+ struct xe_pt *pt = vma->vm->pt_root[tile->id];
(void)xe_pt_walk_shared(&pt->base, pt->level, vma->start, vma->end + 1,
&xe_walk.base);
@@ -1516,19 +1509,17 @@ static unsigned int xe_pt_stage_unbind(struct xe_gt *gt, struct xe_vma *vma,
static void
xe_migrate_clear_pgtable_callback(struct xe_migrate_pt_update *pt_update,
- struct xe_gt *gt, struct iosys_map *map,
+ struct xe_tile *tile, struct iosys_map *map,
void *ptr, u32 qword_ofs, u32 num_qwords,
const struct xe_vm_pgtable_update *update)
{
struct xe_vma *vma = pt_update->vma;
- u64 empty = __xe_pt_empty_pte(gt, vma->vm, update->pt->level);
+ u64 empty = __xe_pt_empty_pte(tile, vma->vm, update->pt->level);
int i;
- XE_BUG_ON(xe_gt_is_media_type(gt));
-
if (map && map->is_iomem)
for (i = 0; i < num_qwords; ++i)
- xe_map_wr(gt_to_xe(gt), map, (qword_ofs + i) *
+ xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *
sizeof(u64), u64, empty);
else if (map)
memset64(map->vaddr + qword_ofs * sizeof(u64), empty,
@@ -1579,7 +1570,7 @@ static const struct xe_migrate_pt_update_ops userptr_unbind_ops = {
/**
* __xe_pt_unbind_vma() - Disconnect and free a page-table tree for the vma
* address range.
- * @gt: The gt to unbind for.
+ * @tile: The tile to unbind for.
* @vma: The vma to unbind.
* @e: The engine with which to do pipelined page-table updates.
* @syncs: Entries to sync on before disconnecting the tree to be destroyed.
@@ -1597,7 +1588,7 @@ static const struct xe_migrate_pt_update_ops userptr_unbind_ops = {
* on success, an error pointer on error.
*/
struct dma_fence *
-__xe_pt_unbind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
+__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e,
struct xe_sync_entry *syncs, u32 num_syncs)
{
struct xe_vm_pgtable_update entries[XE_VM_MAX_LEVEL * 2 + 1];
@@ -1616,16 +1607,15 @@ __xe_pt_unbind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
xe_bo_assert_held(vma->bo);
xe_vm_assert_held(vm);
- XE_BUG_ON(xe_gt_is_media_type(gt));
vm_dbg(&vma->vm->xe->drm,
"Preparing unbind, with range [%llx...%llx) engine %p.\n",
vma->start, vma->end, e);
- num_entries = xe_pt_stage_unbind(gt, vma, entries);
+ num_entries = xe_pt_stage_unbind(tile, vma, entries);
XE_BUG_ON(num_entries > ARRAY_SIZE(entries));
- xe_vm_dbg_print_entries(gt_to_xe(gt), entries, num_entries);
+ xe_vm_dbg_print_entries(tile_to_xe(tile), entries, num_entries);
ifence = kzalloc(sizeof(*ifence), GFP_KERNEL);
if (!ifence)
@@ -1636,9 +1626,9 @@ __xe_pt_unbind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
* clear again here. The eviction may have updated pagetables at a
* lower level, because it needs to be more conservative.
*/
- fence = xe_migrate_update_pgtables(gt->migrate,
+ fence = xe_migrate_update_pgtables(tile->primary_gt.migrate,
vm, NULL, e ? e :
- vm->eng[gt->info.id],
+ vm->eng[tile->id],
entries, num_entries,
syncs, num_syncs,
&unbind_pt_update.base);
@@ -1646,7 +1636,7 @@ __xe_pt_unbind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
int err;
/* TLB invalidation must be done before signaling unbind */
- err = invalidation_fence_init(gt, ifence, fence, vma);
+ err = invalidation_fence_init(&tile->primary_gt, ifence, fence, vma);
if (err) {
dma_fence_put(fence);
kfree(ifence);
@@ -1664,18 +1654,18 @@ __xe_pt_unbind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
DMA_RESV_USAGE_BOOKKEEP);
xe_pt_commit_unbind(vma, entries, num_entries,
unbind_pt_update.locked ? &deferred : NULL);
- vma->gt_present &= ~BIT(gt->info.id);
+ vma->tile_present &= ~BIT(tile->id);
} else {
kfree(ifence);
}
- if (!vma->gt_present)
+ if (!vma->tile_present)
list_del_init(&vma->rebind_link);
if (unbind_pt_update.locked) {
XE_WARN_ON(!xe_vma_is_userptr(vma));
- if (!vma->gt_present) {
+ if (!vma->tile_present) {
spin_lock(&vm->userptr.invalidated_lock);
list_del_init(&vma->userptr.invalidate_link);
spin_unlock(&vm->userptr.invalidated_lock);
diff --git a/drivers/gpu/drm/xe/xe_pt.h b/drivers/gpu/drm/xe/xe_pt.h
index 1152043e5c63..10f334b9c004 100644
--- a/drivers/gpu/drm/xe/xe_pt.h
+++ b/drivers/gpu/drm/xe/xe_pt.h
@@ -13,8 +13,8 @@ struct dma_fence;
struct xe_bo;
struct xe_device;
struct xe_engine;
-struct xe_gt;
struct xe_sync_entry;
+struct xe_tile;
struct xe_vm;
struct xe_vma;
@@ -23,27 +23,27 @@ struct xe_vma;
unsigned int xe_pt_shift(unsigned int level);
-struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_gt *gt,
+struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile,
unsigned int level);
-int xe_pt_create_scratch(struct xe_device *xe, struct xe_gt *gt,
+int xe_pt_create_scratch(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm);
-void xe_pt_populate_empty(struct xe_gt *gt, struct xe_vm *vm,
+void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm,
struct xe_pt *pt);
void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred);
struct dma_fence *
-__xe_pt_bind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
+__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e,
struct xe_sync_entry *syncs, u32 num_syncs,
bool rebind);
struct dma_fence *
-__xe_pt_unbind_vma(struct xe_gt *gt, struct xe_vma *vma, struct xe_engine *e,
+__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e,
struct xe_sync_entry *syncs, u32 num_syncs);
-bool xe_pt_zap_ptes(struct xe_gt *gt, struct xe_vma *vma);
+bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma);
u64 gen8_pde_encode(struct xe_bo *bo, u64 bo_offset,
const enum xe_cache_level level);
diff --git a/drivers/gpu/drm/xe/xe_sa.c b/drivers/gpu/drm/xe/xe_sa.c
index c16f7c14ff52..fee71080bd31 100644
--- a/drivers/gpu/drm/xe/xe_sa.c
+++ b/drivers/gpu/drm/xe/xe_sa.c
@@ -11,7 +11,6 @@
#include "xe_bo.h"
#include "xe_device.h"
-#include "xe_gt.h"
#include "xe_map.h"
static void xe_sa_bo_manager_fini(struct drm_device *drm, void *arg)
@@ -33,14 +32,14 @@ static void xe_sa_bo_manager_fini(struct drm_device *drm, void *arg)
sa_manager->bo = NULL;
}
-struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_gt *gt, u32 size, u32 align)
+struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 align)
{
- struct xe_device *xe = gt_to_xe(gt);
+ struct xe_device *xe = tile_to_xe(tile);
u32 managed_size = size - SZ_4K;
struct xe_bo *bo;
int ret;
- struct xe_sa_manager *sa_manager = drmm_kzalloc(>_to_xe(gt)->drm,
+ struct xe_sa_manager *sa_manager = drmm_kzalloc(&tile_to_xe(tile)->drm,
sizeof(*sa_manager),
GFP_KERNEL);
if (!sa_manager)
@@ -48,8 +47,8 @@ struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_gt *gt, u32 size, u32 alig
sa_manager->bo = NULL;
- bo = xe_bo_create_pin_map(xe, gt, NULL, size, ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+ bo = xe_bo_create_pin_map(xe, tile, NULL, size, ttm_bo_type_kernel,
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(bo)) {
drm_err(&xe->drm, "failed to allocate bo for sa manager: %ld\n",
@@ -90,7 +89,7 @@ struct drm_suballoc *xe_sa_bo_new(struct xe_sa_manager *sa_manager,
void xe_sa_bo_flush_write(struct drm_suballoc *sa_bo)
{
struct xe_sa_manager *sa_manager = to_xe_sa_manager(sa_bo->manager);
- struct xe_device *xe = gt_to_xe(sa_manager->bo->gt);
+ struct xe_device *xe = tile_to_xe(sa_manager->bo->tile);
if (!sa_manager->bo->vmap.is_iomem)
return;
diff --git a/drivers/gpu/drm/xe/xe_sa.h b/drivers/gpu/drm/xe/xe_sa.h
index 3063fb34c720..4e96483057d7 100644
--- a/drivers/gpu/drm/xe/xe_sa.h
+++ b/drivers/gpu/drm/xe/xe_sa.h
@@ -9,9 +9,9 @@
struct dma_fence;
struct xe_bo;
-struct xe_gt;
+struct xe_tile;
-struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_gt *gt, u32 size, u32 align);
+struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 align);
struct drm_suballoc *xe_sa_bo_new(struct xe_sa_manager *sa_manager,
u32 size);
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
index 5530a6b6ef31..59d3e25ea550 100644
--- a/drivers/gpu/drm/xe/xe_tile.c
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -7,6 +7,7 @@
#include "xe_device.h"
#include "xe_ggtt.h"
+#include "xe_sa.h"
#include "xe_tile.h"
#include "xe_ttm_vram_mgr.h"
@@ -76,6 +77,12 @@ int xe_tile_init_noalloc(struct xe_tile *tile)
goto err_mem_access;
err = xe_ggtt_init_noalloc(tile->mem.ggtt);
+ if (err)
+ goto err_mem_access;
+
+ tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16);
+ if (IS_ERR(tile->mem.kernel_bb_pool))
+ err = PTR_ERR(tile->mem.kernel_bb_pool);
err_mem_access:
xe_device_mem_access_put(tile_to_xe(tile));
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 317c541753fb..b05038921e02 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -322,6 +322,7 @@ int xe_uc_fw_init(struct xe_uc_fw *uc_fw)
{
struct xe_device *xe = uc_fw_to_xe(uc_fw);
struct xe_gt *gt = uc_fw_to_gt(uc_fw);
+ struct xe_tile *tile = gt_to_tile(gt);
struct device *dev = xe->drm.dev;
const struct firmware *fw = NULL;
struct uc_css_header *css;
@@ -411,9 +412,9 @@ int xe_uc_fw_init(struct xe_uc_fw *uc_fw)
if (uc_fw->type == XE_UC_FW_TYPE_GUC)
guc_read_css_info(uc_fw, css);
- obj = xe_bo_create_from_data(xe, gt, fw->data, fw->size,
+ obj = xe_bo_create_from_data(xe, tile, fw->data, fw->size,
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+ XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(obj)) {
drm_notice(&xe->drm, "%s firmware %s: failed to create / populate bo",
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index b8fc30c3f370..066679b2df00 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -463,7 +463,7 @@ int xe_vm_lock_dma_resv(struct xe_vm *vm, struct ww_acquire_ctx *ww,
xe_bo_assert_held(vma->bo);
list_del_init(&vma->notifier.rebind_link);
- if (vma->gt_present && !vma->destroyed)
+ if (vma->tile_present && !vma->destroyed)
list_move_tail(&vma->rebind_link, &vm->rebind_list);
}
spin_unlock(&vm->notifier.list_lock);
@@ -701,7 +701,7 @@ static bool vma_userptr_invalidate(struct mmu_interval_notifier *mni,
* Tell exec and rebind worker they need to repin and rebind this
* userptr.
*/
- if (!xe_vm_in_fault_mode(vm) && !vma->destroyed && vma->gt_present) {
+ if (!xe_vm_in_fault_mode(vm) && !vma->destroyed && vma->tile_present) {
spin_lock(&vm->userptr.invalidated_lock);
list_move_tail(&vma->userptr.invalidate_link,
&vm->userptr.invalidated);
@@ -819,7 +819,7 @@ struct dma_fence *xe_vm_rebind(struct xe_vm *vm, bool rebind_worker)
xe_vm_assert_held(vm);
list_for_each_entry_safe(vma, next, &vm->rebind_list, rebind_link) {
- XE_WARN_ON(!vma->gt_present);
+ XE_WARN_ON(!vma->tile_present);
list_del_init(&vma->rebind_link);
dma_fence_put(fence);
@@ -840,10 +840,10 @@ static struct xe_vma *xe_vma_create(struct xe_vm *vm,
u64 bo_offset_or_userptr,
u64 start, u64 end,
bool read_only,
- u64 gt_mask)
+ u64 tile_mask)
{
struct xe_vma *vma;
- struct xe_gt *gt;
+ struct xe_tile *tile;
u8 id;
XE_BUG_ON(start >= end);
@@ -868,12 +868,11 @@ static struct xe_vma *xe_vma_create(struct xe_vm *vm,
if (read_only)
vma->pte_flags = XE_PTE_READ_ONLY;
- if (gt_mask) {
- vma->gt_mask = gt_mask;
+ if (tile_mask) {
+ vma->tile_mask = tile_mask;
} else {
- for_each_gt(gt, vm->xe, id)
- if (!xe_gt_is_media_type(gt))
- vma->gt_mask |= 0x1 << id;
+ for_each_tile(tile, vm->xe, id)
+ vma->tile_mask |= 0x1 << id;
}
if (vm->xe->info.platform == XE_PVC)
@@ -1105,8 +1104,8 @@ static void vm_destroy_work_func(struct work_struct *w);
struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
{
struct xe_vm *vm;
- int err, i = 0, number_gts = 0;
- struct xe_gt *gt;
+ int err, i = 0, number_tiles = 0;
+ struct xe_tile *tile;
u8 id;
vm = kzalloc(sizeof(*vm), GFP_KERNEL);
@@ -1158,15 +1157,12 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
if (IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
vm->flags |= XE_VM_FLAGS_64K;
- for_each_gt(gt, xe, id) {
- if (xe_gt_is_media_type(gt))
- continue;
-
+ for_each_tile(tile, xe, id) {
if (flags & XE_VM_FLAG_MIGRATION &&
- gt->info.id != XE_VM_FLAG_GT_ID(flags))
+ tile->id != XE_VM_FLAG_GT_ID(flags))
continue;
- vm->pt_root[id] = xe_pt_create(vm, gt, xe->info.vm_max_level);
+ vm->pt_root[id] = xe_pt_create(vm, tile, xe->info.vm_max_level);
if (IS_ERR(vm->pt_root[id])) {
err = PTR_ERR(vm->pt_root[id]);
vm->pt_root[id] = NULL;
@@ -1175,11 +1171,11 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
}
if (flags & XE_VM_FLAG_SCRATCH_PAGE) {
- for_each_gt(gt, xe, id) {
+ for_each_tile(tile, xe, id) {
if (!vm->pt_root[id])
continue;
- err = xe_pt_create_scratch(xe, gt, vm);
+ err = xe_pt_create_scratch(xe, tile, vm);
if (err)
goto err_scratch_pt;
}
@@ -1196,17 +1192,18 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
}
/* Fill pt_root after allocating scratch tables */
- for_each_gt(gt, xe, id) {
+ for_each_tile(tile, xe, id) {
if (!vm->pt_root[id])
continue;
- xe_pt_populate_empty(gt, vm, vm->pt_root[id]);
+ xe_pt_populate_empty(tile, vm, vm->pt_root[id]);
}
dma_resv_unlock(&vm->resv);
/* Kernel migration VM shouldn't have a circular loop.. */
if (!(flags & XE_VM_FLAG_MIGRATION)) {
- for_each_gt(gt, xe, id) {
+ for_each_tile(tile, xe, id) {
+ struct xe_gt *gt = &tile->primary_gt;
struct xe_vm *migrate_vm;
struct xe_engine *eng;
@@ -1223,11 +1220,11 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
return ERR_CAST(eng);
}
vm->eng[id] = eng;
- number_gts++;
+ number_tiles++;
}
}
- if (number_gts > 1)
+ if (number_tiles > 1)
vm->composite_fence_ctx = dma_fence_context_alloc(1);
mutex_lock(&xe->usm.lock);
@@ -1242,7 +1239,7 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
return vm;
err_scratch_pt:
- for_each_gt(gt, xe, id) {
+ for_each_tile(tile, xe, id) {
if (!vm->pt_root[id])
continue;
@@ -1255,7 +1252,7 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
xe_bo_put(vm->scratch_bo[id]);
}
err_destroy_root:
- for_each_gt(gt, xe, id) {
+ for_each_tile(tile, xe, id) {
if (vm->pt_root[id])
xe_pt_destroy(vm->pt_root[id], vm->flags, NULL);
}
@@ -1312,7 +1309,7 @@ void xe_vm_close_and_put(struct xe_vm *vm)
struct rb_root contested = RB_ROOT;
struct ww_acquire_ctx ww;
struct xe_device *xe = vm->xe;
- struct xe_gt *gt;
+ struct xe_tile *tile;
u8 id;
XE_BUG_ON(vm->preempt.num_engines);
@@ -1323,7 +1320,7 @@ void xe_vm_close_and_put(struct xe_vm *vm)
if (xe_vm_in_compute_mode(vm))
flush_work(&vm->preempt.rebind_work);
- for_each_gt(gt, xe, id) {
+ for_each_tile(tile, xe, id) {
if (vm->eng[id]) {
xe_engine_kill(vm->eng[id]);
xe_engine_put(vm->eng[id]);
@@ -1360,7 +1357,7 @@ void xe_vm_close_and_put(struct xe_vm *vm)
* install a fence to resv. Hence it's safe to
* destroy the pagetables immediately.
*/
- for_each_gt(gt, xe, id) {
+ for_each_tile(tile, xe, id) {
if (vm->scratch_bo[id]) {
u32 i;
@@ -1410,7 +1407,7 @@ static void vm_destroy_work_func(struct work_struct *w)
container_of(w, struct xe_vm, destroy_work);
struct ww_acquire_ctx ww;
struct xe_device *xe = vm->xe;
- struct xe_gt *gt;
+ struct xe_tile *tile;
u8 id;
void *lookup;
@@ -1435,7 +1432,7 @@ static void vm_destroy_work_func(struct work_struct *w)
* can be moved to xe_vm_close_and_put.
*/
xe_vm_lock(vm, &ww, 0, false);
- for_each_gt(gt, xe, id) {
+ for_each_tile(tile, xe, id) {
if (vm->pt_root[id]) {
xe_pt_destroy(vm->pt_root[id], vm->flags, NULL);
vm->pt_root[id] = NULL;
@@ -1471,11 +1468,9 @@ struct xe_vm *xe_vm_lookup(struct xe_file *xef, u32 id)
return vm;
}
-u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_gt *full_gt)
+u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile)
{
- XE_BUG_ON(xe_gt_is_media_type(full_gt));
-
- return gen8_pde_encode(vm->pt_root[full_gt->info.id]->bo, 0,
+ return gen8_pde_encode(vm->pt_root[tile->id]->bo, 0,
XE_CACHE_WB);
}
@@ -1483,32 +1478,30 @@ static struct dma_fence *
xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e,
struct xe_sync_entry *syncs, u32 num_syncs)
{
- struct xe_gt *gt;
+ struct xe_tile *tile;
struct dma_fence *fence = NULL;
struct dma_fence **fences = NULL;
struct dma_fence_array *cf = NULL;
struct xe_vm *vm = vma->vm;
int cur_fence = 0, i;
- int number_gts = hweight_long(vma->gt_present);
+ int number_tiles = hweight_long(vma->tile_present);
int err;
u8 id;
trace_xe_vma_unbind(vma);
- if (number_gts > 1) {
- fences = kmalloc_array(number_gts, sizeof(*fences),
+ if (number_tiles > 1) {
+ fences = kmalloc_array(number_tiles, sizeof(*fences),
GFP_KERNEL);
if (!fences)
return ERR_PTR(-ENOMEM);
}
- for_each_gt(gt, vm->xe, id) {
- if (!(vma->gt_present & BIT(id)))
+ for_each_tile(tile, vm->xe, id) {
+ if (!(vma->tile_present & BIT(id)))
goto next;
- XE_BUG_ON(xe_gt_is_media_type(gt));
-
- fence = __xe_pt_unbind_vma(gt, vma, e, syncs, num_syncs);
+ fence = __xe_pt_unbind_vma(tile, vma, e, syncs, num_syncs);
if (IS_ERR(fence)) {
err = PTR_ERR(fence);
goto err_fences;
@@ -1523,7 +1516,7 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e,
}
if (fences) {
- cf = dma_fence_array_create(number_gts, fences,
+ cf = dma_fence_array_create(number_tiles, fences,
vm->composite_fence_ctx,
vm->composite_fence_seqno++,
false);
@@ -1555,32 +1548,31 @@ static struct dma_fence *
xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e,
struct xe_sync_entry *syncs, u32 num_syncs)
{
- struct xe_gt *gt;
+ struct xe_tile *tile;
struct dma_fence *fence;
struct dma_fence **fences = NULL;
struct dma_fence_array *cf = NULL;
struct xe_vm *vm = vma->vm;
int cur_fence = 0, i;
- int number_gts = hweight_long(vma->gt_mask);
+ int number_tiles = hweight_long(vma->tile_mask);
int err;
u8 id;
trace_xe_vma_bind(vma);
- if (number_gts > 1) {
- fences = kmalloc_array(number_gts, sizeof(*fences),
+ if (number_tiles > 1) {
+ fences = kmalloc_array(number_tiles, sizeof(*fences),
GFP_KERNEL);
if (!fences)
return ERR_PTR(-ENOMEM);
}
- for_each_gt(gt, vm->xe, id) {
- if (!(vma->gt_mask & BIT(id)))
+ for_each_tile(tile, vm->xe, id) {
+ if (!(vma->tile_mask & BIT(id)))
goto next;
- XE_BUG_ON(xe_gt_is_media_type(gt));
- fence = __xe_pt_bind_vma(gt, vma, e, syncs, num_syncs,
- vma->gt_present & BIT(id));
+ fence = __xe_pt_bind_vma(tile, vma, e, syncs, num_syncs,
+ vma->tile_present & BIT(id));
if (IS_ERR(fence)) {
err = PTR_ERR(fence);
goto err_fences;
@@ -1595,7 +1587,7 @@ xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e,
}
if (fences) {
- cf = dma_fence_array_create(number_gts, fences,
+ cf = dma_fence_array_create(number_tiles, fences,
vm->composite_fence_ctx,
vm->composite_fence_seqno++,
false);
@@ -1983,7 +1975,7 @@ static int xe_vm_prefetch(struct xe_vm *vm, struct xe_vma *vma,
return err;
}
- if (vma->gt_mask != (vma->gt_present & ~vma->usm.gt_invalidated)) {
+ if (vma->tile_mask != (vma->tile_present & ~vma->usm.tile_invalidated)) {
return xe_vm_bind(vm, vma, e, vma->bo, syncs, num_syncs,
afence);
} else {
@@ -2619,7 +2611,7 @@ static struct xe_vma *vm_unbind_lookup_vmas(struct xe_vm *vm,
first->start,
lookup->start - 1,
(first->pte_flags & XE_PTE_READ_ONLY),
- first->gt_mask);
+ first->tile_mask);
if (first->bo)
xe_bo_unlock(first->bo, &ww);
if (!new_first) {
@@ -2650,7 +2642,7 @@ static struct xe_vma *vm_unbind_lookup_vmas(struct xe_vm *vm,
last->start + chunk,
last->end,
(last->pte_flags & XE_PTE_READ_ONLY),
- last->gt_mask);
+ last->tile_mask);
if (last->bo)
xe_bo_unlock(last->bo, &ww);
if (!new_last) {
@@ -2786,7 +2778,7 @@ static struct xe_vma *vm_bind_ioctl_lookup_vma(struct xe_vm *vm,
struct xe_bo *bo,
u64 bo_offset_or_userptr,
u64 addr, u64 range, u32 op,
- u64 gt_mask, u32 region)
+ u64 tile_mask, u32 region)
{
struct ww_acquire_ctx ww;
struct xe_vma *vma, lookup;
@@ -2807,7 +2799,7 @@ static struct xe_vma *vm_bind_ioctl_lookup_vma(struct xe_vm *vm,
vma = xe_vma_create(vm, bo, bo_offset_or_userptr, addr,
addr + range - 1,
op & XE_VM_BIND_FLAG_READONLY,
- gt_mask);
+ tile_mask);
xe_bo_unlock(bo, &ww);
if (!vma)
return ERR_PTR(-ENOMEM);
@@ -2847,7 +2839,7 @@ static struct xe_vma *vm_bind_ioctl_lookup_vma(struct xe_vm *vm,
vma = xe_vma_create(vm, NULL, bo_offset_or_userptr, addr,
addr + range - 1,
op & XE_VM_BIND_FLAG_READONLY,
- gt_mask);
+ tile_mask);
if (!vma)
return ERR_PTR(-ENOMEM);
@@ -3075,11 +3067,11 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
goto put_engine;
}
- if (bind_ops[i].gt_mask) {
- u64 valid_gts = BIT(xe->info.tile_count) - 1;
+ if (bind_ops[i].tile_mask) {
+ u64 valid_tiles = BIT(xe->info.tile_count) - 1;
- if (XE_IOCTL_ERR(xe, bind_ops[i].gt_mask &
- ~valid_gts)) {
+ if (XE_IOCTL_ERR(xe, bind_ops[i].tile_mask &
+ ~valid_tiles)) {
err = -EINVAL;
goto put_engine;
}
@@ -3170,11 +3162,11 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
u64 addr = bind_ops[i].addr;
u32 op = bind_ops[i].op;
u64 obj_offset = bind_ops[i].obj_offset;
- u64 gt_mask = bind_ops[i].gt_mask;
+ u64 tile_mask = bind_ops[i].tile_mask;
u32 region = bind_ops[i].region;
vmas[i] = vm_bind_ioctl_lookup_vma(vm, bos[i], obj_offset,
- addr, range, op, gt_mask,
+ addr, range, op, tile_mask,
region);
if (IS_ERR(vmas[i])) {
err = PTR_ERR(vmas[i]);
@@ -3348,8 +3340,8 @@ void xe_vm_unlock(struct xe_vm *vm, struct ww_acquire_ctx *ww)
int xe_vm_invalidate_vma(struct xe_vma *vma)
{
struct xe_device *xe = vma->vm->xe;
- struct xe_gt *gt;
- u32 gt_needs_invalidate = 0;
+ struct xe_tile *tile;
+ u32 tile_needs_invalidate = 0;
int seqno[XE_MAX_TILES_PER_DEVICE];
u8 id;
int ret;
@@ -3371,25 +3363,29 @@ int xe_vm_invalidate_vma(struct xe_vma *vma)
}
}
- for_each_gt(gt, xe, id) {
- if (xe_pt_zap_ptes(gt, vma)) {
- gt_needs_invalidate |= BIT(id);
+ for_each_tile(tile, xe, id) {
+ if (xe_pt_zap_ptes(tile, vma)) {
+ tile_needs_invalidate |= BIT(id);
xe_device_wmb(xe);
- seqno[id] = xe_gt_tlb_invalidation_vma(gt, NULL, vma);
+ /*
+ * FIXME: We potentially need to invalidate multiple
+ * GTs within the tile
+ */
+ seqno[id] = xe_gt_tlb_invalidation_vma(&tile->primary_gt, NULL, vma);
if (seqno[id] < 0)
return seqno[id];
}
}
- for_each_gt(gt, xe, id) {
- if (gt_needs_invalidate & BIT(id)) {
- ret = xe_gt_tlb_invalidation_wait(gt, seqno[id]);
+ for_each_tile(tile, xe, id) {
+ if (tile_needs_invalidate & BIT(id)) {
+ ret = xe_gt_tlb_invalidation_wait(&tile->primary_gt, seqno[id]);
if (ret < 0)
return ret;
}
}
- vma->usm.gt_invalidated = vma->gt_mask;
+ vma->usm.tile_invalidated = vma->tile_mask;
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h
index 748dc16ebed9..372f26153209 100644
--- a/drivers/gpu/drm/xe/xe_vm.h
+++ b/drivers/gpu/drm/xe/xe_vm.h
@@ -54,7 +54,7 @@ xe_vm_find_overlapping_vma(struct xe_vm *vm, const struct xe_vma *vma);
#define xe_vm_assert_held(vm) dma_resv_assert_held(&(vm)->resv)
-u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_gt *full_gt);
+u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile);
int xe_vm_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h
index 203ba9d946b8..c45c5daeeaa7 100644
--- a/drivers/gpu/drm/xe/xe_vm_types.h
+++ b/drivers/gpu/drm/xe/xe_vm_types.h
@@ -37,17 +37,17 @@ struct xe_vma {
/** @bo_offset: offset into BO if not a userptr, unused for userptr */
u64 bo_offset;
- /** @gt_mask: GT mask of where to create binding for this VMA */
- u64 gt_mask;
+ /** @tile_mask: Tile mask of where to create binding for this VMA */
+ u64 tile_mask;
/**
- * @gt_present: GT mask of binding are present for this VMA.
+ * @tile_present: GT mask of binding are present for this VMA.
* protected by vm->lock, vm->resv and for userptrs,
* vm->userptr.notifier_lock for writing. Needs either for reading,
* but if reading is done under the vm->lock only, it needs to be held
* in write mode.
*/
- u64 gt_present;
+ u64 tile_present;
/**
* @destroyed: VMA is destroyed, in the sense that it shouldn't be
@@ -132,8 +132,8 @@ struct xe_vma {
/** @usm: unified shared memory state */
struct {
- /** @gt_invalidated: VMA has been invalidated */
- u64 gt_invalidated;
+ /** @tile_invalidated: VMA has been invalidated */
+ u64 tile_invalidated;
} usm;
struct {
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index b0b80aae3ee8..11a0ede7155e 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -398,10 +398,10 @@ struct drm_xe_vm_bind_op {
__u64 addr;
/**
- * @gt_mask: Mask for which GTs to create binds for, 0 == All GTs,
+ * @tile_mask: Mask for which tiles to create binds for, 0 == All tiles,
* only applies to creating new VMAs
*/
- __u64 gt_mask;
+ __u64 tile_mask;
/** @op: Operation to perform (lower 16 bits) and flags (upper 16 bits) */
__u32 op;
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 12/30] fixup! drm/xe/display: Implement display support
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (10 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 11/30] drm/xe: Memory allocations are tile-based, not GT-based Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-26 21:14 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 13/30] drm/xe: Move migration from GT to tile Matt Roper
` (20 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
---
drivers/gpu/drm/i915/display/intel_dsb.c | 5 +++--
drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
drivers/gpu/drm/i915/display/intel_fbdev.c | 7 ++++---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 7 ++++---
drivers/gpu/drm/xe/display/xe_plane_initial.c | 2 +-
5 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 7c93580282b4..3830309aacf4 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -379,9 +379,10 @@ struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc,
#else
/* ~1 qword per instruction, full cachelines */
size = ALIGN(max_cmds * 8, 64);
- obj = xe_bo_create_pin_map(i915, to_gt(i915), NULL, PAGE_ALIGN(size),
+ obj = xe_bo_create_pin_map(i915, xe_device_get_root_tile(i915),
+ NULL, PAGE_ALIGN(size),
ttm_bo_type_kernel,
- XE_BO_CREATE_VRAM_IF_DGFX(to_gt(i915)) |
+ XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(i915)) |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(obj)) {
kfree(dsb);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 9dc7083fe974..0e8e899f596b 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -71,7 +71,8 @@ static int i915_gem_stolen_insert_node_in_range(struct xe_device *xe, struct xe_
int err;
u32 flags = XE_BO_CREATE_PINNED_BIT | XE_BO_CREATE_STOLEN_BIT;
- *bo = xe_bo_create_locked_range(xe, to_gt(xe), NULL, size, start, end,
+ *bo = xe_bo_create_locked_range(xe, xe_device_get_root_tile(xe),
+ NULL, size, start, end,
ttm_bo_type_kernel, flags);
if (IS_ERR(*bo)) {
err = PTR_ERR(*bo);
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 95f4cbc2e675..ebb07d0ccff6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -210,7 +210,8 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
}
#else
if (!IS_DGFX(dev_priv)) {
- obj = xe_bo_create_pin_map(dev_priv, to_gt(dev_priv), NULL, size,
+ obj = xe_bo_create_pin_map(dev_priv, xe_device_get_root_tile(dev_priv),
+ NULL, size,
ttm_bo_type_kernel, XE_BO_SCANOUT_BIT |
XE_BO_CREATE_STOLEN_BIT |
XE_BO_CREATE_PINNED_BIT);
@@ -220,9 +221,9 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
drm_info(&dev_priv->drm, "Allocated fbdev into stolen failed: %li\n", PTR_ERR(obj));
}
if (IS_ERR(obj)) {
- obj = xe_bo_create_pin_map(dev_priv, to_gt(dev_priv), NULL, size,
+ obj = xe_bo_create_pin_map(dev_priv, xe_device_get_root_tile(dev_priv), NULL, size,
ttm_bo_type_kernel, XE_BO_SCANOUT_BIT |
- XE_BO_CREATE_VRAM_IF_DGFX(to_gt(dev_priv)) |
+ XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(dev_priv)) |
XE_BO_CREATE_PINNED_BIT);
}
#endif
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 27e4d29aa73d..97e9be79b154 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -45,6 +45,7 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
struct i915_vma *vma)
{
struct xe_device *xe = to_xe_device(fb->base.dev);
+ struct xe_tile *tile0 = xe_device_get_root_tile(xe);
struct xe_bo *bo = intel_fb_obj(&fb->base), *dpt;
u32 dpt_size, size = bo->ttm.base.size;
@@ -55,17 +56,17 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
dpt_size = ALIGN(intel_rotation_info_size(&view->rotated) * 8,
XE_PAGE_SIZE);
- dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
+ dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
ttm_bo_type_kernel,
XE_BO_CREATE_VRAM0_BIT |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(dpt))
- dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
+ dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
ttm_bo_type_kernel,
XE_BO_CREATE_STOLEN_BIT |
XE_BO_CREATE_GGTT_BIT);
if (IS_ERR(dpt))
- dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
+ dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
ttm_bo_type_kernel,
XE_BO_CREATE_SYSTEM_BIT |
XE_BO_CREATE_GGTT_BIT);
diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
index 39dd97acae08..99c35a4ef673 100644
--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
@@ -115,7 +115,7 @@ initial_plane_bo(struct xe_device *xe,
page_size);
size -= base;
- bo = xe_bo_create_pin_map_at(xe, &tile0->primary_gt, NULL, size, phys_base,
+ bo = xe_bo_create_pin_map_at(xe, tile0, NULL, size, phys_base,
ttm_bo_type_kernel, flags);
if (IS_ERR(bo)) {
drm_dbg(&xe->drm,
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 13/30] drm/xe: Move migration from GT to tile
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (11 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 12/30] fixup! drm/xe/display: Implement display support Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 14/30] drm/xe: Clarify 'gt' retrieval for primary tile Matt Roper
` (19 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
Migration primarily focuses on the memory associated with a tile, so it
makes more sense to track this at the tile level (especially since the
driver was already skipping migration operations on media GTs).
Note that the blitter engine used to perform the migration always lives
in the tile's primary GT today. In theory that could change if media
GTs ever start including blitter engines in the future, but we can
extend the design if/when that happens in the future.
v2:
- Fix kunit test build
- Kerneldoc parameter name update
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/tests/xe_bo.c | 4 +-
drivers/gpu/drm/xe/tests/xe_migrate.c | 25 ++++++-----
drivers/gpu/drm/xe/xe_bo.c | 6 +--
drivers/gpu/drm/xe/xe_bo_evict.c | 14 +++---
drivers/gpu/drm/xe/xe_device_types.h | 3 ++
drivers/gpu/drm/xe/xe_engine.c | 2 +-
drivers/gpu/drm/xe/xe_gt.c | 28 +++---------
drivers/gpu/drm/xe/xe_gt.h | 1 -
drivers/gpu/drm/xe/xe_gt_pagefault.c | 2 +-
drivers/gpu/drm/xe/xe_gt_types.h | 3 --
drivers/gpu/drm/xe/xe_migrate.c | 61 +++++++++++++--------------
drivers/gpu/drm/xe/xe_migrate.h | 4 +-
drivers/gpu/drm/xe/xe_pt.c | 4 +-
drivers/gpu/drm/xe/xe_tile.c | 10 ++++-
drivers/gpu/drm/xe/xe_tile.h | 2 +
drivers/gpu/drm/xe/xe_vm.c | 2 +-
drivers/gpu/drm/xe/xe_vm_types.h | 2 +-
17 files changed, 82 insertions(+), 91 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_bo.c b/drivers/gpu/drm/xe/tests/xe_bo.c
index f933e5df6c12..5309204d8d1b 100644
--- a/drivers/gpu/drm/xe/tests/xe_bo.c
+++ b/drivers/gpu/drm/xe/tests/xe_bo.c
@@ -35,7 +35,7 @@ static int ccs_test_migrate(struct xe_gt *gt, struct xe_bo *bo,
/* Optionally clear bo *and* CCS data in VRAM. */
if (clear) {
- fence = xe_migrate_clear(gt->migrate, bo, bo->ttm.resource);
+ fence = xe_migrate_clear(gt_to_tile(gt)->migrate, bo, bo->ttm.resource);
if (IS_ERR(fence)) {
KUNIT_FAIL(test, "Failed to submit bo clear.\n");
return PTR_ERR(fence);
@@ -174,7 +174,7 @@ static int evict_test_run_gt(struct xe_device *xe, struct xe_gt *gt, struct kuni
struct xe_bo *bo, *external;
unsigned int bo_flags = XE_BO_CREATE_USER_BIT |
XE_BO_CREATE_VRAM_IF_DGFX(gt_to_tile(gt));
- struct xe_vm *vm = xe_migrate_get_vm(xe_device_get_root_tile(xe)->primary_gt.migrate);
+ struct xe_vm *vm = xe_migrate_get_vm(xe_device_get_root_tile(xe)->migrate);
struct ww_acquire_ctx ww;
int err, i;
diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c
index 813ebb4832e7..b66d4d194eb7 100644
--- a/drivers/gpu/drm/xe/tests/xe_migrate.c
+++ b/drivers/gpu/drm/xe/tests/xe_migrate.c
@@ -101,14 +101,14 @@ static const struct xe_migrate_pt_update_ops sanity_ops = {
static void test_copy(struct xe_migrate *m, struct xe_bo *bo,
struct kunit *test)
{
- struct xe_device *xe = gt_to_xe(m->gt);
+ struct xe_device *xe = tile_to_xe(m->tile);
u64 retval, expected = 0;
bool big = bo->size >= SZ_2M;
struct dma_fence *fence;
const char *str = big ? "Copying big bo" : "Copying small bo";
int err;
- struct xe_bo *sysmem = xe_bo_create_locked(xe, gt_to_tile(m->gt), NULL,
+ struct xe_bo *sysmem = xe_bo_create_locked(xe, m->tile, NULL,
bo->size,
ttm_bo_type_kernel,
XE_BO_CREATE_SYSTEM_BIT);
@@ -189,7 +189,7 @@ static void test_copy(struct xe_migrate *m, struct xe_bo *bo,
static void test_pt_update(struct xe_migrate *m, struct xe_bo *pt,
struct kunit *test, bool force_gpu)
{
- struct xe_device *xe = gt_to_xe(m->gt);
+ struct xe_device *xe = tile_to_xe(m->tile);
struct dma_fence *fence;
u64 retval, expected;
ktime_t then, now;
@@ -239,16 +239,15 @@ static void test_pt_update(struct xe_migrate *m, struct xe_bo *pt,
static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
{
- struct xe_gt *gt = m->gt;
- struct xe_tile *tile = gt_to_tile(m->gt);
- struct xe_device *xe = gt_to_xe(gt);
+ struct xe_tile *tile = m->tile;
+ struct xe_device *xe = tile_to_xe(tile);
struct xe_bo *pt, *bo = m->pt_bo, *big, *tiny;
struct xe_res_cursor src_it;
struct dma_fence *fence;
u64 retval, expected;
struct xe_bb *bb;
int err;
- u8 id = gt->info.id;
+ u8 id = tile->id;
err = xe_bo_vmap(bo);
if (err) {
@@ -287,7 +286,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
goto free_pt;
}
- bb = xe_bb_new(gt, 32, xe->info.supports_usm);
+ bb = xe_bb_new(&tile->primary_gt, 32, xe->info.supports_usm);
if (IS_ERR(bb)) {
KUNIT_FAIL(test, "Failed to create batchbuffer: %li\n",
PTR_ERR(bb));
@@ -319,7 +318,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
xe_map_wr(xe, &pt->vmap, 0, u32, 0xdeaddead);
expected = 0;
- emit_clear(m->gt, bb, xe_migrate_vm_addr(NUM_KERNEL_PDE - 1, 0), 4, 4,
+ emit_clear(&tile->primary_gt, bb, xe_migrate_vm_addr(NUM_KERNEL_PDE - 1, 0), 4, 4,
IS_DGFX(xe));
run_sanity_job(m, xe, bb, 1, "Writing to our newly mapped pagetable",
test);
@@ -390,14 +389,14 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
static int migrate_test_run_device(struct xe_device *xe)
{
struct kunit *test = xe_cur_kunit();
- struct xe_gt *gt;
+ struct xe_tile *tile;
int id;
- for_each_gt(gt, xe, id) {
- struct xe_migrate *m = gt->migrate;
+ for_each_tile(tile, xe, id) {
+ struct xe_migrate *m = tile->migrate;
struct ww_acquire_ctx ww;
- kunit_info(test, "Testing gt id %d.\n", id);
+ kunit_info(test, "Testing tile id %d.\n", id);
xe_vm_lock(m->eng->vm, &ww, 0, true);
xe_device_mem_access_get(xe);
xe_migrate_sanity_test(m, test);
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 9d613fc5d309..a596f2619e0f 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -637,7 +637,7 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
tile = mem_type_to_tile(xe, old_mem->mem_type);
XE_BUG_ON(!tile);
- XE_BUG_ON(!tile->primary_gt.migrate);
+ XE_BUG_ON(!tile->migrate);
trace_xe_bo_move(bo);
xe_device_mem_access_get(xe);
@@ -675,9 +675,9 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
}
} else {
if (move_lacks_source)
- fence = xe_migrate_clear(tile->primary_gt.migrate, bo, new_mem);
+ fence = xe_migrate_clear(tile->migrate, bo, new_mem);
else
- fence = xe_migrate_copy(tile->primary_gt.migrate, bo, old_mem, new_mem);
+ fence = xe_migrate_copy(tile->migrate, bo, old_mem, new_mem);
if (IS_ERR(fence)) {
ret = PTR_ERR(fence);
xe_device_mem_access_put(xe);
diff --git a/drivers/gpu/drm/xe/xe_bo_evict.c b/drivers/gpu/drm/xe/xe_bo_evict.c
index 9226195bd560..f559a7f3eb3e 100644
--- a/drivers/gpu/drm/xe/xe_bo_evict.c
+++ b/drivers/gpu/drm/xe/xe_bo_evict.c
@@ -8,7 +8,7 @@
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_ggtt.h"
-#include "xe_gt.h"
+#include "xe_tile.h"
/**
* xe_bo_evict_all - evict all BOs from VRAM
@@ -29,7 +29,7 @@ int xe_bo_evict_all(struct xe_device *xe)
struct ttm_device *bdev = &xe->ttm;
struct ww_acquire_ctx ww;
struct xe_bo *bo;
- struct xe_gt *gt;
+ struct xe_tile *tile;
struct list_head still_in_list;
u32 mem_type;
u8 id;
@@ -83,8 +83,8 @@ int xe_bo_evict_all(struct xe_device *xe)
* Wait for all user BO to be evicted as those evictions depend on the
* memory moved below.
*/
- for_each_gt(gt, xe, id)
- xe_gt_migrate_wait(gt);
+ for_each_tile(tile, xe, id)
+ xe_tile_migrate_wait(tile);
spin_lock(&xe->pinned.lock);
for (;;) {
@@ -186,7 +186,7 @@ int xe_bo_restore_user(struct xe_device *xe)
{
struct ww_acquire_ctx ww;
struct xe_bo *bo;
- struct xe_gt *gt;
+ struct xe_tile *tile;
struct list_head still_in_list;
u8 id;
int ret;
@@ -224,8 +224,8 @@ int xe_bo_restore_user(struct xe_device *xe)
spin_unlock(&xe->pinned.lock);
/* Wait for validate to complete */
- for_each_gt(gt, xe, id)
- xe_gt_migrate_wait(gt);
+ for_each_tile(tile, xe, id)
+ xe_tile_migrate_wait(tile);
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index e62ecccad605..9b5a25a86234 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -140,6 +140,9 @@ struct xe_tile {
*/
struct xe_sa_manager *kernel_bb_pool;
} mem;
+
+ /** @migrate: Migration helper for vram blits and clearing */
+ struct xe_migrate *migrate;
};
/**
diff --git a/drivers/gpu/drm/xe/xe_engine.c b/drivers/gpu/drm/xe/xe_engine.c
index 094ec17d3004..2caa368fedda 100644
--- a/drivers/gpu/drm/xe/xe_engine.c
+++ b/drivers/gpu/drm/xe/xe_engine.c
@@ -557,7 +557,7 @@ int xe_engine_create_ioctl(struct drm_device *dev, void *data,
if (XE_IOCTL_ERR(xe, !hwe))
return -EINVAL;
- migrate_vm = xe_migrate_get_vm(gt->migrate);
+ migrate_vm = xe_migrate_get_vm(gt_to_tile(gt)->migrate);
new = xe_engine_create(xe, migrate_vm, logical_mask,
args->width, hwe,
ENGINE_FLAG_PERSISTENT |
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 92407776f5f0..19f2cab3a57d 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -43,16 +43,6 @@
#include "xe_wa.h"
#include "xe_wopcm.h"
-struct xe_gt *xe_find_full_gt(struct xe_gt *gt)
-{
- /*
- * FIXME: Media GTs are disabled at the moment. Once re-enabled,
- * the proper handling here is to return the primary GT from the
- * parameter GT's tile.
- */
- return gt;
-}
-
int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt)
{
XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
@@ -170,6 +160,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_engine *e)
int xe_gt_record_default_lrcs(struct xe_gt *gt)
{
struct xe_device *xe = gt_to_xe(gt);
+ struct xe_tile *tile = gt_to_tile(gt);
struct xe_hw_engine *hwe;
enum xe_hw_engine_id id;
int err = 0;
@@ -193,7 +184,7 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt)
if (!default_lrc)
return -ENOMEM;
- vm = xe_migrate_get_vm(gt->migrate);
+ vm = xe_migrate_get_vm(tile->migrate);
e = xe_engine_create(xe, vm, BIT(hwe->logical_instance), 1,
hwe, ENGINE_FLAG_WA);
if (IS_ERR(e)) {
@@ -378,13 +369,13 @@ static int all_fw_domain_init(struct xe_gt *gt)
}
if (!xe_gt_is_media_type(gt)) {
- gt->migrate = xe_migrate_init(gt);
- if (IS_ERR(gt->migrate)) {
- err = PTR_ERR(gt->migrate);
+ struct xe_tile *tile = gt_to_tile(gt);
+
+ tile->migrate = xe_migrate_init(tile);
+ if (IS_ERR(tile->migrate)) {
+ err = PTR_ERR(tile->migrate);
goto err_force_wake;
}
- } else {
- gt->migrate = xe_find_full_gt(gt)->migrate;
}
err = xe_uc_init_hw(>->uc);
@@ -639,11 +630,6 @@ int xe_gt_resume(struct xe_gt *gt)
return err;
}
-void xe_gt_migrate_wait(struct xe_gt *gt)
-{
- xe_migrate_wait(gt->migrate);
-}
-
struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt,
enum xe_engine_class class,
u16 instance, bool logical)
diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
index f4e98f499b36..c8abbeb0fb96 100644
--- a/drivers/gpu/drm/xe/xe_gt.h
+++ b/drivers/gpu/drm/xe/xe_gt.h
@@ -25,7 +25,6 @@ void xe_gt_suspend_prepare(struct xe_gt *gt);
int xe_gt_suspend(struct xe_gt *gt);
int xe_gt_resume(struct xe_gt *gt);
void xe_gt_reset_async(struct xe_gt *gt);
-void xe_gt_migrate_wait(struct xe_gt *gt);
void xe_gt_sanitize(struct xe_gt *gt);
struct xe_gt *xe_find_full_gt(struct xe_gt *gt);
diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c
index 1c2b23ae89cf..73db7f7c0381 100644
--- a/drivers/gpu/drm/xe/xe_gt_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c
@@ -208,7 +208,7 @@ static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf)
/* Bind VMA only to the GT that has faulted */
trace_xe_vma_pf_bind(vma);
- fence = __xe_pt_bind_vma(tile, vma, xe_gt_migrate_engine(gt), NULL, 0,
+ fence = __xe_pt_bind_vma(tile, vma, xe_tile_migrate_engine(tile), NULL, 0,
vma->tile_present & BIT(tile->id));
if (IS_ERR(fence)) {
ret = PTR_ERR(fence);
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index ecca990183d0..a9b70a757174 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -278,9 +278,6 @@ struct xe_gt {
/** @hw_engines: hardware engines on the GT */
struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES];
- /** @migrate: Migration helper for vram blits and clearing */
- struct xe_migrate *migrate;
-
/** @pcode: GT's PCODE */
struct {
/** @lock: protecting GT's PCODE mailbox data */
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 031a0bde5585..efa2cfc0ea2c 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -36,8 +36,8 @@
struct xe_migrate {
/** @eng: Default engine used for migration */
struct xe_engine *eng;
- /** @gt: Backpointer to the gt this struct xe_migrate belongs to. */
- struct xe_gt *gt;
+ /** @tile: Backpointer to the tile this struct xe_migrate belongs to. */
+ struct xe_tile *tile;
/** @job_mutex: Timeline mutex for @eng. */
struct mutex job_mutex;
/** @pt_bo: Page-table buffer object. */
@@ -70,17 +70,17 @@ struct xe_migrate {
#define NUM_PT_PER_BLIT (MAX_PREEMPTDISABLE_TRANSFER / SZ_2M)
/**
- * xe_gt_migrate_engine() - Get this gt's migrate engine.
- * @gt: The gt.
+ * xe_tile_migrate_engine() - Get this tile's migrate engine.
+ * @tile: The tile.
*
- * Returns the default migrate engine of this gt.
+ * Returns the default migrate engine of this tile.
* TODO: Perhaps this function is slightly misplaced, and even unneeded?
*
* Return: The default migrate engine
*/
-struct xe_engine *xe_gt_migrate_engine(struct xe_gt *gt)
+struct xe_engine *xe_tile_migrate_engine(struct xe_tile *tile)
{
- return gt->migrate->eng;
+ return tile->migrate->eng;
}
static void xe_migrate_fini(struct drm_device *dev, void *arg)
@@ -128,8 +128,7 @@ static u64 xe_migrate_vram_ofs(u64 addr)
*/
static int xe_migrate_create_cleared_bo(struct xe_migrate *m, struct xe_vm *vm)
{
- struct xe_gt *gt = m->gt;
- struct xe_tile *tile = gt_to_tile(gt);
+ struct xe_tile *tile = m->tile;
struct xe_device *xe = vm->xe;
size_t cleared_size;
u64 vram_addr;
@@ -155,14 +154,13 @@ static int xe_migrate_create_cleared_bo(struct xe_migrate *m, struct xe_vm *vm)
return 0;
}
-static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
+static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
struct xe_vm *vm)
{
- u8 id = gt->info.id;
+ struct xe_device *xe = tile_to_xe(tile);
+ u8 id = tile->id;
u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
u32 map_ofs, level, i;
- struct xe_device *xe = gt_to_xe(m->gt);
- struct xe_tile *tile = gt_to_tile(m->gt);
struct xe_bo *bo, *batch = tile->mem.kernel_bb_pool->bo;
u64 entry;
int ret;
@@ -231,7 +229,7 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
m->batch_base_ofs = xe_migrate_vram_ofs(batch_addr);
if (xe->info.supports_usm) {
- batch = gt->usm.bb_pool->bo;
+ batch = tile->primary_gt.usm.bb_pool->bo;
batch_addr = xe_bo_addr(batch, 0, XE_PAGE_SIZE,
&is_vram);
m->usm_batch_base_ofs = xe_migrate_vram_ofs(batch_addr);
@@ -308,34 +306,33 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
/**
* xe_migrate_init() - Initialize a migrate context
- * @gt: Back-pointer to the gt we're initializing for.
+ * @tile: Back-pointer to the tile we're initializing for.
*
* Return: Pointer to a migrate context on success. Error pointer on error.
*/
-struct xe_migrate *xe_migrate_init(struct xe_gt *gt)
+struct xe_migrate *xe_migrate_init(struct xe_tile *tile)
{
- struct xe_device *xe = gt_to_xe(gt);
+ struct xe_device *xe = tile_to_xe(tile);
+ struct xe_gt *primary_gt = &tile->primary_gt;
struct xe_migrate *m;
struct xe_vm *vm;
struct ww_acquire_ctx ww;
int err;
- XE_BUG_ON(xe_gt_is_media_type(gt));
-
m = drmm_kzalloc(&xe->drm, sizeof(*m), GFP_KERNEL);
if (!m)
return ERR_PTR(-ENOMEM);
- m->gt = gt;
+ m->tile = tile;
/* Special layout, prepared below.. */
vm = xe_vm_create(xe, XE_VM_FLAG_MIGRATION |
- XE_VM_FLAG_SET_GT_ID(gt));
+ XE_VM_FLAG_SET_TILE_ID(tile));
if (IS_ERR(vm))
return ERR_CAST(vm);
xe_vm_lock(vm, &ww, 0, false);
- err = xe_migrate_prepare_vm(gt, m, vm);
+ err = xe_migrate_prepare_vm(tile, m, vm);
xe_vm_unlock(vm, &ww);
if (err) {
xe_vm_close_and_put(vm);
@@ -343,9 +340,9 @@ struct xe_migrate *xe_migrate_init(struct xe_gt *gt)
}
if (xe->info.supports_usm) {
- struct xe_hw_engine *hwe = xe_gt_hw_engine(gt,
+ struct xe_hw_engine *hwe = xe_gt_hw_engine(primary_gt,
XE_ENGINE_CLASS_COPY,
- gt->usm.reserved_bcs_instance,
+ primary_gt->usm.reserved_bcs_instance,
false);
if (!hwe)
return ERR_PTR(-EINVAL);
@@ -354,7 +351,7 @@ struct xe_migrate *xe_migrate_init(struct xe_gt *gt)
BIT(hwe->logical_instance), 1,
hwe, ENGINE_FLAG_KERNEL);
} else {
- m->eng = xe_engine_create_class(xe, gt, vm,
+ m->eng = xe_engine_create_class(xe, primary_gt, vm,
XE_ENGINE_CLASS_COPY,
ENGINE_FLAG_KERNEL);
}
@@ -549,7 +546,7 @@ static u32 xe_migrate_ccs_copy(struct xe_migrate *m,
u64 dst_ofs, bool dst_is_vram, u32 dst_size,
u64 ccs_ofs, bool copy_ccs)
{
- struct xe_gt *gt = m->gt;
+ struct xe_gt *gt = &m->tile->primary_gt;
u32 flush_flags = 0;
if (xe_device_has_flat_ccs(gt_to_xe(gt)) && !copy_ccs && dst_is_vram) {
@@ -604,7 +601,7 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
struct ttm_resource *src,
struct ttm_resource *dst)
{
- struct xe_gt *gt = m->gt;
+ struct xe_gt *gt = &m->tile->primary_gt;
struct xe_device *xe = gt_to_xe(gt);
struct dma_fence *fence = NULL;
u64 size = bo->size;
@@ -856,7 +853,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
struct ttm_resource *dst)
{
bool clear_vram = mem_type_is_vram(dst->mem_type);
- struct xe_gt *gt = m->gt;
+ struct xe_gt *gt = &m->tile->primary_gt;
struct xe_device *xe = gt_to_xe(gt);
struct dma_fence *fence = NULL;
u64 size = bo->size;
@@ -1063,7 +1060,7 @@ xe_migrate_update_pgtables_cpu(struct xe_migrate *m,
for (i = 0; i < num_updates; i++) {
const struct xe_vm_pgtable_update *update = &updates[i];
- ops->populate(pt_update, gt_to_tile(m->gt), &update->pt_bo->vmap, NULL,
+ ops->populate(pt_update, m->tile, &update->pt_bo->vmap, NULL,
update->ofs, update->qwords, update);
}
@@ -1130,9 +1127,9 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
struct xe_migrate_pt_update *pt_update)
{
const struct xe_migrate_pt_update_ops *ops = pt_update->ops;
- struct xe_gt *gt = m->gt;
- struct xe_tile *tile = gt_to_tile(m->gt);
- struct xe_device *xe = gt_to_xe(gt);
+ struct xe_tile *tile = m->tile;
+ struct xe_gt *gt = &tile->primary_gt;
+ struct xe_device *xe = tile_to_xe(tile);
struct xe_sched_job *job;
struct dma_fence *fence;
struct drm_suballoc *sa_bo = NULL;
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index e07b2a8845c0..df68a8976194 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -71,7 +71,7 @@ struct xe_migrate_pt_update {
struct xe_vma *vma;
};
-struct xe_migrate *xe_migrate_init(struct xe_gt *gt);
+struct xe_migrate *xe_migrate_init(struct xe_tile *tile);
struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
struct xe_bo *bo,
@@ -96,5 +96,5 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
void xe_migrate_wait(struct xe_migrate *m);
-struct xe_engine *xe_gt_migrate_engine(struct xe_gt *gt);
+struct xe_engine *xe_tile_migrate_engine(struct xe_tile *tile);
#endif
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index ea68e6b38133..a606cd1a7e3a 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -1305,7 +1305,7 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e,
return ERR_PTR(-ENOMEM);
}
- fence = xe_migrate_update_pgtables(tile->primary_gt.migrate,
+ fence = xe_migrate_update_pgtables(tile->migrate,
vm, vma->bo,
e ? e : vm->eng[tile->id],
entries, num_entries,
@@ -1626,7 +1626,7 @@ __xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e
* clear again here. The eviction may have updated pagetables at a
* lower level, because it needs to be more conservative.
*/
- fence = xe_migrate_update_pgtables(tile->primary_gt.migrate,
+ fence = xe_migrate_update_pgtables(tile->migrate,
vm, NULL, e ? e :
vm->eng[tile->id],
entries, num_entries,
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
index 59d3e25ea550..908eec5c17d9 100644
--- a/drivers/gpu/drm/xe/xe_tile.c
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -7,6 +7,7 @@
#include "xe_device.h"
#include "xe_ggtt.h"
+#include "xe_migrate.h"
#include "xe_sa.h"
#include "xe_tile.h"
#include "xe_ttm_vram_mgr.h"
@@ -81,10 +82,17 @@ int xe_tile_init_noalloc(struct xe_tile *tile)
goto err_mem_access;
tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16);
- if (IS_ERR(tile->mem.kernel_bb_pool))
+ if (IS_ERR(tile->mem.kernel_bb_pool)) {
err = PTR_ERR(tile->mem.kernel_bb_pool);
+ goto err_mem_access;
+ }
err_mem_access:
xe_device_mem_access_put(tile_to_xe(tile));
return err;
}
+
+void xe_tile_migrate_wait(struct xe_tile *tile)
+{
+ xe_migrate_wait(tile->migrate);
+}
diff --git a/drivers/gpu/drm/xe/xe_tile.h b/drivers/gpu/drm/xe/xe_tile.h
index 49b64d83ce91..80c13ebfe3bf 100644
--- a/drivers/gpu/drm/xe/xe_tile.h
+++ b/drivers/gpu/drm/xe/xe_tile.h
@@ -11,4 +11,6 @@ struct xe_tile;
int xe_tile_alloc(struct xe_tile *tile);
int xe_tile_init_noalloc(struct xe_tile *tile);
+void xe_tile_migrate_wait(struct xe_tile *tile);
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 066679b2df00..efe15841f047 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -1210,7 +1210,7 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
if (!vm->pt_root[id])
continue;
- migrate_vm = xe_migrate_get_vm(gt->migrate);
+ migrate_vm = xe_migrate_get_vm(tile->migrate);
eng = xe_engine_create_class(xe, gt, migrate_vm,
XE_ENGINE_CLASS_COPY,
ENGINE_FLAG_VM);
diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h
index c45c5daeeaa7..76af6ac0fa84 100644
--- a/drivers/gpu/drm/xe/xe_vm_types.h
+++ b/drivers/gpu/drm/xe/xe_vm_types.h
@@ -179,7 +179,7 @@ struct xe_vm {
#define XE_VM_FLAG_SCRATCH_PAGE BIT(4)
#define XE_VM_FLAG_FAULT_MODE BIT(5)
#define XE_VM_FLAG_GT_ID(flags) (((flags) >> 6) & 0x3)
-#define XE_VM_FLAG_SET_GT_ID(gt) ((gt)->info.id << 6)
+#define XE_VM_FLAG_SET_TILE_ID(tile) ((tile)->id << 6)
unsigned long flags;
/** @composite_fence_ctx: context composite fence */
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 14/30] drm/xe: Clarify 'gt' retrieval for primary tile
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (12 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 13/30] drm/xe: Move migration from GT to tile Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-22 11:47 ` Das, Nirmoy
2023-05-26 21:33 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 15/30] drm/xe: Drop vram_id Matt Roper
` (18 subsequent siblings)
32 siblings, 2 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
There are a bunch of places in the driver where we need to perform
non-GT MMIO against the platform's primary tile (display code, top-level
interrupt enable/disable, driver initialization, etc.). Rename
'to_gt()' to 'xe_primary_mmio_gt()' to clarify that we're trying to get
a primary MMIO handle for these top-level operations.
In the future we need to move away from xe_gt as the target for MMIO
operations (most of which are completely unrelated to GT).
v2:
- s/xe_primary_mmio_gt/xe_root_mmio_gt/ for more consistency with how
we refer to tile 0. (Lucas)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
| 2 +-
drivers/gpu/drm/xe/xe_device.c | 2 +-
drivers/gpu/drm/xe/xe_device.h | 11 +++++++++--
drivers/gpu/drm/xe/xe_irq.c | 6 +++---
drivers/gpu/drm/xe/xe_mmio.c | 8 ++++----
drivers/gpu/drm/xe/xe_query.c | 2 +-
drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 4 ++--
7 files changed, 21 insertions(+), 14 deletions(-)
--git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
index 14f195fe275d..fae6213d26f1 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
@@ -14,7 +14,7 @@ static inline struct xe_gt *__fake_uncore_to_gt(struct fake_uncore *uncore)
{
struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
- return to_gt(xe);
+ return xe_root_mmio_gt(xe);
}
static inline u32 intel_uncore_read(struct fake_uncore *uncore,
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index af165ad6f197..43a585b67581 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -394,7 +394,7 @@ static void device_kill_persistent_engines(struct xe_device *xe,
void xe_device_wmb(struct xe_device *xe)
{
- struct xe_gt *gt = xe_device_get_gt(xe, 0);
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
wmb();
if (IS_DGFX(xe))
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 745dbb16d417..42bc566c53d8 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -66,9 +66,16 @@ static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
}
/*
- * FIXME: Placeholder until multi-gt lands. Once that lands, kill this function.
+ * Provide a GT structure suitable for performing non-GT MMIO operations against
+ * the primary tile. Primarily intended for early tile initialization, display
+ * handling, top-most interrupt enable/disable, etc. Since anything using the
+ * MMIO handle returned by this function doesn't need GSI offset translation,
+ * we'll return the primary GT from the root tile.
+ *
+ * FIXME: Fix the driver design so that 'gt' isn't the target of all MMIO
+ * operations.
*/
-static inline struct xe_gt *to_gt(struct xe_device *xe)
+static inline struct xe_gt *xe_root_mmio_gt(struct xe_device *xe)
{
return &xe_device_get_root_tile(xe)->primary_gt;
}
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 5be31855d789..628057497cd5 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -285,7 +285,7 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
static irqreturn_t xelp_irq_handler(int irq, void *arg)
{
struct xe_device *xe = arg;
- struct xe_gt *gt = xe_device_get_gt(xe, 0); /* Only 1 GT here */
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
u32 master_ctl, gu_misc_iir;
long unsigned int intr_dw[2];
u32 identity[32];
@@ -311,7 +311,7 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
static u32 dg1_intr_disable(struct xe_device *xe)
{
- struct xe_gt *gt = xe_device_get_gt(xe, 0);
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
u32 val;
/* First disable interrupts */
@@ -329,7 +329,7 @@ static u32 dg1_intr_disable(struct xe_device *xe)
static void dg1_intr_enable(struct xe_device *xe, bool stall)
{
- struct xe_gt *gt = xe_device_get_gt(xe, 0);
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
if (stall)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 17b3a9880409..32427c10ba8a 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -150,7 +150,7 @@ static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_size)
{
- struct xe_gt *gt = xe_device_get_gt(xe, 0);
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
int err;
u32 reg_val;
@@ -287,7 +287,7 @@ int xe_mmio_probe_vram(struct xe_device *xe)
static void xe_mmio_probe_tiles(struct xe_device *xe)
{
- struct xe_gt *gt = xe_device_get_gt(xe, 0);
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
u32 mtcfg;
u8 adj_tile_count;
u8 id;
@@ -339,7 +339,7 @@ static void mmio_fini(struct drm_device *drm, void *arg)
int xe_mmio_init(struct xe_device *xe)
{
struct xe_tile *root_tile = xe_device_get_root_tile(xe);
- struct xe_gt *gt = xe_device_get_gt(xe, 0);
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
const int mmio_bar = 0;
int err;
@@ -398,7 +398,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct xe_device *xe = to_xe_device(dev);
- struct xe_gt *gt = xe_device_get_gt(xe, 0);
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
struct drm_xe_mmio *args = data;
unsigned int bits_flag, bytes;
struct xe_reg reg;
diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index c81652d7f4ec..49fff425adcd 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -259,7 +259,7 @@ static int query_gts(struct xe_device *xe, struct drm_xe_device_query *query)
static int query_hwconfig(struct xe_device *xe,
struct drm_xe_device_query *query)
{
- struct xe_gt *gt = xe_device_get_gt(xe, 0);
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
size_t size = xe_guc_hwconfig_size(>->uc.guc);
void __user *query_ptr = u64_to_user_ptr(query->data);
void *hwconfig;
diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
index a3855870321f..012474a6c387 100644
--- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
@@ -54,7 +54,7 @@ bool xe_ttm_stolen_cpu_access_needs_ggtt(struct xe_device *xe)
static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
{
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
- struct xe_gt *gt = to_gt(xe);
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
u64 vram_size, stolen_size;
int err;
@@ -88,7 +88,7 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr
u32 stolen_size;
u32 ggc, gms;
- ggc = xe_mmio_read32(to_gt(xe), GGC);
+ ggc = xe_mmio_read32(xe_root_mmio_gt(xe), GGC);
/* check GGMS, should be fixed 0x3 (8MB) */
if (drm_WARN_ON(&xe->drm, (ggc & GGMS_MASK) != GGMS_MASK))
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 15/30] drm/xe: Drop vram_id
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (13 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 14/30] drm/xe: Clarify 'gt' retrieval for primary tile Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 16/30] drm/xe: Drop extra_gts[] declarations and XE_GT_TYPE_REMOTE Matt Roper
` (17 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
The VRAM ID is always the tile ID; there's no need to track it
separately within a GT.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_pci.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 0269327b26e9..b406f33d115c 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -34,7 +34,6 @@ struct xe_subplatform_desc {
struct xe_gt_desc {
enum xe_gt_type type;
- u8 vram_id;
u32 mmio_adj_limit;
u32 mmio_adj_offset;
};
@@ -276,7 +275,6 @@ static const struct xe_device_desc dg2_desc = {
static const struct xe_gt_desc pvc_gts[] = {
{
.type = XE_GT_TYPE_REMOTE,
- .vram_id = 1,
.mmio_adj_limit = 0,
.mmio_adj_offset = 0,
},
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 16/30] drm/xe: Drop extra_gts[] declarations and XE_GT_TYPE_REMOTE
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (14 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 15/30] drm/xe: Drop vram_id Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 17/30] drm/xe: Allocate GT dynamically Matt Roper
` (16 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
Now that tiles and GTs are handled separately, extra_gts[] doesn't
really provide any useful information that we can't just infer directly.
The primary GT of the root tile and of the remote tiles behave the same
way and don't need independent handling.
When we re-add support for media GTs in a future patch, the presence of
media can be determined from MEDIA_VER() (i.e., >= 13) and media's GSI
offset handling is expected to remain constant for all forseeable future
platforms, so it won't need to be provided in a definition structure
either.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_gt_types.h | 1 -
drivers/gpu/drm/xe/xe_pci.c | 36 ++++++--------------------------
2 files changed, 6 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index a9b70a757174..05ac9eaa12c0 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -20,7 +20,6 @@ struct xe_ring_ops;
enum xe_gt_type {
XE_GT_TYPE_UNINITIALIZED,
XE_GT_TYPE_MAIN,
- XE_GT_TYPE_REMOTE,
XE_GT_TYPE_MEDIA,
};
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index b406f33d115c..888f6b372547 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -46,7 +46,6 @@ struct xe_device_desc {
const char *platform_name;
const struct xe_subplatform_desc *subplatforms;
- const struct xe_gt_desc *extra_gts;
enum xe_platform platform;
@@ -272,21 +271,12 @@ static const struct xe_device_desc dg2_desc = {
.has_display = true,
};
-static const struct xe_gt_desc pvc_gts[] = {
- {
- .type = XE_GT_TYPE_REMOTE,
- .mmio_adj_limit = 0,
- .mmio_adj_offset = 0,
- },
-};
-
static const struct xe_device_desc pvc_desc = {
.graphics = &graphics_xehpc,
DGFX_FEATURES,
PLATFORM(XE_PVC),
.has_display = false,
.require_force_probe = true,
- .extra_gts = pvc_gts,
};
static const struct xe_device_desc mtl_desc = {
@@ -552,28 +542,14 @@ static int xe_info_init(struct xe_device *xe,
tile->id = id;
gt = &tile->primary_gt;
- gt->info.id = id;
+ gt->info.id = id; /* FIXME: Determine sensible numbering */
gt->tile = tile;
+ gt->info.type = XE_GT_TYPE_MAIN;
+ gt->info.__engine_mask = graphics_desc->hw_engine_mask;
+ if (MEDIA_VER(xe) < 13 && media_desc)
+ gt->info.__engine_mask |= media_desc->hw_engine_mask;
- if (id == 0) {
- gt->info.type = XE_GT_TYPE_MAIN;
-
- gt->info.__engine_mask = graphics_desc->hw_engine_mask;
- if (MEDIA_VER(xe) < 13 && media_desc)
- gt->info.__engine_mask |= media_desc->hw_engine_mask;
-
- gt->mmio.adj_limit = 0;
- gt->mmio.adj_offset = 0;
- } else {
- gt->info.type = desc->extra_gts[id - 1].type;
- gt->info.__engine_mask = (gt->info.type == XE_GT_TYPE_MEDIA) ?
- media_desc->hw_engine_mask :
- graphics_desc->hw_engine_mask;
- gt->mmio.adj_limit =
- desc->extra_gts[id - 1].mmio_adj_limit;
- gt->mmio.adj_offset =
- desc->extra_gts[id - 1].mmio_adj_offset;
- }
+ /* TODO: Init media GT, if present */
}
return 0;
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 17/30] drm/xe: Allocate GT dynamically
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (15 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 16/30] drm/xe: Drop extra_gts[] declarations and XE_GT_TYPE_REMOTE Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 18/30] drm/xe: Add media GT to tile Matt Roper
` (15 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
In preparation for re-adding media GT support, switch the primary GT
within the tile to a dynamic allocation.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/tests/xe_migrate.c | 4 ++--
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 2 +-
drivers/gpu/drm/xe/xe_device.c | 4 ----
drivers/gpu/drm/xe/xe_device.h | 8 ++++++--
drivers/gpu/drm/xe/xe_device_types.h | 2 +-
drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
drivers/gpu/drm/xe/xe_gt.c | 11 ++++++++---
drivers/gpu/drm/xe/xe_gt.h | 2 +-
drivers/gpu/drm/xe/xe_migrate.c | 12 ++++++------
drivers/gpu/drm/xe/xe_pci.c | 7 +++++--
drivers/gpu/drm/xe/xe_pt.c | 4 ++--
drivers/gpu/drm/xe/xe_vm.c | 6 +++---
12 files changed, 36 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c
index b66d4d194eb7..c17deb4d8db5 100644
--- a/drivers/gpu/drm/xe/tests/xe_migrate.c
+++ b/drivers/gpu/drm/xe/tests/xe_migrate.c
@@ -286,7 +286,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
goto free_pt;
}
- bb = xe_bb_new(&tile->primary_gt, 32, xe->info.supports_usm);
+ bb = xe_bb_new(tile->primary_gt, 32, xe->info.supports_usm);
if (IS_ERR(bb)) {
KUNIT_FAIL(test, "Failed to create batchbuffer: %li\n",
PTR_ERR(bb));
@@ -318,7 +318,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
xe_map_wr(xe, &pt->vmap, 0, u32, 0xdeaddead);
expected = 0;
- emit_clear(&tile->primary_gt, bb, xe_migrate_vm_addr(NUM_KERNEL_PDE - 1, 0), 4, 4,
+ emit_clear(tile->primary_gt, bb, xe_migrate_vm_addr(NUM_KERNEL_PDE - 1, 0), 4, 4,
IS_DGFX(xe));
run_sanity_job(m, xe, bb, 1, "Writing to our newly mapped pagetable",
test);
diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index 7f8153df43ac..1b05f3cf7b21 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -237,7 +237,7 @@ static void xe_rtp_process_tests(struct kunit *test)
{
const struct rtp_test_case *param = test->param_value;
struct xe_device *xe = test->priv;
- struct xe_gt *gt = &xe_device_get_root_tile(xe)->primary_gt;
+ struct xe_gt *gt = xe_device_get_root_tile(xe)->primary_gt;
struct xe_reg_sr *reg_sr = >->reg_sr;
const struct xe_reg_sr_entry *sre, *sr_entry = NULL;
unsigned long idx, count = 0;
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 43a585b67581..ab3fcec52013 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -251,10 +251,6 @@ int xe_device_probe(struct xe_device *xe)
err = xe_tile_alloc(tile);
if (err)
return err;
-
- err = xe_gt_alloc(xe, &tile->primary_gt);
- if (err)
- return err;
}
err = xe_mmio_init(xe);
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 42bc566c53d8..156c62ac0381 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -58,7 +58,11 @@ static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
struct xe_gt *gt;
XE_BUG_ON(gt_id > XE_MAX_TILES_PER_DEVICE);
- gt = &xe->tiles[gt_id].primary_gt;
+
+ gt = xe->tiles[gt_id].primary_gt;
+ if (drm_WARN_ON(&xe->drm, !gt))
+ return NULL;
+
XE_BUG_ON(gt->info.id != gt_id);
XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
@@ -77,7 +81,7 @@ static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
*/
static inline struct xe_gt *xe_root_mmio_gt(struct xe_device *xe)
{
- return &xe_device_get_root_tile(xe)->primary_gt;
+ return xe_device_get_root_tile(xe)->primary_gt;
}
static inline bool xe_device_guc_submission_enabled(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 9b5a25a86234..7fa473d85be1 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -80,7 +80,7 @@ struct xe_tile {
/**
* @primary_gt: Primary GT
*/
- struct xe_gt primary_gt;
+ struct xe_gt *primary_gt;
/* TODO: Add media GT here */
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index b11f22b68bb8..7c87623ef5c5 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -194,7 +194,7 @@ void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
* TODO: Loop over each GT in tile once media GT support is
* re-added
*/
- struct xe_gt *gt = &ggtt->tile->primary_gt;
+ struct xe_gt *gt = ggtt->tile->primary_gt;
/* TODO: vfunc for GuC vs. non-GuC */
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 19f2cab3a57d..0abd0d912610 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -43,13 +43,18 @@
#include "xe_wa.h"
#include "xe_wopcm.h"
-int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt)
+struct xe_gt *xe_gt_alloc(struct xe_tile *tile)
{
- XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
+ struct xe_gt *gt;
+ gt = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*gt), GFP_KERNEL);
+ if (!gt)
+ return ERR_PTR(-ENOMEM);
+
+ gt->tile = tile;
gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", 0);
- return 0;
+ return gt;
}
void xe_gt_sanitize(struct xe_gt *gt)
diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
index c8abbeb0fb96..abcefd8cde78 100644
--- a/drivers/gpu/drm/xe/xe_gt.h
+++ b/drivers/gpu/drm/xe/xe_gt.h
@@ -16,7 +16,7 @@
for_each_if (((hwe__) = (gt__)->hw_engines + (id__)) && \
xe_hw_engine_is_valid((hwe__)))
-int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt);
+struct xe_gt *xe_gt_alloc(struct xe_tile *tile);
int xe_gt_init_early(struct xe_gt *gt);
int xe_gt_init_noalloc(struct xe_gt *gt);
int xe_gt_init(struct xe_gt *gt);
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index efa2cfc0ea2c..dad5dc984cb5 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -229,7 +229,7 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
m->batch_base_ofs = xe_migrate_vram_ofs(batch_addr);
if (xe->info.supports_usm) {
- batch = tile->primary_gt.usm.bb_pool->bo;
+ batch = tile->primary_gt->usm.bb_pool->bo;
batch_addr = xe_bo_addr(batch, 0, XE_PAGE_SIZE,
&is_vram);
m->usm_batch_base_ofs = xe_migrate_vram_ofs(batch_addr);
@@ -313,7 +313,7 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
struct xe_migrate *xe_migrate_init(struct xe_tile *tile)
{
struct xe_device *xe = tile_to_xe(tile);
- struct xe_gt *primary_gt = &tile->primary_gt;
+ struct xe_gt *primary_gt = tile->primary_gt;
struct xe_migrate *m;
struct xe_vm *vm;
struct ww_acquire_ctx ww;
@@ -546,7 +546,7 @@ static u32 xe_migrate_ccs_copy(struct xe_migrate *m,
u64 dst_ofs, bool dst_is_vram, u32 dst_size,
u64 ccs_ofs, bool copy_ccs)
{
- struct xe_gt *gt = &m->tile->primary_gt;
+ struct xe_gt *gt = m->tile->primary_gt;
u32 flush_flags = 0;
if (xe_device_has_flat_ccs(gt_to_xe(gt)) && !copy_ccs && dst_is_vram) {
@@ -601,7 +601,7 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
struct ttm_resource *src,
struct ttm_resource *dst)
{
- struct xe_gt *gt = &m->tile->primary_gt;
+ struct xe_gt *gt = m->tile->primary_gt;
struct xe_device *xe = gt_to_xe(gt);
struct dma_fence *fence = NULL;
u64 size = bo->size;
@@ -853,7 +853,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
struct ttm_resource *dst)
{
bool clear_vram = mem_type_is_vram(dst->mem_type);
- struct xe_gt *gt = &m->tile->primary_gt;
+ struct xe_gt *gt = m->tile->primary_gt;
struct xe_device *xe = gt_to_xe(gt);
struct dma_fence *fence = NULL;
u64 size = bo->size;
@@ -1128,7 +1128,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
{
const struct xe_migrate_pt_update_ops *ops = pt_update->ops;
struct xe_tile *tile = m->tile;
- struct xe_gt *gt = &tile->primary_gt;
+ struct xe_gt *gt = tile->primary_gt;
struct xe_device *xe = tile_to_xe(tile);
struct xe_sched_job *job;
struct dma_fence *fence;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 888f6b372547..bc0ed2a0e44f 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -541,9 +541,12 @@ static int xe_info_init(struct xe_device *xe,
tile->xe = xe;
tile->id = id;
- gt = &tile->primary_gt;
+ tile->primary_gt = xe_gt_alloc(tile);
+ if (IS_ERR(tile->primary_gt))
+ return PTR_ERR(tile->primary_gt);
+
+ gt = tile->primary_gt;
gt->info.id = id; /* FIXME: Determine sensible numbering */
- gt->tile = tile;
gt->info.type = XE_GT_TYPE_MAIN;
gt->info.__engine_mask = graphics_desc->hw_engine_mask;
if (MEDIA_VER(xe) < 13 && media_desc)
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index a606cd1a7e3a..60e4a97c78fb 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -1316,7 +1316,7 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e,
/* TLB invalidation must be done before signaling rebind */
if (rebind && !xe_vm_no_dma_fences(vma->vm)) {
- int err = invalidation_fence_init(&tile->primary_gt, ifence, fence,
+ int err = invalidation_fence_init(tile->primary_gt, ifence, fence,
vma);
if (err) {
dma_fence_put(fence);
@@ -1636,7 +1636,7 @@ __xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e
int err;
/* TLB invalidation must be done before signaling unbind */
- err = invalidation_fence_init(&tile->primary_gt, ifence, fence, vma);
+ err = invalidation_fence_init(tile->primary_gt, ifence, fence, vma);
if (err) {
dma_fence_put(fence);
kfree(ifence);
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index efe15841f047..ddf6057a61b9 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -1203,7 +1203,7 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
/* Kernel migration VM shouldn't have a circular loop.. */
if (!(flags & XE_VM_FLAG_MIGRATION)) {
for_each_tile(tile, xe, id) {
- struct xe_gt *gt = &tile->primary_gt;
+ struct xe_gt *gt = tile->primary_gt;
struct xe_vm *migrate_vm;
struct xe_engine *eng;
@@ -3371,7 +3371,7 @@ int xe_vm_invalidate_vma(struct xe_vma *vma)
* FIXME: We potentially need to invalidate multiple
* GTs within the tile
*/
- seqno[id] = xe_gt_tlb_invalidation_vma(&tile->primary_gt, NULL, vma);
+ seqno[id] = xe_gt_tlb_invalidation_vma(tile->primary_gt, NULL, vma);
if (seqno[id] < 0)
return seqno[id];
}
@@ -3379,7 +3379,7 @@ int xe_vm_invalidate_vma(struct xe_vma *vma)
for_each_tile(tile, xe, id) {
if (tile_needs_invalidate & BIT(id)) {
- ret = xe_gt_tlb_invalidation_wait(&tile->primary_gt, seqno[id]);
+ ret = xe_gt_tlb_invalidation_wait(tile->primary_gt, seqno[id]);
if (ret < 0)
return ret;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 18/30] drm/xe: Add media GT to tile
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (16 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 17/30] drm/xe: Allocate GT dynamically Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 19/30] drm/xe: Move display IRQ postinstall out of GT function Matt Roper
` (14 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Rodrigo Vivi
This media_gt pointer isn't actually allocated yet. Future patches will
start hooking it up at appropriate places in the code, and then creation
of the media GT will be added once those infrastructure changes are in
place.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 7fa473d85be1..76ac9bb99922 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -82,7 +82,12 @@ struct xe_tile {
*/
struct xe_gt *primary_gt;
- /* TODO: Add media GT here */
+ /**
+ * @media_gt: Media GT
+ *
+ * Only present on devices with media version >= 13.
+ */
+ struct xe_gt *media_gt;
/**
* @mmio: MMIO info for a tile.
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 19/30] drm/xe: Move display IRQ postinstall out of GT function
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (17 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 18/30] drm/xe: Add media GT to tile Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 20/30] drm/xe: Interrupts are delivered per-tile, not per-GT Matt Roper
` (13 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper, Rodrigo Vivi
Display interrupts are unrelated to the GT (and are also only relevant
to the root tile). Move the postinstall call up a level in the
callstack.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 628057497cd5..654c34a5b99a 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -490,8 +490,6 @@ void xe_gt_irq_postinstall(struct xe_gt *gt)
dg1_irq_postinstall(xe, gt);
else
xelp_irq_postinstall(xe, gt);
-
- xe_display_irq_postinstall(xe, gt);
}
static void xe_irq_postinstall(struct xe_device *xe)
@@ -501,6 +499,8 @@ static void xe_irq_postinstall(struct xe_device *xe)
for_each_gt(gt, xe, id)
xe_gt_irq_postinstall(gt);
+
+ xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));
}
static irq_handler_t xe_irq_handler(struct xe_device *xe)
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 20/30] drm/xe: Interrupts are delivered per-tile, not per-GT
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (18 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 19/30] drm/xe: Move display IRQ postinstall out of GT function Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-26 22:16 ` Lucas De Marchi
2023-05-30 6:36 ` Iddamsetty, Aravind
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 21/30] drm/xe/irq: Handle ASLE backlight interrupts at same time as display Matt Roper
` (12 subsequent siblings)
32 siblings, 2 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
IRQ delivery and handling needs to be handled on a per-tile basis. Note
that this is true even for the "GT interrupts" relating to engines and
GuCs --- the interrupts relating to both GTs get raised through a single
set of registers in the tile's sgunit range.
On true multi-tile platforms, interrupts on remote tiles are internally
forwarded to the root tile; the first thing the top-level interrupt
handler should do is consult the root tile's instance of
DG1_MSTR_TILE_INTR to determine which tile(s) had interrupts. This
register is also responsible for enabling/disabling top-level reporting
of any interrupts to the OS. Although this register technically exists
on all tiles, it should only be used on the root tile.
The (mis)use of struct xe_gt as a target for MMIO operations in the
driver makes the code somewhat confusing since we wind up needing a GT
pointer to handle programming that's unrelated to the GT. To mitigate
this confusion, all of the xe_gt structures used solely as an MMIO
target in interrupt code are renamed to 'mmio' so that it's clear that
the structure being passed does not necessarily relate to any specific
GT (primary or media) that we might be dealing with interrupts for.
Reworking the driver's MMIO handling to not be dependent on xe_gt is
planned as a future patch series.
Note that GT initialization code currently calls xe_gt_irq_postinstall()
in an attempt to enable the HWE interrupts for the GT being initialized.
Unfortunately xe_gt_irq_postinstall() doesn't really match its name and
does a bunch of other stuff unrelated to the GT interrupts (such as
enabling the top-level device interrupts). That will be addressed in
future patches.
v2:
- Clarify commit message with explanation of why DG1_MSTR_TILE_INTR is
only used on the root tile, even though it's an sgunit register that
is technically present in each tile's MMIO space. (Aravind)
- Also clarify that the xe_gt used as a target for MMIO operations may
or may not relate to the GT we're dealing with for interrupts.
(Lucas)
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt.c | 2 +-
drivers/gpu/drm/xe/xe_irq.c | 334 ++++++++++++++++++++----------------
drivers/gpu/drm/xe/xe_irq.h | 4 +-
3 files changed, 187 insertions(+), 153 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 0abd0d912610..290935e46059 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -304,7 +304,7 @@ static int gt_fw_domain_init(struct xe_gt *gt)
gt->info.engine_mask = gt->info.__engine_mask;
/* Enables per hw engine IRQs */
- xe_gt_irq_postinstall(gt);
+ xe_gt_irq_postinstall(gt_to_tile(gt));
/* Rerun MCR init as we now have hw engine list */
xe_gt_mcr_init(gt);
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 654c34a5b99a..ad2f73b2a031 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -27,60 +27,66 @@
#define IIR(offset) XE_REG(offset + 0x8)
#define IER(offset) XE_REG(offset + 0xc)
-static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
+static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
{
- u32 val = xe_mmio_read32(gt, reg);
+ u32 val = xe_mmio_read32(mmio, reg);
if (val == 0)
return;
- drm_WARN(>_to_xe(gt)->drm, 1,
+ drm_WARN(>_to_xe(mmio)->drm, 1,
"Interrupt register 0x%x is not zero: 0x%08x\n",
reg.addr, val);
- xe_mmio_write32(gt, reg, 0xffffffff);
- xe_mmio_read32(gt, reg);
- xe_mmio_write32(gt, reg, 0xffffffff);
- xe_mmio_read32(gt, reg);
+ xe_mmio_write32(mmio, reg, 0xffffffff);
+ xe_mmio_read32(mmio, reg);
+ xe_mmio_write32(mmio, reg, 0xffffffff);
+ xe_mmio_read32(mmio, reg);
}
/*
* Unmask and enable the specified interrupts. Does not check current state,
* so any bits not specified here will become masked and disabled.
*/
-static void unmask_and_enable(struct xe_gt *gt, u32 irqregs, u32 bits)
+static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)
{
+ struct xe_gt *mmio = tile->primary_gt;
+
/*
* If we're just enabling an interrupt now, it shouldn't already
* be raised in the IIR.
*/
- assert_iir_is_zero(gt, IIR(irqregs));
+ assert_iir_is_zero(mmio, IIR(irqregs));
- xe_mmio_write32(gt, IER(irqregs), bits);
- xe_mmio_write32(gt, IMR(irqregs), ~bits);
+ xe_mmio_write32(mmio, IER(irqregs), bits);
+ xe_mmio_write32(mmio, IMR(irqregs), ~bits);
/* Posting read */
- xe_mmio_read32(gt, IMR(irqregs));
+ xe_mmio_read32(mmio, IMR(irqregs));
}
/* Mask and disable all interrupts. */
-static void mask_and_disable(struct xe_gt *gt, u32 irqregs)
+static void mask_and_disable(struct xe_tile *tile, u32 irqregs)
{
- xe_mmio_write32(gt, IMR(irqregs), ~0);
+ struct xe_gt *mmio = tile->primary_gt;
+
+ xe_mmio_write32(mmio, IMR(irqregs), ~0);
/* Posting read */
- xe_mmio_read32(gt, IMR(irqregs));
+ xe_mmio_read32(mmio, IMR(irqregs));
- xe_mmio_write32(gt, IER(irqregs), 0);
+ xe_mmio_write32(mmio, IER(irqregs), 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- xe_mmio_write32(gt, IIR(irqregs), ~0);
- xe_mmio_read32(gt, IIR(irqregs));
- xe_mmio_write32(gt, IIR(irqregs), ~0);
- xe_mmio_read32(gt, IIR(irqregs));
+ xe_mmio_write32(mmio, IIR(irqregs), ~0);
+ xe_mmio_read32(mmio, IIR(irqregs));
+ xe_mmio_write32(mmio, IIR(irqregs), ~0);
+ xe_mmio_read32(mmio, IIR(irqregs));
}
-static u32 xelp_intr_disable(struct xe_gt *gt)
+static u32 xelp_intr_disable(struct xe_device *xe)
{
- xe_mmio_write32(gt, GFX_MSTR_IRQ, 0);
+ struct xe_gt *mmio = xe_root_mmio_gt(xe);
+
+ xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0);
/*
* Now with master disabled, get a sample of level indications
@@ -88,36 +94,41 @@ static u32 xelp_intr_disable(struct xe_gt *gt)
* New indications can and will light up during processing,
* and will generate new interrupt after enabling master.
*/
- return xe_mmio_read32(gt, GFX_MSTR_IRQ);
+ return xe_mmio_read32(mmio, GFX_MSTR_IRQ);
}
static u32
-gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
+gu_misc_irq_ack(struct xe_device *xe, const u32 master_ctl)
{
+ struct xe_gt *mmio = xe_root_mmio_gt(xe);
u32 iir;
if (!(master_ctl & GU_MISC_IRQ))
return 0;
- iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET));
+ iir = xe_mmio_read32(mmio, IIR(GU_MISC_IRQ_OFFSET));
if (likely(iir))
- xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET), iir);
+ xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir);
return iir;
}
-static inline void xelp_intr_enable(struct xe_gt *gt, bool stall)
+static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
{
- xe_mmio_write32(gt, GFX_MSTR_IRQ, MASTER_IRQ);
+ struct xe_gt *mmio = xe_root_mmio_gt(xe);
+
+ xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ);
if (stall)
- xe_mmio_read32(gt, GFX_MSTR_IRQ);
+ xe_mmio_read32(mmio, GFX_MSTR_IRQ);
}
-static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
+static void gt_irq_postinstall(struct xe_tile *tile)
{
+ struct xe_device *xe = tile_to_xe(tile);
+ struct xe_gt *mmio = tile->primary_gt;
u32 irqs, dmask, smask;
- u32 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
- u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
+ u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COMPUTE);
+ u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COPY);
if (xe_device_guc_submission_enabled(xe)) {
irqs = GT_RENDER_USER_INTERRUPT |
@@ -133,57 +144,57 @@ static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
smask = irqs << 16;
/* Enable RCS, BCS, VCS and VECS class interrupts. */
- xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
- xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
+ xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
+ xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
if (ccs_mask)
- xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
+ xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
- xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
- xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
+ xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
+ xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
if (bcs_mask & (BIT(1)|BIT(2)))
- xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
if (bcs_mask & (BIT(3)|BIT(4)))
- xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
if (bcs_mask & (BIT(5)|BIT(6)))
- xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
if (bcs_mask & (BIT(7)|BIT(8)))
- xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
- xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
- xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
- xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
if (ccs_mask & (BIT(0)|BIT(1)))
- xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
if (ccs_mask & (BIT(2)|BIT(3)))
- xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled.
*/
/* TODO: gt->pm_ier, gt->pm_imr */
- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
+ xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);
/* Same thing for GuC interrupts */
- xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
- xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);
+ xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
}
-static void xelp_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
+static void xelp_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
{
/* TODO: PCH */
- gt_irq_postinstall(xe, gt);
+ gt_irq_postinstall(tile);
- unmask_and_enable(gt, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
+ unmask_and_enable(tile, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
- xelp_intr_enable(gt, true);
+ xelp_intr_enable(xe, true);
}
static u32
gt_engine_identity(struct xe_device *xe,
- struct xe_gt *gt,
+ struct xe_gt *mmio,
const unsigned int bank,
const unsigned int bit)
{
@@ -192,7 +203,7 @@ gt_engine_identity(struct xe_device *xe,
lockdep_assert_held(&xe->irq.lock);
- xe_mmio_write32(gt, IIR_REG_SELECTOR(bank), BIT(bit));
+ xe_mmio_write32(mmio, IIR_REG_SELECTOR(bank), BIT(bit));
/*
* NB: Specs do not specify how long to spin wait,
@@ -200,7 +211,7 @@ gt_engine_identity(struct xe_device *xe,
*/
timeout_ts = (local_clock() >> 10) + 100;
do {
- ident = xe_mmio_read32(gt, INTR_IDENTITY_REG(bank));
+ ident = xe_mmio_read32(mmio, INTR_IDENTITY_REG(bank));
} while (!(ident & INTR_DATA_VALID) &&
!time_after32(local_clock() >> 10, timeout_ts));
@@ -210,7 +221,7 @@ gt_engine_identity(struct xe_device *xe,
return 0;
}
- xe_mmio_write32(gt, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
+ xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
return ident;
}
@@ -232,10 +243,32 @@ gt_other_irq_handler(struct xe_gt *gt, const u8 instance, const u16 iir)
}
}
-static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
+static struct xe_gt *pick_engine_gt(struct xe_tile *tile,
+ enum xe_engine_class class,
+ unsigned int instance)
+{
+ struct xe_device *xe = tile_to_xe(tile);
+
+ if (MEDIA_VER(xe) < 13)
+ return tile->primary_gt;
+
+ if (class == XE_ENGINE_CLASS_VIDEO_DECODE ||
+ class == XE_ENGINE_CLASS_VIDEO_ENHANCE)
+ return tile->media_gt;
+
+ if (class == XE_ENGINE_CLASS_OTHER &&
+ instance == OTHER_MEDIA_GUC_INSTANCE)
+ return tile->media_gt;
+
+ return tile->primary_gt;
+}
+
+static void gt_irq_handler(struct xe_tile *tile,
u32 master_ctl, long unsigned int *intr_dw,
u32 *identity)
{
+ struct xe_device *xe = tile_to_xe(tile);
+ struct xe_gt *mmio = tile->primary_gt;
unsigned int bank, bit;
u16 instance, intr_vec;
enum xe_engine_class class;
@@ -247,27 +280,26 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
if (!(master_ctl & GT_DW_IRQ(bank)))
continue;
- if (!xe_gt_is_media_type(gt)) {
- intr_dw[bank] =
- xe_mmio_read32(gt, GT_INTR_DW(bank));
- for_each_set_bit(bit, intr_dw + bank, 32)
- identity[bit] = gt_engine_identity(xe, gt,
- bank, bit);
- xe_mmio_write32(gt, GT_INTR_DW(bank),
- intr_dw[bank]);
- }
+ intr_dw[bank] = xe_mmio_read32(mmio, GT_INTR_DW(bank));
+ for_each_set_bit(bit, intr_dw + bank, 32)
+ identity[bit] = gt_engine_identity(xe, mmio, bank, bit);
+ xe_mmio_write32(mmio, GT_INTR_DW(bank), intr_dw[bank]);
for_each_set_bit(bit, intr_dw + bank, 32) {
+ struct xe_gt *engine_gt;
+
class = INTR_ENGINE_CLASS(identity[bit]);
instance = INTR_ENGINE_INSTANCE(identity[bit]);
intr_vec = INTR_ENGINE_INTR(identity[bit]);
+ engine_gt = pick_engine_gt(tile, class, instance);
+
if (class == XE_ENGINE_CLASS_OTHER) {
- gt_other_irq_handler(gt, instance, intr_vec);
+ gt_other_irq_handler(engine_gt, instance, intr_vec);
continue;
}
- hwe = xe_gt_hw_engine(gt, class, instance, false);
+ hwe = xe_gt_hw_engine(engine_gt, class, instance, false);
if (!hwe)
continue;
@@ -285,24 +317,24 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
static irqreturn_t xelp_irq_handler(int irq, void *arg)
{
struct xe_device *xe = arg;
- struct xe_gt *gt = xe_root_mmio_gt(xe);
+ struct xe_tile *tile = xe_device_get_root_tile(xe);
u32 master_ctl, gu_misc_iir;
long unsigned int intr_dw[2];
u32 identity[32];
- master_ctl = xelp_intr_disable(gt);
+ master_ctl = xelp_intr_disable(xe);
if (!master_ctl) {
- xelp_intr_enable(gt, false);
+ xelp_intr_enable(xe, false);
return IRQ_NONE;
}
- gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
+ gt_irq_handler(tile, master_ctl, intr_dw, identity);
xe_display_irq_handler(xe, master_ctl);
- gu_misc_iir = gu_misc_irq_ack(gt, master_ctl);
+ gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
- xelp_intr_enable(gt, false);
+ xelp_intr_enable(xe, false);
xe_display_irq_enable(xe, gu_misc_iir);
@@ -311,38 +343,38 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
static u32 dg1_intr_disable(struct xe_device *xe)
{
- struct xe_gt *gt = xe_root_mmio_gt(xe);
+ struct xe_gt *mmio = xe_root_mmio_gt(xe);
u32 val;
/* First disable interrupts */
- xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, 0);
+ xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0);
/* Get the indication levels and ack the master unit */
- val = xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
+ val = xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
if (unlikely(!val))
return 0;
- xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, val);
+ xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, val);
return val;
}
static void dg1_intr_enable(struct xe_device *xe, bool stall)
{
- struct xe_gt *gt = xe_root_mmio_gt(xe);
+ struct xe_gt *mmio = xe_root_mmio_gt(xe);
- xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
+ xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
if (stall)
- xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
+ xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
}
-static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
+static void dg1_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
{
- gt_irq_postinstall(xe, gt);
+ gt_irq_postinstall(tile);
- unmask_and_enable(gt, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
+ unmask_and_enable(tile, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
- if (gt->info.id == XE_GT0)
+ if (tile->id == 0)
dg1_intr_enable(xe, true);
}
@@ -354,8 +386,8 @@ static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
struct xe_device *xe = arg;
- struct xe_gt *gt;
- u32 master_tile_ctl, master_ctl = 0, tile0_master_ctl = 0, gu_misc_iir;
+ struct xe_tile *tile;
+ u32 master_tile_ctl, master_ctl = 0, gu_misc_iir = 0;
long unsigned int intr_dw[2];
u32 identity[32];
u8 id;
@@ -368,12 +400,13 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
return IRQ_NONE;
}
- for_each_gt(gt, xe, id) {
- if ((master_tile_ctl & DG1_MSTR_TILE(gt_to_tile(gt)->id)) == 0)
+ for_each_tile(tile, xe, id) {
+ struct xe_gt *mmio = tile->primary_gt;
+
+ if ((master_tile_ctl & DG1_MSTR_TILE(tile->id)) == 0)
continue;
- if (!xe_gt_is_media_type(gt))
- master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ);
+ master_ctl = xe_mmio_read32(mmio, GFX_MSTR_IRQ);
/*
* We might be in irq handler just when PCIe DPC is initiated
@@ -381,124 +414,125 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
* irq as device is inaccessible.
*/
if (master_ctl == REG_GENMASK(31, 0)) {
- dev_dbg(gt_to_xe(gt)->drm.dev,
+ dev_dbg(tile_to_xe(tile)->drm.dev,
"Ignore this IRQ as device might be in DPC containment.\n");
return IRQ_HANDLED;
}
- if (!xe_gt_is_media_type(gt))
- xe_mmio_write32(gt, GFX_MSTR_IRQ, master_ctl);
- gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
+ xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);
+
+ gt_irq_handler(tile, master_ctl, intr_dw, identity);
/*
- * Save primary tile's master interrupt register for display
- * processing below.
+ * Display interrupts (including display backlight operations
+ * that get reported as Gunit GSE) would only be hooked up to
+ * the primary tile.
*/
- if (id == 0)
- tile0_master_ctl = master_ctl;
+ if (id == 0) {
+ xe_display_irq_handler(xe, master_ctl);
+ gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
+ }
}
- xe_display_irq_handler(xe, tile0_master_ctl);
-
- /* Gunit GSE interrupts can trigger display backlight operations */
- gu_misc_iir = gu_misc_irq_ack(gt, tile0_master_ctl);
-
dg1_intr_enable(xe, false);
-
xe_display_irq_enable(xe, gu_misc_iir);
return IRQ_HANDLED;
}
-static void gt_irq_reset(struct xe_gt *gt)
+static void gt_irq_reset(struct xe_tile *tile)
{
- u32 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
- u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
+ struct xe_gt *mmio = tile->primary_gt;
+
+ u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
+ XE_ENGINE_CLASS_COMPUTE);
+ u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
+ XE_ENGINE_CLASS_COPY);
/* Disable RCS, BCS, VCS and VECS class engines. */
- xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, 0);
- xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, 0);
+ xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, 0);
+ xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, 0);
if (ccs_mask)
- xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, 0);
+ xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, 0);
/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
- xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~0);
- xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~0);
if (bcs_mask & (BIT(1)|BIT(2)))
- xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
if (bcs_mask & (BIT(3)|BIT(4)))
- xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
if (bcs_mask & (BIT(5)|BIT(6)))
- xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
if (bcs_mask & (BIT(7)|BIT(8)))
- xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
- xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~0);
- xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~0);
- xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~0);
if (ccs_mask & (BIT(0)|BIT(1)))
- xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~0);
if (ccs_mask & (BIT(2)|BIT(3)))
- xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~0);
- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
- xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
- xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
+ xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);
+ xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);
+ xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
}
-static void xelp_irq_reset(struct xe_gt *gt)
+static void xelp_irq_reset(struct xe_tile *tile)
{
- xelp_intr_disable(gt);
+ xelp_intr_disable(tile_to_xe(tile));
- gt_irq_reset(gt);
+ gt_irq_reset(tile);
- mask_and_disable(gt, GU_MISC_IRQ_OFFSET);
- mask_and_disable(gt, PCU_IRQ_OFFSET);
+ mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
+ mask_and_disable(tile, PCU_IRQ_OFFSET);
}
-static void dg1_irq_reset(struct xe_gt *gt)
+static void dg1_irq_reset(struct xe_tile *tile)
{
- if (gt->info.id == 0)
- dg1_intr_disable(gt_to_xe(gt));
+ if (tile->id == 0)
+ dg1_intr_disable(tile_to_xe(tile));
- gt_irq_reset(gt);
+ gt_irq_reset(tile);
- mask_and_disable(gt, GU_MISC_IRQ_OFFSET);
- mask_and_disable(gt, PCU_IRQ_OFFSET);
+ mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
+ mask_and_disable(tile, PCU_IRQ_OFFSET);
}
static void xe_irq_reset(struct xe_device *xe)
{
- struct xe_gt *gt;
+ struct xe_tile *tile;
u8 id;
- for_each_gt(gt, xe, id) {
+ for_each_tile(tile, xe, id) {
if (GRAPHICS_VERx100(xe) >= 1210)
- dg1_irq_reset(gt);
+ dg1_irq_reset(tile);
else
- xelp_irq_reset(gt);
+ xelp_irq_reset(tile);
}
xe_display_irq_reset(xe);
}
-void xe_gt_irq_postinstall(struct xe_gt *gt)
+void xe_gt_irq_postinstall(struct xe_tile *tile)
{
- struct xe_device *xe = gt_to_xe(gt);
+ struct xe_device *xe = tile_to_xe(tile);
if (GRAPHICS_VERx100(xe) >= 1210)
- dg1_irq_postinstall(xe, gt);
+ dg1_irq_postinstall(xe, tile);
else
- xelp_irq_postinstall(xe, gt);
+ xelp_irq_postinstall(xe, tile);
}
static void xe_irq_postinstall(struct xe_device *xe)
{
- struct xe_gt *gt;
+ struct xe_tile *tile;
u8 id;
- for_each_gt(gt, xe, id)
- xe_gt_irq_postinstall(gt);
+ for_each_tile(tile, xe, id)
+ xe_gt_irq_postinstall(tile);
xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));
}
diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
index 34ecf22b32d3..69113c21e1cd 100644
--- a/drivers/gpu/drm/xe/xe_irq.h
+++ b/drivers/gpu/drm/xe/xe_irq.h
@@ -7,10 +7,10 @@
#define _XE_IRQ_H_
struct xe_device;
-struct xe_gt;
+struct xe_tile;
int xe_irq_install(struct xe_device *xe);
-void xe_gt_irq_postinstall(struct xe_gt *gt);
+void xe_gt_irq_postinstall(struct xe_tile *tile);
void xe_irq_shutdown(struct xe_device *xe);
void xe_irq_suspend(struct xe_device *xe);
void xe_irq_resume(struct xe_device *xe);
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 21/30] drm/xe/irq: Handle ASLE backlight interrupts at same time as display
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (19 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 20/30] drm/xe: Interrupts are delivered per-tile, not per-GT Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 22/30] drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt mask Matt Roper
` (11 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
Our only use of GUnit interrupts is to handle ASLE backlight operations
that are reported as GUnit GSE interrupts. Move the enable/disable of
these interrupts adjacent to display interrupts.
In the future we may want to even move these inside the
xe_display_irq_*() functions. But since these rely on xe_irq static
functions like mask_and_disable() it's easier to keep them separate for
now.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_irq.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index ad2f73b2a031..c069e374a947 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -187,8 +187,6 @@ static void xelp_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
gt_irq_postinstall(tile);
- unmask_and_enable(tile, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
-
xelp_intr_enable(xe, true);
}
@@ -372,8 +370,6 @@ static void dg1_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
{
gt_irq_postinstall(tile);
- unmask_and_enable(tile, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
-
if (tile->id == 0)
dg1_intr_enable(xe, true);
}
@@ -486,7 +482,6 @@ static void xelp_irq_reset(struct xe_tile *tile)
gt_irq_reset(tile);
- mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
mask_and_disable(tile, PCU_IRQ_OFFSET);
}
@@ -497,7 +492,6 @@ static void dg1_irq_reset(struct xe_tile *tile)
gt_irq_reset(tile);
- mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
mask_and_disable(tile, PCU_IRQ_OFFSET);
}
@@ -513,6 +507,8 @@ static void xe_irq_reset(struct xe_device *xe)
xelp_irq_reset(tile);
}
+ tile = xe_device_get_root_tile(xe);
+ mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
xe_display_irq_reset(xe);
}
@@ -535,6 +531,13 @@ static void xe_irq_postinstall(struct xe_device *xe)
xe_gt_irq_postinstall(tile);
xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));
+
+ /*
+ * ASLE backlight operations are reported via GUnit GSE interrupts
+ * on the root tile.
+ */
+ unmask_and_enable(xe_device_get_root_tile(xe),
+ GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
}
static irq_handler_t xe_irq_handler(struct xe_device *xe)
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 22/30] drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt mask
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (20 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 21/30] drm/xe/irq: Handle ASLE backlight interrupts at same time as display Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 23/30] drm/xe/irq: Untangle postinstall functions Matt Roper
` (10 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
Although primary and media GuC share a single interrupt enable bit, they
each have distinct bits in the mask register. Although we always enable
interrupts for the primary GuC before the media GuC today (and never
disable either of them), this might not always be the case in the
future, so use a RMW when updating the mask register to ensure the other
GuC's mask doesn't get clobbered.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_guc.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 71f18b32d09b..a14d71bc8202 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -551,12 +551,15 @@ static void guc_enable_irq(struct xe_guc *guc)
REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) :
REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
+ /* Primary GuC and media GuC share a single enable bit */
xe_mmio_write32(gt, GUC_SG_INTR_ENABLE,
REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST));
- if (xe_gt_is_media_type(gt))
- xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0);
- else
- xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~events);
+
+ /*
+ * There are separate mask bits for primary and media GuCs, so use
+ * a RMW operation to avoid clobbering the other GuC's setting.
+ */
+ xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0);
}
int xe_guc_enable_communication(struct xe_guc *guc)
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 23/30] drm/xe/irq: Untangle postinstall functions
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (21 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 22/30] drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt mask Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 24/30] drm/xe: Replace xe_gt_irq_postinstall with xe_irq_enable_hwe Matt Roper
` (9 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
The xe_irq_postinstall() never actually gets called after installing the
interrupt handler. This oversight seems to get papered over due to the
fact that the (misnamed) xe_gt_irq_postinstall does more than it really
should and gets called in the middle of the GT initialization. The
callstack for postinstall is also a bit muddled with top-level device
interrupt enablement happening within platform-specific functions called
from the per-tile xe_gt_irq_postinstall() function.
Clean this all up by adding the missing call to xe_irq_postinstall()
after installing the interrupt handler and pull top-level irq enablement
up to xe_irq_postinstall where we'd expect it to be.
The xe_gt_irq_postinstall() function is still a bit misnamed here; an
upcoming patch will refocus its purpose and rename it.
v2:
- Squash in patch to actually call xe_irq_postinstall() after
installing the interrupt handler.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_irq.c | 37 +++++++++----------------------------
1 file changed, 9 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index c069e374a947..85bb9bd6b6be 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -122,7 +122,7 @@ static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
xe_mmio_read32(mmio, GFX_MSTR_IRQ);
}
-static void gt_irq_postinstall(struct xe_tile *tile)
+void xe_gt_irq_postinstall(struct xe_tile *tile)
{
struct xe_device *xe = tile_to_xe(tile);
struct xe_gt *mmio = tile->primary_gt;
@@ -181,15 +181,6 @@ static void gt_irq_postinstall(struct xe_tile *tile)
xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
}
-static void xelp_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
-{
- /* TODO: PCH */
-
- gt_irq_postinstall(tile);
-
- xelp_intr_enable(xe, true);
-}
-
static u32
gt_engine_identity(struct xe_device *xe,
struct xe_gt *mmio,
@@ -366,14 +357,6 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
}
-static void dg1_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
-{
- gt_irq_postinstall(tile);
-
- if (tile->id == 0)
- dg1_intr_enable(xe, true);
-}
-
/*
* Top-level interrupt handler for Xe_LP+ and beyond. These platforms have
* a "master tile" interrupt register which must be consulted before the
@@ -512,16 +495,6 @@ static void xe_irq_reset(struct xe_device *xe)
xe_display_irq_reset(xe);
}
-void xe_gt_irq_postinstall(struct xe_tile *tile)
-{
- struct xe_device *xe = tile_to_xe(tile);
-
- if (GRAPHICS_VERx100(xe) >= 1210)
- dg1_irq_postinstall(xe, tile);
- else
- xelp_irq_postinstall(xe, tile);
-}
-
static void xe_irq_postinstall(struct xe_device *xe)
{
struct xe_tile *tile;
@@ -538,6 +511,12 @@ static void xe_irq_postinstall(struct xe_device *xe)
*/
unmask_and_enable(xe_device_get_root_tile(xe),
GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
+
+ /* Enable top-level interrupts */
+ if (GRAPHICS_VERx100(xe) >= 1210)
+ dg1_intr_enable(xe, true);
+ else
+ xelp_intr_enable(xe, true);
}
static irq_handler_t xe_irq_handler(struct xe_device *xe)
@@ -588,6 +567,8 @@ int xe_irq_install(struct xe_device *xe)
return err;
}
+ xe_irq_postinstall(xe);
+
err = drmm_add_action_or_reset(&xe->drm, irq_uninstall, xe);
if (err)
return err;
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 24/30] drm/xe: Replace xe_gt_irq_postinstall with xe_irq_enable_hwe
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (22 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 23/30] drm/xe/irq: Untangle postinstall functions Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-26 22:20 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 25/30] drm/xe: Invalidate TLB on all affected GTs during GGTT updates Matt Roper
` (8 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
The majority of xe_gt_irq_postinstall() is really focused on the
hardware engine interrupts; other GT-related interrupts such as the GuC
are enabled/disabled independently. Renaming the function and making it
truly GT-specific will make it more clear what the intended focus is.
Disabling/masking of other interrupts (such as GuC interrupts) is
unnecessary since that has already happened during the irq_reset stage,
and doing so will become harmful once the media GT is re-enabled since
calls to xe_gt_irq_postinstall during media GT initialization would
incorrectly disable the primary GT's GuC interrupts.
Also, since this function is called from gt_fw_domain_init(), it's not
necessary to also call it earlier during xe_irq_postinstall; just
xe_irq_resume to handle runtime resume should be sufficient.
v2:
- Drop unnecessary !gt check. (Lucas)
- Reword some comments about enable/unmask for clarity. (Lucas)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt.c | 4 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 1 +
drivers/gpu/drm/xe/xe_irq.c | 87 +++++++++++++++----------------
drivers/gpu/drm/xe/xe_irq.h | 3 +-
4 files changed, 48 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 290935e46059..b7bf8c01b4fe 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -303,8 +303,8 @@ static int gt_fw_domain_init(struct xe_gt *gt)
/* XXX: Fake that we pull the engine mask from hwconfig blob */
gt->info.engine_mask = gt->info.__engine_mask;
- /* Enables per hw engine IRQs */
- xe_gt_irq_postinstall(gt_to_tile(gt));
+ /* Enable per hw engine IRQs */
+ xe_irq_enable_hwe(gt);
/* Rerun MCR init as we now have hw engine list */
xe_gt_mcr_init(gt);
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index ab25513b753c..5a345b24b9a2 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -17,6 +17,7 @@
#include "xe_gt.h"
#include "xe_gt_topology.h"
#include "xe_hw_fence.h"
+#include "xe_irq.h"
#include "xe_lrc.h"
#include "xe_macros.h"
#include "xe_mmio.h"
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 85bb9bd6b6be..b4ed1e4a3388 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -122,13 +122,12 @@ static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
xe_mmio_read32(mmio, GFX_MSTR_IRQ);
}
-void xe_gt_irq_postinstall(struct xe_tile *tile)
+/* Enable/unmask the HWE interrupts for a specific GT's engines. */
+void xe_irq_enable_hwe(struct xe_gt *gt)
{
- struct xe_device *xe = tile_to_xe(tile);
- struct xe_gt *mmio = tile->primary_gt;
+ struct xe_device *xe = gt_to_xe(gt);
+ u32 ccs_mask, bcs_mask;
u32 irqs, dmask, smask;
- u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COMPUTE);
- u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COPY);
if (xe_device_guc_submission_enabled(xe)) {
irqs = GT_RENDER_USER_INTERRUPT |
@@ -140,45 +139,44 @@ void xe_gt_irq_postinstall(struct xe_tile *tile)
GT_WAIT_SEMAPHORE_INTERRUPT;
}
+ ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
+ bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
+
dmask = irqs << 16 | irqs;
smask = irqs << 16;
- /* Enable RCS, BCS, VCS and VECS class interrupts. */
- xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
- xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
- if (ccs_mask)
- xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
+ if (!xe_gt_is_media_type(gt)) {
+ /* Enable interrupts for each engine class */
+ xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
+ if (ccs_mask)
+ xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
- /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
- xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
- xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
- if (bcs_mask & (BIT(1)|BIT(2)))
- xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
- if (bcs_mask & (BIT(3)|BIT(4)))
- xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
- if (bcs_mask & (BIT(5)|BIT(6)))
- xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
- if (bcs_mask & (BIT(7)|BIT(8)))
- xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
- xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
- xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
- xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
- if (ccs_mask & (BIT(0)|BIT(1)))
- xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
- if (ccs_mask & (BIT(2)|BIT(3)))
- xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
+ /* Unmask interrupts for each engine instance */
+ xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
+ xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
+ if (bcs_mask & (BIT(1)|BIT(2)))
+ xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
+ if (bcs_mask & (BIT(3)|BIT(4)))
+ xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
+ if (bcs_mask & (BIT(5)|BIT(6)))
+ xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
+ if (bcs_mask & (BIT(7)|BIT(8)))
+ xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
+ if (ccs_mask & (BIT(0)|BIT(1)))
+ xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
+ if (ccs_mask & (BIT(2)|BIT(3)))
+ xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
+ }
- /*
- * RPS interrupts will get enabled/disabled on demand when RPS itself
- * is enabled/disabled.
- */
- /* TODO: gt->pm_ier, gt->pm_imr */
- xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
- xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);
+ if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
+ /* Enable interrupts for each engine class */
+ xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
- /* Same thing for GuC interrupts */
- xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);
- xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
+ /* Unmask interrupts for each engine instance */
+ xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
+ xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
+ xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
+ }
}
static u32
@@ -497,12 +495,6 @@ static void xe_irq_reset(struct xe_device *xe)
static void xe_irq_postinstall(struct xe_device *xe)
{
- struct xe_tile *tile;
- u8 id;
-
- for_each_tile(tile, xe, id)
- xe_gt_irq_postinstall(tile);
-
xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));
/*
@@ -591,9 +583,16 @@ void xe_irq_suspend(struct xe_device *xe)
void xe_irq_resume(struct xe_device *xe)
{
+ struct xe_gt *gt;
+ int id;
+
spin_lock_irq(&xe->irq.lock);
xe->irq.enabled = true;
xe_irq_reset(xe);
xe_irq_postinstall(xe);
+
+ for_each_gt(gt, xe, id)
+ xe_irq_enable_hwe(gt);
+
spin_unlock_irq(&xe->irq.lock);
}
diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
index 69113c21e1cd..bc42bc90d967 100644
--- a/drivers/gpu/drm/xe/xe_irq.h
+++ b/drivers/gpu/drm/xe/xe_irq.h
@@ -8,11 +8,12 @@
struct xe_device;
struct xe_tile;
+struct xe_gt;
int xe_irq_install(struct xe_device *xe);
-void xe_gt_irq_postinstall(struct xe_tile *tile);
void xe_irq_shutdown(struct xe_device *xe);
void xe_irq_suspend(struct xe_device *xe);
void xe_irq_resume(struct xe_device *xe);
+void xe_irq_enable_hwe(struct xe_gt *gt);
#endif
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 25/30] drm/xe: Invalidate TLB on all affected GTs during GGTT updates
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (23 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 24/30] drm/xe: Replace xe_gt_irq_postinstall with xe_irq_enable_hwe Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-22 9:02 ` Das, Nirmoy
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 26/30] drm/xe/tlb: Obtain forcewake when doing GGTT TLB invalidations Matt Roper
` (7 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
The GGTT is part of the tile and is shared by the primary and media GTs
on platforms with a standalone media architecture. However each of
these GTs has its own TLBs caching the page table lookups, and each
needs to be invalidated separately.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_ggtt.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 7c87623ef5c5..31f958613c2f 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -188,13 +188,10 @@ int xe_ggtt_init(struct xe_ggtt *ggtt)
#define PVC_GUC_TLB_INV_DESC1 XE_REG(0xcf80)
#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
-void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
+static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)
{
- /*
- * TODO: Loop over each GT in tile once media GT support is
- * re-added
- */
- struct xe_gt *gt = ggtt->tile->primary_gt;
+ if (!gt)
+ return;
/* TODO: vfunc for GuC vs. non-GuC */
@@ -219,6 +216,13 @@ void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
}
}
+void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
+{
+ /* Each GT in a tile has its own TLB to cache GGTT lookups */
+ ggtt_invalidate_gt_tlb(ggtt->tile->primary_gt);
+ ggtt_invalidate_gt_tlb(ggtt->tile->media_gt);
+}
+
void xe_ggtt_printk(struct xe_ggtt *ggtt, const char *prefix)
{
u64 addr, scratch_pte;
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 26/30] drm/xe/tlb: Obtain forcewake when doing GGTT TLB invalidations
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (24 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 25/30] drm/xe: Invalidate TLB on all affected GTs during GGTT updates Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-22 11:47 ` Das, Nirmoy
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 27/30] drm/xe: Allow GT looping and lookup on standalone media Matt Roper
` (6 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, matthew.d.roper
Updates to the GGTT can happen when there are no in-flight jobs keeping
the hardware awake. If the GT is powered down when invalidation is
requested, we will not be able to communicate with the GuC (or MMIO) and
the invalidation request will go missing. Explicitly grab GT forcewake
to ensure the GT and GuC are powered up during the TLB invalidation.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_ggtt.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 31f958613c2f..8f8d0f6a82cd 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -193,6 +193,13 @@ static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)
if (!gt)
return;
+ /*
+ * Invalidation can happen when there's no in-flight work keeping the
+ * GT awake. We need to explicitly grab forcewake to ensure the GT
+ * and GuC are accessible.
+ */
+ xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+
/* TODO: vfunc for GuC vs. non-GuC */
if (gt->uc.guc.submission_state.enabled) {
@@ -214,6 +221,8 @@ static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)
xe_mmio_write32(gt, GUC_TLB_INV_CR,
GUC_TLB_INV_CR_INVALIDATE);
}
+
+ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
}
void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 27/30] drm/xe: Allow GT looping and lookup on standalone media
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (25 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 26/30] drm/xe/tlb: Obtain forcewake when doing GGTT TLB invalidations Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-26 22:37 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 28/30] drm/xe: Update query uapi to support " Matt Roper
` (5 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Allow xe_device_get_gt() and for_each_gt() to operate as expected on
platforms with standalone media.
FIXME: We need to figure out a consistent ID scheme for GTs. At the
moment our platforms either have multi-tile (i.e., PVC) or standalone
media (MTL) but not both. If a future platform supports both of these
capabilities at the same time, how will we number the GTs of the
platform? primary-primary-media-media? primary-media-primary-media?
For that matter should we even still be exposing the concept of 'GT' to
userspace or should that switch to tile instead (and keep the hardware's
separation of render and media an internal implementation detail like it
is on i915)? If we only expose tiles to userspace and not GTs, then we
may not even need per-GT ID numbers anymore.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_device.h | 27 +++++++++++++++++++++------
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 156c62ac0381..e0085fcd3f47 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -55,16 +55,27 @@ static inline struct xe_tile *xe_device_get_root_tile(struct xe_device *xe)
static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
{
+ struct xe_tile *root_tile = xe_device_get_root_tile(xe);
struct xe_gt *gt;
- XE_BUG_ON(gt_id > XE_MAX_TILES_PER_DEVICE);
+ if (drm_WARN_ON(&xe->drm, gt_id > XE_MAX_TILES_PER_DEVICE))
+ return root_tile->primary_gt;
- gt = xe->tiles[gt_id].primary_gt;
- if (drm_WARN_ON(&xe->drm, !gt))
+ /*
+ * FIXME: This only works for now because multi-tile and standalone
+ * media are mutually exclusive on the platforms we have today.
+ */
+ if (MEDIA_VER(xe) >= 13) {
+ gt = gt_id ? root_tile->media_gt : root_tile->primary_gt;
+ } else {
+ gt = xe->tiles[gt_id].primary_gt;
+ }
+
+ if (!gt)
return NULL;
- XE_BUG_ON(gt->info.id != gt_id);
- XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
+ drm_WARN_ON(&xe->drm, gt->info.id != gt_id);
+ drm_WARN_ON(&xe->drm, gt->info.type == XE_GT_TYPE_UNINITIALIZED);
return gt;
}
@@ -98,8 +109,12 @@ static inline void xe_device_guc_submission_disable(struct xe_device *xe)
for ((id__) = 0; (id__) < (xe__)->info.tile_count; (id__++)) \
for_each_if ((tile__) = &(xe__)->tiles[(id__)])
+/*
+ * FIXME: This only works for now since multi-tile and standalone media
+ * happen to be mutually exclusive. Future platforms may change this...
+ */
#define for_each_gt(gt__, xe__, id__) \
- for ((id__) = 0; (id__) < (xe__)->info.tile_count; (id__++)) \
+ for ((id__) = 0; (id__) < (xe__)->info.tile_count + (MEDIA_VER(xe__) >= 13 ? 1 : 0); (id__++)) \
for_each_if ((gt__) = xe_device_get_gt((xe__), (id__)))
static inline struct xe_force_wake * gt_to_fw(struct xe_gt *gt)
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 28/30] drm/xe: Update query uapi to support standalone media
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (26 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 27/30] drm/xe: Allow GT looping and lookup on standalone media Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 29/30] drm/xe: Reinstate media GT support Matt Roper
` (4 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Now that a higher GT count can result from either multiple tiles (with
one GT each) or an extra media GT within the root tile, we need to
update the query code slightly to stop looking at tile_count.
FIXME: As noted previously, we need to decide on a formal direction for
exposing tiles and/or GTs to userspace.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_query.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index 49fff425adcd..c7ccac9ce581 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -26,6 +26,18 @@ static const enum xe_engine_class xe_to_user_engine_class[] = {
[XE_ENGINE_CLASS_COMPUTE] = DRM_XE_ENGINE_CLASS_COMPUTE,
};
+static int num_gt(struct xe_device *xe)
+{
+ int num = xe->info.tile_count;
+
+ if (xe_device_get_root_tile(xe)->media_gt) {
+ drm_WARN_ON(&xe->drm, num > 1);
+ num++;
+ }
+
+ return num;
+}
+
static size_t calc_hw_engine_info_size(struct xe_device *xe)
{
struct xe_hw_engine *hwe;
@@ -192,7 +204,7 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query)
xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
config->info[XE_QUERY_CONFIG_VA_BITS] = 12 +
(9 * (xe->info.vm_max_level + 1));
- config->info[XE_QUERY_CONFIG_GT_COUNT] = xe->info.tile_count;
+ config->info[XE_QUERY_CONFIG_GT_COUNT] = num_gt(xe);
config->info[XE_QUERY_CONFIG_MEM_REGION_COUNT] =
hweight_long(xe->info.mem_region_mask);
config->info[XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY] =
@@ -211,7 +223,7 @@ static int query_gts(struct xe_device *xe, struct drm_xe_device_query *query)
{
struct xe_gt *gt;
size_t size = sizeof(struct drm_xe_query_gts) +
- xe->info.tile_count * sizeof(struct drm_xe_query_gt);
+ num_gt(xe) * sizeof(struct drm_xe_query_gt);
struct drm_xe_query_gts __user *query_ptr =
u64_to_user_ptr(query->data);
struct drm_xe_query_gts *gts;
@@ -228,14 +240,12 @@ static int query_gts(struct xe_device *xe, struct drm_xe_device_query *query)
if (XE_IOCTL_ERR(xe, !gts))
return -ENOMEM;
- gts->num_gt = xe->info.tile_count;
+ gts->num_gt = num_gt(xe);
for_each_gt(gt, xe, id) {
- if (id == 0)
- gts->gts[id].type = XE_QUERY_GT_TYPE_MAIN;
- else if (xe_gt_is_media_type(gt))
+ if (xe_gt_is_media_type(gt))
gts->gts[id].type = XE_QUERY_GT_TYPE_MEDIA;
else
- gts->gts[id].type = XE_QUERY_GT_TYPE_REMOTE;
+ gts->gts[id].type = XE_QUERY_GT_TYPE_MAIN;
gts->gts[id].instance = id;
gts->gts[id].clock_freq = gt->info.clock_freq;
if (!IS_DGFX(xe))
@@ -290,7 +300,7 @@ static int query_hwconfig(struct xe_device *xe,
static size_t calc_topo_query_size(struct xe_device *xe)
{
- return xe->info.tile_count *
+ return num_gt(xe) *
(3 * sizeof(struct drm_xe_query_topology_mask) +
sizeof_field(struct xe_gt, fuse_topo.g_dss_mask) +
sizeof_field(struct xe_gt, fuse_topo.c_dss_mask) +
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 29/30] drm/xe: Reinstate media GT support
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (27 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 28/30] drm/xe: Update query uapi to support " Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-26 22:46 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 30/30] drm/xe: Add kerneldoc description of multi-tile devices Matt Roper
` (3 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Now that tiles and GTs are handled separately and other prerequisite
changes are in place, we're ready to re-enable the media GT.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 8 ++++++++
drivers/gpu/drm/xe/xe_pci.c | 26 +++++++++++++++++++++++++-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 4d87f1fe010d..26247725e0d8 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -8,6 +8,14 @@
#include "regs/xe_reg_defs.h"
+/*
+ * The GSI register range [0x0 - 0x40000) is replicated at a higher offset
+ * for the media GT. xe_mmio and xe_gt_mcr functions will automatically
+ * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT.
+ */
+#define MEDIA_GT_GSI_OFFSET 0x380000
+#define MEDIA_GT_GSI_LENGTH 0x40000
+
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 XE_REG(0xd00)
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index bc0ed2a0e44f..890625598209 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -552,7 +552,31 @@ static int xe_info_init(struct xe_device *xe,
if (MEDIA_VER(xe) < 13 && media_desc)
gt->info.__engine_mask |= media_desc->hw_engine_mask;
- /* TODO: Init media GT, if present */
+ if (MEDIA_VER(xe) < 13 || !media_desc)
+ continue;
+
+ /*
+ * Allocate and setup media GT for platforms with standalone
+ * media.
+ */
+ tile->media_gt = xe_gt_alloc(tile);
+ if (IS_ERR(tile->media_gt))
+ return PTR_ERR(tile->media_gt);
+
+ gt = tile->media_gt;
+ gt->info.type = XE_GT_TYPE_MEDIA;
+ gt->info.__engine_mask = media_desc->hw_engine_mask;
+ gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET;
+ gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH;
+
+ /*
+ * FIXME: At the moment multi-tile and standalone media are
+ * mutually exclusive on current platforms. We'll need to
+ * come up with a better way to number GTs if we ever wind
+ * up with platforms that support both together.
+ */
+ drm_WARN_ON(&xe->drm, id != 0);
+ gt->info.id = 1;
}
return 0;
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] [PATCH v2 30/30] drm/xe: Add kerneldoc description of multi-tile devices
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (28 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 29/30] drm/xe: Reinstate media GT support Matt Roper
@ 2023-05-19 23:18 ` Matt Roper
2023-05-26 22:52 ` Lucas De Marchi
2023-05-19 23:23 ` [Intel-xe] ✓ CI.Patch_applied: success for Separate GT and tile (rev3) Patchwork
` (2 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Matt Roper @ 2023-05-19 23:18 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
Documentation/gpu/xe/index.rst | 1 +
Documentation/gpu/xe/xe_tile.rst | 14 ++++++++
drivers/gpu/drm/xe/xe_tile.c | 57 ++++++++++++++++++++++++++++++++
3 files changed, 72 insertions(+)
create mode 100644 Documentation/gpu/xe/xe_tile.rst
diff --git a/Documentation/gpu/xe/index.rst b/Documentation/gpu/xe/index.rst
index 2fddf9ed251e..5c4d6bb370f3 100644
--- a/Documentation/gpu/xe/index.rst
+++ b/Documentation/gpu/xe/index.rst
@@ -21,3 +21,4 @@ DG2, etc is provided to prototype the driver.
xe_wa
xe_rtp
xe_firmware
+ xe_tile
diff --git a/Documentation/gpu/xe/xe_tile.rst b/Documentation/gpu/xe/xe_tile.rst
new file mode 100644
index 000000000000..c33f68dd95b6
--- /dev/null
+++ b/Documentation/gpu/xe/xe_tile.rst
@@ -0,0 +1,14 @@
+.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+==================
+Multi-tile Devices
+==================
+
+.. kernel-doc:: drivers/gpu/drm/xe/xe_tile.c
+ :doc: Multi-tile Design
+
+Internal API
+============
+
+.. kernel-doc:: drivers/gpu/drm/xe/xe_tile.c
+ :internal:
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
index 908eec5c17d9..d2654b78cfb4 100644
--- a/drivers/gpu/drm/xe/xe_tile.c
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -12,6 +12,63 @@
#include "xe_tile.h"
#include "xe_ttm_vram_mgr.h"
+/**
+ * DOC: Multi-tile Design
+ *
+ * Different vendors use the term "tile" a bit differently, but in the Intel
+ * world, a 'tile' is pretty close to what most people would think of as being
+ * a complete GPU. When multiple GPUs are placed behind a single PCI device,
+ * that's what is referred to as a "multi-tile device." In such cases, pretty
+ * much all hardware is replicated per-tile, although certain responsibilities
+ * like PCI communication, reporting of interrupts to the OS, etc. are handled
+ * solely by the "root tile." A multi-tile platform takes care of tying the
+ * tiles together in a way such that interrupt notifications from remote tiles
+ * are forwarded to the root tile, the per-tile vram is combined into a single
+ * address space, etc.
+ *
+ * In contrast, a "GT" (which officially stands for "Graphics Technology") is
+ * the subset of a GPU/tile that is responsible for implementing graphics
+ * and/or media operations. The GT is where a lot of the driver implementation
+ * happens since it's where the hardware engines, the execution units, and the
+ * GuC all reside.
+ *
+ * Historically most Intel devices were single-tile devices that contained a
+ * single GT. PVC is an example of an Intel platform built on a multi-tile
+ * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only
+ * has a single GT. In contrast, platforms like MTL that have separate chips
+ * for render and media IP are still only a single logical GPU, but the
+ * graphics and media IP blocks are exposed each exposed as a separate GT
+ * within that single GPU. This is important from a software perspective
+ * because multi-GT platforms like MTL only replicate a subset of the GPU
+ * hardware and behave differently than multi-tile platforms like PVC where
+ * nearly everything is replicated.
+ *
+ * Per-tile functionality (shared by all GTs within the tile):
+ * - Complete 4MB MMIO space (containing SGunit/SoC registers, GT
+ * registers, display registers, etc.)
+ * - Global GTT
+ * - VRAM (if discrete)
+ * - Interrupt flows
+ * - Migration context
+ * - kernel batchbuffer pool
+ * - Primary GT
+ * - Media GT (if media version >= 13)
+ *
+ * Per-GT functionality:
+ * - GuC
+ * - Hardware engines
+ * - Programmable hardware units (subslices, EUs)
+ * - GSI subset of registers (multiple copies of these registers reside
+ * within the complete MMIO space provided by the tile, but at different
+ * offsets --- 0 for render, 0x380000 for media)
+ * - Multicast register steering
+ * - TLBs to cache page table translations
+ * - Reset capability
+ * - Low-level power management (e.g., C6)
+ * - Clock frequency
+ * - MOCS and PAT programming
+ */
+
/**
* xe_tile_alloc - Perform per-tile memory allocation
* @tile: Tile to perform allocations for
--
2.40.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [Intel-xe] ✓ CI.Patch_applied: success for Separate GT and tile (rev3)
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (29 preceding siblings ...)
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 30/30] drm/xe: Add kerneldoc description of multi-tile devices Matt Roper
@ 2023-05-19 23:23 ` Patchwork
2023-05-19 23:26 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
2023-05-19 23:29 ` [Intel-xe] ✓ CI.Build: " Patchwork
32 siblings, 0 replies; 54+ messages in thread
From: Patchwork @ 2023-05-19 23:23 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Separate GT and tile (rev3)
URL : https://patchwork.freedesktop.org/series/117614/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: 383c5ce3a drm/xe: Change GuC interrupt data
=== git am output follows ===
Applying: drm/xe/mtl: Disable media GT
Applying: drm/xe: Introduce xe_tile
Applying: drm/xe: Add backpointer from gt to tile
Applying: drm/xe: Add for_each_tile iterator
Applying: drm/xe: Move register MMIO into xe_tile
Applying: fixup! drm/xe/display: Implement display support
Applying: drm/xe: Move GGTT from GT to tile
Applying: fixup! drm/xe/display: Implement display support
Applying: drm/xe: Move VRAM from GT to tile
Applying: fixup! drm/xe/display: Implement display support
Applying: drm/xe: Memory allocations are tile-based, not GT-based
Applying: fixup! drm/xe/display: Implement display support
Applying: drm/xe: Move migration from GT to tile
Applying: drm/xe: Clarify 'gt' retrieval for primary tile
Applying: drm/xe: Drop vram_id
Applying: drm/xe: Drop extra_gts[] declarations and XE_GT_TYPE_REMOTE
Applying: drm/xe: Allocate GT dynamically
Applying: drm/xe: Add media GT to tile
Applying: drm/xe: Move display IRQ postinstall out of GT function
Applying: drm/xe: Interrupts are delivered per-tile, not per-GT
Applying: drm/xe/irq: Handle ASLE backlight interrupts at same time as display
Applying: drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt mask
Applying: drm/xe/irq: Untangle postinstall functions
Applying: drm/xe: Replace xe_gt_irq_postinstall with xe_irq_enable_hwe
Applying: drm/xe: Invalidate TLB on all affected GTs during GGTT updates
Applying: drm/xe/tlb: Obtain forcewake when doing GGTT TLB invalidations
Applying: drm/xe: Allow GT looping and lookup on standalone media
Applying: drm/xe: Update query uapi to support standalone media
Applying: drm/xe: Reinstate media GT support
Applying: drm/xe: Add kerneldoc description of multi-tile devices
^ permalink raw reply [flat|nested] 54+ messages in thread
* [Intel-xe] ✓ CI.KUnit: success for Separate GT and tile (rev3)
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (30 preceding siblings ...)
2023-05-19 23:23 ` [Intel-xe] ✓ CI.Patch_applied: success for Separate GT and tile (rev3) Patchwork
@ 2023-05-19 23:26 ` Patchwork
2023-05-19 23:29 ` [Intel-xe] ✓ CI.Build: " Patchwork
32 siblings, 0 replies; 54+ messages in thread
From: Patchwork @ 2023-05-19 23:26 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Separate GT and tile (rev3)
URL : https://patchwork.freedesktop.org/series/117614/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
stty: 'standard input': Inappropriate ioctl for device
[23:24:57] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:25:01] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[23:25:23] Starting KUnit Kernel (1/1)...
[23:25:23] ============================================================
[23:25:23] ==================== xe_bo (2 subtests) ====================
[23:25:23] [SKIPPED] xe_ccs_migrate_kunit
[23:25:23] [SKIPPED] xe_bo_evict_kunit
[23:25:23] ===================== [SKIPPED] xe_bo ======================
[23:25:23] ================== xe_dma_buf (1 subtest) ==================
[23:25:23] [SKIPPED] xe_dma_buf_kunit
[23:25:23] =================== [SKIPPED] xe_dma_buf ===================
[23:25:23] ================== xe_migrate (1 subtest) ==================
[23:25:23] [SKIPPED] xe_migrate_sanity_kunit
[23:25:23] =================== [SKIPPED] xe_migrate ===================
[23:25:23] =================== xe_pci (2 subtests) ====================
[23:25:23] [PASSED] xe_gmdid_graphics_ip
[23:25:23] [PASSED] xe_gmdid_media_ip
[23:25:23] ===================== [PASSED] xe_pci ======================
[23:25:23] ==================== xe_rtp (1 subtest) ====================
[23:25:23] ================== xe_rtp_process_tests ===================
[23:25:23] [PASSED] coalesce-same-reg
[23:25:23] [PASSED] no-match-no-add
[23:25:23] [PASSED] no-match-no-add-multiple-rules
[23:25:23] [PASSED] two-regs-two-entries
[23:25:23] [PASSED] clr-one-set-other
[23:25:23] [PASSED] set-field
[23:25:23] [PASSED] conflict-duplicate
[23:25:23] [PASSED] conflict-not-disjoint
[23:25:23] [PASSED] conflict-reg-type
[23:25:23] ============== [PASSED] xe_rtp_process_tests ===============
[23:25:23] ===================== [PASSED] xe_rtp ======================
[23:25:23] ==================== xe_wa (1 subtest) =====================
[23:25:23] ======================== xe_wa_gt =========================
[23:25:23] [PASSED] TIGERLAKE (B0)
[23:25:23] [PASSED] DG1 (A0)
[23:25:23] [PASSED] DG1 (B0)
[23:25:23] [PASSED] ALDERLAKE_S (A0)
[23:25:23] [PASSED] ALDERLAKE_S (B0)
[23:25:23] [PASSED] ALDERLAKE_S (C0)
[23:25:23] [PASSED] ALDERLAKE_S (D0)
[23:25:23] [PASSED] DG2_G10 (A0)
[23:25:23] [ERROR] Test: xe_wa_gt: missing subtest result line!
[23:25:23]
[23:25:23] Pid: 39, comm: kunit_try_catch Tainted: G W N 6.3.0
[23:25:23] RIP: 0033:klist_put+0x14/0x90
[23:25:23] RSP: 00000000a107be90 EFLAGS: 00010246
[23:25:23] RAX: 0000000000000000 RBX: 0000000061648810 RCX: 00000000607056c8
[23:25:23] RDX: 000000006002acd0 RSI: 0000000000000001 RDI: 00000000616c0120
[23:25:23] RBP: 00000000616c0120 R08: 0000000000000001 R09: 000000006017739e
[23:25:23] R10: 0000000000000006 R11: 000000006185e000 R12: 0000000061648890
[23:25:23] R13: 000000006062a320 R14: 0000000060442850 R15: 0000000000000000
[23:25:23] Kernel panic - not syncing: Segfault with no mm
[23:25:23] ==================== [CRASHED] xe_wa_gt ====================
[23:25:23] [ERROR] Test: xe_wa: missing subtest result line!
[23:25:23] ===================== [CRASHED] xe_wa ======================
[23:25:23] ============================================================
[23:25:23] Testing complete. Ran 23 tests: passed: 19, skipped: 4, errors: 2
[23:25:23] Elapsed time: 26.276s total, 4.243s configuring, 21.711s building, 0.320s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:25:23] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:25:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[23:25:43] Starting KUnit Kernel (1/1)...
[23:25:43] ============================================================
[23:25:43] ============ drm_test_pick_cmdline (2 subtests) ============
[23:25:43] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:25:43] =============== drm_test_pick_cmdline_named ===============
[23:25:43] [PASSED] NTSC
[23:25:43] [PASSED] NTSC-J
[23:25:43] [PASSED] PAL
[23:25:43] [PASSED] PAL-M
[23:25:43] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:25:43] ============== [PASSED] drm_test_pick_cmdline ==============
[23:25:43] ================== drm_buddy (6 subtests) ==================
[23:25:43] [PASSED] drm_test_buddy_alloc_limit
[23:25:43] [PASSED] drm_test_buddy_alloc_range
[23:25:43] [PASSED] drm_test_buddy_alloc_optimistic
[23:25:44] [PASSED] drm_test_buddy_alloc_pessimistic
[23:25:44] [PASSED] drm_test_buddy_alloc_smoke
[23:25:44] [PASSED] drm_test_buddy_alloc_pathological
[23:25:44] ==================== [PASSED] drm_buddy ====================
[23:25:44] ============= drm_cmdline_parser (40 subtests) =============
[23:25:44] [PASSED] drm_test_cmdline_force_d_only
[23:25:44] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:25:44] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:25:44] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:25:44] [PASSED] drm_test_cmdline_force_e_only
[23:25:44] [PASSED] drm_test_cmdline_res
[23:25:44] [PASSED] drm_test_cmdline_res_vesa
[23:25:44] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:25:44] [PASSED] drm_test_cmdline_res_rblank
[23:25:44] [PASSED] drm_test_cmdline_res_bpp
[23:25:44] [PASSED] drm_test_cmdline_res_refresh
[23:25:44] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:25:44] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:25:44] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:25:44] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:25:44] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:25:44] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:25:44] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:25:44] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:25:44] [PASSED] drm_test_cmdline_res_margins_force_on
[23:25:44] [PASSED] drm_test_cmdline_res_vesa_margins
[23:25:44] [PASSED] drm_test_cmdline_name
[23:25:44] [PASSED] drm_test_cmdline_name_bpp
[23:25:44] [PASSED] drm_test_cmdline_name_option
[23:25:44] [PASSED] drm_test_cmdline_name_bpp_option
[23:25:44] [PASSED] drm_test_cmdline_rotate_0
[23:25:44] [PASSED] drm_test_cmdline_rotate_90
[23:25:44] [PASSED] drm_test_cmdline_rotate_180
[23:25:44] [PASSED] drm_test_cmdline_rotate_270
[23:25:44] [PASSED] drm_test_cmdline_hmirror
[23:25:44] [PASSED] drm_test_cmdline_vmirror
[23:25:44] [PASSED] drm_test_cmdline_margin_options
[23:25:44] [PASSED] drm_test_cmdline_multiple_options
[23:25:44] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:25:44] [PASSED] drm_test_cmdline_extra_and_option
[23:25:44] [PASSED] drm_test_cmdline_freestanding_options
[23:25:44] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:25:44] [PASSED] drm_test_cmdline_panel_orientation
[23:25:44] ================ drm_test_cmdline_invalid =================
[23:25:44] [PASSED] margin_only
[23:25:44] [PASSED] interlace_only
[23:25:44] [PASSED] res_missing_x
[23:25:44] [PASSED] res_missing_y
[23:25:44] [PASSED] res_bad_y
[23:25:44] [PASSED] res_missing_y_bpp
[23:25:44] [PASSED] res_bad_bpp
[23:25:44] [PASSED] res_bad_refresh
[23:25:44] [PASSED] res_bpp_refresh_force_on_off
[23:25:44] [PASSED] res_invalid_mode
[23:25:44] [PASSED] res_bpp_wrong_place_mode
[23:25:44] [PASSED] name_bpp_refresh
[23:25:44] [PASSED] name_refresh
[23:25:44] [PASSED] name_refresh_wrong_mode
[23:25:44] [PASSED] name_refresh_invalid_mode
[23:25:44] [PASSED] rotate_multiple
[23:25:44] [PASSED] rotate_invalid_val
[23:25:44] [PASSED] rotate_truncated
[23:25:44] [PASSED] invalid_option
[23:25:44] [PASSED] invalid_tv_option
[23:25:44] [PASSED] truncated_tv_option
[23:25:44] ============ [PASSED] drm_test_cmdline_invalid =============
[23:25:44] =============== drm_test_cmdline_tv_options ===============
[23:25:44] [PASSED] NTSC
[23:25:44] [PASSED] NTSC_443
[23:25:44] [PASSED] NTSC_J
[23:25:44] [PASSED] PAL
[23:25:44] [PASSED] PAL_M
[23:25:44] [PASSED] PAL_N
[23:25:44] [PASSED] SECAM
[23:25:44] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:25:44] =============== [PASSED] drm_cmdline_parser ================
[23:25:44] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:25:44] ========== drm_test_get_tv_mode_from_name_valid ===========
[23:25:44] [PASSED] NTSC
[23:25:44] [PASSED] NTSC-443
[23:25:44] [PASSED] NTSC-J
[23:25:44] [PASSED] PAL
[23:25:44] [PASSED] PAL-M
[23:25:44] [PASSED] PAL-N
[23:25:44] [PASSED] SECAM
[23:25:44] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:25:44] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:25:44] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:25:44] ============= drm_damage_helper (21 subtests) ==============
[23:25:44] [PASSED] drm_test_damage_iter_no_damage
[23:25:44] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:25:44] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:25:44] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:25:44] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:25:44] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:25:44] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:25:44] [PASSED] drm_test_damage_iter_simple_damage
[23:25:44] [PASSED] drm_test_damage_iter_single_damage
[23:25:44] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:25:44] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:25:44] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:25:44] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:25:44] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:25:44] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:25:44] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:25:44] [PASSED] drm_test_damage_iter_damage
[23:25:44] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:25:44] [PASSED] drm_test_damage_iter_damage_one_outside
[23:25:44] [PASSED] drm_test_damage_iter_damage_src_moved
[23:25:44] [PASSED] drm_test_damage_iter_damage_not_visible
[23:25:44] ================ [PASSED] drm_damage_helper ================
[23:25:44] ============== drm_dp_mst_helper (2 subtests) ==============
[23:25:44] ============== drm_test_dp_mst_calc_pbn_mode ==============
[23:25:44] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:25:44] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:25:44] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:25:44] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:25:44] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:25:44] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:25:44] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[23:25:44] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:25:44] [PASSED] DP_POWER_UP_PHY with port number
[23:25:44] [PASSED] DP_POWER_DOWN_PHY with port number
[23:25:44] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:25:44] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:25:44] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:25:44] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:25:44] [PASSED] DP_QUERY_PAYLOAD with port number
[23:25:44] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:25:44] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:25:44] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:25:44] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:25:44] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:25:44] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:25:44] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:25:44] [PASSED] DP_REMOTE_I2C_READ with port number
[23:25:44] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:25:44] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:25:44] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:25:44] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:25:44] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:25:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:25:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:25:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:25:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:25:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:25:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:25:44] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:25:44] ================ [PASSED] drm_dp_mst_helper ================
[23:25:44] =========== drm_format_helper_test (11 subtests) ===========
[23:25:44] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:25:44] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:25:44] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:25:44] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:25:44] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:25:44] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:25:44] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:25:44] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:25:44] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:25:44] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:25:44] ============== drm_test_fb_xrgb8888_to_mono ===============
[23:25:44] [PASSED] single_pixel_source_buffer
[23:25:44] [PASSED] single_pixel_clip_rectangle
[23:25:44] [PASSED] well_known_colors
[23:25:44] [PASSED] destination_pitch
[23:25:44] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:25:44] ============= [PASSED] drm_format_helper_test ==============
[23:25:44] ================= drm_format (18 subtests) =================
[23:25:44] [PASSED] drm_test_format_block_width_invalid
[23:25:44] [PASSED] drm_test_format_block_width_one_plane
[23:25:44] [PASSED] drm_test_format_block_width_two_plane
[23:25:44] [PASSED] drm_test_format_block_width_three_plane
[23:25:44] [PASSED] drm_test_format_block_width_tiled
[23:25:44] [PASSED] drm_test_format_block_height_invalid
[23:25:44] [PASSED] drm_test_format_block_height_one_plane
[23:25:44] [PASSED] drm_test_format_block_height_two_plane
[23:25:44] [PASSED] drm_test_format_block_height_three_plane
[23:25:44] [PASSED] drm_test_format_block_height_tiled
[23:25:44] [PASSED] drm_test_format_min_pitch_invalid
[23:25:44] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:25:44] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:25:44] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:25:44] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:25:44] [PASSED] drm_test_format_min_pitch_two_plane
[23:25:44] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:25:44] [PASSED] drm_test_format_min_pitch_tiled
[23:25:44] =================== [PASSED] drm_format ====================
[23:25:44] =============== drm_framebuffer (1 subtest) ================
[23:25:44] =============== drm_test_framebuffer_create ===============
[23:25:44] [PASSED] ABGR8888 normal sizes
[23:25:44] [PASSED] ABGR8888 max sizes
[23:25:44] [PASSED] ABGR8888 pitch greater than min required
[23:25:44] [PASSED] ABGR8888 pitch less than min required
[23:25:44] [PASSED] ABGR8888 Invalid width
[23:25:44] [PASSED] ABGR8888 Invalid buffer handle
[23:25:44] [PASSED] No pixel format
[23:25:44] [PASSED] ABGR8888 Width 0
[23:25:44] [PASSED] ABGR8888 Height 0
[23:25:44] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:25:44] [PASSED] ABGR8888 Large buffer offset
[23:25:44] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:25:44] [PASSED] ABGR8888 Valid buffer modifier
[23:25:44] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:25:44] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:25:44] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:25:44] [PASSED] NV12 Normal sizes
[23:25:44] [PASSED] NV12 Max sizes
[23:25:44] [PASSED] NV12 Invalid pitch
[23:25:44] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:25:44] [PASSED] NV12 different modifier per-plane
[23:25:44] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:25:44] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:25:44] [PASSED] NV12 Modifier for inexistent plane
[23:25:44] [PASSED] NV12 Handle for inexistent plane
[23:25:44] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:25:44] [PASSED] YVU420 Normal sizes
[23:25:44] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:25:44] [PASSED] YVU420 Max sizes
[23:25:44] [PASSED] YVU420 Invalid pitch
[23:25:44] [PASSED] YVU420 Different pitches
[23:25:44] [PASSED] YVU420 Different buffer offsets/pitches
[23:25:44] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:25:44] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:25:44] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:25:44] [PASSED] YVU420 Valid modifier
[23:25:44] [PASSED] YVU420 Different modifiers per plane
[23:25:44] [PASSED] YVU420 Modifier for inexistent plane
[23:25:44] [PASSED] X0L2 Normal sizes
[23:25:44] [PASSED] X0L2 Max sizes
[23:25:44] [PASSED] X0L2 Invalid pitch
[23:25:44] [PASSED] X0L2 Pitch greater than minimum required
stty: 'standard input': Inappropriate ioctl for device
[23:25:44] [PASSED] X0L2 Handle for inexistent plane
[23:25:44] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:25:44] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:25:44] [PASSED] X0L2 Valid modifier
[23:25:44] [PASSED] X0L2 Modifier for inexistent plane
[23:25:44] =========== [PASSED] drm_test_framebuffer_create ===========
[23:25:44] ================= [PASSED] drm_framebuffer =================
[23:25:44] =============== drm-test-managed (1 subtest) ===============
[23:25:44] [PASSED] drm_test_managed_run_action
[23:25:44] ================ [PASSED] drm-test-managed =================
[23:25:44] =================== drm_mm (19 subtests) ===================
[23:25:44] [PASSED] drm_test_mm_init
[23:25:44] [PASSED] drm_test_mm_debug
[23:25:53] [PASSED] drm_test_mm_reserve
[23:26:03] [PASSED] drm_test_mm_insert
[23:26:04] [PASSED] drm_test_mm_replace
[23:26:04] [PASSED] drm_test_mm_insert_range
[23:26:04] [PASSED] drm_test_mm_frag
[23:26:04] [PASSED] drm_test_mm_align
[23:26:04] [PASSED] drm_test_mm_align32
[23:26:04] [PASSED] drm_test_mm_align64
[23:26:05] [PASSED] drm_test_mm_evict
[23:26:05] [PASSED] drm_test_mm_evict_range
[23:26:05] [PASSED] drm_test_mm_topdown
[23:26:05] [PASSED] drm_test_mm_bottomup
[23:26:05] [PASSED] drm_test_mm_lowest
[23:26:05] [PASSED] drm_test_mm_highest
[23:26:05] [PASSED] drm_test_mm_color
[23:26:06] [PASSED] drm_test_mm_color_evict
[23:26:06] [PASSED] drm_test_mm_color_evict_range
[23:26:06] ===================== [PASSED] drm_mm ======================
[23:26:06] ============= drm_modes_analog_tv (4 subtests) =============
[23:26:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:26:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:26:06] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:26:06] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:26:06] =============== [PASSED] drm_modes_analog_tv ===============
[23:26:06] ============== drm_plane_helper (2 subtests) ===============
[23:26:06] =============== drm_test_check_plane_state ================
[23:26:06] [PASSED] clipping_simple
[23:26:06] [PASSED] clipping_rotate_reflect
[23:26:06] [PASSED] positioning_simple
[23:26:06] [PASSED] upscaling
[23:26:06] [PASSED] downscaling
[23:26:06] [PASSED] rounding1
[23:26:06] [PASSED] rounding2
[23:26:06] [PASSED] rounding3
[23:26:06] [PASSED] rounding4
[23:26:06] =========== [PASSED] drm_test_check_plane_state ============
[23:26:06] =========== drm_test_check_invalid_plane_state ============
[23:26:06] [PASSED] positioning_invalid
[23:26:06] [PASSED] upscaling_invalid
[23:26:06] [PASSED] downscaling_invalid
[23:26:06] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:26:06] ================ [PASSED] drm_plane_helper =================
[23:26:06] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:26:06] ====== drm_test_connector_helper_tv_get_modes_check =======
[23:26:06] [PASSED] None
[23:26:06] [PASSED] PAL
[23:26:06] [PASSED] NTSC
[23:26:06] [PASSED] Both, NTSC Default
[23:26:06] [PASSED] Both, PAL Default
[23:26:06] [PASSED] Both, NTSC Default, with PAL on command-line
[23:26:06] [PASSED] Both, PAL Default, with NTSC on command-line
[23:26:06] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:26:06] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:26:06] ================== drm_rect (9 subtests) ===================
[23:26:06] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:26:06] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:26:06] [PASSED] drm_test_rect_clip_scaled_clipped
[23:26:06] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:26:06] ================= drm_test_rect_intersect =================
[23:26:06] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:26:06] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:26:06] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:26:06] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:26:06] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:26:06] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:26:06] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:26:06] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:26:06] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:26:06] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:26:06] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:26:06] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:26:06] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:26:06] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:26:06] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[23:26:06] ============= [PASSED] drm_test_rect_intersect =============
[23:26:06] ================ drm_test_rect_calc_hscale ================
[23:26:06] [PASSED] normal use
[23:26:06] [PASSED] out of max range
[23:26:06] [PASSED] out of min range
[23:26:06] [PASSED] zero dst
[23:26:06] [PASSED] negative src
[23:26:06] [PASSED] negative dst
[23:26:06] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:26:06] ================ drm_test_rect_calc_vscale ================
[23:26:06] [PASSED] normal use
[23:26:06] [PASSED] out of max range
[23:26:06] [PASSED] out of min range
[23:26:06] [PASSED] zero dst
[23:26:06] [PASSED] negative src
[23:26:06] [PASSED] negative dst
[23:26:06] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:26:06] ================== drm_test_rect_rotate ===================
[23:26:06] [PASSED] reflect-x
[23:26:06] [PASSED] reflect-y
[23:26:06] [PASSED] rotate-0
[23:26:06] [PASSED] rotate-90
[23:26:06] [PASSED] rotate-180
[23:26:06] [PASSED] rotate-270
[23:26:06] ============== [PASSED] drm_test_rect_rotate ===============
[23:26:06] ================ drm_test_rect_rotate_inv =================
[23:26:06] [PASSED] reflect-x
[23:26:06] [PASSED] reflect-y
[23:26:06] [PASSED] rotate-0
[23:26:06] [PASSED] rotate-90
[23:26:06] [PASSED] rotate-180
[23:26:06] [PASSED] rotate-270
[23:26:06] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:26:06] ==================== [PASSED] drm_rect =====================
[23:26:06] ============================================================
[23:26:06] Testing complete. Ran 333 tests: passed: 333
[23:26:06] Elapsed time: 42.725s total, 1.694s configuring, 18.087s building, 22.891s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 54+ messages in thread
* [Intel-xe] ✓ CI.Build: success for Separate GT and tile (rev3)
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
` (31 preceding siblings ...)
2023-05-19 23:26 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
@ 2023-05-19 23:29 ` Patchwork
32 siblings, 0 replies; 54+ messages in thread
From: Patchwork @ 2023-05-19 23:29 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Separate GT and tile (rev3)
URL : https://patchwork.freedesktop.org/series/117614/
State : success
== Summary ==
+ trap cleanup EXIT
+ cd /kernel
+ git clone https://gitlab.freedesktop.org/drm/xe/ci.git .ci
Cloning into '.ci'...
++ date +%s
+ echo -e '\e[0Ksection_start:1684538776:build_x86_64[collapsed=true]\r\e[0KBuild x86-64'
+ mkdir -p build64
^[[0Ksection_start:1684538776:build_x86_64[collapsed=true]
^[[0KBuild x86-64
+ cat .ci/kernel/kconfig
+ make O=build64 olddefconfig
make[1]: Entering directory '/kernel/build64'
GEN Makefile
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
HOSTCC scripts/kconfig/confdata.o
HOSTCC scripts/kconfig/expr.o
LEX scripts/kconfig/lexer.lex.c
YACC scripts/kconfig/parser.tab.[ch]
HOSTCC scripts/kconfig/lexer.lex.o
HOSTCC scripts/kconfig/menu.o
HOSTCC scripts/kconfig/parser.tab.o
HOSTCC scripts/kconfig/preprocess.o
HOSTCC scripts/kconfig/symbol.o
HOSTCC scripts/kconfig/util.o
HOSTLD scripts/kconfig/conf
#
# configuration written to .config
#
make[1]: Leaving directory '/kernel/build64'
++ nproc
+ make O=build64 -j48
make[1]: Entering directory '/kernel/build64'
GEN Makefile
WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h
WRAP arch/x86/include/generated/uapi/asm/errno.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h
WRAP arch/x86/include/generated/uapi/asm/fcntl.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h
WRAP arch/x86/include/generated/uapi/asm/ioctl.h
WRAP arch/x86/include/generated/uapi/asm/ioctls.h
SYSTBL arch/x86/include/generated/asm/syscalls_32.h
WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h
SYSHDR arch/x86/include/generated/asm/unistd_32_ia32.h
WRAP arch/x86/include/generated/uapi/asm/param.h
SYSHDR arch/x86/include/generated/asm/unistd_64_x32.h
WRAP arch/x86/include/generated/uapi/asm/poll.h
WRAP arch/x86/include/generated/uapi/asm/resource.h
SYSTBL arch/x86/include/generated/asm/syscalls_64.h
WRAP arch/x86/include/generated/uapi/asm/socket.h
WRAP arch/x86/include/generated/uapi/asm/sockios.h
WRAP arch/x86/include/generated/uapi/asm/termbits.h
WRAP arch/x86/include/generated/uapi/asm/termios.h
WRAP arch/x86/include/generated/uapi/asm/types.h
UPD include/generated/uapi/linux/version.h
UPD include/config/kernel.release
HOSTCC arch/x86/tools/relocs_32.o
HOSTCC arch/x86/tools/relocs_64.o
HOSTCC arch/x86/tools/relocs_common.o
WRAP arch/x86/include/generated/asm/early_ioremap.h
WRAP arch/x86/include/generated/asm/export.h
WRAP arch/x86/include/generated/asm/mcs_spinlock.h
WRAP arch/x86/include/generated/asm/irq_regs.h
UPD include/generated/compile.h
WRAP arch/x86/include/generated/asm/kmap_size.h
WRAP arch/x86/include/generated/asm/mmiowb.h
WRAP arch/x86/include/generated/asm/local64.h
WRAP arch/x86/include/generated/asm/module.lds.h
WRAP arch/x86/include/generated/asm/rwonce.h
WRAP arch/x86/include/generated/asm/unaligned.h
HOSTCC scripts/unifdef
UPD include/generated/utsrelease.h
HOSTCC scripts/kallsyms
HOSTCC scripts/sorttable
HOSTCC scripts/asn1_compiler
DESCEND objtool
HOSTCC /kernel/build64/tools/objtool/fixdep.o
HOSTLD /kernel/build64/tools/objtool/fixdep-in.o
LINK /kernel/build64/tools/objtool/fixdep
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/exec-cmd.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/help.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/pager.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/run-command.h
INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/parse-options.h
CC /kernel/build64/tools/objtool/libsubcmd/exec-cmd.o
CC /kernel/build64/tools/objtool/libsubcmd/help.o
INSTALL libsubcmd_headers
CC /kernel/build64/tools/objtool/libsubcmd/pager.o
CC /kernel/build64/tools/objtool/libsubcmd/parse-options.o
CC /kernel/build64/tools/objtool/libsubcmd/run-command.o
CC /kernel/build64/tools/objtool/libsubcmd/sigchain.o
CC /kernel/build64/tools/objtool/libsubcmd/subcmd-config.o
HOSTLD arch/x86/tools/relocs
CC scripts/mod/empty.o
HOSTCC scripts/mod/mk_elfconfig
CC scripts/mod/devicetable-offsets.s
HDRINST usr/include/video/edid.h
HDRINST usr/include/video/sisfb.h
HDRINST usr/include/video/uvesafb.h
HDRINST usr/include/drm/amdgpu_drm.h
HDRINST usr/include/drm/qaic_accel.h
HDRINST usr/include/drm/i915_drm.h
HDRINST usr/include/drm/vgem_drm.h
HDRINST usr/include/drm/virtgpu_drm.h
HDRINST usr/include/drm/xe_drm.h
HDRINST usr/include/drm/omap_drm.h
HDRINST usr/include/drm/radeon_drm.h
HDRINST usr/include/drm/tegra_drm.h
HDRINST usr/include/drm/drm_mode.h
HDRINST usr/include/drm/ivpu_accel.h
HDRINST usr/include/drm/v3d_drm.h
HDRINST usr/include/drm/exynos_drm.h
HDRINST usr/include/drm/drm_sarea.h
HDRINST usr/include/drm/qxl_drm.h
HDRINST usr/include/drm/nouveau_drm.h
HDRINST usr/include/drm/drm_fourcc.h
HDRINST usr/include/drm/habanalabs_accel.h
HDRINST usr/include/drm/msm_drm.h
HDRINST usr/include/drm/vmwgfx_drm.h
HDRINST usr/include/drm/etnaviv_drm.h
HDRINST usr/include/drm/vc4_drm.h
HDRINST usr/include/drm/panfrost_drm.h
HDRINST usr/include/drm/lima_drm.h
HDRINST usr/include/drm/drm.h
HDRINST usr/include/drm/armada_drm.h
HDRINST usr/include/mtd/inftl-user.h
HDRINST usr/include/mtd/nftl-user.h
HDRINST usr/include/mtd/mtd-user.h
HDRINST usr/include/mtd/ubi-user.h
HDRINST usr/include/mtd/mtd-abi.h
HDRINST usr/include/xen/gntdev.h
HDRINST usr/include/xen/gntalloc.h
HDRINST usr/include/xen/evtchn.h
HDRINST usr/include/xen/privcmd.h
HDRINST usr/include/asm-generic/auxvec.h
HDRINST usr/include/asm-generic/bitsperlong.h
HDRINST usr/include/asm-generic/posix_types.h
HDRINST usr/include/asm-generic/ioctls.h
HDRINST usr/include/asm-generic/mman.h
HDRINST usr/include/asm-generic/shmbuf.h
HDRINST usr/include/asm-generic/bpf_perf_event.h
HDRINST usr/include/asm-generic/types.h
HDRINST usr/include/asm-generic/poll.h
HDRINST usr/include/asm-generic/msgbuf.h
HDRINST usr/include/asm-generic/swab.h
HDRINST usr/include/asm-generic/statfs.h
HDRINST usr/include/asm-generic/unistd.h
HDRINST usr/include/asm-generic/hugetlb_encode.h
HDRINST usr/include/asm-generic/resource.h
HDRINST usr/include/asm-generic/param.h
HDRINST usr/include/asm-generic/termbits-common.h
HDRINST usr/include/asm-generic/sockios.h
HDRINST usr/include/asm-generic/kvm_para.h
HDRINST usr/include/asm-generic/errno.h
HDRINST usr/include/asm-generic/termios.h
HDRINST usr/include/asm-generic/mman-common.h
HDRINST usr/include/asm-generic/ioctl.h
HDRINST usr/include/asm-generic/socket.h
HDRINST usr/include/asm-generic/signal-defs.h
HDRINST usr/include/asm-generic/termbits.h
HDRINST usr/include/asm-generic/int-ll64.h
HDRINST usr/include/asm-generic/signal.h
HDRINST usr/include/asm-generic/siginfo.h
HDRINST usr/include/asm-generic/stat.h
HDRINST usr/include/asm-generic/int-l64.h
HDRINST usr/include/asm-generic/errno-base.h
HDRINST usr/include/asm-generic/fcntl.h
HDRINST usr/include/asm-generic/setup.h
HDRINST usr/include/asm-generic/ipcbuf.h
HDRINST usr/include/asm-generic/sembuf.h
HDRINST usr/include/asm-generic/ucontext.h
HDRINST usr/include/rdma/mlx5_user_ioctl_cmds.h
HDRINST usr/include/rdma/irdma-abi.h
HDRINST usr/include/rdma/mana-abi.h
HDRINST usr/include/rdma/hfi/hfi1_user.h
HDRINST usr/include/rdma/hfi/hfi1_ioctl.h
HDRINST usr/include/rdma/rdma_user_rxe.h
HDRINST usr/include/rdma/rdma_user_ioctl.h
HDRINST usr/include/rdma/mlx5_user_ioctl_verbs.h
HDRINST usr/include/rdma/bnxt_re-abi.h
HDRINST usr/include/rdma/hns-abi.h
HDRINST usr/include/rdma/qedr-abi.h
HDRINST usr/include/rdma/ib_user_ioctl_cmds.h
HDRINST usr/include/rdma/vmw_pvrdma-abi.h
HDRINST usr/include/rdma/ib_user_sa.h
HDRINST usr/include/rdma/ib_user_ioctl_verbs.h
HDRINST usr/include/rdma/rvt-abi.h
HDRINST usr/include/rdma/mlx5-abi.h
HDRINST usr/include/rdma/rdma_netlink.h
HDRINST usr/include/rdma/erdma-abi.h
HDRINST usr/include/rdma/rdma_user_ioctl_cmds.h
HDRINST usr/include/rdma/rdma_user_cm.h
HDRINST usr/include/rdma/ib_user_verbs.h
HDRINST usr/include/rdma/efa-abi.h
HDRINST usr/include/rdma/siw-abi.h
UPD scripts/mod/devicetable-offsets.h
HDRINST usr/include/rdma/mlx4-abi.h
HDRINST usr/include/rdma/mthca-abi.h
HDRINST usr/include/rdma/ib_user_mad.h
HDRINST usr/include/rdma/ocrdma-abi.h
HDRINST usr/include/rdma/cxgb4-abi.h
HDRINST usr/include/misc/xilinx_sdfec.h
HDRINST usr/include/misc/uacce/hisi_qm.h
HDRINST usr/include/misc/uacce/uacce.h
HDRINST usr/include/misc/cxl.h
HDRINST usr/include/misc/ocxl.h
HDRINST usr/include/misc/fastrpc.h
HDRINST usr/include/misc/pvpanic.h
HDRINST usr/include/linux/i8k.h
HDRINST usr/include/linux/acct.h
HDRINST usr/include/linux/atmmpc.h
HDRINST usr/include/linux/fs.h
HDRINST usr/include/linux/cifs/cifs_mount.h
HDRINST usr/include/linux/cifs/cifs_netlink.h
HDRINST usr/include/linux/if_packet.h
HDRINST usr/include/linux/route.h
HDRINST usr/include/linux/patchkey.h
HDRINST usr/include/linux/tc_ematch/tc_em_cmp.h
HDRINST usr/include/linux/tc_ematch/tc_em_ipt.h
HDRINST usr/include/linux/tc_ematch/tc_em_meta.h
HDRINST usr/include/linux/tc_ematch/tc_em_nbyte.h
HDRINST usr/include/linux/tc_ematch/tc_em_text.h
HDRINST usr/include/linux/virtio_pmem.h
HDRINST usr/include/linux/rkisp1-config.h
HDRINST usr/include/linux/vhost.h
HDRINST usr/include/linux/cec-funcs.h
HDRINST usr/include/linux/ppdev.h
HDRINST usr/include/linux/isdn/capicmd.h
HDRINST usr/include/linux/virtio_fs.h
HDRINST usr/include/linux/netfilter_ipv6.h
HDRINST usr/include/linux/lirc.h
HDRINST usr/include/linux/mroute6.h
HDRINST usr/include/linux/nl80211-vnd-intel.h
HDRINST usr/include/linux/ivtvfb.h
HDRINST usr/include/linux/auxvec.h
HDRINST usr/include/linux/dm-log-userspace.h
HDRINST usr/include/linux/dccp.h
HDRINST usr/include/linux/virtio_scmi.h
HDRINST usr/include/linux/atmarp.h
HDRINST usr/include/linux/arcfb.h
HDRINST usr/include/linux/nbd-netlink.h
HDRINST usr/include/linux/sched/types.h
HDRINST usr/include/linux/tcp.h
HDRINST usr/include/linux/neighbour.h
HDRINST usr/include/linux/dlm_device.h
HDRINST usr/include/linux/wmi.h
HDRINST usr/include/linux/btrfs_tree.h
HDRINST usr/include/linux/virtio_crypto.h
HDRINST usr/include/linux/vbox_err.h
HDRINST usr/include/linux/edd.h
HDRINST usr/include/linux/loop.h
HDRINST usr/include/linux/nvme_ioctl.h
HDRINST usr/include/linux/mmtimer.h
HDRINST usr/include/linux/if_pppol2tp.h
HDRINST usr/include/linux/mtio.h
HDRINST usr/include/linux/if_arcnet.h
HDRINST usr/include/linux/romfs_fs.h
HDRINST usr/include/linux/posix_types.h
HDRINST usr/include/linux/rtc.h
HDRINST usr/include/linux/landlock.h
HDRINST usr/include/linux/gpio.h
HDRINST usr/include/linux/selinux_netlink.h
HDRINST usr/include/linux/pps.h
HDRINST usr/include/linux/ndctl.h
HDRINST usr/include/linux/virtio_gpu.h
HDRINST usr/include/linux/android/binderfs.h
HDRINST usr/include/linux/android/binder.h
HDRINST usr/include/linux/virtio_vsock.h
HDRINST usr/include/linux/sound.h
HDRINST usr/include/linux/vtpm_proxy.h
HDRINST usr/include/linux/nfs_fs.h
HDRINST usr/include/linux/elf-fdpic.h
HDRINST usr/include/linux/adfs_fs.h
HDRINST usr/include/linux/target_core_user.h
HDRINST usr/include/linux/netlink_diag.h
HDRINST usr/include/linux/const.h
HDRINST usr/include/linux/firewire-cdev.h
HDRINST usr/include/linux/vdpa.h
HDRINST usr/include/linux/if_infiniband.h
HDRINST usr/include/linux/serial.h
MKELF scripts/mod/elfconfig.h
HDRINST usr/include/linux/iio/types.h
HDRINST usr/include/linux/iio/buffer.h
HDRINST usr/include/linux/iio/events.h
HOSTCC scripts/mod/modpost.o
HDRINST usr/include/linux/baycom.h
HOSTCC scripts/mod/file2alias.o
HDRINST usr/include/linux/major.h
HOSTCC scripts/mod/sumversion.o
HDRINST usr/include/linux/atmppp.h
HDRINST usr/include/linux/ipv6_route.h
HDRINST usr/include/linux/spi/spidev.h
HDRINST usr/include/linux/spi/spi.h
HDRINST usr/include/linux/virtio_ring.h
HDRINST usr/include/linux/hdlc/ioctl.h
HDRINST usr/include/linux/remoteproc_cdev.h
HDRINST usr/include/linux/hyperv.h
HDRINST usr/include/linux/rpl_iptunnel.h
HDRINST usr/include/linux/sync_file.h
HDRINST usr/include/linux/igmp.h
HDRINST usr/include/linux/v4l2-dv-timings.h
HDRINST usr/include/linux/virtio_i2c.h
HDRINST usr/include/linux/xfrm.h
HDRINST usr/include/linux/capability.h
HDRINST usr/include/linux/gtp.h
HDRINST usr/include/linux/xdp_diag.h
HDRINST usr/include/linux/pkt_cls.h
HDRINST usr/include/linux/suspend_ioctls.h
HDRINST usr/include/linux/vt.h
HDRINST usr/include/linux/loadpin.h
HDRINST usr/include/linux/dlm_plock.h
HDRINST usr/include/linux/fb.h
HDRINST usr/include/linux/max2175.h
HDRINST usr/include/linux/sunrpc/debug.h
HDRINST usr/include/linux/gsmmux.h
HDRINST usr/include/linux/watchdog.h
HDRINST usr/include/linux/vhost_types.h
HDRINST usr/include/linux/vduse.h
HDRINST usr/include/linux/ila.h
HDRINST usr/include/linux/tdx-guest.h
HDRINST usr/include/linux/close_range.h
HDRINST usr/include/linux/ivtv.h
HDRINST usr/include/linux/cryptouser.h
HDRINST usr/include/linux/netfilter/xt_string.h
HDRINST usr/include/linux/netfilter/nfnetlink_compat.h
HDRINST usr/include/linux/netfilter/nf_nat.h
HDRINST usr/include/linux/netfilter/xt_recent.h
HDRINST usr/include/linux/netfilter/xt_addrtype.h
HDRINST usr/include/linux/netfilter/nf_conntrack_tcp.h
HDRINST usr/include/linux/netfilter/xt_MARK.h
HDRINST usr/include/linux/netfilter/xt_SYNPROXY.h
HDRINST usr/include/linux/netfilter/xt_multiport.h
HDRINST usr/include/linux/netfilter/nfnetlink.h
HDRINST usr/include/linux/netfilter/xt_cgroup.h
HDRINST usr/include/linux/netfilter/nf_synproxy.h
HDRINST usr/include/linux/netfilter/xt_TCPOPTSTRIP.h
HDRINST usr/include/linux/netfilter/nfnetlink_log.h
HDRINST usr/include/linux/netfilter/xt_TPROXY.h
HDRINST usr/include/linux/netfilter/xt_u32.h
HDRINST usr/include/linux/netfilter/nfnetlink_osf.h
HDRINST usr/include/linux/netfilter/xt_ecn.h
HDRINST usr/include/linux/netfilter/xt_esp.h
HDRINST usr/include/linux/netfilter/nfnetlink_hook.h
HDRINST usr/include/linux/netfilter/xt_mac.h
HDRINST usr/include/linux/netfilter/xt_comment.h
HDRINST usr/include/linux/netfilter/xt_NFQUEUE.h
HDRINST usr/include/linux/netfilter/xt_osf.h
HDRINST usr/include/linux/netfilter/xt_hashlimit.h
HDRINST usr/include/linux/netfilter/nf_conntrack_sctp.h
HDRINST usr/include/linux/netfilter/xt_socket.h
HDRINST usr/include/linux/netfilter/xt_connmark.h
HDRINST usr/include/linux/netfilter/xt_sctp.h
HDRINST usr/include/linux/netfilter/xt_tcpudp.h
HDRINST usr/include/linux/netfilter/xt_DSCP.h
HDRINST usr/include/linux/netfilter/xt_time.h
HDRINST usr/include/linux/netfilter/xt_IDLETIMER.h
HDRINST usr/include/linux/netfilter/xt_policy.h
HDRINST usr/include/linux/netfilter/xt_rpfilter.h
HDRINST usr/include/linux/netfilter/xt_nfacct.h
HDRINST usr/include/linux/netfilter/xt_SECMARK.h
HDRINST usr/include/linux/netfilter/xt_length.h
HDRINST usr/include/linux/netfilter/nfnetlink_cthelper.h
HDRINST usr/include/linux/netfilter/xt_quota.h
HDRINST usr/include/linux/netfilter/xt_CLASSIFY.h
HDRINST usr/include/linux/netfilter/xt_ipcomp.h
HDRINST usr/include/linux/netfilter/xt_iprange.h
HDRINST usr/include/linux/netfilter/xt_bpf.h
HDRINST usr/include/linux/netfilter/xt_LOG.h
HDRINST usr/include/linux/netfilter/xt_rateest.h
HDRINST usr/include/linux/netfilter/xt_CONNSECMARK.h
HDRINST usr/include/linux/netfilter/xt_HMARK.h
HDRINST usr/include/linux/netfilter/xt_CONNMARK.h
HDRINST usr/include/linux/netfilter/xt_pkttype.h
HDRINST usr/include/linux/netfilter/xt_ipvs.h
HDRINST usr/include/linux/netfilter/xt_devgroup.h
HDRINST usr/include/linux/netfilter/xt_AUDIT.h
HDRINST usr/include/linux/netfilter/xt_realm.h
HDRINST usr/include/linux/netfilter/nf_conntrack_common.h
HDRINST usr/include/linux/netfilter/xt_LED.h
HDRINST usr/include/linux/netfilter/xt_set.h
HDRINST usr/include/linux/netfilter/xt_connlabel.h
HDRINST usr/include/linux/netfilter/xt_owner.h
HDRINST usr/include/linux/netfilter/xt_dccp.h
HDRINST usr/include/linux/netfilter/xt_limit.h
HDRINST usr/include/linux/netfilter/xt_conntrack.h
HDRINST usr/include/linux/netfilter/xt_TEE.h
HDRINST usr/include/linux/netfilter/xt_RATEEST.h
HDRINST usr/include/linux/netfilter/xt_connlimit.h
HDRINST usr/include/linux/netfilter/ipset/ip_set.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_list.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_hash.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_bitmap.h
HDRINST usr/include/linux/netfilter/x_tables.h
HDRINST usr/include/linux/netfilter/xt_dscp.h
HDRINST usr/include/linux/netfilter/nf_conntrack_ftp.h
HDRINST usr/include/linux/netfilter/xt_cluster.h
HDRINST usr/include/linux/netfilter/nf_conntrack_tuple_common.h
HDRINST usr/include/linux/netfilter/nf_log.h
HDRINST usr/include/linux/netfilter/xt_tcpmss.h
HDRINST usr/include/linux/netfilter/xt_NFLOG.h
HDRINST usr/include/linux/netfilter/xt_l2tp.h
HDRINST usr/include/linux/netfilter/xt_helper.h
HDRINST usr/include/linux/netfilter/xt_statistic.h
HDRINST usr/include/linux/netfilter/nfnetlink_queue.h
HDRINST usr/include/linux/netfilter/nfnetlink_cttimeout.h
HDRINST usr/include/linux/netfilter/xt_CT.h
HDRINST usr/include/linux/netfilter/xt_CHECKSUM.h
HDRINST usr/include/linux/netfilter/xt_connbytes.h
HDRINST usr/include/linux/netfilter/xt_state.h
HDRINST usr/include/linux/netfilter/nf_tables.h
HDRINST usr/include/linux/netfilter/xt_mark.h
HDRINST usr/include/linux/netfilter/xt_cpu.h
HDRINST usr/include/linux/netfilter/nf_tables_compat.h
HDRINST usr/include/linux/netfilter/xt_physdev.h
HDRINST usr/include/linux/netfilter/nfnetlink_conntrack.h
HDRINST usr/include/linux/netfilter/nfnetlink_acct.h
HDRINST usr/include/linux/netfilter/xt_TCPMSS.h
HDRINST usr/include/linux/tty_flags.h
HDRINST usr/include/linux/if_phonet.h
HDRINST usr/include/linux/elf-em.h
HDRINST usr/include/linux/vm_sockets.h
HDRINST usr/include/linux/dlmconstants.h
HDRINST usr/include/linux/bsg.h
HDRINST usr/include/linux/matroxfb.h
HDRINST usr/include/linux/sysctl.h
HDRINST usr/include/linux/unix_diag.h
HDRINST usr/include/linux/pcitest.h
HDRINST usr/include/linux/mman.h
HDRINST usr/include/linux/if_plip.h
HDRINST usr/include/linux/virtio_balloon.h
HDRINST usr/include/linux/pidfd.h
HDRINST usr/include/linux/f2fs.h
HDRINST usr/include/linux/x25.h
HDRINST usr/include/linux/if_cablemodem.h
HDRINST usr/include/linux/utsname.h
HDRINST usr/include/linux/counter.h
HDRINST usr/include/linux/atm_tcp.h
HDRINST usr/include/linux/atalk.h
HDRINST usr/include/linux/virtio_rng.h
HDRINST usr/include/linux/vboxguest.h
HDRINST usr/include/linux/bpf_perf_event.h
HDRINST usr/include/linux/ipmi_ssif_bmc.h
HDRINST usr/include/linux/nfs_mount.h
HDRINST usr/include/linux/sonet.h
HDRINST usr/include/linux/netfilter.h
HDRINST usr/include/linux/keyctl.h
HDRINST usr/include/linux/nl80211.h
HDRINST usr/include/linux/misc/bcm_vk.h
HDRINST usr/include/linux/audit.h
HDRINST usr/include/linux/tipc_config.h
HDRINST usr/include/linux/tipc_sockets_diag.h
HDRINST usr/include/linux/futex.h
HDRINST usr/include/linux/sev-guest.h
HDRINST usr/include/linux/ublk_cmd.h
HDRINST usr/include/linux/types.h
HDRINST usr/include/linux/virtio_input.h
HDRINST usr/include/linux/if_slip.h
HDRINST usr/include/linux/personality.h
HDRINST usr/include/linux/openat2.h
HDRINST usr/include/linux/poll.h
HDRINST usr/include/linux/posix_acl.h
HDRINST usr/include/linux/smc_diag.h
HDRINST usr/include/linux/snmp.h
HDRINST usr/include/linux/errqueue.h
HDRINST usr/include/linux/if_tunnel.h
HDRINST usr/include/linux/fanotify.h
HDRINST usr/include/linux/kernel.h
HDRINST usr/include/linux/rtnetlink.h
HDRINST usr/include/linux/rpl.h
HDRINST usr/include/linux/memfd.h
HDRINST usr/include/linux/serial_core.h
HDRINST usr/include/linux/dns_resolver.h
HDRINST usr/include/linux/pr.h
HDRINST usr/include/linux/atm_eni.h
HDRINST usr/include/linux/lp.h
HDRINST usr/include/linux/virtio_mem.h
HDRINST usr/include/linux/ultrasound.h
HDRINST usr/include/linux/sctp.h
HDRINST usr/include/linux/uio.h
HDRINST usr/include/linux/tcp_metrics.h
HDRINST usr/include/linux/wwan.h
HDRINST usr/include/linux/atmbr2684.h
HDRINST usr/include/linux/in_route.h
HDRINST usr/include/linux/qemu_fw_cfg.h
HDRINST usr/include/linux/if_macsec.h
HDRINST usr/include/linux/usb/charger.h
HDRINST usr/include/linux/usb/g_uvc.h
HDRINST usr/include/linux/usb/raw_gadget.h
HDRINST usr/include/linux/usb/gadgetfs.h
HDRINST usr/include/linux/usb/cdc-wdm.h
HDRINST usr/include/linux/usb/g_printer.h
HDRINST usr/include/linux/usb/midi.h
HDRINST usr/include/linux/usb/tmc.h
HDRINST usr/include/linux/usb/video.h
HDRINST usr/include/linux/usb/functionfs.h
HDRINST usr/include/linux/usb/audio.h
HDRINST usr/include/linux/usb/ch11.h
HDRINST usr/include/linux/usb/ch9.h
HDRINST usr/include/linux/usb/cdc.h
HDRINST usr/include/linux/jffs2.h
HDRINST usr/include/linux/ax25.h
HDRINST usr/include/linux/auto_fs.h
HDRINST usr/include/linux/tiocl.h
HDRINST usr/include/linux/scc.h
HDRINST usr/include/linux/psci.h
HDRINST usr/include/linux/swab.h
HDRINST usr/include/linux/cec.h
HDRINST usr/include/linux/kfd_ioctl.h
HDRINST usr/include/linux/smc.h
HDRINST usr/include/linux/qrtr.h
HDRINST usr/include/linux/screen_info.h
HDRINST usr/include/linux/nfsacl.h
HDRINST usr/include/linux/seg6_hmac.h
HDRINST usr/include/linux/gameport.h
HDRINST usr/include/linux/wireless.h
HDRINST usr/include/linux/fdreg.h
HDRINST usr/include/linux/cciss_defs.h
HDRINST usr/include/linux/serial_reg.h
HDRINST usr/include/linux/perf_event.h
HDRINST usr/include/linux/in6.h
HDRINST usr/include/linux/hid.h
HDRINST usr/include/linux/netlink.h
HDRINST usr/include/linux/fuse.h
HDRINST usr/include/linux/magic.h
HDRINST usr/include/linux/ioam6_iptunnel.h
HDRINST usr/include/linux/stm.h
HDRINST usr/include/linux/vsockmon.h
HDRINST usr/include/linux/seg6.h
HDRINST usr/include/linux/idxd.h
HDRINST usr/include/linux/nitro_enclaves.h
HDRINST usr/include/linux/ptrace.h
HDRINST usr/include/linux/ioam6_genl.h
HDRINST usr/include/linux/qnx4_fs.h
HDRINST usr/include/linux/fsl_mc.h
HDRINST usr/include/linux/net_tstamp.h
HDRINST usr/include/linux/msg.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_TTL.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ttl.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ah.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ECN.h
HDRINST usr/include/linux/netfilter_ipv4/ip_tables.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ecn.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_REJECT.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_LOG.h
HDRINST usr/include/linux/sem.h
HDRINST usr/include/linux/net_namespace.h
HDRINST usr/include/linux/radeonfb.h
HDRINST usr/include/linux/tee.h
HDRINST usr/include/linux/udp.h
HDRINST usr/include/linux/virtio_bt.h
HDRINST usr/include/linux/v4l2-subdev.h
HDRINST usr/include/linux/posix_acl_xattr.h
HDRINST usr/include/linux/v4l2-mediabus.h
HDRINST usr/include/linux/atmapi.h
HDRINST usr/include/linux/raid/md_p.h
HDRINST usr/include/linux/raid/md_u.h
HDRINST usr/include/linux/zorro_ids.h
HDRINST usr/include/linux/nbd.h
HDRINST usr/include/linux/isst_if.h
HDRINST usr/include/linux/rxrpc.h
HDRINST usr/include/linux/unistd.h
HDRINST usr/include/linux/if_arp.h
HDRINST usr/include/linux/atm_zatm.h
HDRINST usr/include/linux/io_uring.h
HDRINST usr/include/linux/if_fddi.h
HDRINST usr/include/linux/bpqether.h
HDRINST usr/include/linux/sysinfo.h
HDRINST usr/include/linux/auto_dev-ioctl.h
HDRINST usr/include/linux/nfs4_mount.h
HDRINST usr/include/linux/keyboard.h
HDRINST usr/include/linux/virtio_mmio.h
HDRINST usr/include/linux/input.h
HDRINST usr/include/linux/qnxtypes.h
HDRINST usr/include/linux/mdio.h
HDRINST usr/include/linux/lwtunnel.h
HDRINST usr/include/linux/gfs2_ondisk.h
HDRINST usr/include/linux/nfs4.h
HDRINST usr/include/linux/ptp_clock.h
HDRINST usr/include/linux/nubus.h
HDRINST usr/include/linux/if_bonding.h
HDRINST usr/include/linux/kcov.h
HDRINST usr/include/linux/fadvise.h
HDRINST usr/include/linux/taskstats.h
HDRINST usr/include/linux/veth.h
HDRINST usr/include/linux/atm.h
HDRINST usr/include/linux/ipmi.h
HDRINST usr/include/linux/kdev_t.h
HDRINST usr/include/linux/mount.h
HDRINST usr/include/linux/shm.h
HDRINST usr/include/linux/resource.h
HDRINST usr/include/linux/prctl.h
HDRINST usr/include/linux/watch_queue.h
HDRINST usr/include/linux/sched.h
HDRINST usr/include/linux/phonet.h
HDRINST usr/include/linux/random.h
HDRINST usr/include/linux/tty.h
HDRINST usr/include/linux/apm_bios.h
HDRINST usr/include/linux/fd.h
HDRINST usr/include/linux/um_timetravel.h
HDRINST usr/include/linux/tls.h
HDRINST usr/include/linux/rpmsg_types.h
HDRINST usr/include/linux/pfrut.h
HDRINST usr/include/linux/mei.h
HDRINST usr/include/linux/fsi.h
HDRINST usr/include/linux/rds.h
HDRINST usr/include/linux/if_x25.h
HDRINST usr/include/linux/param.h
HDRINST usr/include/linux/netdevice.h
HDRINST usr/include/linux/binfmts.h
HDRINST usr/include/linux/if_pppox.h
HDRINST usr/include/linux/sockios.h
HDRINST usr/include/linux/kcm.h
HDRINST usr/include/linux/virtio_9p.h
HDRINST usr/include/linux/genwqe/genwqe_card.h
HDRINST usr/include/linux/if_tun.h
HDRINST usr/include/linux/if_ether.h
HDRINST usr/include/linux/kvm_para.h
HDRINST usr/include/linux/kernel-page-flags.h
HDRINST usr/include/linux/cdrom.h
HDRINST usr/include/linux/un.h
HDRINST usr/include/linux/module.h
HDRINST usr/include/linux/mqueue.h
HDRINST usr/include/linux/a.out.h
HDRINST usr/include/linux/input-event-codes.h
HDRINST usr/include/linux/coda.h
HDRINST usr/include/linux/rio_mport_cdev.h
HDRINST usr/include/linux/ipsec.h
HDRINST usr/include/linux/blkpg.h
HDRINST usr/include/linux/blkzoned.h
HDRINST usr/include/linux/netfilter_bridge/ebt_arpreply.h
HDRINST usr/include/linux/netfilter_bridge/ebt_redirect.h
HDRINST usr/include/linux/netfilter_bridge/ebt_nflog.h
HDRINST usr/include/linux/netfilter_bridge/ebt_802_3.h
HDRINST usr/include/linux/netfilter_bridge/ebt_nat.h
HDRINST usr/include/linux/netfilter_bridge/ebt_mark_m.h
HDRINST usr/include/linux/netfilter_bridge/ebtables.h
HDRINST usr/include/linux/netfilter_bridge/ebt_vlan.h
HDRINST usr/include/linux/netfilter_bridge/ebt_limit.h
HDRINST usr/include/linux/netfilter_bridge/ebt_log.h
HDRINST usr/include/linux/netfilter_bridge/ebt_stp.h
HDRINST usr/include/linux/netfilter_bridge/ebt_pkttype.h
HDRINST usr/include/linux/netfilter_bridge/ebt_ip.h
HDRINST usr/include/linux/netfilter_bridge/ebt_ip6.h
HDRINST usr/include/linux/netfilter_bridge/ebt_arp.h
HDRINST usr/include/linux/netfilter_bridge/ebt_mark_t.h
HDRINST usr/include/linux/netfilter_bridge/ebt_among.h
HDRINST usr/include/linux/reiserfs_fs.h
HDRINST usr/include/linux/cciss_ioctl.h
HDRINST usr/include/linux/fsmap.h
HDRINST usr/include/linux/smiapp.h
LD /kernel/build64/tools/objtool/libsubcmd/libsubcmd-in.o
HDRINST usr/include/linux/switchtec_ioctl.h
HDRINST usr/include/linux/atmdev.h
HDRINST usr/include/linux/hpet.h
HDRINST usr/include/linux/virtio_config.h
HDRINST usr/include/linux/string.h
HDRINST usr/include/linux/kfd_sysfs.h
HDRINST usr/include/linux/inet_diag.h
HDRINST usr/include/linux/netdev.h
HDRINST usr/include/linux/xattr.h
HDRINST usr/include/linux/iommufd.h
HDRINST usr/include/linux/errno.h
HDRINST usr/include/linux/icmp.h
HDRINST usr/include/linux/i2o-dev.h
HDRINST usr/include/linux/pg.h
HDRINST usr/include/linux/if_bridge.h
HDRINST usr/include/linux/thermal.h
HDRINST usr/include/linux/uinput.h
HDRINST usr/include/linux/dqblk_xfs.h
HDRINST usr/include/linux/v4l2-common.h
HDRINST usr/include/linux/nvram.h
HDRINST usr/include/linux/if_vlan.h
HDRINST usr/include/linux/uhid.h
HDRINST usr/include/linux/omap3isp.h
HDRINST usr/include/linux/rose.h
HDRINST usr/include/linux/phantom.h
HDRINST usr/include/linux/ipmi_msgdefs.h
HDRINST usr/include/linux/bcm933xx_hcs.h
HDRINST usr/include/linux/bpf.h
HDRINST usr/include/linux/mempolicy.h
HDRINST usr/include/linux/efs_fs_sb.h
HDRINST usr/include/linux/nexthop.h
HDRINST usr/include/linux/net_dropmon.h
HDRINST usr/include/linux/surface_aggregator/cdev.h
AR /kernel/build64/tools/objtool/libsubcmd/libsubcmd.a
HDRINST usr/include/linux/surface_aggregator/dtx.h
HDRINST usr/include/linux/net.h
HDRINST usr/include/linux/mii.h
HDRINST usr/include/linux/cm4000_cs.h
HDRINST usr/include/linux/virtio_pcidev.h
HDRINST usr/include/linux/termios.h
HDRINST usr/include/linux/cgroupstats.h
HDRINST usr/include/linux/mpls.h
HDRINST usr/include/linux/iommu.h
HDRINST usr/include/linux/toshiba.h
HDRINST usr/include/linux/virtio_scsi.h
HDRINST usr/include/linux/zorro.h
HDRINST usr/include/linux/chio.h
HDRINST usr/include/linux/pkt_sched.h
HDRINST usr/include/linux/cramfs_fs.h
HDRINST usr/include/linux/nfs3.h
HDRINST usr/include/linux/vfio_ccw.h
HDRINST usr/include/linux/atm_nicstar.h
HDRINST usr/include/linux/ncsi.h
HDRINST usr/include/linux/virtio_net.h
HDRINST usr/include/linux/ioctl.h
HDRINST usr/include/linux/stddef.h
HDRINST usr/include/linux/limits.h
HDRINST usr/include/linux/ipmi_bmc.h
HDRINST usr/include/linux/netfilter_arp.h
HDRINST usr/include/linux/if_addr.h
HDRINST usr/include/linux/rpmsg.h
HDRINST usr/include/linux/media-bus-format.h
HDRINST usr/include/linux/kernelcapi.h
HDRINST usr/include/linux/ppp_defs.h
HDRINST usr/include/linux/ethtool.h
HDRINST usr/include/linux/aspeed-video.h
HDRINST usr/include/linux/hdlc.h
HDRINST usr/include/linux/fscrypt.h
HDRINST usr/include/linux/batadv_packet.h
HDRINST usr/include/linux/uuid.h
HDRINST usr/include/linux/capi.h
HDRINST usr/include/linux/mptcp.h
HDRINST usr/include/linux/hidraw.h
HDRINST usr/include/linux/virtio_console.h
HDRINST usr/include/linux/irqnr.h
HDRINST usr/include/linux/coresight-stm.h
HDRINST usr/include/linux/cxl_mem.h
HDRINST usr/include/linux/iso_fs.h
HDRINST usr/include/linux/virtio_blk.h
HDRINST usr/include/linux/udf_fs_i.h
HDRINST usr/include/linux/coff.h
HDRINST usr/include/linux/dma-buf.h
HDRINST usr/include/linux/ife.h
HDRINST usr/include/linux/agpgart.h
HDRINST usr/include/linux/socket.h
HDRINST usr/include/linux/nilfs2_ondisk.h
HDRINST usr/include/linux/connector.h
HDRINST usr/include/linux/auto_fs4.h
HDRINST usr/include/linux/bt-bmc.h
HDRINST usr/include/linux/map_to_7segment.h
HDRINST usr/include/linux/tc_act/tc_skbedit.h
HDRINST usr/include/linux/tc_act/tc_ctinfo.h
HDRINST usr/include/linux/tc_act/tc_defact.h
HDRINST usr/include/linux/tc_act/tc_gact.h
HDRINST usr/include/linux/tc_act/tc_vlan.h
CC /kernel/build64/tools/objtool/weak.o
HDRINST usr/include/linux/tc_act/tc_skbmod.h
HDRINST usr/include/linux/tc_act/tc_sample.h
HDRINST usr/include/linux/tc_act/tc_tunnel_key.h
CC /kernel/build64/tools/objtool/check.o
HDRINST usr/include/linux/tc_act/tc_gate.h
HDRINST usr/include/linux/tc_act/tc_mirred.h
HDRINST usr/include/linux/tc_act/tc_nat.h
HDRINST usr/include/linux/tc_act/tc_csum.h
CC /kernel/build64/tools/objtool/special.o
MKDIR /kernel/build64/tools/objtool/arch/x86/
HDRINST usr/include/linux/tc_act/tc_connmark.h
HDRINST usr/include/linux/tc_act/tc_ife.h
CC /kernel/build64/tools/objtool/builtin-check.o
HDRINST usr/include/linux/tc_act/tc_mpls.h
MKDIR /kernel/build64/tools/objtool/arch/x86/lib/
CC /kernel/build64/tools/objtool/elf.o
HDRINST usr/include/linux/tc_act/tc_ct.h
CC /kernel/build64/tools/objtool/objtool.o
HDRINST usr/include/linux/tc_act/tc_pedit.h
HDRINST usr/include/linux/tc_act/tc_bpf.h
CC /kernel/build64/tools/objtool/arch/x86/special.o
GEN /kernel/build64/tools/objtool/arch/x86/lib/inat-tables.c
CC /kernel/build64/tools/objtool/orc_gen.o
HDRINST usr/include/linux/tc_act/tc_ipt.h
HDRINST usr/include/linux/netrom.h
CC /kernel/build64/tools/objtool/orc_dump.o
HDRINST usr/include/linux/joystick.h
HDRINST usr/include/linux/falloc.h
HDRINST usr/include/linux/cycx_cfm.h
CC /kernel/build64/tools/objtool/libstring.o
HDRINST usr/include/linux/omapfb.h
HDRINST usr/include/linux/msdos_fs.h
CC /kernel/build64/tools/objtool/libctype.o
HDRINST usr/include/linux/virtio_types.h
HDRINST usr/include/linux/mroute.h
CC /kernel/build64/tools/objtool/str_error_r.o
HDRINST usr/include/linux/psample.h
CC /kernel/build64/tools/objtool/librbtree.o
HDRINST usr/include/linux/ipv6.h
HDRINST usr/include/linux/dw100.h
HDRINST usr/include/linux/psp-sev.h
HDRINST usr/include/linux/vfio.h
HDRINST usr/include/linux/if_ppp.h
HDRINST usr/include/linux/byteorder/big_endian.h
HDRINST usr/include/linux/byteorder/little_endian.h
HDRINST usr/include/linux/comedi.h
HDRINST usr/include/linux/scif_ioctl.h
HDRINST usr/include/linux/timerfd.h
HDRINST usr/include/linux/time_types.h
HDRINST usr/include/linux/firewire-constants.h
HDRINST usr/include/linux/virtio_snd.h
HDRINST usr/include/linux/ppp-ioctl.h
HDRINST usr/include/linux/fib_rules.h
HDRINST usr/include/linux/gen_stats.h
HDRINST usr/include/linux/virtio_iommu.h
HDRINST usr/include/linux/genetlink.h
HDRINST usr/include/linux/uvcvideo.h
HDRINST usr/include/linux/pfkeyv2.h
HDRINST usr/include/linux/soundcard.h
HDRINST usr/include/linux/times.h
HDRINST usr/include/linux/nfc.h
HDRINST usr/include/linux/affs_hardblocks.h
HDRINST usr/include/linux/nilfs2_api.h
HDRINST usr/include/linux/rseq.h
HDRINST usr/include/linux/caif/caif_socket.h
HDRINST usr/include/linux/caif/if_caif.h
HDRINST usr/include/linux/i2c-dev.h
HDRINST usr/include/linux/cuda.h
HDRINST usr/include/linux/cn_proc.h
HDRINST usr/include/linux/parport.h
HDRINST usr/include/linux/v4l2-controls.h
HDRINST usr/include/linux/hsi/cs-protocol.h
HDRINST usr/include/linux/hsi/hsi_char.h
HDRINST usr/include/linux/seg6_genl.h
HDRINST usr/include/linux/am437x-vpfe.h
HDRINST usr/include/linux/amt.h
HDRINST usr/include/linux/netconf.h
HDRINST usr/include/linux/erspan.h
HDRINST usr/include/linux/nsfs.h
HDRINST usr/include/linux/xilinx-v4l2-controls.h
HDRINST usr/include/linux/aspeed-p2a-ctrl.h
HDRINST usr/include/linux/vfio_zdev.h
HDRINST usr/include/linux/serio.h
HDRINST usr/include/linux/acrn.h
HDRINST usr/include/linux/nfs2.h
HDRINST usr/include/linux/virtio_pci.h
HDRINST usr/include/linux/ipc.h
HDRINST usr/include/linux/ethtool_netlink.h
HDRINST usr/include/linux/kd.h
HDRINST usr/include/linux/elf.h
HDRINST usr/include/linux/videodev2.h
HDRINST usr/include/linux/if_alg.h
HDRINST usr/include/linux/sonypi.h
HDRINST usr/include/linux/fsverity.h
HDRINST usr/include/linux/if.h
HDRINST usr/include/linux/btrfs.h
HDRINST usr/include/linux/vm_sockets_diag.h
HDRINST usr/include/linux/netfilter_bridge.h
HDRINST usr/include/linux/packet_diag.h
HDRINST usr/include/linux/netfilter_ipv4.h
HDRINST usr/include/linux/kvm.h
HDRINST usr/include/linux/pci.h
HDRINST usr/include/linux/if_addrlabel.h
CC /kernel/build64/tools/objtool/arch/x86/decode.o
HDRINST usr/include/linux/hdlcdrv.h
HDRINST usr/include/linux/cfm_bridge.h
HDRINST usr/include/linux/fiemap.h
HDRINST usr/include/linux/dm-ioctl.h
HDRINST usr/include/linux/aspeed-lpc-ctrl.h
HDRINST usr/include/linux/atmioc.h
HDRINST usr/include/linux/dlm.h
HDRINST usr/include/linux/pci_regs.h
HDRINST usr/include/linux/cachefiles.h
HDRINST usr/include/linux/membarrier.h
HDRINST usr/include/linux/nfs_idmap.h
HDRINST usr/include/linux/atm_he.h
HDRINST usr/include/linux/ip.h
HDRINST usr/include/linux/nfsd/export.h
HDRINST usr/include/linux/nfsd/stats.h
HDRINST usr/include/linux/nfsd/debug.h
HDRINST usr/include/linux/nfsd/cld.h
HDRINST usr/include/linux/ip_vs.h
HDRINST usr/include/linux/vmcore.h
HDRINST usr/include/linux/vbox_vmmdev_types.h
HDRINST usr/include/linux/dvb/osd.h
HDRINST usr/include/linux/dvb/dmx.h
HDRINST usr/include/linux/dvb/net.h
HDRINST usr/include/linux/dvb/frontend.h
HDRINST usr/include/linux/dvb/ca.h
HDRINST usr/include/linux/dvb/version.h
HDRINST usr/include/linux/dvb/video.h
HDRINST usr/include/linux/dvb/audio.h
HDRINST usr/include/linux/nfs.h
HDRINST usr/include/linux/if_link.h
HDRINST usr/include/linux/wait.h
HDRINST usr/include/linux/icmpv6.h
HDRINST usr/include/linux/media.h
HDRINST usr/include/linux/seg6_local.h
HDRINST usr/include/linux/openvswitch.h
HDRINST usr/include/linux/atmsap.h
HDRINST usr/include/linux/bpfilter.h
HDRINST usr/include/linux/fpga-dfl.h
HDRINST usr/include/linux/userio.h
HDRINST usr/include/linux/signal.h
HDRINST usr/include/linux/map_to_14segment.h
HDRINST usr/include/linux/hdreg.h
HDRINST usr/include/linux/utime.h
HDRINST usr/include/linux/usbdevice_fs.h
HDRINST usr/include/linux/timex.h
HDRINST usr/include/linux/if_fc.h
HDRINST usr/include/linux/reiserfs_xattr.h
HDRINST usr/include/linux/hw_breakpoint.h
HDRINST usr/include/linux/quota.h
HDRINST usr/include/linux/ioprio.h
HDRINST usr/include/linux/eventpoll.h
HDRINST usr/include/linux/atmclip.h
HDRINST usr/include/linux/can.h
HDRINST usr/include/linux/if_team.h
HDRINST usr/include/linux/usbip.h
HDRINST usr/include/linux/stat.h
HDRINST usr/include/linux/fou.h
HDRINST usr/include/linux/hash_info.h
HDRINST usr/include/linux/ppp-comp.h
HDRINST usr/include/linux/ip6_tunnel.h
HDRINST usr/include/linux/tipc_netlink.h
HDRINST usr/include/linux/in.h
HDRINST usr/include/linux/wireguard.h
HDRINST usr/include/linux/btf.h
HDRINST usr/include/linux/batman_adv.h
HDRINST usr/include/linux/fcntl.h
HDRINST usr/include/linux/if_ltalk.h
HDRINST usr/include/linux/i2c.h
HDRINST usr/include/linux/atm_idt77105.h
HDRINST usr/include/linux/kexec.h
HDRINST usr/include/linux/arm_sdei.h
HDRINST usr/include/linux/netfilter_ipv6/ip6_tables.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_ah.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_NPT.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_rt.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_REJECT.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_opts.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_srh.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_LOG.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_mh.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_HL.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_hl.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_frag.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_ipv6header.h
HDRINST usr/include/linux/minix_fs.h
HDRINST usr/include/linux/aio_abi.h
HDRINST usr/include/linux/pktcdvd.h
HDRINST usr/include/linux/libc-compat.h
HDRINST usr/include/linux/atmlec.h
HDRINST usr/include/linux/signalfd.h
HDRINST usr/include/linux/bpf_common.h
HDRINST usr/include/linux/seg6_iptunnel.h
HDRINST usr/include/linux/synclink.h
HDRINST usr/include/linux/mpls_iptunnel.h
HDRINST usr/include/linux/mctp.h
HDRINST usr/include/linux/if_xdp.h
HDRINST usr/include/linux/llc.h
HDRINST usr/include/linux/atmsvc.h
HDRINST usr/include/linux/sed-opal.h
HDRINST usr/include/linux/sock_diag.h
HDRINST usr/include/linux/time.h
HDRINST usr/include/linux/securebits.h
HDRINST usr/include/linux/fsl_hypervisor.h
HDRINST usr/include/linux/if_hippi.h
HDRINST usr/include/linux/dlm_netlink.h
HDRINST usr/include/linux/seccomp.h
HDRINST usr/include/linux/oom.h
HDRINST usr/include/linux/filter.h
HDRINST usr/include/linux/inotify.h
HDRINST usr/include/linux/rfkill.h
HDRINST usr/include/linux/reboot.h
HDRINST usr/include/linux/can/vxcan.h
HDRINST usr/include/linux/can/j1939.h
HDRINST usr/include/linux/can/netlink.h
HDRINST usr/include/linux/can/bcm.h
HDRINST usr/include/linux/can/raw.h
HDRINST usr/include/linux/can/gw.h
HDRINST usr/include/linux/can/error.h
HDRINST usr/include/linux/can/isotp.h
HDRINST usr/include/linux/if_eql.h
HDRINST usr/include/linux/hiddev.h
HDRINST usr/include/linux/blktrace_api.h
HDRINST usr/include/linux/ccs.h
HDRINST usr/include/linux/ioam6.h
HDRINST usr/include/linux/hsr_netlink.h
HDRINST usr/include/linux/mmc/ioctl.h
HDRINST usr/include/linux/bfs_fs.h
HDRINST usr/include/linux/rio_cm_cdev.h
HDRINST usr/include/linux/uleds.h
HDRINST usr/include/linux/mrp_bridge.h
HDRINST usr/include/linux/adb.h
HDRINST usr/include/linux/pmu.h
HDRINST usr/include/linux/udmabuf.h
HDRINST usr/include/linux/kcmp.h
HDRINST usr/include/linux/dma-heap.h
HDRINST usr/include/linux/userfaultfd.h
HDRINST usr/include/linux/netfilter_arp/arpt_mangle.h
HDRINST usr/include/linux/netfilter_arp/arp_tables.h
HDRINST usr/include/linux/tipc.h
HDRINST usr/include/linux/virtio_ids.h
HDRINST usr/include/linux/l2tp.h
HDRINST usr/include/linux/devlink.h
HDRINST usr/include/linux/virtio_gpio.h
HDRINST usr/include/linux/dcbnl.h
HDRINST usr/include/linux/cyclades.h
HDRINST usr/include/sound/intel/avs/tokens.h
HDRINST usr/include/sound/sof/fw.h
HDRINST usr/include/sound/sof/abi.h
HDRINST usr/include/sound/sof/tokens.h
HDRINST usr/include/sound/sof/header.h
HDRINST usr/include/sound/usb_stream.h
HDRINST usr/include/sound/sfnt_info.h
HDRINST usr/include/sound/asequencer.h
HDRINST usr/include/sound/tlv.h
HDRINST usr/include/sound/asound.h
HDRINST usr/include/sound/asoc.h
HDRINST usr/include/sound/sb16_csp.h
HDRINST usr/include/sound/compress_offload.h
HDRINST usr/include/sound/hdsp.h
HDRINST usr/include/sound/emu10k1.h
HDRINST usr/include/sound/snd_ar_tokens.h
HDRINST usr/include/sound/snd_sst_tokens.h
HDRINST usr/include/sound/asound_fm.h
HDRINST usr/include/sound/hdspm.h
HDRINST usr/include/sound/compress_params.h
HDRINST usr/include/sound/firewire.h
HDRINST usr/include/sound/skl-tplg-interface.h
HDRINST usr/include/scsi/scsi_bsg_ufs.h
HDRINST usr/include/scsi/scsi_netlink_fc.h
HDRINST usr/include/scsi/scsi_bsg_mpi3mr.h
HDRINST usr/include/scsi/fc/fc_ns.h
HDRINST usr/include/scsi/fc/fc_fs.h
HDRINST usr/include/scsi/fc/fc_els.h
HDRINST usr/include/scsi/fc/fc_gs.h
HDRINST usr/include/scsi/scsi_bsg_fc.h
HDRINST usr/include/scsi/cxlflash_ioctl.h
HDRINST usr/include/scsi/scsi_netlink.h
HDRINST usr/include/linux/version.h
HDRINST usr/include/asm/processor-flags.h
HDRINST usr/include/asm/auxvec.h
HDRINST usr/include/asm/svm.h
HDRINST usr/include/asm/bitsperlong.h
HDRINST usr/include/asm/kvm_perf.h
HDRINST usr/include/asm/mce.h
HDRINST usr/include/asm/posix_types.h
HDRINST usr/include/asm/msr.h
HDRINST usr/include/asm/sigcontext32.h
HDRINST usr/include/asm/mman.h
HDRINST usr/include/asm/shmbuf.h
HDRINST usr/include/asm/e820.h
HDRINST usr/include/asm/posix_types_64.h
HDRINST usr/include/asm/vsyscall.h
HDRINST usr/include/asm/msgbuf.h
HDRINST usr/include/asm/swab.h
HDRINST usr/include/asm/statfs.h
HDRINST usr/include/asm/posix_types_x32.h
HDRINST usr/include/asm/ptrace.h
HDRINST usr/include/asm/unistd.h
HDRINST usr/include/asm/ist.h
HDRINST usr/include/asm/prctl.h
HDRINST usr/include/asm/boot.h
HDRINST usr/include/asm/sigcontext.h
HDRINST usr/include/asm/posix_types_32.h
HDRINST usr/include/asm/kvm_para.h
HDRINST usr/include/asm/a.out.h
HDRINST usr/include/asm/mtrr.h
HDRINST usr/include/asm/amd_hsmp.h
HDRINST usr/include/asm/hwcap2.h
HDRINST usr/include/asm/ptrace-abi.h
HDRINST usr/include/asm/vm86.h
HDRINST usr/include/asm/ldt.h
HDRINST usr/include/asm/vmx.h
HDRINST usr/include/asm/kvm.h
HDRINST usr/include/asm/perf_regs.h
HDRINST usr/include/asm/debugreg.h
HDRINST usr/include/asm/signal.h
HDRINST usr/include/asm/bootparam.h
HDRINST usr/include/asm/siginfo.h
HDRINST usr/include/asm/hw_breakpoint.h
HDRINST usr/include/asm/stat.h
HDRINST usr/include/asm/setup.h
HDRINST usr/include/asm/sembuf.h
HDRINST usr/include/asm/sgx.h
HDRINST usr/include/asm/ucontext.h
HDRINST usr/include/asm/byteorder.h
HDRINST usr/include/asm/unistd_64.h
HDRINST usr/include/asm/ioctls.h
HDRINST usr/include/asm/bpf_perf_event.h
HDRINST usr/include/asm/types.h
HDRINST usr/include/asm/poll.h
HDRINST usr/include/asm/resource.h
HDRINST usr/include/asm/param.h
HDRINST usr/include/asm/sockios.h
HDRINST usr/include/asm/unistd_x32.h
HDRINST usr/include/asm/errno.h
HDRINST usr/include/asm/termios.h
HDRINST usr/include/asm/ioctl.h
HDRINST usr/include/asm/socket.h
HDRINST usr/include/asm/unistd_32.h
HDRINST usr/include/asm/termbits.h
HDRINST usr/include/asm/fcntl.h
HDRINST usr/include/asm/ipcbuf.h
HOSTLD scripts/mod/modpost
CC kernel/bounds.s
CHKSHA1 ../include/linux/atomic/atomic-arch-fallback.h
CHKSHA1 ../include/linux/atomic/atomic-instrumented.h
CHKSHA1 ../include/linux/atomic/atomic-long.h
UPD include/generated/timeconst.h
UPD include/generated/bounds.h
CC arch/x86/kernel/asm-offsets.s
LD /kernel/build64/tools/objtool/arch/x86/objtool-in.o
UPD include/generated/asm-offsets.h
CALL ../scripts/checksyscalls.sh
LD /kernel/build64/tools/objtool/objtool-in.o
LINK /kernel/build64/tools/objtool/objtool
LDS scripts/module.lds
CC ipc/compat.o
CC ipc/util.o
CC ipc/msgutil.o
CC ipc/msg.o
CC init/main.o
AR certs/built-in.a
HOSTCC usr/gen_init_cpio
CC arch/x86/power/cpu.o
CC init/do_mounts.o
CC ipc/sem.o
CC ipc/shm.o
CC init/do_mounts_initrd.o
CC arch/x86/power/hibernate_64.o
CC block/bdev.o
CC ipc/syscall.o
CC init/initramfs.o
AS arch/x86/lib/clear_page_64.o
CC block/fops.o
CC ipc/ipc_sysctl.o
AS arch/x86/power/hibernate_asm_64.o
CC security/commoncap.o
UPD init/utsversion-tmp.h
AR arch/x86/video/built-in.a
CC io_uring/io_uring.o
CC arch/x86/pci/i386.o
AS arch/x86/crypto/aesni-intel_asm.o
CC arch/x86/realmode/init.o
AR virt/lib/built-in.a
CC security/keys/gc.o
CC [M] arch/x86/video/fbdev.o
CC block/partitions/core.o
AR arch/x86/ia32/built-in.a
AR sound/ppc/built-in.a
AR drivers/irqchip/built-in.a
CC [M] virt/lib/irqbypass.o
CC arch/x86/events/amd/core.o
CC net/core/sock.o
AR sound/drivers/opl3/built-in.a
CC arch/x86/mm/pat/set_memory.o
AR sound/i2c/other/built-in.a
AR sound/isa/ad1816a/built-in.a
CC block/partitions/ldm.o
AR sound/pci/ac97/built-in.a
CC arch/x86/events/intel/core.o
CC fs/notify/dnotify/dnotify.o
CC arch/x86/kernel/fpu/init.o
CC sound/core/seq/seq.o
AR arch/x86/platform/atom/built-in.a
AR sound/i2c/built-in.a
AR sound/drivers/opl4/built-in.a
AR sound/pci/ali5451/built-in.a
AR sound/isa/ad1848/built-in.a
CC lib/kunit/test.o
AR drivers/bus/mhi/built-in.a
AR arch/x86/platform/ce4100/built-in.a
CC arch/x86/kernel/cpu/mce/core.o
AR sound/drivers/mpu401/built-in.a
CC net/core/request_sock.o
CC arch/x86/entry/vdso/vma.o
CC arch/x86/lib/cmdline.o
AR drivers/bus/built-in.a
AR sound/pci/asihpi/built-in.a
AR sound/isa/cs423x/built-in.a
CC arch/x86/platform/efi/memmap.o
CC arch/x86/events/zhaoxin/core.o
AR sound/drivers/vx/built-in.a
CC kernel/sched/core.o
CC mm/kasan/common.o
AR sound/pci/au88x0/built-in.a
AR sound/isa/es1688/built-in.a
CC arch/x86/crypto/aesni-intel_glue.o
AR drivers/phy/allwinner/built-in.a
AR sound/drivers/pcsp/built-in.a
AR sound/drivers/built-in.a
AR sound/pci/aw2/built-in.a
AR sound/isa/galaxy/built-in.a
CC crypto/api.o
AR drivers/phy/amlogic/built-in.a
AR sound/pci/ctxfi/built-in.a
AR sound/isa/gus/built-in.a
CC sound/core/sound.o
AR drivers/phy/broadcom/built-in.a
AR sound/isa/msnd/built-in.a
AR sound/pci/ca0106/built-in.a
AR drivers/phy/cadence/built-in.a
AR sound/isa/opti9xx/built-in.a
AR sound/pci/cs46xx/built-in.a
AR drivers/phy/freescale/built-in.a
AR sound/isa/sb/built-in.a
AR sound/pci/cs5535audio/built-in.a
AR sound/isa/wavefront/built-in.a
AR drivers/phy/hisilicon/built-in.a
AR sound/pci/lola/built-in.a
AR sound/isa/wss/built-in.a
AR drivers/phy/ingenic/built-in.a
AR sound/pci/lx6464es/built-in.a
AR sound/isa/built-in.a
AR drivers/phy/intel/built-in.a
AS arch/x86/lib/cmpxchg16b_emu.o
AR sound/pci/echoaudio/built-in.a
AR drivers/phy/lantiq/built-in.a
AR sound/pci/emu10k1/built-in.a
AR drivers/phy/marvell/built-in.a
CC arch/x86/lib/copy_mc.o
AR sound/pci/hda/built-in.a
AR drivers/phy/mediatek/built-in.a
AR drivers/pinctrl/actions/built-in.a
CC [M] sound/pci/hda/hda_bind.o
AR drivers/phy/microchip/built-in.a
AR drivers/pinctrl/bcm/built-in.a
AR drivers/phy/motorola/built-in.a
AR drivers/pinctrl/cirrus/built-in.a
AR drivers/phy/mscc/built-in.a
AR drivers/pinctrl/freescale/built-in.a
AR drivers/phy/qualcomm/built-in.a
CC drivers/pinctrl/intel/pinctrl-baytrail.o
AR drivers/phy/ralink/built-in.a
AR drivers/phy/renesas/built-in.a
GEN usr/initramfs_data.cpio
COPY usr/initramfs_inc_data
AS usr/initramfs_data.o
AR drivers/phy/rockchip/built-in.a
AR drivers/phy/samsung/built-in.a
AR usr/built-in.a
AR drivers/phy/socionext/built-in.a
CC drivers/pinctrl/intel/pinctrl-intel.o
AR drivers/phy/st/built-in.a
AR drivers/phy/sunplus/built-in.a
AR drivers/phy/tegra/built-in.a
AR drivers/phy/ti/built-in.a
AR drivers/phy/xilinx/built-in.a
CC drivers/phy/phy-core.o
AR virt/built-in.a
AS arch/x86/lib/copy_mc_64.o
CC lib/kunit/resource.o
AS arch/x86/lib/copy_page_64.o
AS arch/x86/lib/copy_user_64.o
CC sound/core/seq/seq_lock.o
CC lib/kunit/static_stub.o
AS arch/x86/realmode/rm/header.o
CC arch/x86/lib/cpu.o
CC lib/kunit/string-stream.o
CC arch/x86/kernel/fpu/bugs.o
AS arch/x86/realmode/rm/trampoline_64.o
CC security/keys/key.o
CC arch/x86/lib/delay.o
AS arch/x86/realmode/rm/stack.o
CC init/calibrate.o
CC mm/kasan/report.o
AR fs/notify/dnotify/built-in.a
AS arch/x86/realmode/rm/reboot.o
CC arch/x86/kernel/fpu/core.o
CC fs/notify/inotify/inotify_fsnotify.o
AS arch/x86/realmode/rm/wakeup_asm.o
CC fs/notify/inotify/inotify_user.o
CC arch/x86/pci/init.o
CC arch/x86/realmode/rm/wakemain.o
CC sound/core/seq/seq_clientmgr.o
AR arch/x86/platform/geode/built-in.a
CC lib/kunit/assert.o
CC arch/x86/pci/mmconfig_64.o
CC arch/x86/platform/efi/quirks.o
CC arch/x86/realmode/rm/video-mode.o
CC crypto/cipher.o
CC arch/x86/entry/vdso/extable.o
CC arch/x86/power/hibernate.o
CC mm/filemap.o
CC arch/x86/pci/direct.o
AR arch/x86/events/zhaoxin/built-in.a
CC drivers/gpio/gpiolib.o
CC mm/mempool.o
CC [M] sound/pci/hda/hda_codec.o
AS arch/x86/realmode/rm/copy.o
CC net/core/skbuff.o
AS arch/x86/lib/getuser.o
CC arch/x86/entry/vdso/vdso32-setup.o
AS arch/x86/realmode/rm/bioscall.o
AR arch/x86/platform/iris/built-in.a
CC [M] sound/pci/hda/hda_jack.o
GEN arch/x86/lib/inat-tables.c
CC block/bio.o
CC fs/notify/fanotify/fanotify.o
CC arch/x86/realmode/rm/regs.o
CC fs/notify/fanotify/fanotify_user.o
CC block/partitions/msdos.o
CC arch/x86/lib/insn-eval.o
CC arch/x86/realmode/rm/video-vga.o
AS arch/x86/crypto/aesni-intel_avx-x86_64.o
CC arch/x86/realmode/rm/video-vesa.o
CC arch/x86/events/amd/lbr.o
CC arch/x86/kernel/fpu/regset.o
CC init/init_task.o
CC arch/x86/realmode/rm/video-bios.o
CC drivers/gpio/gpiolib-devres.o
CC init/version.o
LDS arch/x86/entry/vdso/vdso.lds
CC arch/x86/platform/efi/efi.o
CC arch/x86/platform/efi/efi_64.o
AR arch/x86/net/built-in.a
AS arch/x86/entry/vdso/vdso-note.o
CC arch/x86/kernel/fpu/signal.o
CC drivers/gpio/gpiolib-legacy.o
CC arch/x86/mm/pat/memtype.o
PASYMS arch/x86/realmode/rm/pasyms.h
LDS arch/x86/realmode/rm/realmode.lds
LD arch/x86/realmode/rm/realmode.elf
CC crypto/compress.o
RELOCS arch/x86/realmode/rm/realmode.relocs
OBJCOPY arch/x86/realmode/rm/realmode.bin
AS arch/x86/realmode/rmpiggy.o
CC lib/kunit/try-catch.o
CC security/min_addr.o
AR arch/x86/realmode/built-in.a
CC block/elevator.o
CC lib/kunit/executor.o
AS arch/x86/crypto/aes_ctrby8_avx-x86_64.o
AR drivers/phy/built-in.a
AR sound/pci/ice1712/built-in.a
AR sound/pci/korg1212/built-in.a
CC fs/notify/fsnotify.o
AR sound/pci/mixart/built-in.a
AS [M] arch/x86/crypto/ghash-clmulni-intel_asm.o
CC ipc/mqueue.o
CC mm/oom_kill.o
CC mm/kasan/init.o
CC [M] arch/x86/crypto/ghash-clmulni-intel_glue.o
CC arch/x86/mm/pat/memtype_interval.o
AR drivers/pinctrl/mediatek/built-in.a
CC arch/x86/entry/vdso/vclock_gettime.o
CC fs/notify/notification.o
CC arch/x86/pci/mmconfig-shared.o
AR arch/x86/power/built-in.a
CC ipc/namespace.o
CC security/keys/keyring.o
CC arch/x86/events/intel/bts.o
CC [M] drivers/pinctrl/intel/pinctrl-cherryview.o
CC [M] drivers/pinctrl/intel/pinctrl-broxton.o
CC crypto/algapi.o
AR fs/notify/inotify/built-in.a
AR drivers/pwm/built-in.a
CC lib/math/div64.o
CC lib/math/gcd.o
CC lib/math/lcm.o
CC arch/x86/kernel/cpu/mce/severity.o
CC lib/math/int_pow.o
CC lib/math/int_sqrt.o
CC lib/kunit/hooks.o
CC arch/x86/kernel/cpu/mce/genpool.o
CC block/blk-core.o
AR init/built-in.a
CC lib/math/reciprocal_div.o
CC arch/x86/kernel/fpu/xstate.o
CC crypto/scatterwalk.o
CC mm/fadvise.o
CC block/partitions/efi.o
CC [M] drivers/pinctrl/intel/pinctrl-geminilake.o
CC mm/maccess.o
CC arch/x86/events/amd/ibs.o
CC lib/math/rational.o
CC arch/x86/lib/insn.o
AR sound/pci/nm256/built-in.a
CC drivers/gpio/gpiolib-cdev.o
CC kernel/locking/mutex.o
AS [M] arch/x86/crypto/crc32-pclmul_asm.o
CC drivers/gpio/gpiolib-sysfs.o
AR lib/kunit/built-in.a
AS arch/x86/platform/efi/efi_stub_64.o
CC arch/x86/entry/vdso/vgetcpu.o
HOSTCC arch/x86/entry/vdso/vdso2c
CC [M] arch/x86/crypto/crc32-pclmul_glue.o
LDS arch/x86/entry/vdso/vdso32/vdso32.lds
CC sound/core/seq/seq_memory.o
CC arch/x86/events/amd/uncore.o
AR arch/x86/platform/efi/built-in.a
AS arch/x86/entry/vdso/vdso32/note.o
AS arch/x86/entry/vdso/vdso32/system_call.o
AR arch/x86/mm/pat/built-in.a
CC arch/x86/platform/intel/iosf_mbi.o
CC arch/x86/mm/init.o
CC ipc/mq_sysctl.o
CC kernel/power/qos.o
CC sound/core/seq/seq_queue.o
AR sound/pci/oxygen/built-in.a
CC arch/x86/kernel/cpu/mce/intel.o
AS arch/x86/lib/memcpy_64.o
CC kernel/printk/printk.o
AS arch/x86/lib/memmove_64.o
AR sound/pci/pcxhr/built-in.a
AS arch/x86/lib/memset_64.o
AR sound/pci/riptide/built-in.a
AR arch/x86/platform/intel-mid/built-in.a
CC security/inode.o
CC [M] drivers/pinctrl/intel/pinctrl-sunrisepoint.o
CC [M] lib/math/prime_numbers.o
CC mm/kasan/generic.o
CC arch/x86/lib/misc.o
CC sound/core/seq/seq_fifo.o
AR arch/x86/platform/intel-quark/built-in.a
CC fs/notify/group.o
CC kernel/irq/irqdesc.o
CC arch/x86/lib/pc-conf-reg.o
AS arch/x86/entry/vdso/vdso32/sigreturn.o
AR fs/notify/fanotify/built-in.a
CC arch/x86/entry/vdso/vdso32/vclock_gettime.o
CC crypto/proc.o
CC block/blk-sysfs.o
CC fs/notify/mark.o
CC arch/x86/pci/fixup.o
CC drivers/gpio/gpiolib-acpi.o
CC kernel/locking/semaphore.o
CC kernel/irq/handle.o
AS [M] arch/x86/crypto/crct10dif-pcl-asm_64.o
CC [M] arch/x86/crypto/crct10dif-pclmul_glue.o
AS arch/x86/lib/putuser.o
CC mm/kasan/report_generic.o
CC mm/kasan/shadow.o
AS arch/x86/lib/retpoline.o
CC arch/x86/lib/usercopy.o
AR block/partitions/built-in.a
CC block/blk-flush.o
CC block/blk-settings.o
CC kernel/locking/rwsem.o
CC kernel/locking/percpu-rwsem.o
CC security/keys/keyctl.o
CC arch/x86/kernel/cpu/mce/threshold.o
CC arch/x86/events/intel/ds.o
AR arch/x86/platform/intel/built-in.a
CC arch/x86/kernel/cpu/mce/apei.o
AR arch/x86/platform/olpc/built-in.a
CC arch/x86/pci/acpi.o
AR lib/math/built-in.a
AR arch/x86/platform/scx200/built-in.a
AR drivers/pinctrl/intel/built-in.a
AR arch/x86/platform/ts5500/built-in.a
AR drivers/pinctrl/mvebu/built-in.a
CC lib/crypto/memneq.o
AR arch/x86/platform/uv/built-in.a
AR drivers/pinctrl/nomadik/built-in.a
AR arch/x86/platform/built-in.a
AR drivers/pinctrl/nuvoton/built-in.a
AR drivers/pinctrl/sprd/built-in.a
AR drivers/pinctrl/sunplus/built-in.a
CC sound/core/seq/seq_timer.o
CC sound/core/seq/seq_prioq.o
CC sound/core/seq/seq_system.o
AR drivers/pinctrl/ti/built-in.a
CC lib/zlib_inflate/inffast.o
CC drivers/pinctrl/core.o
CC [M] arch/x86/kvm/../../../virt/kvm/kvm_main.o
LD [M] arch/x86/crypto/ghash-clmulni-intel.o
LD [M] arch/x86/crypto/crc32-pclmul.o
CC crypto/aead.o
LD [M] arch/x86/crypto/crct10dif-pclmul.o
AR arch/x86/events/amd/built-in.a
CC sound/core/seq/seq_ports.o
AR arch/x86/crypto/built-in.a
CC arch/x86/lib/usercopy_64.o
CC arch/x86/entry/vdso/vdso32/vgetcpu.o
AR arch/x86/kernel/fpu/built-in.a
CC arch/x86/entry/vsyscall/vsyscall_64.o
AS arch/x86/entry/entry.o
CC kernel/power/main.o
CC [M] sound/pci/hda/hda_auto_parser.o
CC arch/x86/mm/init_64.o
CC lib/crypto/utils.o
VDSO arch/x86/entry/vdso/vdso64.so.dbg
CC [M] sound/pci/hda/hda_sysfs.o
CC lib/zlib_inflate/inflate.o
VDSO arch/x86/entry/vdso/vdso32.so.dbg
CC kernel/locking/irqflag-debug.o
CC drivers/pinctrl/pinctrl-utils.o
CC kernel/irq/manage.o
OBJCOPY arch/x86/entry/vdso/vdso64.so
OBJCOPY arch/x86/entry/vdso/vdso32.so
VDSO2C arch/x86/entry/vdso/vdso-image-64.c
CC [M] sound/pci/hda/hda_controller.o
VDSO2C arch/x86/entry/vdso/vdso-image-32.c
CC arch/x86/entry/vdso/vdso-image-64.o
CC arch/x86/kernel/acpi/boot.o
AR ipc/built-in.a
CC arch/x86/kernel/apic/apic.o
CC mm/kasan/quarantine.o
CC arch/x86/pci/legacy.o
CC arch/x86/kernel/apic/apic_common.o
CC arch/x86/kernel/acpi/sleep.o
CC lib/zlib_inflate/infutil.o
CC fs/notify/fdinfo.o
CC kernel/irq/spurious.o
CC arch/x86/mm/fault.o
CC arch/x86/entry/vdso/vdso-image-32.o
AS arch/x86/entry/vsyscall/vsyscall_emu_64.o
CC crypto/geniv.o
CC arch/x86/kernel/apic/apic_noop.o
CC arch/x86/kernel/apic/ipi.o
CC block/blk-ioc.o
CC net/core/datagram.o
CC lib/crypto/chacha.o
AR arch/x86/kernel/cpu/mce/built-in.a
CC net/core/stream.o
CC arch/x86/lib/msr-smp.o
CC arch/x86/kernel/cpu/mtrr/mtrr.o
CC drivers/gpio/gpiolib-swnode.o
CC arch/x86/kernel/cpu/mtrr/if.o
CC kernel/irq/resend.o
AR arch/x86/entry/vdso/built-in.a
CC sound/core/seq/seq_info.o
CC arch/x86/kernel/cpu/mtrr/generic.o
CC arch/x86/kernel/cpu/mtrr/cleanup.o
CC sound/core/init.o
CC sound/core/memory.o
CC lib/crypto/aes.o
CC arch/x86/kernel/apic/vector.o
CC arch/x86/events/intel/knc.o
AS arch/x86/entry/entry_64.o
CC kernel/locking/mutex-debug.o
CC arch/x86/entry/syscall_64.o
CC crypto/skcipher.o
CC arch/x86/pci/irq.o
CC arch/x86/lib/cache-smp.o
CC lib/zlib_inflate/inftrees.o
CC arch/x86/lib/msr.o
AR arch/x86/entry/vsyscall/built-in.a
CC drivers/pinctrl/pinmux.o
CC sound/core/control.o
CC [M] arch/x86/kvm/../../../virt/kvm/eventfd.o
AR fs/notify/built-in.a
CC security/keys/permission.o
CC fs/nfs_common/grace.o
AS arch/x86/kernel/acpi/wakeup_64.o
CC arch/x86/kernel/acpi/apei.o
AR mm/kasan/built-in.a
CC kernel/power/console.o
CC [M] sound/pci/hda/hda_proc.o
CC arch/x86/kernel/acpi/cppc.o
CC lib/zlib_inflate/inflate_syms.o
CC [M] arch/x86/kvm/../../../virt/kvm/binary_stats.o
CC [M] arch/x86/kvm/../../../virt/kvm/vfio.o
AR drivers/gpio/built-in.a
CC kernel/power/process.o
CC drivers/pinctrl/pinconf.o
AS arch/x86/lib/msr-reg.o
AR sound/core/seq/built-in.a
CC arch/x86/pci/common.o
CC kernel/printk/printk_safe.o
CC net/llc/llc_core.o
CC mm/page-writeback.o
CC net/llc/llc_input.o
CC [M] arch/x86/kvm/../../../virt/kvm/coalesced_mmio.o
CC [M] sound/pci/hda/hda_hwdep.o
CC lib/zlib_deflate/deflate.o
CC block/blk-map.o
CC lib/zlib_deflate/deftree.o
CC lib/crypto/gf128mul.o
CC lib/zlib_deflate/deflate_syms.o
CC kernel/locking/lockdep.o
AR lib/zlib_inflate/built-in.a
AR sound/arm/built-in.a
CC [M] arch/x86/kvm/../../../virt/kvm/async_pf.o
CC arch/x86/events/intel/lbr.o
CC arch/x86/entry/common.o
CC sound/core/misc.o
CC arch/x86/events/intel/p4.o
AS arch/x86/entry/thunk_64.o
CC security/keys/process_keys.o
CC security/keys/request_key.o
CC [M] sound/pci/hda/hda_generic.o
CC security/keys/request_key_auth.o
CC security/keys/user_defined.o
CC kernel/irq/chip.o
CC arch/x86/kernel/acpi/cstate.o
AR arch/x86/kernel/cpu/mtrr/built-in.a
CC arch/x86/kernel/cpu/cacheinfo.o
CC security/keys/compat.o
CC io_uring/xattr.o
CC arch/x86/lib/msr-reg-export.o
CC sound/core/device.o
AR fs/nfs_common/built-in.a
CC arch/x86/mm/ioremap.o
CC fs/iomap/trace.o
CC kernel/printk/printk_ringbuffer.o
CC sound/core/info.o
CC fs/iomap/iter.o
CC drivers/pinctrl/pinconf-generic.o
AS arch/x86/lib/hweight.o
CC fs/iomap/buffered-io.o
CC arch/x86/lib/iomem.o
CC lib/crypto/blake2s.o
CC net/llc/llc_output.o
CC arch/x86/mm/extable.o
CC arch/x86/pci/early.o
CC arch/x86/mm/mmap.o
AR sound/pci/rme9652/built-in.a
CC net/core/scm.o
CC [M] arch/x86/kvm/../../../virt/kvm/irqchip.o
AR sound/pci/trident/built-in.a
CC arch/x86/pci/bus_numa.o
CC crypto/seqiv.o
AR sound/pci/ymfpci/built-in.a
CC crypto/echainiv.o
CC lib/lzo/lzo1x_compress.o
CC lib/lz4/lz4_compress.o
CC lib/zstd/zstd_compress_module.o
CC kernel/power/suspend.o
CC lib/zstd/compress/fse_compress.o
CC kernel/power/hibernate.o
CC lib/xz/xz_dec_syms.o
AR arch/x86/kernel/acpi/built-in.a
CC lib/xz/xz_dec_stream.o
CC lib/raid6/algos.o
AS arch/x86/lib/iomap_copy_64.o
AS arch/x86/entry/entry_64_compat.o
CC lib/raid6/recov.o
CC arch/x86/kernel/apic/hw_nmi.o
CC arch/x86/lib/inat.o
CC lib/crypto/blake2s-generic.o
CC arch/x86/entry/syscall_32.o
AR lib/zlib_deflate/built-in.a
CC security/device_cgroup.o
CC drivers/pci/msi/pcidev_msi.o
CC drivers/pci/msi/api.o
AR drivers/pinctrl/built-in.a
CC drivers/pci/msi/msi.o
CC block/blk-merge.o
CC kernel/printk/sysctl.o
AR arch/x86/lib/built-in.a
AR arch/x86/lib/lib.a
CC drivers/pci/msi/irqdomain.o
CC drivers/pci/pcie/portdrv.o
CC drivers/pci/pcie/rcec.o
CC crypto/ahash.o
CC io_uring/nop.o
CC security/keys/proc.o
CC drivers/pci/hotplug/pci_hotplug_core.o
CC drivers/pci/pcie/aspm.o
CC drivers/pci/hotplug/acpi_pcihp.o
CC lib/xz/xz_dec_lzma2.o
CC lib/lzo/lzo1x_decompress_safe.o
CC lib/zstd/compress/hist.o
CC drivers/video/console/dummycon.o
CC sound/core/isadma.o
CC drivers/video/console/vgacon.o
AR kernel/printk/built-in.a
CC drivers/pci/hotplug/pciehp_core.o
CC kernel/irq/dummychip.o
CC arch/x86/events/core.o
CC sound/core/vmaster.o
CC arch/x86/pci/amd_bus.o
AR net/llc/built-in.a
CC arch/x86/kernel/cpu/scattered.o
CC arch/x86/mm/pgtable.o
CC drivers/pci/pcie/aer.o
AR drivers/pci/controller/dwc/built-in.a
CC arch/x86/events/intel/p6.o
CC lib/zstd/compress/huf_compress.o
AR drivers/pci/controller/mobiveil/built-in.a
CC drivers/pci/controller/vmd.o
CC kernel/irq/devres.o
CC arch/x86/kernel/apic/io_apic.o
CC sound/core/ctljack.o
CC io_uring/fs.o
AR arch/x86/entry/built-in.a
CC lib/zstd/compress/zstd_compress.o
CC lib/zstd/compress/zstd_compress_literals.o
HOSTCC lib/raid6/mktables
CC io_uring/splice.o
CC io_uring/sync.o
CC lib/crypto/blake2s-selftest.o
CC arch/x86/kernel/apic/msi.o
AR drivers/pci/switch/built-in.a
CC net/ethernet/eth.o
AR lib/lzo/built-in.a
CC kernel/irq/autoprobe.o
CC drivers/pci/pcie/err.o
UNROLL lib/raid6/int1.c
CC arch/x86/kernel/cpu/topology.o
UNROLL lib/raid6/int2.c
UNROLL lib/raid6/int4.c
UNROLL lib/raid6/int8.c
UNROLL lib/raid6/int16.c
CC net/core/gen_stats.o
UNROLL lib/raid6/int32.c
CC lib/raid6/recov_ssse3.o
CC drivers/pci/access.o
CC arch/x86/kernel/apic/x2apic_phys.o
CC security/keys/sysctl.o
CC kernel/irq/irqdomain.o
CC lib/raid6/recov_avx2.o
CC kernel/power/snapshot.o
CC sound/core/jack.o
CC lib/lz4/lz4hc_compress.o
CC kernel/sched/fair.o
CC net/802/p8022.o
CC lib/crypto/des.o
CC net/802/psnap.o
CC net/802/stp.o
AR drivers/pci/msi/built-in.a
CC lib/crypto/sha1.o
CC lib/xz/xz_dec_bcj.o
CC lib/zstd/compress/zstd_compress_sequences.o
CC mm/folio-compat.o
CC crypto/shash.o
CC io_uring/advise.o
CC drivers/pci/hotplug/pciehp_ctrl.o
CC arch/x86/events/intel/pt.o
AR arch/x86/pci/built-in.a
CC [M] arch/x86/kvm/../../../virt/kvm/dirty_ring.o
CC [M] arch/x86/kvm/../../../virt/kvm/pfncache.o
CC arch/x86/kernel/cpu/common.o
CC arch/x86/mm/physaddr.o
CC arch/x86/mm/tlb.o
AR security/keys/built-in.a
AR drivers/video/console/built-in.a
AR security/built-in.a
CC arch/x86/mm/cpu_entry_area.o
CC drivers/video/logo/logo.o
CC arch/x86/mm/maccess.o
HOSTCC drivers/video/logo/pnmtologo
CC lib/lz4/lz4_decompress.o
CC kernel/irq/proc.o
CC arch/x86/kernel/cpu/rdrand.o
CC [M] arch/x86/kvm/x86.o
CC [M] arch/x86/kvm/emulate.o
AR drivers/pci/controller/built-in.a
CC io_uring/filetable.o
CC fs/iomap/direct-io.o
CC kernel/irq/migration.o
CC arch/x86/mm/pgprot.o
CC kernel/sched/build_policy.o
CC io_uring/openclose.o
CC lib/raid6/mmx.o
CC block/blk-timeout.o
CC lib/raid6/sse1.o
AR lib/xz/built-in.a
CC lib/zstd/compress/zstd_compress_superblock.o
CC drivers/pci/pcie/aer_inject.o
CC lib/raid6/sse2.o
CC sound/core/timer.o
CC net/core/gen_estimator.o
CC mm/readahead.o
CC arch/x86/kernel/apic/x2apic_cluster.o
LOGO drivers/video/logo/logo_linux_clut224.c
CC drivers/pci/bus.o
CC drivers/video/logo/logo_linux_clut224.o
CC drivers/pci/probe.o
CC net/core/net_namespace.o
CC arch/x86/kernel/kprobes/core.o
CC arch/x86/kernel/kprobes/opt.o
CC sound/core/hrtimer.o
AR drivers/video/logo/built-in.a
AR net/802/built-in.a
CC sound/core/seq_device.o
CC lib/raid6/avx2.o
CC drivers/video/backlight/backlight.o
CC arch/x86/kernel/kprobes/ftrace.o
CC kernel/rcu/update.o
CC drivers/pci/hotplug/pciehp_pci.o
CC crypto/akcipher.o
CC arch/x86/mm/hugetlbpage.o
CC [M] arch/x86/kvm/i8259.o
AR net/ethernet/built-in.a
CC [M] arch/x86/kvm/irq.o
CC [M] sound/core/control_led.o
CC lib/crypto/sha256.o
CC [M] sound/core/hwdep.o
CC crypto/kpp.o
CC arch/x86/kernel/apic/apic_flat_64.o
CC io_uring/uring_cmd.o
CC kernel/irq/cpuhotplug.o
CC block/blk-lib.o
CC arch/x86/kernel/apic/probe_64.o
CC kernel/power/swap.o
CC lib/raid6/avx512.o
CC kernel/power/user.o
CC io_uring/epoll.o
AR kernel/livepatch/built-in.a
CC [M] arch/x86/kvm/lapic.o
CC block/blk-mq.o
CC arch/x86/events/intel/uncore.o
CC arch/x86/events/probe.o
CC drivers/pci/pcie/pme.o
CC lib/raid6/recov_avx512.o
CC kernel/sched/build_utility.o
AR lib/lz4/built-in.a
CC fs/iomap/fiemap.o
CC drivers/video/fbdev/core/fb_notify.o
AR drivers/video/fbdev/omap/built-in.a
CC lib/argv_split.o
CC lib/fonts/fonts.o
CC drivers/pci/hotplug/pciehp_hpc.o
CC drivers/pci/host-bridge.o
CC drivers/idle/intel_idle.o
CC net/core/secure_seq.o
CC net/core/flow_dissector.o
CC [M] lib/crypto/arc4.o
CC net/core/sysctl_net_core.o
AR arch/x86/kernel/apic/built-in.a
CC arch/x86/kernel/cpu/match.o
CC mm/swap.o
CC io_uring/statx.o
AR drivers/video/backlight/built-in.a
CC fs/iomap/seek.o
AR arch/x86/kernel/kprobes/built-in.a
CC kernel/irq/pm.o
AR fs/quota/built-in.a
CC arch/x86/kernel/cpu/bugs.o
CC crypto/acompress.o
CC arch/x86/mm/kasan_init_64.o
CC io_uring/net.o
CC [M] drivers/video/fbdev/core/fbmem.o
CC kernel/dma/mapping.o
CC kernel/dma/direct.o
CC fs/proc/task_mmu.o
CC kernel/dma/ops_helpers.o
CC lib/fonts/font_8x8.o
CC kernel/locking/lockdep_proc.o
CC kernel/dma/dummy.o
CC lib/fonts/font_8x16.o
AR lib/crypto/built-in.a
CC drivers/pci/remove.o
LD [M] lib/crypto/libarc4.o
CC lib/zstd/compress/zstd_double_fast.o
CC arch/x86/kernel/cpu/aperfmperf.o
CC [M] sound/pci/hda/patch_realtek.o
TABLE lib/raid6/tables.c
CC fs/kernfs/mount.o
CC lib/raid6/int1.o
CC arch/x86/events/utils.o
CC drivers/pci/pcie/dpc.o
CC fs/iomap/swapfile.o
CC kernel/rcu/sync.o
CC drivers/pci/pci.o
CC fs/sysfs/file.o
CC kernel/entry/common.o
CC [M] sound/core/pcm.o
CC kernel/entry/syscall_user_dispatch.o
CC [M] sound/core/pcm_native.o
CC arch/x86/mm/pkeys.o
AR lib/fonts/built-in.a
CC [M] arch/x86/kvm/i8254.o
CC lib/zstd/compress/zstd_fast.o
CC kernel/rcu/srcutree.o
CC kernel/irq/msi.o
CC kernel/irq/affinity.o
CC kernel/dma/contiguous.o
CC kernel/module/main.o
CC [M] arch/x86/kvm/ioapic.o
CC crypto/scompress.o
CC kernel/module/strict_rwx.o
CC arch/x86/events/rapl.o
CC kernel/power/poweroff.o
CC drivers/pci/hotplug/acpiphp_core.o
CC kernel/entry/kvm.o
CC lib/zstd/compress/zstd_lazy.o
CC lib/raid6/int2.o
CC io_uring/msg_ring.o
AR drivers/idle/built-in.a
CC io_uring/timeout.o
CC kernel/dma/swiotlb.o
CC kernel/locking/spinlock.o
CC fs/kernfs/inode.o
CC drivers/pci/pci-driver.o
AR fs/iomap/built-in.a
CC arch/x86/kernel/cpu/cpuid-deps.o
CC lib/zstd/compress/zstd_ldm.o
AR kernel/power/built-in.a
CC drivers/video/aperture.o
CC kernel/time/time.o
AR drivers/pci/pcie/built-in.a
CC drivers/video/cmdline.o
CC arch/x86/mm/pti.o
CC fs/sysfs/dir.o
CC fs/kernfs/dir.o
CC arch/x86/events/intel/uncore_nhmex.o
CC kernel/dma/remap.o
CC drivers/pci/hotplug/acpiphp_glue.o
CC kernel/locking/osq_lock.o
CC net/core/dev.o
CC arch/x86/kernel/cpu/umwait.o
CC kernel/time/timer.o
AR sound/sh/built-in.a
CC [M] drivers/video/fbdev/core/fbmon.o
CC lib/raid6/int4.o
CC kernel/locking/qspinlock.o
CC crypto/algboss.o
AR sound/synth/emux/built-in.a
AR sound/synth/built-in.a
CC kernel/locking/rtmutex_api.o
CC fs/sysfs/symlink.o
AR drivers/char/ipmi/built-in.a
CC [M] drivers/video/fbdev/core/fbcmap.o
CC net/core/dev_addr_lists.o
AR kernel/entry/built-in.a
CC kernel/time/hrtimer.o
CC kernel/futex/core.o
CC kernel/futex/syscalls.o
CC kernel/cgroup/cgroup.o
CC kernel/trace/trace_clock.o
CC fs/sysfs/mount.o
CC mm/truncate.o
CC fs/proc/inode.o
CC kernel/cgroup/rstat.o
CC kernel/rcu/tree.o
CC kernel/cgroup/namespace.o
CC kernel/irq/matrix.o
CC fs/sysfs/group.o
AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a
AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a
AR drivers/video/fbdev/omap2/omapfb/built-in.a
AR arch/x86/mm/built-in.a
AR drivers/video/fbdev/omap2/built-in.a
CC io_uring/sqpoll.o
CC kernel/futex/pi.o
CC kernel/futex/requeue.o
CC kernel/rcu/rcu_segcblist.o
CC kernel/locking/spinlock_debug.o
CC kernel/trace/ftrace.o
CC arch/x86/kernel/cpu/proc.o
CC net/core/dst.o
AR kernel/dma/built-in.a
CC lib/bug.o
CC kernel/cgroup/cgroup-v1.o
CC [M] arch/x86/kvm/irq_comm.o
CC lib/raid6/int8.o
CC drivers/pci/search.o
CC arch/x86/events/intel/uncore_snb.o
CC crypto/testmgr.o
CC fs/kernfs/file.o
CC [M] drivers/video/fbdev/core/fbsysfs.o
AR drivers/pci/hotplug/built-in.a
CC drivers/pci/pci-sysfs.o
CC kernel/events/core.o
CC kernel/locking/qrwlock.o
CC kernel/cgroup/freezer.o
CC kernel/futex/waitwake.o
AR fs/sysfs/built-in.a
CC kernel/bpf/core.o
CC fs/configfs/inode.o
CC fs/devpts/inode.o
CC fs/ext4/balloc.o
CC fs/jbd2/transaction.o
CC fs/proc/root.o
CC fs/jbd2/commit.o
CC kernel/cgroup/legacy_freezer.o
CC block/blk-mq-tag.o
MKCAP arch/x86/kernel/cpu/capflags.c
CC fs/proc/base.o
CC kernel/fork.o
CC mm/vmscan.o
CC [M] sound/pci/hda/patch_analog.o
CC kernel/exec_domain.o
CC lib/raid6/int16.o
CC kernel/panic.o
CC io_uring/fdinfo.o
CC kernel/module/tree_lookup.o
AR kernel/locking/built-in.a
CC drivers/acpi/acpica/dsargs.o
AR kernel/irq/built-in.a
CC drivers/acpi/acpica/dscontrol.o
AR kernel/futex/built-in.a
CC kernel/time/timekeeping.o
CC drivers/acpi/apei/apei-base.o
CC drivers/pnp/pnpacpi/core.o
CC drivers/pnp/core.o
CC drivers/pnp/pnpacpi/rsparser.o
CC arch/x86/events/intel/uncore_snbep.o
CC drivers/acpi/apei/hest.o
CC fs/configfs/file.o
CC drivers/acpi/apei/erst.o
CC fs/kernfs/symlink.o
CC [M] drivers/video/fbdev/core/modedb.o
CC drivers/pci/rom.o
CC [M] sound/core/pcm_lib.o
AR fs/devpts/built-in.a
CC [M] drivers/video/fbdev/core/fbcvt.o
AR sound/usb/misc/built-in.a
AR sound/usb/usx2y/built-in.a
AR sound/usb/caiaq/built-in.a
CC kernel/cgroup/pids.o
CC lib/raid6/int32.o
AR sound/usb/6fire/built-in.a
CC lib/buildid.o
CC kernel/time/ntp.o
AR sound/usb/hiface/built-in.a
AR sound/usb/bcd2000/built-in.a
AR sound/usb/built-in.a
CC drivers/acpi/acpica/dsdebug.o
CC kernel/cgroup/cpuset.o
CC kernel/module/debug_kmemleak.o
CC fs/ramfs/inode.o
CC fs/hugetlbfs/inode.o
CC [M] sound/pci/hda/patch_hdmi.o
CC lib/cmdline.o
AR sound/firewire/built-in.a
CC fs/proc/generic.o
CC block/blk-stat.o
CC block/blk-mq-sysfs.o
CC lib/cpumask.o
CC [M] drivers/video/fbdev/core/fb_cmdline.o
CC net/sched/sch_generic.o
CC drivers/pci/setup-res.o
AR fs/kernfs/built-in.a
CC fs/configfs/dir.o
CC fs/jbd2/recovery.o
CC drivers/acpi/acpica/dsfield.o
CC drivers/acpi/acpica/dsinit.o
CC fs/ext4/bitmap.o
CC lib/raid6/tables.o
CC fs/ext4/block_validity.o
CC kernel/module/kallsyms.o
AR drivers/pnp/pnpacpi/built-in.a
CC kernel/module/procfs.o
AR sound/sparc/built-in.a
CC fs/proc/array.o
CC drivers/pnp/card.o
CC fs/ext4/dir.o
CC io_uring/tctx.o
CC arch/x86/events/msr.o
CC kernel/cpu.o
CC fs/ext4/ext4_jbd2.o
CC fs/ext4/extents.o
CC fs/ramfs/file-mmu.o
CC fs/ext4/extents_status.o
CC fs/ext4/file.o
CC drivers/acpi/apei/bert.o
CC [M] drivers/video/fbdev/core/fb_defio.o
CC drivers/pnp/driver.o
CC block/blk-mq-cpumap.o
CC drivers/acpi/acpica/dsmethod.o
AR sound/spi/built-in.a
CC drivers/pci/irq.o
CC fs/jbd2/checkpoint.o
CC kernel/time/clocksource.o
CC fs/jbd2/revoke.o
CC fs/jbd2/journal.o
CC lib/ctype.o
CC mm/shmem.o
CC mm/util.o
AR kernel/sched/built-in.a
CC kernel/module/sysfs.o
AR lib/raid6/built-in.a
CC crypto/cmac.o
CC fs/configfs/symlink.o
AR fs/ramfs/built-in.a
AR drivers/amba/built-in.a
CC fs/ext4/fsmap.o
AR drivers/acpi/pmic/built-in.a
AR sound/parisc/built-in.a
AR sound/pcmcia/vx/built-in.a
AR sound/pcmcia/pdaudiocf/built-in.a
AR sound/pcmcia/built-in.a
AR sound/mips/built-in.a
CC drivers/acpi/apei/ghes.o
CC drivers/pnp/resource.o
AR sound/pci/vx222/built-in.a
CC mm/mmzone.o
CC io_uring/poll.o
AR sound/soc/built-in.a
CC kernel/exit.o
CC mm/vmstat.o
CC kernel/time/jiffies.o
CC arch/x86/kernel/cpu/powerflags.o
CC drivers/acpi/acpica/dsmthdat.o
AR fs/hugetlbfs/built-in.a
CC mm/backing-dev.o
CC kernel/time/timer_list.o
CC [M] sound/core/pcm_misc.o
CC block/blk-mq-sched.o
AR kernel/bpf/built-in.a
CC mm/mm_init.o
CC drivers/video/nomodeset.o
CC drivers/pci/vpd.o
CC drivers/pnp/manager.o
CC [M] drivers/video/fbdev/core/fbcon.o
CC fs/proc/fd.o
CC arch/x86/kernel/cpu/feat_ctl.o
CC crypto/hmac.o
CC [M] sound/pci/hda/hda_eld.o
CC fs/configfs/mount.o
CC kernel/softirq.o
CC [M] sound/pci/hda/hda_intel.o
LD [M] sound/pci/hda/snd-hda-codec.o
CC arch/x86/events/intel/uncore_discovery.o
AR kernel/module/built-in.a
CC drivers/acpi/acpica/dsobject.o
LDS arch/x86/kernel/vmlinux.lds
CC lib/zstd/compress/zstd_opt.o
CC drivers/video/hdmi.o
CC drivers/acpi/acpica/dsopcode.o
CC kernel/resource.o
CC drivers/acpi/acpica/dspkginit.o
CC arch/x86/events/intel/cstate.o
CC drivers/pci/setup-bus.o
CC net/sched/sch_mq.o
CC drivers/pci/vc.o
CC kernel/trace/ring_buffer.o
CC [M] sound/core/pcm_memory.o
CC kernel/trace/trace.o
CC kernel/time/timeconv.o
CC mm/percpu.o
CC arch/x86/kernel/cpu/intel.o
CC kernel/time/timecounter.o
CC mm/slab_common.o
CC net/netlink/af_netlink.o
CC net/netlink/genetlink.o
CC drivers/pnp/support.o
CC fs/configfs/item.o
CC drivers/pnp/interface.o
CC crypto/vmac.o
CC drivers/pci/mmap.o
CC fs/proc/proc_tty.o
CC drivers/acpi/acpica/dsutils.o
AR drivers/acpi/apei/built-in.a
CC drivers/acpi/dptf/int340x_thermal.o
CC kernel/time/alarmtimer.o
CC io_uring/cancel.o
CC block/ioctl.o
CC kernel/time/posix-timers.o
CC crypto/xcbc.o
CC drivers/pnp/quirks.o
CC drivers/pci/setup-irq.o
CC [M] arch/x86/kvm/cpuid.o
CC arch/x86/kernel/cpu/intel_pconfig.o
CC io_uring/kbuf.o
AR arch/x86/events/intel/built-in.a
CC drivers/acpi/tables.o
AR arch/x86/events/built-in.a
CC block/genhd.o
CC mm/compaction.o
CC kernel/sysctl.o
AR kernel/rcu/built-in.a
CC [M] arch/x86/kvm/pmu.o
AR fs/configfs/built-in.a
CC crypto/crypto_null.o
CC [M] sound/core/memalloc.o
CC fs/fat/cache.o
CC [M] sound/core/pcm_timer.o
CC drivers/acpi/acpica/dswexec.o
AR kernel/cgroup/built-in.a
CC fs/fat/dir.o
CC lib/dec_and_lock.o
CC fs/proc/cmdline.o
CC kernel/capability.o
AR drivers/acpi/dptf/built-in.a
CC mm/interval_tree.o
CC fs/nfs/client.o
CC net/sched/sch_frag.o
CC fs/nfs/dir.o
CC fs/nfs/file.o
CC arch/x86/kernel/cpu/tsx.o
CC lib/zstd/zstd_decompress_module.o
CC [M] arch/x86/kvm/mtrr.o
LD [M] sound/core/snd-ctl-led.o
CC net/core/netevent.o
AR sound/atmel/built-in.a
AR sound/hda/built-in.a
CC [M] sound/hda/hda_bus_type.o
CC drivers/pnp/system.o
CC fs/ext4/fsync.o
AR sound/x86/built-in.a
CC io_uring/rsrc.o
CC [M] drivers/video/fbdev/core/bitblit.o
LD [M] sound/pci/hda/snd-hda-codec-generic.o
CC drivers/acpi/acpica/dswload.o
LD [M] sound/pci/hda/snd-hda-codec-realtek.o
CC crypto/md5.o
CC fs/proc/consoles.o
LD [M] sound/pci/hda/snd-hda-codec-analog.o
CC fs/proc/cpuinfo.o
LD [M] sound/pci/hda/snd-hda-codec-hdmi.o
LD [M] sound/pci/hda/snd-hda-intel.o
AR sound/pci/built-in.a
AR drivers/clk/actions/built-in.a
CC arch/x86/kernel/cpu/intel_epb.o
AR drivers/clk/analogbits/built-in.a
AR drivers/clk/bcm/built-in.a
CC arch/x86/kernel/cpu/amd.o
AR drivers/clk/imgtec/built-in.a
AR drivers/clk/imx/built-in.a
CC arch/x86/kernel/cpu/hygon.o
AR drivers/clk/ingenic/built-in.a
CC drivers/pci/proc.o
AR drivers/clk/mediatek/built-in.a
AR drivers/clk/microchip/built-in.a
CC fs/fat/fatent.o
AR drivers/clk/mstar/built-in.a
AR drivers/clk/mvebu/built-in.a
CC block/ioprio.o
CC lib/decompress.o
AR drivers/clk/ralink/built-in.a
AR drivers/clk/renesas/built-in.a
AR drivers/clk/socfpga/built-in.a
AR drivers/clk/sprd/built-in.a
AR drivers/clk/sunxi-ng/built-in.a
AR fs/jbd2/built-in.a
CC kernel/events/ring_buffer.o
AR drivers/clk/ti/built-in.a
AR drivers/clk/versatile/built-in.a
CC kernel/ptrace.o
CC lib/decompress_bunzip2.o
CC drivers/clk/x86/clk-lpss-atom.o
LD [M] sound/core/snd-hwdep.o
CC drivers/clk/x86/clk-pmc-atom.o
LD [M] sound/core/snd-pcm.o
CC kernel/user.o
AR drivers/pnp/built-in.a
CC [M] sound/hda/hdac_bus.o
AR sound/core/built-in.a
CC kernel/events/callchain.o
CC drivers/pci/slot.o
CC kernel/signal.o
CC drivers/acpi/acpica/dswload2.o
CC fs/ext4/hash.o
CC kernel/events/hw_breakpoint.o
CC crypto/sha1_generic.o
CC kernel/events/uprobes.o
CC kernel/sys.o
CC fs/ext4/ialloc.o
CC kernel/umh.o
CC fs/proc/devices.o
CC kernel/time/posix-cpu-timers.o
CC net/core/neighbour.o
CC arch/x86/kernel/cpu/centaur.o
CC net/sched/sch_api.o
CC [M] sound/hda/hdac_device.o
CC arch/x86/kernel/cpu/zhaoxin.o
CC kernel/workqueue.o
CC [M] drivers/video/fbdev/core/softcursor.o
CC [M] drivers/video/fbdev/core/tileblit.o
AR drivers/clk/x86/built-in.a
AR drivers/clk/xilinx/built-in.a
CC drivers/acpi/acpica/dswscope.o
CC drivers/clk/clk-devres.o
CC mm/list_lru.o
CC kernel/time/posix-clock.o
CC block/badblocks.o
CC fs/ext4/indirect.o
CC kernel/pid.o
CC kernel/task_work.o
CC crypto/sha256_generic.o
CC lib/decompress_inflate.o
CC drivers/acpi/acpica/dswstate.o
CC kernel/time/itimer.o
CC fs/proc/interrupts.o
CC crypto/sha512_generic.o
CC arch/x86/kernel/cpu/perfctr-watchdog.o
CC drivers/pci/pci-acpi.o
CC fs/exportfs/expfs.o
CC arch/x86/kernel/cpu/vmware.o
CC mm/workingset.o
CC [M] drivers/video/fbdev/core/cfbfillrect.o
CC fs/fat/file.o
CC fs/lockd/clntlock.o
CC fs/ext4/inline.o
CC fs/nls/nls_base.o
AR fs/unicode/built-in.a
CC fs/nls/nls_cp437.o
AR net/bpf/built-in.a
CC drivers/clk/clk-bulk.o
CC fs/ntfs/aops.o
CC fs/fat/inode.o
CC drivers/clk/clkdev.o
CC [M] drivers/video/fbdev/core/cfbcopyarea.o
CC net/netlink/policy.o
CC [M] sound/hda/hdac_sysfs.o
CC [M] sound/hda/hdac_regmap.o
CC drivers/acpi/acpica/evevent.o
CC [M] sound/hda/hdac_controller.o
CC block/blk-rq-qos.o
CC fs/proc/loadavg.o
CC fs/nls/nls_ascii.o
CC fs/nfs/getroot.o
CC io_uring/rw.o
CC lib/decompress_unlz4.o
CC lib/decompress_unlzma.o
CC net/ethtool/ioctl.o
CC lib/decompress_unlzo.o
CC fs/fat/misc.o
CC arch/x86/kernel/cpu/hypervisor.o
CC block/disk-events.o
CC net/ethtool/common.o
AR fs/exportfs/built-in.a
CC kernel/time/clockevents.o
CC fs/autofs/init.o
CC crypto/blake2b_generic.o
CC net/ethtool/netlink.o
CC lib/decompress_unxz.o
CC fs/nls/nls_iso8859-1.o
CC crypto/ecb.o
CC drivers/clk/clk.o
CC drivers/acpi/acpica/evgpe.o
CC fs/debugfs/inode.o
CC arch/x86/kernel/cpu/mshyperv.o
CC fs/proc/meminfo.o
CC mm/debug.o
CC io_uring/opdef.o
CC drivers/pci/quirks.o
CC kernel/time/tick-common.o
CC kernel/extable.o
CC fs/autofs/inode.o
CC lib/decompress_unzstd.o
CC fs/lockd/clntproc.o
CC kernel/time/tick-broadcast.o
CC fs/lockd/clntxdr.o
CC net/netlink/diag.o
CC fs/autofs/root.o
CC io_uring/notif.o
AR kernel/events/built-in.a
CC fs/nls/nls_utf8.o
CC kernel/time/tick-broadcast-hrtimer.o
CC fs/ntfs/attrib.o
CC [M] drivers/video/fbdev/core/cfbimgblt.o
CC [M] sound/hda/hdac_stream.o
CC kernel/time/tick-oneshot.o
CC kernel/time/tick-sched.o
CC kernel/trace/trace_output.o
CC lib/zstd/decompress/huf_decompress.o
CC drivers/pci/ats.o
CC fs/proc/stat.o
CC block/blk-ia-ranges.o
CC crypto/cbc.o
CC fs/ntfs/collate.o
CC drivers/acpi/acpica/evgpeblk.o
CC fs/nfs/inode.o
CC [M] arch/x86/kvm/hyperv.o
CC fs/ext4/inode.o
CC net/ethtool/bitset.o
CC net/sched/sch_blackhole.o
CC lib/dump_stack.o
AR fs/nls/built-in.a
CC io_uring/io-wq.o
CC kernel/time/vsyscall.o
CC fs/fat/nfs.o
CC drivers/clk/clk-divider.o
CC drivers/clk/clk-fixed-factor.o
CC arch/x86/kernel/cpu/capflags.o
AS arch/x86/kernel/head_64.o
CC crypto/pcbc.o
CC fs/debugfs/file.o
AR arch/x86/kernel/cpu/built-in.a
CC fs/proc/uptime.o
CC arch/x86/kernel/head64.o
CC mm/gup.o
CC fs/tracefs/inode.o
CC mm/mmap_lock.o
CC crypto/cts.o
CC drivers/acpi/acpica/evgpeinit.o
CC drivers/clk/clk-fixed-rate.o
CC fs/ext4/ioctl.o
CC net/sched/sch_fifo.o
CC drivers/clk/clk-gate.o
CC fs/proc/util.o
CC drivers/clk/clk-multiplier.o
CC fs/autofs/symlink.o
CC drivers/acpi/acpica/evgpeutil.o
CC net/ethtool/strset.o
CC block/bsg.o
CC drivers/acpi/acpica/evglock.o
CC [M] drivers/video/fbdev/core/sysfillrect.o
CC net/ethtool/linkinfo.o
AR net/netlink/built-in.a
CC [M] arch/x86/kvm/debugfs.o
CC net/ethtool/linkmodes.o
CC [M] net/netfilter/ipvs/ip_vs_conn.o
AR net/ipv4/netfilter/built-in.a
CC [M] net/ipv4/netfilter/nf_defrag_ipv4.o
CC [M] sound/hda/array.o
CC [M] net/netfilter/ipvs/ip_vs_core.o
CC drivers/clk/clk-mux.o
CC fs/ntfs/compress.o
CC [M] net/netfilter/ipvs/ip_vs_ctl.o
CC kernel/time/timekeeping_debug.o
CC fs/fat/namei_vfat.o
CC kernel/time/namespace.o
CC [M] net/netfilter/ipvs/ip_vs_sched.o
CC [M] net/netfilter/ipvs/ip_vs_xmit.o
CC fs/lockd/host.o
CC fs/autofs/waitq.o
CC fs/proc/version.o
CC fs/proc/softirqs.o
CC arch/x86/kernel/ebda.o
CC fs/ntfs/debug.o
CC net/ethtool/rss.o
CC [M] drivers/video/fbdev/core/syscopyarea.o
CC net/netfilter/core.o
CC drivers/acpi/acpica/evhandler.o
CC kernel/trace/trace_seq.o
AR fs/tracefs/built-in.a
CC block/bsg-lib.o
CC crypto/lrw.o
AR fs/debugfs/built-in.a
CC kernel/params.o
CC net/core/rtnetlink.o
CC [M] sound/hda/hdmi_chmap.o
CC [M] net/netfilter/ipvs/ip_vs_app.o
CC [M] sound/hda/trace.o
CC kernel/kthread.o
CC fs/btrfs/super.o
CC drivers/acpi/acpica/evmisc.o
CC net/xfrm/xfrm_policy.o
AR net/sched/built-in.a
CC drivers/acpi/acpica/evregion.o
CC drivers/acpi/acpica/evrgnini.o
CC net/xfrm/xfrm_state.o
CC fs/proc/namespaces.o
CC arch/x86/kernel/platform-quirks.o
CC net/xfrm/xfrm_hash.o
CC net/core/utils.o
CC kernel/sys_ni.o
CC [M] sound/hda/hdac_component.o
CC fs/autofs/expire.o
CC fs/nfs/super.o
AR kernel/time/built-in.a
CC drivers/clk/clk-composite.o
CC fs/btrfs/ctree.o
CC arch/x86/kernel/process_64.o
AR io_uring/built-in.a
CC fs/proc/self.o
CC fs/autofs/dev-ioctl.o
CC drivers/pci/iov.o
CC kernel/trace/trace_stat.o
CC [M] net/ipv4/netfilter/nf_reject_ipv4.o
CC drivers/acpi/acpica/evsci.o
CC crypto/xts.o
CC block/blk-cgroup.o
CC [M] drivers/video/fbdev/core/sysimgblt.o
CC fs/ntfs/dir.o
CC net/ethtool/linkstate.o
CC net/ethtool/debug.o
CC [M] net/netfilter/ipvs/ip_vs_sync.o
CC fs/pstore/inode.o
CC fs/fat/namei_msdos.o
CC fs/pstore/platform.o
CC fs/pstore/pmsg.o
CC fs/proc/thread_self.o
CC fs/lockd/svc.o
CC [M] drivers/video/fbdev/core/fb_sys_fops.o
CC net/ipv4/route.o
CC [M] net/ipv4/netfilter/ip_tables.o
CC drivers/acpi/acpica/evxface.o
CC [M] net/ipv4/netfilter/iptable_filter.o
CC [M] sound/hda/hdac_i915.o
CC drivers/acpi/blacklist.o
CC kernel/nsproxy.o
CC fs/ext4/mballoc.o
AR fs/autofs/built-in.a
CC kernel/notifier.o
CC block/blk-cgroup-rwstat.o
CC kernel/ksysfs.o
CC [M] arch/x86/kvm/mmu/mmu.o
CC kernel/trace/trace_printk.o
CC net/core/link_watch.o
CC fs/nfs/io.o
CC crypto/ctr.o
CC kernel/cred.o
CC drivers/clk/clk-fractional-divider.o
CC mm/highmem.o
CC drivers/clk/clk-gpio.o
CC [M] net/netfilter/ipvs/ip_vs_est.o
CC [M] arch/x86/kvm/mmu/page_track.o
CC fs/proc/proc_sysctl.o
CC arch/x86/kernel/signal.o
CC fs/proc/proc_net.o
AR fs/pstore/built-in.a
CC [M] net/netfilter/ipvs/ip_vs_proto.o
CC fs/efivarfs/inode.o
CC drivers/pci/pci-label.o
CC drivers/acpi/acpica/evxfevnt.o
CC drivers/acpi/osi.o
CC [M] fs/netfs/buffered_read.o
CC [M] fs/netfs/io.o
CC net/ethtool/wol.o
AR fs/fat/built-in.a
CC [M] fs/netfs/iterator.o
CC [M] sound/hda/intel-dsp-config.o
LD [M] drivers/video/fbdev/core/fb.o
CC net/xfrm/xfrm_input.o
CC kernel/trace/pid_list.o
AR drivers/video/fbdev/core/built-in.a
CC [M] drivers/video/fbdev/uvesafb.o
CC fs/proc/kcore.o
CC fs/ntfs/file.o
CC net/ipv4/inetpeer.o
CC drivers/dma/dw/core.o
CC crypto/gcm.o
CC [M] drivers/video/fbdev/simplefb.o
CC kernel/trace/trace_sched_switch.o
CC drivers/dma/dw/dw.o
AR drivers/clk/built-in.a
CC drivers/dma/hsu/hsu.o
CC [M] fs/fscache/cache.o
CC mm/memory.o
CC [M] fs/fscache/cookie.o
CC drivers/acpi/acpica/evxfgpe.o
CC fs/efivarfs/file.o
CC [M] fs/fscache/io.o
CC fs/lockd/svclock.o
CC arch/x86/kernel/signal_64.o
CC drivers/pci/pci-stub.o
CC [M] arch/x86/kvm/mmu/spte.o
CC fs/nfs/direct.o
CC mm/mincore.o
CC drivers/acpi/osl.o
CC [M] sound/hda/intel-nhlt.o
CC [M] net/netfilter/ipvs/ip_vs_pe.o
CC [M] net/netfilter/ipvs/ip_vs_proto_tcp.o
CC net/core/filter.o
CC fs/ntfs/index.o
CC net/core/sock_diag.o
CC arch/x86/kernel/traps.o
CC net/ethtool/features.o
CC block/blk-throttle.o
CC drivers/acpi/acpica/evxfregn.o
CC kernel/trace/trace_functions.o
AR drivers/video/fbdev/built-in.a
CC [M] fs/netfs/main.o
CC fs/efivarfs/super.o
CC fs/proc/kmsg.o
CC block/mq-deadline.o
CC arch/x86/kernel/idt.o
CC kernel/trace/trace_preemptirq.o
CC [M] net/ipv4/netfilter/iptable_mangle.o
CC fs/lockd/svcshare.o
AR drivers/dma/hsu/built-in.a
CC net/netfilter/nf_log.o
CC drivers/pci/vgaarb.o
AR drivers/soc/apple/built-in.a
AR drivers/soc/aspeed/built-in.a
CC drivers/virtio/virtio.o
AR drivers/soc/bcm/bcm63xx/built-in.a
CC crypto/pcrypt.o
AR drivers/soc/bcm/built-in.a
CC [M] sound/hda/intel-sdw-acpi.o
AR drivers/soc/fsl/built-in.a
AR drivers/soc/fujitsu/built-in.a
CC [M] fs/fscache/main.o
AR drivers/soc/imx/built-in.a
AR drivers/soc/ixp4xx/built-in.a
CC arch/x86/kernel/irq.o
AR drivers/soc/loongson/built-in.a
CC drivers/acpi/acpica/exconcat.o
CC drivers/tty/vt/vt_ioctl.o
AR drivers/soc/mediatek/built-in.a
AR drivers/soc/microchip/built-in.a
AR drivers/soc/nuvoton/built-in.a
CC arch/x86/kernel/irq_64.o
AR drivers/soc/pxa/built-in.a
AR drivers/soc/amlogic/built-in.a
AR drivers/soc/qcom/built-in.a
AR drivers/soc/renesas/built-in.a
CC drivers/dma/dw/idma32.o
AR drivers/soc/rockchip/built-in.a
AR drivers/soc/sifive/built-in.a
AR drivers/soc/sunxi/built-in.a
AR drivers/soc/ti/built-in.a
AR drivers/soc/xilinx/built-in.a
AR drivers/soc/built-in.a
CC fs/proc/page.o
CC fs/ntfs/inode.o
CC drivers/virtio/virtio_ring.o
CC mm/mlock.o
CC crypto/cryptd.o
CC net/xfrm/xfrm_output.o
CC fs/efivarfs/vars.o
CC net/ethtool/privflags.o
CC lib/zstd/decompress/zstd_ddict.o
AR drivers/video/built-in.a
CC net/xfrm/xfrm_sysctl.o
CC drivers/virtio/virtio_anchor.o
CC drivers/virtio/virtio_pci_modern_dev.o
CC fs/ext4/migrate.o
CC arch/x86/kernel/dumpstack_64.o
CC arch/x86/kernel/time.o
CC drivers/acpi/acpica/exconfig.o
CC drivers/acpi/acpica/exconvrt.o
CC drivers/acpi/acpica/excreate.o
CC arch/x86/kernel/ioport.o
CC kernel/trace/trace_nop.o
LD [M] sound/hda/snd-hda-core.o
CC fs/ext4/mmp.o
CC lib/zstd/decompress/zstd_decompress.o
LD [M] sound/hda/snd-intel-dspcfg.o
CC drivers/acpi/utils.o
LD [M] sound/hda/snd-intel-sdw-acpi.o
AR sound/xen/built-in.a
AR sound/virtio/built-in.a
CC drivers/acpi/reboot.o
CC sound/sound_core.o
CC fs/ntfs/mft.o
CC [M] fs/netfs/objects.o
CC net/netfilter/nf_queue.o
CC fs/lockd/svcproc.o
CC [M] net/ipv4/netfilter/iptable_nat.o
CC drivers/dma/dw/acpi.o
CC [M] net/netfilter/ipvs/ip_vs_proto_udp.o
CC fs/btrfs/extent-tree.o
CC kernel/reboot.o
CC drivers/virtio/virtio_pci_legacy_dev.o
CC kernel/async.o
CC drivers/acpi/acpica/exdebug.o
CC arch/x86/kernel/dumpstack.o
CC block/kyber-iosched.o
CC net/core/dev_ioctl.o
CC sound/last.o
AR drivers/pci/built-in.a
CC crypto/des_generic.o
CC net/unix/af_unix.o
CC arch/x86/kernel/nmi.o
AR fs/proc/built-in.a
CC block/bfq-iosched.o
CC fs/btrfs/print-tree.o
CC drivers/tty/vt/vc_screen.o
AR fs/efivarfs/built-in.a
CC drivers/tty/vt/selection.o
CC fs/nfs/pagelist.o
CC fs/lockd/svcsubs.o
CC [M] fs/fscache/volume.o
CC fs/lockd/mon.o
CC arch/x86/kernel/ldt.o
CC drivers/tty/vt/keyboard.o
CC kernel/trace/trace_functions_graph.o
CC net/core/tso.o
CC [M] arch/x86/kvm/mmu/tdp_iter.o
CC net/xfrm/xfrm_replay.o
CC net/ethtool/rings.o
CC net/xfrm/xfrm_device.o
CC fs/ntfs/mst.o
CC drivers/tty/vt/consolemap.o
CC drivers/dma/dw/pci.o
CC crypto/aes_generic.o
LD [M] fs/netfs/netfs.o
AR sound/built-in.a
CC lib/zstd/decompress/zstd_decompress_block.o
CC net/unix/garbage.o
CC drivers/acpi/acpica/exdump.o
CC [M] fs/smbfs_common/cifs_arc4.o
CC [M] fs/smbfs_common/cifs_md4.o
CC fs/ntfs/namei.o
CC drivers/acpi/nvs.o
CC arch/x86/kernel/setup.o
CC arch/x86/kernel/x86_init.o
CC arch/x86/kernel/i8259.o
CC lib/zstd/zstd_common_module.o
CC drivers/virtio/virtio_mmio.o
CC fs/lockd/xdr.o
CC drivers/acpi/acpica/exfield.o
CC [M] net/ipv4/netfilter/ipt_REJECT.o
CC block/bfq-wf2q.o
CC mm/mmap.o
CC fs/ntfs/runlist.o
CC net/unix/sysctl_net_unix.o
CC drivers/virtio/virtio_pci_modern.o
AR drivers/dma/idxd/built-in.a
CC crypto/deflate.o
HOSTCC drivers/tty/vt/conmakehash
CC fs/ntfs/super.o
AR drivers/dma/dw/built-in.a
CC [M] net/netfilter/ipvs/ip_vs_nfct.o
AR drivers/dma/mediatek/built-in.a
AR drivers/dma/qcom/built-in.a
AR drivers/dma/ti/built-in.a
AR drivers/dma/xilinx/built-in.a
CC drivers/acpi/acpica/exfldio.o
CC [M] drivers/dma/ioat/init.o
CC [M] arch/x86/kvm/mmu/tdp_mmu.o
CC drivers/virtio/virtio_pci_common.o
CC drivers/acpi/acpica/exmisc.o
CC [M] net/netfilter/ipvs/ip_vs_rr.o
CC [M] fs/fscache/proc.o
CC [M] arch/x86/kvm/smm.o
CC drivers/dma/dmaengine.o
CC net/netfilter/nf_sockopt.o
CC [M] drivers/dma/ioat/dma.o
CC fs/ext4/move_extent.o
CC fs/lockd/clnt4xdr.o
CC drivers/tty/vt/vt.o
CC fs/lockd/xdr4.o
CC net/ethtool/channels.o
CC net/core/sock_reuseport.o
CC kernel/trace/fgraph.o
AR net/ipv6/netfilter/built-in.a
CC [M] net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
CC net/packet/af_packet.o
CC net/ipv6/af_inet6.o
CC arch/x86/kernel/irqinit.o
CC net/key/af_key.o
CC crypto/crc32c_generic.o
AR net/bridge/netfilter/built-in.a
CC drivers/virtio/virtio_pci_legacy.o
CC net/bridge/br.o
CC block/bfq-cgroup.o
CC drivers/acpi/acpica/exmutex.o
CC [M] drivers/virtio/virtio_mem.o
CC net/xfrm/xfrm_algo.o
CC drivers/acpi/acpica/exnames.o
CC net/ipv4/protocol.o
CC [M] net/ipv6/netfilter/nf_conntrack_reasm.o
LD [M] fs/fscache/fscache.o
CC drivers/tty/hvc/hvc_console.o
CC mm/mmu_gather.o
CC net/ipv4/ip_input.o
CC fs/nfs/read.o
CC fs/lockd/svc4proc.o
CC fs/nfs/symlink.o
CC net/ethtool/coalesce.o
CC crypto/crct10dif_common.o
CC net/ethtool/pause.o
CC drivers/tty/serial/8250/8250_core.o
AR drivers/tty/ipwireless/built-in.a
CC drivers/tty/tty_io.o
CC drivers/tty/serial/8250/8250_pnp.o
LD [M] net/netfilter/ipvs/ip_vs.o
CC drivers/acpi/acpica/exoparg1.o
CC drivers/tty/serial/serial_core.o
CC [M] fs/cifs/trace.o
CC fs/nfs/unlink.o
CC net/netfilter/utils.o
CC arch/x86/kernel/jump_label.o
CC arch/x86/kernel/irq_work.o
CC kernel/trace/blktrace.o
CC fs/nfs/write.o
CC fs/ntfs/sysctl.o
CC fs/ext4/namei.o
CC fs/ntfs/unistr.o
CC crypto/crct10dif_generic.o
CC fs/lockd/procfs.o
CC net/ipv4/ip_fragment.o
CC [M] drivers/dma/ioat/prep.o
CC [M] drivers/dma/ioat/dca.o
CC drivers/dma/virt-dma.o
COPY drivers/tty/vt/defkeymap.c
CC block/blk-mq-pci.o
CC net/ipv6/anycast.o
CC [M] fs/cifs/cifsfs.o
CC net/unix/diag.o
CC net/bridge/br_device.o
CC drivers/tty/serial/earlycon.o
CC fs/btrfs/root-tree.o
CC net/xfrm/xfrm_user.o
CC drivers/acpi/acpica/exoparg2.o
AR drivers/tty/hvc/built-in.a
CC drivers/tty/n_tty.o
CC drivers/tty/serial/8250/8250_port.o
CC crypto/authenc.o
CC fs/nfs/namespace.o
CC arch/x86/kernel/probe_roms.o
CC net/ipv4/ip_forward.o
CC fs/ext4/page-io.o
CC fs/ntfs/upcase.o
CC net/ethtool/eee.o
CC [M] drivers/dma/ioat/sysfs.o
AR fs/lockd/built-in.a
CC mm/mprotect.o
CC drivers/tty/serial/8250/8250_dma.o
CC kernel/trace/trace_events.o
CC block/blk-mq-virtio.o
CC drivers/tty/serial/8250/8250_dwlib.o
CC net/ethtool/tsinfo.o
LD [M] net/ipv6/netfilter/nf_defrag_ipv6.o
CC net/ipv6/ip6_output.o
CC net/ethtool/cabletest.o
CC net/ipv6/ip6_input.o
CC net/ipv6/addrconf.o
CC drivers/acpi/acpica/exoparg3.o
CC mm/mremap.o
CC [M] net/netfilter/nfnetlink.o
CC drivers/acpi/wakeup.o
AR drivers/virtio/built-in.a
CC drivers/char/hw_random/core.o
CC drivers/char/agp/backend.o
CC arch/x86/kernel/sys_ia32.o
CC drivers/char/hw_random/intel-rng.o
AR fs/ntfs/built-in.a
CC lib/zstd/common/debug.o
AR drivers/iommu/amd/built-in.a
CC lib/zstd/common/entropy_common.o
CC drivers/iommu/intel/dmar.o
AR drivers/iommu/arm/arm-smmu/built-in.a
CC net/unix/scm.o
CC kernel/trace/trace_export.o
AR drivers/iommu/arm/arm-smmu-v3/built-in.a
AR drivers/iommu/arm/built-in.a
CC drivers/char/tpm/tpm-chip.o
CC drivers/acpi/acpica/exoparg6.o
CC drivers/char/mem.o
LD [M] drivers/dma/ioat/ioatdma.o
CC crypto/authencesn.o
CC drivers/dma/acpi-dma.o
CC block/blk-mq-debugfs.o
CC block/blk-pm.o
CONMK drivers/tty/vt/consolemap_deftbl.c
CC [M] arch/x86/kvm/vmx/vmx.o
CC drivers/tty/vt/defkeymap.o
CC lib/zstd/common/error_private.o
CC drivers/tty/serial/8250/8250_pcilib.o
CC net/bridge/br_fdb.o
CC drivers/acpi/sleep.o
CC net/ethtool/tunnels.o
CC net/core/fib_notifier.o
CC lib/zstd/common/fse_decompress.o
CC arch/x86/kernel/signal_32.o
CC [M] fs/fuse/dev.o
CC fs/btrfs/dir-item.o
CC drivers/tty/vt/consolemap_deftbl.o
CC [M] fs/fuse/dir.o
CC net/core/xdp.o
AR drivers/tty/vt/built-in.a
CC net/ethtool/fec.o
AR net/key/built-in.a
CC drivers/tty/tty_ioctl.o
CC net/core/flow_offload.o
CC drivers/acpi/acpica/exprep.o
CC drivers/char/agp/generic.o
CC drivers/iommu/intel/iommu.o
CC net/ipv4/ip_options.o
CC net/ipv4/ip_output.o
AR drivers/char/hw_random/built-in.a
CC drivers/char/agp/isoch.o
CC net/ethtool/eeprom.o
CC [M] net/netfilter/nf_conntrack_core.o
CC [M] net/sunrpc/auth_gss/auth_gss.o
CC [M] net/sunrpc/auth_gss/gss_generic_token.o
CC net/8021q/vlan_core.o
CC drivers/char/tpm/tpm-dev-common.o
AR drivers/dma/built-in.a
CC [M] net/sunrpc/auth_gss/gss_mech_switch.o
CC [M] fs/fuse/file.o
CC [M] net/sunrpc/auth_gss/svcauth_gss.o
CC [M] net/sunrpc/auth_gss/gss_rpc_upcall.o
AR net/unix/built-in.a
CC drivers/tty/serial/8250/8250_pci.o
CC mm/msync.o
CC drivers/acpi/acpica/exregion.o
CC block/holder.o
CC crypto/lzo.o
CC net/core/gro.o
CC net/ipv4/ip_sockglue.o
CC net/dcb/dcbnl.o
CC arch/x86/kernel/sys_x86_64.o
CC lib/zstd/common/zstd_common.o
CC net/dcb/dcbevent.o
AR lib/zstd/built-in.a
CC fs/nfs/mount_clnt.o
CC lib/earlycpio.o
CC [M] fs/cifs/cifs_debug.o
CC drivers/tty/tty_ldisc.o
CC net/packet/diag.o
CC fs/nfs/nfstrace.o
CC arch/x86/kernel/espfix_64.o
CC lib/extable.o
CC mm/page_vma_mapped.o
CC [M] fs/fuse/inode.o
CC drivers/acpi/acpica/exresnte.o
CC [M] fs/fuse/control.o
CC fs/btrfs/file-item.o
CC drivers/char/tpm/tpm-dev.o
CC fs/btrfs/inode-item.o
AR block/built-in.a
AR net/xfrm/built-in.a
CC net/ethtool/stats.o
CC net/l3mdev/l3mdev.o
CC crypto/lzo-rle.o
CC net/ipv6/addrlabel.o
CC drivers/char/tpm/tpm-interface.o
CC fs/ext4/readpage.o
CC drivers/char/agp/intel-agp.o
CC fs/btrfs/disk-io.o
CC lib/flex_proportions.o
CC kernel/trace/trace_event_perf.o
CC drivers/tty/serial/8250/8250_exar.o
CC drivers/tty/serial/serial_mctrl_gpio.o
CC [M] fs/fuse/xattr.o
CC drivers/acpi/acpica/exresolv.o
CC drivers/char/agp/intel-gtt.o
CC drivers/char/random.o
CC [M] net/bluetooth/af_bluetooth.o
CC [M] net/bluetooth/hci_core.o
CC [M] net/sunrpc/auth_gss/gss_rpc_xdr.o
CC drivers/tty/tty_buffer.o
CC arch/x86/kernel/ksysfs.o
CC [M] net/8021q/vlan.o
CC fs/btrfs/transaction.o
CC kernel/trace/trace_events_filter.o
CC lib/idr.o
CC drivers/char/tpm/tpm1-cmd.o
CC crypto/lz4.o
CC crypto/lz4hc.o
AR net/packet/built-in.a
CC drivers/tty/serial/8250/8250_early.o
CC crypto/xxhash_generic.o
CC mm/pagewalk.o
CC [M] net/dns_resolver/dns_key.o
CC drivers/acpi/acpica/exresop.o
CC net/bridge/br_forward.o
CC [M] net/dns_resolver/dns_query.o
AR net/l3mdev/built-in.a
CC arch/x86/kernel/bootflag.o
CC [M] fs/fuse/acl.o
CC [M] fs/cifs/connect.o
CC net/bridge/br_if.o
CC fs/ext4/resize.o
CC [M] net/8021q/vlan_dev.o
CC fs/btrfs/inode.o
CC drivers/char/tpm/tpm2-cmd.o
CC net/core/netdev-genl.o
CC crypto/rng.o
CC arch/x86/kernel/e820.o
CC kernel/trace/trace_events_trigger.o
CC [M] net/bluetooth/hci_conn.o
CC net/ethtool/phc_vclocks.o
CC lib/irq_regs.o
CC [M] fs/cifs/dir.o
CC net/ipv6/route.o
CC drivers/acpi/acpica/exserial.o
CC drivers/tty/tty_port.o
CC [M] net/sunrpc/auth_gss/trace.o
CC drivers/tty/serial/8250/8250_dw.o
AR drivers/char/agp/built-in.a
CC lib/is_single_threaded.o
CC [M] fs/fuse/readdir.o
CC fs/btrfs/file.o
AR net/dcb/built-in.a
CC fs/btrfs/defrag.o
CC fs/btrfs/extent_map.o
CC drivers/tty/tty_mutex.o
CC [M] fs/fuse/ioctl.o
CC [M] fs/cifs/file.o
CC [M] net/bluetooth/hci_event.o
CC net/devres.o
CC net/ipv4/inet_hashtables.o
CC net/core/netdev-genl-gen.o
CC drivers/char/misc.o
LD [M] net/dns_resolver/dns_resolver.o
CC net/ethtool/mm.o
CC fs/btrfs/sysfs.o
CC mm/pgtable-generic.o
CC [M] fs/overlayfs/super.o
CC [M] net/netfilter/nf_conntrack_standalone.o
CC [M] fs/overlayfs/namei.o
CC drivers/acpi/acpica/exstore.o
CC [M] fs/overlayfs/util.o
CC lib/klist.o
CC [M] net/netfilter/nf_conntrack_expect.o
CC crypto/drbg.o
CC drivers/iommu/intel/pasid.o
CC crypto/jitterentropy.o
CC drivers/tty/tty_ldsem.o
CC net/ipv4/inet_timewait_sock.o
CC kernel/trace/trace_eprobe.o
CC lib/kobject.o
CC drivers/tty/serial/8250/8250_lpss.o
CC drivers/char/tpm/tpmrm-dev.o
CC [M] net/sunrpc/auth_gss/gss_krb5_mech.o
CC [M] net/bluetooth/mgmt.o
CC drivers/acpi/acpica/exstoren.o
CC [M] net/8021q/vlan_netlink.o
CC net/core/net-sysfs.o
CC drivers/char/virtio_console.o
CC [M] net/8021q/vlanproc.o
CC fs/open.o
CC net/ipv4/inet_connection_sock.o
CC arch/x86/kernel/pci-dma.o
CC net/bridge/br_input.o
LD [M] fs/fuse/fuse.o
CC net/ipv4/tcp.o
CC mm/rmap.o
CC fs/read_write.o
CC net/ethtool/module.o
CC drivers/acpi/acpica/exstorob.o
CC net/ipv6/ip6_fib.o
CC [M] fs/overlayfs/inode.o
CC drivers/char/tpm/tpm2-space.o
CC drivers/tty/serial/8250/8250_mid.o
CC [M] fs/overlayfs/file.o
CC drivers/tty/tty_baudrate.o
CC lib/kobject_uevent.o
CC fs/btrfs/accessors.o
CC fs/ext4/super.o
CC arch/x86/kernel/quirks.o
CC drivers/iommu/intel/trace.o
CC lib/logic_pio.o
CC [M] net/sunrpc/auth_gss/gss_krb5_seal.o
CC drivers/acpi/acpica/exsystem.o
CC fs/file_table.o
CC drivers/acpi/acpica/extrace.o
CC kernel/range.o
CC lib/maple_tree.o
AR net/8021q/built-in.a
LD [M] net/8021q/8021q.o
CC net/socket.o
CC net/ipv4/tcp_input.o
CC [M] net/netfilter/nf_conntrack_helper.o
CC [M] fs/overlayfs/dir.o
CC crypto/jitterentropy-kcapi.o
CC lib/memcat_p.o
CC [M] net/sunrpc/auth_gss/gss_krb5_unseal.o
CC drivers/tty/serial/8250/8250_pericom.o
CC net/bridge/br_ioctl.o
CC kernel/trace/trace_kprobe.o
CC drivers/acpi/acpica/exutils.o
AR drivers/gpu/host1x/built-in.a
CC net/ethtool/pse-pd.o
AR drivers/gpu/drm/tests/built-in.a
CC [M] drivers/gpu/drm/tests/drm_kunit_helpers.o
CC drivers/connector/cn_queue.o
CC drivers/char/tpm/tpm-sysfs.o
CC lib/nmi_backtrace.o
CC drivers/char/tpm/eventlog/common.o
CC drivers/connector/connector.o
CC mm/vmalloc.o
CC kernel/smpboot.o
AR drivers/gpu/vga/built-in.a
CC drivers/iommu/intel/cap_audit.o
CC arch/x86/kernel/topology.o
CC crypto/ghash-generic.o
CC drivers/iommu/intel/irq_remapping.o
CC drivers/iommu/intel/perfmon.o
CC drivers/char/hpet.o
CC fs/super.o
CC drivers/char/tpm/eventlog/tpm1.o
CC lib/plist.o
CC [M] net/sunrpc/auth_gss/gss_krb5_seqnum.o
CC drivers/connector/cn_proc.o
CC fs/ext4/symlink.o
CC drivers/acpi/acpica/hwacpi.o
CC fs/ext4/sysfs.o
CC net/core/net-procfs.o
CC [M] drivers/gpu/drm/tests/drm_buddy_test.o
CC net/ipv6/ipv6_sockglue.o
CC fs/nfs/export.o
AR drivers/tty/serial/8250/built-in.a
AR drivers/tty/serial/built-in.a
CC drivers/tty/tty_jobctrl.o
CC fs/btrfs/xattr.o
CC arch/x86/kernel/kdebugfs.o
CC crypto/af_alg.o
CC drivers/acpi/acpica/hwesleep.o
CC [M] drivers/gpu/drm/tests/drm_cmdline_parser_test.o
CC net/sunrpc/clnt.o
CC drivers/char/nvram.o
CC [M] fs/overlayfs/readdir.o
CC net/ipv4/tcp_output.o
CC [M] net/netfilter/nf_conntrack_proto.o
CC crypto/algif_hash.o
CC net/ethtool/plca.o
CC fs/nfs/sysfs.o
CC [M] fs/cifs/inode.o
CC drivers/char/tpm/eventlog/tpm2.o
CC arch/x86/kernel/alternative.o
CC [M] net/sunrpc/auth_gss/gss_krb5_wrap.o
CC drivers/char/tpm/tpm_ppi.o
CC net/bridge/br_stp.o
CC drivers/char/tpm/eventlog/acpi.o
CC [M] arch/x86/kvm/kvm-asm-offsets.s
CC drivers/acpi/acpica/hwgpe.o
CC drivers/acpi/acpica/hwregs.o
CC mm/page_alloc.o
CC drivers/acpi/acpica/hwsleep.o
CC drivers/char/tpm/eventlog/efi.o
CC [M] net/netfilter/nf_conntrack_proto_generic.o
CC net/ipv6/ndisc.o
CC [M] net/netfilter/nf_conntrack_proto_tcp.o
CC drivers/tty/n_null.o
CC net/core/netpoll.o
CC net/core/fib_rules.o
AR drivers/connector/built-in.a
CC fs/ext4/xattr.o
AR drivers/iommu/intel/built-in.a
CC [M] net/bluetooth/hci_sock.o
CC fs/char_dev.o
AR drivers/iommu/iommufd/built-in.a
CC fs/btrfs/ordered-data.o
CC drivers/iommu/iommu.o
CC drivers/char/tpm/tpm_crb.o
CC net/ipv6/udp.o
CC fs/stat.o
CC drivers/acpi/acpica/hwvalid.o
CC fs/exec.o
CC [M] net/sunrpc/auth_gss/gss_krb5_crypto.o
CC [M] net/sunrpc/auth_gss/gss_krb5_keys.o
CC [M] arch/x86/kvm/vmx/pmu_intel.o
LD [M] net/sunrpc/auth_gss/auth_rpcgss.o
CC kernel/trace/error_report-traces.o
CC net/sunrpc/xprt.o
CC fs/nfs/fs_context.o
AR net/ethtool/built-in.a
CC [M] drivers/gpu/drm/tests/drm_connector_test.o
CC fs/pipe.o
CC [M] drivers/gpu/drm/tests/drm_damage_helper_test.o
CC drivers/iommu/iommu-traces.o
CC drivers/tty/pty.o
CC [M] fs/overlayfs/copy_up.o
CC drivers/acpi/acpica/hwxface.o
CC net/compat.o
CC drivers/acpi/acpica/hwxfsleep.o
CC [M] net/netfilter/nf_conntrack_proto_udp.o
CC net/bridge/br_stp_bpdu.o
CC crypto/algif_skcipher.o
CC fs/namei.o
CC arch/x86/kernel/i8253.o
CC [M] drivers/gpu/drm/tests/drm_dp_mst_helper_test.o
CC mm/init-mm.o
AR drivers/char/tpm/built-in.a
AR drivers/char/built-in.a
CC net/ipv4/tcp_timer.o
CC [M] fs/overlayfs/export.o
CC net/ipv4/tcp_ipv4.o
CC kernel/trace/power-traces.o
CC kernel/trace/rpm-traces.o
CC net/bridge/br_stp_if.o
CC drivers/acpi/acpica/hwpci.o
CC fs/fcntl.o
CC drivers/iommu/iommu-sysfs.o
CC arch/x86/kernel/hw_breakpoint.o
CC drivers/tty/sysrq.o
LD [M] net/sunrpc/auth_gss/rpcsec_gss_krb5.o
CC net/sunrpc/socklib.o
CC [M] drivers/gpu/drm/tests/drm_format_helper_test.o
CC [M] net/bluetooth/hci_sysfs.o
CC kernel/trace/trace_dynevent.o
CC [M] net/netfilter/nf_conntrack_proto_icmp.o
CC net/ipv4/tcp_minisocks.o
CC drivers/acpi/acpica/nsaccess.o
CC crypto/xor.o
CC fs/ioctl.o
CC [M] arch/x86/kvm/vmx/vmcs12.o
CC net/core/net-traces.o
CC net/core/selftests.o
CC fs/readdir.o
CC [M] drivers/gpu/drm/tests/drm_format_test.o
CC fs/select.o
CC [M] drivers/gpu/drm/tests/drm_framebuffer_test.o
LD [M] fs/overlayfs/overlay.o
CC net/sunrpc/xprtsock.o
CC [M] arch/x86/kvm/vmx/hyperv.o
CC net/core/ptp_classifier.o
CC fs/ext4/xattr_hurd.o
CC arch/x86/kernel/tsc.o
CC lib/radix-tree.o
CC net/ipv4/tcp_cong.o
CC crypto/hash_info.o
CC drivers/iommu/dma-iommu.o
CC crypto/simd.o
CC drivers/acpi/device_sysfs.o
CC drivers/acpi/acpica/nsalloc.o
CC arch/x86/kernel/tsc_msr.o
CC drivers/acpi/acpica/nsarguments.o
CC [M] fs/cifs/link.o
CC lib/ratelimit.o
CC fs/nfs/sysctl.o
CC fs/btrfs/extent_io.o
CC net/bridge/br_stp_timer.o
CC fs/dcache.o
CC drivers/acpi/acpica/nsconvert.o
CC net/sunrpc/sched.o
CC fs/nfs/nfs2super.o
CC [M] drivers/gpu/drm/tests/drm_managed_test.o
CC lib/rbtree.o
AR drivers/tty/built-in.a
CC [M] fs/cifs/misc.o
CC drivers/acpi/device_pm.o
CC net/sunrpc/auth.o
CC lib/seq_buf.o
CC fs/ext4/xattr_trusted.o
CC fs/btrfs/volumes.o
CC fs/ext4/xattr_user.o
CC net/ipv6/udplite.o
CC kernel/trace/trace_probe.o
CC fs/ext4/fast_commit.o
CC drivers/base/power/sysfs.o
CC [M] net/netfilter/nf_conntrack_extend.o
CC [M] crypto/md4.o
CC drivers/base/firmware_loader/builtin/main.o
CC drivers/base/firmware_loader/main.o
CC fs/inode.o
CC [M] fs/cifs/netmisc.o
CC drivers/block/loop.o
CC drivers/block/virtio_blk.o
CC [M] drivers/block/nbd.o
CC drivers/acpi/acpica/nsdump.o
CC [M] crypto/ccm.o
CC [M] drivers/gpu/drm/tests/drm_mm_test.o
CC lib/show_mem.o
CC arch/x86/kernel/io_delay.o
CC [M] arch/x86/kvm/vmx/nested.o
CC [M] net/netfilter/nf_conntrack_acct.o
CC lib/siphash.o
AR drivers/base/firmware_loader/builtin/built-in.a
CC drivers/acpi/proc.o
CC net/ipv4/tcp_metrics.o
CC [M] crypto/arc4.o
CC net/ipv6/raw.o
CC fs/nfs/proc.o
CC [M] net/bluetooth/l2cap_core.o
CC net/ipv6/icmp.o
CC drivers/base/power/generic_ops.o
CC [M] fs/cifs/smbencrypt.o
CC [M] fs/cifs/transport.o
CC drivers/acpi/acpica/nseval.o
CC arch/x86/kernel/rtc.o
CC net/bridge/br_netlink.o
CC [M] drivers/gpu/drm/tests/drm_modes_test.o
CC [M] crypto/ecc.o
CC drivers/iommu/ioasid.o
CC fs/btrfs/async-thread.o
CC net/core/netprio_cgroup.o
CC [M] crypto/essiv.o
CC lib/string.o
CC drivers/acpi/acpica/nsinit.o
CC [M] fs/cifs/cached_dir.o
CC [M] crypto/ecdh.o
CC net/ipv6/mcast.o
CC net/sunrpc/auth_null.o
CC net/bridge/br_netlink_tunnel.o
AR drivers/base/firmware_loader/built-in.a
CC drivers/base/power/common.o
CC net/bridge/br_arp_nd_proxy.o
CC net/bridge/br_sysfs_if.o
CC net/ipv4/tcp_fastopen.o
CC [M] crypto/ecdh_helper.o
CC drivers/iommu/iova.o
CC [M] net/netfilter/nf_conntrack_seqadj.o
CC kernel/trace/trace_uprobe.o
CC arch/x86/kernel/resource.o
CC drivers/acpi/acpica/nsload.o
CC [M] fs/cifs/cifs_unicode.o
CC [M] drivers/gpu/drm/tests/drm_plane_helper_test.o
CC drivers/iommu/irq_remapping.o
CC lib/timerqueue.o
CC fs/attr.o
AS arch/x86/kernel/irqflags.o
CC net/bridge/br_sysfs_br.o
CC arch/x86/kernel/static_call.o
CC arch/x86/kernel/process.o
CC lib/vsprintf.o
CC drivers/base/power/qos.o
CC net/bridge/br_nf_core.o
CC net/ipv4/tcp_rate.o
CC fs/ext4/orphan.o
CC net/ipv4/tcp_recovery.o
CC fs/nfs/nfs2xdr.o
CC drivers/acpi/acpica/nsnames.o
CC drivers/acpi/bus.o
CC net/core/dst_cache.o
AR drivers/block/built-in.a
CC net/bridge/br_multicast.o
CC net/sunrpc/auth_unix.o
CC fs/bad_inode.o
CC net/ipv4/tcp_ulp.o
CC drivers/acpi/acpica/nsobject.o
CC lib/win_minmax.o
CC arch/x86/kernel/ptrace.o
CC drivers/acpi/glue.o
CC mm/memblock.o
CC [M] drivers/gpu/drm/tests/drm_probe_helper_test.o
AR drivers/iommu/built-in.a
CC [M] arch/x86/kvm/vmx/posted_intr.o
CC net/sysctl_net.o
CC [M] drivers/gpu/drm/tests/drm_rect_test.o
CC fs/btrfs/ioctl.o
CC net/ipv4/tcp_offload.o
CC fs/file.o
CC drivers/acpi/acpica/nsparse.o
CC drivers/acpi/scan.o
CC fs/btrfs/locking.o
CC net/ipv6/reassembly.o
CC arch/x86/kernel/tls.o
CC arch/x86/kernel/step.o
CC net/ipv4/tcp_plb.o
CC fs/filesystems.o
CC [M] fs/cifs/nterr.o
LD [M] crypto/ecdh_generic.o
CC [M] net/netfilter/nf_conntrack_proto_icmpv6.o
AR crypto/built-in.a
CC [M] net/netfilter/nf_conntrack_proto_dccp.o
CC fs/btrfs/orphan.o
CC mm/memory_hotplug.o
CC drivers/base/power/runtime.o
CC net/ipv4/datagram.o
CC net/ipv6/tcp_ipv6.o
CC drivers/acpi/acpica/nspredef.o
LD [M] arch/x86/kvm/kvm.o
CC fs/namespace.o
CC net/bridge/br_mdb.o
CC fs/seq_file.o
CC kernel/ucount.o
CC drivers/acpi/resource.o
UPD arch/x86/kvm/kvm-asm-offsets.h
CC [M] fs/cifs/cifsencrypt.o
CC net/ipv4/raw.o
CC drivers/acpi/acpica/nsprepkg.o
CC net/ipv4/udp.o
CC net/core/gro_cells.o
CC drivers/acpi/acpi_processor.o
AR drivers/gpu/drm/arm/built-in.a
AR drivers/gpu/drm/display/built-in.a
CC [M] drivers/gpu/drm/display/drm_display_helper_mod.o
AS [M] arch/x86/kvm/vmx/vmenter.o
CC drivers/base/regmap/regmap.o
CC net/bridge/br_multicast_eht.o
CC arch/x86/kernel/i8237.o
CC arch/x86/kernel/stacktrace.o
CC net/bridge/br_vlan.o
CC net/core/failover.o
CC kernel/trace/rethook.o
CC drivers/acpi/acpica/nsrepair.o
CC net/ipv4/udplite.o
AR drivers/misc/eeprom/built-in.a
AR drivers/misc/cb710/built-in.a
AR drivers/misc/ti-st/built-in.a
AR drivers/misc/lis3lv02d/built-in.a
AR drivers/misc/cardreader/built-in.a
CC [M] drivers/misc/mei/hdcp/mei_hdcp.o
CC fs/nfs/nfs3super.o
CC [M] drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
CC drivers/acpi/processor_core.o
CC net/bridge/br_vlan_tunnel.o
CC mm/madvise.o
CC [M] drivers/misc/mei/pxp/mei_pxp.o
AR drivers/gpu/drm/rcar-du/built-in.a
AR drivers/gpu/drm/omapdrm/built-in.a
CC mm/page_io.o
CC fs/btrfs/export.o
CC drivers/acpi/acpica/nsrepair2.o
CC net/sunrpc/svc.o
CC kernel/regset.o
AR drivers/misc/built-in.a
CC fs/btrfs/tree-log.o
CC drivers/mfd/mfd-core.o
CC [M] net/netfilter/nf_conntrack_proto_sctp.o
CC drivers/acpi/processor_pdc.o
CC arch/x86/kernel/reboot.o
CC kernel/kmod.o
CC drivers/base/power/wakeirq.o
CC arch/x86/kernel/msr.o
CC fs/btrfs/free-space-cache.o
CC fs/xattr.o
CC fs/libfs.o
CC fs/nfs/nfs3client.o
CC drivers/mfd/intel-lpss.o
CC drivers/base/power/main.o
AR kernel/trace/built-in.a
CC [M] drivers/gpu/drm/display/drm_dp_helper.o
CC drivers/acpi/ec.o
CC net/ipv6/ping.o
AR net/core/built-in.a
CC net/bridge/br_vlan_options.o
CC lib/xarray.o
CC net/ipv6/exthdrs.o
CC [M] drivers/misc/mei/init.o
CC drivers/acpi/acpica/nssearch.o
CC drivers/acpi/acpica/nsutils.o
AR drivers/nfc/built-in.a
AR drivers/dax/hmem/built-in.a
CC drivers/dax/super.o
CC drivers/acpi/dock.o
CC drivers/dax/bus.o
AR fs/ext4/built-in.a
CC [M] drivers/misc/mei/hbm.o
CC fs/nfs/nfs3proc.o
CC drivers/mfd/intel-lpss-pci.o
AR drivers/gpu/drm/tilcdc/built-in.a
CC [M] net/bluetooth/l2cap_sock.o
CC arch/x86/kernel/cpuid.o
CC [M] fs/cifs/readdir.o
CC net/ipv4/udp_offload.o
CC kernel/groups.o
CC net/ipv4/arp.o
CC net/ipv4/icmp.o
CC drivers/mfd/intel-lpss-acpi.o
AR drivers/gpu/drm/imx/built-in.a
CC drivers/acpi/acpica/nswalk.o
AR drivers/gpu/drm/i2c/built-in.a
AR drivers/gpu/drm/panel/built-in.a
AR drivers/gpu/drm/bridge/analogix/built-in.a
AR drivers/gpu/drm/bridge/cadence/built-in.a
AR drivers/gpu/drm/bridge/imx/built-in.a
AR drivers/gpu/drm/bridge/synopsys/built-in.a
AR drivers/gpu/drm/bridge/built-in.a
CC arch/x86/kernel/early-quirks.o
CC fs/btrfs/zlib.o
CC net/ipv4/devinet.o
CC kernel/kcmp.o
CC drivers/acpi/acpica/nsxfeval.o
CC net/bridge/br_mst.o
CC lib/lockref.o
CC lib/bcd.o
CC drivers/dma-buf/dma-buf.o
CC [M] net/netfilter/nf_conntrack_netlink.o
CC drivers/dma-buf/dma-fence.o
CC fs/btrfs/lzo.o
CC fs/btrfs/zstd.o
CC mm/swap_state.o
AR drivers/cxl/core/built-in.a
AR drivers/cxl/built-in.a
AR drivers/macintosh/built-in.a
CC mm/swapfile.o
CC drivers/acpi/pci_root.o
CC drivers/acpi/pci_link.o
CC mm/swap_slots.o
CC drivers/base/power/wakeup.o
CC fs/fs-writeback.o
CC drivers/mfd/intel_soc_pmic_crc.o
CC fs/pnode.o
CC kernel/freezer.o
CC drivers/acpi/acpica/nsxfname.o
CC [M] drivers/misc/mei/interrupt.o
CC [M] drivers/misc/mei/client.o
CC arch/x86/kernel/smp.o
AR drivers/dax/built-in.a
CC net/ipv4/af_inet.o
CC [M] drivers/gpu/drm/display/drm_dp_mst_topology.o
CC lib/sort.o
CC drivers/dma-buf/dma-fence-array.o
CC net/ipv6/datagram.o
CC [M] fs/cifs/ioctl.o
CC [M] net/netfilter/nf_nat_core.o
AR drivers/gpu/drm/hisilicon/built-in.a
CC lib/parser.o
CC fs/nfs/nfs3xdr.o
CC mm/dmapool.o
LD [M] arch/x86/kvm/kvm-intel.o
CC [M] drivers/gpu/drm/display/drm_dsc_helper.o
CC [M] drivers/gpu/drm/display/drm_hdcp_helper.o
CC net/ipv6/ip6_flowlabel.o
CC drivers/base/power/wakeup_stats.o
AR drivers/gpu/drm/mxsfb/built-in.a
CC drivers/acpi/acpica/nsxfobj.o
CC [M] net/netfilter/nf_nat_proto.o
CC [M] drivers/mfd/lpc_sch.o
CC net/sunrpc/svcsock.o
CC [M] fs/cifs/sess.o
CC fs/splice.o
CC [M] fs/cifs/export.o
CC drivers/dma-buf/dma-fence-chain.o
CC drivers/dma-buf/dma-fence-unwrap.o
CC [M] fs/cifs/unc.o
CC drivers/base/regmap/regcache.o
CC [M] fs/cifs/winucase.o
CC [M] net/netfilter/nf_nat_helper.o
CC fs/sync.o
CC kernel/stacktrace.o
CC lib/debug_locks.o
CC net/ipv4/igmp.o
CC net/sunrpc/svcauth.o
CC arch/x86/kernel/smpboot.o
CC drivers/acpi/pci_irq.o
CC drivers/base/regmap/regcache-rbtree.o
CC [M] net/bluetooth/smp.o
CC [M] drivers/misc/mei/main.o
CC drivers/acpi/acpica/psargs.o
CC lib/random32.o
CC [M] drivers/misc/mei/dma-ring.o
CC fs/btrfs/compression.o
CC [M] net/bridge/br_netfilter_hooks.o
CC fs/btrfs/delayed-ref.o
CC [M] fs/cifs/smb2ops.o
CC drivers/base/power/domain.o
CC net/ipv6/inet6_connection_sock.o
CC net/sunrpc/svcauth_unix.o
CC drivers/acpi/acpi_lpss.o
CC net/ipv4/fib_frontend.o
CC [M] drivers/misc/mei/bus.o
CC drivers/acpi/acpi_apd.o
CC [M] drivers/mfd/lpc_ich.o
AR drivers/base/test/built-in.a
CC drivers/dma-buf/dma-resv.o
CC net/sunrpc/addr.o
CC lib/bust_spinlocks.o
CC kernel/dma.o
CC fs/btrfs/relocation.o
CC drivers/acpi/acpica/psloop.o
CC fs/utimes.o
CC [M] fs/cifs/smb2maperror.o
CC drivers/base/regmap/regcache-flat.o
CC drivers/dma-buf/sync_file.o
CC [M] drivers/misc/mei/bus-fixup.o
CC [M] fs/cifs/smb2transport.o
CC net/ipv4/fib_semantics.o
CC drivers/acpi/acpi_platform.o
CC [M] net/netfilter/nf_nat_redirect.o
CC fs/btrfs/delayed-inode.o
CC kernel/smp.o
CC [M] fs/cifs/smb2misc.o
CC [M] net/netfilter/nf_nat_masquerade.o
CC lib/kasprintf.o
CC [M] net/netfilter/x_tables.o
CC net/ipv6/udp_offload.o
CC drivers/acpi/acpi_pnp.o
CC [M] fs/cifs/smb2pdu.o
CC drivers/acpi/acpica/psobject.o
AR drivers/mfd/built-in.a
CC drivers/base/regmap/regmap-debugfs.o
AR drivers/gpu/drm/tiny/built-in.a
CC drivers/scsi/scsi.o
CC drivers/base/regmap/regmap-i2c.o
CC drivers/scsi/hosts.o
CC arch/x86/kernel/tsc_sync.o
CC [M] net/netfilter/xt_tcpudp.o
CC [M] drivers/misc/mei/debugfs.o
CC net/ipv6/seg6.o
CC [M] drivers/misc/mei/mei-trace.o
CC drivers/acpi/power.o
AR fs/nfs/built-in.a
CC fs/d_path.o
CC fs/stack.o
CC net/ipv4/fib_trie.o
CC lib/bitmap.o
CC net/ipv4/fib_notifier.o
CC arch/x86/kernel/setup_percpu.o
CC mm/hugetlb.o
CC drivers/dma-buf/sw_sync.o
CC [M] net/netfilter/xt_mark.o
CC drivers/acpi/event.o
CC drivers/acpi/evged.o
CC drivers/acpi/sysfs.o
CC [M] drivers/gpu/drm/display/drm_hdmi_helper.o
CC drivers/acpi/acpica/psopcode.o
CC fs/btrfs/scrub.o
CC kernel/uid16.o
CC drivers/base/power/domain_governor.o
CC drivers/base/power/clock_ops.o
CC fs/fs_struct.o
CC lib/scatterlist.o
CC fs/statfs.o
CC net/sunrpc/rpcb_clnt.o
CC mm/hugetlb_vmemmap.o
CC mm/sparse.o
AR drivers/gpu/drm/xlnx/built-in.a
AR drivers/gpu/drm/gud/built-in.a
CC drivers/base/regmap/regmap-irq.o
CC fs/btrfs/backref.o
CC net/sunrpc/timer.o
CC arch/x86/kernel/ftrace.o
CC [M] net/netfilter/xt_nat.o
CC drivers/acpi/acpica/psopinfo.o
CC drivers/acpi/acpica/psparse.o
CC drivers/acpi/acpica/psscope.o
CC drivers/base/component.o
CC [M] drivers/misc/mei/pci-me.o
CC mm/sparse-vmemmap.o
CC [M] net/bridge/br_netfilter_ipv6.o
CC [M] net/netfilter/xt_REDIRECT.o
CC drivers/acpi/property.o
CC [M] drivers/gpu/drm/display/drm_scdc_helper.o
CC [M] fs/cifs/smb2inode.o
CC drivers/base/core.o
CC fs/btrfs/ulist.o
CC drivers/dma-buf/sync_debug.o
CC [M] drivers/gpu/drm/display/drm_dp_aux_dev.o
CC net/ipv4/inet_fragment.o
CC net/ipv6/fib6_notifier.o
CC drivers/acpi/acpi_cmos_rtc.o
CC fs/fs_pin.o
CC fs/btrfs/qgroup.o
CC fs/nsfs.o
CC drivers/scsi/scsi_ioctl.o
CC net/ipv4/ping.o
AR drivers/base/power/built-in.a
CC mm/mmu_notifier.o
CC drivers/base/bus.o
CC mm/ksm.o
CC drivers/scsi/scsicam.o
CC drivers/acpi/acpica/pstree.o
CC [M] net/bluetooth/lib.o
CC drivers/acpi/x86/apple.o
CC drivers/nvme/host/core.o
CC drivers/ata/libata-core.o
CC kernel/kallsyms.o
CC lib/list_sort.o
CC drivers/ata/libata-scsi.o
AS arch/x86/kernel/ftrace_64.o
CC lib/uuid.o
CC [M] drivers/dma-buf/selftest.o
CC [M] drivers/misc/mei/hw-me.o
CC arch/x86/kernel/trace_clock.o
CC drivers/ata/libata-eh.o
CC kernel/acct.o
CC mm/slub.o
CC drivers/nvme/host/ioctl.o
CC [M] fs/cifs/smb2file.o
AR drivers/nvme/target/built-in.a
CC [M] fs/cifs/cifsacl.o
CC drivers/acpi/acpica/psutils.o
CC arch/x86/kernel/trace.o
AR drivers/gpu/drm/solomon/built-in.a
CC kernel/crash_core.o
CC [M] drivers/dma-buf/st-dma-fence.o
CC [M] drivers/gpu/drm/ttm/ttm_tt.o
CC drivers/base/dd.o
CC [M] drivers/gpu/drm/scheduler/sched_main.o
CC lib/iov_iter.o
CC [M] drivers/gpu/drm/scheduler/sched_fence.o
CC fs/btrfs/send.o
CC drivers/scsi/scsi_error.o
AR drivers/base/regmap/built-in.a
CC drivers/scsi/scsi_lib.o
LD [M] drivers/gpu/drm/display/drm_display_helper.o
CC net/ipv6/rpl.o
CC [M] drivers/gpu/drm/scheduler/sched_entity.o
CC drivers/acpi/x86/utils.o
CC drivers/base/syscore.o
CC net/ipv4/ip_tunnel_core.o
CC drivers/scsi/scsi_lib_dma.o
CC mm/migrate.o
CC [M] net/netfilter/xt_MASQUERADE.o
CC drivers/acpi/x86/s2idle.o
CC drivers/acpi/acpica/pswalk.o
CC [M] net/bluetooth/ecdh_helper.o
AR net/bridge/built-in.a
CC arch/x86/kernel/rethook.o
LD [M] net/bridge/br_netfilter.o
CC net/sunrpc/xdr.o
CC net/sunrpc/sunrpc_syms.o
CC net/sunrpc/cache.o
CC kernel/compat.o
CC [M] drivers/dma-buf/st-dma-fence-chain.o
CC drivers/acpi/acpica/psxface.o
CC [M] fs/cifs/fs_context.o
CC [M] fs/cifs/dns_resolve.o
CC drivers/acpi/acpica/rsaddr.o
CC [M] drivers/gpu/drm/ttm/ttm_bo.o
CC net/ipv4/gre_offload.o
CC mm/migrate_device.o
CC net/ipv4/metrics.o
CC net/ipv4/netlink.o
CC [M] net/bluetooth/hci_request.o
CC [M] drivers/misc/mei/gsc-me.o
CC arch/x86/kernel/crash_core_64.o
CC drivers/ata/libata-transport.o
ASN.1 fs/cifs/cifs_spnego_negtokeninit.asn1.[ch]
LD [M] drivers/misc/mei/mei.o
CC [M] drivers/gpu/drm/ttm/ttm_bo_util.o
CC net/ipv6/ioam6.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_drv.o
CC net/ipv6/sysctl_net_ipv6.o
CC [M] fs/cifs/smb1ops.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o
CC drivers/acpi/acpica/rscalc.o
CC [M] fs/cifs/cifssmb.o
CC drivers/nvme/host/trace.o
LD [M] drivers/gpu/drm/scheduler/gpu-sched.o
CC [M] net/netfilter/xt_addrtype.o
CC fs/fs_types.o
CC kernel/utsname.o
CC [M] drivers/gpu/drm/i915/i915_driver.o
CC [M] drivers/dma-buf/st-dma-fence-unwrap.o
CC arch/x86/kernel/module.o
CC drivers/ata/libata-trace.o
CC drivers/base/driver.o
CC drivers/scsi/scsi_scan.o
CC drivers/base/class.o
LD [M] drivers/misc/mei/mei-me.o
CC kernel/user_namespace.o
CC drivers/ata/libata-sata.o
LD [M] drivers/misc/mei/mei-gsc.o
CC drivers/spi/spi.o
CC drivers/acpi/acpica/rscreate.o
CC fs/btrfs/dev-replace.o
CC net/ipv6/xfrm6_policy.o
CC drivers/base/platform.o
CC net/sunrpc/rpc_pipe.o
CC [M] net/bluetooth/mgmt_util.o
CC [M] net/bluetooth/mgmt_config.o
CC [M] net/bluetooth/hci_codec.o
CC kernel/pid_namespace.o
CC [M] drivers/gpu/drm/ttm/ttm_bo_vm.o
GEN drivers/scsi/scsi_devinfo_tbl.c
CC drivers/scsi/scsi_devinfo.o
CC net/ipv4/nexthop.o
CC drivers/scsi/scsi_sysctl.o
CC drivers/ata/libata-sff.o
CC [M] net/netfilter/xt_conntrack.o
CC net/ipv6/xfrm6_state.o
CC net/sunrpc/sysfs.o
CC [M] drivers/dma-buf/st-dma-resv.o
CC arch/x86/kernel/early_printk.o
CC drivers/nvme/host/pci.o
CC net/ipv4/udp_tunnel_stub.o
CC drivers/acpi/acpica/rsdumpinfo.o
CC mm/huge_memory.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_kms.o
CC [M] fs/cifs/cifs_spnego_negtokeninit.asn1.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.o
CC [M] fs/cifs/asn1.o
CC fs/btrfs/raid56.o
CC fs/fs_context.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_crtc.o
CC drivers/scsi/scsi_debugfs.o
CC lib/clz_ctz.o
AR drivers/dma-buf/built-in.a
LD [M] drivers/dma-buf/dmabuf_selftests.o
CC lib/bsearch.o
CC arch/x86/kernel/hpet.o
CC arch/x86/kernel/amd_nb.o
CC drivers/net/phy/mdio-boardinfo.o
CC drivers/acpi/acpica/rsinfo.o
CC drivers/net/phy/mdio_devres.o
CC drivers/acpi/acpica/rsio.o
CC [M] drivers/gpu/drm/ttm/ttm_module.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.o
UPD kernel/config_data
CC kernel/stop_machine.o
CC arch/x86/kernel/kvm.o
CC drivers/ata/libata-pmp.o
CC net/ipv6/xfrm6_input.o
CC net/ipv6/xfrm6_output.o
CC fs/fs_parser.o
CC [M] drivers/gpu/drm/ttm/ttm_execbuf_util.o
CC [M] drivers/gpu/drm/amd/amdgpu/atom.o
CC drivers/acpi/acpica/rsirq.o
CC drivers/base/cpu.o
CC drivers/scsi/scsi_trace.o
CC kernel/kprobes.o
CC [M] net/bluetooth/eir.o
CC drivers/ata/libata-acpi.o
CC [M] drivers/gpu/drm/i915/i915_drm_client.o
CC drivers/scsi/scsi_logging.o
CC drivers/base/firmware.o
CC lib/find_bit.o
CC [M] drivers/gpu/drm/i915/i915_config.o
CC drivers/ata/libata-pata-timings.o
CC kernel/hung_task.o
CC [M] net/netfilter/xt_ipvs.o
CC fs/btrfs/uuid-tree.o
CC fs/btrfs/props.o
CC [M] drivers/gpu/drm/ttm/ttm_range_manager.o
CC drivers/net/phy/phy.o
CC drivers/acpi/acpica/rslist.o
CC drivers/net/phy/phy-c45.o
CC net/ipv4/sysctl_net_ipv4.o
CC fs/btrfs/free-space-tree.o
CC lib/llist.o
CC kernel/watchdog.o
CC net/sunrpc/svc_xprt.o
CC mm/khugepaged.o
CC drivers/scsi/scsi_pm.o
CC net/sunrpc/xprtmultipath.o
CC drivers/scsi/scsi_bsg.o
CC lib/memweight.o
CC lib/kfifo.o
CC net/ipv6/xfrm6_protocol.o
CC drivers/base/init.o
CC mm/page_counter.o
CC [M] drivers/gpu/drm/i915/i915_getparam.o
CC [M] drivers/gpu/drm/i915/i915_ioctl.o
CC fs/btrfs/tree-checker.o
CC mm/memcontrol.o
CC drivers/acpi/acpica/rsmemory.o
CC [M] drivers/gpu/drm/ttm/ttm_resource.o
CC drivers/scsi/scsi_common.o
CC net/ipv4/proc.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fence.o
CC [M] drivers/gpu/drm/i915/i915_irq.o
CC net/sunrpc/stats.o
CC drivers/acpi/acpica/rsmisc.o
CC arch/x86/kernel/kvmclock.o
CC arch/x86/kernel/paravirt.o
CC [M] net/bluetooth/hci_sync.o
CC [M] drivers/gpu/drm/i915/i915_mitigations.o
CC [M] drivers/gpu/drm/i915/i915_module.o
CC [M] drivers/gpu/drm/ttm/ttm_pool.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.o
CC net/ipv6/netfilter.o
CC drivers/ata/ahci.o
CC drivers/base/map.o
CC fs/fsopen.o
CC arch/x86/kernel/pvclock.o
CC drivers/scsi/sd.o
CC [M] drivers/gpu/drm/i915/i915_params.o
LD [M] net/netfilter/nf_conntrack.o
CC drivers/scsi/sg.o
LD [M] net/netfilter/nf_nat.o
CC arch/x86/kernel/pcspeaker.o
AR net/netfilter/built-in.a
CC lib/percpu-refcount.o
CC drivers/acpi/acpica/rsserial.o
CC lib/rhashtable.o
CC arch/x86/kernel/check.o
CC [M] drivers/gpu/drm/i915/i915_pci.o
CC drivers/acpi/acpica/rsutils.o
CC drivers/net/phy/phy-core.o
CC kernel/watchdog_hld.o
CC drivers/base/devres.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_object.o
CC net/ipv6/fib6_rules.o
AR drivers/nvme/host/built-in.a
AR drivers/nvme/built-in.a
AR drivers/firewire/built-in.a
CC arch/x86/kernel/uprobes.o
CC lib/base64.o
CC net/ipv4/syncookies.o
CC net/ipv4/esp4.o
CC arch/x86/kernel/perf_regs.o
CC arch/x86/kernel/tracepoint.o
CC fs/btrfs/space-info.o
CC kernel/seccomp.o
CC net/sunrpc/sysctl.o
CC [M] drivers/gpu/drm/ttm/ttm_device.o
CC arch/x86/kernel/itmt.o
CC drivers/net/phy/phy_device.o
CC [M] drivers/gpu/drm/vgem/vgem_drv.o
CC [M] drivers/gpu/drm/xe/tests/xe_bo_test.o
CC [M] drivers/gpu/drm/xe/tests/xe_dma_buf_test.o
CC [M] drivers/gpu/drm/xe/tests/xe_migrate_test.o
AR drivers/spi/built-in.a
CC arch/x86/kernel/umip.o
CC kernel/relay.o
CC drivers/acpi/acpica/rsxface.o
CC drivers/net/phy/linkmode.o
CC fs/init.o
CC [M] drivers/gpu/drm/nouveau/nvif/object.o
CC fs/kernel_read_file.o
CC lib/once.o
CC [M] drivers/gpu/drm/nouveau/nvif/client.o
LD [M] fs/cifs/cifs.o
CC fs/mnt_idmapping.o
AR drivers/cdrom/built-in.a
CC fs/btrfs/block-rsv.o
AR drivers/auxdisplay/built-in.a
CC drivers/net/phy/mdio_bus.o
CC drivers/ata/libahci.o
CC lib/refcount.o
CC arch/x86/kernel/unwind_orc.o
CC net/ipv6/proc.o
CC drivers/acpi/acpica/tbdata.o
CC [M] drivers/gpu/drm/xe/xe_bb.o
CC kernel/utsname_sysctl.o
CC [M] drivers/gpu/drm/xe/tests/xe_pci_test.o
CC [M] drivers/gpu/drm/xe/tests/xe_rtp_test.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gart.o
CC drivers/acpi/acpica/tbfadt.o
CC fs/btrfs/delalloc-space.o
CC drivers/base/attribute_container.o
CC drivers/base/transport_class.o
CC [M] drivers/gpu/drm/ttm/ttm_sys_manager.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.o
CC fs/btrfs/block-group.o
CC drivers/base/topology.o
CC drivers/acpi/acpica/tbfind.o
CC [M] drivers/gpu/drm/ttm/ttm_agp_backend.o
CC [M] drivers/gpu/drm/vgem/vgem_fence.o
CC drivers/base/container.o
CC mm/vmpressure.o
CC kernel/delayacct.o
CC arch/x86/kernel/callthunks.o
CC drivers/base/property.o
CC drivers/acpi/acpica/tbinstal.o
CC drivers/base/cacheinfo.o
CC drivers/base/swnode.o
CC lib/usercopy.o
AR net/sunrpc/built-in.a
CC [M] drivers/gpu/drm/xe/xe_bo.o
CC [M] drivers/gpu/drm/nouveau/nvif/conn.o
CC mm/swap_cgroup.o
CC drivers/scsi/scsi_sysfs.o
CC fs/btrfs/discard.o
CC drivers/acpi/acpica/tbprint.o
CC drivers/acpi/acpica/tbutils.o
CC [M] drivers/gpu/drm/xe/xe_bo_evict.o
CC drivers/acpi/acpica/tbxface.o
CC drivers/base/auxiliary.o
CC net/ipv6/syncookies.o
CC lib/errseq.o
CC [M] drivers/gpu/drm/ast/ast_drv.o
CC drivers/gpu/drm/drm_mipi_dsi.o
CC [M] drivers/gpu/drm/ast/ast_i2c.o
CC [M] drivers/gpu/drm/xe/xe_debugfs.o
CC [M] drivers/gpu/drm/ast/ast_main.o
CC lib/bucket_locks.o
CC [M] drivers/gpu/drm/ast/ast_mm.o
CC [M] drivers/gpu/drm/ast/ast_mode.o
CC fs/remap_range.o
LD [M] drivers/gpu/drm/ttm/ttm.o
CC arch/x86/kernel/mmconf-fam10h_64.o
CC [M] drivers/gpu/drm/xe/tests/xe_wa_test.o
CC kernel/taskstats.o
LD [M] drivers/gpu/drm/vgem/vgem.o
AR drivers/net/pse-pd/built-in.a
CC net/ipv6/mip6.o
CC drivers/acpi/acpica/tbxfload.o
CC drivers/acpi/acpica/tbxfroot.o
CC mm/hugetlb_cgroup.o
CC [M] drivers/gpu/drm/ast/ast_post.o
CC lib/generic-radix-tree.o
CC net/ipv4/esp4_offload.o
CC [M] net/bluetooth/sco.o
CC drivers/usb/common/common.o
CC net/ipv6/addrconf_core.o
CC drivers/usb/core/usb.o
AR drivers/usb/phy/built-in.a
CC mm/kmemleak.o
CC mm/page_isolation.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_display.o
CC drivers/usb/core/hub.o
CC mm/early_ioremap.o
CC kernel/tsacct.o
CC net/ipv6/exthdrs_core.o
CC [M] drivers/gpu/drm/i915/i915_scatterlist.o
CC kernel/tracepoint.o
CC kernel/latencytop.o
CC mm/cma.o
CC drivers/base/devtmpfs.o
CC [M] drivers/gpu/drm/i915/i915_suspend.o
CC drivers/net/phy/mdio_device.o
CC [M] drivers/gpu/drm/i915/i915_switcheroo.o
CC drivers/acpi/acpica/utaddress.o
CC [M] drivers/gpu/drm/nouveau/nvif/device.o
CC [M] drivers/gpu/drm/nouveau/nvif/disp.o
CC [M] drivers/gpu/drm/ast/ast_dp501.o
CC lib/string_helpers.o
CC arch/x86/kernel/vsmp_64.o
CC drivers/base/memory.o
CC [M] drivers/gpu/drm/ast/ast_dp.o
CC fs/btrfs/reflink.o
CC [M] drivers/gpu/drm/nouveau/nvif/driver.o
CC drivers/base/module.o
CC [M] drivers/gpu/drm/xe/xe_devcoredump.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.o
CC drivers/input/serio/serio.o
CC drivers/ata/ata_piix.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gem.o
CC drivers/usb/common/debug.o
CC mm/secretmem.o
CC [M] drivers/gpu/drm/xe/xe_device.o
CC drivers/acpi/acpica/utalloc.o
CC drivers/usb/core/hcd.o
CC kernel/irq_work.o
CC drivers/acpi/acpica/utascii.o
CC drivers/input/serio/i8042.o
AR arch/x86/kernel/built-in.a
AR drivers/usb/common/built-in.a
CC drivers/usb/host/pci-quirks.o
AR arch/x86/built-in.a
AR drivers/scsi/built-in.a
CC kernel/static_call.o
CC drivers/usb/host/ehci-hcd.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ring.o
CC drivers/input/keyboard/atkbd.o
AR drivers/input/mouse/built-in.a
CC drivers/usb/core/urb.o
CC drivers/input/input.o
CC drivers/rtc/lib.o
CC drivers/rtc/class.o
CC drivers/net/phy/swphy.o
CC drivers/rtc/interface.o
CC [M] drivers/gpu/drm/nouveau/nvif/event.o
CC net/ipv6/ip6_checksum.o
CC kernel/static_call_inline.o
CC [M] drivers/gpu/drm/nouveau/nvif/fifo.o
CC kernel/user-return-notifier.o
CC net/ipv4/netfilter.o
CC net/ipv4/inet_diag.o
CC lib/hexdump.o
CC net/ipv6/ip6_icmp.o
CC net/ipv6/output_core.o
CC drivers/acpi/acpica/utbuffer.o
CC [M] drivers/gpu/drm/xe/xe_dma_buf.o
CC drivers/base/pinctrl.o
CC drivers/base/devcoredump.o
CC kernel/padata.o
CC net/ipv4/tcp_diag.o
CC net/ipv4/udp_diag.o
CC drivers/rtc/nvmem.o
CC [M] drivers/gpu/drm/i915/i915_sysfs.o
LD [M] drivers/gpu/drm/ast/ast.o
CC drivers/net/phy/fixed_phy.o
CC drivers/input/input-compat.o
CC drivers/input/serio/libps2.o
CC kernel/jump_label.o
AR drivers/i2c/algos/built-in.a
CC lib/kstrtox.o
CC [M] drivers/i2c/algos/i2c-algo-bit.o
CC kernel/context_tracking.o
CC drivers/usb/core/message.o
CC [M] drivers/gpu/drm/xe/xe_engine.o
CC [M] net/bluetooth/iso.o
CC drivers/usb/storage/scsiglue.o
CC [M] net/bluetooth/a2mp.o
CC drivers/acpi/acpica/utcksum.o
CC drivers/usb/storage/protocol.o
CC fs/btrfs/subpage.o
CC drivers/usb/storage/transport.o
CC [M] drivers/net/phy/phylink.o
CC drivers/acpi/acpica/utcopy.o
AR drivers/ata/built-in.a
CC drivers/usb/serial/usb-serial.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_cs.o
CC drivers/usb/serial/generic.o
CC drivers/usb/host/ehci-pci.o
CC lib/debug_info.o
CC drivers/base/platform-msi.o
CC drivers/usb/serial/bus.o
CC fs/btrfs/tree-mod-log.o
CC fs/btrfs/extent-io-tree.o
CC drivers/input/input-mt.o
CC [M] drivers/gpu/drm/nouveau/nvif/head.o
CC drivers/net/mdio/acpi_mdio.o
CC mm/userfaultfd.o
AR drivers/input/keyboard/built-in.a
CC mm/memremap.o
CC drivers/acpi/acpica/utexcep.o
CC drivers/usb/core/driver.o
CC drivers/acpi/acpica/utdebug.o
CC mm/hmm.o
AR drivers/input/serio/built-in.a
CC [M] net/bluetooth/amp.o
CC [M] drivers/gpu/drm/nouveau/nvif/mem.o
CC [M] drivers/gpu/drm/nouveau/nvif/mmu.o
CC fs/btrfs/fs.o
CC kernel/iomem.o
CC [M] drivers/gpu/drm/i915/i915_utils.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_bios.o
CC drivers/net/mdio/fwnode_mdio.o
CC drivers/usb/storage/usb.o
CC net/ipv6/protocol.o
CC fs/btrfs/messages.o
CC mm/memfd.o
CC drivers/i2c/busses/i2c-designware-common.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.o
CC drivers/i2c/busses/i2c-designware-master.o
CC net/ipv4/tcp_cubic.o
CC drivers/base/physical_location.o
CC drivers/i2c/busses/i2c-designware-platdrv.o
CC drivers/acpi/acpica/utdecode.o
CC drivers/acpi/acpica/utdelete.o
CC drivers/usb/host/ohci-hcd.o
CC drivers/usb/serial/console.o
CC drivers/usb/host/ohci-pci.o
CC drivers/rtc/dev.o
CC drivers/input/input-poller.o
CC net/ipv4/xfrm4_policy.o
CC drivers/acpi/debugfs.o
CC mm/bootmem_info.o
CC [M] net/bluetooth/hci_debugfs.o
CC kernel/rseq.o
AR drivers/i2c/muxes/built-in.a
CC [M] drivers/i2c/muxes/i2c-mux-gpio.o
CC net/ipv4/xfrm4_state.o
CC drivers/usb/serial/ftdi_sio.o
CC [M] drivers/gpu/drm/nouveau/nvif/outp.o
CC drivers/base/trace.o
CC drivers/usb/host/uhci-hcd.o
AR drivers/net/mdio/built-in.a
CC drivers/usb/storage/initializers.o
CC drivers/acpi/acpica/uterror.o
CC [M] drivers/gpu/drm/xe/xe_exec.o
CC lib/iomap.o
CC [M] drivers/gpu/drm/xe/xe_execlist.o
CC [M] drivers/gpu/drm/i915/intel_clock_gating.o
CC drivers/usb/host/xhci.o
CC drivers/acpi/acpi_lpat.o
CC drivers/usb/serial/pl2303.o
CC drivers/acpi/acpica/uteval.o
CC net/ipv6/ip6_offload.o
CC net/ipv6/tcpv6_offload.o
CC [M] drivers/gpu/drm/drm_aperture.o
CC [M] drivers/gpu/drm/drm_atomic.o
CC drivers/input/ff-core.o
CC drivers/usb/storage/sierra_ms.o
CC drivers/usb/core/config.o
CC drivers/usb/storage/option_ms.o
CC drivers/i2c/i2c-boardinfo.o
CC drivers/rtc/proc.o
CC drivers/i2c/i2c-core-base.o
CC drivers/usb/storage/usual-tables.o
CC drivers/acpi/acpi_lpit.o
CC fs/btrfs/bio.o
CC fs/btrfs/lru_cache.o
CC drivers/acpi/prmt.o
GZIP kernel/config_data.gz
AR mm/built-in.a
AR drivers/net/pcs/built-in.a
CC drivers/usb/core/file.o
CC net/ipv6/exthdrs_offload.o
CC drivers/acpi/acpi_pcc.o
AR drivers/net/ethernet/adi/built-in.a
CC drivers/acpi/ac.o
CC drivers/i2c/busses/i2c-designware-baytrail.o
CC [M] drivers/gpu/drm/xe/xe_force_wake.o
AR drivers/net/ethernet/alacritech/built-in.a
AR drivers/net/ethernet/amazon/built-in.a
AR drivers/net/ethernet/aquantia/built-in.a
AR drivers/net/ethernet/asix/built-in.a
AR drivers/net/ethernet/cadence/built-in.a
AR drivers/net/ethernet/broadcom/built-in.a
CC [M] drivers/net/ethernet/broadcom/b44.o
CC drivers/acpi/button.o
CC drivers/i2c/i2c-core-smbus.o
CC drivers/acpi/acpica/utglobal.o
CC net/ipv6/inet6_hashtables.o
CC [M] drivers/net/phy/aquantia_main.o
AR drivers/base/built-in.a
CC [M] drivers/net/phy/aquantia_hwmon.o
AR drivers/i3c/built-in.a
CC fs/btrfs/acl.o
CC kernel/configs.o
CC drivers/usb/core/buffer.o
CC net/ipv4/xfrm4_input.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_dp.o
CC net/ipv4/xfrm4_output.o
CC drivers/rtc/sysfs.o
CC drivers/usb/core/sysfs.o
AR drivers/net/usb/built-in.a
CC [M] drivers/net/usb/pegasus.o
CC lib/pci_iomap.o
CC net/ipv4/xfrm4_protocol.o
CC [M] drivers/gpu/drm/nouveau/nvif/timer.o
CC [M] net/ipv4/ip_tunnel.o
CC drivers/input/touchscreen.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.o
AR drivers/usb/storage/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvif/vmm.o
CC drivers/acpi/fan_core.o
AR drivers/usb/misc/built-in.a
CC [M] drivers/usb/misc/ftdi-elan.o
CC drivers/usb/gadget/udc/core.o
CC drivers/i2c/i2c-core-acpi.o
CC drivers/acpi/acpica/uthex.o
AR drivers/usb/gadget/function/built-in.a
CC drivers/acpi/fan_attr.o
CC [M] drivers/gpu/drm/xe/xe_ggtt.o
AR drivers/media/i2c/built-in.a
AR drivers/media/tuners/built-in.a
AR drivers/ptp/built-in.a
AR drivers/media/rc/keymaps/built-in.a
AR drivers/media/rc/built-in.a
CC [M] drivers/ptp/ptp_clock.o
CC [M] drivers/i2c/busses/i2c-scmi.o
AR drivers/media/common/b2c2/built-in.a
AR drivers/media/common/saa7146/built-in.a
AR drivers/media/common/siano/built-in.a
AR drivers/media/common/v4l2-tpg/built-in.a
AR kernel/built-in.a
AR drivers/media/common/videobuf2/built-in.a
AR drivers/media/common/built-in.a
AR drivers/media/platform/allegro-dvt/built-in.a
AR drivers/usb/serial/built-in.a
AR drivers/media/platform/amphion/built-in.a
AR drivers/media/pci/ttpci/built-in.a
AR drivers/media/platform/amlogic/meson-ge2d/built-in.a
AR drivers/media/usb/b2c2/built-in.a
AR drivers/media/platform/amlogic/built-in.a
CC [M] drivers/usb/class/usbtmc.o
AR drivers/media/mmc/siano/built-in.a
AR drivers/media/pci/b2c2/built-in.a
AR drivers/media/usb/dvb-usb/built-in.a
AR drivers/media/mmc/built-in.a
AR drivers/media/platform/aspeed/built-in.a
AR drivers/media/pci/pluto2/built-in.a
AR drivers/media/usb/dvb-usb-v2/built-in.a
AR drivers/media/firewire/built-in.a
AR drivers/media/platform/atmel/built-in.a
CC drivers/i2c/i2c-core-slave.o
AR drivers/media/usb/s2255/built-in.a
AR drivers/media/pci/dm1105/built-in.a
AR drivers/media/platform/cadence/built-in.a
AR drivers/media/usb/siano/built-in.a
AR drivers/media/pci/pt1/built-in.a
AR drivers/media/usb/ttusb-budget/built-in.a
AR drivers/media/platform/chips-media/built-in.a
AR drivers/usb/gadget/legacy/built-in.a
CC [M] drivers/net/ethernet/broadcom/bnx2.o
AR drivers/media/pci/pt3/built-in.a
AR drivers/media/usb/ttusb-dec/built-in.a
CC net/ipv6/mcast_snoop.o
LD [M] net/bluetooth/bluetooth.o
AR drivers/media/platform/intel/built-in.a
AR drivers/media/usb/built-in.a
AR drivers/media/pci/mantis/built-in.a
CC [M] drivers/net/usb/rtl8150.o
AR drivers/media/platform/marvell/built-in.a
AR drivers/media/pci/ngene/built-in.a
CC [M] drivers/i2c/busses/i2c-ccgx-ucsi.o
CC drivers/input/ff-memless.o
AR drivers/media/pci/ddbridge/built-in.a
AR drivers/media/platform/mediatek/jpeg/built-in.a
AR drivers/media/pci/saa7146/built-in.a
AR drivers/media/platform/mediatek/mdp/built-in.a
AR drivers/media/pci/smipcie/built-in.a
CC drivers/usb/core/endpoint.o
AR drivers/media/platform/mediatek/vcodec/built-in.a
AR drivers/media/pci/netup_unidvb/built-in.a
AR drivers/media/platform/mediatek/vpu/built-in.a
AR drivers/media/platform/mediatek/mdp3/built-in.a
AR drivers/media/pci/intel/ipu3/built-in.a
AR drivers/media/platform/mediatek/built-in.a
AR drivers/media/pci/intel/built-in.a
CC drivers/acpi/acpica/utids.o
AR drivers/media/pci/built-in.a
AR drivers/media/platform/microchip/built-in.a
CC [M] drivers/net/phy/ax88796b.o
CC drivers/rtc/rtc-mc146818-lib.o
CC drivers/usb/gadget/usbstring.o
AR drivers/media/platform/nvidia/tegra-vde/built-in.a
CC lib/iomap_copy.o
AR drivers/media/platform/nvidia/built-in.a
CC lib/devres.o
AR drivers/media/platform/nxp/dw100/built-in.a
AR drivers/media/spi/built-in.a
AR drivers/media/platform/nxp/imx-jpeg/built-in.a
CC drivers/input/vivaldi-fmap.o
AR drivers/media/platform/nxp/built-in.a
AR drivers/media/platform/qcom/camss/built-in.a
AR drivers/media/test-drivers/built-in.a
AR drivers/media/platform/qcom/venus/built-in.a
AR drivers/media/platform/qcom/built-in.a
AR drivers/power/reset/built-in.a
CC drivers/power/supply/power_supply_core.o
CC [M] drivers/net/usb/r8152.o
AR drivers/media/platform/renesas/rcar-vin/built-in.a
AR drivers/media/platform/renesas/rzg2l-cru/built-in.a
AR drivers/media/platform/renesas/vsp1/built-in.a
AR drivers/media/platform/renesas/built-in.a
AR drivers/media/platform/rockchip/rga/built-in.a
AR drivers/media/platform/rockchip/rkisp1/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvif/user.o
AR drivers/media/platform/rockchip/built-in.a
CC drivers/hwmon/hwmon.o
CC [M] drivers/hwmon/acpi_power_meter.o
CC [M] drivers/gpu/drm/i915/intel_device_info.o
AR drivers/media/platform/samsung/exynos-gsc/built-in.a
AR drivers/media/platform/st/sti/bdisp/built-in.a
AR drivers/media/platform/samsung/exynos4-is/built-in.a
AR drivers/media/platform/st/sti/c8sectpfe/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvif/userc361.o
AR drivers/media/platform/samsung/s3c-camif/built-in.a
CC [M] drivers/gpu/drm/drm_atomic_uapi.o
AR drivers/media/platform/st/sti/delta/built-in.a
AR drivers/media/platform/samsung/s5p-g2d/built-in.a
AR drivers/media/platform/st/sti/hva/built-in.a
AR drivers/media/platform/samsung/s5p-jpeg/built-in.a
AR drivers/media/platform/st/stm32/built-in.a
AR drivers/media/platform/st/built-in.a
AR drivers/media/platform/samsung/s5p-mfc/built-in.a
AR drivers/media/platform/samsung/built-in.a
AR fs/btrfs/built-in.a
CC drivers/power/supply/power_supply_sysfs.o
CC fs/buffer.o
AR drivers/thermal/broadcom/built-in.a
AR drivers/media/platform/sunxi/sun4i-csi/built-in.a
AR drivers/thermal/samsung/built-in.a
AR drivers/media/platform/sunxi/sun6i-csi/built-in.a
CC drivers/power/supply/power_supply_leds.o
CC drivers/thermal/intel/intel_tcc.o
AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
CC [M] drivers/i2c/busses/i2c-i801.o
AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
CC fs/mpage.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.o
AR drivers/media/platform/sunxi/sun8i-di/built-in.a
AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a
AR drivers/media/platform/sunxi/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt.o
AR drivers/media/platform/ti/am437x/built-in.a
CC [M] drivers/gpu/drm/i915/intel_memory_region.o
CC [M] drivers/net/phy/bcm7xxx.o
AR drivers/media/platform/ti/cal/built-in.a
AR drivers/media/platform/ti/vpe/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_encoders.o
AR drivers/media/platform/ti/davinci/built-in.a
AR drivers/media/platform/ti/omap/built-in.a
CC drivers/acpi/acpica/utinit.o
AR drivers/media/platform/ti/omap3isp/built-in.a
CC drivers/acpi/acpica/utlock.o
AR drivers/media/platform/ti/built-in.a
CC drivers/acpi/acpica/utmath.o
CC drivers/thermal/intel/therm_throt.o
AR drivers/media/platform/verisilicon/built-in.a
CC [M] net/ipv6/ip6_udp_tunnel.o
AR drivers/media/platform/via/built-in.a
CC [M] drivers/i2c/busses/i2c-isch.o
AR drivers/media/platform/xilinx/built-in.a
CC drivers/usb/gadget/config.o
CC drivers/power/supply/power_supply_hwmon.o
AR drivers/media/platform/built-in.a
CC drivers/usb/gadget/epautoconf.o
CC [M] drivers/ptp/ptp_chardev.o
CC drivers/usb/core/devio.o
AR drivers/media/built-in.a
CC [M] net/ipv4/udp_tunnel_core.o
CC fs/proc_namespace.o
CC drivers/rtc/rtc-cmos.o
CC drivers/input/input-leds.o
CC [M] drivers/i2c/busses/i2c-ismt.o
CC drivers/usb/gadget/composite.o
CC drivers/usb/gadget/udc/trace.o
CC lib/check_signature.o
CC [M] drivers/net/phy/bcm87xx.o
CC [M] drivers/net/phy/bcm-phy-lib.o
CC [M] drivers/net/phy/broadcom.o
CC fs/direct-io.o
CC [M] drivers/i2c/busses/i2c-piix4.o
CC drivers/input/mousedev.o
CC drivers/acpi/acpica/utmisc.o
CC [M] drivers/net/phy/lxt.o
CC lib/interval_tree.o
CC drivers/acpi/acpica/utmutex.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/client.o
CC drivers/usb/host/xhci-mem.o
CC drivers/usb/gadget/functions.o
CC [M] drivers/net/ipvlan/ipvlan_core.o
CC [M] drivers/net/usb/asix_devices.o
CC [M] drivers/hwmon/coretemp.o
AR drivers/power/supply/built-in.a
AR drivers/power/built-in.a
CC [M] drivers/net/ipvlan/ipvlan_main.o
CC drivers/usb/host/xhci-ext-caps.o
CC lib/assoc_array.o
CC drivers/input/evdev.o
CC fs/eventpoll.o
CC drivers/usb/gadget/configfs.o
CC [M] drivers/net/ethernet/broadcom/cnic.o
CC drivers/usb/core/notify.o
CC drivers/usb/host/xhci-ring.o
CC drivers/acpi/acpica/utnonansi.o
CC drivers/acpi/acpica/utobject.o
CC [M] drivers/net/phy/realtek.o
CC drivers/acpi/acpica/utosi.o
CC [M] drivers/ptp/ptp_sysfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_clock.o
CC [M] drivers/ptp/ptp_vclock.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o
CC [M] drivers/net/ipvlan/ipvlan_l3s.o
CC [M] drivers/net/ethernet/broadcom/tg3.o
CC [M] net/ipv4/udp_tunnel_nic.o
CC drivers/usb/host/xhci-hub.o
AR net/ipv6/built-in.a
CC fs/anon_inodes.o
CC [M] drivers/i2c/busses/i2c-designware-pcidrv.o
AR drivers/rtc/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o
CC [M] drivers/thermal/intel/intel_menlow.o
CC drivers/acpi/processor_driver.o
CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o
CC drivers/usb/gadget/u_f.o
CC drivers/i2c/i2c-dev.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/engine.o
CC drivers/watchdog/watchdog_core.o
CC fs/signalfd.o
CC [M] drivers/i2c/i2c-smbus.o
CC [M] drivers/i2c/i2c-mux.o
CC drivers/acpi/acpica/utownerid.o
CC [M] drivers/net/phy/smsc.o
CC fs/timerfd.o
AR drivers/usb/gadget/udc/built-in.a
CC fs/eventfd.o
CC drivers/acpi/acpica/utpredef.o
CC drivers/watchdog/watchdog_dev.o
AR drivers/hwmon/built-in.a
CC [M] drivers/md/persistent-data/dm-array.o
CC drivers/md/md.o
CC lib/list_debug.o
CC drivers/md/md-bitmap.o
CC fs/userfaultfd.o
CC drivers/watchdog/softdog.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/enum.o
CC lib/debugobjects.o
CC [M] drivers/ptp/ptp_kvm_x86.o
CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o
CC [M] drivers/md/persistent-data/dm-bitset.o
CC [M] drivers/net/usb/asix_common.o
CC [M] drivers/net/vxlan/vxlan_core.o
CC [M] drivers/net/vxlan/vxlan_multicast.o
CC drivers/acpi/acpica/utresdecode.o
CC [M] drivers/gpu/drm/i915/intel_pcode.o
CC [M] drivers/net/vxlan/vxlan_vnifilter.o
AR drivers/input/built-in.a
CC [M] drivers/ptp/ptp_kvm_common.o
CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o
CC [M] drivers/gpu/drm/i915/intel_region_ttm.o
LD [M] drivers/i2c/busses/i2c-designware-pci.o
AR drivers/i2c/busses/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sa.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_i2c.o
AR drivers/thermal/intel/built-in.a
AR drivers/thermal/st/built-in.a
AR drivers/thermal/qcom/built-in.a
AR drivers/thermal/tegra/built-in.a
AR drivers/thermal/mediatek/built-in.a
CC drivers/thermal/thermal_core.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/event.o
LD [M] drivers/net/ipvlan/ipvlan.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/firmware.o
CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
LD [M] drivers/ptp/ptp.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.o
CC fs/aio.o
CC drivers/acpi/processor_thermal.o
CC drivers/usb/host/xhci-dbg.o
CC drivers/acpi/processor_idle.o
AR drivers/usb/gadget/built-in.a
CC drivers/usb/core/generic.o
CC drivers/usb/core/quirks.o
CC [M] drivers/gpu/drm/i915/intel_runtime_pm.o
CC drivers/net/loopback.o
CC drivers/acpi/acpica/utresrc.o
AR drivers/i2c/built-in.a
LD [M] drivers/net/phy/aquantia.o
CC drivers/md/md-autodetect.o
CC drivers/usb/host/xhci-trace.o
AR drivers/net/phy/built-in.a
CC fs/locks.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/gpuobj.o
CC [M] drivers/gpu/drm/xe/xe_gt_topology.o
AR drivers/net/ethernet/cortina/built-in.a
AR drivers/net/ethernet/cavium/common/built-in.a
AR drivers/net/ethernet/cavium/thunder/built-in.a
AR drivers/net/ethernet/engleder/built-in.a
AR drivers/net/ethernet/cavium/liquidio/built-in.a
AR drivers/watchdog/built-in.a
AR drivers/net/ethernet/ezchip/built-in.a
CC lib/bitrev.o
AR drivers/net/ethernet/cavium/octeon/built-in.a
CC drivers/opp/core.o
AR drivers/net/ethernet/cavium/built-in.a
CC drivers/opp/cpu.o
CC [M] drivers/md/persistent-data/dm-block-manager.o
CC drivers/opp/debugfs.o
CC fs/binfmt_script.o
LD [M] drivers/ptp/ptp_kvm.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o
AR drivers/net/ethernet/fungible/built-in.a
AR drivers/net/ethernet/huawei/built-in.a
CC [M] drivers/net/ethernet/intel/e1000/e1000_main.o
AR net/ipv4/built-in.a
CC [M] drivers/net/ethernet/intel/e1000/e1000_hw.o
LD [M] net/ipv4/udp_tunnel.o
AR drivers/net/ethernet/i825xx/built-in.a
CC drivers/acpi/acpica/utstate.o
AR net/built-in.a
AR drivers/net/ethernet/microsoft/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/intr.o
AR drivers/net/ethernet/litex/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ib.o
CC [M] drivers/net/ethernet/intel/e1000e/82571.o
CC lib/crc16.o
CC [M] drivers/net/ethernet/intel/e1000e/ich8lan.o
CC [M] drivers/net/ethernet/intel/e1000e/80003es2lan.o
CC lib/crc-t10dif.o
CC drivers/usb/core/devices.o
CC drivers/usb/core/phy.o
HOSTCC lib/gen_crc32table
CC [M] drivers/gpu/drm/nouveau/nvkm/core/ioctl.o
CC lib/libcrc32c.o
AR drivers/net/ethernet/microchip/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/memory.o
CC drivers/acpi/processor_throttling.o
CC drivers/md/dm-uevent.o
CC lib/xxhash.o
CC lib/genalloc.o
CC lib/percpu_counter.o
CC drivers/md/dm.o
CC [M] drivers/net/ethernet/intel/igb/igb_main.o
CC [M] drivers/net/ethernet/intel/e1000e/mac.o
CC [M] drivers/gpu/drm/xe/xe_guc.o
CC [M] drivers/net/ethernet/intel/e1000e/manage.o
CC [M] drivers/gpu/drm/i915/intel_sbi.o
CC [M] drivers/md/persistent-data/dm-space-map-common.o
CC drivers/acpi/acpica/utstring.o
CC lib/fault-inject.o
CC [M] drivers/md/persistent-data/dm-space-map-disk.o
CC drivers/net/netconsole.o
CC drivers/usb/host/xhci-debugfs.o
CC lib/syscall.o
CC [M] drivers/net/usb/ax88172a.o
CC [M] drivers/net/ethernet/intel/igc/igc_main.o
CC [M] drivers/net/usb/ax88179_178a.o
CC drivers/acpi/acpica/utstrsuppt.o
CC [M] drivers/net/usb/cdc_ether.o
CC drivers/thermal/thermal_sysfs.o
CC drivers/cpufreq/cpufreq.o
CC [M] drivers/net/ethernet/intel/e1000e/nvm.o
CC drivers/acpi/acpica/utstrtoul64.o
CC drivers/usb/core/port.o
CC [M] drivers/md/persistent-data/dm-space-map-metadata.o
CC drivers/md/dm-table.o
CC drivers/usb/host/xhci-pci.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/mm.o
CC drivers/acpi/acpica/utxface.o
CC [M] drivers/gpu/drm/i915/intel_step.o
CC drivers/cpuidle/governors/menu.o
CC drivers/cpuidle/cpuidle.o
CC lib/dynamic_debug.o
CC [M] drivers/gpu/drm/i915/intel_uncore.o
CC drivers/cpuidle/driver.o
AR drivers/opp/built-in.a
CC drivers/usb/core/hcd-pci.o
CC drivers/usb/core/usb-acpi.o
AR drivers/net/ethernet/mscc/built-in.a
CC drivers/cpuidle/governors/haltpoll.o
CC fs/binfmt_elf.o
CC drivers/thermal/thermal_trip.o
CC [M] drivers/net/ethernet/intel/e1000e/phy.o
CC [M] drivers/gpu/drm/i915/intel_wakeref.o
CC [M] drivers/gpu/drm/i915/vlv_sideband.o
CC [M] drivers/net/ethernet/intel/e1000e/param.o
CC drivers/net/virtio_net.o
CC [M] drivers/net/ethernet/intel/igb/igb_ethtool.o
CC [M] drivers/gpu/drm/xe/xe_guc_ads.o
CC [M] drivers/gpu/drm/xe/xe_guc_ct.o
CC drivers/acpi/acpica/utxfinit.o
CC drivers/acpi/acpica/utxferror.o
CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o
CC drivers/thermal/thermal_helpers.o
CC [M] drivers/net/ethernet/intel/e1000e/ethtool.o
CC lib/errname.o
CC drivers/acpi/processor_perflib.o
CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o
CC [M] drivers/net/ethernet/intel/e1000e/netdev.o
CC [M] drivers/md/persistent-data/dm-transaction-manager.o
CC [M] drivers/md/persistent-data/dm-btree.o
CC [M] drivers/net/ethernet/intel/igb/e1000_82575.o
CC drivers/mmc/core/core.o
AR drivers/ufs/built-in.a
AR drivers/leds/trigger/built-in.a
CC [M] drivers/leds/trigger/ledtrig-audio.o
AR drivers/leds/blink/built-in.a
CC fs/compat_binfmt_elf.o
AR drivers/firmware/arm_ffa/built-in.a
AR drivers/firmware/arm_scmi/built-in.a
AR drivers/firmware/broadcom/built-in.a
CC drivers/acpi/acpica/utxfmutex.o
CC [M] drivers/md/persistent-data/dm-btree-remove.o
AR drivers/firmware/cirrus/built-in.a
AR drivers/firmware/meson/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/object.o
CC drivers/cpufreq/freq_table.o
CC drivers/mmc/host/sdhci.o
CC [M] drivers/net/usb/cdc_eem.o
CC [M] drivers/net/usb/smsc75xx.o
AR drivers/cpuidle/governors/built-in.a
CC drivers/mmc/host/sdhci-pci-core.o
CC drivers/firmware/efi/libstub/efi-stub-helper.o
AR drivers/usb/core/built-in.a
CC drivers/thermal/thermal_hwmon.o
CC drivers/clocksource/acpi_pm.o
AR drivers/crypto/stm32/built-in.a
AR drivers/crypto/xilinx/built-in.a
AR drivers/crypto/hisilicon/built-in.a
AR drivers/crypto/keembay/built-in.a
AR drivers/crypto/built-in.a
CC drivers/thermal/gov_fair_share.o
AR drivers/usb/host/built-in.a
AR drivers/usb/built-in.a
CC drivers/mmc/host/sdhci-pci-o2micro.o
CC drivers/cpuidle/governor.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_pll.o
CC drivers/mmc/host/sdhci-pci-arasan.o
AR drivers/leds/simple/built-in.a
CC drivers/leds/led-core.o
CC drivers/md/dm-target.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_ethtool.o
AR drivers/acpi/acpica/built-in.a
CC drivers/acpi/container.o
CC [M] drivers/gpu/drm/xe/xe_guc_log.o
CC drivers/hid/usbhid/hid-core.o
CC [M] drivers/net/usb/smsc95xx.o
CC drivers/hid/hid-core.o
CC drivers/acpi/thermal.o
CC [M] drivers/gpu/drm/i915/vlv_suspend.o
CC [M] drivers/gpu/drm/xe/xe_guc_pc.o
AR drivers/staging/media/built-in.a
AR drivers/staging/built-in.a
CC drivers/acpi/acpi_memhotplug.o
CC drivers/firmware/efi/efi-bgrt.o
CC drivers/cpuidle/sysfs.o
CC drivers/thermal/gov_step_wise.o
CC [M] drivers/net/usb/mcs7830.o
CC lib/nlattr.o
CC drivers/clocksource/i8253.o
CC [M] drivers/md/persistent-data/dm-btree-spine.o
CC drivers/cpufreq/cpufreq_performance.o
CC drivers/firmware/efi/libstub/gop.o
CC drivers/acpi/ioapic.o
AR drivers/platform/x86/amd/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_submit.o
CC drivers/platform/x86/intel/pmc/core.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/oproxy.o
CC drivers/platform/x86/intel/pmc/spt.o
CC drivers/leds/led-class.o
CC [M] drivers/gpu/drm/xe/xe_hw_fence.o
CC drivers/mailbox/mailbox.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/option.o
CC [M] drivers/net/usb/usbnet.o
CC drivers/thermal/gov_user_space.o
CC [M] drivers/net/usb/cdc_ncm.o
CC drivers/md/dm-linear.o
AR drivers/clocksource/built-in.a
CC drivers/firmware/efi/libstub/secureboot.o
CC drivers/cpufreq/cpufreq_ondemand.o
CC drivers/firmware/efi/libstub/tpm.o
CC [M] drivers/gpu/drm/xe/xe_huc.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.o
LD [M] drivers/net/vxlan/vxlan.o
CC drivers/cpuidle/poll_state.o
CC [M] drivers/net/ethernet/intel/igc/igc_mac.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_param.o
CC drivers/acpi/battery.o
CC drivers/mmc/host/sdhci-pci-dwc-mshc.o
LD [M] drivers/md/persistent-data/dm-persistent-data.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/ramht.o
CC drivers/cpuidle/cpuidle-haltpoll.o
CC fs/mbcache.o
CC drivers/md/dm-stripe.o
CC drivers/devfreq/devfreq.o
CC drivers/mailbox/pcc.o
CC [M] drivers/devfreq/governor_simpleondemand.o
CC drivers/leds/led-triggers.o
CC [M] drivers/devfreq/governor_performance.o
AR drivers/thermal/built-in.a
CC drivers/firmware/efi/libstub/file.o
CC drivers/firmware/efi/libstub/mem.o
CC drivers/platform/x86/intel/pmc/cnp.o
CC [M] drivers/net/ethernet/intel/e1000e/ptp.o
CC lib/checksum.o
CC [M] drivers/net/ethernet/intel/igc/igc_i225.o
CC [M] drivers/net/usb/r8153_ecm.o
CC drivers/platform/x86/intel/pmc/icl.o
CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_irq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/subdev.o
CC drivers/mmc/core/bus.o
CC [M] drivers/net/ethernet/intel/igc/igc_base.o
CC drivers/hid/usbhid/hiddev.o
AR drivers/cpuidle/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/uevent.o
CC drivers/platform/x86/intel/pmc/tgl.o
AR drivers/platform/surface/built-in.a
CC drivers/powercap/powercap_sys.o
CC drivers/mmc/core/host.o
CC drivers/powercap/intel_rapl_common.o
CC lib/cpu_rmap.o
CC drivers/cpufreq/cpufreq_governor.o
CC drivers/powercap/intel_rapl_msr.o
CC drivers/cpufreq/cpufreq_governor_attr_set.o
CC [M] drivers/net/ethernet/intel/igb/e1000_mac.o
CC fs/posix_acl.o
CC drivers/mmc/core/mmc.o
CC [M] drivers/gpu/drm/xe/xe_lrc.o
CC drivers/platform/x86/intel/pmc/adl.o
CC fs/coredump.o
CC [M] drivers/gpu/drm/i915/soc/intel_dram.o
AR drivers/mailbox/built-in.a
CC drivers/net/net_failover.o
CC drivers/firmware/efi/efi.o
CC drivers/firmware/efi/vars.o
CC lib/dynamic_queue_limits.o
CC drivers/firmware/efi/libstub/random.o
CC lib/glob.o
AR drivers/leds/built-in.a
CC drivers/mmc/host/sdhci-pci-gli.o
CC fs/drop_caches.o
CC [M] drivers/platform/x86/intel/pmt/class.o
CC fs/fhandle.o
LD [M] drivers/net/ethernet/intel/e1000/e1000.o
CC [M] drivers/gpu/drm/xe/xe_migrate.o
CC drivers/platform/x86/p2sb.o
CC drivers/platform/x86/pmc_atom.o
CC [M] drivers/net/ethernet/intel/igc/igc_nvm.o
CC drivers/acpi/hed.o
AR drivers/perf/built-in.a
CC [M] drivers/platform/x86/wmi.o
CC drivers/cpufreq/acpi-cpufreq.o
CC drivers/platform/x86/intel/turbo_max_3.o
CC drivers/ras/ras.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.o
CC drivers/platform/x86/intel/pmc/mtl.o
AR drivers/hwtracing/intel_th/built-in.a
CC drivers/ras/debugfs.o
CC drivers/cpufreq/intel_pstate.o
CC drivers/platform/x86/intel/pmc/pltdrv.o
CC lib/strncpy_from_user.o
CC [M] drivers/platform/x86/intel/pmt/telemetry.o
CC [M] drivers/gpu/drm/xe/xe_mmio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/fw.o
CC drivers/mmc/host/sdhci-acpi.o
CC [M] drivers/net/ethernet/intel/igc/igc_phy.o
CC drivers/acpi/bgrt.o
CC drivers/acpi/cppc_acpi.o
CC [M] drivers/net/ethernet/intel/igc/igc_diag.o
CC [M] drivers/net/dummy.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.o
CC drivers/firmware/efi/libstub/randomalloc.o
CC [M] drivers/net/macvlan.o
AR drivers/hid/usbhid/built-in.a
CC drivers/hid/hid-input.o
CC [M] drivers/gpu/drm/i915/soc/intel_gmch.o
AR drivers/devfreq/built-in.a
LD [M] drivers/net/usb/asix.o
CC drivers/android/binderfs.o
CC drivers/nvmem/core.o
CC [M] drivers/net/mii.o
CC [M] drivers/gpu/drm/xe/xe_mocs.o
AR drivers/firmware/imx/built-in.a
CC [M] drivers/net/mdio.o
AR drivers/powercap/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sync.o
CC drivers/android/binder.o
CC drivers/acpi/spcr.o
CC [M] drivers/gpu/drm/xe/xe_module.o
CC [M] drivers/gpu/drm/xe/xe_pat.o
CC [M] drivers/gpu/drm/xe/xe_pci.o
AR drivers/platform/x86/intel/pmc/built-in.a
CC drivers/acpi/acpi_pad.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/hs.o
CC [M] drivers/platform/x86/intel/pmt/crashlog.o
CC [M] drivers/mtd/chips/chipreg.o
CC lib/strnlen_user.o
CC drivers/firmware/efi/reboot.o
CC [M] drivers/gpu/drm/i915/soc/intel_pch.o
CC [M] drivers/gpu/drm/i915/i915_memcpy.o
CC [M] drivers/net/ethernet/intel/igb/e1000_nvm.o
CC drivers/md/dm-ioctl.o
CC [M] drivers/acpi/acpi_video.o
CC [M] drivers/acpi/video_detect.o
AR drivers/firmware/psci/built-in.a
CC [M] drivers/net/tun.o
CC drivers/firmware/efi/libstub/pci.o
CC drivers/firmware/efi/libstub/skip_spaces.o
CC [M] drivers/platform/x86/wmi-bmof.o
CC drivers/md/dm-io.o
CC [M] drivers/gpu/drm/xe/xe_pcode.o
CC [M] drivers/platform/x86/mxm-wmi.o
CC [M] drivers/gpu/drm/xe/xe_pm.o
AR drivers/ras/built-in.a
CC lib/net_utils.o
CC drivers/md/dm-kcopyd.o
CC [M] drivers/uio/uio.o
AR fs/built-in.a
AR drivers/firmware/smccc/built-in.a
CC [M] drivers/net/ethernet/intel/igc/igc_ethtool.o
CC [M] drivers/vfio/pci/vfio_pci_core.o
CC [M] drivers/gpu/drm/i915/i915_mm.o
CC drivers/mmc/host/cqhci-core.o
CC [M] drivers/net/ethernet/intel/igc/igc_ptp.o
CC [M] drivers/net/ethernet/intel/igc/igc_dump.o
CC [M] drivers/net/ethernet/intel/igc/igc_tsn.o
CC [M] drivers/mtd/mtdcore.o
CC drivers/mmc/core/mmc_ops.o
CC [M] drivers/mmc/host/sdhci-pltfm.o
CC [M] drivers/platform/x86/intel_ips.o
CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o
LD [M] drivers/platform/x86/intel/pmt/pmt_class.o
LD [M] drivers/platform/x86/intel/pmt/pmt_telemetry.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.o
LD [M] drivers/platform/x86/intel/pmt/pmt_crashlog.o
CC [M] drivers/vfio/pci/vfio_pci_intrs.o
CC [M] drivers/platform/x86/intel/vsec.o
CC [M] drivers/net/ethernet/intel/igc/igc_xdp.o
CC lib/sg_pool.o
CC drivers/hid/hid-quirks.o
CC lib/stackdepot.o
CC lib/ucs2_string.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/ls.o
CC drivers/firmware/efi/memattr.o
AR drivers/acpi/built-in.a
CC drivers/firmware/efi/tpm.o
CC drivers/firmware/efi/memmap.o
AR drivers/nvmem/built-in.a
CC drivers/firmware/efi/libstub/lib-cmdline.o
CC drivers/firmware/efi/libstub/lib-ctype.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.o
LD [M] drivers/net/ethernet/intel/e1000e/e1000e.o
CC [M] drivers/gpu/drm/xe/xe_pt.o
CC drivers/firmware/efi/libstub/alignedmem.o
CC [M] drivers/vfio/vfio_main.o
CC lib/sbitmap.o
CC [M] drivers/bluetooth/btusb.o
CC [M] drivers/pps/pps.o
CC [M] drivers/dca/dca-core.o
CC [M] drivers/net/ethernet/intel/igb/e1000_phy.o
CC [M] drivers/net/ethernet/intel/igb/e1000_mbx.o
CC drivers/md/dm-sysfs.o
CC lib/group_cpus.o
CC [M] drivers/bluetooth/btintel.o
CC [M] drivers/gpu/drm/xe/xe_pt_walk.o
AR drivers/net/ethernet/neterion/built-in.a
AR drivers/net/ethernet/netronome/built-in.a
CC [M] drivers/bluetooth/btbcm.o
CC [M] drivers/bluetooth/btrtl.o
CC [M] drivers/dca/dca-sysfs.o
CC [M] drivers/gpu/drm/i915/i915_sw_fence.o
CC [M] drivers/platform/x86/intel/rst.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/acr.o
CC [M] drivers/vfio/pci/vfio_pci_rdwr.o
CC [M] drivers/vfio/pci/vfio_pci_config.o
AR drivers/cpufreq/built-in.a
CC [M] drivers/vfio/pci/vfio_pci.o
CC drivers/mmc/core/sd.o
CC [M] drivers/ssb/main.o
CC [M] drivers/vhost/net.o
CC [M] drivers/ssb/scan.o
CC [M] drivers/pps/kapi.o
CC [M] drivers/ssb/sprom.o
CC [M] drivers/ssb/pci.o
CC [M] drivers/vhost/vhost.o
CC drivers/firmware/efi/libstub/relocate.o
CC drivers/firmware/efi/libstub/printk.o
CC [M] lib/asn1_decoder.o
LD [M] drivers/acpi/video.o
CC [M] drivers/pps/sysfs.o
CC drivers/md/dm-stats.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.o
CC drivers/md/dm-rq.o
CC drivers/md/dm-io-rewind.o
CC drivers/md/dm-builtin.o
CC [M] drivers/md/dm-bufio.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o
LD [M] drivers/platform/x86/intel/intel_vsec.o
AR drivers/platform/x86/intel/built-in.a
AR drivers/mmc/host/built-in.a
CC [M] drivers/net/ethernet/intel/igbvf/vf.o
GEN lib/oid_registry_data.c
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_main.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_common.o
CC [M] drivers/net/ethernet/intel/igbvf/mbx.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.o
LD [M] drivers/platform/x86/intel/intel-rst.o
LD [M] drivers/dca/dca.o
AR drivers/platform/x86/built-in.a
CC [M] drivers/gpu/drm/i915/i915_sw_fence_work.o
AR drivers/platform/built-in.a
CC drivers/firmware/efi/libstub/vsprintf.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/base.o
CC [M] lib/oid_registry.o
CC [M] drivers/net/ethernet/intel/igbvf/ethtool.o
CC [M] drivers/net/ethernet/intel/igbvf/netdev.o
LD [M] drivers/pps/pps_core.o
LD [M] drivers/net/ethernet/intel/igc/igc.o
CC [M] drivers/md/dm-bio-prison-v1.o
CC drivers/firmware/efi/esrt.o
CC [M] drivers/mtd/mtdsuper.o
CC [M] drivers/gpu/drm/i915/i915_syncmap.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.o
CC [M] drivers/md/dm-bio-prison-v2.o
CC [M] drivers/gpu/drm/xe/xe_query.o
AR drivers/net/ethernet/ni/built-in.a
CC [M] drivers/gpu/drm/i915/i915_user_extensions.o
CC [M] drivers/net/ethernet/intel/ixgbevf/vf.o
CC drivers/firmware/efi/libstub/x86-stub.o
AR drivers/net/ethernet/packetengines/built-in.a
CC drivers/hid/hid-debug.o
CC [M] drivers/net/ethernet/intel/ixgbevf/mbx.o
CC [M] drivers/mtd/mtdconcat.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/fw.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_82599.o
AR lib/lib.a
CC [M] drivers/vfio/group.o
GEN lib/crc32table.h
CC [M] drivers/md/dm-crypt.o
CC [M] drivers/gpu/drm/i915/i915_ioc32.o
CC lib/crc32.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ethtool.o
CC drivers/mmc/core/sd_ops.o
CC [M] drivers/gpu/drm/xe/xe_reg_sr.o
CC drivers/android/binder_alloc.o
CC drivers/mmc/core/sdio.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.o
CC [M] drivers/net/ethernet/intel/igb/e1000_i210.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_82598.o
CC drivers/firmware/efi/efi-pstore.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/msgq.o
CC [M] drivers/ssb/pcihost_wrapper.o
CC [M] drivers/md/dm-thin.o
LD [M] drivers/vfio/pci/vfio-pci.o
LD [M] drivers/vfio/pci/vfio-pci-core.o
CC [M] drivers/vfio/iova_bitmap.o
CC [M] drivers/net/ethernet/intel/igb/igb_ptp.o
CC [M] drivers/gpu/drm/i915/i915_debugfs.o
CC [M] drivers/net/ethernet/intel/igb/igb_hwmon.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ipsec.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.o
CC [M] drivers/mtd/mtdpart.o
CC [M] drivers/ssb/driver_chipcommon.o
CC drivers/mmc/core/sdio_ops.o
CC drivers/mmc/core/sdio_bus.o
AR lib/built-in.a
CC [M] drivers/vhost/iotlb.o
STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_phy.o
STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
STUBCPY drivers/firmware/efi/libstub/file.stub.o
STUBCPY drivers/firmware/efi/libstub/gop.stub.o
STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
STUBCPY drivers/firmware/efi/libstub/mem.stub.o
STUBCPY drivers/firmware/efi/libstub/pci.stub.o
STUBCPY drivers/firmware/efi/libstub/printk.stub.o
STUBCPY drivers/firmware/efi/libstub/random.stub.o
STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o
STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
CC [M] drivers/md/dm-thin-metadata.o
STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
LD [M] drivers/md/dm-bio-prison.o
STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
AR drivers/md/built-in.a
STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
CC drivers/mmc/core/sdio_cis.o
STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
CC drivers/hid/hidraw.o
CC drivers/mmc/core/sdio_io.o
CC drivers/hid/hid-generic.o
CC [M] drivers/gpu/drm/xe/xe_rtp.o
CC [M] drivers/ssb/driver_chipcommon_pmu.o
AR drivers/firmware/efi/libstub/lib.a
CC drivers/mmc/core/sdio_irq.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.o
CC [M] drivers/gpu/drm/i915/i915_debugfs_params.o
CC drivers/firmware/efi/cper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/v1.o
CC [M] drivers/gpu/drm/drm_auth.o
LD [M] drivers/vhost/vhost_net.o
CC [M] drivers/ssb/driver_pcicore.o
CC [M] drivers/gpu/drm/i915/display/intel_display_debugfs.o
CC [M] drivers/gpu/drm/drm_blend.o
CC [M] drivers/vfio/container.o
CC [M] drivers/mtd/mtdchar.o
CC [M] drivers/gpu/drm/i915/display/intel_pipe_crc.o
CC [M] drivers/gpu/drm/i915/i915_pmu.o
LD [M] drivers/vhost/vhost_iotlb.o
CC [M] drivers/gpu/drm/i915/gt/gen2_engine_cs.o
CC [M] drivers/net/veth.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.o
CC drivers/mmc/core/slot-gpio.o
CC drivers/hid/hid-a4tech.o
CC drivers/mmc/core/regulator.o
CC drivers/hid/hid-apple.o
CC drivers/hid/hid-belkin.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/gm200.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_x540.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_x550.o
CC drivers/mmc/core/debugfs.o
AR drivers/net/ethernet/realtek/built-in.a
CC [M] drivers/net/ethernet/realtek/8139cp.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_lib.o
CC [M] drivers/gpu/drm/xe/xe_ring_ops.o
AR drivers/net/ethernet/renesas/built-in.a
CC [M] drivers/gpu/drm/xe/xe_sa.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sched.o
CC [M] drivers/gpu/drm/drm_bridge.o
CC [M] drivers/vfio/virqfd.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.o
CC [M] drivers/gpu/drm/drm_cache.o
CC [M] drivers/net/ethernet/realtek/8139too.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.o
CC [M] drivers/vfio/vfio_iommu_type1.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ids.o
LD [M] drivers/ssb/ssb.o
CC [M] drivers/gpu/drm/i915/gt/gen6_engine_cs.o
CC [M] drivers/gpu/drm/i915/gt/gen6_ppgtt.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_main.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_hw.o
LD [M] drivers/net/ethernet/intel/igbvf/igbvf.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_ee.o
CC [M] drivers/gpu/drm/i915/gt/gen7_renderclear.o
AR drivers/net/ethernet/intel/built-in.a
CC [M] drivers/gpu/drm/i915/gt/gen8_engine_cs.o
CC drivers/firmware/efi/cper_cxl.o
CC drivers/mmc/core/block.o
LD [M] drivers/net/ethernet/intel/igb/igb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/gp102.o
AR drivers/net/ethernet/sfc/built-in.a
CC drivers/mmc/core/queue.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_ethtool.o
CC drivers/hid/hid-cherry.o
CC [M] drivers/net/ethernet/realtek/r8169_main.o
CC [M] drivers/net/ethernet/intel/e100.o
CC [M] drivers/gpu/drm/drm_client.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.o
LD [M] drivers/mtd/mtd.o
AR drivers/android/built-in.a
CC drivers/firmware/efi/runtime-wrappers.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.o
AR drivers/firmware/tegra/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.o
CC drivers/hid/hid-chicony.o
CC [M] drivers/gpu/drm/xe/xe_sched_job.o
CC [M] drivers/gpu/drm/i915/gt/gen8_ppgtt.o
CC [M] drivers/net/ethernet/intel/ixgb/ixgb_param.o
CC [M] drivers/gpu/drm/xe/xe_step.o
CC [M] drivers/gpu/drm/drm_client_modeset.o
CC [M] drivers/gpu/drm/drm_color_mgmt.o
CC [M] drivers/gpu/drm/xe/xe_sync.o
CC drivers/hid/hid-cypress.o
CC [M] drivers/net/ethernet/realtek/r8169_firmware.o
AR drivers/net/ethernet/smsc/built-in.a
CC [M] drivers/net/ethernet/smsc/smsc9420.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/ga100.o
CC drivers/firmware/efi/dev-path-parser.o
CC [M] drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.o
LD [M] drivers/vfio/vfio.o
LD [M] drivers/md/dm-thin-pool.o
CC drivers/hid/hid-ezkey.o
CC drivers/hid/hid-kensington.o
CC [M] drivers/gpu/drm/xe/xe_tile.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.o
CC [M] drivers/gpu/drm/i915/gt/intel_context.o
AR drivers/firmware/xilinx/built-in.a
CC [M] drivers/net/ethernet/realtek/r8169_phy_config.o
CC [M] drivers/gpu/drm/i915/gt/intel_context_sseu.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_cs.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
CC [M] drivers/gpu/drm/drm_connector.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.o
CC [M] drivers/gpu/drm/xe/xe_trace.o
CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.o
CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_pm.o
CC [M] drivers/gpu/drm/drm_crtc.o
CC drivers/firmware/dmi_scan.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/ga102.o
CC drivers/hid/hid-lg.o
CC drivers/firmware/efi/apple-properties.o
AR drivers/net/ethernet/socionext/built-in.a
AR drivers/net/ethernet/vertexcom/built-in.a
AR drivers/net/ethernet/wangxun/built-in.a
AR drivers/net/ethernet/xilinx/built-in.a
AR drivers/net/ethernet/synopsys/built-in.a
CC drivers/firmware/dmi-sysfs.o
AR drivers/net/ethernet/pensando/built-in.a
CC drivers/firmware/efi/earlycon.o
CC drivers/hid/hid-lg-g15.o
CC drivers/firmware/efi/cper-x86.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.o
CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.o
CC drivers/hid/hid-microsoft.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.o
CC drivers/hid/hid-monterey.o
CC [M] drivers/gpu/drm/xe/xe_tuning.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_csa.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
LD [M] drivers/net/ethernet/intel/ixgbevf/ixgbevf.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.o
LD [M] drivers/net/ethernet/intel/ixgb/ixgb.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.o
CC [M] drivers/gpu/drm/drm_displayid.o
CC [M] drivers/gpu/drm/xe/xe_uc.o
CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_user.o
AR drivers/mmc/core/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_execlists_submission.o
AR drivers/mmc/built-in.a
CC drivers/firmware/dmi-id.o
CC [M] drivers/gpu/drm/xe/xe_uc_fw.o
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.o
CC [M] drivers/gpu/drm/drm_drv.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.o
CC drivers/firmware/memmap.o
AR drivers/firmware/efi/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gv100.o
CC [M] drivers/gpu/drm/drm_dumb_buffers.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.o
CC [M] drivers/gpu/drm/xe/xe_vm.o
CC [M] drivers/gpu/drm/xe/xe_vm_madvise.o
CC [M] drivers/gpu/drm/drm_edid.o
CC [M] drivers/gpu/drm/drm_encoder.o
CC [M] drivers/gpu/drm/drm_file.o
CC [M] drivers/gpu/drm/drm_fourcc.o
CC [M] drivers/gpu/drm/drm_framebuffer.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.o
CC [M] drivers/gpu/drm/drm_gem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.o
AR drivers/hid/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
CC [M] drivers/gpu/drm/drm_ioctl.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_umc.o
CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o
CC [M] drivers/gpu/drm/xe/xe_wa.o
CC [M] drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
AR drivers/firmware/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
CC [M] drivers/gpu/drm/xe/xe_wopcm.o
CC [M] drivers/gpu/drm/drm_lease.o
CC [M] drivers/gpu/drm/xe/xe_display.o
CC [M] drivers/gpu/drm/drm_managed.o
CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.o
CC [M] drivers/gpu/drm/drm_mm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.o
CC [M] drivers/gpu/drm/drm_mode_config.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
CC [M] drivers/gpu/drm/drm_mode_object.o
CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_irq.o
LD [M] drivers/net/ethernet/realtek/r8169.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.o
CC [M] drivers/gpu/drm/drm_modes.o
CC [M] drivers/gpu/drm/drm_modeset_lock.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.o
CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.o
CC [M] drivers/gpu/drm/drm_plane.o
CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_rap.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_clock_gating.o
CC [M] drivers/gpu/drm/drm_prime.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_mcr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
CC [M] drivers/gpu/drm/drm_print.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.o
CC [M] drivers/gpu/drm/drm_property.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
CC [M] drivers/gpu/drm/drm_syncobj.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mca.o
CC [M] drivers/gpu/drm/drm_sysfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_requests.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_device_info.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
CC [M] drivers/gpu/drm/drm_trace_points.o
CC [M] drivers/gpu/drm/drm_vblank.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.o
CC [M] drivers/gpu/drm/drm_vblank_work.o
CC [M] drivers/gpu/drm/drm_vma_manager.o
CC [M] drivers/gpu/drm/i915/gt/intel_gtt.o
CC [M] drivers/gpu/drm/drm_writeback.o
CC [M] drivers/gpu/drm/i915/gt/intel_llc.o
LD [M] drivers/net/ethernet/intel/ixgbe/ixgbe.o
CC [M] drivers/gpu/drm/lib/drm_random.o
CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.o
AR drivers/net/ethernet/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.o
AR drivers/net/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_migrate.o
CC [M] drivers/gpu/drm/i915/gt/intel_mocs.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_dram.o
../drivers/gpu/drm/i915/gt/intel_engine_cs.c:1525: warning: expecting prototype for intel_engines_cleanup_common(). Prototype was for intel_engine_cleanup_common() instead
CC [M] drivers/gpu/drm/i915/gt/intel_ppgtt.o
CC [M] drivers/gpu/drm/xe/display/ext/intel_pch.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.o
CC [M] drivers/gpu/drm/xe/i915-display/icl_dsi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik.o
CC [M] drivers/gpu/drm/drm_ioc32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.o
CC [M] drivers/gpu/drm/drm_panel.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/drm_pci.o
CC [M] drivers/gpu/drm/drm_debugfs.o
CC [M] drivers/gpu/drm/drm_debugfs_crc.o
CC [M] drivers/gpu/drm/drm_edid_load.o
CC [M] drivers/gpu/drm/i915/gt/intel_rc6.o
CC [M] drivers/gpu/drm/i915/gt/intel_region_lmem.o
CC [M] drivers/gpu/drm/i915/gt/intel_renderstate.o
CC [M] drivers/gpu/drm/drm_panel_orientation_quirks.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik_ih.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v8_0.o
CC [M] drivers/gpu/drm/i915/gt/intel_reset.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.o
CC [M] drivers/gpu/drm/i915/gt/intel_ring.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.o
CC [M] drivers/gpu/drm/i915/gt/intel_ring_submission.o
CC [M] drivers/gpu/drm/i915/gt/intel_rps.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.o
CC [M] drivers/gpu/drm/i915/gt/intel_sa_media.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_audio.o
CC [M] drivers/gpu/drm/i915/gt/intel_sseu.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_backlight.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.o
CC [M] drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v7_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik_sdma.o
CC [M] drivers/gpu/drm/drm_buddy.o
CC [M] drivers/gpu/drm/drm_gem_shmem_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bios.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.o
CC [M] drivers/gpu/drm/drm_suballoc.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v4_2.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v2_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.o
CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o
CC [M] drivers/gpu/drm/i915/gt/intel_timeline.o
CC [M] drivers/gpu/drm/i915/gt/intel_wopcm.o
CC [M] drivers/gpu/drm/i915/gt/intel_workarounds.o
CC [M] drivers/gpu/drm/amd/amdgpu/si.o
CC [M] drivers/gpu/drm/drm_atomic_helper.o
CC [M] drivers/gpu/drm/drm_atomic_state_helper.o
CC [M] drivers/gpu/drm/drm_bridge_connector.o
CC [M] drivers/gpu/drm/drm_crtc_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v6_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bw.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.o
CC [M] drivers/gpu/drm/i915/gt/shmem_utils.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.o
CC [M] drivers/gpu/drm/i915/gt/sysfs_engines.o
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
CC [M] drivers/gpu/drm/i915/gt/gen6_renderstate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cdclk.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v6_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/si_ih.o
CC [M] drivers/gpu/drm/drm_damage_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/si_dma.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.o
CC [M] drivers/gpu/drm/drm_encoder_slave.o
CC [M] drivers/gpu/drm/i915/gt/gen7_renderstate.o
CC [M] drivers/gpu/drm/drm_flip_work.o
CC [M] drivers/gpu/drm/drm_format_helper.o
CC [M] drivers/gpu/drm/i915/gt/gen8_renderstate.o
CC [M] drivers/gpu/drm/i915/gt/gen9_renderstate.o
CC [M] drivers/gpu/drm/drm_gem_atomic_helper.o
CC [M] drivers/gpu/drm/drm_gem_framebuffer_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_busy.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_clflush.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v6_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/vpstate.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_color.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_context.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_create.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v3_1.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
CC [M] drivers/gpu/drm/drm_kms_helper_common.o
CC [M] drivers/gpu/drm/drm_modeset_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_domain.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
CC [M] drivers/gpu/drm/drm_plane_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_internal.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.o
CC [M] drivers/gpu/drm/amd/amdgpu/vi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_object.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_lmem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_mman.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_pages.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_vi.o
CC [M] drivers/gpu/drm/drm_probe_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v6_1.o
CC [M] drivers/gpu/drm/drm_rect.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/soc15.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_combo_phy.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_phys.o
CC [M] drivers/gpu/drm/drm_self_refresh_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_pm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_connector.o
CC [M] drivers/gpu/drm/drm_simple_kms_helper.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/emu_soc.o
CC [M] drivers/gpu/drm/bridge/panel.o
CC [M] drivers/gpu/drm/drm_fbdev_generic.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_region.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_shmem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_stolen.o
CC [M] drivers/gpu/drm/drm_fb_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_ai.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega10_reg_init.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_throttle.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o
LD [M] drivers/gpu/drm/drm.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_tiling.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega20_reg_init.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_4.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.o
LD [M] drivers/gpu/drm/drm_shmem_helper.o
LD [M] drivers/gpu/drm/drm_suballoc_helper.o
LD [M] drivers/gpu/drm/drm_ttm_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
AR drivers/gpu/drm/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cursor.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_userptr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v2_3.o
CC [M] drivers/gpu/drm/amd/amdgpu/nv.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_wait.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.o
CC [M] drivers/gpu/drm/i915/gem/i915_gemfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/arct_reg_init.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_nv.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_2.o
CC [M] drivers/gpu/drm/i915/i915_active.o
CC [M] drivers/gpu/drm/i915/i915_cmd_parser.o
CC [M] drivers/gpu/drm/i915/i915_deps.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v4_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v5_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.o
CC [M] drivers/gpu/drm/i915/i915_gem_evict.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.o
CC [M] drivers/gpu/drm/i915/i915_gem_gtt.o
CC [M] drivers/gpu/drm/i915/i915_gem_ww.o
CC [M] drivers/gpu/drm/amd/amdgpu/aldebaran.o
CC [M] drivers/gpu/drm/i915/i915_gem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.o
CC [M] drivers/gpu/drm/i915/i915_query.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display.o
CC [M] drivers/gpu/drm/i915/i915_request.o
CC [M] drivers/gpu/drm/i915/i915_scheduler.o
CC [M] drivers/gpu/drm/i915/i915_trace_points.o
CC [M] drivers/gpu/drm/amd/amdgpu/soc21.o
CC [M] drivers/gpu/drm/amd/amdgpu/sienna_cichlid.o
CC [M] drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
CC [M] drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_driver.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.o
CC [M] drivers/gpu/drm/i915/i915_vma.o
CC [M] drivers/gpu/drm/i915/i915_vma_resource.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v4_3.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
LD [M] drivers/gpu/drm/drm_kms_helper.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v6_0.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_7.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v5_2.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power.o
CC [M] drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_9.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v1_7.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_map.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v3_6.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v4_3.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_well.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v7_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v8_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_trace.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v9_0.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.o
CC [M] drivers/gpu/drm/i915/gt/intel_gsc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.o
CC [M] drivers/gpu/drm/i915/i915_hwmon.o
CC [M] drivers/gpu/drm/i915/display/hsw_ips.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.o
CC [M] drivers/gpu/drm/i915/display/intel_atomic.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.o
CC [M] drivers/gpu/drm/i915/display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v10_0.o
CC [M] drivers/gpu/drm/i915/display/intel_audio.o
CC [M] drivers/gpu/drm/i915/display/intel_bios.o
CC [M] drivers/gpu/drm/i915/display/intel_bw.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.o
CC [M] drivers/gpu/drm/i915/display/intel_cdclk.o
CC [M] drivers/gpu/drm/i915/display/intel_color.o
CC [M] drivers/gpu/drm/i915/display/intel_combo_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.o
CC [M] drivers/gpu/drm/i915/display/intel_connector.o
CC [M] drivers/gpu/drm/i915/display/intel_crtc.o
CC [M] drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/i915/display/intel_cursor.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc.o
CC [M] drivers/gpu/drm/i915/display/intel_display.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp.o
CC [M] drivers/gpu/drm/i915/display/intel_display_driver.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power_map.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power_well.o
CC [M] drivers/gpu/drm/i915/display/intel_display_reset.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.o
CC [M] drivers/gpu/drm/i915/display/intel_display_rps.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v11_0.o
CC [M] drivers/gpu/drm/i915/display/intel_dmc.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.o
CC [M] drivers/gpu/drm/i915/display/intel_dpio_phy.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.o
CC [M] drivers/gpu/drm/i915/display/intel_dpll.o
CC [M] drivers/gpu/drm/i915/display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.o
CC [M] drivers/gpu/drm/i915/display/intel_dpt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.o
CC [M] drivers/gpu/drm/i915/display/intel_drrs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.o
CC [M] drivers/gpu/drm/i915/display/intel_dsb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_1.o
CC [M] drivers/gpu/drm/i915/display/intel_fb.o
CC [M] drivers/gpu/drm/i915/display/intel_fb_pin.o
CC [M] drivers/gpu/drm/i915/display/intel_fbc.o
CC [M] drivers/gpu/drm/i915/display/intel_fdi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.o
CC [M] drivers/gpu/drm/i915/display/intel_fifo_underrun.o
CC [M] drivers/gpu/drm/i915/display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/i915/display/intel_global_state.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o
CC [M] drivers/gpu/drm/i915/display/intel_hdcp.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_7.o
CC [M] drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v8_7.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_mst.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v8_10.o
CC [M] drivers/gpu/drm/i915/display/intel_hotplug.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll.o
CC [M] drivers/gpu/drm/i915/display/intel_hotplug_irq.o
CC [M] drivers/gpu/drm/i915/display/intel_hti.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_irq.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ih.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpt.o
CC [M] drivers/gpu/drm/amd/amdgpu/iceland_ih.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.o
CC [M] drivers/gpu/drm/amd/amdgpu/tonga_ih.o
CC [M] drivers/gpu/drm/i915/display/intel_load_detect.o
CC [M] drivers/gpu/drm/amd/amdgpu/cz_ih.o
CC [M] drivers/gpu/drm/i915/display/intel_lpe_audio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.o
CC [M] drivers/gpu/drm/i915/display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/i915/display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_drrs.o
CC [M] drivers/gpu/drm/i915/display/intel_overlay.o
CC [M] drivers/gpu/drm/i915/display/intel_pch_display.o
CC [M] drivers/gpu/drm/i915/display/intel_pch_refclk.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega10_ih.o
CC [M] drivers/gpu/drm/i915/display/intel_plane_initial.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsb.o
CC [M] drivers/gpu/drm/i915/display/intel_psr.o
CC [M] drivers/gpu/drm/i915/display/intel_quirks.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega20_ih.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.o
CC [M] drivers/gpu/drm/i915/display/intel_sprite.o
CC [M] drivers/gpu/drm/i915/display/intel_sprite_uapi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.o
CC [M] drivers/gpu/drm/i915/display/intel_tc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.o
CC [M] drivers/gpu/drm/i915/display/intel_vblank.o
CC [M] drivers/gpu/drm/i915/display/intel_vga.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi.o
CC [M] drivers/gpu/drm/i915/display/intel_wm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o
CC [M] drivers/gpu/drm/i915/display/i9xx_plane.o
CC [M] drivers/gpu/drm/amd/amdgpu/navi10_ih.o
CC [M] drivers/gpu/drm/i915/display/i9xx_wm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.o
CC [M] drivers/gpu/drm/amd/amdgpu/ih_v6_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_psp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fbc.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v3_1.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v10_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fdi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/i915/display/skl_scaler.o
CC [M] drivers/gpu/drm/i915/display/skl_universal_plane.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_global_state.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_gmbus.o
CC [M] drivers/gpu/drm/i915/display/skl_watermark.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v11_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.o
CC [M] drivers/gpu/drm/i915/display/intel_acpi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdmi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.o
CC [M] drivers/gpu/drm/i915/display/intel_opregion.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v12_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v13_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hti.o
CC [M] drivers/gpu/drm/i915/display/intel_fbdev.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.o
CC [M] drivers/gpu/drm/i915/display/dvo_ch7017.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.o
CC [M] drivers/gpu/drm/i915/display/dvo_ch7xxx.o
CC [M] drivers/gpu/drm/i915/display/dvo_ivch.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_lspcon.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v10_0.o
CC [M] drivers/gpu/drm/i915/display/dvo_ns2501.o
CC [M] drivers/gpu/drm/i915/display/dvo_sil164.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v11_0.o
CC [M] drivers/gpu/drm/i915/display/dvo_tfp410.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.o
CC [M] drivers/gpu/drm/i915/display/g4x_dp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_panel.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.o
CC [M] drivers/gpu/drm/i915/display/g4x_hdmi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pps.o
CC [M] drivers/gpu/drm/i915/display/icl_dsi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_psr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_qp_tables.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v8_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.o
CC [M] drivers/gpu/drm/i915/display/intel_backlight.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_0.o
CC [M] drivers/gpu/drm/i915/display/intel_crt.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_quirks.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_phy.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.o
CC [M] drivers/gpu/drm/i915/display/intel_cx0_phy.o
CC [M] drivers/gpu/drm/i915/display/intel_ddi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_tc.o
CC [M] drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.o
CC [M] drivers/gpu/drm/i915/display/intel_display_trace.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.o
CC [M] drivers/gpu/drm/i915/display/intel_dkl_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.o
CC [M] drivers/gpu/drm/i915/display/intel_dp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vblank.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_aux.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_link_training.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vdsc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vga.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vrr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_wm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v10_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/imu_v11_0.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_scaler.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v11_0.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_universal_plane.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_watermark.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_acpi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_mst.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_opregion.o
CC [M] drivers/gpu/drm/i915/display/intel_dsi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fbdev.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.o
CC [M] drivers/gpu/drm/amd/amdgpu/imu_v11_0_3.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.o
CC [M] drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
CC [M] drivers/gpu/drm/i915/display/intel_dsi_vbt.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v2_4.o
CC [M] drivers/gpu/drm/i915/display/intel_dvo.o
HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v3_0.o
HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h
CC [M] drivers/gpu/drm/i915/display/intel_gmbus.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.o
HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_0.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h
CC [M] drivers/gpu/drm/i915/display/intel_hdmi.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
CC [M] drivers/gpu/drm/i915/display/intel_lspcon.o
CC [M] drivers/gpu/drm/i915/display/intel_lvds.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_4.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.o
CC [M] drivers/gpu/drm/i915/display/intel_panel.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h
CC [M] drivers/gpu/drm/i915/display/intel_pps.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v5_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h
CC [M] drivers/gpu/drm/i915/display/intel_qp_tables.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h
CC [M] drivers/gpu/drm/i915/display/intel_sdvo.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h
CC [M] drivers/gpu/drm/i915/display/intel_snps_phy.o
CC [M] drivers/gpu/drm/i915/display/intel_tv.o
CC [M] drivers/gpu/drm/i915/display/intel_vdsc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_config.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h
CC [M] drivers/gpu/drm/i915/display/intel_vrr.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v5_2.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h
CC [M] drivers/gpu/drm/i915/display/vlv_dsi.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v6_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h
CC [M] drivers/gpu/drm/i915/display/vlv_dsi_pll.o
CC [M] drivers/gpu/drm/i915/i915_perf.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mes.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h
CC [M] drivers/gpu/drm/amd/amdgpu/mes_v10_1.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pm_types.h
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_cmd.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/mes_v11_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.o
HDRTEST drivers/gpu/drm/xe/display/ext/i915_irq.h
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_irq.o
HDRTEST drivers/gpu/drm/xe/display/ext/intel_pch.h
HDRTEST drivers/gpu/drm/xe/display/ext/intel_dram.h
HDRTEST drivers/gpu/drm/xe/display/ext/intel_device_info.h
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_pm.o
HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_session.o
HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h
CC [M] drivers/gpu/drm/i915/i915_gpu_error.o
HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h
HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h
CC [M] drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.o
HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h
HDRTEST drivers/gpu/drm/xe/tests/xe_test.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.o
HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h
HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.o
HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v5_0.o
HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h
HDRTEST drivers/gpu/drm/xe/xe_bb.h
HDRTEST drivers/gpu/drm/xe/xe_bb_types.h
HDRTEST drivers/gpu/drm/xe/xe_bo.h
CC [M] drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.o
CC [M] drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.o
HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h
HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h
HDRTEST drivers/gpu/drm/xe/xe_bo_types.h
HDRTEST drivers/gpu/drm/xe/xe_debugfs.h
CC [M] drivers/gpu/drm/i915/selftests/i915_random.o
HDRTEST drivers/gpu/drm/xe/xe_devcoredump.h
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v6_0.o
HDRTEST drivers/gpu/drm/xe/xe_devcoredump_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.o
CC [M] drivers/gpu/drm/i915/selftests/i915_selftest.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v7_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vce.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v3_0.o
CC [M] drivers/gpu/drm/i915/selftests/igt_atomic.o
HDRTEST drivers/gpu/drm/xe/xe_device.h
CC [M] drivers/gpu/drm/i915/selftests/igt_flush_test.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v4_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.o
CC [M] drivers/gpu/drm/i915/selftests/igt_live_test.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.o
CC [M] drivers/gpu/drm/i915/selftests/igt_mmap.o
CC [M] drivers/gpu/drm/i915/selftests/igt_reset.o
CC [M] drivers/gpu/drm/i915/selftests/igt_spinner.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.o
CC [M] drivers/gpu/drm/i915/selftests/librapl.o
HDRTEST drivers/gpu/drm/xe/xe_device_types.h
HDRTEST drivers/gpu/drm/xe/xe_display.h
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v1_0.o
CC [M] drivers/gpu/drm/i915/i915_vgpu.o
HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v2_0.o
HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h
HDRTEST drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
HDRTEST drivers/gpu/drm/i915/display/hsw_ips.h
HDRTEST drivers/gpu/drm/i915/display/g4x_hdmi.h
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_overlay.h
HDRTEST drivers/gpu/drm/xe/xe_drv.h
HDRTEST drivers/gpu/drm/i915/display/intel_display.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.o
HDRTEST drivers/gpu/drm/i915/display/skl_watermark_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_dmc.h
HDRTEST drivers/gpu/drm/i915/display/intel_vga.h
HDRTEST drivers/gpu/drm/xe/xe_engine.h
HDRTEST drivers/gpu/drm/i915/display/intel_audio.h
HDRTEST drivers/gpu/drm/i915/display/intel_lvds.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.o
HDRTEST drivers/gpu/drm/i915/display/intel_modeset_setup.h
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v2_5.o
HDRTEST drivers/gpu/drm/i915/display/intel_cdclk.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_limits.h
HDRTEST drivers/gpu/drm/i915/display/intel_hotplug.h
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v3_0.o
HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy.h
HDRTEST drivers/gpu/drm/i915/display/intel_atomic.h
HDRTEST drivers/gpu/drm/xe/xe_engine_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_driver.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.o
HDRTEST drivers/gpu/drm/i915/display/intel_dpll.h
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v4_0.o
HDRTEST drivers/gpu/drm/xe/xe_exec.h
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h
HDRTEST drivers/gpu/drm/xe/xe_execlist.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_mst.h
HDRTEST drivers/gpu/drm/i915/display/intel_fdi_regs.h
HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h
HDRTEST drivers/gpu/drm/i915/display/g4x_dp.h
HDRTEST drivers/gpu/drm/i915/display/intel_tc.h
HDRTEST drivers/gpu/drm/i915/display/intel_dsi_vbt.h
HDRTEST drivers/gpu/drm/i915/display/intel_frontbuffer.h
HDRTEST drivers/gpu/drm/xe/xe_force_wake.h
HDRTEST drivers/gpu/drm/i915/display/intel_psr.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.o
HDRTEST drivers/gpu/drm/i915/display/intel_crt.h
HDRTEST drivers/gpu/drm/i915/display/intel_opregion.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.o
HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.o
HDRTEST drivers/gpu/drm/i915/display/i9xx_wm.h
HDRTEST drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.o
HDRTEST drivers/gpu/drm/i915/display/intel_global_state.h
HDRTEST drivers/gpu/drm/i915/display/intel_lpe_audio.h
HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_drrs.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_rps.h
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.o
HDRTEST drivers/gpu/drm/xe/xe_ggtt.h
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.o
HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt.h
HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h
HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h
HDRTEST drivers/gpu/drm/i915/display/intel_fbdev.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.o
HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h
HDRTEST drivers/gpu/drm/xe/xe_gt_printk.h
HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h
HDRTEST drivers/gpu/drm/i915/display/intel_pps_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v1_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.o
HDRTEST drivers/gpu/drm/i915/display/intel_hdmi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v2_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.o
HDRTEST drivers/gpu/drm/i915/display/intel_fdi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.o
HDRTEST drivers/gpu/drm/i915/display/intel_fb.h
HDRTEST drivers/gpu/drm/i915/display/intel_qp_tables.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.o
HDRTEST drivers/gpu/drm/i915/display/intel_dsb_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_vdsc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v2_1.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.o
HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v3_0.o
HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy.h
HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_core.h
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll.h
HDRTEST drivers/gpu/drm/i915/display/intel_dvo_dev.h
HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v9_0.o
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp.h
../drivers/gpu/drm/i915/i915_gpu_error.c:2174: warning: Function parameter or member 'dump_flags' not described in 'i915_capture_error_state'
HDRTEST drivers/gpu/drm/i915/display/intel_sdvo_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v11_0.o
HDRTEST drivers/gpu/drm/i915/display/intel_pch_refclk.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_trace.h
HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_power.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.o
HDRTEST drivers/gpu/drm/xe/xe_gt_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.o
HDRTEST drivers/gpu/drm/xe/xe_guc.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0.o
HDRTEST drivers/gpu/drm/i915/display/i9xx_plane.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_backlight.h
HDRTEST drivers/gpu/drm/i915/display/intel_dpll_mgr.h
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.o
HDRTEST drivers/gpu/drm/i915/display/intel_plane_initial.h
HDRTEST drivers/gpu/drm/i915/display/intel_fifo_underrun.h
../drivers/gpu/drm/i915/i915_perf.c:5307: warning: Function parameter or member 'i915' not described in 'i915_perf_ioctl_version'
HDRTEST drivers/gpu/drm/i915/display/intel_cursor.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.o
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_cx0_phy.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.o
HDRTEST drivers/gpu/drm/i915/display/skl_scaler.h
HDRTEST drivers/gpu/drm/i915/display/intel_hti.h
HDRTEST drivers/gpu/drm/i915/display/icl_dsi_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_reset.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/mca_v3_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.o
HDRTEST drivers/gpu/drm/i915/display/intel_atomic_plane.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_module.o
HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h
HDRTEST drivers/gpu/drm/i915/display/skl_watermark.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.o
HDRTEST drivers/gpu/drm/i915/display/intel_fbc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv4e.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_reg_defs.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.o
HDRTEST drivers/gpu/drm/i915/display/intel_acpi.h
HDRTEST drivers/gpu/drm/i915/display/intel_connector.h
HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_guc_engine_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_dpt.h
HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.o
HDRTEST drivers/gpu/drm/i915/display/intel_quirks.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_link_training.h
HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h
HDRTEST drivers/gpu/drm/i915/display/intel_color.h
HDRTEST drivers/gpu/drm/xe/xe_guc_log.h
HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_crtc.h
HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_modeset_verify.h
HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h
HDRTEST drivers/gpu/drm/xe/xe_guc_submit_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_power_well.h
HDRTEST drivers/gpu/drm/xe/xe_guc_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv50.o
HDRTEST drivers/gpu/drm/xe/xe_huc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_pasid.o
HDRTEST drivers/gpu/drm/i915/display/intel_psr_regs.h
HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.o
HDRTEST drivers/gpu/drm/xe/xe_huc_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.o
HDRTEST drivers/gpu/drm/i915/display/intel_wm.h
HDRTEST drivers/gpu/drm/i915/display/intel_pipe_crc.h
HDRTEST drivers/gpu/drm/i915/display/intel_audio_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgf119.o
HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_flat_memory.o
HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.o
HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h
HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h
HDRTEST drivers/gpu/drm/xe/xe_irq.h
HDRTEST drivers/gpu/drm/i915/display/intel_panel.h
HDRTEST drivers/gpu/drm/i915/display/intel_sprite.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.o
HDRTEST drivers/gpu/drm/i915/display/intel_wm_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.o
HDRTEST drivers/gpu/drm/xe/xe_lrc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager.o
HDRTEST drivers/gpu/drm/i915/display/intel_tv.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_cik.o
HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.o
HDRTEST drivers/gpu/drm/xe/xe_macros.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.o
HDRTEST drivers/gpu/drm/i915/display/intel_hti_regs.h
HDRTEST drivers/gpu/drm/xe/xe_map.h
HDRTEST drivers/gpu/drm/xe/xe_migrate.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.o
HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h
HDRTEST drivers/gpu/drm/xe/xe_mmio.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v9.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgf119.o
HDRTEST drivers/gpu/drm/xe/xe_mocs.h
HDRTEST drivers/gpu/drm/i915/display/intel_vrr.h
HDRTEST drivers/gpu/drm/xe/xe_module.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.o
HDRTEST drivers/gpu/drm/i915/display/intel_load_detect.h
HDRTEST drivers/gpu/drm/xe/xe_pat.h
HDRTEST drivers/gpu/drm/i915/display/skl_universal_plane.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v11.o
HDRTEST drivers/gpu/drm/xe/xe_pci.h
HDRTEST drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
HDRTEST drivers/gpu/drm/xe/xe_pci_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue.o
HDRTEST drivers/gpu/drm/i915/display/intel_bw.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager.o
HDRTEST drivers/gpu/drm/i915/display/intel_de.h
HDRTEST drivers/gpu/drm/i915/display/intel_lvds_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.o
HDRTEST drivers/gpu/drm/i915/display/intel_gmbus_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.o
HDRTEST drivers/gpu/drm/i915/display/intel_dvo.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_vi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_v9.o
HDRTEST drivers/gpu/drm/xe/xe_pcode.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process_queue_manager.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.o
HDRTEST drivers/gpu/drm/i915/display/intel_sdvo.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux.h
HDRTEST drivers/gpu/drm/i915/display/intel_vdsc_regs.h
HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.o
HDRTEST drivers/gpu/drm/xe/xe_platform_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy.h
HDRTEST drivers/gpu/drm/xe/xe_pm.h
HDRTEST drivers/gpu/drm/i915/display/intel_dvo_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.o
HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.o
HDRTEST drivers/gpu/drm/i915/display/intel_gmbus.h
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_cik.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.o
HDRTEST drivers/gpu/drm/i915/display/intel_dsi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.o
HDRTEST drivers/gpu/drm/i915/display/intel_dmc_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_ddi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_vi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v9.o
HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.o
HDRTEST drivers/gpu/drm/i915/display/intel_hotplug_irq.h
HDRTEST drivers/gpu/drm/xe/xe_pt.h
HDRTEST drivers/gpu/drm/i915/display/intel_tv_regs.h
HDRTEST drivers/gpu/drm/xe/xe_pt_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_dsb.h
HDRTEST drivers/gpu/drm/i915/display/intel_bios.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v10.o
HDRTEST drivers/gpu/drm/xe/xe_pt_walk.h
HDRTEST drivers/gpu/drm/i915/display/intel_pch_display.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.o
HDRTEST drivers/gpu/drm/i915/display/intel_backlight.h
HDRTEST drivers/gpu/drm/i915/display/intel_vblank.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp.h
HDRTEST drivers/gpu/drm/i915/display/intel_backlight_regs.h
HDRTEST drivers/gpu/drm/xe/xe_query.h
HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v11.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.o
HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_reset.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ga102.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_power_map.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.o
HDRTEST drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.o
HDRTEST drivers/gpu/drm/i915/display/icl_dsi.h
HDRTEST drivers/gpu/drm/i915/display/intel_lspcon.h
HDRTEST drivers/gpu/drm/i915/display/intel_dpio_phy.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/cik_event_interrupt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_hdcp.h
HDRTEST drivers/gpu/drm/i915/display/intel_fb_pin.h
HDRTEST drivers/gpu/drm/i915/display/intel_pps.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.o
HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h
HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.o
HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h
HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.o
HDRTEST drivers/gpu/drm/i915/display/intel_sprite_uapi.h
HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_region.h
HDRTEST drivers/gpu/drm/xe/xe_rtp.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context_types.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_lmem.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.o
../drivers/gpu/drm/i915/gem/i915_gem_region.h:25: warning: Incorrect use of kernel-doc format: * process_obj - Process the current object
../drivers/gpu/drm/i915/gem/i915_gem_region.h:35: warning: Function parameter or member 'process_obj' not described in 'i915_gem_apply_to_region_ops'
HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h
HDRTEST drivers/gpu/drm/xe/xe_sa.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_mman.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object_types.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.o
HDRTEST drivers/gpu/drm/xe/xe_sa_types.h
HDRTEST drivers/gpu/drm/xe/xe_sched_job.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.o
HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h
HDRTEST drivers/gpu/drm/xe/xe_step.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.o
HDRTEST drivers/gpu/drm/xe/xe_step_types.h
HDRTEST drivers/gpu/drm/xe/xe_sync.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.o
HDRTEST drivers/gpu/drm/xe/xe_sync_types.h
HDRTEST drivers/gpu/drm/xe/xe_tile.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.o
HDRTEST drivers/gpu/drm/xe/xe_trace.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_clflush.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_tiling.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.o
HDRTEST drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h
HDRTEST drivers/gpu/drm/xe/xe_ttm_sys_mgr.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_stolen.h
HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.o
HDRTEST drivers/gpu/drm/xe/xe_tuning.h
HDRTEST drivers/gpu/drm/xe/xe_uc.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
HDRTEST drivers/gpu/drm/xe/xe_uc_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.o
HDRTEST drivers/gpu/drm/xe/xe_uc_fw.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_create.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_job.o
HDRTEST drivers/gpu/drm/xe/xe_uc_fw_abi.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_move.h
../drivers/gpu/drm/i915/gem/i915_gem_ttm.h:50: warning: Function parameter or member 'bo' not described in 'i915_ttm_to_gem'
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_acp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.o
HDRTEST drivers/gpu/drm/xe/xe_uc_fw_types.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_domain.h
HDRTEST drivers/gpu/drm/xe/xe_uc_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_internal.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h
CC [M] drivers/gpu/drm/amd/amdgpu/../acp/acp_hw.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_context.h
HDRTEST drivers/gpu/drm/i915/gem/selftests/huge_gem_object.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_gem_object.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h
HDRTEST drivers/gpu/drm/xe/xe_vm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.o
HDRTEST drivers/gpu/drm/xe/xe_vm_doc.h
HDRTEST drivers/gpu/drm/xe/xe_vm_madvise.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/arcturus_ppt.o
HDRTEST drivers/gpu/drm/xe/xe_vm_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.o
HDRTEST drivers/gpu/drm/xe/xe_wa.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.o
HDRTEST drivers/gpu/drm/xe/xe_wait_user_fence.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_userptr.h
HDRTEST drivers/gpu/drm/xe/xe_wopcm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.o
HDRTEST drivers/gpu/drm/xe/xe_wopcm_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.o
LD [M] drivers/gpu/drm/xe/xe.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_pm.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gemfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/cyan_skillfish_ppt.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/smu_v11_0.o
HDRTEST drivers/gpu/drm/i915/gt/intel_timeline_types.h
HDRTEST drivers/gpu/drm/i915/gt/selftest_engine.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/renoir_ppt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmmcp77.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/smu_v12_0.o
HDRTEST drivers/gpu/drm/i915/gt/intel_context_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.o
HDRTEST drivers/gpu/drm/i915/gt/intel_execlists_submission.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm.h
HDRTEST drivers/gpu/drm/i915/gt/selftest_rc6.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_0_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_4_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_5_ppt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_7_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.o
HDRTEST drivers/gpu/drm/i915/gt/intel_llc_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt.h
HDRTEST drivers/gpu/drm/i915/gt/intel_region_lmem.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.o
drivers/gpu/drm/xe/xe.o: warning: objtool: intel_set_cpu_fifo_underrun_reporting+0x306: unreachable instruction
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_requests.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.o
HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smumgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_print.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.o
HDRTEST drivers/gpu/drm/i915/gt/gen8_ppgtt.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_mcr.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.o
../drivers/gpu/drm/i915/gem/i915_gem_object.h:94: warning: Function parameter or member 'file' not described in 'i915_gem_object_lookup_rcu'
../drivers/gpu/drm/i915/gem/i915_gem_object.h:94: warning: Excess function parameter 'filp' description in 'i915_gem_object_lookup_rcu'
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu8_smumgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_timeline.h
HDRTEST drivers/gpu/drm/i915/gt/gen6_engine_cs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds_types.h
HDRTEST drivers/gpu/drm/i915/gt/selftest_rps.h
HDRTEST drivers/gpu/drm/i915/gt/intel_sa_media.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/tonga_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h
HDRTEST drivers/gpu/drm/i915/gt/intel_rps_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/fiji_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/polaris10_smumgr.o
HDRTEST drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h
HDRTEST drivers/gpu/drm/i915/gt/sysfs_engines.h
HDRTEST drivers/gpu/drm/i915/gt/gen7_renderclear.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.o
HDRTEST drivers/gpu/drm/i915/gt/intel_context.h
HDRTEST drivers/gpu/drm/i915/gt/intel_wopcm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.o
HDRTEST drivers/gpu/drm/i915/gt/intel_mocs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_rc6.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ring_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/iceland_smumgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu7_smumgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega10_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.o
HDRTEST drivers/gpu/drm/i915/gt/shmem_utils.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine.h
HDRTEST drivers/gpu/drm/i915/gt/intel_reset_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu10_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.o
HDRTEST drivers/gpu/drm/i915/gt/intel_reset.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
HDRTEST drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/ci_smumgr.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega12_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vegam_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu9_smumgr.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega20_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hwmgr.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/processpptables.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu8_hwmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pppcielanes.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/process_pptables_v1_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.o
../drivers/gpu/drm/i915/gt/intel_context.h:108: warning: Function parameter or member 'ce' not described in 'intel_context_lock_pinned'
../drivers/gpu/drm/i915/gt/intel_context.h:123: warning: Function parameter or member 'ce' not described in 'intel_context_is_pinned'
../drivers/gpu/drm/i915/gt/intel_context.h:142: warning: Function parameter or member 'ce' not described in 'intel_context_unlock_pinned'
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomfwctrl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:27: warning: Function parameter or member 'size' not described in '__guc_capture_bufstate'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:27: warning: Function parameter or member 'data' not described in '__guc_capture_bufstate'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:27: warning: Function parameter or member 'rd' not described in '__guc_capture_bufstate'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:27: warning: Function parameter or member 'wr' not described in '__guc_capture_bufstate'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:59: warning: Function parameter or member 'link' not described in '__guc_capture_parsed_output'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:59: warning: Function parameter or member 'is_partial' not described in '__guc_capture_parsed_output'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:59: warning: Function parameter or member 'eng_class' not described in '__guc_capture_parsed_output'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:59: warning: Function parameter or member 'eng_inst' not described in '__guc_capture_parsed_output'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:59: warning: Function parameter or member 'guc_id' not described in '__guc_capture_parsed_output'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:59: warning: Function parameter or member 'lrca' not described in '__guc_capture_parsed_output'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:59: warning: Function parameter or member 'reginfo' not described in '__guc_capture_parsed_output'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:62: warning: wrong kernel-doc identifier on line:
* struct guc_debug_capture_list_header / struct guc_debug_capture_list
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:80: warning: wrong kernel-doc identifier on line:
* struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:105: warning: wrong kernel-doc identifier on line:
* struct guc_state_capture_header_t / struct guc_state_capture_t /
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:163: warning: Function parameter or member 'is_valid' not described in '__guc_capture_ads_cache'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:163: warning: Function parameter or member 'ptr' not described in '__guc_capture_ads_cache'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:163: warning: Function parameter or member 'size' not described in '__guc_capture_ads_cache'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:163: warning: Function parameter or member 'status' not described in '__guc_capture_ads_cache'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:216: warning: Function parameter or member 'ads_null_cache' not described in 'intel_guc_state_capture'
../drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:216: warning: Function parameter or member 'max_mmio_per_node' not described in 'intel_guc_state_capture'
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_powertune.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_hwconfig.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.o
HDRTEST drivers/gpu/drm/i915/gt/intel_llc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_thermal.o
HDRTEST drivers/gpu/drm/i915/gt/gen8_engine_cs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_clockpowergating.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_processpptables.o
HDRTEST drivers/gpu/drm/i915/gt/intel_sseu_debugfs.h
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'marker' not described in 'guc_log_buffer_state'
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'read_ptr' not described in 'guc_log_buffer_state'
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'write_ptr' not described in 'guc_log_buffer_state'
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'size' not described in 'guc_log_buffer_state'
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'sampled_write_ptr' not described in 'guc_log_buffer_state'
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'wrap_offset' not described in 'guc_log_buffer_state'
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'flush_to_file' not described in 'guc_log_buffer_state'
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'buffer_full_cnt' not described in 'guc_log_buffer_state'
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'reserved' not described in 'guc_log_buffer_state'
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'flags' not described in 'guc_log_buffer_state'
../drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:491: warning: Function parameter or member 'version' not described in 'guc_log_buffer_state'
HDRTEST drivers/gpu/drm/i915/gt/intel_rc6_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.o
HDRTEST drivers/gpu/drm/i915/gt/intel_context_param.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gpu_commands.h
../drivers/gpu/drm/i915/gt/uc/intel_guc.h:274: warning: Function parameter or member 'dbgfs_node' not described in 'intel_guc'
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_user.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_irq.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gsc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_powertune.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_thermal.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu10_hwmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_psm.o
HDRTEST drivers/gpu/drm/i915/gt/intel_rps.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.o
HDRTEST drivers/gpu/drm/i915/gt/selftest_llc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_processpptables.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.o
HDRTEST drivers/gpu/drm/i915/gt/gen6_ppgtt.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
HDRTEST drivers/gpu/drm/i915/gt/intel_migrate_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.o
HDRTEST drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
HDRTEST drivers/gpu/drm/i915/gt/intel_lrc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.o
HDRTEST drivers/gpu/drm/i915/gt/intel_lrc_reg.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_hwmgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_migrate.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_thermal.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.o
HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_overdriver.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.o
HDRTEST drivers/gpu/drm/i915/gt/mock_engine.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_processpptables.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_hwmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_powertune.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_thermal.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/common_baco.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_stats.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_baco.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_baco.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gtt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_baco.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ring.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf100.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_renderstate.h
HDRTEST drivers/gpu/drm/i915/gt/intel_sseu.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu9_baco.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/tonga_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/polaris_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/fiji_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ci_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_baco.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/gen2_engine_cs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/amd_powerplay.o
HDRTEST drivers/gpu/drm/i915/gvt/gvt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.o
HDRTEST drivers/gpu/drm/i915/gvt/trace.h
HDRTEST drivers/gpu/drm/i915/gvt/debug.h
HDRTEST drivers/gpu/drm/i915/gvt/edid.h
HDRTEST drivers/gpu/drm/i915/gvt/page_track.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.o
HDRTEST drivers/gpu/drm/i915/gvt/mmio.h
HDRTEST drivers/gpu/drm/i915/gvt/sched_policy.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/legacy_dpm.o
HDRTEST drivers/gpu/drm/i915/gvt/fb_decoder.h
HDRTEST drivers/gpu/drm/i915/gvt/cmd_parser.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.o
HDRTEST drivers/gpu/drm/i915/gvt/dmabuf.h
../drivers/gpu/drm/i915/gt/intel_gtt.h:515: warning: Function parameter or member 'vm' not described in 'i915_vm_resv_put'
../drivers/gpu/drm/i915/gt/intel_gtt.h:515: warning: Excess function parameter 'resv' description in 'i915_vm_resv_put'
HDRTEST drivers/gpu/drm/i915/gvt/mmio_context.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_dpm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_smc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_dpm.o
HDRTEST drivers/gpu/drm/i915/gvt/display.h
HDRTEST drivers/gpu/drm/i915/gvt/gtt.h
HDRTEST drivers/gpu/drm/i915/gvt/scheduler.h
HDRTEST drivers/gpu/drm/i915/gvt/reg.h
HDRTEST drivers/gpu/drm/i915/gvt/execlist.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.o
HDRTEST drivers/gpu/drm/i915/gvt/interrupt.h
HDRTEST drivers/gpu/drm/i915/i915_active.h
../drivers/gpu/drm/i915/gt/intel_engine_types.h:293: warning: Function parameter or member 'preempt_hang' not described in 'intel_engine_execlists'
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/base.o
HDRTEST drivers/gpu/drm/i915/i915_active_types.h
HDRTEST drivers/gpu/drm/i915/i915_cmd_parser.h
HDRTEST drivers/gpu/drm/i915/i915_config.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_smc.o
HDRTEST drivers/gpu/drm/i915/i915_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.o
HDRTEST drivers/gpu/drm/i915/i915_debugfs_params.h
HDRTEST drivers/gpu/drm/i915/i915_deps.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_pm.o
HDRTEST drivers/gpu/drm/i915/i915_driver.h
HDRTEST drivers/gpu/drm/i915/i915_drm_client.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.o
HDRTEST drivers/gpu/drm/i915/i915_drv.h
HDRTEST drivers/gpu/drm/i915/i915_file_private.h
HDRTEST drivers/gpu/drm/i915/i915_fixed.h
HDRTEST drivers/gpu/drm/i915/i915_gem.h
HDRTEST drivers/gpu/drm/i915/i915_gem_evict.h
HDRTEST drivers/gpu/drm/i915/i915_gem_gtt.h
HDRTEST drivers/gpu/drm/i915/i915_gem_ww.h
HDRTEST drivers/gpu/drm/i915/i915_getparam.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.o
HDRTEST drivers/gpu/drm/i915/i915_gpu_error.h
HDRTEST drivers/gpu/drm/i915/i915_hwmon.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crtc.o
HDRTEST drivers/gpu/drm/i915/i915_ioc32.h
HDRTEST drivers/gpu/drm/i915/i915_ioctl.h
HDRTEST drivers/gpu/drm/i915/i915_iosf_mbi.h
HDRTEST drivers/gpu/drm/i915/i915_irq.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/base.o
HDRTEST drivers/gpu/drm/i915/i915_memcpy.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.o
HDRTEST drivers/gpu/drm/i915/i915_mitigations.h
HDRTEST drivers/gpu/drm/i915/i915_mm.h
HDRTEST drivers/gpu/drm/i915/i915_params.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_color.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/uvfn.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/tu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_services.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/ga100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.o
HDRTEST drivers/gpu/drm/i915/i915_pci.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.o
HDRTEST drivers/gpu/drm/i915/i915_perf.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.o
HDRTEST drivers/gpu/drm/i915/i915_perf_oa_regs.h
HDRTEST drivers/gpu/drm/i915/i915_perf_types.h
HDRTEST drivers/gpu/drm/i915/i915_pmu.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.o
HDRTEST drivers/gpu/drm/i915/i915_priolist_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crc.o
HDRTEST drivers/gpu/drm/i915/i915_pvinfo.h
../drivers/gpu/drm/i915/i915_active.h:66: warning: Function parameter or member 'active' not described in '__i915_active_fence_init'
../drivers/gpu/drm/i915/i915_active.h:66: warning: Function parameter or member 'fence' not described in '__i915_active_fence_init'
../drivers/gpu/drm/i915/i915_active.h:66: warning: Function parameter or member 'fn' not described in '__i915_active_fence_init'
../drivers/gpu/drm/i915/i915_active.h:89: warning: Function parameter or member 'active' not described in 'i915_active_fence_set'
../drivers/gpu/drm/i915/i915_active.h:89: warning: Function parameter or member 'rq' not described in 'i915_active_fence_set'
../drivers/gpu/drm/i915/i915_active.h:102: warning: Function parameter or member 'active' not described in 'i915_active_fence_get'
../drivers/gpu/drm/i915/i915_active.h:122: warning: Function parameter or member 'active' not described in 'i915_active_fence_isset'
HDRTEST drivers/gpu/drm/i915/i915_query.h
HDRTEST drivers/gpu/drm/i915/i915_reg.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.o
HDRTEST drivers/gpu/drm/i915/i915_reg_defs.h
HDRTEST drivers/gpu/drm/i915/i915_request.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.o
HDRTEST drivers/gpu/drm/i915/i915_scatterlist.h
HDRTEST drivers/gpu/drm/i915/i915_scheduler.h
HDRTEST drivers/gpu/drm/i915/i915_scheduler_types.h
HDRTEST drivers/gpu/drm/i915/i915_selftest.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/conversion.o
HDRTEST drivers/gpu/drm/i915/i915_suspend.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/fixpt31_32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/vector.o
HDRTEST drivers/gpu/drm/i915/i915_sw_fence.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/falcon.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/xtensa.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.o
../drivers/gpu/drm/i915/i915_pmu.h:21: warning: cannot understand function prototype: 'enum i915_pmu_tracked_events '
../drivers/gpu/drm/i915/i915_pmu.h:32: warning: cannot understand function prototype: 'enum '
../drivers/gpu/drm/i915/i915_pmu.h:41: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* How many different events we track in the global PMU mask.
HDRTEST drivers/gpu/drm/i915/i915_sw_fence_work.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.o
HDRTEST drivers/gpu/drm/i915/i915_switcheroo.h
HDRTEST drivers/gpu/drm/i915/i915_syncmap.h
HDRTEST drivers/gpu/drm/i915/i915_sysfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.o
HDRTEST drivers/gpu/drm/i915/i915_tasklet.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.o
HDRTEST drivers/gpu/drm/i915/i915_trace.h
HDRTEST drivers/gpu/drm/i915/i915_ttm_buddy_manager.h
HDRTEST drivers/gpu/drm/i915/i915_user_extensions.h
HDRTEST drivers/gpu/drm/i915/i915_utils.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_interface.o
HDRTEST drivers/gpu/drm/i915/i915_vgpu.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.o
../drivers/gpu/drm/i915/i915_scatterlist.h:160: warning: Incorrect use of kernel-doc format: * release() - Free the memory of the struct i915_refct_sgt
../drivers/gpu/drm/i915/i915_scatterlist.h:164: warning: Function parameter or member 'release' not described in 'i915_refct_sgt_ops'
../drivers/gpu/drm/i915/i915_scatterlist.h:187: warning: Function parameter or member 'rsgt' not described in 'i915_refct_sgt_put'
../drivers/gpu/drm/i915/i915_scatterlist.h:198: warning: Function parameter or member 'rsgt' not described in 'i915_refct_sgt_get'
../drivers/gpu/drm/i915/i915_scatterlist.h:214: warning: Function parameter or member 'rsgt' not described in '__i915_refct_sgt_init'
HDRTEST drivers/gpu/drm/i915/i915_vma.h
../drivers/gpu/drm/i915/i915_request.h:176: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Request queue structure.
../drivers/gpu/drm/i915/i915_request.h:477: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Returns true if seq1 is later than seq2.
HDRTEST drivers/gpu/drm/i915/i915_vma_resource.h
HDRTEST drivers/gpu/drm/i915/i915_vma_types.h
HDRTEST drivers/gpu/drm/i915/intel_clock_gating.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.o
HDRTEST drivers/gpu/drm/i915/intel_device_info.h
HDRTEST drivers/gpu/drm/i915/intel_gvt.h
HDRTEST drivers/gpu/drm/i915/intel_mchbar_regs.h
HDRTEST drivers/gpu/drm/i915/intel_memory_region.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.o
HDRTEST drivers/gpu/drm/i915/intel_pci_config.h
HDRTEST drivers/gpu/drm/i915/intel_pcode.h
HDRTEST drivers/gpu/drm/i915/intel_region_ttm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_common.o
HDRTEST drivers/gpu/drm/i915/intel_runtime_pm.h
HDRTEST drivers/gpu/drm/i915/intel_sbi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table2.o
HDRTEST drivers/gpu/drm/i915/intel_step.h
HDRTEST drivers/gpu/drm/i915/intel_uncore.h
../drivers/gpu/drm/i915/i915_utils.h:284: warning: Function parameter or member 'OP' not described in '__wait_for'
../drivers/gpu/drm/i915/i915_utils.h:284: warning: Function parameter or member 'COND' not described in '__wait_for'
../drivers/gpu/drm/i915/i915_utils.h:284: warning: Function parameter or member 'US' not described in '__wait_for'
../drivers/gpu/drm/i915/i915_utils.h:284: warning: Function parameter or member 'Wmin' not described in '__wait_for'
../drivers/gpu/drm/i915/i915_utils.h:284: warning: Function parameter or member 'Wmax' not described in '__wait_for'
HDRTEST drivers/gpu/drm/i915/intel_wakeref.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper2.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/ga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce60/command_table_helper_dce60.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/base.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_session.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/pci.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_types.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.o
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
HDRTEST drivers/gpu/drm/i915/selftests/igt_live_test.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/user.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/base.o
HDRTEST drivers/gpu/drm/i915/selftests/igt_atomic.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_gem_device.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_drm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper_dce112.o
HDRTEST drivers/gpu/drm/i915/selftests/igt_reset.h
HDRTEST drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.o
../drivers/gpu/drm/i915/i915_vma_resource.h:91: warning: Incorrect use of kernel-doc format: * struct i915_vma_bindinfo - Information needed for async bind
../drivers/gpu/drm/i915/i915_vma_resource.h:129: warning: Function parameter or member 'wakeref' not described in 'i915_vma_resource'
../drivers/gpu/drm/i915/i915_vma_resource.h:129: warning: Function parameter or member 'bi' not described in 'i915_vma_resource'
HDRTEST drivers/gpu/drm/i915/selftests/lib_sw_fence.h
HDRTEST drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_uncore.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_gtt.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper2_dce112.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.o
HDRTEST drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dce_calcs.o
HDRTEST drivers/gpu/drm/i915/selftests/mock_request.h
HDRTEST drivers/gpu/drm/i915/selftests/i915_random.h
../drivers/gpu/drm/i915/pxp/intel_pxp_types.h:96: warning: Function parameter or member 'dev_link' not described in 'intel_pxp'
HDRTEST drivers/gpu/drm/i915/selftests/igt_spinner.h
HDRTEST drivers/gpu/drm/i915/selftests/librapl.h
HDRTEST drivers/gpu/drm/i915/selftests/mock_region.h
HDRTEST drivers/gpu/drm/i915/selftests/i915_live_selftests.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.o
HDRTEST drivers/gpu/drm/i915/selftests/igt_mmap.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/custom_float.o
../drivers/gpu/drm/i915/i915_vma.h:145: warning: expecting prototype for i915_vma_offset(). Prototype was for i915_vma_size() instead
HDRTEST drivers/gpu/drm/i915/selftests/igt_flush_test.h
HDRTEST drivers/gpu/drm/i915/soc/intel_pch.h
HDRTEST drivers/gpu/drm/i915/soc/intel_dram.h
HDRTEST drivers/gpu/drm/i915/soc/intel_gmch.h
HDRTEST drivers/gpu/drm/i915/vlv_sideband.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/bw_fixed.o
HDRTEST drivers/gpu/drm/i915/vlv_sideband_reg.h
HDRTEST drivers/gpu/drm/i915/vlv_suspend.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_rq_dlg_helpers.o
LD [M] drivers/gpu/drm/i915/i915.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dml1_display_rq_dlg_calc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn10/dcn10_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_vba.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/head.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_rq_dlg_calc_21.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_rq_dlg_calc_30.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_rq_dlg_calc_31.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_mode_vba_314.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn321/dcn321_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn302/dcn302_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dsc/rc_calc_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calcs.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_math.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_auto.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce60/dce60_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce100/dce_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce110/dce110_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce112/dce112_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce120/dce120_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv2_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/user.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/dcn301_smu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chid.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/runq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.o
C
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 01/30] drm/xe/mtl: Disable media GT
2023-05-19 23:17 ` [Intel-xe] [PATCH v2 01/30] drm/xe/mtl: Disable media GT Matt Roper
@ 2023-05-20 5:50 ` Lucas De Marchi
0 siblings, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-20 5:50 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, May 19, 2023 at 04:17:58PM -0700, Matt Roper wrote:
>Xe incorrectly conflates the concept of 'tile' and 'GT.' Since MTL's
>media support is not yet functioning properly, let's just disable it
>completely for now while we fix the fundamental driver design. Support
>for media GTs on platforms like MTL will be re-added later.
>
>v2:
> - Drop some unrelated code cleanup that didn't belong in this patch.
> (Lucas)
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 06/30] fixup! drm/xe/display: Implement display support
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 06/30] fixup! drm/xe/display: Implement display support Matt Roper
@ 2023-05-20 5:52 ` Lucas De Marchi
0 siblings, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-20 5:52 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
On Fri, May 19, 2023 at 04:18:03PM -0700, Matt Roper wrote:
>---
> drivers/gpu/drm/xe/display/ext/i915_irq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/xe/display/ext/i915_irq.c b/drivers/gpu/drm/xe/display/ext/i915_irq.c
>index a0f22bd52549..6235ff9dec36 100644
>--- a/drivers/gpu/drm/xe/display/ext/i915_irq.c
>+++ b/drivers/gpu/drm/xe/display/ext/i915_irq.c
>@@ -670,7 +670,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>
> void gen11_display_irq_handler(struct drm_i915_private *i915)
> {
>- void __iomem * const regs = to_gt(i915)->mmio.regs;
>+ void __iomem * const regs = xe_device_get_root_tile(i915)->mmio.regs;
> const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
>
> /*
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 25/30] drm/xe: Invalidate TLB on all affected GTs during GGTT updates
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 25/30] drm/xe: Invalidate TLB on all affected GTs during GGTT updates Matt Roper
@ 2023-05-22 9:02 ` Das, Nirmoy
0 siblings, 0 replies; 54+ messages in thread
From: Das, Nirmoy @ 2023-05-22 9:02 UTC (permalink / raw)
To: Matt Roper, intel-xe
On 5/20/2023 1:18 AM, Matt Roper wrote:
> The GGTT is part of the tile and is shared by the primary and media GTs
> on platforms with a standalone media architecture. However each of
> these GTs has its own TLBs caching the page table lookups, and each
> needs to be invalidated separately.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> drivers/gpu/drm/xe/xe_ggtt.c | 16 ++++++++++------
> 1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 7c87623ef5c5..31f958613c2f 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -188,13 +188,10 @@ int xe_ggtt_init(struct xe_ggtt *ggtt)
> #define PVC_GUC_TLB_INV_DESC1 XE_REG(0xcf80)
> #define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
>
> -void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
> +static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)
> {
> - /*
> - * TODO: Loop over each GT in tile once media GT support is
> - * re-added
> - */
> - struct xe_gt *gt = ggtt->tile->primary_gt;
> + if (!gt)
> + return;
>
> /* TODO: vfunc for GuC vs. non-GuC */
>
> @@ -219,6 +216,13 @@ void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
> }
> }
>
> +void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
> +{
> + /* Each GT in a tile has its own TLB to cache GGTT lookups */
> + ggtt_invalidate_gt_tlb(ggtt->tile->primary_gt);
> + ggtt_invalidate_gt_tlb(ggtt->tile->media_gt);
> +}
> +
> void xe_ggtt_printk(struct xe_ggtt *ggtt, const char *prefix)
> {
> u64 addr, scratch_pte;
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 14/30] drm/xe: Clarify 'gt' retrieval for primary tile
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 14/30] drm/xe: Clarify 'gt' retrieval for primary tile Matt Roper
@ 2023-05-22 11:47 ` Das, Nirmoy
2023-05-26 21:33 ` Lucas De Marchi
1 sibling, 0 replies; 54+ messages in thread
From: Das, Nirmoy @ 2023-05-22 11:47 UTC (permalink / raw)
To: Matt Roper, intel-xe
On 5/20/2023 1:18 AM, Matt Roper wrote:
> There are a bunch of places in the driver where we need to perform
> non-GT MMIO against the platform's primary tile (display code, top-level
> interrupt enable/disable, driver initialization, etc.). Rename
> 'to_gt()' to 'xe_primary_mmio_gt()' to clarify that we're trying to get
> a primary MMIO handle for these top-level operations.
>
> In the future we need to move away from xe_gt as the target for MMIO
> operations (most of which are completely unrelated to GT).
>
> v2:
> - s/xe_primary_mmio_gt/xe_root_mmio_gt/ for more consistency with how
> we refer to tile 0. (Lucas)
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h | 2 +-
> drivers/gpu/drm/xe/xe_device.c | 2 +-
> drivers/gpu/drm/xe/xe_device.h | 11 +++++++++--
> drivers/gpu/drm/xe/xe_irq.c | 6 +++---
> drivers/gpu/drm/xe/xe_mmio.c | 8 ++++----
> drivers/gpu/drm/xe/xe_query.c | 2 +-
> drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 4 ++--
> 7 files changed, 21 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> index 14f195fe275d..fae6213d26f1 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> @@ -14,7 +14,7 @@ static inline struct xe_gt *__fake_uncore_to_gt(struct fake_uncore *uncore)
> {
> struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
>
> - return to_gt(xe);
> + return xe_root_mmio_gt(xe);
> }
>
> static inline u32 intel_uncore_read(struct fake_uncore *uncore,
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index af165ad6f197..43a585b67581 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -394,7 +394,7 @@ static void device_kill_persistent_engines(struct xe_device *xe,
>
> void xe_device_wmb(struct xe_device *xe)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
>
> wmb();
> if (IS_DGFX(xe))
> diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
> index 745dbb16d417..42bc566c53d8 100644
> --- a/drivers/gpu/drm/xe/xe_device.h
> +++ b/drivers/gpu/drm/xe/xe_device.h
> @@ -66,9 +66,16 @@ static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
> }
>
> /*
> - * FIXME: Placeholder until multi-gt lands. Once that lands, kill this function.
> + * Provide a GT structure suitable for performing non-GT MMIO operations against
> + * the primary tile. Primarily intended for early tile initialization, display
> + * handling, top-most interrupt enable/disable, etc. Since anything using the
> + * MMIO handle returned by this function doesn't need GSI offset translation,
> + * we'll return the primary GT from the root tile.
> + *
> + * FIXME: Fix the driver design so that 'gt' isn't the target of all MMIO
> + * operations.
> */
> -static inline struct xe_gt *to_gt(struct xe_device *xe)
> +static inline struct xe_gt *xe_root_mmio_gt(struct xe_device *xe)
> {
> return &xe_device_get_root_tile(xe)->primary_gt;
> }
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 5be31855d789..628057497cd5 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -285,7 +285,7 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> static irqreturn_t xelp_irq_handler(int irq, void *arg)
> {
> struct xe_device *xe = arg;
> - struct xe_gt *gt = xe_device_get_gt(xe, 0); /* Only 1 GT here */
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> u32 master_ctl, gu_misc_iir;
> long unsigned int intr_dw[2];
> u32 identity[32];
> @@ -311,7 +311,7 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>
> static u32 dg1_intr_disable(struct xe_device *xe)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> u32 val;
>
> /* First disable interrupts */
> @@ -329,7 +329,7 @@ static u32 dg1_intr_disable(struct xe_device *xe)
>
> static void dg1_intr_enable(struct xe_device *xe, bool stall)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
>
> xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
> if (stall)
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 17b3a9880409..32427c10ba8a 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -150,7 +150,7 @@ static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
>
> int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_size)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> int err;
> u32 reg_val;
> @@ -287,7 +287,7 @@ int xe_mmio_probe_vram(struct xe_device *xe)
>
> static void xe_mmio_probe_tiles(struct xe_device *xe)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> u32 mtcfg;
> u8 adj_tile_count;
> u8 id;
> @@ -339,7 +339,7 @@ static void mmio_fini(struct drm_device *drm, void *arg)
> int xe_mmio_init(struct xe_device *xe)
> {
> struct xe_tile *root_tile = xe_device_get_root_tile(xe);
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> const int mmio_bar = 0;
> int err;
>
> @@ -398,7 +398,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> struct xe_device *xe = to_xe_device(dev);
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> struct drm_xe_mmio *args = data;
> unsigned int bits_flag, bytes;
> struct xe_reg reg;
> diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
> index c81652d7f4ec..49fff425adcd 100644
> --- a/drivers/gpu/drm/xe/xe_query.c
> +++ b/drivers/gpu/drm/xe/xe_query.c
> @@ -259,7 +259,7 @@ static int query_gts(struct xe_device *xe, struct drm_xe_device_query *query)
> static int query_hwconfig(struct xe_device *xe,
> struct drm_xe_device_query *query)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> size_t size = xe_guc_hwconfig_size(>->uc.guc);
> void __user *query_ptr = u64_to_user_ptr(query->data);
> void *hwconfig;
> diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> index a3855870321f..012474a6c387 100644
> --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> @@ -54,7 +54,7 @@ bool xe_ttm_stolen_cpu_access_needs_ggtt(struct xe_device *xe)
> static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
> {
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> - struct xe_gt *gt = to_gt(xe);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> u64 vram_size, stolen_size;
> int err;
>
> @@ -88,7 +88,7 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr
> u32 stolen_size;
> u32 ggc, gms;
>
> - ggc = xe_mmio_read32(to_gt(xe), GGC);
> + ggc = xe_mmio_read32(xe_root_mmio_gt(xe), GGC);
>
> /* check GGMS, should be fixed 0x3 (8MB) */
> if (drm_WARN_ON(&xe->drm, (ggc & GGMS_MASK) != GGMS_MASK))
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 26/30] drm/xe/tlb: Obtain forcewake when doing GGTT TLB invalidations
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 26/30] drm/xe/tlb: Obtain forcewake when doing GGTT TLB invalidations Matt Roper
@ 2023-05-22 11:47 ` Das, Nirmoy
0 siblings, 0 replies; 54+ messages in thread
From: Das, Nirmoy @ 2023-05-22 11:47 UTC (permalink / raw)
To: Matt Roper, intel-xe; +Cc: Lucas De Marchi
On 5/20/2023 1:18 AM, Matt Roper wrote:
> Updates to the GGTT can happen when there are no in-flight jobs keeping
> the hardware awake. If the GT is powered down when invalidation is
> requested, we will not be able to communicate with the GuC (or MMIO) and
> the invalidation request will go missing. Explicitly grab GT forcewake
> to ensure the GT and GuC are powered up during the TLB invalidation.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> drivers/gpu/drm/xe/xe_ggtt.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 31f958613c2f..8f8d0f6a82cd 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -193,6 +193,13 @@ static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)
> if (!gt)
> return;
>
> + /*
> + * Invalidation can happen when there's no in-flight work keeping the
> + * GT awake. We need to explicitly grab forcewake to ensure the GT
> + * and GuC are accessible.
> + */
> + xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> +
> /* TODO: vfunc for GuC vs. non-GuC */
>
> if (gt->uc.guc.submission_state.enabled) {
> @@ -214,6 +221,8 @@ static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)
> xe_mmio_write32(gt, GUC_TLB_INV_CR,
> GUC_TLB_INV_CR_INVALIDATE);
> }
> +
> + xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> }
>
> void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 07/30] drm/xe: Move GGTT from GT to tile
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 07/30] drm/xe: Move GGTT from GT to tile Matt Roper
@ 2023-05-25 23:29 ` Lucas De Marchi
0 siblings, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-25 23:29 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, May 19, 2023 at 04:18:04PM -0700, Matt Roper wrote:
>The GGTT exists at the tile level. When a tile contains multiple GTs,
>they share the same GGTT.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/xe_bo.c | 6 ++--
> drivers/gpu/drm/xe/xe_bo_evict.c | 8 +++--
> drivers/gpu/drm/xe/xe_device_types.h | 8 +++++
> drivers/gpu/drm/xe/xe_ggtt.c | 30 ++++++++--------
> drivers/gpu/drm/xe/xe_ggtt.h | 6 ++--
> drivers/gpu/drm/xe/xe_ggtt_types.h | 2 +-
> drivers/gpu/drm/xe/xe_gt.c | 10 +-----
> drivers/gpu/drm/xe/xe_gt_debugfs.c | 2 +-
> drivers/gpu/drm/xe/xe_gt_types.h | 3 --
> drivers/gpu/drm/xe/xe_tile.c | 52 ++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_tile.h | 14 ++++++++
> 11 files changed, 104 insertions(+), 37 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/xe_tile.c
> create mode 100644 drivers/gpu/drm/xe/xe_tile.h
>
>diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
>index c82e995df779..ecc82fefdf4c 100644
>--- a/drivers/gpu/drm/xe/xe_bo.c
>+++ b/drivers/gpu/drm/xe/xe_bo.c
>@@ -958,7 +958,7 @@ static void xe_ttm_bo_destroy(struct ttm_buffer_object *ttm_bo)
> WARN_ON(!list_empty(&bo->vmas));
>
> if (bo->ggtt_node.size)
>- xe_ggtt_remove_bo(bo->gt->mem.ggtt, bo);
>+ xe_ggtt_remove_bo(gt_to_tile(bo->gt)->mem.ggtt, bo);
>
> if (bo->vm && xe_bo_is_user(bo))
> xe_vm_put(bo->vm);
>@@ -1235,10 +1235,10 @@ xe_bo_create_locked_range(struct xe_device *xe,
> XE_BUG_ON(!gt);
>
> if (flags & XE_BO_FIXED_PLACEMENT_BIT) {
>- err = xe_ggtt_insert_bo_at(gt->mem.ggtt, bo,
>+ err = xe_ggtt_insert_bo_at(gt_to_tile(gt)->mem.ggtt, bo,
> start + bo->size, U64_MAX);
> } else {
>- err = xe_ggtt_insert_bo(gt->mem.ggtt, bo);
>+ err = xe_ggtt_insert_bo(gt_to_tile(gt)->mem.ggtt, bo);
> }
> if (err)
> goto err_unlock_put_bo;
>diff --git a/drivers/gpu/drm/xe/xe_bo_evict.c b/drivers/gpu/drm/xe/xe_bo_evict.c
>index 6642c5f52009..a72963c54bf3 100644
>--- a/drivers/gpu/drm/xe/xe_bo_evict.c
>+++ b/drivers/gpu/drm/xe/xe_bo_evict.c
>@@ -149,9 +149,11 @@ int xe_bo_restore_kernel(struct xe_device *xe)
> }
>
> if (bo->flags & XE_BO_CREATE_GGTT_BIT) {
>- mutex_lock(&bo->gt->mem.ggtt->lock);
>- xe_ggtt_map_bo(bo->gt->mem.ggtt, bo);
>- mutex_unlock(&bo->gt->mem.ggtt->lock);
>+ struct xe_tile *tile = gt_to_tile(bo->gt);
>+
>+ mutex_lock(&tile->mem.ggtt->lock);
>+ xe_ggtt_map_bo(tile->mem.ggtt, bo);
>+ mutex_unlock(&tile->mem.ggtt->lock);
> }
>
> /*
>diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>index ea7143c04db9..cb4d0c2ea184 100644
>--- a/drivers/gpu/drm/xe/xe_device_types.h
>+++ b/drivers/gpu/drm/xe/xe_device_types.h
>@@ -54,6 +54,8 @@
> const struct xe_tile *: (const struct xe_device *)((tile__)->xe), \
> struct xe_tile *: (tile__)->xe)
>
>+struct xe_ggtt;
I think all fwd declarations should be at the top.
>+
> /**
> * struct xe_tile - hardware tile structure
> *
>@@ -97,6 +99,12 @@ struct xe_tile {
> /** @regs: pointer to tile's MMIO space (starting with registers) */
> void *regs;
> } mmio;
>+
>+ /** @mem: memory management info for tile */
>+ struct {
>+ /** @ggtt: Global graphics translation table */
>+ struct xe_ggtt *ggtt;
>+ } mem;
> };
>
> /**
>diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
>index 200976da3dc1..52d293d61cc0 100644
>--- a/drivers/gpu/drm/xe/xe_ggtt.c
>+++ b/drivers/gpu/drm/xe/xe_ggtt.c
>@@ -90,24 +90,19 @@ static void ggtt_fini_noalloc(struct drm_device *drm, void *arg)
> xe_bo_unpin_map_no_vm(ggtt->scratch);
> }
>
>-int xe_ggtt_init_noalloc(struct xe_gt *gt, struct xe_ggtt *ggtt)
>+int xe_ggtt_init_noalloc(struct xe_ggtt *ggtt)
> {
>- struct xe_device *xe = gt_to_xe(gt);
>- struct xe_tile *tile = gt_to_tile(gt);
>+ struct xe_device *xe = tile_to_xe(ggtt->tile);
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> unsigned int gsm_size;
>
>- XE_BUG_ON(xe_gt_is_media_type(gt));
>-
>- ggtt->gt = gt;
>-
> gsm_size = probe_gsm_size(pdev);
> if (gsm_size == 0) {
> drm_err(&xe->drm, "Hardware reported no preallocated GSM\n");
> return -ENOMEM;
> }
>
>- ggtt->gsm = tile->mmio.regs + SZ_8M;
>+ ggtt->gsm = ggtt->tile->mmio.regs + SZ_8M;
> ggtt->size = (gsm_size / 8) * (u64) XE_PAGE_SIZE;
>
> if (IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
>@@ -147,13 +142,14 @@ static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
> drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
> xe_ggtt_clear(ggtt, start, end - start);
>
>- xe_ggtt_invalidate(ggtt->gt);
>+ xe_ggtt_invalidate(ggtt);
> mutex_unlock(&ggtt->lock);
> }
>
>-int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
>+int xe_ggtt_init(struct xe_ggtt *ggtt)
> {
>- struct xe_device *xe = gt_to_xe(gt);
>+ struct xe_device *xe = tile_to_xe(ggtt->tile);
>+ struct xe_gt *gt = &ggtt->tile->primary_gt;
> unsigned int flags;
> int err;
>
>@@ -193,8 +189,14 @@ int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
> #define PVC_GUC_TLB_INV_DESC1 XE_REG(0xcf80)
> #define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
>
>-void xe_ggtt_invalidate(struct xe_gt *gt)
>+void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
> {
>+ /*
>+ * TODO: Loop over each GT in tile once media GT support is
>+ * re-added
>+ */
>+ struct xe_gt *gt = &ggtt->tile->primary_gt;
>+
> /* TODO: vfunc for GuC vs. non-GuC */
>
> if (gt->uc.guc.submission_state.enabled) {
>@@ -267,7 +269,7 @@ void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)
> xe_ggtt_set_pte(ggtt, start + offset, pte);
> }
>
>- xe_ggtt_invalidate(ggtt->gt);
>+ xe_ggtt_invalidate(ggtt);
> }
>
> static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,
>@@ -318,7 +320,7 @@ void xe_ggtt_remove_node(struct xe_ggtt *ggtt, struct drm_mm_node *node)
> drm_mm_remove_node(node);
> node->size = 0;
>
>- xe_ggtt_invalidate(ggtt->gt);
>+ xe_ggtt_invalidate(ggtt);
>
> mutex_unlock(&ggtt->lock);
> }
>diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
>index 333947100504..205a6d058bbd 100644
>--- a/drivers/gpu/drm/xe/xe_ggtt.h
>+++ b/drivers/gpu/drm/xe/xe_ggtt.h
>@@ -12,9 +12,9 @@ struct drm_printer;
>
> u64 xe_ggtt_pte_encode(struct xe_bo *bo, u64 bo_offset);
> void xe_ggtt_set_pte(struct xe_ggtt *ggtt, u64 addr, u64 pte);
>-void xe_ggtt_invalidate(struct xe_gt *gt);
>-int xe_ggtt_init_noalloc(struct xe_gt *gt, struct xe_ggtt *ggtt);
>-int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt);
>+void xe_ggtt_invalidate(struct xe_ggtt *ggtt);
>+int xe_ggtt_init_noalloc(struct xe_ggtt *ggtt);
>+int xe_ggtt_init(struct xe_ggtt *ggtt);
> void xe_ggtt_printk(struct xe_ggtt *ggtt, const char *prefix);
>
> int xe_ggtt_insert_special_node(struct xe_ggtt *ggtt, struct drm_mm_node *node,
>diff --git a/drivers/gpu/drm/xe/xe_ggtt_types.h b/drivers/gpu/drm/xe/xe_ggtt_types.h
>index ea70aaef4b31..d34b3e733945 100644
>--- a/drivers/gpu/drm/xe/xe_ggtt_types.h
>+++ b/drivers/gpu/drm/xe/xe_ggtt_types.h
>@@ -12,7 +12,7 @@ struct xe_bo;
> struct xe_gt;
>
> struct xe_ggtt {
>- struct xe_gt *gt;
>+ struct xe_tile *tile;
>
> u64 size;
>
>diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>index 80d42c7c7cfa..1c58a9aff2cb 100644
>--- a/drivers/gpu/drm/xe/xe_gt.c
>+++ b/drivers/gpu/drm/xe/xe_gt.c
>@@ -67,11 +67,6 @@ int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt)
> XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
>
> if (!xe_gt_is_media_type(gt)) {
>- gt->mem.ggtt = drmm_kzalloc(drm, sizeof(*gt->mem.ggtt),
>- GFP_KERNEL);
>- if (!gt->mem.ggtt)
>- return -ENOMEM;
>-
> gt->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*gt->mem.vram_mgr),
> GFP_KERNEL);
> if (!gt->mem.vram_mgr)
>@@ -80,7 +75,6 @@ int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt)
> } else {
> struct xe_gt *full_gt = xe_find_full_gt(gt);
>
>- gt->mem.ggtt = full_gt->mem.ggtt;
> gt->mem.vram_mgr = full_gt->mem.vram_mgr;
> }
>
>@@ -348,8 +342,6 @@ int xe_gt_init_noalloc(struct xe_gt *gt)
> if (err)
> goto err_force_wake;
>
>- err = xe_ggtt_init_noalloc(gt, gt->mem.ggtt);
>-
> err_force_wake:
> err2 = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> XE_WARN_ON(err2);
>@@ -370,7 +362,7 @@ static int gt_fw_domain_init(struct xe_gt *gt)
> xe_pat_init(gt);
>
> if (!xe_gt_is_media_type(gt)) {
>- err = xe_ggtt_init(gt, gt->mem.ggtt);
>+ err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt);
> if (err)
> goto err_force_wake;
> }
>diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
>index 8bf441e850a0..a0f633109124 100644
>--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
>+++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
>@@ -97,7 +97,7 @@ static int ggtt(struct seq_file *m, void *data)
> struct xe_gt *gt = node_to_gt(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
>
>- return xe_ggtt_dump(gt->mem.ggtt, &p);
>+ return xe_ggtt_dump(gt_to_tile(gt)->mem.ggtt, &p);
> }
>
> static int register_save_restore(struct seq_file *m, void *data)
>diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
>index 6f4243443d04..e910ec1b8dd3 100644
>--- a/drivers/gpu/drm/xe/xe_gt_types.h
>+++ b/drivers/gpu/drm/xe/xe_gt_types.h
>@@ -14,7 +14,6 @@
> #include "xe_uc_types.h"
>
> struct xe_engine_ops;
>-struct xe_ggtt;
> struct xe_migrate;
> struct xe_ring_ops;
> struct xe_ttm_gtt_mgr;
>@@ -174,8 +173,6 @@ struct xe_gt {
> } vram;
> /** @vram_mgr: VRAM TTM manager */
> struct xe_ttm_vram_mgr *vram_mgr;
>- /** @ggtt: Global graphics translation table */
>- struct xe_ggtt *ggtt;
> } mem;
>
> /** @reset: state for GT resets */
>diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
>new file mode 100644
>index 000000000000..7ef594f301ca
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_tile.c
>@@ -0,0 +1,52 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2023 Intel Corporation
>+ */
>+
>+#include <drm/drm_managed.h>
>+
>+#include "xe_device.h"
>+#include "xe_ggtt.h"
>+#include "xe_tile.h"
>+#include "xe_ttm_vram_mgr.h"
>+
>+/**
>+ * xe_tile_alloc - Perform per-tile memory allocation
>+ * @tile: Tile to perform allocations for
>+ *
>+ * Allocates various per-tile data structures using DRM-managed allocations.
>+ * Does not touch the hardware.
>+ *
>+ * Returns -ENOMEM if allocations fail, otherwise 0.
>+ */
>+int xe_tile_alloc(struct xe_tile *tile)
>+{
>+ struct drm_device *drm = &tile_to_xe(tile)->drm;
>+
>+ tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt),
>+ GFP_KERNEL);
>+ if (!tile->mem.ggtt)
>+ return -ENOMEM;
>+ tile->mem.ggtt->tile = tile;
>+
>+ return 0;
>+}
>+
>+/**
>+ * xe_tile_init_noalloc - Init tile up to the point where allocations can happen.
>+ * @tile: The tile to initialize.
>+ *
>+ * This function prepares the tile to allow memory allocations to VRAM, but is
>+ * not allowed to allocate memory itself. This state is useful for display
>+ * readout, because the inherited display framebuffer will otherwise be
>+ * overwritten as it is usually put at the start of VRAM.
>+ *
>+ * Note that since this is tile initialization, it should not perform any
>+ * GT-specific operations, and thus does not need to hold GT forcewake.
>+ *
>+ * Returns: 0 on success, negative error code on error.
>+ */
>+int xe_tile_init_noalloc(struct xe_tile *tile)
>+{
>+ return xe_ggtt_init_noalloc(tile->mem.ggtt);
>+}
>diff --git a/drivers/gpu/drm/xe/xe_tile.h b/drivers/gpu/drm/xe/xe_tile.h
>new file mode 100644
>index 000000000000..49b64d83ce91
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_tile.h
>@@ -0,0 +1,14 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2023 Intel Corporation
>+ */
>+
>+#ifndef __XE_TILE_H__
>+#define __XE_TILE_H__
we use 1 _ only
jus cosmetic issues, otherwise LGTM
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>+
>+struct xe_tile;
>+
>+int xe_tile_alloc(struct xe_tile *tile);
>+int xe_tile_init_noalloc(struct xe_tile *tile);
>+
>+#endif
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 08/30] fixup! drm/xe/display: Implement display support
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 08/30] fixup! drm/xe/display: Implement display support Matt Roper
@ 2023-05-25 23:30 ` Lucas De Marchi
0 siblings, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-25 23:30 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
On Fri, May 19, 2023 at 04:18:05PM -0700, Matt Roper wrote:
>---
> drivers/gpu/drm/xe/display/xe_fb_pin.c | 6 +++---
> drivers/gpu/drm/xe/display/xe_plane_initial.c | 5 +++--
> 2 files changed, 6 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>index c7c4df18e439..27e4d29aa73d 100644
>--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>@@ -123,7 +123,7 @@ static int __xe_pin_fb_vma_ggtt(struct intel_framebuffer *fb,
> {
> struct xe_bo *bo = intel_fb_obj(&fb->base);
> struct xe_device *xe = to_xe_device(fb->base.dev);
>- struct xe_ggtt *ggtt = to_gt(xe)->mem.ggtt;
>+ struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
> u32 align;
> int ret;
>
>@@ -173,7 +173,7 @@ static int __xe_pin_fb_vma_ggtt(struct intel_framebuffer *fb,
> rot_info->plane[i].dst_stride);
> }
>
>- xe_ggtt_invalidate(to_gt(xe));
>+ xe_ggtt_invalidate(ggtt);
>
> out:
> mutex_unlock(&ggtt->lock);
>@@ -238,7 +238,7 @@ static struct i915_vma *__xe_pin_fb_vma(struct intel_framebuffer *fb,
> static void __xe_unpin_fb_vma(struct i915_vma *vma)
> {
> struct xe_device *xe = to_xe_device(vma->bo->ttm.base.dev);
>- struct xe_ggtt *ggtt = to_gt(xe)->mem.ggtt;
>+ struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
>
> if (vma->dpt)
> xe_bo_unpin_map_no_vm(vma->dpt);
>diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
>index 34ae461865a7..41540b27775c 100644
>--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
>+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
>@@ -52,6 +52,7 @@ initial_plane_bo(struct xe_device *xe,
> struct intel_initial_plane_config *plane_config)
> {
> struct xe_gt *gt0 = xe_device_get_gt(xe, 0);
>+ struct xe_tile *tile0 = xe_device_get_root_tile(xe);
> struct xe_bo *bo;
> resource_size_t phys_base;
> u32 base, size, flags;
>@@ -64,7 +65,7 @@ initial_plane_bo(struct xe_device *xe,
>
> base = round_down(plane_config->base, page_size);
> if (IS_DGFX(xe)) {
>- u64 __iomem *gte = gt0->mem.ggtt->gsm;
>+ u64 __iomem *gte = tile0->mem.ggtt->gsm;
> u64 pte;
>
> gte += base / XE_PAGE_SIZE;
>@@ -115,7 +116,7 @@ initial_plane_bo(struct xe_device *xe,
> page_size);
> size -= base;
>
>- bo = xe_bo_create_pin_map_at(xe, gt0, NULL, size, phys_base,
>+ bo = xe_bo_create_pin_map_at(xe, &tile0->primary_gt, NULL, size, phys_base,
> ttm_bo_type_kernel, flags);
> if (IS_ERR(bo)) {
> drm_dbg(&xe->drm,
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 09/30] drm/xe: Move VRAM from GT to tile
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 09/30] drm/xe: Move VRAM from GT to tile Matt Roper
@ 2023-05-26 21:11 ` Lucas De Marchi
0 siblings, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-26 21:11 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, May 19, 2023 at 04:18:06PM -0700, Matt Roper wrote:
>On platforms with VRAM, the VRAM is associated with the tile, not the
>GT.
>
>v2:
> - Unsquash the GGTT handling back into its own patch.
> - Fix kunit test build
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/tests/xe_bo.c | 6 +-
> drivers/gpu/drm/xe/xe_bo.c | 44 ++++++------
> drivers/gpu/drm/xe/xe_bo.h | 4 +-
> drivers/gpu/drm/xe/xe_device.c | 14 ++--
> drivers/gpu/drm/xe/xe_device_types.h | 28 ++++++++
> drivers/gpu/drm/xe/xe_gt.c | 83 ++--------------------
> drivers/gpu/drm/xe/xe_gt_pagefault.c | 6 +-
> drivers/gpu/drm/xe/xe_gt_types.h | 35 ---------
> drivers/gpu/drm/xe/xe_irq.c | 2 +-
> drivers/gpu/drm/xe/xe_mmio.c | 45 ++++++------
> drivers/gpu/drm/xe/xe_pci.c | 2 -
> drivers/gpu/drm/xe/xe_pt.c | 4 +-
> drivers/gpu/drm/xe/xe_query.c | 4 +-
> drivers/gpu/drm/xe/xe_res_cursor.h | 2 +-
> drivers/gpu/drm/xe/xe_tile.c | 33 ++++++++-
> drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | 16 ++---
> drivers/gpu/drm/xe/xe_ttm_vram_mgr.h | 4 +-
> drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h | 6 +-
> 19 files changed, 147 insertions(+), 192 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>index cd1614b68734..94ed64be86e3 100644
>--- a/drivers/gpu/drm/xe/Makefile
>+++ b/drivers/gpu/drm/xe/Makefile
>@@ -84,6 +84,7 @@ xe-y += xe_bb.o \
> xe_sched_job.o \
> xe_step.o \
> xe_sync.o \
>+ xe_tile.o \
> xe_trace.o \
> xe_ttm_sys_mgr.o \
> xe_ttm_stolen_mgr.o \
>diff --git a/drivers/gpu/drm/xe/tests/xe_bo.c b/drivers/gpu/drm/xe/tests/xe_bo.c
>index 8f3afdc6cca6..6235a6c73a06 100644
>--- a/drivers/gpu/drm/xe/tests/xe_bo.c
>+++ b/drivers/gpu/drm/xe/tests/xe_bo.c
>@@ -115,9 +115,9 @@ static void ccs_test_run_gt(struct xe_device *xe, struct xe_gt *gt,
> int ret;
>
> /* TODO: Sanity check */
>- vram_bit = XE_BO_CREATE_VRAM0_BIT << gt->info.vram_id;
>+ vram_bit = XE_BO_CREATE_VRAM0_BIT << gt_to_tile(gt)->id;
> kunit_info(test, "Testing gt id %u vram id %u\n", gt->info.id,
>- gt->info.vram_id);
>+ gt_to_tile(gt)->id);
>
> bo = xe_bo_create_locked(xe, NULL, NULL, SZ_1M, ttm_bo_type_device,
> vram_bit);
>@@ -179,7 +179,7 @@ static int evict_test_run_gt(struct xe_device *xe, struct xe_gt *gt, struct kuni
> int err, i;
>
> kunit_info(test, "Testing device %s gt id %u vram id %u\n",
>- dev_name(xe->drm.dev), gt->info.id, gt->info.vram_id);
>+ dev_name(xe->drm.dev), gt->info.id, gt_to_tile(gt)->id);
>
> for (i = 0; i < 2; ++i) {
> xe_vm_lock(vm, &ww, 0, false);
>diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
>index ecc82fefdf4c..5dbca5bbca8f 100644
>--- a/drivers/gpu/drm/xe/xe_bo.c
>+++ b/drivers/gpu/drm/xe/xe_bo.c
>@@ -71,25 +71,25 @@ static bool xe_bo_is_user(struct xe_bo *bo)
> return bo->flags & XE_BO_CREATE_USER_BIT;
> }
>
>-static struct xe_gt *
>-mem_type_to_gt(struct xe_device *xe, u32 mem_type)
>+static struct xe_tile *
>+mem_type_to_tile(struct xe_device *xe, u32 mem_type)
> {
> XE_BUG_ON(mem_type != XE_PL_STOLEN && !mem_type_is_vram(mem_type));
>
>- return xe_device_get_gt(xe, mem_type == XE_PL_STOLEN ? 0 : (mem_type - XE_PL_VRAM0));
>+ return &xe->tiles[mem_type == XE_PL_STOLEN ? 0 : (mem_type - XE_PL_VRAM0)];
> }
>
> /**
>- * xe_bo_to_gt() - Get a GT from a BO's memory location
>+ * xe_bo_to_tile() - Get a tile from a BO's memory location
> * @bo: The buffer object
> *
>- * Get a GT from a BO's memory location, should be called on BOs in VRAM only.
>+ * Get a tile from a BO's memory location, should be called on BOs in VRAM only.
> *
>- * Return: xe_gt object which is closest to the BO
>+ * Return: xe_tile object which is closest to the BO
> */
>-struct xe_gt *xe_bo_to_gt(struct xe_bo *bo)
>+struct xe_tile *xe_bo_to_tile(struct xe_bo *bo)
> {
>- return mem_type_to_gt(xe_bo_device(bo), bo->ttm.resource->mem_type);
>+ return mem_type_to_tile(xe_bo_device(bo), bo->ttm.resource->mem_type);
> }
>
> static void try_add_system(struct xe_bo *bo, struct ttm_place *places,
>@@ -109,9 +109,9 @@ static void try_add_system(struct xe_bo *bo, struct ttm_place *places,
> static void add_vram(struct xe_device *xe, struct xe_bo *bo,
> struct ttm_place *places, u32 bo_flags, u32 mem_type, u32 *c)
> {
>- struct xe_gt *gt = mem_type_to_gt(xe, mem_type);
>+ struct xe_tile *tile = mem_type_to_tile(xe, mem_type);
>
>- XE_BUG_ON(!gt->mem.vram.size);
>+ XE_BUG_ON(!tile->mem.vram.size);
>
> places[*c] = (struct ttm_place) {
> .mem_type = mem_type,
>@@ -356,7 +356,7 @@ static int xe_ttm_io_mem_reserve(struct ttm_device *bdev,
> struct ttm_resource *mem)
> {
> struct xe_device *xe = ttm_to_xe_device(bdev);
>- struct xe_gt *gt;
>+ struct xe_tile *tile;
>
> switch (mem->mem_type) {
> case XE_PL_SYSTEM:
>@@ -364,15 +364,15 @@ static int xe_ttm_io_mem_reserve(struct ttm_device *bdev,
> return 0;
> case XE_PL_VRAM0:
> case XE_PL_VRAM1:
>- gt = mem_type_to_gt(xe, mem->mem_type);
>+ tile = mem_type_to_tile(xe, mem->mem_type);
> mem->bus.offset = mem->start << PAGE_SHIFT;
>
>- if (gt->mem.vram.mapping &&
>+ if (tile->mem.vram.mapping &&
> mem->placement & TTM_PL_FLAG_CONTIGUOUS)
>- mem->bus.addr = (u8 *)gt->mem.vram.mapping +
>+ mem->bus.addr = (u8 *)tile->mem.vram.mapping +
> mem->bus.offset;
>
>- mem->bus.offset += gt->mem.vram.io_start;
>+ mem->bus.offset += tile->mem.vram.io_start;
> mem->bus.is_iomem = true;
>
> #if !defined(CONFIG_X86)
>@@ -632,9 +632,9 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
> if (bo->gt)
> gt = bo->gt;
> else if (resource_is_vram(new_mem))
>- gt = mem_type_to_gt(xe, new_mem->mem_type);
>+ gt = &mem_type_to_tile(xe, new_mem->mem_type)->primary_gt;
> else if (resource_is_vram(old_mem))
>- gt = mem_type_to_gt(xe, old_mem->mem_type);
>+ gt = &mem_type_to_tile(xe, old_mem->mem_type)->primary_gt;
>
> XE_BUG_ON(!gt);
> XE_BUG_ON(!gt->migrate);
>@@ -658,7 +658,7 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
>
> /* Create a new VMAP once kernel BO back in VRAM */
> if (!ret && resource_is_vram(new_mem)) {
>- void *new_addr = gt->mem.vram.mapping +
>+ void *new_addr = gt_to_tile(gt)->mem.vram.mapping +
> (new_mem->start << PAGE_SHIFT);
>
> if (XE_WARN_ON(new_mem->start == XE_BO_INVALID_OFFSET)) {
>@@ -830,14 +830,14 @@ static unsigned long xe_ttm_io_mem_pfn(struct ttm_buffer_object *ttm_bo,
> {
> struct xe_device *xe = ttm_to_xe_device(ttm_bo->bdev);
> struct xe_bo *bo = ttm_to_xe_bo(ttm_bo);
>- struct xe_gt *gt = mem_type_to_gt(xe, ttm_bo->resource->mem_type);
>+ struct xe_tile *tile = mem_type_to_tile(xe, ttm_bo->resource->mem_type);
> struct xe_res_cursor cursor;
>
> if (ttm_bo->resource->mem_type == XE_PL_STOLEN)
> return xe_ttm_stolen_io_offset(bo, page_offset << PAGE_SHIFT) >> PAGE_SHIFT;
>
> xe_res_first(ttm_bo->resource, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
>- return (gt->mem.vram.io_start + cursor.start) >> PAGE_SHIFT;
>+ return (tile->mem.vram.io_start + cursor.start) >> PAGE_SHIFT;
> }
>
> static void __xe_bo_vunmap(struct xe_bo *bo);
>@@ -1338,12 +1338,12 @@ struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_gt *gt,
> uint64_t vram_region_io_offset(struct ttm_resource *res)
> {
> struct xe_device *xe = ttm_to_xe_device(res->bo->bdev);
>- struct xe_gt *gt = mem_type_to_gt(xe, res->mem_type);
>+ struct xe_tile *tile = mem_type_to_tile(xe, res->mem_type);
>
> if (res->mem_type == XE_PL_STOLEN)
> return xe_ttm_stolen_gpu_offset(xe);
>
>- return gt->mem.vram.io_start - xe->mem.vram.io_start;
>+ return tile->mem.vram.io_start - xe->mem.vram.io_start;
> }
>
> /**
>diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
>index 7e111332c35a..7a79f3893260 100644
>--- a/drivers/gpu/drm/xe/xe_bo.h
>+++ b/drivers/gpu/drm/xe/xe_bo.h
>@@ -22,7 +22,7 @@
> /* -- */
> #define XE_BO_CREATE_STOLEN_BIT BIT(4)
> #define XE_BO_CREATE_VRAM_IF_DGFX(gt) \
>- (IS_DGFX(gt_to_xe(gt)) ? XE_BO_CREATE_VRAM0_BIT << gt->info.vram_id : \
>+ (IS_DGFX(gt_to_xe(gt)) ? XE_BO_CREATE_VRAM0_BIT << gt_to_tile(gt)->id : \
> XE_BO_CREATE_SYSTEM_BIT)
> #define XE_BO_CREATE_GGTT_BIT BIT(5)
> #define XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT BIT(6)
>@@ -107,7 +107,7 @@ struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_gt *gt,
> int xe_bo_placement_for_flags(struct xe_device *xe, struct xe_bo *bo,
> u32 bo_flags);
>
>-struct xe_gt *xe_bo_to_gt(struct xe_bo *bo);
>+struct xe_tile *xe_bo_to_tile(struct xe_bo *bo);
>
> static inline struct xe_bo *ttm_to_xe_bo(const struct ttm_buffer_object *bo)
> {
>diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>index f7f6a6a97757..af165ad6f197 100644
>--- a/drivers/gpu/drm/xe/xe_device.c
>+++ b/drivers/gpu/drm/xe/xe_device.c
>@@ -27,6 +27,7 @@
> #include "xe_pcode.h"
> #include "xe_pm.h"
> #include "xe_query.h"
>+#include "xe_tile.h"
> #include "xe_ttm_stolen_mgr.h"
> #include "xe_ttm_sys_mgr.h"
> #include "xe_vm.h"
>@@ -236,6 +237,7 @@ static void xe_device_sanitize(struct drm_device *drm, void *arg)
>
> int xe_device_probe(struct xe_device *xe)
> {
>+ struct xe_tile *tile;
> struct xe_gt *gt;
> int err;
> u8 id;
>@@ -245,8 +247,12 @@ int xe_device_probe(struct xe_device *xe)
> if (err)
> return err;
>
>- for_each_gt(gt, xe, id) {
>- err = xe_gt_alloc(xe, gt);
>+ for_each_tile(tile, xe, id) {
>+ err = xe_tile_alloc(tile);
>+ if (err)
>+ return err;
>+
>+ err = xe_gt_alloc(xe, &tile->primary_gt);
> if (err)
> return err;
> }
>@@ -281,8 +287,8 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_ttm_sys_mgr_init(xe);
>
>- for_each_gt(gt, xe, id) {
>- err = xe_gt_init_noalloc(gt);
>+ for_each_tile(tile, xe, id) {
>+ err = xe_tile_init_noalloc(tile);
> if (err)
> goto err_irq_shutdown;
> }
>diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>index cb4d0c2ea184..e3fe47c13269 100644
>--- a/drivers/gpu/drm/xe/xe_device_types.h
>+++ b/drivers/gpu/drm/xe/xe_device_types.h
>@@ -102,6 +102,34 @@ struct xe_tile {
>
> /** @mem: memory management info for tile */
> struct {
>+ /**
>+ * @vram: VRAM info for tile.
>+ *
>+ * Although VRAM is associated with a specific tile, it can
>+ * still be accessed by all tiles' GTs.
>+ */
>+ struct {
>+ /** @io_start: IO start address of this VRAM instance */
>+ resource_size_t io_start;
>+ /**
>+ * @io_size: IO size of this VRAM instance
>+ *
>+ * This represents how much of this VRAM we can access
>+ * via the CPU through the VRAM BAR. This can be smaller
>+ * than @size, in which case only part of VRAM is CPU
>+ * accessible (typically the first 256M). This
>+ * configuration is known as small-bar.
>+ */
>+ resource_size_t io_size;
>+ /** @size: size of VRAM. */
>+ resource_size_t size;
>+ /** @mapping: pointer to VRAM mappable space */
>+ void *__iomem mapping;
>+ } vram;
>+
>+ /** @vram_mgr: VRAM TTM manager */
>+ struct xe_ttm_vram_mgr *vram_mgr;
>+
> /** @ggtt: Global graphics translation table */
> struct xe_ggtt *ggtt;
> } mem;
>diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>index 1c58a9aff2cb..ac6073a7fb59 100644
>--- a/drivers/gpu/drm/xe/xe_gt.c
>+++ b/drivers/gpu/drm/xe/xe_gt.c
>@@ -37,7 +37,6 @@
> #include "xe_ring_ops.h"
> #include "xe_sa.h"
> #include "xe_sched_job.h"
>-#include "xe_ttm_vram_mgr.h"
> #include "xe_tuning.h"
> #include "xe_uc.h"
> #include "xe_vm.h"
>@@ -46,58 +45,23 @@
>
> struct xe_gt *xe_find_full_gt(struct xe_gt *gt)
> {
>- struct xe_gt *search;
>- u8 id;
>-
>- XE_BUG_ON(!xe_gt_is_media_type(gt));
>-
>- for_each_gt(search, gt_to_xe(gt), id) {
>- if (search->info.vram_id == gt->info.vram_id)
>- return search;
>- }
>-
>- XE_BUG_ON("NOT POSSIBLE");
>- return NULL;
>+ /*
>+ * FIXME: Media GTs are disabled at the moment. Once re-enabled,
>+ * the proper handling here is to return the primary GT from the
>+ * parameter GT's tile.
>+ */
>+ return gt;
this function gets removed later when migration is moved from GT to
tile. So probably the FIXME is more "Once the code is prepared for
re-enabling, this function will be gone. Just return the only possible
gt for now."
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> }
>
> int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt)
> {
>- struct drm_device *drm = &xe->drm;
>-
> XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
>
>- if (!xe_gt_is_media_type(gt)) {
>- gt->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*gt->mem.vram_mgr),
>- GFP_KERNEL);
>- if (!gt->mem.vram_mgr)
>- return -ENOMEM;
>-
>- } else {
>- struct xe_gt *full_gt = xe_find_full_gt(gt);
>-
>- gt->mem.vram_mgr = full_gt->mem.vram_mgr;
>- }
>-
> gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", 0);
>
> return 0;
> }
>
>-static int gt_ttm_mgr_init(struct xe_gt *gt)
>-{
>- struct xe_device *xe = gt_to_xe(gt);
>- int err;
>-
>- if (gt->mem.vram.size) {
>- err = xe_ttm_vram_mgr_init(gt, gt->mem.vram_mgr);
>- if (err)
>- return err;
>- xe->info.mem_region_mask |= BIT(gt->info.vram_id) << 1;
>- }
>-
>- return 0;
>-}
>-
> void xe_gt_sanitize(struct xe_gt *gt)
> {
> /*
>@@ -315,41 +279,6 @@ int xe_gt_init_early(struct xe_gt *gt)
> return 0;
> }
>
>-/**
>- * xe_gt_init_noalloc - Init GT up to the point where allocations can happen.
>- * @gt: The GT to initialize.
>- *
>- * This function prepares the GT to allow memory allocations to VRAM, but is not
>- * allowed to allocate memory itself. This state is useful for display readout,
>- * because the inherited display framebuffer will otherwise be overwritten as it
>- * is usually put at the start of VRAM.
>- *
>- * Returns: 0 on success, negative error code on error.
>- */
>-int xe_gt_init_noalloc(struct xe_gt *gt)
>-{
>- int err, err2;
>-
>- if (xe_gt_is_media_type(gt))
>- return 0;
>-
>- xe_device_mem_access_get(gt_to_xe(gt));
>- err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
>- if (err)
>- goto err;
>-
>- err = gt_ttm_mgr_init(gt);
>- if (err)
>- goto err_force_wake;
>-
>-err_force_wake:
>- err2 = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
>- XE_WARN_ON(err2);
>- xe_device_mem_access_put(gt_to_xe(gt));
>-err:
>- return err;
>-}
>-
> static int gt_fw_domain_init(struct xe_gt *gt)
> {
> int err, i;
>diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c
>index 1677640e1075..f4f3d95ae6b1 100644
>--- a/drivers/gpu/drm/xe/xe_gt_pagefault.c
>+++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c
>@@ -107,6 +107,7 @@ static struct xe_vma *lookup_vma(struct xe_vm *vm, u64 page_addr)
> static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf)
> {
> struct xe_device *xe = gt_to_xe(gt);
>+ struct xe_tile *tile = gt_to_tile(gt);
> struct xe_vm *vm;
> struct xe_vma *vma = NULL;
> struct xe_bo *bo;
>@@ -195,7 +196,7 @@ static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf)
> }
>
> /* Migrate to VRAM, move should invalidate the VMA first */
>- ret = xe_bo_migrate(bo, XE_PL_VRAM0 + gt->info.vram_id);
>+ ret = xe_bo_migrate(bo, XE_PL_VRAM0 + tile->id);
> if (ret)
> goto unlock_dma_resv;
> } else if (bo) {
>@@ -498,6 +499,7 @@ static struct xe_vma *get_acc_vma(struct xe_vm *vm, struct acc *acc)
> static int handle_acc(struct xe_gt *gt, struct acc *acc)
> {
> struct xe_device *xe = gt_to_xe(gt);
>+ struct xe_tile *tile = gt_to_tile(gt);
> struct xe_vm *vm;
> struct xe_vma *vma;
> struct xe_bo *bo;
>@@ -553,7 +555,7 @@ static int handle_acc(struct xe_gt *gt, struct acc *acc)
> goto unlock_vm;
>
> /* Migrate to VRAM, move should invalidate the VMA first */
>- ret = xe_bo_migrate(bo, XE_PL_VRAM0 + gt->info.vram_id);
>+ ret = xe_bo_migrate(bo, XE_PL_VRAM0 + tile->id);
>
> if (only_needs_bo_lock(bo))
> xe_bo_unlock(bo, &ww);
>diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
>index e910ec1b8dd3..fcea0dc150ed 100644
>--- a/drivers/gpu/drm/xe/xe_gt_types.h
>+++ b/drivers/gpu/drm/xe/xe_gt_types.h
>@@ -16,8 +16,6 @@
> struct xe_engine_ops;
> struct xe_migrate;
> struct xe_ring_ops;
>-struct xe_ttm_gtt_mgr;
>-struct xe_ttm_vram_mgr;
>
> enum xe_gt_type {
> XE_GT_TYPE_UNINITIALIZED,
>@@ -108,8 +106,6 @@ struct xe_gt {
> enum xe_gt_type type;
> /** @id: id of GT */
> u8 id;
>- /** @vram: id of the VRAM for this GT */
>- u8 vram_id;
> /** @clock_freq: clock frequency */
> u32 clock_freq;
> /** @engine_mask: mask of engines present on GT */
>@@ -144,37 +140,6 @@ struct xe_gt {
> */
> struct xe_reg_sr reg_sr;
>
>- /**
>- * @mem: memory management info for GT, multiple GTs can point to same
>- * objects (virtual split)
>- */
>- struct {
>- /**
>- * @vram: VRAM info for GT, multiple GTs can point to same info
>- * (virtual split), can be subset of global device VRAM
>- */
>- struct {
>- /** @io_start: IO start address of this VRAM instance */
>- resource_size_t io_start;
>- /**
>- * @io_size: IO size of this VRAM instance
>- *
>- * This represents how much of this VRAM we can access
>- * via the CPU through the VRAM BAR. This can be smaller
>- * than @size, in which case only part of VRAM is CPU
>- * accessible (typically the first 256M). This
>- * configuration is known as small-bar.
>- */
>- resource_size_t io_size;
>- /** @size: size of VRAM. */
>- resource_size_t size;
>- /** @mapping: pointer to VRAM mappable space */
>- void *__iomem mapping;
>- } vram;
>- /** @vram_mgr: VRAM TTM manager */
>- struct xe_ttm_vram_mgr *vram_mgr;
>- } mem;
>-
> /** @reset: state for GT resets */
> struct {
> /**
>diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>index 5bf359c81cc5..5be31855d789 100644
>--- a/drivers/gpu/drm/xe/xe_irq.c
>+++ b/drivers/gpu/drm/xe/xe_irq.c
>@@ -369,7 +369,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> }
>
> for_each_gt(gt, xe, id) {
>- if ((master_tile_ctl & DG1_MSTR_TILE(gt->info.vram_id)) == 0)
>+ if ((master_tile_ctl & DG1_MSTR_TILE(gt_to_tile(gt)->id)) == 0)
> continue;
>
> if (!xe_gt_is_media_type(gt))
>diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
>index 54fa1212fcd9..17b3a9880409 100644
>--- a/drivers/gpu/drm/xe/xe_mmio.c
>+++ b/drivers/gpu/drm/xe/xe_mmio.c
>@@ -182,7 +182,7 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_si
> int xe_mmio_probe_vram(struct xe_device *xe)
> {
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>- struct xe_gt *gt;
>+ struct xe_tile *tile;
> u8 id;
> u64 vram_size;
> u64 original_size;
>@@ -195,11 +195,11 @@ int xe_mmio_probe_vram(struct xe_device *xe)
> xe->mem.vram.io_start = 0;
> xe->mem.vram.io_size = 0;
>
>- for_each_gt(gt, xe, id) {
>- gt->mem.vram.mapping = 0;
>- gt->mem.vram.size = 0;
>- gt->mem.vram.io_start = 0;
>- gt->mem.vram.io_size = 0;
>+ for_each_tile(tile, xe, id) {
>+ tile->mem.vram.mapping = 0;
>+ tile->mem.vram.size = 0;
>+ tile->mem.vram.io_start = 0;
>+ tile->mem.vram.io_size = 0;
> }
> return 0;
> }
>@@ -209,7 +209,6 @@ int xe_mmio_probe_vram(struct xe_device *xe)
> return -ENXIO;
> }
>
>- gt = xe_device_get_gt(xe, 0);
> original_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
>
> err = xe_mmio_total_vram_size(xe, &vram_size, &usable_size);
>@@ -239,23 +238,19 @@ int xe_mmio_probe_vram(struct xe_device *xe)
> u8 adj_tile_count = xe->info.tile_count;
> resource_size_t size, io_start, io_size;
>
>- for_each_gt(gt, xe, id)
>- if (xe_gt_is_media_type(gt))
>- --adj_tile_count;
>-
> XE_BUG_ON(!adj_tile_count);
>
> size = xe->mem.vram.size / adj_tile_count;
> io_start = xe->mem.vram.io_start;
> io_size = xe->mem.vram.io_size;
>
>- for_each_gt(gt, xe, id) {
>- if (id && !xe_gt_is_media_type(gt)) {
>+ for_each_tile(tile, xe, id) {
>+ if (id) {
> io_size -= min(io_size, size);
> io_start += io_size;
> }
>
>- gt->mem.vram.size = size;
>+ tile->mem.vram.size = size;
>
> /*
> * XXX: multi-tile small-bar might be wild. Hopefully
>@@ -263,10 +258,10 @@ int xe_mmio_probe_vram(struct xe_device *xe)
> * we care about.
> */
>
>- gt->mem.vram.io_size = min(size, io_size);
>+ tile->mem.vram.io_size = min(size, io_size);
> if (io_size) {
>- gt->mem.vram.io_start = io_start;
>- gt->mem.vram.mapping = xe->mem.vram.mapping +
>+ tile->mem.vram.io_start = io_start;
>+ tile->mem.vram.mapping = xe->mem.vram.mapping +
> (io_start - xe->mem.vram.io_start);
> } else {
> drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
>@@ -274,16 +269,18 @@ int xe_mmio_probe_vram(struct xe_device *xe)
> }
>
> drm_info(&xe->drm, "VRAM[%u, %u]: %pa, %pa\n",
>- id, gt->info.vram_id, >->mem.vram.io_start,
>- >->mem.vram.size);
>+ id, tile->id, &tile->mem.vram.io_start,
>+ &tile->mem.vram.size);
> }
> } else {
>- gt->mem.vram.size = xe->mem.vram.size;
>- gt->mem.vram.io_start = xe->mem.vram.io_start;
>- gt->mem.vram.io_size = xe->mem.vram.io_size;
>- gt->mem.vram.mapping = xe->mem.vram.mapping;
>+ tile = xe_device_get_root_tile(xe);
>
>- drm_info(&xe->drm, "VRAM: %pa\n", >->mem.vram.size);
>+ tile->mem.vram.size = xe->mem.vram.size;
>+ tile->mem.vram.io_start = xe->mem.vram.io_start;
>+ tile->mem.vram.io_size = xe->mem.vram.io_size;
>+ tile->mem.vram.mapping = xe->mem.vram.mapping;
>+
>+ drm_info(&xe->drm, "VRAM: %pa\n", &tile->mem.vram.size);
> }
> return 0;
> }
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index 0fb7ebb9653e..0269327b26e9 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -559,7 +559,6 @@ static int xe_info_init(struct xe_device *xe,
>
> if (id == 0) {
> gt->info.type = XE_GT_TYPE_MAIN;
>- gt->info.vram_id = id;
>
> gt->info.__engine_mask = graphics_desc->hw_engine_mask;
> if (MEDIA_VER(xe) < 13 && media_desc)
>@@ -569,7 +568,6 @@ static int xe_info_init(struct xe_device *xe,
> gt->mmio.adj_offset = 0;
> } else {
> gt->info.type = desc->extra_gts[id - 1].type;
>- gt->info.vram_id = desc->extra_gts[id - 1].vram_id;
> gt->info.__engine_mask = (gt->info.type == XE_GT_TYPE_MEDIA) ?
> media_desc->hw_engine_mask :
> graphics_desc->hw_engine_mask;
>diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
>index 61126cefe0b5..ad42a21c0e22 100644
>--- a/drivers/gpu/drm/xe/xe_pt.c
>+++ b/drivers/gpu/drm/xe/xe_pt.c
>@@ -758,12 +758,12 @@ xe_pt_stage_bind(struct xe_gt *gt, struct xe_vma *vma,
> int ret;
>
> if (is_vram) {
>- struct xe_gt *bo_gt = xe_bo_to_gt(bo);
>+ struct xe_tile *bo_tile = xe_bo_to_tile(bo);
>
> xe_walk.default_pte = XE_PPGTT_PTE_LM;
> if (vma && vma->use_atomic_access_pte_bit)
> xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
>- xe_walk.dma_offset = bo_gt->mem.vram.io_start -
>+ xe_walk.dma_offset = bo_tile->mem.vram.io_start -
> gt_to_xe(gt)->mem.vram.io_start;
> xe_walk.cache = XE_CACHE_WB;
> } else {
>diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
>index dd64ff0d2a57..c81652d7f4ec 100644
>--- a/drivers/gpu/drm/xe/xe_query.c
>+++ b/drivers/gpu/drm/xe/xe_query.c
>@@ -182,7 +182,7 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query)
> config->num_params = num_params;
> config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID] =
> xe->info.devid | (xe->info.revid << 16);
>- if (to_gt(xe)->mem.vram.size)
>+ if (xe_device_get_root_tile(xe)->mem.vram.size)
> config->info[XE_QUERY_CONFIG_FLAGS] =
> XE_QUERY_CONFIG_FLAGS_HAS_VRAM;
> if (xe->info.enable_guc)
>@@ -242,7 +242,7 @@ static int query_gts(struct xe_device *xe, struct drm_xe_device_query *query)
> gts->gts[id].native_mem_regions = 0x1;
> else
> gts->gts[id].native_mem_regions =
>- BIT(gt->info.vram_id) << 1;
>+ BIT(gt_to_tile(gt)->id) << 1;
> gts->gts[id].slow_mem_regions = xe->info.mem_region_mask ^
> gts->gts[id].native_mem_regions;
> }
>diff --git a/drivers/gpu/drm/xe/xe_res_cursor.h b/drivers/gpu/drm/xe/xe_res_cursor.h
>index 4e99fae26b4c..f2ba609712d3 100644
>--- a/drivers/gpu/drm/xe/xe_res_cursor.h
>+++ b/drivers/gpu/drm/xe/xe_res_cursor.h
>@@ -53,7 +53,7 @@ static struct drm_buddy *xe_res_get_buddy(struct ttm_resource *res)
> struct xe_device *xe = ttm_to_xe_device(res->bo->bdev);
>
> if (res->mem_type != XE_PL_STOLEN) {
>- return &xe_device_get_gt(xe, res->mem_type - XE_PL_VRAM0)->mem.vram_mgr->mm;
>+ return &xe->tiles[res->mem_type - XE_PL_VRAM0].mem.vram_mgr->mm;
> } else {
> struct ttm_resource_manager *mgr =
> ttm_manager_type(&xe->ttm, XE_PL_STOLEN);
>diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
>index 7ef594f301ca..5530a6b6ef31 100644
>--- a/drivers/gpu/drm/xe/xe_tile.c
>+++ b/drivers/gpu/drm/xe/xe_tile.c
>@@ -29,6 +29,25 @@ int xe_tile_alloc(struct xe_tile *tile)
> return -ENOMEM;
> tile->mem.ggtt->tile = tile;
>
>+ tile->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile->mem.vram_mgr), GFP_KERNEL);
>+ if (!tile->mem.vram_mgr)
>+ return -ENOMEM;
>+
>+ return 0;
>+}
>+
>+static int tile_ttm_mgr_init(struct xe_tile *tile)
>+{
>+ struct xe_device *xe = tile_to_xe(tile);
>+ int err;
>+
>+ if (tile->mem.vram.size) {
>+ err = xe_ttm_vram_mgr_init(tile, tile->mem.vram_mgr);
>+ if (err)
>+ return err;
>+ xe->info.mem_region_mask |= BIT(tile->id) << 1;
>+ }
>+
> return 0;
> }
>
>@@ -48,5 +67,17 @@ int xe_tile_alloc(struct xe_tile *tile)
> */
> int xe_tile_init_noalloc(struct xe_tile *tile)
> {
>- return xe_ggtt_init_noalloc(tile->mem.ggtt);
>+ int err;
>+
>+ xe_device_mem_access_get(tile_to_xe(tile));
>+
>+ err = tile_ttm_mgr_init(tile);
>+ if (err)
>+ goto err_mem_access;
>+
>+ err = xe_ggtt_init_noalloc(tile->mem.ggtt);
>+
>+err_mem_access:
>+ xe_device_mem_access_put(tile_to_xe(tile));
>+ return err;
> }
>diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
>index 73836b9b7fed..1a84abd35fcf 100644
>--- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
>+++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
>@@ -353,16 +353,14 @@ int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct xe_ttm_vram_mgr *mgr,
> return drmm_add_action_or_reset(&xe->drm, ttm_vram_mgr_fini, mgr);
> }
>
>-int xe_ttm_vram_mgr_init(struct xe_gt *gt, struct xe_ttm_vram_mgr *mgr)
>+int xe_ttm_vram_mgr_init(struct xe_tile *tile, struct xe_ttm_vram_mgr *mgr)
> {
>- struct xe_device *xe = gt_to_xe(gt);
>+ struct xe_device *xe = tile_to_xe(tile);
>
>- XE_BUG_ON(xe_gt_is_media_type(gt));
>+ mgr->tile = tile;
>
>- mgr->gt = gt;
>-
>- return __xe_ttm_vram_mgr_init(xe, mgr, XE_PL_VRAM0 + gt->info.vram_id,
>- gt->mem.vram.size, gt->mem.vram.io_size,
>+ return __xe_ttm_vram_mgr_init(xe, mgr, XE_PL_VRAM0 + tile->id,
>+ tile->mem.vram.size, tile->mem.vram.io_size,
> PAGE_SIZE);
> }
>
>@@ -373,7 +371,7 @@ int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,
> enum dma_data_direction dir,
> struct sg_table **sgt)
> {
>- struct xe_gt *gt = xe_device_get_gt(xe, res->mem_type - XE_PL_VRAM0);
>+ struct xe_tile *tile = &xe->tiles[res->mem_type - XE_PL_VRAM0];
> struct xe_res_cursor cursor;
> struct scatterlist *sg;
> int num_entries = 0;
>@@ -406,7 +404,7 @@ int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,
> */
> xe_res_first(res, offset, length, &cursor);
> for_each_sgtable_sg((*sgt), sg, i) {
>- phys_addr_t phys = cursor.start + gt->mem.vram.io_start;
>+ phys_addr_t phys = cursor.start + tile->mem.vram.io_start;
> size_t size = cursor.size;
> dma_addr_t addr;
>
>diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
>index 35e5367a79fb..6e1d6033d739 100644
>--- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
>+++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
>@@ -10,12 +10,12 @@
>
> enum dma_data_direction;
> struct xe_device;
>-struct xe_gt;
>+struct xe_tile;
>
> int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct xe_ttm_vram_mgr *mgr,
> u32 mem_type, u64 size, u64 io_size,
> u64 default_page_size);
>-int xe_ttm_vram_mgr_init(struct xe_gt *gt, struct xe_ttm_vram_mgr *mgr);
>+int xe_ttm_vram_mgr_init(struct xe_tile *tile, struct xe_ttm_vram_mgr *mgr);
> int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,
> struct ttm_resource *res,
> u64 offset, u64 length,
>diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h b/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
>index 3d9417ff7434..48bb991c14a5 100644
>--- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
>+++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
>@@ -9,7 +9,7 @@
> #include <drm/drm_buddy.h>
> #include <drm/ttm/ttm_device.h>
>
>-struct xe_gt;
>+struct xe_tile;
>
> /**
> * struct xe_ttm_vram_mgr - XE TTM VRAM manager
>@@ -17,8 +17,8 @@ struct xe_gt;
> * Manages placement of TTM resource in VRAM.
> */
> struct xe_ttm_vram_mgr {
>- /** @gt: Graphics tile which the VRAM belongs to */
>- struct xe_gt *gt;
>+ /** @tile: Tile which the VRAM belongs to */
>+ struct xe_tile *tile;
> /** @manager: Base TTM resource manager */
> struct ttm_resource_manager manager;
> /** @mm: DRM buddy allocator which manages the VRAM */
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 10/30] fixup! drm/xe/display: Implement display support
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 10/30] fixup! drm/xe/display: Implement display support Matt Roper
@ 2023-05-26 21:12 ` Lucas De Marchi
0 siblings, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-26 21:12 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
On Fri, May 19, 2023 at 04:18:07PM -0700, Matt Roper wrote:
>---
> drivers/gpu/drm/xe/display/xe_plane_initial.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
>index 41540b27775c..39dd97acae08 100644
>--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
>+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
>@@ -51,7 +51,6 @@ static struct xe_bo *
> initial_plane_bo(struct xe_device *xe,
> struct intel_initial_plane_config *plane_config)
> {
>- struct xe_gt *gt0 = xe_device_get_gt(xe, 0);
> struct xe_tile *tile0 = xe_device_get_root_tile(xe);
> struct xe_bo *bo;
> resource_size_t phys_base;
>@@ -84,7 +83,7 @@ initial_plane_bo(struct xe_device *xe,
> * We don't currently expect this to ever be placed in the
> * stolen portion.
> */
>- if (phys_base >= gt0->mem.vram.size) {
>+ if (phys_base >= tile0->mem.vram.size) {
> drm_err(&xe->drm,
> "Initial plane programming using invalid range, phys_base=%pa\n",
> &phys_base);
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 12/30] fixup! drm/xe/display: Implement display support
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 12/30] fixup! drm/xe/display: Implement display support Matt Roper
@ 2023-05-26 21:14 ` Lucas De Marchi
0 siblings, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-26 21:14 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
On Fri, May 19, 2023 at 04:18:09PM -0700, Matt Roper wrote:
>---
> drivers/gpu/drm/i915/display/intel_dsb.c | 5 +++--
> drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_fbdev.c | 7 ++++---
> drivers/gpu/drm/xe/display/xe_fb_pin.c | 7 ++++---
> drivers/gpu/drm/xe/display/xe_plane_initial.c | 2 +-
> 5 files changed, 14 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>index 7c93580282b4..3830309aacf4 100644
>--- a/drivers/gpu/drm/i915/display/intel_dsb.c
>+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>@@ -379,9 +379,10 @@ struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc,
> #else
> /* ~1 qword per instruction, full cachelines */
> size = ALIGN(max_cmds * 8, 64);
>- obj = xe_bo_create_pin_map(i915, to_gt(i915), NULL, PAGE_ALIGN(size),
>+ obj = xe_bo_create_pin_map(i915, xe_device_get_root_tile(i915),
>+ NULL, PAGE_ALIGN(size),
> ttm_bo_type_kernel,
>- XE_BO_CREATE_VRAM_IF_DGFX(to_gt(i915)) |
>+ XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(i915)) |
> XE_BO_CREATE_GGTT_BIT);
> if (IS_ERR(obj)) {
> kfree(dsb);
>diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
>index 9dc7083fe974..0e8e899f596b 100644
>--- a/drivers/gpu/drm/i915/display/intel_fbc.c
>+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>@@ -71,7 +71,8 @@ static int i915_gem_stolen_insert_node_in_range(struct xe_device *xe, struct xe_
> int err;
> u32 flags = XE_BO_CREATE_PINNED_BIT | XE_BO_CREATE_STOLEN_BIT;
>
>- *bo = xe_bo_create_locked_range(xe, to_gt(xe), NULL, size, start, end,
>+ *bo = xe_bo_create_locked_range(xe, xe_device_get_root_tile(xe),
>+ NULL, size, start, end,
> ttm_bo_type_kernel, flags);
> if (IS_ERR(*bo)) {
> err = PTR_ERR(*bo);
>diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
>index 95f4cbc2e675..ebb07d0ccff6 100644
>--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
>+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
>@@ -210,7 +210,8 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
> }
> #else
> if (!IS_DGFX(dev_priv)) {
>- obj = xe_bo_create_pin_map(dev_priv, to_gt(dev_priv), NULL, size,
>+ obj = xe_bo_create_pin_map(dev_priv, xe_device_get_root_tile(dev_priv),
>+ NULL, size,
> ttm_bo_type_kernel, XE_BO_SCANOUT_BIT |
> XE_BO_CREATE_STOLEN_BIT |
> XE_BO_CREATE_PINNED_BIT);
>@@ -220,9 +221,9 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
> drm_info(&dev_priv->drm, "Allocated fbdev into stolen failed: %li\n", PTR_ERR(obj));
> }
> if (IS_ERR(obj)) {
>- obj = xe_bo_create_pin_map(dev_priv, to_gt(dev_priv), NULL, size,
>+ obj = xe_bo_create_pin_map(dev_priv, xe_device_get_root_tile(dev_priv), NULL, size,
> ttm_bo_type_kernel, XE_BO_SCANOUT_BIT |
>- XE_BO_CREATE_VRAM_IF_DGFX(to_gt(dev_priv)) |
>+ XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(dev_priv)) |
> XE_BO_CREATE_PINNED_BIT);
> }
> #endif
>diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>index 27e4d29aa73d..97e9be79b154 100644
>--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>@@ -45,6 +45,7 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
> struct i915_vma *vma)
> {
> struct xe_device *xe = to_xe_device(fb->base.dev);
>+ struct xe_tile *tile0 = xe_device_get_root_tile(xe);
> struct xe_bo *bo = intel_fb_obj(&fb->base), *dpt;
> u32 dpt_size, size = bo->ttm.base.size;
>
>@@ -55,17 +56,17 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
> dpt_size = ALIGN(intel_rotation_info_size(&view->rotated) * 8,
> XE_PAGE_SIZE);
>
>- dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
>+ dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
> ttm_bo_type_kernel,
> XE_BO_CREATE_VRAM0_BIT |
> XE_BO_CREATE_GGTT_BIT);
> if (IS_ERR(dpt))
>- dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
>+ dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
> ttm_bo_type_kernel,
> XE_BO_CREATE_STOLEN_BIT |
> XE_BO_CREATE_GGTT_BIT);
> if (IS_ERR(dpt))
>- dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
>+ dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
> ttm_bo_type_kernel,
> XE_BO_CREATE_SYSTEM_BIT |
> XE_BO_CREATE_GGTT_BIT);
>diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
>index 39dd97acae08..99c35a4ef673 100644
>--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
>+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
>@@ -115,7 +115,7 @@ initial_plane_bo(struct xe_device *xe,
> page_size);
> size -= base;
>
>- bo = xe_bo_create_pin_map_at(xe, &tile0->primary_gt, NULL, size, phys_base,
>+ bo = xe_bo_create_pin_map_at(xe, tile0, NULL, size, phys_base,
> ttm_bo_type_kernel, flags);
> if (IS_ERR(bo)) {
> drm_dbg(&xe->drm,
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 14/30] drm/xe: Clarify 'gt' retrieval for primary tile
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 14/30] drm/xe: Clarify 'gt' retrieval for primary tile Matt Roper
2023-05-22 11:47 ` Das, Nirmoy
@ 2023-05-26 21:33 ` Lucas De Marchi
1 sibling, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-26 21:33 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, May 19, 2023 at 04:18:11PM -0700, Matt Roper wrote:
>There are a bunch of places in the driver where we need to perform
>non-GT MMIO against the platform's primary tile (display code, top-level
>interrupt enable/disable, driver initialization, etc.). Rename
>'to_gt()' to 'xe_primary_mmio_gt()' to clarify that we're trying to get
>a primary MMIO handle for these top-level operations.
>
>In the future we need to move away from xe_gt as the target for MMIO
>operations (most of which are completely unrelated to GT).
>
>v2:
> - s/xe_primary_mmio_gt/xe_root_mmio_gt/ for more consistency with how
> we refer to tile 0. (Lucas)
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h | 2 +-
> drivers/gpu/drm/xe/xe_device.c | 2 +-
> drivers/gpu/drm/xe/xe_device.h | 11 +++++++++--
> drivers/gpu/drm/xe/xe_irq.c | 6 +++---
> drivers/gpu/drm/xe/xe_mmio.c | 8 ++++----
> drivers/gpu/drm/xe/xe_query.c | 2 +-
> drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 4 ++--
> 7 files changed, 21 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
>index 14f195fe275d..fae6213d26f1 100644
>--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
>+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
the history of this file is odd. Apparently it was a cherry-pick with
the compat-i915-headers squashed (cherry picked from commit da38ba98645d789ddda2a584d40e2de00139e98b)
the cherry-pick really match that though. I think we will need to split
this change out from the rest, but since the current state is already
wrong we can leave it as is and later just take the final diff of
drivers/gpu/drm/xe/compat-i915-headers to squash somewhere when we
rebase again.
>@@ -14,7 +14,7 @@ static inline struct xe_gt *__fake_uncore_to_gt(struct fake_uncore *uncore)
> {
> struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
>
>- return to_gt(xe);
>+ return xe_root_mmio_gt(xe);
> }
>
> static inline u32 intel_uncore_read(struct fake_uncore *uncore,
>diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>index af165ad6f197..43a585b67581 100644
>--- a/drivers/gpu/drm/xe/xe_device.c
>+++ b/drivers/gpu/drm/xe/xe_device.c
>@@ -394,7 +394,7 @@ static void device_kill_persistent_engines(struct xe_device *xe,
>
> void xe_device_wmb(struct xe_device *xe)
> {
>- struct xe_gt *gt = xe_device_get_gt(xe, 0);
>+ struct xe_gt *gt = xe_root_mmio_gt(xe);
>
> wmb();
> if (IS_DGFX(xe))
>diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
>index 745dbb16d417..42bc566c53d8 100644
>--- a/drivers/gpu/drm/xe/xe_device.h
>+++ b/drivers/gpu/drm/xe/xe_device.h
>@@ -66,9 +66,16 @@ static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
> }
>
> /*
>- * FIXME: Placeholder until multi-gt lands. Once that lands, kill this function.
>+ * Provide a GT structure suitable for performing non-GT MMIO operations against
>+ * the primary tile. Primarily intended for early tile initialization, display
>+ * handling, top-most interrupt enable/disable, etc. Since anything using the
>+ * MMIO handle returned by this function doesn't need GSI offset translation,
>+ * we'll return the primary GT from the root tile.
>+ *
>+ * FIXME: Fix the driver design so that 'gt' isn't the target of all MMIO
>+ * operations.
could add a short line here:
Returns the primary gt of the root tile
Anyway,
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> */
>-static inline struct xe_gt *to_gt(struct xe_device *xe)
>+static inline struct xe_gt *xe_root_mmio_gt(struct xe_device *xe)
> {
> return &xe_device_get_root_tile(xe)->primary_gt;
> }
>diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>index 5be31855d789..628057497cd5 100644
>--- a/drivers/gpu/drm/xe/xe_irq.c
>+++ b/drivers/gpu/drm/xe/xe_irq.c
>@@ -285,7 +285,7 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> static irqreturn_t xelp_irq_handler(int irq, void *arg)
> {
> struct xe_device *xe = arg;
>- struct xe_gt *gt = xe_device_get_gt(xe, 0); /* Only 1 GT here */
>+ struct xe_gt *gt = xe_root_mmio_gt(xe);
> u32 master_ctl, gu_misc_iir;
> long unsigned int intr_dw[2];
> u32 identity[32];
>@@ -311,7 +311,7 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>
> static u32 dg1_intr_disable(struct xe_device *xe)
> {
>- struct xe_gt *gt = xe_device_get_gt(xe, 0);
>+ struct xe_gt *gt = xe_root_mmio_gt(xe);
> u32 val;
>
> /* First disable interrupts */
>@@ -329,7 +329,7 @@ static u32 dg1_intr_disable(struct xe_device *xe)
>
> static void dg1_intr_enable(struct xe_device *xe, bool stall)
> {
>- struct xe_gt *gt = xe_device_get_gt(xe, 0);
>+ struct xe_gt *gt = xe_root_mmio_gt(xe);
>
> xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
> if (stall)
>diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
>index 17b3a9880409..32427c10ba8a 100644
>--- a/drivers/gpu/drm/xe/xe_mmio.c
>+++ b/drivers/gpu/drm/xe/xe_mmio.c
>@@ -150,7 +150,7 @@ static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
>
> int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_size)
> {
>- struct xe_gt *gt = xe_device_get_gt(xe, 0);
>+ struct xe_gt *gt = xe_root_mmio_gt(xe);
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> int err;
> u32 reg_val;
>@@ -287,7 +287,7 @@ int xe_mmio_probe_vram(struct xe_device *xe)
>
> static void xe_mmio_probe_tiles(struct xe_device *xe)
> {
>- struct xe_gt *gt = xe_device_get_gt(xe, 0);
>+ struct xe_gt *gt = xe_root_mmio_gt(xe);
> u32 mtcfg;
> u8 adj_tile_count;
> u8 id;
>@@ -339,7 +339,7 @@ static void mmio_fini(struct drm_device *drm, void *arg)
> int xe_mmio_init(struct xe_device *xe)
> {
> struct xe_tile *root_tile = xe_device_get_root_tile(xe);
>- struct xe_gt *gt = xe_device_get_gt(xe, 0);
>+ struct xe_gt *gt = xe_root_mmio_gt(xe);
> const int mmio_bar = 0;
> int err;
>
>@@ -398,7 +398,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> struct xe_device *xe = to_xe_device(dev);
>- struct xe_gt *gt = xe_device_get_gt(xe, 0);
>+ struct xe_gt *gt = xe_root_mmio_gt(xe);
> struct drm_xe_mmio *args = data;
> unsigned int bits_flag, bytes;
> struct xe_reg reg;
>diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
>index c81652d7f4ec..49fff425adcd 100644
>--- a/drivers/gpu/drm/xe/xe_query.c
>+++ b/drivers/gpu/drm/xe/xe_query.c
>@@ -259,7 +259,7 @@ static int query_gts(struct xe_device *xe, struct drm_xe_device_query *query)
> static int query_hwconfig(struct xe_device *xe,
> struct drm_xe_device_query *query)
> {
>- struct xe_gt *gt = xe_device_get_gt(xe, 0);
>+ struct xe_gt *gt = xe_root_mmio_gt(xe);
> size_t size = xe_guc_hwconfig_size(>->uc.guc);
> void __user *query_ptr = u64_to_user_ptr(query->data);
> void *hwconfig;
>diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
>index a3855870321f..012474a6c387 100644
>--- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
>+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
>@@ -54,7 +54,7 @@ bool xe_ttm_stolen_cpu_access_needs_ggtt(struct xe_device *xe)
> static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
> {
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>- struct xe_gt *gt = to_gt(xe);
>+ struct xe_gt *gt = xe_root_mmio_gt(xe);
> u64 vram_size, stolen_size;
> int err;
>
>@@ -88,7 +88,7 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr
> u32 stolen_size;
> u32 ggc, gms;
>
>- ggc = xe_mmio_read32(to_gt(xe), GGC);
>+ ggc = xe_mmio_read32(xe_root_mmio_gt(xe), GGC);
>
> /* check GGMS, should be fixed 0x3 (8MB) */
> if (drm_WARN_ON(&xe->drm, (ggc & GGMS_MASK) != GGMS_MASK))
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 20/30] drm/xe: Interrupts are delivered per-tile, not per-GT
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 20/30] drm/xe: Interrupts are delivered per-tile, not per-GT Matt Roper
@ 2023-05-26 22:16 ` Lucas De Marchi
2023-05-30 6:36 ` Iddamsetty, Aravind
1 sibling, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-26 22:16 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, May 19, 2023 at 04:18:17PM -0700, Matt Roper wrote:
>IRQ delivery and handling needs to be handled on a per-tile basis. Note
>that this is true even for the "GT interrupts" relating to engines and
>GuCs --- the interrupts relating to both GTs get raised through a single
>set of registers in the tile's sgunit range.
>
>On true multi-tile platforms, interrupts on remote tiles are internally
>forwarded to the root tile; the first thing the top-level interrupt
>handler should do is consult the root tile's instance of
>DG1_MSTR_TILE_INTR to determine which tile(s) had interrupts. This
>register is also responsible for enabling/disabling top-level reporting
>of any interrupts to the OS. Although this register technically exists
>on all tiles, it should only be used on the root tile.
>
>The (mis)use of struct xe_gt as a target for MMIO operations in the
>driver makes the code somewhat confusing since we wind up needing a GT
>pointer to handle programming that's unrelated to the GT. To mitigate
>this confusion, all of the xe_gt structures used solely as an MMIO
>target in interrupt code are renamed to 'mmio' so that it's clear that
I still think it's odd to call an instance of `struct xe_gt` as mmio and
if we decide to create a better abstraction for the mmio, we may have in
future a struct xe_mmio that will clash here. Hence I think it would be
better to call it mmio_gt. But I won´t insist and leave this just as
feedback.
Reviewing this after applying it locally and using --color-words was
much easier
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>the structure being passed does not necessarily relate to any specific
>GT (primary or media) that we might be dealing with interrupts for.
>Reworking the driver's MMIO handling to not be dependent on xe_gt is
>planned as a future patch series.
>
>Note that GT initialization code currently calls xe_gt_irq_postinstall()
>in an attempt to enable the HWE interrupts for the GT being initialized.
>Unfortunately xe_gt_irq_postinstall() doesn't really match its name and
>does a bunch of other stuff unrelated to the GT interrupts (such as
>enabling the top-level device interrupts). That will be addressed in
>future patches.
>
>v2:
> - Clarify commit message with explanation of why DG1_MSTR_TILE_INTR is
> only used on the root tile, even though it's an sgunit register that
> is technically present in each tile's MMIO space. (Aravind)
> - Also clarify that the xe_gt used as a target for MMIO operations may
> or may not relate to the GT we're dealing with for interrupts.
> (Lucas)
>
>Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/xe_gt.c | 2 +-
> drivers/gpu/drm/xe/xe_irq.c | 334 ++++++++++++++++++++----------------
> drivers/gpu/drm/xe/xe_irq.h | 4 +-
> 3 files changed, 187 insertions(+), 153 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>index 0abd0d912610..290935e46059 100644
>--- a/drivers/gpu/drm/xe/xe_gt.c
>+++ b/drivers/gpu/drm/xe/xe_gt.c
>@@ -304,7 +304,7 @@ static int gt_fw_domain_init(struct xe_gt *gt)
> gt->info.engine_mask = gt->info.__engine_mask;
>
> /* Enables per hw engine IRQs */
>- xe_gt_irq_postinstall(gt);
>+ xe_gt_irq_postinstall(gt_to_tile(gt));
>
> /* Rerun MCR init as we now have hw engine list */
> xe_gt_mcr_init(gt);
>diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>index 654c34a5b99a..ad2f73b2a031 100644
>--- a/drivers/gpu/drm/xe/xe_irq.c
>+++ b/drivers/gpu/drm/xe/xe_irq.c
>@@ -27,60 +27,66 @@
> #define IIR(offset) XE_REG(offset + 0x8)
> #define IER(offset) XE_REG(offset + 0xc)
>
>-static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
>+static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
> {
>- u32 val = xe_mmio_read32(gt, reg);
>+ u32 val = xe_mmio_read32(mmio, reg);
>
> if (val == 0)
> return;
>
>- drm_WARN(>_to_xe(gt)->drm, 1,
>+ drm_WARN(>_to_xe(mmio)->drm, 1,
> "Interrupt register 0x%x is not zero: 0x%08x\n",
> reg.addr, val);
>- xe_mmio_write32(gt, reg, 0xffffffff);
>- xe_mmio_read32(gt, reg);
>- xe_mmio_write32(gt, reg, 0xffffffff);
>- xe_mmio_read32(gt, reg);
>+ xe_mmio_write32(mmio, reg, 0xffffffff);
>+ xe_mmio_read32(mmio, reg);
>+ xe_mmio_write32(mmio, reg, 0xffffffff);
>+ xe_mmio_read32(mmio, reg);
> }
>
> /*
> * Unmask and enable the specified interrupts. Does not check current state,
> * so any bits not specified here will become masked and disabled.
> */
>-static void unmask_and_enable(struct xe_gt *gt, u32 irqregs, u32 bits)
>+static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)
> {
>+ struct xe_gt *mmio = tile->primary_gt;
>+
> /*
> * If we're just enabling an interrupt now, it shouldn't already
> * be raised in the IIR.
> */
>- assert_iir_is_zero(gt, IIR(irqregs));
>+ assert_iir_is_zero(mmio, IIR(irqregs));
>
>- xe_mmio_write32(gt, IER(irqregs), bits);
>- xe_mmio_write32(gt, IMR(irqregs), ~bits);
>+ xe_mmio_write32(mmio, IER(irqregs), bits);
>+ xe_mmio_write32(mmio, IMR(irqregs), ~bits);
>
> /* Posting read */
>- xe_mmio_read32(gt, IMR(irqregs));
>+ xe_mmio_read32(mmio, IMR(irqregs));
> }
>
> /* Mask and disable all interrupts. */
>-static void mask_and_disable(struct xe_gt *gt, u32 irqregs)
>+static void mask_and_disable(struct xe_tile *tile, u32 irqregs)
> {
>- xe_mmio_write32(gt, IMR(irqregs), ~0);
>+ struct xe_gt *mmio = tile->primary_gt;
>+
>+ xe_mmio_write32(mmio, IMR(irqregs), ~0);
> /* Posting read */
>- xe_mmio_read32(gt, IMR(irqregs));
>+ xe_mmio_read32(mmio, IMR(irqregs));
>
>- xe_mmio_write32(gt, IER(irqregs), 0);
>+ xe_mmio_write32(mmio, IER(irqregs), 0);
>
> /* IIR can theoretically queue up two events. Be paranoid. */
>- xe_mmio_write32(gt, IIR(irqregs), ~0);
>- xe_mmio_read32(gt, IIR(irqregs));
>- xe_mmio_write32(gt, IIR(irqregs), ~0);
>- xe_mmio_read32(gt, IIR(irqregs));
>+ xe_mmio_write32(mmio, IIR(irqregs), ~0);
>+ xe_mmio_read32(mmio, IIR(irqregs));
>+ xe_mmio_write32(mmio, IIR(irqregs), ~0);
>+ xe_mmio_read32(mmio, IIR(irqregs));
> }
>
>-static u32 xelp_intr_disable(struct xe_gt *gt)
>+static u32 xelp_intr_disable(struct xe_device *xe)
> {
>- xe_mmio_write32(gt, GFX_MSTR_IRQ, 0);
>+ struct xe_gt *mmio = xe_root_mmio_gt(xe);
>+
>+ xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0);
>
> /*
> * Now with master disabled, get a sample of level indications
>@@ -88,36 +94,41 @@ static u32 xelp_intr_disable(struct xe_gt *gt)
> * New indications can and will light up during processing,
> * and will generate new interrupt after enabling master.
> */
>- return xe_mmio_read32(gt, GFX_MSTR_IRQ);
>+ return xe_mmio_read32(mmio, GFX_MSTR_IRQ);
> }
>
> static u32
>-gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
>+gu_misc_irq_ack(struct xe_device *xe, const u32 master_ctl)
> {
>+ struct xe_gt *mmio = xe_root_mmio_gt(xe);
> u32 iir;
>
> if (!(master_ctl & GU_MISC_IRQ))
> return 0;
>
>- iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET));
>+ iir = xe_mmio_read32(mmio, IIR(GU_MISC_IRQ_OFFSET));
> if (likely(iir))
>- xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET), iir);
>+ xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir);
>
> return iir;
> }
>
>-static inline void xelp_intr_enable(struct xe_gt *gt, bool stall)
>+static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
> {
>- xe_mmio_write32(gt, GFX_MSTR_IRQ, MASTER_IRQ);
>+ struct xe_gt *mmio = xe_root_mmio_gt(xe);
>+
>+ xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ);
> if (stall)
>- xe_mmio_read32(gt, GFX_MSTR_IRQ);
>+ xe_mmio_read32(mmio, GFX_MSTR_IRQ);
> }
>
>-static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
>+static void gt_irq_postinstall(struct xe_tile *tile)
> {
>+ struct xe_device *xe = tile_to_xe(tile);
>+ struct xe_gt *mmio = tile->primary_gt;
> u32 irqs, dmask, smask;
>- u32 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
>- u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
>+ u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COMPUTE);
>+ u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COPY);
>
> if (xe_device_guc_submission_enabled(xe)) {
> irqs = GT_RENDER_USER_INTERRUPT |
>@@ -133,57 +144,57 @@ static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> smask = irqs << 16;
>
> /* Enable RCS, BCS, VCS and VECS class interrupts. */
>- xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
>- xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
>+ xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
>+ xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
> if (ccs_mask)
>- xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
>+ xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
>
> /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
>- xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
>- xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
>+ xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
>+ xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
> if (bcs_mask & (BIT(1)|BIT(2)))
>- xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
>+ xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
> if (bcs_mask & (BIT(3)|BIT(4)))
>- xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
>+ xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
> if (bcs_mask & (BIT(5)|BIT(6)))
>- xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
>+ xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
> if (bcs_mask & (BIT(7)|BIT(8)))
>- xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
>- xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
>- xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
>- xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
>+ xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
>+ xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
>+ xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
>+ xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
> if (ccs_mask & (BIT(0)|BIT(1)))
>- xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
>+ xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
> if (ccs_mask & (BIT(2)|BIT(3)))
>- xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
>+ xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
>
> /*
> * RPS interrupts will get enabled/disabled on demand when RPS itself
> * is enabled/disabled.
> */
> /* TODO: gt->pm_ier, gt->pm_imr */
>- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
>- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
>+ xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);
>
> /* Same thing for GuC interrupts */
>- xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
>- xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);
>+ xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
> }
>
>-static void xelp_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
>+static void xelp_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
> {
> /* TODO: PCH */
>
>- gt_irq_postinstall(xe, gt);
>+ gt_irq_postinstall(tile);
>
>- unmask_and_enable(gt, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
>+ unmask_and_enable(tile, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
>
>- xelp_intr_enable(gt, true);
>+ xelp_intr_enable(xe, true);
> }
>
> static u32
> gt_engine_identity(struct xe_device *xe,
>- struct xe_gt *gt,
>+ struct xe_gt *mmio,
> const unsigned int bank,
> const unsigned int bit)
> {
>@@ -192,7 +203,7 @@ gt_engine_identity(struct xe_device *xe,
>
> lockdep_assert_held(&xe->irq.lock);
>
>- xe_mmio_write32(gt, IIR_REG_SELECTOR(bank), BIT(bit));
>+ xe_mmio_write32(mmio, IIR_REG_SELECTOR(bank), BIT(bit));
>
> /*
> * NB: Specs do not specify how long to spin wait,
>@@ -200,7 +211,7 @@ gt_engine_identity(struct xe_device *xe,
> */
> timeout_ts = (local_clock() >> 10) + 100;
> do {
>- ident = xe_mmio_read32(gt, INTR_IDENTITY_REG(bank));
>+ ident = xe_mmio_read32(mmio, INTR_IDENTITY_REG(bank));
> } while (!(ident & INTR_DATA_VALID) &&
> !time_after32(local_clock() >> 10, timeout_ts));
>
>@@ -210,7 +221,7 @@ gt_engine_identity(struct xe_device *xe,
> return 0;
> }
>
>- xe_mmio_write32(gt, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
>+ xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
>
> return ident;
> }
>@@ -232,10 +243,32 @@ gt_other_irq_handler(struct xe_gt *gt, const u8 instance, const u16 iir)
> }
> }
>
>-static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
>+static struct xe_gt *pick_engine_gt(struct xe_tile *tile,
>+ enum xe_engine_class class,
>+ unsigned int instance)
>+{
>+ struct xe_device *xe = tile_to_xe(tile);
>+
>+ if (MEDIA_VER(xe) < 13)
>+ return tile->primary_gt;
>+
>+ if (class == XE_ENGINE_CLASS_VIDEO_DECODE ||
>+ class == XE_ENGINE_CLASS_VIDEO_ENHANCE)
>+ return tile->media_gt;
>+
>+ if (class == XE_ENGINE_CLASS_OTHER &&
>+ instance == OTHER_MEDIA_GUC_INSTANCE)
>+ return tile->media_gt;
>+
>+ return tile->primary_gt;
>+}
>+
>+static void gt_irq_handler(struct xe_tile *tile,
> u32 master_ctl, long unsigned int *intr_dw,
> u32 *identity)
> {
>+ struct xe_device *xe = tile_to_xe(tile);
>+ struct xe_gt *mmio = tile->primary_gt;
> unsigned int bank, bit;
> u16 instance, intr_vec;
> enum xe_engine_class class;
>@@ -247,27 +280,26 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> if (!(master_ctl & GT_DW_IRQ(bank)))
> continue;
>
>- if (!xe_gt_is_media_type(gt)) {
>- intr_dw[bank] =
>- xe_mmio_read32(gt, GT_INTR_DW(bank));
>- for_each_set_bit(bit, intr_dw + bank, 32)
>- identity[bit] = gt_engine_identity(xe, gt,
>- bank, bit);
>- xe_mmio_write32(gt, GT_INTR_DW(bank),
>- intr_dw[bank]);
>- }
>+ intr_dw[bank] = xe_mmio_read32(mmio, GT_INTR_DW(bank));
>+ for_each_set_bit(bit, intr_dw + bank, 32)
>+ identity[bit] = gt_engine_identity(xe, mmio, bank, bit);
>+ xe_mmio_write32(mmio, GT_INTR_DW(bank), intr_dw[bank]);
>
> for_each_set_bit(bit, intr_dw + bank, 32) {
>+ struct xe_gt *engine_gt;
>+
> class = INTR_ENGINE_CLASS(identity[bit]);
> instance = INTR_ENGINE_INSTANCE(identity[bit]);
> intr_vec = INTR_ENGINE_INTR(identity[bit]);
>
>+ engine_gt = pick_engine_gt(tile, class, instance);
>+
> if (class == XE_ENGINE_CLASS_OTHER) {
>- gt_other_irq_handler(gt, instance, intr_vec);
>+ gt_other_irq_handler(engine_gt, instance, intr_vec);
> continue;
> }
>
>- hwe = xe_gt_hw_engine(gt, class, instance, false);
>+ hwe = xe_gt_hw_engine(engine_gt, class, instance, false);
> if (!hwe)
> continue;
>
>@@ -285,24 +317,24 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> static irqreturn_t xelp_irq_handler(int irq, void *arg)
> {
> struct xe_device *xe = arg;
>- struct xe_gt *gt = xe_root_mmio_gt(xe);
>+ struct xe_tile *tile = xe_device_get_root_tile(xe);
> u32 master_ctl, gu_misc_iir;
> long unsigned int intr_dw[2];
> u32 identity[32];
>
>- master_ctl = xelp_intr_disable(gt);
>+ master_ctl = xelp_intr_disable(xe);
> if (!master_ctl) {
>- xelp_intr_enable(gt, false);
>+ xelp_intr_enable(xe, false);
> return IRQ_NONE;
> }
>
>- gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
>+ gt_irq_handler(tile, master_ctl, intr_dw, identity);
>
> xe_display_irq_handler(xe, master_ctl);
>
>- gu_misc_iir = gu_misc_irq_ack(gt, master_ctl);
>+ gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
>
>- xelp_intr_enable(gt, false);
>+ xelp_intr_enable(xe, false);
>
> xe_display_irq_enable(xe, gu_misc_iir);
>
>@@ -311,38 +343,38 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>
> static u32 dg1_intr_disable(struct xe_device *xe)
> {
>- struct xe_gt *gt = xe_root_mmio_gt(xe);
>+ struct xe_gt *mmio = xe_root_mmio_gt(xe);
> u32 val;
>
> /* First disable interrupts */
>- xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, 0);
>+ xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0);
>
> /* Get the indication levels and ack the master unit */
>- val = xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
>+ val = xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
> if (unlikely(!val))
> return 0;
>
>- xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, val);
>+ xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, val);
>
> return val;
> }
>
> static void dg1_intr_enable(struct xe_device *xe, bool stall)
> {
>- struct xe_gt *gt = xe_root_mmio_gt(xe);
>+ struct xe_gt *mmio = xe_root_mmio_gt(xe);
>
>- xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
>+ xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
> if (stall)
>- xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
>+ xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
> }
>
>-static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
>+static void dg1_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
> {
>- gt_irq_postinstall(xe, gt);
>+ gt_irq_postinstall(tile);
>
>- unmask_and_enable(gt, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
>+ unmask_and_enable(tile, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
>
>- if (gt->info.id == XE_GT0)
>+ if (tile->id == 0)
> dg1_intr_enable(xe, true);
> }
>
>@@ -354,8 +386,8 @@ static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> static irqreturn_t dg1_irq_handler(int irq, void *arg)
> {
> struct xe_device *xe = arg;
>- struct xe_gt *gt;
>- u32 master_tile_ctl, master_ctl = 0, tile0_master_ctl = 0, gu_misc_iir;
>+ struct xe_tile *tile;
>+ u32 master_tile_ctl, master_ctl = 0, gu_misc_iir = 0;
> long unsigned int intr_dw[2];
> u32 identity[32];
> u8 id;
>@@ -368,12 +400,13 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> return IRQ_NONE;
> }
>
>- for_each_gt(gt, xe, id) {
>- if ((master_tile_ctl & DG1_MSTR_TILE(gt_to_tile(gt)->id)) == 0)
>+ for_each_tile(tile, xe, id) {
>+ struct xe_gt *mmio = tile->primary_gt;
>+
>+ if ((master_tile_ctl & DG1_MSTR_TILE(tile->id)) == 0)
> continue;
>
>- if (!xe_gt_is_media_type(gt))
>- master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ);
>+ master_ctl = xe_mmio_read32(mmio, GFX_MSTR_IRQ);
>
> /*
> * We might be in irq handler just when PCIe DPC is initiated
>@@ -381,124 +414,125 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> * irq as device is inaccessible.
> */
> if (master_ctl == REG_GENMASK(31, 0)) {
>- dev_dbg(gt_to_xe(gt)->drm.dev,
>+ dev_dbg(tile_to_xe(tile)->drm.dev,
> "Ignore this IRQ as device might be in DPC containment.\n");
> return IRQ_HANDLED;
> }
>
>- if (!xe_gt_is_media_type(gt))
>- xe_mmio_write32(gt, GFX_MSTR_IRQ, master_ctl);
>- gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
>+ xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);
>+
>+ gt_irq_handler(tile, master_ctl, intr_dw, identity);
>
> /*
>- * Save primary tile's master interrupt register for display
>- * processing below.
>+ * Display interrupts (including display backlight operations
>+ * that get reported as Gunit GSE) would only be hooked up to
>+ * the primary tile.
> */
>- if (id == 0)
>- tile0_master_ctl = master_ctl;
>+ if (id == 0) {
>+ xe_display_irq_handler(xe, master_ctl);
>+ gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
>+ }
> }
>
>- xe_display_irq_handler(xe, tile0_master_ctl);
>-
>- /* Gunit GSE interrupts can trigger display backlight operations */
>- gu_misc_iir = gu_misc_irq_ack(gt, tile0_master_ctl);
>-
> dg1_intr_enable(xe, false);
>-
> xe_display_irq_enable(xe, gu_misc_iir);
>
> return IRQ_HANDLED;
> }
>
>-static void gt_irq_reset(struct xe_gt *gt)
>+static void gt_irq_reset(struct xe_tile *tile)
> {
>- u32 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
>- u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
>+ struct xe_gt *mmio = tile->primary_gt;
>+
>+ u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
>+ XE_ENGINE_CLASS_COMPUTE);
>+ u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
>+ XE_ENGINE_CLASS_COPY);
>
> /* Disable RCS, BCS, VCS and VECS class engines. */
>- xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, 0);
>- xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, 0);
>+ xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, 0);
>+ xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, 0);
> if (ccs_mask)
>- xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, 0);
>+ xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, 0);
>
> /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
>- xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~0);
>- xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~0);
> if (bcs_mask & (BIT(1)|BIT(2)))
>- xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
> if (bcs_mask & (BIT(3)|BIT(4)))
>- xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
> if (bcs_mask & (BIT(5)|BIT(6)))
>- xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
> if (bcs_mask & (BIT(7)|BIT(8)))
>- xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
>- xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~0);
>- xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~0);
>- xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~0);
> if (ccs_mask & (BIT(0)|BIT(1)))
>- xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~0);
> if (ccs_mask & (BIT(2)|BIT(3)))
>- xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~0);
>
>- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
>- xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
>- xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
>- xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
>+ xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);
>+ xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);
>+ xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
> }
>
>-static void xelp_irq_reset(struct xe_gt *gt)
>+static void xelp_irq_reset(struct xe_tile *tile)
> {
>- xelp_intr_disable(gt);
>+ xelp_intr_disable(tile_to_xe(tile));
>
>- gt_irq_reset(gt);
>+ gt_irq_reset(tile);
>
>- mask_and_disable(gt, GU_MISC_IRQ_OFFSET);
>- mask_and_disable(gt, PCU_IRQ_OFFSET);
>+ mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
>+ mask_and_disable(tile, PCU_IRQ_OFFSET);
> }
>
>-static void dg1_irq_reset(struct xe_gt *gt)
>+static void dg1_irq_reset(struct xe_tile *tile)
> {
>- if (gt->info.id == 0)
>- dg1_intr_disable(gt_to_xe(gt));
>+ if (tile->id == 0)
>+ dg1_intr_disable(tile_to_xe(tile));
>
>- gt_irq_reset(gt);
>+ gt_irq_reset(tile);
>
>- mask_and_disable(gt, GU_MISC_IRQ_OFFSET);
>- mask_and_disable(gt, PCU_IRQ_OFFSET);
>+ mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
>+ mask_and_disable(tile, PCU_IRQ_OFFSET);
> }
>
> static void xe_irq_reset(struct xe_device *xe)
> {
>- struct xe_gt *gt;
>+ struct xe_tile *tile;
> u8 id;
>
>- for_each_gt(gt, xe, id) {
>+ for_each_tile(tile, xe, id) {
> if (GRAPHICS_VERx100(xe) >= 1210)
>- dg1_irq_reset(gt);
>+ dg1_irq_reset(tile);
> else
>- xelp_irq_reset(gt);
>+ xelp_irq_reset(tile);
> }
>
> xe_display_irq_reset(xe);
> }
>
>-void xe_gt_irq_postinstall(struct xe_gt *gt)
>+void xe_gt_irq_postinstall(struct xe_tile *tile)
> {
>- struct xe_device *xe = gt_to_xe(gt);
>+ struct xe_device *xe = tile_to_xe(tile);
>
> if (GRAPHICS_VERx100(xe) >= 1210)
>- dg1_irq_postinstall(xe, gt);
>+ dg1_irq_postinstall(xe, tile);
> else
>- xelp_irq_postinstall(xe, gt);
>+ xelp_irq_postinstall(xe, tile);
> }
>
> static void xe_irq_postinstall(struct xe_device *xe)
> {
>- struct xe_gt *gt;
>+ struct xe_tile *tile;
> u8 id;
>
>- for_each_gt(gt, xe, id)
>- xe_gt_irq_postinstall(gt);
>+ for_each_tile(tile, xe, id)
>+ xe_gt_irq_postinstall(tile);
>
> xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));
> }
>diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
>index 34ecf22b32d3..69113c21e1cd 100644
>--- a/drivers/gpu/drm/xe/xe_irq.h
>+++ b/drivers/gpu/drm/xe/xe_irq.h
>@@ -7,10 +7,10 @@
> #define _XE_IRQ_H_
>
> struct xe_device;
>-struct xe_gt;
>+struct xe_tile;
>
> int xe_irq_install(struct xe_device *xe);
>-void xe_gt_irq_postinstall(struct xe_gt *gt);
>+void xe_gt_irq_postinstall(struct xe_tile *tile);
> void xe_irq_shutdown(struct xe_device *xe);
> void xe_irq_suspend(struct xe_device *xe);
> void xe_irq_resume(struct xe_device *xe);
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 24/30] drm/xe: Replace xe_gt_irq_postinstall with xe_irq_enable_hwe
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 24/30] drm/xe: Replace xe_gt_irq_postinstall with xe_irq_enable_hwe Matt Roper
@ 2023-05-26 22:20 ` Lucas De Marchi
0 siblings, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-26 22:20 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, May 19, 2023 at 04:18:21PM -0700, Matt Roper wrote:
>The majority of xe_gt_irq_postinstall() is really focused on the
>hardware engine interrupts; other GT-related interrupts such as the GuC
>are enabled/disabled independently. Renaming the function and making it
>truly GT-specific will make it more clear what the intended focus is.
>
>Disabling/masking of other interrupts (such as GuC interrupts) is
>unnecessary since that has already happened during the irq_reset stage,
>and doing so will become harmful once the media GT is re-enabled since
>calls to xe_gt_irq_postinstall during media GT initialization would
>incorrectly disable the primary GT's GuC interrupts.
>
>Also, since this function is called from gt_fw_domain_init(), it's not
>necessary to also call it earlier during xe_irq_postinstall; just
>xe_irq_resume to handle runtime resume should be sufficient.
>
>v2:
> - Drop unnecessary !gt check. (Lucas)
> - Reword some comments about enable/unmask for clarity. (Lucas)
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/xe/xe_gt.c | 4 +-
> drivers/gpu/drm/xe/xe_hw_engine.c | 1 +
> drivers/gpu/drm/xe/xe_irq.c | 87 +++++++++++++++----------------
> drivers/gpu/drm/xe/xe_irq.h | 3 +-
> 4 files changed, 48 insertions(+), 47 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>index 290935e46059..b7bf8c01b4fe 100644
>--- a/drivers/gpu/drm/xe/xe_gt.c
>+++ b/drivers/gpu/drm/xe/xe_gt.c
>@@ -303,8 +303,8 @@ static int gt_fw_domain_init(struct xe_gt *gt)
> /* XXX: Fake that we pull the engine mask from hwconfig blob */
> gt->info.engine_mask = gt->info.__engine_mask;
>
>- /* Enables per hw engine IRQs */
>- xe_gt_irq_postinstall(gt_to_tile(gt));
>+ /* Enable per hw engine IRQs */
>+ xe_irq_enable_hwe(gt);
>
> /* Rerun MCR init as we now have hw engine list */
> xe_gt_mcr_init(gt);
>diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>index ab25513b753c..5a345b24b9a2 100644
>--- a/drivers/gpu/drm/xe/xe_hw_engine.c
>+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>@@ -17,6 +17,7 @@
> #include "xe_gt.h"
> #include "xe_gt_topology.h"
> #include "xe_hw_fence.h"
>+#include "xe_irq.h"
> #include "xe_lrc.h"
> #include "xe_macros.h"
> #include "xe_mmio.h"
>diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>index 85bb9bd6b6be..b4ed1e4a3388 100644
>--- a/drivers/gpu/drm/xe/xe_irq.c
>+++ b/drivers/gpu/drm/xe/xe_irq.c
>@@ -122,13 +122,12 @@ static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
> xe_mmio_read32(mmio, GFX_MSTR_IRQ);
> }
>
>-void xe_gt_irq_postinstall(struct xe_tile *tile)
>+/* Enable/unmask the HWE interrupts for a specific GT's engines. */
>+void xe_irq_enable_hwe(struct xe_gt *gt)
> {
>- struct xe_device *xe = tile_to_xe(tile);
>- struct xe_gt *mmio = tile->primary_gt;
>+ struct xe_device *xe = gt_to_xe(gt);
>+ u32 ccs_mask, bcs_mask;
> u32 irqs, dmask, smask;
>- u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COMPUTE);
>- u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COPY);
>
> if (xe_device_guc_submission_enabled(xe)) {
> irqs = GT_RENDER_USER_INTERRUPT |
>@@ -140,45 +139,44 @@ void xe_gt_irq_postinstall(struct xe_tile *tile)
> GT_WAIT_SEMAPHORE_INTERRUPT;
> }
>
>+ ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
>+ bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
>+
> dmask = irqs << 16 | irqs;
> smask = irqs << 16;
>
>- /* Enable RCS, BCS, VCS and VECS class interrupts. */
>- xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
>- xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
>- if (ccs_mask)
>- xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
>+ if (!xe_gt_is_media_type(gt)) {
>+ /* Enable interrupts for each engine class */
>+ xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
>+ if (ccs_mask)
>+ xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
>
>- /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
>- xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
>- xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
>- if (bcs_mask & (BIT(1)|BIT(2)))
>- xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
>- if (bcs_mask & (BIT(3)|BIT(4)))
>- xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
>- if (bcs_mask & (BIT(5)|BIT(6)))
>- xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
>- if (bcs_mask & (BIT(7)|BIT(8)))
>- xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
>- xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
>- xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
>- xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
>- if (ccs_mask & (BIT(0)|BIT(1)))
>- xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
>- if (ccs_mask & (BIT(2)|BIT(3)))
>- xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
>+ /* Unmask interrupts for each engine instance */
>+ xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
>+ xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
>+ if (bcs_mask & (BIT(1)|BIT(2)))
>+ xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
>+ if (bcs_mask & (BIT(3)|BIT(4)))
>+ xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
>+ if (bcs_mask & (BIT(5)|BIT(6)))
>+ xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
>+ if (bcs_mask & (BIT(7)|BIT(8)))
>+ xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
>+ if (ccs_mask & (BIT(0)|BIT(1)))
>+ xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
>+ if (ccs_mask & (BIT(2)|BIT(3)))
>+ xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
>+ }
>
>- /*
>- * RPS interrupts will get enabled/disabled on demand when RPS itself
>- * is enabled/disabled.
>- */
>- /* TODO: gt->pm_ier, gt->pm_imr */
>- xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
>- xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);
>+ if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
>+ /* Enable interrupts for each engine class */
>+ xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
>
>- /* Same thing for GuC interrupts */
>- xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);
>- xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
>+ /* Unmask interrupts for each engine instance */
>+ xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
>+ xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
>+ xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
>+ }
> }
>
> static u32
>@@ -497,12 +495,6 @@ static void xe_irq_reset(struct xe_device *xe)
>
> static void xe_irq_postinstall(struct xe_device *xe)
> {
>- struct xe_tile *tile;
>- u8 id;
>-
>- for_each_tile(tile, xe, id)
>- xe_gt_irq_postinstall(tile);
>-
> xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));
>
> /*
>@@ -591,9 +583,16 @@ void xe_irq_suspend(struct xe_device *xe)
>
> void xe_irq_resume(struct xe_device *xe)
> {
>+ struct xe_gt *gt;
>+ int id;
>+
> spin_lock_irq(&xe->irq.lock);
> xe->irq.enabled = true;
> xe_irq_reset(xe);
> xe_irq_postinstall(xe);
>+
>+ for_each_gt(gt, xe, id)
>+ xe_irq_enable_hwe(gt);
>+
> spin_unlock_irq(&xe->irq.lock);
> }
>diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
>index 69113c21e1cd..bc42bc90d967 100644
>--- a/drivers/gpu/drm/xe/xe_irq.h
>+++ b/drivers/gpu/drm/xe/xe_irq.h
>@@ -8,11 +8,12 @@
>
> struct xe_device;
> struct xe_tile;
>+struct xe_gt;
>
> int xe_irq_install(struct xe_device *xe);
>-void xe_gt_irq_postinstall(struct xe_tile *tile);
> void xe_irq_shutdown(struct xe_device *xe);
> void xe_irq_suspend(struct xe_device *xe);
> void xe_irq_resume(struct xe_device *xe);
>+void xe_irq_enable_hwe(struct xe_gt *gt);
>
> #endif
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 27/30] drm/xe: Allow GT looping and lookup on standalone media
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 27/30] drm/xe: Allow GT looping and lookup on standalone media Matt Roper
@ 2023-05-26 22:37 ` Lucas De Marchi
2023-05-30 16:41 ` Matt Roper
0 siblings, 1 reply; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-26 22:37 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, May 19, 2023 at 04:18:24PM -0700, Matt Roper wrote:
>Allow xe_device_get_gt() and for_each_gt() to operate as expected on
>platforms with standalone media.
>
>FIXME: We need to figure out a consistent ID scheme for GTs. At the
>moment our platforms either have multi-tile (i.e., PVC) or standalone
>media (MTL) but not both. If a future platform supports both of these
>capabilities at the same time, how will we number the GTs of the
>platform? primary-primary-media-media? primary-media-primary-media?
>For that matter should we even still be exposing the concept of 'GT' to
>userspace or should that switch to tile instead (and keep the hardware's
>separation of render and media an internal implementation detail like it
>is on i915)? If we only expose tiles to userspace and not GTs, then we
>may not even need per-GT ID numbers anymore.
is this something to leave on the commit or something to solve now?
I think userspace may care about what tile the GT is located, but not
much about the order... I think just making it a depth-first on each
tile would be ok and we can have a tile as a gt attribute.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/xe_device.h | 27 +++++++++++++++++++++------
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
>index 156c62ac0381..e0085fcd3f47 100644
>--- a/drivers/gpu/drm/xe/xe_device.h
>+++ b/drivers/gpu/drm/xe/xe_device.h
>@@ -55,16 +55,27 @@ static inline struct xe_tile *xe_device_get_root_tile(struct xe_device *xe)
>
> static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
> {
>+ struct xe_tile *root_tile = xe_device_get_root_tile(xe);
> struct xe_gt *gt;
>
>- XE_BUG_ON(gt_id > XE_MAX_TILES_PER_DEVICE);
>+ if (drm_WARN_ON(&xe->drm, gt_id > XE_MAX_TILES_PER_DEVICE))
this condition is odd.
>+ return root_tile->primary_gt;
>
>- gt = xe->tiles[gt_id].primary_gt;
>- if (drm_WARN_ON(&xe->drm, !gt))
>+ /*
>+ * FIXME: This only works for now because multi-tile and standalone
>+ * media are mutually exclusive on the platforms we have today.
>+ */
>+ if (MEDIA_VER(xe) >= 13) {
>+ gt = gt_id ? root_tile->media_gt : root_tile->primary_gt;
>+ } else {
>+ gt = xe->tiles[gt_id].primary_gt;
>+ }
I would expect something like:
for_each_tile(...)
for_each_gt(...)
if (gt->id == gt_id)
return gt_id
which could be optimized by reserving the gt numbers
with XE_MAX_TILES_PER_DEVICE
#define XE_MAX_GTS_PER_TILE 2
tile = gt_id / XE_MAX_GTS_PER_TILE;
gt = gt_id % XE_MAX_GTS_PER_TILE;
return !gt ? xe->tiles[tile].primary_gt : xe->tiles[tile].media_gt;
but hey... why are we not keeping a gt[] to make things simpler instead
of calling them explicitly primary_gt/media_gt?
Lucas De Marchi
>+
>+ if (!gt)
> return NULL;
>
>- XE_BUG_ON(gt->info.id != gt_id);
>- XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
>+ drm_WARN_ON(&xe->drm, gt->info.id != gt_id);
>+ drm_WARN_ON(&xe->drm, gt->info.type == XE_GT_TYPE_UNINITIALIZED);
>
> return gt;
> }
>@@ -98,8 +109,12 @@ static inline void xe_device_guc_submission_disable(struct xe_device *xe)
> for ((id__) = 0; (id__) < (xe__)->info.tile_count; (id__++)) \
> for_each_if ((tile__) = &(xe__)->tiles[(id__)])
>
>+/*
>+ * FIXME: This only works for now since multi-tile and standalone media
>+ * happen to be mutually exclusive. Future platforms may change this...
>+ */
> #define for_each_gt(gt__, xe__, id__) \
>- for ((id__) = 0; (id__) < (xe__)->info.tile_count; (id__++)) \
>+ for ((id__) = 0; (id__) < (xe__)->info.tile_count + (MEDIA_VER(xe__) >= 13 ? 1 : 0); (id__++)) \
> for_each_if ((gt__) = xe_device_get_gt((xe__), (id__)))
>
> static inline struct xe_force_wake * gt_to_fw(struct xe_gt *gt)
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 29/30] drm/xe: Reinstate media GT support
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 29/30] drm/xe: Reinstate media GT support Matt Roper
@ 2023-05-26 22:46 ` Lucas De Marchi
0 siblings, 0 replies; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-26 22:46 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, May 19, 2023 at 04:18:26PM -0700, Matt Roper wrote:
>Now that tiles and GTs are handled separately and other prerequisite
>changes are in place, we're ready to re-enable the media GT.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 8 ++++++++
> drivers/gpu/drm/xe/xe_pci.c | 26 +++++++++++++++++++++++++-
> 2 files changed, 33 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>index 4d87f1fe010d..26247725e0d8 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>@@ -8,6 +8,14 @@
>
> #include "regs/xe_reg_defs.h"
>
>+/*
>+ * The GSI register range [0x0 - 0x40000) is replicated at a higher offset
>+ * for the media GT. xe_mmio and xe_gt_mcr functions will automatically
>+ * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT.
>+ */
>+#define MEDIA_GT_GSI_OFFSET 0x380000
>+#define MEDIA_GT_GSI_LENGTH 0x40000
>+
> /* RPM unit config (Gen8+) */
> #define RPM_CONFIG0 XE_REG(0xd00)
> #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index bc0ed2a0e44f..890625598209 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -552,7 +552,31 @@ static int xe_info_init(struct xe_device *xe,
> if (MEDIA_VER(xe) < 13 && media_desc)
> gt->info.__engine_mask |= media_desc->hw_engine_mask;
>
>- /* TODO: Init media GT, if present */
>+ if (MEDIA_VER(xe) < 13 || !media_desc)
>+ continue;
>+
>+ /*
>+ * Allocate and setup media GT for platforms with standalone
>+ * media.
>+ */
>+ tile->media_gt = xe_gt_alloc(tile);
>+ if (IS_ERR(tile->media_gt))
>+ return PTR_ERR(tile->media_gt);
>+
>+ gt = tile->media_gt;
>+ gt->info.type = XE_GT_TYPE_MEDIA;
>+ gt->info.__engine_mask = media_desc->hw_engine_mask;
>+ gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET;
>+ gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH;
>+
>+ /*
>+ * FIXME: At the moment multi-tile and standalone media are
>+ * mutually exclusive on current platforms. We'll need to
>+ * come up with a better way to number GTs if we ever wind
>+ * up with platforms that support both together.
>+ */
>+ drm_WARN_ON(&xe->drm, id != 0);
>+ gt->info.id = 1;
> }
>
> return 0;
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 30/30] drm/xe: Add kerneldoc description of multi-tile devices
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 30/30] drm/xe: Add kerneldoc description of multi-tile devices Matt Roper
@ 2023-05-26 22:52 ` Lucas De Marchi
2023-05-27 0:22 ` Matt Roper
0 siblings, 1 reply; 54+ messages in thread
From: Lucas De Marchi @ 2023-05-26 22:52 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, May 19, 2023 at 04:18:27PM -0700, Matt Roper wrote:
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> Documentation/gpu/xe/index.rst | 1 +
> Documentation/gpu/xe/xe_tile.rst | 14 ++++++++
> drivers/gpu/drm/xe/xe_tile.c | 57 ++++++++++++++++++++++++++++++++
> 3 files changed, 72 insertions(+)
> create mode 100644 Documentation/gpu/xe/xe_tile.rst
>
>diff --git a/Documentation/gpu/xe/index.rst b/Documentation/gpu/xe/index.rst
>index 2fddf9ed251e..5c4d6bb370f3 100644
>--- a/Documentation/gpu/xe/index.rst
>+++ b/Documentation/gpu/xe/index.rst
>@@ -21,3 +21,4 @@ DG2, etc is provided to prototype the driver.
> xe_wa
> xe_rtp
> xe_firmware
>+ xe_tile
>diff --git a/Documentation/gpu/xe/xe_tile.rst b/Documentation/gpu/xe/xe_tile.rst
>new file mode 100644
>index 000000000000..c33f68dd95b6
>--- /dev/null
>+++ b/Documentation/gpu/xe/xe_tile.rst
>@@ -0,0 +1,14 @@
>+.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>+
>+==================
>+Multi-tile Devices
>+==================
>+
>+.. kernel-doc:: drivers/gpu/drm/xe/xe_tile.c
>+ :doc: Multi-tile Design
>+
>+Internal API
>+============
>+
>+.. kernel-doc:: drivers/gpu/drm/xe/xe_tile.c
>+ :internal:
>diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
>index 908eec5c17d9..d2654b78cfb4 100644
>--- a/drivers/gpu/drm/xe/xe_tile.c
>+++ b/drivers/gpu/drm/xe/xe_tile.c
>@@ -12,6 +12,63 @@
> #include "xe_tile.h"
> #include "xe_ttm_vram_mgr.h"
>
>+/**
>+ * DOC: Multi-tile Design
>+ *
>+ * Different vendors use the term "tile" a bit differently, but in the Intel
>+ * world, a 'tile' is pretty close to what most people would think of as being
>+ * a complete GPU. When multiple GPUs are placed behind a single PCI device,
>+ * that's what is referred to as a "multi-tile device." In such cases, pretty
>+ * much all hardware is replicated per-tile, although certain responsibilities
>+ * like PCI communication, reporting of interrupts to the OS, etc. are handled
>+ * solely by the "root tile." A multi-tile platform takes care of tying the
". instead of ."
>+ * tiles together in a way such that interrupt notifications from remote tiles
>+ * are forwarded to the root tile, the per-tile vram is combined into a single
>+ * address space, etc.
>+ *
>+ * In contrast, a "GT" (which officially stands for "Graphics Technology") is
>+ * the subset of a GPU/tile that is responsible for implementing graphics
>+ * and/or media operations. The GT is where a lot of the driver implementation
>+ * happens since it's where the hardware engines, the execution units, and the
>+ * GuC all reside.
>+ *
>+ * Historically most Intel devices were single-tile devices that contained a
>+ * single GT. PVC is an example of an Intel platform built on a multi-tile
>+ * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only
>+ * has a single GT. In contrast, platforms like MTL that have separate chips
>+ * for render and media IP are still only a single logical GPU, but the
>+ * graphics and media IP blocks are exposed each exposed as a separate GT
too many exposed words here
other than that,
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
thanks
Lucas De Marchi
>+ * within that single GPU. This is important from a software perspective
>+ * because multi-GT platforms like MTL only replicate a subset of the GPU
>+ * hardware and behave differently than multi-tile platforms like PVC where
>+ * nearly everything is replicated.
>+ *
>+ * Per-tile functionality (shared by all GTs within the tile):
>+ * - Complete 4MB MMIO space (containing SGunit/SoC registers, GT
>+ * registers, display registers, etc.)
>+ * - Global GTT
>+ * - VRAM (if discrete)
>+ * - Interrupt flows
>+ * - Migration context
>+ * - kernel batchbuffer pool
>+ * - Primary GT
>+ * - Media GT (if media version >= 13)
>+ *
>+ * Per-GT functionality:
>+ * - GuC
>+ * - Hardware engines
>+ * - Programmable hardware units (subslices, EUs)
>+ * - GSI subset of registers (multiple copies of these registers reside
>+ * within the complete MMIO space provided by the tile, but at different
>+ * offsets --- 0 for render, 0x380000 for media)
>+ * - Multicast register steering
>+ * - TLBs to cache page table translations
>+ * - Reset capability
>+ * - Low-level power management (e.g., C6)
>+ * - Clock frequency
>+ * - MOCS and PAT programming
>+ */
>+
> /**
> * xe_tile_alloc - Perform per-tile memory allocation
> * @tile: Tile to perform allocations for
>--
>2.40.0
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 30/30] drm/xe: Add kerneldoc description of multi-tile devices
2023-05-26 22:52 ` Lucas De Marchi
@ 2023-05-27 0:22 ` Matt Roper
0 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-27 0:22 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Fri, May 26, 2023 at 03:52:16PM -0700, Lucas De Marchi wrote:
> On Fri, May 19, 2023 at 04:18:27PM -0700, Matt Roper wrote:
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > Documentation/gpu/xe/index.rst | 1 +
> > Documentation/gpu/xe/xe_tile.rst | 14 ++++++++
> > drivers/gpu/drm/xe/xe_tile.c | 57 ++++++++++++++++++++++++++++++++
> > 3 files changed, 72 insertions(+)
> > create mode 100644 Documentation/gpu/xe/xe_tile.rst
> >
> > diff --git a/Documentation/gpu/xe/index.rst b/Documentation/gpu/xe/index.rst
> > index 2fddf9ed251e..5c4d6bb370f3 100644
> > --- a/Documentation/gpu/xe/index.rst
> > +++ b/Documentation/gpu/xe/index.rst
> > @@ -21,3 +21,4 @@ DG2, etc is provided to prototype the driver.
> > xe_wa
> > xe_rtp
> > xe_firmware
> > + xe_tile
> > diff --git a/Documentation/gpu/xe/xe_tile.rst b/Documentation/gpu/xe/xe_tile.rst
> > new file mode 100644
> > index 000000000000..c33f68dd95b6
> > --- /dev/null
> > +++ b/Documentation/gpu/xe/xe_tile.rst
> > @@ -0,0 +1,14 @@
> > +.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +
> > +==================
> > +Multi-tile Devices
> > +==================
> > +
> > +.. kernel-doc:: drivers/gpu/drm/xe/xe_tile.c
> > + :doc: Multi-tile Design
> > +
> > +Internal API
> > +============
> > +
> > +.. kernel-doc:: drivers/gpu/drm/xe/xe_tile.c
> > + :internal:
> > diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
> > index 908eec5c17d9..d2654b78cfb4 100644
> > --- a/drivers/gpu/drm/xe/xe_tile.c
> > +++ b/drivers/gpu/drm/xe/xe_tile.c
> > @@ -12,6 +12,63 @@
> > #include "xe_tile.h"
> > #include "xe_ttm_vram_mgr.h"
> >
> > +/**
> > + * DOC: Multi-tile Design
> > + *
> > + * Different vendors use the term "tile" a bit differently, but in the Intel
> > + * world, a 'tile' is pretty close to what most people would think of as being
> > + * a complete GPU. When multiple GPUs are placed behind a single PCI device,
> > + * that's what is referred to as a "multi-tile device." In such cases, pretty
> > + * much all hardware is replicated per-tile, although certain responsibilities
> > + * like PCI communication, reporting of interrupts to the OS, etc. are handled
> > + * solely by the "root tile." A multi-tile platform takes care of tying the
>
> ". instead of ."
Actually this one is correct as-is; periods at the end of sentences
always go inside the quotation marks (at least in English; not sure
about other languages).
https://www.grammar.com/periods-with-quotation-marks/
>
> > + * tiles together in a way such that interrupt notifications from remote tiles
> > + * are forwarded to the root tile, the per-tile vram is combined into a single
> > + * address space, etc.
> > + *
> > + * In contrast, a "GT" (which officially stands for "Graphics Technology") is
> > + * the subset of a GPU/tile that is responsible for implementing graphics
> > + * and/or media operations. The GT is where a lot of the driver implementation
> > + * happens since it's where the hardware engines, the execution units, and the
> > + * GuC all reside.
> > + *
> > + * Historically most Intel devices were single-tile devices that contained a
> > + * single GT. PVC is an example of an Intel platform built on a multi-tile
> > + * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only
> > + * has a single GT. In contrast, platforms like MTL that have separate chips
> > + * for render and media IP are still only a single logical GPU, but the
> > + * graphics and media IP blocks are exposed each exposed as a separate GT
>
> too many exposed words here
Good catch, thanks.
Matt
>
> other than that,
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> thanks
> Lucas De Marchi
>
> > + * within that single GPU. This is important from a software perspective
> > + * because multi-GT platforms like MTL only replicate a subset of the GPU
> > + * hardware and behave differently than multi-tile platforms like PVC where
> > + * nearly everything is replicated.
> > + *
> > + * Per-tile functionality (shared by all GTs within the tile):
> > + * - Complete 4MB MMIO space (containing SGunit/SoC registers, GT
> > + * registers, display registers, etc.)
> > + * - Global GTT
> > + * - VRAM (if discrete)
> > + * - Interrupt flows
> > + * - Migration context
> > + * - kernel batchbuffer pool
> > + * - Primary GT
> > + * - Media GT (if media version >= 13)
> > + *
> > + * Per-GT functionality:
> > + * - GuC
> > + * - Hardware engines
> > + * - Programmable hardware units (subslices, EUs)
> > + * - GSI subset of registers (multiple copies of these registers reside
> > + * within the complete MMIO space provided by the tile, but at different
> > + * offsets --- 0 for render, 0x380000 for media)
> > + * - Multicast register steering
> > + * - TLBs to cache page table translations
> > + * - Reset capability
> > + * - Low-level power management (e.g., C6)
> > + * - Clock frequency
> > + * - MOCS and PAT programming
> > + */
> > +
> > /**
> > * xe_tile_alloc - Perform per-tile memory allocation
> > * @tile: Tile to perform allocations for
> > --
> > 2.40.0
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 20/30] drm/xe: Interrupts are delivered per-tile, not per-GT
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 20/30] drm/xe: Interrupts are delivered per-tile, not per-GT Matt Roper
2023-05-26 22:16 ` Lucas De Marchi
@ 2023-05-30 6:36 ` Iddamsetty, Aravind
2023-05-30 15:58 ` Matt Roper
1 sibling, 1 reply; 54+ messages in thread
From: Iddamsetty, Aravind @ 2023-05-30 6:36 UTC (permalink / raw)
To: Matt Roper, intel-xe
On 20-05-2023 04:48, Matt Roper wrote:
> IRQ delivery and handling needs to be handled on a per-tile basis. Note
> that this is true even for the "GT interrupts" relating to engines and
> GuCs --- the interrupts relating to both GTs get raised through a single
> set of registers in the tile's sgunit range.
>
> On true multi-tile platforms, interrupts on remote tiles are internally
> forwarded to the root tile; the first thing the top-level interrupt
> handler should do is consult the root tile's instance of
> DG1_MSTR_TILE_INTR to determine which tile(s) had interrupts. This
> register is also responsible for enabling/disabling top-level reporting
> of any interrupts to the OS. Although this register technically exists
> on all tiles, it should only be used on the root tile.
>
> The (mis)use of struct xe_gt as a target for MMIO operations in the
> driver makes the code somewhat confusing since we wind up needing a GT
> pointer to handle programming that's unrelated to the GT. To mitigate
> this confusion, all of the xe_gt structures used solely as an MMIO
> target in interrupt code are renamed to 'mmio' so that it's clear that
> the structure being passed does not necessarily relate to any specific
> GT (primary or media) that we might be dealing with interrupts for.
> Reworking the driver's MMIO handling to not be dependent on xe_gt is
> planned as a future patch series.
>
> Note that GT initialization code currently calls xe_gt_irq_postinstall()
> in an attempt to enable the HWE interrupts for the GT being initialized.
> Unfortunately xe_gt_irq_postinstall() doesn't really match its name and
> does a bunch of other stuff unrelated to the GT interrupts (such as
> enabling the top-level device interrupts). That will be addressed in
> future patches.
>
> v2:
> - Clarify commit message with explanation of why DG1_MSTR_TILE_INTR is
> only used on the root tile, even though it's an sgunit register that
> is technically present in each tile's MMIO space. (Aravind)
> - Also clarify that the xe_gt used as a target for MMIO operations may
> or may not relate to the GT we're dealing with for interrupts.
> (Lucas)
>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt.c | 2 +-
> drivers/gpu/drm/xe/xe_irq.c | 334 ++++++++++++++++++++----------------
> drivers/gpu/drm/xe/xe_irq.h | 4 +-
> 3 files changed, 187 insertions(+), 153 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 0abd0d912610..290935e46059 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -304,7 +304,7 @@ static int gt_fw_domain_init(struct xe_gt *gt)
> gt->info.engine_mask = gt->info.__engine_mask;
>
> /* Enables per hw engine IRQs */
> - xe_gt_irq_postinstall(gt);
> + xe_gt_irq_postinstall(gt_to_tile(gt));
>
> /* Rerun MCR init as we now have hw engine list */
> xe_gt_mcr_init(gt);
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 654c34a5b99a..ad2f73b2a031 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -27,60 +27,66 @@
> #define IIR(offset) XE_REG(offset + 0x8)
> #define IER(offset) XE_REG(offset + 0xc)
>
> -static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
> +static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
> {
> - u32 val = xe_mmio_read32(gt, reg);
> + u32 val = xe_mmio_read32(mmio, reg);
>
> if (val == 0)
> return;
>
> - drm_WARN(>_to_xe(gt)->drm, 1,
> + drm_WARN(>_to_xe(mmio)->drm, 1,
> "Interrupt register 0x%x is not zero: 0x%08x\n",
> reg.addr, val);
> - xe_mmio_write32(gt, reg, 0xffffffff);
> - xe_mmio_read32(gt, reg);
> - xe_mmio_write32(gt, reg, 0xffffffff);
> - xe_mmio_read32(gt, reg);
> + xe_mmio_write32(mmio, reg, 0xffffffff);
> + xe_mmio_read32(mmio, reg);
> + xe_mmio_write32(mmio, reg, 0xffffffff);
> + xe_mmio_read32(mmio, reg);
> }
>
> /*
> * Unmask and enable the specified interrupts. Does not check current state,
> * so any bits not specified here will become masked and disabled.
> */
> -static void unmask_and_enable(struct xe_gt *gt, u32 irqregs, u32 bits)
> +static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)
> {
> + struct xe_gt *mmio = tile->primary_gt;
> +
> /*
> * If we're just enabling an interrupt now, it shouldn't already
> * be raised in the IIR.
> */
> - assert_iir_is_zero(gt, IIR(irqregs));
> + assert_iir_is_zero(mmio, IIR(irqregs));
>
> - xe_mmio_write32(gt, IER(irqregs), bits);
> - xe_mmio_write32(gt, IMR(irqregs), ~bits);
> + xe_mmio_write32(mmio, IER(irqregs), bits);
> + xe_mmio_write32(mmio, IMR(irqregs), ~bits);
>
> /* Posting read */
> - xe_mmio_read32(gt, IMR(irqregs));
> + xe_mmio_read32(mmio, IMR(irqregs));
> }
>
> /* Mask and disable all interrupts. */
> -static void mask_and_disable(struct xe_gt *gt, u32 irqregs)
> +static void mask_and_disable(struct xe_tile *tile, u32 irqregs)
> {
> - xe_mmio_write32(gt, IMR(irqregs), ~0);
> + struct xe_gt *mmio = tile->primary_gt;
> +
> + xe_mmio_write32(mmio, IMR(irqregs), ~0);
> /* Posting read */
> - xe_mmio_read32(gt, IMR(irqregs));
> + xe_mmio_read32(mmio, IMR(irqregs));
>
> - xe_mmio_write32(gt, IER(irqregs), 0);
> + xe_mmio_write32(mmio, IER(irqregs), 0);
>
> /* IIR can theoretically queue up two events. Be paranoid. */
> - xe_mmio_write32(gt, IIR(irqregs), ~0);
> - xe_mmio_read32(gt, IIR(irqregs));
> - xe_mmio_write32(gt, IIR(irqregs), ~0);
> - xe_mmio_read32(gt, IIR(irqregs));
> + xe_mmio_write32(mmio, IIR(irqregs), ~0);
> + xe_mmio_read32(mmio, IIR(irqregs));
> + xe_mmio_write32(mmio, IIR(irqregs), ~0);
> + xe_mmio_read32(mmio, IIR(irqregs));
> }
>
> -static u32 xelp_intr_disable(struct xe_gt *gt)
> +static u32 xelp_intr_disable(struct xe_device *xe)
> {
> - xe_mmio_write32(gt, GFX_MSTR_IRQ, 0);
> + struct xe_gt *mmio = xe_root_mmio_gt(xe);
> +
> + xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0);
>
> /*
> * Now with master disabled, get a sample of level indications
> @@ -88,36 +94,41 @@ static u32 xelp_intr_disable(struct xe_gt *gt)
> * New indications can and will light up during processing,
> * and will generate new interrupt after enabling master.
> */
> - return xe_mmio_read32(gt, GFX_MSTR_IRQ);
> + return xe_mmio_read32(mmio, GFX_MSTR_IRQ);
> }
>
> static u32
> -gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
> +gu_misc_irq_ack(struct xe_device *xe, const u32 master_ctl)
> {
> + struct xe_gt *mmio = xe_root_mmio_gt(xe);
> u32 iir;
>
> if (!(master_ctl & GU_MISC_IRQ))
> return 0;
>
> - iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET));
> + iir = xe_mmio_read32(mmio, IIR(GU_MISC_IRQ_OFFSET));
> if (likely(iir))
> - xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET), iir);
> + xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir);
>
> return iir;
> }
>
> -static inline void xelp_intr_enable(struct xe_gt *gt, bool stall)
> +static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
> {
> - xe_mmio_write32(gt, GFX_MSTR_IRQ, MASTER_IRQ);
> + struct xe_gt *mmio = xe_root_mmio_gt(xe);
> +
> + xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ);
> if (stall)
> - xe_mmio_read32(gt, GFX_MSTR_IRQ);
> + xe_mmio_read32(mmio, GFX_MSTR_IRQ);
> }
>
> -static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> +static void gt_irq_postinstall(struct xe_tile *tile)
> {
> + struct xe_device *xe = tile_to_xe(tile);
> + struct xe_gt *mmio = tile->primary_gt;
> u32 irqs, dmask, smask;
> - u32 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
> - u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
> + u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COMPUTE);
> + u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COPY);
>
> if (xe_device_guc_submission_enabled(xe)) {
> irqs = GT_RENDER_USER_INTERRUPT |
> @@ -133,57 +144,57 @@ static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> smask = irqs << 16;
>
> /* Enable RCS, BCS, VCS and VECS class interrupts. */
> - xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
> - xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
> + xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
> + xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
> if (ccs_mask)
> - xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
> + xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
>
> /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> - xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
> - xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
> + xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
> + xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
> if (bcs_mask & (BIT(1)|BIT(2)))
> - xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
> + xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
> if (bcs_mask & (BIT(3)|BIT(4)))
> - xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
> + xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
> if (bcs_mask & (BIT(5)|BIT(6)))
> - xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
> + xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
> if (bcs_mask & (BIT(7)|BIT(8)))
> - xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
> - xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
> - xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
> - xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
> + xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
> + xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
> + xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
> + xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
> if (ccs_mask & (BIT(0)|BIT(1)))
> - xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
> + xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
> if (ccs_mask & (BIT(2)|BIT(3)))
> - xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
> + xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
>
> /*
> * RPS interrupts will get enabled/disabled on demand when RPS itself
> * is enabled/disabled.
> */
> /* TODO: gt->pm_ier, gt->pm_imr */
> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
> + xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);
>
> /* Same thing for GuC interrupts */
> - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
> - xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);
> + xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
> }
>
> -static void xelp_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> +static void xelp_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
> {
> /* TODO: PCH */
>
> - gt_irq_postinstall(xe, gt);
> + gt_irq_postinstall(tile);
>
> - unmask_and_enable(gt, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
> + unmask_and_enable(tile, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
>
> - xelp_intr_enable(gt, true);
> + xelp_intr_enable(xe, true);
> }
>
> static u32
> gt_engine_identity(struct xe_device *xe,
> - struct xe_gt *gt,
> + struct xe_gt *mmio,
> const unsigned int bank,
> const unsigned int bit)
> {
> @@ -192,7 +203,7 @@ gt_engine_identity(struct xe_device *xe,
>
> lockdep_assert_held(&xe->irq.lock);
>
> - xe_mmio_write32(gt, IIR_REG_SELECTOR(bank), BIT(bit));
> + xe_mmio_write32(mmio, IIR_REG_SELECTOR(bank), BIT(bit));
>
> /*
> * NB: Specs do not specify how long to spin wait,
> @@ -200,7 +211,7 @@ gt_engine_identity(struct xe_device *xe,
> */
> timeout_ts = (local_clock() >> 10) + 100;
> do {
> - ident = xe_mmio_read32(gt, INTR_IDENTITY_REG(bank));
> + ident = xe_mmio_read32(mmio, INTR_IDENTITY_REG(bank));
> } while (!(ident & INTR_DATA_VALID) &&
> !time_after32(local_clock() >> 10, timeout_ts));
>
> @@ -210,7 +221,7 @@ gt_engine_identity(struct xe_device *xe,
> return 0;
> }
>
> - xe_mmio_write32(gt, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
> + xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
>
> return ident;
> }
> @@ -232,10 +243,32 @@ gt_other_irq_handler(struct xe_gt *gt, const u8 instance, const u16 iir)
> }
> }
>
> -static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> +static struct xe_gt *pick_engine_gt(struct xe_tile *tile,
> + enum xe_engine_class class,
> + unsigned int instance)
> +{
> + struct xe_device *xe = tile_to_xe(tile);
> +
> + if (MEDIA_VER(xe) < 13)
> + return tile->primary_gt;
> +
> + if (class == XE_ENGINE_CLASS_VIDEO_DECODE ||
> + class == XE_ENGINE_CLASS_VIDEO_ENHANCE)
> + return tile->media_gt;
> +
> + if (class == XE_ENGINE_CLASS_OTHER &&
> + instance == OTHER_MEDIA_GUC_INSTANCE)
> + return tile->media_gt;
> +
> + return tile->primary_gt;
> +}
> +
> +static void gt_irq_handler(struct xe_tile *tile,
> u32 master_ctl, long unsigned int *intr_dw,
> u32 *identity)
> {
> + struct xe_device *xe = tile_to_xe(tile);
> + struct xe_gt *mmio = tile->primary_gt;
> unsigned int bank, bit;
> u16 instance, intr_vec;
> enum xe_engine_class class;
> @@ -247,27 +280,26 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> if (!(master_ctl & GT_DW_IRQ(bank)))
> continue;
>
> - if (!xe_gt_is_media_type(gt)) {
> - intr_dw[bank] =
> - xe_mmio_read32(gt, GT_INTR_DW(bank));
> - for_each_set_bit(bit, intr_dw + bank, 32)
> - identity[bit] = gt_engine_identity(xe, gt,
> - bank, bit);
> - xe_mmio_write32(gt, GT_INTR_DW(bank),
> - intr_dw[bank]);
> - }
> + intr_dw[bank] = xe_mmio_read32(mmio, GT_INTR_DW(bank));
> + for_each_set_bit(bit, intr_dw + bank, 32)
> + identity[bit] = gt_engine_identity(xe, mmio, bank, bit);
> + xe_mmio_write32(mmio, GT_INTR_DW(bank), intr_dw[bank]);
as I notice earlier we are doing the above processing only on a non
media GT, with your change we are even processing on media tile, was
there a bug earlier hence you made this change ?
Thanks,
Aravind.
>
> for_each_set_bit(bit, intr_dw + bank, 32) {
> + struct xe_gt *engine_gt;
> +
> class = INTR_ENGINE_CLASS(identity[bit]);
> instance = INTR_ENGINE_INSTANCE(identity[bit]);
> intr_vec = INTR_ENGINE_INTR(identity[bit]);
>
> + engine_gt = pick_engine_gt(tile, class, instance);
> +
> if (class == XE_ENGINE_CLASS_OTHER) {
> - gt_other_irq_handler(gt, instance, intr_vec);
> + gt_other_irq_handler(engine_gt, instance, intr_vec);
> continue;
> }
>
> - hwe = xe_gt_hw_engine(gt, class, instance, false);
> + hwe = xe_gt_hw_engine(engine_gt, class, instance, false);
> if (!hwe)
> continue;
>
> @@ -285,24 +317,24 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> static irqreturn_t xelp_irq_handler(int irq, void *arg)
> {
> struct xe_device *xe = arg;
> - struct xe_gt *gt = xe_root_mmio_gt(xe);
> + struct xe_tile *tile = xe_device_get_root_tile(xe);
> u32 master_ctl, gu_misc_iir;
> long unsigned int intr_dw[2];
> u32 identity[32];
>
> - master_ctl = xelp_intr_disable(gt);
> + master_ctl = xelp_intr_disable(xe);
> if (!master_ctl) {
> - xelp_intr_enable(gt, false);
> + xelp_intr_enable(xe, false);
> return IRQ_NONE;
> }
>
> - gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
> + gt_irq_handler(tile, master_ctl, intr_dw, identity);
>
> xe_display_irq_handler(xe, master_ctl);
>
> - gu_misc_iir = gu_misc_irq_ack(gt, master_ctl);
> + gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
>
> - xelp_intr_enable(gt, false);
> + xelp_intr_enable(xe, false);
>
> xe_display_irq_enable(xe, gu_misc_iir);
>
> @@ -311,38 +343,38 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>
> static u32 dg1_intr_disable(struct xe_device *xe)
> {
> - struct xe_gt *gt = xe_root_mmio_gt(xe);
> + struct xe_gt *mmio = xe_root_mmio_gt(xe);
> u32 val;
>
> /* First disable interrupts */
> - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, 0);
> + xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0);
>
> /* Get the indication levels and ack the master unit */
> - val = xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
> + val = xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
> if (unlikely(!val))
> return 0;
>
> - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, val);
> + xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, val);
>
> return val;
> }
>
> static void dg1_intr_enable(struct xe_device *xe, bool stall)
> {
> - struct xe_gt *gt = xe_root_mmio_gt(xe);
> + struct xe_gt *mmio = xe_root_mmio_gt(xe);
>
> - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
> + xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
> if (stall)
> - xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
> + xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
> }
>
> -static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> +static void dg1_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
> {
> - gt_irq_postinstall(xe, gt);
> + gt_irq_postinstall(tile);
>
> - unmask_and_enable(gt, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
> + unmask_and_enable(tile, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
>
> - if (gt->info.id == XE_GT0)
> + if (tile->id == 0)
> dg1_intr_enable(xe, true);
> }
>
> @@ -354,8 +386,8 @@ static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> static irqreturn_t dg1_irq_handler(int irq, void *arg)
> {
> struct xe_device *xe = arg;
> - struct xe_gt *gt;
> - u32 master_tile_ctl, master_ctl = 0, tile0_master_ctl = 0, gu_misc_iir;
> + struct xe_tile *tile;
> + u32 master_tile_ctl, master_ctl = 0, gu_misc_iir = 0;
> long unsigned int intr_dw[2];
> u32 identity[32];
> u8 id;
> @@ -368,12 +400,13 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> return IRQ_NONE;
> }
>
> - for_each_gt(gt, xe, id) {
> - if ((master_tile_ctl & DG1_MSTR_TILE(gt_to_tile(gt)->id)) == 0)
> + for_each_tile(tile, xe, id) {
> + struct xe_gt *mmio = tile->primary_gt;
> +
> + if ((master_tile_ctl & DG1_MSTR_TILE(tile->id)) == 0)
> continue;
>
> - if (!xe_gt_is_media_type(gt))
> - master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ);
> + master_ctl = xe_mmio_read32(mmio, GFX_MSTR_IRQ);
>
> /*
> * We might be in irq handler just when PCIe DPC is initiated
> @@ -381,124 +414,125 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> * irq as device is inaccessible.
> */
> if (master_ctl == REG_GENMASK(31, 0)) {
> - dev_dbg(gt_to_xe(gt)->drm.dev,
> + dev_dbg(tile_to_xe(tile)->drm.dev,
> "Ignore this IRQ as device might be in DPC containment.\n");
> return IRQ_HANDLED;
> }
>
> - if (!xe_gt_is_media_type(gt))
> - xe_mmio_write32(gt, GFX_MSTR_IRQ, master_ctl);
> - gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
> + xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);
> +
> + gt_irq_handler(tile, master_ctl, intr_dw, identity);
>
> /*
> - * Save primary tile's master interrupt register for display
> - * processing below.
> + * Display interrupts (including display backlight operations
> + * that get reported as Gunit GSE) would only be hooked up to
> + * the primary tile.
> */
> - if (id == 0)
> - tile0_master_ctl = master_ctl;
> + if (id == 0) {
> + xe_display_irq_handler(xe, master_ctl);
> + gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> + }
> }
>
> - xe_display_irq_handler(xe, tile0_master_ctl);
> -
> - /* Gunit GSE interrupts can trigger display backlight operations */
> - gu_misc_iir = gu_misc_irq_ack(gt, tile0_master_ctl);
> -
> dg1_intr_enable(xe, false);
> -
> xe_display_irq_enable(xe, gu_misc_iir);
>
> return IRQ_HANDLED;
> }
>
> -static void gt_irq_reset(struct xe_gt *gt)
> +static void gt_irq_reset(struct xe_tile *tile)
> {
> - u32 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
> - u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
> + struct xe_gt *mmio = tile->primary_gt;
> +
> + u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
> + XE_ENGINE_CLASS_COMPUTE);
> + u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
> + XE_ENGINE_CLASS_COPY);
>
> /* Disable RCS, BCS, VCS and VECS class engines. */
> - xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, 0);
> - xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, 0);
> + xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, 0);
> + xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, 0);
> if (ccs_mask)
> - xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, 0);
> + xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, 0);
>
> /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> - xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~0);
> - xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~0);
> if (bcs_mask & (BIT(1)|BIT(2)))
> - xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
> if (bcs_mask & (BIT(3)|BIT(4)))
> - xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
> if (bcs_mask & (BIT(5)|BIT(6)))
> - xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
> if (bcs_mask & (BIT(7)|BIT(8)))
> - xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
> - xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~0);
> - xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~0);
> - xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~0);
> if (ccs_mask & (BIT(0)|BIT(1)))
> - xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~0);
> if (ccs_mask & (BIT(2)|BIT(3)))
> - xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~0);
>
> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
> - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
> - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
> - xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
> + xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);
> + xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);
> + xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
> }
>
> -static void xelp_irq_reset(struct xe_gt *gt)
> +static void xelp_irq_reset(struct xe_tile *tile)
> {
> - xelp_intr_disable(gt);
> + xelp_intr_disable(tile_to_xe(tile));
>
> - gt_irq_reset(gt);
> + gt_irq_reset(tile);
>
> - mask_and_disable(gt, GU_MISC_IRQ_OFFSET);
> - mask_and_disable(gt, PCU_IRQ_OFFSET);
> + mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
> + mask_and_disable(tile, PCU_IRQ_OFFSET);
> }
>
> -static void dg1_irq_reset(struct xe_gt *gt)
> +static void dg1_irq_reset(struct xe_tile *tile)
> {
> - if (gt->info.id == 0)
> - dg1_intr_disable(gt_to_xe(gt));
> + if (tile->id == 0)
> + dg1_intr_disable(tile_to_xe(tile));
>
> - gt_irq_reset(gt);
> + gt_irq_reset(tile);
>
> - mask_and_disable(gt, GU_MISC_IRQ_OFFSET);
> - mask_and_disable(gt, PCU_IRQ_OFFSET);
> + mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
> + mask_and_disable(tile, PCU_IRQ_OFFSET);
> }
>
> static void xe_irq_reset(struct xe_device *xe)
> {
> - struct xe_gt *gt;
> + struct xe_tile *tile;
> u8 id;
>
> - for_each_gt(gt, xe, id) {
> + for_each_tile(tile, xe, id) {
> if (GRAPHICS_VERx100(xe) >= 1210)
> - dg1_irq_reset(gt);
> + dg1_irq_reset(tile);
> else
> - xelp_irq_reset(gt);
> + xelp_irq_reset(tile);
> }
>
> xe_display_irq_reset(xe);
> }
>
> -void xe_gt_irq_postinstall(struct xe_gt *gt)
> +void xe_gt_irq_postinstall(struct xe_tile *tile)
> {
> - struct xe_device *xe = gt_to_xe(gt);
> + struct xe_device *xe = tile_to_xe(tile);
>
> if (GRAPHICS_VERx100(xe) >= 1210)
> - dg1_irq_postinstall(xe, gt);
> + dg1_irq_postinstall(xe, tile);
> else
> - xelp_irq_postinstall(xe, gt);
> + xelp_irq_postinstall(xe, tile);
> }
>
> static void xe_irq_postinstall(struct xe_device *xe)
> {
> - struct xe_gt *gt;
> + struct xe_tile *tile;
> u8 id;
>
> - for_each_gt(gt, xe, id)
> - xe_gt_irq_postinstall(gt);
> + for_each_tile(tile, xe, id)
> + xe_gt_irq_postinstall(tile);
>
> xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));
> }
> diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
> index 34ecf22b32d3..69113c21e1cd 100644
> --- a/drivers/gpu/drm/xe/xe_irq.h
> +++ b/drivers/gpu/drm/xe/xe_irq.h
> @@ -7,10 +7,10 @@
> #define _XE_IRQ_H_
>
> struct xe_device;
> -struct xe_gt;
> +struct xe_tile;
>
> int xe_irq_install(struct xe_device *xe);
> -void xe_gt_irq_postinstall(struct xe_gt *gt);
> +void xe_gt_irq_postinstall(struct xe_tile *tile);
> void xe_irq_shutdown(struct xe_device *xe);
> void xe_irq_suspend(struct xe_device *xe);
> void xe_irq_resume(struct xe_device *xe);
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 20/30] drm/xe: Interrupts are delivered per-tile, not per-GT
2023-05-30 6:36 ` Iddamsetty, Aravind
@ 2023-05-30 15:58 ` Matt Roper
0 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-30 15:58 UTC (permalink / raw)
To: Iddamsetty, Aravind; +Cc: intel-xe
On Tue, May 30, 2023 at 12:06:39PM +0530, Iddamsetty, Aravind wrote:
>
>
> On 20-05-2023 04:48, Matt Roper wrote:
> > IRQ delivery and handling needs to be handled on a per-tile basis. Note
> > that this is true even for the "GT interrupts" relating to engines and
> > GuCs --- the interrupts relating to both GTs get raised through a single
> > set of registers in the tile's sgunit range.
> >
> > On true multi-tile platforms, interrupts on remote tiles are internally
> > forwarded to the root tile; the first thing the top-level interrupt
> > handler should do is consult the root tile's instance of
> > DG1_MSTR_TILE_INTR to determine which tile(s) had interrupts. This
> > register is also responsible for enabling/disabling top-level reporting
> > of any interrupts to the OS. Although this register technically exists
> > on all tiles, it should only be used on the root tile.
> >
> > The (mis)use of struct xe_gt as a target for MMIO operations in the
> > driver makes the code somewhat confusing since we wind up needing a GT
> > pointer to handle programming that's unrelated to the GT. To mitigate
> > this confusion, all of the xe_gt structures used solely as an MMIO
> > target in interrupt code are renamed to 'mmio' so that it's clear that
> > the structure being passed does not necessarily relate to any specific
> > GT (primary or media) that we might be dealing with interrupts for.
> > Reworking the driver's MMIO handling to not be dependent on xe_gt is
> > planned as a future patch series.
> >
> > Note that GT initialization code currently calls xe_gt_irq_postinstall()
> > in an attempt to enable the HWE interrupts for the GT being initialized.
> > Unfortunately xe_gt_irq_postinstall() doesn't really match its name and
> > does a bunch of other stuff unrelated to the GT interrupts (such as
> > enabling the top-level device interrupts). That will be addressed in
> > future patches.
> >
> > v2:
> > - Clarify commit message with explanation of why DG1_MSTR_TILE_INTR is
> > only used on the root tile, even though it's an sgunit register that
> > is technically present in each tile's MMIO space. (Aravind)
> > - Also clarify that the xe_gt used as a target for MMIO operations may
> > or may not relate to the GT we're dealing with for interrupts.
> > (Lucas)
> >
> > Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_gt.c | 2 +-
> > drivers/gpu/drm/xe/xe_irq.c | 334 ++++++++++++++++++++----------------
> > drivers/gpu/drm/xe/xe_irq.h | 4 +-
> > 3 files changed, 187 insertions(+), 153 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> > index 0abd0d912610..290935e46059 100644
> > --- a/drivers/gpu/drm/xe/xe_gt.c
> > +++ b/drivers/gpu/drm/xe/xe_gt.c
> > @@ -304,7 +304,7 @@ static int gt_fw_domain_init(struct xe_gt *gt)
> > gt->info.engine_mask = gt->info.__engine_mask;
> >
> > /* Enables per hw engine IRQs */
> > - xe_gt_irq_postinstall(gt);
> > + xe_gt_irq_postinstall(gt_to_tile(gt));
> >
> > /* Rerun MCR init as we now have hw engine list */
> > xe_gt_mcr_init(gt);
> > diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> > index 654c34a5b99a..ad2f73b2a031 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.c
> > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > @@ -27,60 +27,66 @@
> > #define IIR(offset) XE_REG(offset + 0x8)
> > #define IER(offset) XE_REG(offset + 0xc)
> >
> > -static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
> > +static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
> > {
> > - u32 val = xe_mmio_read32(gt, reg);
> > + u32 val = xe_mmio_read32(mmio, reg);
> >
> > if (val == 0)
> > return;
> >
> > - drm_WARN(>_to_xe(gt)->drm, 1,
> > + drm_WARN(>_to_xe(mmio)->drm, 1,
> > "Interrupt register 0x%x is not zero: 0x%08x\n",
> > reg.addr, val);
> > - xe_mmio_write32(gt, reg, 0xffffffff);
> > - xe_mmio_read32(gt, reg);
> > - xe_mmio_write32(gt, reg, 0xffffffff);
> > - xe_mmio_read32(gt, reg);
> > + xe_mmio_write32(mmio, reg, 0xffffffff);
> > + xe_mmio_read32(mmio, reg);
> > + xe_mmio_write32(mmio, reg, 0xffffffff);
> > + xe_mmio_read32(mmio, reg);
> > }
> >
> > /*
> > * Unmask and enable the specified interrupts. Does not check current state,
> > * so any bits not specified here will become masked and disabled.
> > */
> > -static void unmask_and_enable(struct xe_gt *gt, u32 irqregs, u32 bits)
> > +static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)
> > {
> > + struct xe_gt *mmio = tile->primary_gt;
> > +
> > /*
> > * If we're just enabling an interrupt now, it shouldn't already
> > * be raised in the IIR.
> > */
> > - assert_iir_is_zero(gt, IIR(irqregs));
> > + assert_iir_is_zero(mmio, IIR(irqregs));
> >
> > - xe_mmio_write32(gt, IER(irqregs), bits);
> > - xe_mmio_write32(gt, IMR(irqregs), ~bits);
> > + xe_mmio_write32(mmio, IER(irqregs), bits);
> > + xe_mmio_write32(mmio, IMR(irqregs), ~bits);
> >
> > /* Posting read */
> > - xe_mmio_read32(gt, IMR(irqregs));
> > + xe_mmio_read32(mmio, IMR(irqregs));
> > }
> >
> > /* Mask and disable all interrupts. */
> > -static void mask_and_disable(struct xe_gt *gt, u32 irqregs)
> > +static void mask_and_disable(struct xe_tile *tile, u32 irqregs)
> > {
> > - xe_mmio_write32(gt, IMR(irqregs), ~0);
> > + struct xe_gt *mmio = tile->primary_gt;
> > +
> > + xe_mmio_write32(mmio, IMR(irqregs), ~0);
> > /* Posting read */
> > - xe_mmio_read32(gt, IMR(irqregs));
> > + xe_mmio_read32(mmio, IMR(irqregs));
> >
> > - xe_mmio_write32(gt, IER(irqregs), 0);
> > + xe_mmio_write32(mmio, IER(irqregs), 0);
> >
> > /* IIR can theoretically queue up two events. Be paranoid. */
> > - xe_mmio_write32(gt, IIR(irqregs), ~0);
> > - xe_mmio_read32(gt, IIR(irqregs));
> > - xe_mmio_write32(gt, IIR(irqregs), ~0);
> > - xe_mmio_read32(gt, IIR(irqregs));
> > + xe_mmio_write32(mmio, IIR(irqregs), ~0);
> > + xe_mmio_read32(mmio, IIR(irqregs));
> > + xe_mmio_write32(mmio, IIR(irqregs), ~0);
> > + xe_mmio_read32(mmio, IIR(irqregs));
> > }
> >
> > -static u32 xelp_intr_disable(struct xe_gt *gt)
> > +static u32 xelp_intr_disable(struct xe_device *xe)
> > {
> > - xe_mmio_write32(gt, GFX_MSTR_IRQ, 0);
> > + struct xe_gt *mmio = xe_root_mmio_gt(xe);
> > +
> > + xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0);
> >
> > /*
> > * Now with master disabled, get a sample of level indications
> > @@ -88,36 +94,41 @@ static u32 xelp_intr_disable(struct xe_gt *gt)
> > * New indications can and will light up during processing,
> > * and will generate new interrupt after enabling master.
> > */
> > - return xe_mmio_read32(gt, GFX_MSTR_IRQ);
> > + return xe_mmio_read32(mmio, GFX_MSTR_IRQ);
> > }
> >
> > static u32
> > -gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
> > +gu_misc_irq_ack(struct xe_device *xe, const u32 master_ctl)
> > {
> > + struct xe_gt *mmio = xe_root_mmio_gt(xe);
> > u32 iir;
> >
> > if (!(master_ctl & GU_MISC_IRQ))
> > return 0;
> >
> > - iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET));
> > + iir = xe_mmio_read32(mmio, IIR(GU_MISC_IRQ_OFFSET));
> > if (likely(iir))
> > - xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET), iir);
> > + xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir);
> >
> > return iir;
> > }
> >
> > -static inline void xelp_intr_enable(struct xe_gt *gt, bool stall)
> > +static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
> > {
> > - xe_mmio_write32(gt, GFX_MSTR_IRQ, MASTER_IRQ);
> > + struct xe_gt *mmio = xe_root_mmio_gt(xe);
> > +
> > + xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ);
> > if (stall)
> > - xe_mmio_read32(gt, GFX_MSTR_IRQ);
> > + xe_mmio_read32(mmio, GFX_MSTR_IRQ);
> > }
> >
> > -static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> > +static void gt_irq_postinstall(struct xe_tile *tile)
> > {
> > + struct xe_device *xe = tile_to_xe(tile);
> > + struct xe_gt *mmio = tile->primary_gt;
> > u32 irqs, dmask, smask;
> > - u32 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
> > - u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
> > + u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COMPUTE);
> > + u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, XE_ENGINE_CLASS_COPY);
> >
> > if (xe_device_guc_submission_enabled(xe)) {
> > irqs = GT_RENDER_USER_INTERRUPT |
> > @@ -133,57 +144,57 @@ static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> > smask = irqs << 16;
> >
> > /* Enable RCS, BCS, VCS and VECS class interrupts. */
> > - xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
> > - xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
> > + xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
> > + xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
> > if (ccs_mask)
> > - xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
> > + xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
> >
> > /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> > - xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
> > - xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
> > + xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
> > + xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
> > if (bcs_mask & (BIT(1)|BIT(2)))
> > - xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
> > + xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
> > if (bcs_mask & (BIT(3)|BIT(4)))
> > - xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
> > + xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
> > if (bcs_mask & (BIT(5)|BIT(6)))
> > - xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
> > + xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
> > if (bcs_mask & (BIT(7)|BIT(8)))
> > - xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
> > - xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
> > - xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
> > - xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
> > + xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
> > + xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
> > + xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
> > + xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
> > if (ccs_mask & (BIT(0)|BIT(1)))
> > - xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
> > + xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
> > if (ccs_mask & (BIT(2)|BIT(3)))
> > - xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
> > + xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
> >
> > /*
> > * RPS interrupts will get enabled/disabled on demand when RPS itself
> > * is enabled/disabled.
> > */
> > /* TODO: gt->pm_ier, gt->pm_imr */
> > - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
> > - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
> > + xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);
> >
> > /* Same thing for GuC interrupts */
> > - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
> > - xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);
> > + xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
> > }
> >
> > -static void xelp_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> > +static void xelp_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
> > {
> > /* TODO: PCH */
> >
> > - gt_irq_postinstall(xe, gt);
> > + gt_irq_postinstall(tile);
> >
> > - unmask_and_enable(gt, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
> > + unmask_and_enable(tile, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
> >
> > - xelp_intr_enable(gt, true);
> > + xelp_intr_enable(xe, true);
> > }
> >
> > static u32
> > gt_engine_identity(struct xe_device *xe,
> > - struct xe_gt *gt,
> > + struct xe_gt *mmio,
> > const unsigned int bank,
> > const unsigned int bit)
> > {
> > @@ -192,7 +203,7 @@ gt_engine_identity(struct xe_device *xe,
> >
> > lockdep_assert_held(&xe->irq.lock);
> >
> > - xe_mmio_write32(gt, IIR_REG_SELECTOR(bank), BIT(bit));
> > + xe_mmio_write32(mmio, IIR_REG_SELECTOR(bank), BIT(bit));
> >
> > /*
> > * NB: Specs do not specify how long to spin wait,
> > @@ -200,7 +211,7 @@ gt_engine_identity(struct xe_device *xe,
> > */
> > timeout_ts = (local_clock() >> 10) + 100;
> > do {
> > - ident = xe_mmio_read32(gt, INTR_IDENTITY_REG(bank));
> > + ident = xe_mmio_read32(mmio, INTR_IDENTITY_REG(bank));
> > } while (!(ident & INTR_DATA_VALID) &&
> > !time_after32(local_clock() >> 10, timeout_ts));
> >
> > @@ -210,7 +221,7 @@ gt_engine_identity(struct xe_device *xe,
> > return 0;
> > }
> >
> > - xe_mmio_write32(gt, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
> > + xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), INTR_DATA_VALID);
> >
> > return ident;
> > }
> > @@ -232,10 +243,32 @@ gt_other_irq_handler(struct xe_gt *gt, const u8 instance, const u16 iir)
> > }
> > }
> >
> > -static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> > +static struct xe_gt *pick_engine_gt(struct xe_tile *tile,
> > + enum xe_engine_class class,
> > + unsigned int instance)
> > +{
> > + struct xe_device *xe = tile_to_xe(tile);
> > +
> > + if (MEDIA_VER(xe) < 13)
> > + return tile->primary_gt;
> > +
> > + if (class == XE_ENGINE_CLASS_VIDEO_DECODE ||
> > + class == XE_ENGINE_CLASS_VIDEO_ENHANCE)
> > + return tile->media_gt;
> > +
> > + if (class == XE_ENGINE_CLASS_OTHER &&
> > + instance == OTHER_MEDIA_GUC_INSTANCE)
> > + return tile->media_gt;
> > +
> > + return tile->primary_gt;
> > +}
> > +
> > +static void gt_irq_handler(struct xe_tile *tile,
> > u32 master_ctl, long unsigned int *intr_dw,
> > u32 *identity)
> > {
> > + struct xe_device *xe = tile_to_xe(tile);
> > + struct xe_gt *mmio = tile->primary_gt;
> > unsigned int bank, bit;
> > u16 instance, intr_vec;
> > enum xe_engine_class class;
> > @@ -247,27 +280,26 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> > if (!(master_ctl & GT_DW_IRQ(bank)))
> > continue;
> >
> > - if (!xe_gt_is_media_type(gt)) {
> > - intr_dw[bank] =
> > - xe_mmio_read32(gt, GT_INTR_DW(bank));
> > - for_each_set_bit(bit, intr_dw + bank, 32)
> > - identity[bit] = gt_engine_identity(xe, gt,
> > - bank, bit);
> > - xe_mmio_write32(gt, GT_INTR_DW(bank),
> > - intr_dw[bank]);
> > - }
> > + intr_dw[bank] = xe_mmio_read32(mmio, GT_INTR_DW(bank));
> > + for_each_set_bit(bit, intr_dw + bank, 32)
> > + identity[bit] = gt_engine_identity(xe, mmio, bank, bit);
> > + xe_mmio_write32(mmio, GT_INTR_DW(bank), intr_dw[bank]);
>
> as I notice earlier we are doing the above processing only on a non
> media GT, with your change we are even processing on media tile, was
> there a bug earlier hence you made this change ?
The media GT is still disabled at this point in the series, but we still
need to put the proper handling in place so that we'll be able to
re-enable it at the end of the series. So even though "engine_gt" below
will always be the primary GT after this patch, near the end of the
series we re-enable media GT and the pick_engine_gt() call willl start
getting used. We're just putting the infrastructure in place right now
so that it will be ready.
Note that the 'struct xe_gt *mmio' used as the target for MMIO
operations is unrelated to the GT(s) we're handling interrupts for.
It's unfortunate that 'struct xe_gt' is the target for MMIO operations
right now. I'll have another series to update that design once this
series lands.
Matt
>
> Thanks,
> Aravind.
> >
> > for_each_set_bit(bit, intr_dw + bank, 32) {
> > + struct xe_gt *engine_gt;
> > +
> > class = INTR_ENGINE_CLASS(identity[bit]);
> > instance = INTR_ENGINE_INSTANCE(identity[bit]);
> > intr_vec = INTR_ENGINE_INTR(identity[bit]);
> >
> > + engine_gt = pick_engine_gt(tile, class, instance);
> > +
> > if (class == XE_ENGINE_CLASS_OTHER) {
> > - gt_other_irq_handler(gt, instance, intr_vec);
> > + gt_other_irq_handler(engine_gt, instance, intr_vec);
> > continue;
> > }
> >
> > - hwe = xe_gt_hw_engine(gt, class, instance, false);
> > + hwe = xe_gt_hw_engine(engine_gt, class, instance, false);
> > if (!hwe)
> > continue;
> >
> > @@ -285,24 +317,24 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> > static irqreturn_t xelp_irq_handler(int irq, void *arg)
> > {
> > struct xe_device *xe = arg;
> > - struct xe_gt *gt = xe_root_mmio_gt(xe);
> > + struct xe_tile *tile = xe_device_get_root_tile(xe);
> > u32 master_ctl, gu_misc_iir;
> > long unsigned int intr_dw[2];
> > u32 identity[32];
> >
> > - master_ctl = xelp_intr_disable(gt);
> > + master_ctl = xelp_intr_disable(xe);
> > if (!master_ctl) {
> > - xelp_intr_enable(gt, false);
> > + xelp_intr_enable(xe, false);
> > return IRQ_NONE;
> > }
> >
> > - gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
> > + gt_irq_handler(tile, master_ctl, intr_dw, identity);
> >
> > xe_display_irq_handler(xe, master_ctl);
> >
> > - gu_misc_iir = gu_misc_irq_ack(gt, master_ctl);
> > + gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> >
> > - xelp_intr_enable(gt, false);
> > + xelp_intr_enable(xe, false);
> >
> > xe_display_irq_enable(xe, gu_misc_iir);
> >
> > @@ -311,38 +343,38 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
> >
> > static u32 dg1_intr_disable(struct xe_device *xe)
> > {
> > - struct xe_gt *gt = xe_root_mmio_gt(xe);
> > + struct xe_gt *mmio = xe_root_mmio_gt(xe);
> > u32 val;
> >
> > /* First disable interrupts */
> > - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, 0);
> > + xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0);
> >
> > /* Get the indication levels and ack the master unit */
> > - val = xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
> > + val = xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
> > if (unlikely(!val))
> > return 0;
> >
> > - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, val);
> > + xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, val);
> >
> > return val;
> > }
> >
> > static void dg1_intr_enable(struct xe_device *xe, bool stall)
> > {
> > - struct xe_gt *gt = xe_root_mmio_gt(xe);
> > + struct xe_gt *mmio = xe_root_mmio_gt(xe);
> >
> > - xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
> > + xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
> > if (stall)
> > - xe_mmio_read32(gt, DG1_MSTR_TILE_INTR);
> > + xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
> > }
> >
> > -static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> > +static void dg1_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
> > {
> > - gt_irq_postinstall(xe, gt);
> > + gt_irq_postinstall(tile);
> >
> > - unmask_and_enable(gt, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
> > + unmask_and_enable(tile, GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
> >
> > - if (gt->info.id == XE_GT0)
> > + if (tile->id == 0)
> > dg1_intr_enable(xe, true);
> > }
> >
> > @@ -354,8 +386,8 @@ static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> > static irqreturn_t dg1_irq_handler(int irq, void *arg)
> > {
> > struct xe_device *xe = arg;
> > - struct xe_gt *gt;
> > - u32 master_tile_ctl, master_ctl = 0, tile0_master_ctl = 0, gu_misc_iir;
> > + struct xe_tile *tile;
> > + u32 master_tile_ctl, master_ctl = 0, gu_misc_iir = 0;
> > long unsigned int intr_dw[2];
> > u32 identity[32];
> > u8 id;
> > @@ -368,12 +400,13 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> > return IRQ_NONE;
> > }
> >
> > - for_each_gt(gt, xe, id) {
> > - if ((master_tile_ctl & DG1_MSTR_TILE(gt_to_tile(gt)->id)) == 0)
> > + for_each_tile(tile, xe, id) {
> > + struct xe_gt *mmio = tile->primary_gt;
> > +
> > + if ((master_tile_ctl & DG1_MSTR_TILE(tile->id)) == 0)
> > continue;
> >
> > - if (!xe_gt_is_media_type(gt))
> > - master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ);
> > + master_ctl = xe_mmio_read32(mmio, GFX_MSTR_IRQ);
> >
> > /*
> > * We might be in irq handler just when PCIe DPC is initiated
> > @@ -381,124 +414,125 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> > * irq as device is inaccessible.
> > */
> > if (master_ctl == REG_GENMASK(31, 0)) {
> > - dev_dbg(gt_to_xe(gt)->drm.dev,
> > + dev_dbg(tile_to_xe(tile)->drm.dev,
> > "Ignore this IRQ as device might be in DPC containment.\n");
> > return IRQ_HANDLED;
> > }
> >
> > - if (!xe_gt_is_media_type(gt))
> > - xe_mmio_write32(gt, GFX_MSTR_IRQ, master_ctl);
> > - gt_irq_handler(xe, gt, master_ctl, intr_dw, identity);
> > + xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);
> > +
> > + gt_irq_handler(tile, master_ctl, intr_dw, identity);
> >
> > /*
> > - * Save primary tile's master interrupt register for display
> > - * processing below.
> > + * Display interrupts (including display backlight operations
> > + * that get reported as Gunit GSE) would only be hooked up to
> > + * the primary tile.
> > */
> > - if (id == 0)
> > - tile0_master_ctl = master_ctl;
> > + if (id == 0) {
> > + xe_display_irq_handler(xe, master_ctl);
> > + gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> > + }
> > }
> >
> > - xe_display_irq_handler(xe, tile0_master_ctl);
> > -
> > - /* Gunit GSE interrupts can trigger display backlight operations */
> > - gu_misc_iir = gu_misc_irq_ack(gt, tile0_master_ctl);
> > -
> > dg1_intr_enable(xe, false);
> > -
> > xe_display_irq_enable(xe, gu_misc_iir);
> >
> > return IRQ_HANDLED;
> > }
> >
> > -static void gt_irq_reset(struct xe_gt *gt)
> > +static void gt_irq_reset(struct xe_tile *tile)
> > {
> > - u32 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
> > - u32 bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
> > + struct xe_gt *mmio = tile->primary_gt;
> > +
> > + u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
> > + XE_ENGINE_CLASS_COMPUTE);
> > + u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
> > + XE_ENGINE_CLASS_COPY);
> >
> > /* Disable RCS, BCS, VCS and VECS class engines. */
> > - xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, 0);
> > - xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, 0);
> > + xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, 0);
> > + xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, 0);
> > if (ccs_mask)
> > - xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, 0);
> > + xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, 0);
> >
> > /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> > - xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~0);
> > - xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~0);
> > if (bcs_mask & (BIT(1)|BIT(2)))
> > - xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
> > if (bcs_mask & (BIT(3)|BIT(4)))
> > - xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
> > if (bcs_mask & (BIT(5)|BIT(6)))
> > - xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
> > if (bcs_mask & (BIT(7)|BIT(8)))
> > - xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
> > - xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~0);
> > - xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~0);
> > - xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~0);
> > if (ccs_mask & (BIT(0)|BIT(1)))
> > - xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~0);
> > if (ccs_mask & (BIT(2)|BIT(3)))
> > - xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~0);
> >
> > - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_ENABLE, 0);
> > - xe_mmio_write32(gt, GPM_WGBOXPERF_INTR_MASK, ~0);
> > - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 0);
> > - xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);
> > + xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);
> > + xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);
> > + xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
> > }
> >
> > -static void xelp_irq_reset(struct xe_gt *gt)
> > +static void xelp_irq_reset(struct xe_tile *tile)
> > {
> > - xelp_intr_disable(gt);
> > + xelp_intr_disable(tile_to_xe(tile));
> >
> > - gt_irq_reset(gt);
> > + gt_irq_reset(tile);
> >
> > - mask_and_disable(gt, GU_MISC_IRQ_OFFSET);
> > - mask_and_disable(gt, PCU_IRQ_OFFSET);
> > + mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
> > + mask_and_disable(tile, PCU_IRQ_OFFSET);
> > }
> >
> > -static void dg1_irq_reset(struct xe_gt *gt)
> > +static void dg1_irq_reset(struct xe_tile *tile)
> > {
> > - if (gt->info.id == 0)
> > - dg1_intr_disable(gt_to_xe(gt));
> > + if (tile->id == 0)
> > + dg1_intr_disable(tile_to_xe(tile));
> >
> > - gt_irq_reset(gt);
> > + gt_irq_reset(tile);
> >
> > - mask_and_disable(gt, GU_MISC_IRQ_OFFSET);
> > - mask_and_disable(gt, PCU_IRQ_OFFSET);
> > + mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
> > + mask_and_disable(tile, PCU_IRQ_OFFSET);
> > }
> >
> > static void xe_irq_reset(struct xe_device *xe)
> > {
> > - struct xe_gt *gt;
> > + struct xe_tile *tile;
> > u8 id;
> >
> > - for_each_gt(gt, xe, id) {
> > + for_each_tile(tile, xe, id) {
> > if (GRAPHICS_VERx100(xe) >= 1210)
> > - dg1_irq_reset(gt);
> > + dg1_irq_reset(tile);
> > else
> > - xelp_irq_reset(gt);
> > + xelp_irq_reset(tile);
> > }
> >
> > xe_display_irq_reset(xe);
> > }
> >
> > -void xe_gt_irq_postinstall(struct xe_gt *gt)
> > +void xe_gt_irq_postinstall(struct xe_tile *tile)
> > {
> > - struct xe_device *xe = gt_to_xe(gt);
> > + struct xe_device *xe = tile_to_xe(tile);
> >
> > if (GRAPHICS_VERx100(xe) >= 1210)
> > - dg1_irq_postinstall(xe, gt);
> > + dg1_irq_postinstall(xe, tile);
> > else
> > - xelp_irq_postinstall(xe, gt);
> > + xelp_irq_postinstall(xe, tile);
> > }
> >
> > static void xe_irq_postinstall(struct xe_device *xe)
> > {
> > - struct xe_gt *gt;
> > + struct xe_tile *tile;
> > u8 id;
> >
> > - for_each_gt(gt, xe, id)
> > - xe_gt_irq_postinstall(gt);
> > + for_each_tile(tile, xe, id)
> > + xe_gt_irq_postinstall(tile);
> >
> > xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));
> > }
> > diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
> > index 34ecf22b32d3..69113c21e1cd 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.h
> > +++ b/drivers/gpu/drm/xe/xe_irq.h
> > @@ -7,10 +7,10 @@
> > #define _XE_IRQ_H_
> >
> > struct xe_device;
> > -struct xe_gt;
> > +struct xe_tile;
> >
> > int xe_irq_install(struct xe_device *xe);
> > -void xe_gt_irq_postinstall(struct xe_gt *gt);
> > +void xe_gt_irq_postinstall(struct xe_tile *tile);
> > void xe_irq_shutdown(struct xe_device *xe);
> > void xe_irq_suspend(struct xe_device *xe);
> > void xe_irq_resume(struct xe_device *xe);
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [Intel-xe] [PATCH v2 27/30] drm/xe: Allow GT looping and lookup on standalone media
2023-05-26 22:37 ` Lucas De Marchi
@ 2023-05-30 16:41 ` Matt Roper
0 siblings, 0 replies; 54+ messages in thread
From: Matt Roper @ 2023-05-30 16:41 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
On Fri, May 26, 2023 at 03:37:07PM -0700, Lucas De Marchi wrote:
> On Fri, May 19, 2023 at 04:18:24PM -0700, Matt Roper wrote:
> > Allow xe_device_get_gt() and for_each_gt() to operate as expected on
> > platforms with standalone media.
> >
> > FIXME: We need to figure out a consistent ID scheme for GTs. At the
> > moment our platforms either have multi-tile (i.e., PVC) or standalone
> > media (MTL) but not both. If a future platform supports both of these
> > capabilities at the same time, how will we number the GTs of the
> > platform? primary-primary-media-media? primary-media-primary-media?
> > For that matter should we even still be exposing the concept of 'GT' to
> > userspace or should that switch to tile instead (and keep the hardware's
> > separation of render and media an internal implementation detail like it
> > is on i915)? If we only expose tiles to userspace and not GTs, then we
> > may not even need per-GT ID numbers anymore.
>
> is this something to leave on the commit or something to solve now?
> I think userspace may care about what tile the GT is located, but not
> much about the order... I think just making it a depth-first on each
> tile would be ok and we can have a tile as a gt attribute.
>
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_device.h | 27 +++++++++++++++++++++------
> > 1 file changed, 21 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
> > index 156c62ac0381..e0085fcd3f47 100644
> > --- a/drivers/gpu/drm/xe/xe_device.h
> > +++ b/drivers/gpu/drm/xe/xe_device.h
> > @@ -55,16 +55,27 @@ static inline struct xe_tile *xe_device_get_root_tile(struct xe_device *xe)
> >
> > static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
> > {
> > + struct xe_tile *root_tile = xe_device_get_root_tile(xe);
> > struct xe_gt *gt;
> >
> > - XE_BUG_ON(gt_id > XE_MAX_TILES_PER_DEVICE);
> > + if (drm_WARN_ON(&xe->drm, gt_id > XE_MAX_TILES_PER_DEVICE))
>
> this condition is odd.
>
> > + return root_tile->primary_gt;
> >
> > - gt = xe->tiles[gt_id].primary_gt;
> > - if (drm_WARN_ON(&xe->drm, !gt))
> > + /*
> > + * FIXME: This only works for now because multi-tile and standalone
> > + * media are mutually exclusive on the platforms we have today.
> > + */
> > + if (MEDIA_VER(xe) >= 13) {
> > + gt = gt_id ? root_tile->media_gt : root_tile->primary_gt;
> > + } else {
> > + gt = xe->tiles[gt_id].primary_gt;
> > + }
>
> I would expect something like:
>
> for_each_tile(...)
> for_each_gt(...)
> if (gt->id == gt_id)
> return gt_id
>
> which could be optimized by reserving the gt numbers
> with XE_MAX_TILES_PER_DEVICE
>
> #define XE_MAX_GTS_PER_TILE 2
>
> tile = gt_id / XE_MAX_GTS_PER_TILE;
> gt = gt_id % XE_MAX_GTS_PER_TILE;
> return !gt ? xe->tiles[tile].primary_gt : xe->tiles[tile].media_gt;
That seems more natural, but it does cause an immediate uapi change that
I'm not sure userspace can cope with without changes on their side
(i.e., the GT IDs for PVC would become 0 and 2 instead of 0 and 1).
With this initial series I was hoping to keep things working as-is for
now while we figure out the bigger question of what we want our UAPI to
look like. From an IOCTL point of view, it seems like userspace only
ever cares about tiles rather than GTs, although from a sysfs/debugfs
point of view there are some places where exposing both concepts is
important (e.g., GT-level power management). Maybe GTs don't even
really need user-visible IDs as long as we come up with sensible
sysfs/debugfs interfaces?
Whatever we decide, I think there's definitely a bunch of places in the
uapi that will need to be cleaned up to work with GTs and/or tiles
appropriately. But that might be best left to a follow-up series
specifically focused on whatever UAPI changes we settle on?
>
> but hey... why are we not keeping a gt[] to make things simpler instead
> of calling them explicitly primary_gt/media_gt?
I used gt[] in an early version, but switched to explicit primary /
media pointers because it made GTs and tiles more distinct and made it
harder to accidentally use GT indices where tile indices should have
been used or vice-versa.
Matt
>
> Lucas De Marchi
>
> > +
> > + if (!gt)
> > return NULL;
> >
> > - XE_BUG_ON(gt->info.id != gt_id);
> > - XE_BUG_ON(gt->info.type == XE_GT_TYPE_UNINITIALIZED);
> > + drm_WARN_ON(&xe->drm, gt->info.id != gt_id);
> > + drm_WARN_ON(&xe->drm, gt->info.type == XE_GT_TYPE_UNINITIALIZED);
> >
> > return gt;
> > }
> > @@ -98,8 +109,12 @@ static inline void xe_device_guc_submission_disable(struct xe_device *xe)
> > for ((id__) = 0; (id__) < (xe__)->info.tile_count; (id__++)) \
> > for_each_if ((tile__) = &(xe__)->tiles[(id__)])
> >
> > +/*
> > + * FIXME: This only works for now since multi-tile and standalone media
> > + * happen to be mutually exclusive. Future platforms may change this...
> > + */
> > #define for_each_gt(gt__, xe__, id__) \
> > - for ((id__) = 0; (id__) < (xe__)->info.tile_count; (id__++)) \
> > + for ((id__) = 0; (id__) < (xe__)->info.tile_count + (MEDIA_VER(xe__) >= 13 ? 1 : 0); (id__++)) \
> > for_each_if ((gt__) = xe_device_get_gt((xe__), (id__)))
> >
> > static inline struct xe_force_wake * gt_to_fw(struct xe_gt *gt)
> > --
> > 2.40.0
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 54+ messages in thread
end of thread, other threads:[~2023-05-30 16:41 UTC | newest]
Thread overview: 54+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
2023-05-19 23:17 ` [Intel-xe] [PATCH v2 01/30] drm/xe/mtl: Disable media GT Matt Roper
2023-05-20 5:50 ` Lucas De Marchi
2023-05-19 23:17 ` [Intel-xe] [PATCH v2 02/30] drm/xe: Introduce xe_tile Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 03/30] drm/xe: Add backpointer from gt to tile Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 04/30] drm/xe: Add for_each_tile iterator Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 05/30] drm/xe: Move register MMIO into xe_tile Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 06/30] fixup! drm/xe/display: Implement display support Matt Roper
2023-05-20 5:52 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 07/30] drm/xe: Move GGTT from GT to tile Matt Roper
2023-05-25 23:29 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 08/30] fixup! drm/xe/display: Implement display support Matt Roper
2023-05-25 23:30 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 09/30] drm/xe: Move VRAM from GT to tile Matt Roper
2023-05-26 21:11 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 10/30] fixup! drm/xe/display: Implement display support Matt Roper
2023-05-26 21:12 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 11/30] drm/xe: Memory allocations are tile-based, not GT-based Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 12/30] fixup! drm/xe/display: Implement display support Matt Roper
2023-05-26 21:14 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 13/30] drm/xe: Move migration from GT to tile Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 14/30] drm/xe: Clarify 'gt' retrieval for primary tile Matt Roper
2023-05-22 11:47 ` Das, Nirmoy
2023-05-26 21:33 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 15/30] drm/xe: Drop vram_id Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 16/30] drm/xe: Drop extra_gts[] declarations and XE_GT_TYPE_REMOTE Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 17/30] drm/xe: Allocate GT dynamically Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 18/30] drm/xe: Add media GT to tile Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 19/30] drm/xe: Move display IRQ postinstall out of GT function Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 20/30] drm/xe: Interrupts are delivered per-tile, not per-GT Matt Roper
2023-05-26 22:16 ` Lucas De Marchi
2023-05-30 6:36 ` Iddamsetty, Aravind
2023-05-30 15:58 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 21/30] drm/xe/irq: Handle ASLE backlight interrupts at same time as display Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 22/30] drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt mask Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 23/30] drm/xe/irq: Untangle postinstall functions Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 24/30] drm/xe: Replace xe_gt_irq_postinstall with xe_irq_enable_hwe Matt Roper
2023-05-26 22:20 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 25/30] drm/xe: Invalidate TLB on all affected GTs during GGTT updates Matt Roper
2023-05-22 9:02 ` Das, Nirmoy
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 26/30] drm/xe/tlb: Obtain forcewake when doing GGTT TLB invalidations Matt Roper
2023-05-22 11:47 ` Das, Nirmoy
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 27/30] drm/xe: Allow GT looping and lookup on standalone media Matt Roper
2023-05-26 22:37 ` Lucas De Marchi
2023-05-30 16:41 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 28/30] drm/xe: Update query uapi to support " Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 29/30] drm/xe: Reinstate media GT support Matt Roper
2023-05-26 22:46 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 30/30] drm/xe: Add kerneldoc description of multi-tile devices Matt Roper
2023-05-26 22:52 ` Lucas De Marchi
2023-05-27 0:22 ` Matt Roper
2023-05-19 23:23 ` [Intel-xe] ✓ CI.Patch_applied: success for Separate GT and tile (rev3) Patchwork
2023-05-19 23:26 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
2023-05-19 23:29 ` [Intel-xe] ✓ CI.Build: " Patchwork
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