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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	linux-riscv@lists.infradead.org, Icenowy Zheng <uwu@icenowy.me>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Guo Ren <guoren@kernel.org>, Yangtao Li <frank.li@vivo.com>,
	Conor Dooley <conor+dt@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	devicetree@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Marc Zyngier <maz@kernel.org>, Wei Fu <wefu@redhat.com>
Subject: Re: [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset
Date: Tue, 30 May 2023 14:55:27 +0200	[thread overview]
Message-ID: <20230530125527.njppujzixnv3bbjd@krzk-bin> (raw)
In-Reply-To: <20230518184541.2627-5-jszhang@kernel.org>

On Fri, 19 May 2023 02:45:36 +0800, Jisheng Zhang wrote:
> The secondary CPUs in T-HEAD SMP capable platforms need some special
> handling. The first one is to write the warm reset entry to entry
> register. The second one is write a SoC specific control value to
> a SoC specific control reg. The last one is to clone some CSRs for
> secondary CPUs to ensure these CSRs' values are the same as the
> main boot CPU. This DT node is mainly used by opensbi firmware.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  .../bindings/riscv/thead,cpu-reset.yaml       | 69 +++++++++++++++++++
>  1 file changed, 69 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dts:18.35-25.11: Warning (unit_address_vs_reg): /example-0/cpurst@ffff019050: node has a unit name, but no reg or ranges property
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dtb: cpurst@ffff019050: control-reg:0: [255, 4278276100] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1783487

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: devicetree@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>,
	Albert Ou <aou@eecs.berkeley.edu>, Yangtao Li <frank.li@vivo.com>,
	Marc Zyngier <maz@kernel.org>,
	linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Guo Ren <guoren@kernel.org>,
	linux-riscv@lists.infradead.org,
	Thomas Gleixner <tglx@linutronix.de>, Wei Fu <wefu@redhat.com>
Subject: Re: [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset
Date: Tue, 30 May 2023 14:55:27 +0200	[thread overview]
Message-ID: <20230530125527.njppujzixnv3bbjd@krzk-bin> (raw)
In-Reply-To: <20230518184541.2627-5-jszhang@kernel.org>

On Fri, 19 May 2023 02:45:36 +0800, Jisheng Zhang wrote:
> The secondary CPUs in T-HEAD SMP capable platforms need some special
> handling. The first one is to write the warm reset entry to entry
> register. The second one is write a SoC specific control value to
> a SoC specific control reg. The last one is to clone some CSRs for
> secondary CPUs to ensure these CSRs' values are the same as the
> main boot CPU. This DT node is mainly used by opensbi firmware.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  .../bindings/riscv/thead,cpu-reset.yaml       | 69 +++++++++++++++++++
>  1 file changed, 69 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dts:18.35-25.11: Warning (unit_address_vs_reg): /example-0/cpurst@ffff019050: node has a unit name, but no reg or ranges property
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dtb: cpurst@ffff019050: control-reg:0: [255, 4278276100] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1783487

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2023-05-30 12:56 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-18 18:45 [PATCH v2 0/9] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-05-18 18:45 ` Jisheng Zhang
2023-05-18 18:45 ` [PATCH v2 1/9] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Jisheng Zhang
2023-05-18 18:45   ` Jisheng Zhang
2023-05-18 19:36   ` Conor Dooley
2023-05-18 19:36     ` Conor Dooley
2023-05-21 13:14   ` Guo Ren
2023-05-21 13:14     ` Guo Ren
2023-05-18 18:45 ` [PATCH v2 2/9] dt-bindings: timer: Add T-HEAD TH1520 clint Jisheng Zhang
2023-05-18 18:45   ` Jisheng Zhang
2023-05-18 19:37   ` Conor Dooley
2023-05-18 19:37     ` Conor Dooley
2023-05-18 18:45 ` [PATCH v2 3/9] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Jisheng Zhang
2023-05-18 18:45   ` Jisheng Zhang
2023-05-18 19:40   ` Conor Dooley
2023-05-18 19:40     ` Conor Dooley
2023-05-19 15:50     ` Icenowy Zheng
2023-05-19 15:50       ` Icenowy Zheng
2023-05-18 18:45 ` [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset Jisheng Zhang
2023-05-18 18:45   ` Jisheng Zhang
2023-05-18 19:39   ` Rob Herring
2023-05-18 19:39     ` Rob Herring
2023-05-18 19:53   ` Conor Dooley
2023-05-18 19:53     ` Conor Dooley
2023-05-22  2:16     ` Guo Ren
2023-05-22  2:16       ` Guo Ren
2023-05-22  7:09       ` Conor Dooley
2023-05-22  7:09         ` Conor Dooley
2023-05-22  7:42         ` Guo Ren
2023-05-22  7:42           ` Guo Ren
2023-05-30 12:55   ` Krzysztof Kozlowski [this message]
2023-05-30 12:55     ` Krzysztof Kozlowski
2023-05-18 18:45 ` [PATCH v2 5/9] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-05-18 18:45   ` Jisheng Zhang
2023-05-18 19:42   ` Conor Dooley
2023-05-18 19:42     ` Conor Dooley
2023-05-18 18:45 ` [PATCH v2 6/9] riscv: dts: add initial T-HEAD TH1520 SoC device tree Jisheng Zhang
2023-05-18 18:45   ` Jisheng Zhang
2023-05-18 21:02   ` Conor Dooley
2023-05-18 21:02     ` Conor Dooley
2023-05-26  2:21   ` Yixun Lan
2023-05-26  2:21     ` Yixun Lan
2023-05-18 18:45 ` [PATCH v2 7/9] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-05-18 18:45   ` Jisheng Zhang
2023-05-18 21:03   ` Conor Dooley
2023-05-18 21:03     ` Conor Dooley
2023-05-18 18:45 ` [PATCH v2 8/9] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-05-18 18:45   ` Jisheng Zhang
2023-05-18 20:57   ` Conor Dooley
2023-05-18 20:57     ` Conor Dooley
2023-05-18 18:45 ` [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC Jisheng Zhang
2023-05-18 18:45   ` Jisheng Zhang
2023-05-18 20:58   ` Conor Dooley
2023-05-18 20:58     ` Conor Dooley
2023-05-19 20:56   ` Palmer Dabbelt
2023-05-19 20:56     ` Palmer Dabbelt
2023-05-20  1:16     ` Guo Ren
2023-05-20  1:16       ` Guo Ren
2023-05-26  2:19 ` [PATCH v2 0/9] Add Sipeed Lichee Pi 4A RISC-V board support Yixun Lan
2023-05-26  2:19   ` Yixun Lan

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