* [PATCH 0/2] mtd: rawnand: marvell: add support for AC5 SoC @ 2023-05-31 2:58 ` Chris Packham 0 siblings, 0 replies; 12+ messages in thread From: Chris Packham @ 2023-05-31 2:58 UTC (permalink / raw) To: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare Cc: linux-mtd, devicetree, linux-kernel, Chris Packham This series adds support for the NAND Flash Controller on the AC5/AC5X SOC. It needs to be applied on top of two other recent series [1] (applied to mtd/fixes, not yet in mainline) [2] (v7 out for review). I've tried to stick to the minimal changes required to get the NFC working on the board I have (AC5X + S34ML02G2). Marvell's SDK has hard coded tables of ndtr values for the different timing modes but so far that seems unnecessary. [1] - https://lore.kernel.org/linux-mtd/20230525003154.2303012-1-chris.packham@alliedtelesis.co.nz/raw [2] - https://lore.kernel.org/linux-mtd/20230530235456.1009082-1-chris.packham@alliedtelesis.co.nz/raw Chris Packham (2): dt-bindings: mtd: Add AC5 specific binding mtd: rawnand: marvell: add support for AC5 SoC .../bindings/mtd/marvell,nand-controller.yaml | 1 + drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ 3 files changed, 18 insertions(+), 1 deletion(-) -- 2.40.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/2] mtd: rawnand: marvell: add support for AC5 SoC @ 2023-05-31 2:58 ` Chris Packham 0 siblings, 0 replies; 12+ messages in thread From: Chris Packham @ 2023-05-31 2:58 UTC (permalink / raw) To: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare Cc: linux-mtd, devicetree, linux-kernel, Chris Packham This series adds support for the NAND Flash Controller on the AC5/AC5X SOC. It needs to be applied on top of two other recent series [1] (applied to mtd/fixes, not yet in mainline) [2] (v7 out for review). I've tried to stick to the minimal changes required to get the NFC working on the board I have (AC5X + S34ML02G2). Marvell's SDK has hard coded tables of ndtr values for the different timing modes but so far that seems unnecessary. [1] - https://lore.kernel.org/linux-mtd/20230525003154.2303012-1-chris.packham@alliedtelesis.co.nz/raw [2] - https://lore.kernel.org/linux-mtd/20230530235456.1009082-1-chris.packham@alliedtelesis.co.nz/raw Chris Packham (2): dt-bindings: mtd: Add AC5 specific binding mtd: rawnand: marvell: add support for AC5 SoC .../bindings/mtd/marvell,nand-controller.yaml | 1 + drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ 3 files changed, 18 insertions(+), 1 deletion(-) -- 2.40.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/2] dt-bindings: mtd: Add AC5 specific binding 2023-05-31 2:58 ` Chris Packham @ 2023-05-31 2:58 ` Chris Packham -1 siblings, 0 replies; 12+ messages in thread From: Chris Packham @ 2023-05-31 2:58 UTC (permalink / raw) To: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare Cc: linux-mtd, devicetree, linux-kernel, Chris Packham Add binding for AC5 SoC. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- .../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml index 80ce854291cb..c09efd7a0043 100644 --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml @@ -18,6 +18,7 @@ properties: - enum: - marvell,armada370-nand-controller - marvell,pxa3xx-nand-controller + - marvell,ac5-nand-controller reg: maxItems: 1 -- 2.40.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/2] dt-bindings: mtd: Add AC5 specific binding @ 2023-05-31 2:58 ` Chris Packham 0 siblings, 0 replies; 12+ messages in thread From: Chris Packham @ 2023-05-31 2:58 UTC (permalink / raw) To: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare Cc: linux-mtd, devicetree, linux-kernel, Chris Packham Add binding for AC5 SoC. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- .../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml index 80ce854291cb..c09efd7a0043 100644 --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml @@ -18,6 +18,7 @@ properties: - enum: - marvell,armada370-nand-controller - marvell,pxa3xx-nand-controller + - marvell,ac5-nand-controller reg: maxItems: 1 -- 2.40.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mtd: Add AC5 specific binding 2023-05-31 2:58 ` Chris Packham @ 2023-05-31 12:42 ` Conor Dooley -1 siblings, 0 replies; 12+ messages in thread From: Conor Dooley @ 2023-05-31 12:42 UTC (permalink / raw) To: Chris Packham Cc: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare, linux-mtd, devicetree, linux-kernel [-- Attachment #1: Type: text/plain, Size: 1376 bytes --] On Wed, May 31, 2023 at 02:58:46PM +1200, Chris Packham wrote: > Add binding for AC5 SoC. Ideally the comment about how it has only 3 of something-I-forget would go here too, explaining why you cannot use a fallback compatible. > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > .../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml > index 80ce854291cb..c09efd7a0043 100644 > --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml > +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml > @@ -18,6 +18,7 @@ properties: > - enum: > - marvell,armada370-nand-controller > - marvell,pxa3xx-nand-controller > + - marvell,ac5-nand-controller IFF you end up respinning for another reason, I think alphanumerical order would be preferable. Otherwise, Acked-by: Conor Dooley <conor.dooley@microchip.com> I figure this depends on the conversion, so alphanumerical order would be good to have there from the beginning of the yaml binding's existence if it isn't already. Cheers, Conor. > > reg: > maxItems: 1 > -- > 2.40.1 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mtd: Add AC5 specific binding @ 2023-05-31 12:42 ` Conor Dooley 0 siblings, 0 replies; 12+ messages in thread From: Conor Dooley @ 2023-05-31 12:42 UTC (permalink / raw) To: Chris Packham Cc: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare, linux-mtd, devicetree, linux-kernel [-- Attachment #1.1: Type: text/plain, Size: 1376 bytes --] On Wed, May 31, 2023 at 02:58:46PM +1200, Chris Packham wrote: > Add binding for AC5 SoC. Ideally the comment about how it has only 3 of something-I-forget would go here too, explaining why you cannot use a fallback compatible. > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > .../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml > index 80ce854291cb..c09efd7a0043 100644 > --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml > +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml > @@ -18,6 +18,7 @@ properties: > - enum: > - marvell,armada370-nand-controller > - marvell,pxa3xx-nand-controller > + - marvell,ac5-nand-controller IFF you end up respinning for another reason, I think alphanumerical order would be preferable. Otherwise, Acked-by: Conor Dooley <conor.dooley@microchip.com> I figure this depends on the conversion, so alphanumerical order would be good to have there from the beginning of the yaml binding's existence if it isn't already. Cheers, Conor. > > reg: > maxItems: 1 > -- > 2.40.1 > [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 144 bytes --] ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/2] mtd: rawnand: marvell: add support for AC5 SoC 2023-05-31 2:58 ` Chris Packham @ 2023-05-31 2:58 ` Chris Packham -1 siblings, 0 replies; 12+ messages in thread From: Chris Packham @ 2023-05-31 2:58 UTC (permalink / raw) To: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare Cc: linux-mtd, devicetree, linux-kernel, Chris Packham Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only supports SDR modes up to 3. Marvell's SDK includes some predefined values for the ndtr registers. These haven't been incorporated as the existing code seems to get good values based on measurements taken with an oscilloscope. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b523354dfb00..0f4cbb497010 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -160,7 +160,7 @@ config MTD_NAND_MARVELL including: - PXA3xx processors (NFCv1) - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) - - 64-bit Aramda platforms (7k, 8k) (NFCv2) + - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2) config MTD_NAND_SLC_LPC32XX tristate "NXP LPC32xx SLC NAND controller" diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index 30c15e4e1cc0..b9a8dd324211 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip * BCH error detection and correction algorithm, * NDCB3 register has been added * @use_dma: Use dma for data transfers + * @max_mode_number: Maximum timing mode supported by the controller */ struct marvell_nfc_caps { unsigned int max_cs_nb; @@ -383,6 +384,7 @@ struct marvell_nfc_caps { bool legacy_of_bindings; bool is_nfcv2; bool use_dma; + unsigned int max_mode_number; }; /** @@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, if (IS_ERR(sdr)) return PTR_ERR(sdr); + if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode) + return -EOPNOTSUPP; + /* * SDR timings are given in pico-seconds while NFC timings must be * expressed in NAND controller clock cycles, which is half of the @@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { .is_nfcv2 = true, }; +static const struct marvell_nfc_caps marvell_ac5_caps = { + .max_cs_nb = 2, + .max_rb_nb = 1, + .is_nfcv2 = true, + .max_mode_number = 3, +}; + static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { .max_cs_nb = 4, .max_rb_nb = 2, @@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[] = { .compatible = "marvell,armada-8k-nand-controller", .data = &marvell_armada_8k_nfc_caps, }, + { + .compatible = "marvell,ac5-nand-controller", + .data = &marvell_ac5_caps, + }, { .compatible = "marvell,armada370-nand-controller", .data = &marvell_armada370_nfc_caps, -- 2.40.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] mtd: rawnand: marvell: add support for AC5 SoC @ 2023-05-31 2:58 ` Chris Packham 0 siblings, 0 replies; 12+ messages in thread From: Chris Packham @ 2023-05-31 2:58 UTC (permalink / raw) To: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare Cc: linux-mtd, devicetree, linux-kernel, Chris Packham Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only supports SDR modes up to 3. Marvell's SDK includes some predefined values for the ndtr registers. These haven't been incorporated as the existing code seems to get good values based on measurements taken with an oscilloscope. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b523354dfb00..0f4cbb497010 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -160,7 +160,7 @@ config MTD_NAND_MARVELL including: - PXA3xx processors (NFCv1) - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) - - 64-bit Aramda platforms (7k, 8k) (NFCv2) + - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2) config MTD_NAND_SLC_LPC32XX tristate "NXP LPC32xx SLC NAND controller" diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index 30c15e4e1cc0..b9a8dd324211 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip * BCH error detection and correction algorithm, * NDCB3 register has been added * @use_dma: Use dma for data transfers + * @max_mode_number: Maximum timing mode supported by the controller */ struct marvell_nfc_caps { unsigned int max_cs_nb; @@ -383,6 +384,7 @@ struct marvell_nfc_caps { bool legacy_of_bindings; bool is_nfcv2; bool use_dma; + unsigned int max_mode_number; }; /** @@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, if (IS_ERR(sdr)) return PTR_ERR(sdr); + if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode) + return -EOPNOTSUPP; + /* * SDR timings are given in pico-seconds while NFC timings must be * expressed in NAND controller clock cycles, which is half of the @@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { .is_nfcv2 = true, }; +static const struct marvell_nfc_caps marvell_ac5_caps = { + .max_cs_nb = 2, + .max_rb_nb = 1, + .is_nfcv2 = true, + .max_mode_number = 3, +}; + static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { .max_cs_nb = 4, .max_rb_nb = 2, @@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[] = { .compatible = "marvell,armada-8k-nand-controller", .data = &marvell_armada_8k_nfc_caps, }, + { + .compatible = "marvell,ac5-nand-controller", + .data = &marvell_ac5_caps, + }, { .compatible = "marvell,armada370-nand-controller", .data = &marvell_armada370_nfc_caps, -- 2.40.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] mtd: rawnand: marvell: add support for AC5 SoC 2023-05-31 2:58 ` Chris Packham @ 2023-05-31 7:37 ` Miquel Raynal -1 siblings, 0 replies; 12+ messages in thread From: Miquel Raynal @ 2023-05-31 7:37 UTC (permalink / raw) To: Chris Packham Cc: richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare, linux-mtd, devicetree, linux-kernel Hi Chris, chris.packham@alliedtelesis.co.nz wrote on Wed, 31 May 2023 14:58:47 +1200: > Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only > supports SDR modes up to 3. Strange! But alright, I'm okay with the series. I'll put it aside waiting for all binding changes to be acked (yaml conversion series + this one) and then I'll apply everything. > Marvell's SDK includes some predefined values for the ndtr registers. > These haven't been incorporated as the existing code seems to get good > values based on measurements taken with an oscilloscope. Good :) By the way did you sort the timings question on 8k? > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > drivers/mtd/nand/raw/Kconfig | 2 +- > drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ > 2 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > index b523354dfb00..0f4cbb497010 100644 > --- a/drivers/mtd/nand/raw/Kconfig > +++ b/drivers/mtd/nand/raw/Kconfig > @@ -160,7 +160,7 @@ config MTD_NAND_MARVELL > including: > - PXA3xx processors (NFCv1) > - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) > - - 64-bit Aramda platforms (7k, 8k) (NFCv2) > + - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2) > > config MTD_NAND_SLC_LPC32XX > tristate "NXP LPC32xx SLC NAND controller" > diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c > index 30c15e4e1cc0..b9a8dd324211 100644 > --- a/drivers/mtd/nand/raw/marvell_nand.c > +++ b/drivers/mtd/nand/raw/marvell_nand.c > @@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip > * BCH error detection and correction algorithm, > * NDCB3 register has been added > * @use_dma: Use dma for data transfers > + * @max_mode_number: Maximum timing mode supported by the controller > */ > struct marvell_nfc_caps { > unsigned int max_cs_nb; > @@ -383,6 +384,7 @@ struct marvell_nfc_caps { > bool legacy_of_bindings; > bool is_nfcv2; > bool use_dma; > + unsigned int max_mode_number; > }; > > /** > @@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, > if (IS_ERR(sdr)) > return PTR_ERR(sdr); > > + if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode) > + return -EOPNOTSUPP; > + > /* > * SDR timings are given in pico-seconds while NFC timings must be > * expressed in NAND controller clock cycles, which is half of the > @@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { > .is_nfcv2 = true, > }; > > +static const struct marvell_nfc_caps marvell_ac5_caps = { > + .max_cs_nb = 2, > + .max_rb_nb = 1, > + .is_nfcv2 = true, > + .max_mode_number = 3, > +}; > + > static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { > .max_cs_nb = 4, > .max_rb_nb = 2, > @@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[] = { > .compatible = "marvell,armada-8k-nand-controller", > .data = &marvell_armada_8k_nfc_caps, > }, > + { > + .compatible = "marvell,ac5-nand-controller", > + .data = &marvell_ac5_caps, > + }, > { > .compatible = "marvell,armada370-nand-controller", > .data = &marvell_armada370_nfc_caps, Thanks, Miquèl ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] mtd: rawnand: marvell: add support for AC5 SoC @ 2023-05-31 7:37 ` Miquel Raynal 0 siblings, 0 replies; 12+ messages in thread From: Miquel Raynal @ 2023-05-31 7:37 UTC (permalink / raw) To: Chris Packham Cc: richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare, linux-mtd, devicetree, linux-kernel Hi Chris, chris.packham@alliedtelesis.co.nz wrote on Wed, 31 May 2023 14:58:47 +1200: > Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only > supports SDR modes up to 3. Strange! But alright, I'm okay with the series. I'll put it aside waiting for all binding changes to be acked (yaml conversion series + this one) and then I'll apply everything. > Marvell's SDK includes some predefined values for the ndtr registers. > These haven't been incorporated as the existing code seems to get good > values based on measurements taken with an oscilloscope. Good :) By the way did you sort the timings question on 8k? > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > drivers/mtd/nand/raw/Kconfig | 2 +- > drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ > 2 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > index b523354dfb00..0f4cbb497010 100644 > --- a/drivers/mtd/nand/raw/Kconfig > +++ b/drivers/mtd/nand/raw/Kconfig > @@ -160,7 +160,7 @@ config MTD_NAND_MARVELL > including: > - PXA3xx processors (NFCv1) > - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) > - - 64-bit Aramda platforms (7k, 8k) (NFCv2) > + - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2) > > config MTD_NAND_SLC_LPC32XX > tristate "NXP LPC32xx SLC NAND controller" > diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c > index 30c15e4e1cc0..b9a8dd324211 100644 > --- a/drivers/mtd/nand/raw/marvell_nand.c > +++ b/drivers/mtd/nand/raw/marvell_nand.c > @@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip > * BCH error detection and correction algorithm, > * NDCB3 register has been added > * @use_dma: Use dma for data transfers > + * @max_mode_number: Maximum timing mode supported by the controller > */ > struct marvell_nfc_caps { > unsigned int max_cs_nb; > @@ -383,6 +384,7 @@ struct marvell_nfc_caps { > bool legacy_of_bindings; > bool is_nfcv2; > bool use_dma; > + unsigned int max_mode_number; > }; > > /** > @@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, > if (IS_ERR(sdr)) > return PTR_ERR(sdr); > > + if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode) > + return -EOPNOTSUPP; > + > /* > * SDR timings are given in pico-seconds while NFC timings must be > * expressed in NAND controller clock cycles, which is half of the > @@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { > .is_nfcv2 = true, > }; > > +static const struct marvell_nfc_caps marvell_ac5_caps = { > + .max_cs_nb = 2, > + .max_rb_nb = 1, > + .is_nfcv2 = true, > + .max_mode_number = 3, > +}; > + > static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { > .max_cs_nb = 4, > .max_rb_nb = 2, > @@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[] = { > .compatible = "marvell,armada-8k-nand-controller", > .data = &marvell_armada_8k_nfc_caps, > }, > + { > + .compatible = "marvell,ac5-nand-controller", > + .data = &marvell_ac5_caps, > + }, > { > .compatible = "marvell,armada370-nand-controller", > .data = &marvell_armada370_nfc_caps, Thanks, Miquèl ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] mtd: rawnand: marvell: add support for AC5 SoC 2023-05-31 7:37 ` Miquel Raynal @ 2023-05-31 21:31 ` Chris Packham -1 siblings, 0 replies; 12+ messages in thread From: Chris Packham @ 2023-05-31 21:31 UTC (permalink / raw) To: Miquel Raynal Cc: richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare, linux-mtd, devicetree, linux-kernel On 31/05/23 19:37, Miquel Raynal wrote: > Hi Chris, > > chris.packham@alliedtelesis.co.nz wrote on Wed, 31 May 2023 14:58:47 > +1200: > >> Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only >> supports SDR modes up to 3. > Strange! Yeah I'm a bit surprised too. They only recently updated the datasheet to say it supported mode 3 so I think maybe they're qualifying things as they go. > But alright, I'm okay with the series. > > I'll put it aside waiting for all binding changes to be acked (yaml > conversion series + this one) and then I'll apply everything. > >> Marvell's SDK includes some predefined values for the ndtr registers. >> These haven't been incorporated as the existing code seems to get good >> values based on measurements taken with an oscilloscope. > Good :) > > By the way did you sort the timings question on 8k? Yes with those two patches you've already applied the 8k seems good as far as I'm concerned. >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >> --- >> drivers/mtd/nand/raw/Kconfig | 2 +- >> drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ >> 2 files changed, 17 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig >> index b523354dfb00..0f4cbb497010 100644 >> --- a/drivers/mtd/nand/raw/Kconfig >> +++ b/drivers/mtd/nand/raw/Kconfig >> @@ -160,7 +160,7 @@ config MTD_NAND_MARVELL >> including: >> - PXA3xx processors (NFCv1) >> - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) >> - - 64-bit Aramda platforms (7k, 8k) (NFCv2) >> + - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2) >> >> config MTD_NAND_SLC_LPC32XX >> tristate "NXP LPC32xx SLC NAND controller" >> diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c >> index 30c15e4e1cc0..b9a8dd324211 100644 >> --- a/drivers/mtd/nand/raw/marvell_nand.c >> +++ b/drivers/mtd/nand/raw/marvell_nand.c >> @@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip >> * BCH error detection and correction algorithm, >> * NDCB3 register has been added >> * @use_dma: Use dma for data transfers >> + * @max_mode_number: Maximum timing mode supported by the controller >> */ >> struct marvell_nfc_caps { >> unsigned int max_cs_nb; >> @@ -383,6 +384,7 @@ struct marvell_nfc_caps { >> bool legacy_of_bindings; >> bool is_nfcv2; >> bool use_dma; >> + unsigned int max_mode_number; >> }; >> >> /** >> @@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, >> if (IS_ERR(sdr)) >> return PTR_ERR(sdr); >> >> + if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode) >> + return -EOPNOTSUPP; >> + >> /* >> * SDR timings are given in pico-seconds while NFC timings must be >> * expressed in NAND controller clock cycles, which is half of the >> @@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { >> .is_nfcv2 = true, >> }; >> >> +static const struct marvell_nfc_caps marvell_ac5_caps = { >> + .max_cs_nb = 2, >> + .max_rb_nb = 1, >> + .is_nfcv2 = true, >> + .max_mode_number = 3, >> +}; >> + >> static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { >> .max_cs_nb = 4, >> .max_rb_nb = 2, >> @@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[] = { >> .compatible = "marvell,armada-8k-nand-controller", >> .data = &marvell_armada_8k_nfc_caps, >> }, >> + { >> + .compatible = "marvell,ac5-nand-controller", >> + .data = &marvell_ac5_caps, >> + }, >> { >> .compatible = "marvell,armada370-nand-controller", >> .data = &marvell_armada370_nfc_caps, > > Thanks, > Miquèl ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] mtd: rawnand: marvell: add support for AC5 SoC @ 2023-05-31 21:31 ` Chris Packham 0 siblings, 0 replies; 12+ messages in thread From: Chris Packham @ 2023-05-31 21:31 UTC (permalink / raw) To: Miquel Raynal Cc: richard, vigneshr, robh+dt, krzysztof.kozlowski+dt, conor+dt, arnd, daniel.lezcano, neil.armstrong, f.fainelli, christophe.kerello, liang.yang, jdelvare, linux-mtd, devicetree, linux-kernel On 31/05/23 19:37, Miquel Raynal wrote: > Hi Chris, > > chris.packham@alliedtelesis.co.nz wrote on Wed, 31 May 2023 14:58:47 > +1200: > >> Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only >> supports SDR modes up to 3. > Strange! Yeah I'm a bit surprised too. They only recently updated the datasheet to say it supported mode 3 so I think maybe they're qualifying things as they go. > But alright, I'm okay with the series. > > I'll put it aside waiting for all binding changes to be acked (yaml > conversion series + this one) and then I'll apply everything. > >> Marvell's SDK includes some predefined values for the ndtr registers. >> These haven't been incorporated as the existing code seems to get good >> values based on measurements taken with an oscilloscope. > Good :) > > By the way did you sort the timings question on 8k? Yes with those two patches you've already applied the 8k seems good as far as I'm concerned. >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >> --- >> drivers/mtd/nand/raw/Kconfig | 2 +- >> drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ >> 2 files changed, 17 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig >> index b523354dfb00..0f4cbb497010 100644 >> --- a/drivers/mtd/nand/raw/Kconfig >> +++ b/drivers/mtd/nand/raw/Kconfig >> @@ -160,7 +160,7 @@ config MTD_NAND_MARVELL >> including: >> - PXA3xx processors (NFCv1) >> - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) >> - - 64-bit Aramda platforms (7k, 8k) (NFCv2) >> + - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2) >> >> config MTD_NAND_SLC_LPC32XX >> tristate "NXP LPC32xx SLC NAND controller" >> diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c >> index 30c15e4e1cc0..b9a8dd324211 100644 >> --- a/drivers/mtd/nand/raw/marvell_nand.c >> +++ b/drivers/mtd/nand/raw/marvell_nand.c >> @@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip >> * BCH error detection and correction algorithm, >> * NDCB3 register has been added >> * @use_dma: Use dma for data transfers >> + * @max_mode_number: Maximum timing mode supported by the controller >> */ >> struct marvell_nfc_caps { >> unsigned int max_cs_nb; >> @@ -383,6 +384,7 @@ struct marvell_nfc_caps { >> bool legacy_of_bindings; >> bool is_nfcv2; >> bool use_dma; >> + unsigned int max_mode_number; >> }; >> >> /** >> @@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, >> if (IS_ERR(sdr)) >> return PTR_ERR(sdr); >> >> + if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode) >> + return -EOPNOTSUPP; >> + >> /* >> * SDR timings are given in pico-seconds while NFC timings must be >> * expressed in NAND controller clock cycles, which is half of the >> @@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { >> .is_nfcv2 = true, >> }; >> >> +static const struct marvell_nfc_caps marvell_ac5_caps = { >> + .max_cs_nb = 2, >> + .max_rb_nb = 1, >> + .is_nfcv2 = true, >> + .max_mode_number = 3, >> +}; >> + >> static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { >> .max_cs_nb = 4, >> .max_rb_nb = 2, >> @@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[] = { >> .compatible = "marvell,armada-8k-nand-controller", >> .data = &marvell_armada_8k_nfc_caps, >> }, >> + { >> + .compatible = "marvell,ac5-nand-controller", >> + .data = &marvell_ac5_caps, >> + }, >> { >> .compatible = "marvell,armada370-nand-controller", >> .data = &marvell_armada370_nfc_caps, > > Thanks, > Miquèl ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-05-31 22:42 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-05-31 2:58 [PATCH 0/2] mtd: rawnand: marvell: add support for AC5 SoC Chris Packham 2023-05-31 2:58 ` Chris Packham 2023-05-31 2:58 ` [PATCH 1/2] dt-bindings: mtd: Add AC5 specific binding Chris Packham 2023-05-31 2:58 ` Chris Packham 2023-05-31 12:42 ` Conor Dooley 2023-05-31 12:42 ` Conor Dooley 2023-05-31 2:58 ` [PATCH 2/2] mtd: rawnand: marvell: add support for AC5 SoC Chris Packham 2023-05-31 2:58 ` Chris Packham 2023-05-31 7:37 ` Miquel Raynal 2023-05-31 7:37 ` Miquel Raynal 2023-05-31 21:31 ` Chris Packham 2023-05-31 21:31 ` Chris Packham
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