[PATCH] i386/cpu: Don't emulate L3 cache on 8000_001D if l3-cache is disabled

[PATCH] i386/cpu: Don't emulate L3 cache on 8000_001D if l3-cache is disabled

[Yanan Wang via]

Currently, we only avoid emulating L3 cache properties for AMD CPU
when l3-cache is off, but failed to consider this case on CPUID 8000_001D.
This result in a fact that we will still have L3 caches in the VM
although we pass "host-cache-info=off,l3-cache=off" CLI to qemu.

Fixes: 8f4202fb108 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D")
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
---
 target/i386/cpu.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1242bd541a..17c367c5ba 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6337,8 +6337,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
                                        &topo_info, eax, ebx, ecx, edx);
             break;
         case 3: /* L3 cache info */
-            encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
-                                       &topo_info, eax, ebx, ecx, edx);
+            if (cpu->enable_l3_cache) {
+                encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
+                                           &topo_info, eax, ebx, ecx, edx);
+            }
             break;
         default: /* end of info */
             *eax = *ebx = *ecx = *edx = 0;
-- 
2.33.0

Re: [PATCH] i386/cpu: Don't emulate L3 cache on 8000_001D if l3-cache is disabled

[Xiaoyao Li]

On 5/31/2023 8:00 PM, Yanan Wang wrote:
> Currently, we only avoid emulating L3 cache properties for AMD CPU
> when l3-cache is off, but failed to consider this case on CPUID 8000_001D.
> This result in a fact that we will still have L3 caches in the VM
> although we pass "host-cache-info=off,l3-cache=off" CLI to qemu.

Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>

Out of curiosity, do you have a valid real use case to run VM with 
"l3-cache = off"?

> Fixes: 8f4202fb108 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D")
> Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
> ---
>   target/i386/cpu.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 1242bd541a..17c367c5ba 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -6337,8 +6337,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>                                          &topo_info, eax, ebx, ecx, edx);
>               break;
>           case 3: /* L3 cache info */
> -            encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
> -                                       &topo_info, eax, ebx, ecx, edx);
> +            if (cpu->enable_l3_cache) {
> +                encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
> +                                           &topo_info, eax, ebx, ecx, edx);
> +            }
>               break;
>           default: /* end of info */
>               *eax = *ebx = *ecx = *edx = 0;

Re: [PATCH] i386/cpu: Don't emulate L3 cache on 8000_001D if l3-cache is disabled

[wangyanan (Y) via]

在 2023/6/2 14:52, Xiaoyao Li 写道:
> On 5/31/2023 8:00 PM, Yanan Wang wrote:
>> Currently, we only avoid emulating L3 cache properties for AMD CPU
>> when l3-cache is off, but failed to consider this case on CPUID 
>> 8000_001D.
>> This result in a fact that we will still have L3 caches in the VM
>> although we pass "host-cache-info=off,l3-cache=off" CLI to qemu.
>
> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Thanks.
>
> Out of curiosity, do you have a valid real use case to run VM with 
> "l3-cache = off"?
No, actually. This problem is found just in testing.

Yanan.
>
>> Fixes: 8f4202fb108 ("i386: Populate AMD Processor Cache Information 
>> for cpuid 0x8000001D")
>> Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
>> ---
>>   target/i386/cpu.c | 6 ++++--
>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 1242bd541a..17c367c5ba 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -6337,8 +6337,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t 
>> index, uint32_t count,
>>                                          &topo_info, eax, ebx, ecx, 
>> edx);
>>               break;
>>           case 3: /* L3 cache info */
>> - encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
>> -                                       &topo_info, eax, ebx, ecx, edx);
>> +            if (cpu->enable_l3_cache) {
>> + encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
>> +                                           &topo_info, eax, ebx, 
>> ecx, edx);
>> +            }
>>               break;
>>           default: /* end of info */
>>               *eax = *ebx = *ecx = *edx = 0;
>
>