* [PATCH v2 0/3] Add initialization of clock for StarFive JH7110 SoC
@ 2023-06-02 8:49 ` William Qiu
0 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-02 8:49 UTC (permalink / raw)
To: devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu, William Qiu
Hi,
This patchset adds initial rudimentary support for the StarFive
Quad SPI controller driver. And this driver will be used in
StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB
clocks changed from the default ON state to the default OFF state,
so these clocks need to be enabled in the driver.At the same time,
dts patch is added to this series.
Changes v1->v2:
- Renamed the clock names.
- Specified a different array of clocks
- Used clk_bulk_ APIs
The patch series is based on v6.4rc3.
William Qiu (3):
dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
.../bindings/spi/cdns,qspi-nor.yaml | 15 +++++++--
.../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++
drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++
4 files changed, 82 insertions(+), 3 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 0/3] Add initialization of clock for StarFive JH7110 SoC
@ 2023-06-02 8:49 ` William Qiu
0 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-02 8:49 UTC (permalink / raw)
To: devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu, William Qiu
Hi,
This patchset adds initial rudimentary support for the StarFive
Quad SPI controller driver. And this driver will be used in
StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB
clocks changed from the default ON state to the default OFF state,
so these clocks need to be enabled in the driver.At the same time,
dts patch is added to this series.
Changes v1->v2:
- Renamed the clock names.
- Specified a different array of clocks
- Used clk_bulk_ APIs
The patch series is based on v6.4rc3.
William Qiu (3):
dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
.../bindings/spi/cdns,qspi-nor.yaml | 15 +++++++--
.../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++
drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++
4 files changed, 82 insertions(+), 3 deletions(-)
--
2.34.1
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
2023-06-02 8:49 ` William Qiu
@ 2023-06-02 8:49 ` William Qiu
-1 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-02 8:49 UTC (permalink / raw)
To: devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu, William Qiu
The QSPI controller needs three clock items to work properly on StarFive
JH7110 SoC, so there is need to change the maxItems's value to 3. Other
platforms do not have this constraint.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
.../devicetree/bindings/spi/cdns,qspi-nor.yaml | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index b310069762dd..b6a27171d965 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -26,6 +26,15 @@ allOf:
const: starfive,jh7110-qspi
then:
properties:
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: hclk
+ - const: pclk
+
resets:
minItems: 2
maxItems: 3
@@ -38,6 +47,9 @@ allOf:
else:
properties:
+ clocks:
+ maxItems: 1
+
resets:
maxItems: 2
@@ -69,9 +81,6 @@ properties:
interrupts:
maxItems: 1
- clocks:
- maxItems: 1
-
cdns,fifo-depth:
description:
Size of the data FIFO in words.
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
@ 2023-06-02 8:49 ` William Qiu
0 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-02 8:49 UTC (permalink / raw)
To: devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu, William Qiu
The QSPI controller needs three clock items to work properly on StarFive
JH7110 SoC, so there is need to change the maxItems's value to 3. Other
platforms do not have this constraint.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
.../devicetree/bindings/spi/cdns,qspi-nor.yaml | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index b310069762dd..b6a27171d965 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -26,6 +26,15 @@ allOf:
const: starfive,jh7110-qspi
then:
properties:
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: hclk
+ - const: pclk
+
resets:
minItems: 2
maxItems: 3
@@ -38,6 +47,9 @@ allOf:
else:
properties:
+ clocks:
+ maxItems: 1
+
resets:
maxItems: 2
@@ -69,9 +81,6 @@ properties:
interrupts:
maxItems: 1
- clocks:
- maxItems: 1
-
cdns,fifo-depth:
description:
Size of the data FIFO in words.
--
2.34.1
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
2023-06-02 8:49 ` William Qiu
@ 2023-06-02 18:02 ` Conor Dooley
-1 siblings, 0 replies; 24+ messages in thread
From: Conor Dooley @ 2023-06-02 18:02 UTC (permalink / raw)
To: William Qiu
Cc: devicetree, linux-spi, linux-kernel, linux-riscv, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu
[-- Attachment #1: Type: text/plain, Size: 1332 bytes --]
On Fri, Jun 02, 2023 at 04:49:23PM +0800, William Qiu wrote:
> The QSPI controller needs three clock items to work properly on StarFive
> JH7110 SoC, so there is need to change the maxItems's value to 3. Other
> platforms do not have this constraint.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> index b310069762dd..b6a27171d965 100644
> --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> @@ -26,6 +26,15 @@ allOf:
> const: starfive,jh7110-qspi
> then:
> properties:
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + items:
> + - const: ref_clk
Aww, I liked Mark's suggestions better.
If you are respinning to fix the LKP reported issue w/ ignoring the result
of enabling the clocks, could you chop the _clk off of this one?
Otherwise,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
@ 2023-06-02 18:02 ` Conor Dooley
0 siblings, 0 replies; 24+ messages in thread
From: Conor Dooley @ 2023-06-02 18:02 UTC (permalink / raw)
To: William Qiu
Cc: devicetree, linux-spi, linux-kernel, linux-riscv, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu
[-- Attachment #1.1: Type: text/plain, Size: 1332 bytes --]
On Fri, Jun 02, 2023 at 04:49:23PM +0800, William Qiu wrote:
> The QSPI controller needs three clock items to work properly on StarFive
> JH7110 SoC, so there is need to change the maxItems's value to 3. Other
> platforms do not have this constraint.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> index b310069762dd..b6a27171d965 100644
> --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> @@ -26,6 +26,15 @@ allOf:
> const: starfive,jh7110-qspi
> then:
> properties:
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + items:
> + - const: ref_clk
Aww, I liked Mark's suggestions better.
If you are respinning to fix the LKP reported issue w/ ignoring the result
of enabling the clocks, could you chop the _clk off of this one?
Otherwise,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
2023-06-02 18:02 ` Conor Dooley
@ 2023-06-06 3:34 ` William Qiu
-1 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-06 3:34 UTC (permalink / raw)
To: Conor Dooley
Cc: devicetree, linux-spi, linux-kernel, linux-riscv, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu
On 2023/6/3 2:02, Conor Dooley wrote:
> On Fri, Jun 02, 2023 at 04:49:23PM +0800, William Qiu wrote:
>> The QSPI controller needs three clock items to work properly on StarFive
>> JH7110 SoC, so there is need to change the maxItems's value to 3. Other
>> platforms do not have this constraint.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 15 ++++++++++++---
>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>> index b310069762dd..b6a27171d965 100644
>> --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>> @@ -26,6 +26,15 @@ allOf:
>> const: starfive,jh7110-qspi
>> then:
>> properties:
>> + clocks:
>> + maxItems: 3
>> +
>> + clock-names:
>> + items:
>> + - const: ref_clk
>
> Aww, I liked Mark's suggestions better.
> If you are respinning to fix the LKP reported issue w/ ignoring the result
> of enabling the clocks, could you chop the _clk off of this one?
>
> Otherwise,
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks,
> Conor.
Hi Conor,
Thanks for taking time to review this patch series.
About the clock name, I would take Mark's suggestions, and will update it in
next version.
Best regards,
William
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
@ 2023-06-06 3:34 ` William Qiu
0 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-06 3:34 UTC (permalink / raw)
To: Conor Dooley
Cc: devicetree, linux-spi, linux-kernel, linux-riscv, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu
On 2023/6/3 2:02, Conor Dooley wrote:
> On Fri, Jun 02, 2023 at 04:49:23PM +0800, William Qiu wrote:
>> The QSPI controller needs three clock items to work properly on StarFive
>> JH7110 SoC, so there is need to change the maxItems's value to 3. Other
>> platforms do not have this constraint.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 15 ++++++++++++---
>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>> index b310069762dd..b6a27171d965 100644
>> --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>> @@ -26,6 +26,15 @@ allOf:
>> const: starfive,jh7110-qspi
>> then:
>> properties:
>> + clocks:
>> + maxItems: 3
>> +
>> + clock-names:
>> + items:
>> + - const: ref_clk
>
> Aww, I liked Mark's suggestions better.
> If you are respinning to fix the LKP reported issue w/ ignoring the result
> of enabling the clocks, could you chop the _clk off of this one?
>
> Otherwise,
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks,
> Conor.
Hi Conor,
Thanks for taking time to review this patch series.
About the clock name, I would take Mark's suggestions, and will update it in
next version.
Best regards,
William
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
2023-06-02 8:49 ` William Qiu
@ 2023-06-06 12:43 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 24+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-06 12:43 UTC (permalink / raw)
To: William Qiu, devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu
On 02/06/2023 10:49, William Qiu wrote:
> The QSPI controller needs three clock items to work properly on StarFive
> JH7110 SoC, so there is need to change the maxItems's value to 3. Other
> platforms do not have this constraint.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>
> @@ -69,9 +81,6 @@ properties:
> interrupts:
> maxItems: 1
>
> - clocks:
> - maxItems: 1
Properties should be defined in top-level properties. Don't remove them
from here.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
@ 2023-06-06 12:43 ` Krzysztof Kozlowski
0 siblings, 0 replies; 24+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-06 12:43 UTC (permalink / raw)
To: William Qiu, devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu
On 02/06/2023 10:49, William Qiu wrote:
> The QSPI controller needs three clock items to work properly on StarFive
> JH7110 SoC, so there is need to change the maxItems's value to 3. Other
> platforms do not have this constraint.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>
> @@ -69,9 +81,6 @@ properties:
> interrupts:
> maxItems: 1
>
> - clocks:
> - maxItems: 1
Properties should be defined in top-level properties. Don't remove them
from here.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
2023-06-06 12:43 ` Krzysztof Kozlowski
@ 2023-06-19 7:27 ` William Qiu
-1 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-19 7:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu
On 2023/6/6 20:43, Krzysztof Kozlowski wrote:
> On 02/06/2023 10:49, William Qiu wrote:
>> The QSPI controller needs three clock items to work properly on StarFive
>> JH7110 SoC, so there is need to change the maxItems's value to 3. Other
>> platforms do not have this constraint.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>
>
>
>>
>> @@ -69,9 +81,6 @@ properties:
>> interrupts:
>> maxItems: 1
>>
>> - clocks:
>> - maxItems: 1
>
> Properties should be defined in top-level properties. Don't remove them
> from here.
>
> Best regards,
> Krzysztof
>
Hi Krzysztof,
Sorry for the late reply. I'll fix it in next version.
Best regards,
William
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
@ 2023-06-19 7:27 ` William Qiu
0 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-19 7:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu
On 2023/6/6 20:43, Krzysztof Kozlowski wrote:
> On 02/06/2023 10:49, William Qiu wrote:
>> The QSPI controller needs three clock items to work properly on StarFive
>> JH7110 SoC, so there is need to change the maxItems's value to 3. Other
>> platforms do not have this constraint.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>
>
>
>>
>> @@ -69,9 +81,6 @@ properties:
>> interrupts:
>> maxItems: 1
>>
>> - clocks:
>> - maxItems: 1
>
> Properties should be defined in top-level properties. Don't remove them
> from here.
>
> Best regards,
> Krzysztof
>
Hi Krzysztof,
Sorry for the late reply. I'll fix it in next version.
Best regards,
William
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
2023-06-02 8:49 ` William Qiu
@ 2023-06-02 8:49 ` William Qiu
-1 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-02 8:49 UTC (permalink / raw)
To: devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu, William Qiu
Add QSPI clock operation in device probe.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 6ddb2dfc0f00..21788472c7fb 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -63,6 +63,8 @@ struct cqspi_st {
struct platform_device *pdev;
struct spi_master *master;
struct clk *clk;
+ struct clk_bulk_data *clks;
+ unsigned int num_clks;
unsigned int sclk;
void __iomem *iobase;
@@ -1715,6 +1717,16 @@ static int cqspi_probe(struct platform_device *pdev)
}
if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
+ cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks);
+ if (cqspi->num_clks < 0) {
+ dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks);
+ return -EINVAL;
+ }
+
+ ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
+ if (ret)
+ dev_err(dev, "Cannot enable clock clks\n");
+
rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
if (IS_ERR(rstc_ref)) {
ret = PTR_ERR(rstc_ref);
@@ -1816,6 +1828,9 @@ static void cqspi_remove(struct platform_device *pdev)
clk_disable_unprepare(cqspi->clk);
+ if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi"))
+ clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks);
+
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
@@ -1831,6 +1846,9 @@ static int cqspi_suspend(struct device *dev)
clk_disable_unprepare(cqspi->clk);
+ if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
+ clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks);
+
return ret;
}
@@ -1840,6 +1858,8 @@ static int cqspi_resume(struct device *dev)
struct spi_master *master = dev_get_drvdata(dev);
clk_prepare_enable(cqspi->clk);
+ if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
+ clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
cqspi_wait_idle(cqspi);
cqspi_controller_init(cqspi);
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
@ 2023-06-02 8:49 ` William Qiu
0 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-02 8:49 UTC (permalink / raw)
To: devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu, William Qiu
Add QSPI clock operation in device probe.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 6ddb2dfc0f00..21788472c7fb 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -63,6 +63,8 @@ struct cqspi_st {
struct platform_device *pdev;
struct spi_master *master;
struct clk *clk;
+ struct clk_bulk_data *clks;
+ unsigned int num_clks;
unsigned int sclk;
void __iomem *iobase;
@@ -1715,6 +1717,16 @@ static int cqspi_probe(struct platform_device *pdev)
}
if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
+ cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks);
+ if (cqspi->num_clks < 0) {
+ dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks);
+ return -EINVAL;
+ }
+
+ ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
+ if (ret)
+ dev_err(dev, "Cannot enable clock clks\n");
+
rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
if (IS_ERR(rstc_ref)) {
ret = PTR_ERR(rstc_ref);
@@ -1816,6 +1828,9 @@ static void cqspi_remove(struct platform_device *pdev)
clk_disable_unprepare(cqspi->clk);
+ if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi"))
+ clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks);
+
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
@@ -1831,6 +1846,9 @@ static int cqspi_suspend(struct device *dev)
clk_disable_unprepare(cqspi->clk);
+ if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
+ clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks);
+
return ret;
}
@@ -1840,6 +1858,8 @@ static int cqspi_resume(struct device *dev)
struct spi_master *master = dev_get_drvdata(dev);
clk_prepare_enable(cqspi->clk);
+ if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
+ clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
cqspi_wait_idle(cqspi);
cqspi_controller_init(cqspi);
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
2023-06-02 8:49 ` William Qiu
@ 2023-06-02 12:33 ` kernel test robot
-1 siblings, 0 replies; 24+ messages in thread
From: kernel test robot @ 2023-06-02 12:33 UTC (permalink / raw)
To: William Qiu, devicetree, linux-spi, linux-kernel, linux-riscv
Cc: oe-kbuild-all, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Emil Renner Berthing, Ziv Xu, William Qiu
Hi William,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on linus/master v6.4-rc4 next-20230602]
[cannot apply to robh/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20230602084925.215411-3-william.qiu%40starfivetech.com
patch subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
config: powerpc-allyesconfig (https://download.01.org/0day-ci/archive/20230602/202306022017.UbwjjWRN-lkp@intel.com/config)
compiler: powerpc-linux-gcc (GCC) 12.3.0
reproduce (this is a W=1 build):
mkdir -p ~/bin
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/6bbd49e32d407d210b6ea322696cef2e49bf3fa1
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
git checkout 6bbd49e32d407d210b6ea322696cef2e49bf3fa1
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/spi/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306022017.UbwjjWRN-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_resume':
>> drivers/spi/spi-cadence-quadspi.c:1873:17: warning: ignoring return value of 'clk_bulk_prepare_enable' declared with attribute 'warn_unused_result' [-Wunused-result]
1873 | clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +1873 drivers/spi/spi-cadence-quadspi.c
1865
1866 static int cqspi_resume(struct device *dev)
1867 {
1868 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1869 struct spi_master *master = dev_get_drvdata(dev);
1870
1871 clk_prepare_enable(cqspi->clk);
1872 if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
> 1873 clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
1874 cqspi_wait_idle(cqspi);
1875 cqspi_controller_init(cqspi);
1876
1877 cqspi->current_cs = -1;
1878 cqspi->sclk = 0;
1879
1880 return spi_master_resume(master);
1881 }
1882
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
@ 2023-06-02 12:33 ` kernel test robot
0 siblings, 0 replies; 24+ messages in thread
From: kernel test robot @ 2023-06-02 12:33 UTC (permalink / raw)
To: William Qiu, devicetree, linux-spi, linux-kernel, linux-riscv
Cc: oe-kbuild-all, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Emil Renner Berthing, Ziv Xu, William Qiu
Hi William,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on linus/master v6.4-rc4 next-20230602]
[cannot apply to robh/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20230602084925.215411-3-william.qiu%40starfivetech.com
patch subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
config: powerpc-allyesconfig (https://download.01.org/0day-ci/archive/20230602/202306022017.UbwjjWRN-lkp@intel.com/config)
compiler: powerpc-linux-gcc (GCC) 12.3.0
reproduce (this is a W=1 build):
mkdir -p ~/bin
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/6bbd49e32d407d210b6ea322696cef2e49bf3fa1
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
git checkout 6bbd49e32d407d210b6ea322696cef2e49bf3fa1
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/spi/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306022017.UbwjjWRN-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_resume':
>> drivers/spi/spi-cadence-quadspi.c:1873:17: warning: ignoring return value of 'clk_bulk_prepare_enable' declared with attribute 'warn_unused_result' [-Wunused-result]
1873 | clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +1873 drivers/spi/spi-cadence-quadspi.c
1865
1866 static int cqspi_resume(struct device *dev)
1867 {
1868 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1869 struct spi_master *master = dev_get_drvdata(dev);
1870
1871 clk_prepare_enable(cqspi->clk);
1872 if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
> 1873 clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
1874 cqspi_wait_idle(cqspi);
1875 cqspi_controller_init(cqspi);
1876
1877 cqspi->current_cs = -1;
1878 cqspi->sclk = 0;
1879
1880 return spi_master_resume(master);
1881 }
1882
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
2023-06-02 12:33 ` kernel test robot
@ 2023-06-06 3:32 ` William Qiu
-1 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-06 3:32 UTC (permalink / raw)
To: kernel test robot, devicetree, linux-spi, linux-kernel, linux-riscv
Cc: oe-kbuild-all, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Emil Renner Berthing, Ziv Xu
On 2023/6/2 20:33, kernel test robot wrote:
> Hi William,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on broonie-spi/for-next]
> [also build test WARNING on linus/master v6.4-rc4 next-20230602]
> [cannot apply to robh/for-next]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
> base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
> patch link: https://lore.kernel.org/r/20230602084925.215411-3-william.qiu%40starfivetech.com
> patch subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
> config: powerpc-allyesconfig (https://download.01.org/0day-ci/archive/20230602/202306022017.UbwjjWRN-lkp@intel.com/config)
> compiler: powerpc-linux-gcc (GCC) 12.3.0
> reproduce (this is a W=1 build):
> mkdir -p ~/bin
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # https://github.com/intel-lab-lkp/linux/commit/6bbd49e32d407d210b6ea322696cef2e49bf3fa1
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
> git checkout 6bbd49e32d407d210b6ea322696cef2e49bf3fa1
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc olddefconfig
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/spi/
>
> If you fix the issue, kindly add following tag where applicable
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202306022017.UbwjjWRN-lkp@intel.com/
>
> All warnings (new ones prefixed by >>):
>
> drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_resume':
>>> drivers/spi/spi-cadence-quadspi.c:1873:17: warning: ignoring return value of 'clk_bulk_prepare_enable' declared with attribute 'warn_unused_result' [-Wunused-result]
> 1873 | clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
> vim +1873 drivers/spi/spi-cadence-quadspi.c
>
> 1865
> 1866 static int cqspi_resume(struct device *dev)
> 1867 {
> 1868 struct cqspi_st *cqspi = dev_get_drvdata(dev);
> 1869 struct spi_master *master = dev_get_drvdata(dev);
> 1870
> 1871 clk_prepare_enable(cqspi->clk);
> 1872 if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
>> 1873 clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
> 1874 cqspi_wait_idle(cqspi);
> 1875 cqspi_controller_init(cqspi);
> 1876
> 1877 cqspi->current_cs = -1;
> 1878 cqspi->sclk = 0;
> 1879
> 1880 return spi_master_resume(master);
> 1881 }
> 1882
>
Thanks about that. I'll fix it in next version.
Best Regards,
William
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
@ 2023-06-06 3:32 ` William Qiu
0 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-06 3:32 UTC (permalink / raw)
To: kernel test robot, devicetree, linux-spi, linux-kernel, linux-riscv
Cc: oe-kbuild-all, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Emil Renner Berthing, Ziv Xu
On 2023/6/2 20:33, kernel test robot wrote:
> Hi William,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on broonie-spi/for-next]
> [also build test WARNING on linus/master v6.4-rc4 next-20230602]
> [cannot apply to robh/for-next]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
> base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
> patch link: https://lore.kernel.org/r/20230602084925.215411-3-william.qiu%40starfivetech.com
> patch subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
> config: powerpc-allyesconfig (https://download.01.org/0day-ci/archive/20230602/202306022017.UbwjjWRN-lkp@intel.com/config)
> compiler: powerpc-linux-gcc (GCC) 12.3.0
> reproduce (this is a W=1 build):
> mkdir -p ~/bin
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # https://github.com/intel-lab-lkp/linux/commit/6bbd49e32d407d210b6ea322696cef2e49bf3fa1
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
> git checkout 6bbd49e32d407d210b6ea322696cef2e49bf3fa1
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc olddefconfig
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/spi/
>
> If you fix the issue, kindly add following tag where applicable
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202306022017.UbwjjWRN-lkp@intel.com/
>
> All warnings (new ones prefixed by >>):
>
> drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_resume':
>>> drivers/spi/spi-cadence-quadspi.c:1873:17: warning: ignoring return value of 'clk_bulk_prepare_enable' declared with attribute 'warn_unused_result' [-Wunused-result]
> 1873 | clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
> vim +1873 drivers/spi/spi-cadence-quadspi.c
>
> 1865
> 1866 static int cqspi_resume(struct device *dev)
> 1867 {
> 1868 struct cqspi_st *cqspi = dev_get_drvdata(dev);
> 1869 struct spi_master *master = dev_get_drvdata(dev);
> 1870
> 1871 clk_prepare_enable(cqspi->clk);
> 1872 if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
>> 1873 clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
> 1874 cqspi_wait_idle(cqspi);
> 1875 cqspi_controller_init(cqspi);
> 1876
> 1877 cqspi->current_cs = -1;
> 1878 cqspi->sclk = 0;
> 1879
> 1880 return spi_master_resume(master);
> 1881 }
> 1882
>
Thanks about that. I'll fix it in next version.
Best Regards,
William
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
2023-06-02 8:49 ` William Qiu
(?)
(?)
@ 2023-06-15 7:57 ` kernel test robot
-1 siblings, 0 replies; 24+ messages in thread
From: kernel test robot @ 2023-06-15 7:57 UTC (permalink / raw)
To: William Qiu; +Cc: oe-kbuild-all
Hi William,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on robh/for-next linus/master v6.4-rc6 next-20230614]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20230602084925.215411-3-william.qiu%40starfivetech.com
patch subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
config: x86_64-randconfig-m001-20230614 (https://download.01.org/0day-ci/archive/20230615/202306151528.WAq9bHnS-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306151528.WAq9bHnS-lkp@intel.com/
smatch warnings:
drivers/spi/spi-cadence-quadspi.c:1730 cqspi_probe() warn: unsigned 'cqspi->num_clks' is never less than zero.
drivers/spi/spi-cadence-quadspi.c:1732 cqspi_probe() warn: missing unwind goto?
vim +1730 drivers/spi/spi-cadence-quadspi.c
1634
1635 static int cqspi_probe(struct platform_device *pdev)
1636 {
1637 const struct cqspi_driver_platdata *ddata;
1638 struct reset_control *rstc, *rstc_ocp, *rstc_ref;
1639 struct device *dev = &pdev->dev;
1640 struct spi_master *master;
1641 struct resource *res_ahb;
1642 struct cqspi_st *cqspi;
1643 int ret;
1644 int irq;
1645
1646 master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi));
1647 if (!master) {
1648 dev_err(&pdev->dev, "spi_alloc_master failed\n");
1649 return -ENOMEM;
1650 }
1651 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1652 master->mem_ops = &cqspi_mem_ops;
1653 master->mem_caps = &cqspi_mem_caps;
1654 master->dev.of_node = pdev->dev.of_node;
1655
1656 cqspi = spi_master_get_devdata(master);
1657
1658 cqspi->pdev = pdev;
1659 cqspi->master = master;
1660 platform_set_drvdata(pdev, cqspi);
1661
1662 /* Obtain configuration from OF. */
1663 ret = cqspi_of_get_pdata(cqspi);
1664 if (ret) {
1665 dev_err(dev, "Cannot get mandatory OF data.\n");
1666 return -ENODEV;
1667 }
1668
1669 /* Obtain QSPI clock. */
1670 cqspi->clk = devm_clk_get(dev, NULL);
1671 if (IS_ERR(cqspi->clk)) {
1672 dev_err(dev, "Cannot claim QSPI clock.\n");
1673 ret = PTR_ERR(cqspi->clk);
1674 return ret;
1675 }
1676
1677 /* Obtain and remap controller address. */
1678 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
1679 if (IS_ERR(cqspi->iobase)) {
1680 dev_err(dev, "Cannot remap controller address.\n");
1681 ret = PTR_ERR(cqspi->iobase);
1682 return ret;
1683 }
1684
1685 /* Obtain and remap AHB address. */
1686 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb);
1687 if (IS_ERR(cqspi->ahb_base)) {
1688 dev_err(dev, "Cannot remap AHB address.\n");
1689 ret = PTR_ERR(cqspi->ahb_base);
1690 return ret;
1691 }
1692 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1693 cqspi->ahb_size = resource_size(res_ahb);
1694
1695 init_completion(&cqspi->transfer_complete);
1696
1697 /* Obtain IRQ line. */
1698 irq = platform_get_irq(pdev, 0);
1699 if (irq < 0)
1700 return -ENXIO;
1701
1702 pm_runtime_enable(dev);
1703 ret = pm_runtime_resume_and_get(dev);
1704 if (ret < 0)
1705 goto probe_pm_failed;
1706
1707 ret = clk_prepare_enable(cqspi->clk);
1708 if (ret) {
1709 dev_err(dev, "Cannot enable QSPI clock.\n");
1710 goto probe_clk_failed;
1711 }
1712
1713 /* Obtain QSPI reset control */
1714 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1715 if (IS_ERR(rstc)) {
1716 ret = PTR_ERR(rstc);
1717 dev_err(dev, "Cannot get QSPI reset.\n");
1718 goto probe_reset_failed;
1719 }
1720
1721 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1722 if (IS_ERR(rstc_ocp)) {
1723 ret = PTR_ERR(rstc_ocp);
1724 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1725 goto probe_reset_failed;
1726 }
1727
1728 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
1729 cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks);
> 1730 if (cqspi->num_clks < 0) {
1731 dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks);
> 1732 return -EINVAL;
1733 }
1734
1735 ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
1736 if (ret)
1737 dev_err(dev, "Cannot enable clock clks\n");
1738
1739 rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
1740 if (IS_ERR(rstc_ref)) {
1741 ret = PTR_ERR(rstc_ref);
1742 dev_err(dev, "Cannot get QSPI REF reset.\n");
1743 goto probe_reset_failed;
1744 }
1745 reset_control_assert(rstc_ref);
1746 reset_control_deassert(rstc_ref);
1747 }
1748
1749 reset_control_assert(rstc);
1750 reset_control_deassert(rstc);
1751
1752 reset_control_assert(rstc_ocp);
1753 reset_control_deassert(rstc_ocp);
1754
1755 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1756 master->max_speed_hz = cqspi->master_ref_clk_hz;
1757
1758 /* write completion is supported by default */
1759 cqspi->wr_completion = true;
1760
1761 ddata = of_device_get_match_data(dev);
1762 if (ddata) {
1763 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1764 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1765 cqspi->master_ref_clk_hz);
1766 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1767 master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1768 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) {
1769 cqspi->use_direct_mode = true;
1770 cqspi->use_direct_mode_wr = true;
1771 }
1772 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
1773 cqspi->use_dma_read = true;
1774 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
1775 cqspi->wr_completion = false;
1776 if (ddata->quirks & CQSPI_SLOW_SRAM)
1777 cqspi->slow_sram = true;
1778 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR)
1779 cqspi->apb_ahb_hazard = true;
1780
1781 if (of_device_is_compatible(pdev->dev.of_node,
1782 "xlnx,versal-ospi-1.0"))
1783 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1784 }
1785
1786 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1787 pdev->name, cqspi);
1788 if (ret) {
1789 dev_err(dev, "Cannot request IRQ.\n");
1790 goto probe_reset_failed;
1791 }
1792
1793 cqspi_wait_idle(cqspi);
1794 cqspi_controller_init(cqspi);
1795 cqspi->current_cs = -1;
1796 cqspi->sclk = 0;
1797
1798 master->num_chipselect = cqspi->num_chipselect;
1799
1800 ret = cqspi_setup_flash(cqspi);
1801 if (ret) {
1802 dev_err(dev, "failed to setup flash parameters %d\n", ret);
1803 goto probe_setup_failed;
1804 }
1805
1806 if (cqspi->use_direct_mode) {
1807 ret = cqspi_request_mmap_dma(cqspi);
1808 if (ret == -EPROBE_DEFER)
1809 goto probe_setup_failed;
1810 }
1811
1812 ret = spi_register_master(master);
1813 if (ret) {
1814 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1815 goto probe_setup_failed;
1816 }
1817
1818 return 0;
1819 probe_setup_failed:
1820 cqspi_controller_enable(cqspi, 0);
1821 probe_reset_failed:
1822 clk_disable_unprepare(cqspi->clk);
1823 probe_clk_failed:
1824 pm_runtime_put_sync(dev);
1825 probe_pm_failed:
1826 pm_runtime_disable(dev);
1827 return ret;
1828 }
1829
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
2023-06-02 8:49 ` William Qiu
@ 2023-06-02 8:49 ` William Qiu
-1 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-02 8:49 UTC (permalink / raw)
To: devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu, William Qiu
Add the quad spi controller node for the StarFive JH7110 SoC.
Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++
2 files changed, 50 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2a6d81609284..22212c1150f9 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -126,6 +126,38 @@ &i2c6 {
status = "okay";
};
+&qspi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nor_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg=<0>;
+ cdns,read-delay = <5>;
+ spi-max-frequency = <12000000>;
+ cdns,tshsl-ns = <1>;
+ cdns,tsd2d-ns = <1>;
+ cdns,tchsh-ns = <1>;
+ cdns,tslch-ns = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spl@0 {
+ reg = <0x0 0x20000>;
+ };
+ uboot@100000 {
+ reg = <0x100000 0x300000>;
+ };
+ data@f00000 {
+ reg = <0xf00000 0x100000>;
+ };
+ };
+ };
+};
+
&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..e1a51e57a851 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -440,6 +440,24 @@ i2c6: i2c@12060000 {
status = "disabled";
};
+ qspi: spi@13010000 {
+ compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+ reg = <0x0 0x13010000 0x0 0x10000
+ 0x0 0x21000000 0x0 0x400000>;
+ interrupts = <25>;
+ clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
+ <&syscrg JH7110_SYSCLK_QSPI_AHB>,
+ <&syscrg JH7110_SYSCLK_QSPI_APB>;
+ clock-names = "ref_clk", "hclk", "pclk";
+ resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+ <&syscrg JH7110_SYSRST_QSPI_AHB>,
+ <&syscrg JH7110_SYSRST_QSPI_REF>;
+ reset-names = "qspi", "qspi-ocp", "rstc_ref";
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ };
+
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
@ 2023-06-02 8:49 ` William Qiu
0 siblings, 0 replies; 24+ messages in thread
From: William Qiu @ 2023-06-02 8:49 UTC (permalink / raw)
To: devicetree, linux-spi, linux-kernel, linux-riscv
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu, William Qiu
Add the quad spi controller node for the StarFive JH7110 SoC.
Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++
2 files changed, 50 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2a6d81609284..22212c1150f9 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -126,6 +126,38 @@ &i2c6 {
status = "okay";
};
+&qspi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nor_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg=<0>;
+ cdns,read-delay = <5>;
+ spi-max-frequency = <12000000>;
+ cdns,tshsl-ns = <1>;
+ cdns,tsd2d-ns = <1>;
+ cdns,tchsh-ns = <1>;
+ cdns,tslch-ns = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spl@0 {
+ reg = <0x0 0x20000>;
+ };
+ uboot@100000 {
+ reg = <0x100000 0x300000>;
+ };
+ data@f00000 {
+ reg = <0xf00000 0x100000>;
+ };
+ };
+ };
+};
+
&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..e1a51e57a851 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -440,6 +440,24 @@ i2c6: i2c@12060000 {
status = "disabled";
};
+ qspi: spi@13010000 {
+ compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+ reg = <0x0 0x13010000 0x0 0x10000
+ 0x0 0x21000000 0x0 0x400000>;
+ interrupts = <25>;
+ clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
+ <&syscrg JH7110_SYSCLK_QSPI_AHB>,
+ <&syscrg JH7110_SYSCLK_QSPI_APB>;
+ clock-names = "ref_clk", "hclk", "pclk";
+ resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+ <&syscrg JH7110_SYSRST_QSPI_AHB>,
+ <&syscrg JH7110_SYSRST_QSPI_REF>;
+ reset-names = "qspi", "qspi-ocp", "rstc_ref";
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ };
+
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: (subset) [PATCH v2 0/3] Add initialization of clock for StarFive JH7110 SoC
2023-06-02 8:49 ` William Qiu
@ 2023-08-04 19:04 ` Mark Brown
-1 siblings, 0 replies; 24+ messages in thread
From: Mark Brown @ 2023-08-04 19:04 UTC (permalink / raw)
To: devicetree, linux-spi, linux-kernel, linux-riscv, William Qiu
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu
On Fri, 02 Jun 2023 16:49:22 +0800, William Qiu wrote:
> This patchset adds initial rudimentary support for the StarFive
> Quad SPI controller driver. And this driver will be used in
> StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB
> clocks changed from the default ON state to the default OFF state,
> so these clocks need to be enabled in the driver.At the same time,
> dts patch is added to this series.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
commit: 0d2b6a1b8515204924b9174ae0135e1f4ff29b21
[2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
commit: 33f1ef6d4eb6bca726608ed939c9fd94d96ceefd
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: (subset) [PATCH v2 0/3] Add initialization of clock for StarFive JH7110 SoC
@ 2023-08-04 19:04 ` Mark Brown
0 siblings, 0 replies; 24+ messages in thread
From: Mark Brown @ 2023-08-04 19:04 UTC (permalink / raw)
To: devicetree, linux-spi, linux-kernel, linux-riscv, William Qiu
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Ziv Xu
On Fri, 02 Jun 2023 16:49:22 +0800, William Qiu wrote:
> This patchset adds initial rudimentary support for the StarFive
> Quad SPI controller driver. And this driver will be used in
> StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB
> clocks changed from the default ON state to the default OFF state,
> so these clocks need to be enabled in the driver.At the same time,
> dts patch is added to this series.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
commit: 0d2b6a1b8515204924b9174ae0135e1f4ff29b21
[2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
commit: 33f1ef6d4eb6bca726608ed939c9fd94d96ceefd
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
@ 2023-06-03 22:58 kernel test robot
0 siblings, 0 replies; 24+ messages in thread
From: kernel test robot @ 2023-06-03 22:58 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp, Julia Lawall
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20230602084925.215411-3-william.qiu@starfivetech.com>
References: <20230602084925.215411-3-william.qiu@starfivetech.com>
TO: William Qiu <william.qiu@starfivetech.com>
Hi William,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on linus/master v6.4-rc4 next-20230602]
[cannot apply to robh/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20230602084925.215411-3-william.qiu%40starfivetech.com
patch subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
:::::: branch date: 2 days ago
:::::: commit date: 2 days ago
config: x86_64-randconfig-c002-20230604 (https://download.01.org/0day-ci/archive/20230604/202306040644.6ZHs55x4-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Julia Lawall <julia.lawall@inria.fr>
| Closes: https://lore.kernel.org/r/202306040644.6ZHs55x4-lkp@intel.com/
cocci warnings: (new ones prefixed by >>)
>> drivers/spi/spi-cadence-quadspi.c:1730:6-21: WARNING: Unsigned expression compared with zero: cqspi -> num_clks < 0
vim +1730 drivers/spi/spi-cadence-quadspi.c
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1634
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1635 static int cqspi_probe(struct platform_device *pdev)
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1636 {
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1637 const struct cqspi_driver_platdata *ddata;
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1638 struct reset_control *rstc, *rstc_ocp, *rstc_ref;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1639 struct device *dev = &pdev->dev;
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1640 struct spi_master *master;
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1641 struct resource *res_ahb;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1642 struct cqspi_st *cqspi;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1643 int ret;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1644 int irq;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1645
606e5d40818498 drivers/spi/spi-cadence-quadspi.c Vaishnav Achath 2022-05-11 1646 master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi));
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1647 if (!master) {
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1648 dev_err(&pdev->dev, "spi_alloc_master failed\n");
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1649 return -ENOMEM;
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1650 }
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1651 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1652 master->mem_ops = &cqspi_mem_ops;
a9be454927de3b drivers/spi/spi-cadence-quadspi.c Miquel Raynal 2022-01-27 1653 master->mem_caps = &cqspi_mem_caps;
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1654 master->dev.of_node = pdev->dev.of_node;
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1655
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1656 cqspi = spi_master_get_devdata(master);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1657
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1658 cqspi->pdev = pdev;
606e5d40818498 drivers/spi/spi-cadence-quadspi.c Vaishnav Achath 2022-05-11 1659 cqspi->master = master;
ea94191e584b14 drivers/spi/spi-cadence-quadspi.c Meng Li 2021-03-11 1660 platform_set_drvdata(pdev, cqspi);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1661
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1662 /* Obtain configuration from OF. */
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1663 ret = cqspi_of_get_pdata(cqspi);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1664 if (ret) {
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1665 dev_err(dev, "Cannot get mandatory OF data.\n");
73d5fe04627028 drivers/spi/spi-cadence-quadspi.c Vaishnav Achath 2022-06-01 1666 return -ENODEV;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1667 }
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1668
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1669 /* Obtain QSPI clock. */
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1670 cqspi->clk = devm_clk_get(dev, NULL);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1671 if (IS_ERR(cqspi->clk)) {
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1672 dev_err(dev, "Cannot claim QSPI clock.\n");
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1673 ret = PTR_ERR(cqspi->clk);
73d5fe04627028 drivers/spi/spi-cadence-quadspi.c Vaishnav Achath 2022-06-01 1674 return ret;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1675 }
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1676
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1677 /* Obtain and remap controller address. */
4e12ef2b2e3f65 drivers/spi/spi-cadence-quadspi.c Yang Yingliang 2022-09-28 1678 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1679 if (IS_ERR(cqspi->iobase)) {
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1680 dev_err(dev, "Cannot remap controller address.\n");
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1681 ret = PTR_ERR(cqspi->iobase);
73d5fe04627028 drivers/spi/spi-cadence-quadspi.c Vaishnav Achath 2022-06-01 1682 return ret;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1683 }
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1684
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1685 /* Obtain and remap AHB address. */
4e12ef2b2e3f65 drivers/spi/spi-cadence-quadspi.c Yang Yingliang 2022-09-28 1686 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1687 if (IS_ERR(cqspi->ahb_base)) {
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1688 dev_err(dev, "Cannot remap AHB address.\n");
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1689 ret = PTR_ERR(cqspi->ahb_base);
73d5fe04627028 drivers/spi/spi-cadence-quadspi.c Vaishnav Achath 2022-06-01 1690 return ret;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1691 }
ffa639e069fb55 drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2018-04-10 1692 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
a27f2eaf2b2757 drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2017-12-29 1693 cqspi->ahb_size = resource_size(res_ahb);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1694
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1695 init_completion(&cqspi->transfer_complete);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1696
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1697 /* Obtain IRQ line. */
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1698 irq = platform_get_irq(pdev, 0);
73d5fe04627028 drivers/spi/spi-cadence-quadspi.c Vaishnav Achath 2022-06-01 1699 if (irq < 0)
73d5fe04627028 drivers/spi/spi-cadence-quadspi.c Vaishnav Achath 2022-06-01 1700 return -ENXIO;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1701
4892b374c9b797 drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2017-10-03 1702 pm_runtime_enable(dev);
b7be05d5e4a304 drivers/spi/spi-cadence-quadspi.c Minghao Chi 2022-04-14 1703 ret = pm_runtime_resume_and_get(dev);
b7be05d5e4a304 drivers/spi/spi-cadence-quadspi.c Minghao Chi 2022-04-14 1704 if (ret < 0)
4d0ef0a1c35189 drivers/spi/spi-cadence-quadspi.c Zhang Qilong 2022-09-24 1705 goto probe_pm_failed;
4892b374c9b797 drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2017-10-03 1706
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1707 ret = clk_prepare_enable(cqspi->clk);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1708 if (ret) {
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1709 dev_err(dev, "Cannot enable QSPI clock.\n");
4892b374c9b797 drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2017-10-03 1710 goto probe_clk_failed;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1711 }
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1712
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1713 /* Obtain QSPI reset control */
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1714 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1715 if (IS_ERR(rstc)) {
ac9978fcad3c5a drivers/spi/spi-cadence-quadspi.c Zhihao Cheng 2020-11-16 1716 ret = PTR_ERR(rstc);
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1717 dev_err(dev, "Cannot get QSPI reset.\n");
c61088d1f99329 drivers/mtd/spi-nor/controllers/cadence-quadspi.c Vignesh Raghavendra 2020-06-01 1718 goto probe_reset_failed;
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1719 }
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1720
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1721 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1722 if (IS_ERR(rstc_ocp)) {
ac9978fcad3c5a drivers/spi/spi-cadence-quadspi.c Zhihao Cheng 2020-11-16 1723 ret = PTR_ERR(rstc_ocp);
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1724 dev_err(dev, "Cannot get QSPI OCP reset.\n");
c61088d1f99329 drivers/mtd/spi-nor/controllers/cadence-quadspi.c Vignesh Raghavendra 2020-06-01 1725 goto probe_reset_failed;
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1726 }
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1727
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1728 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
6bbd49e32d407d drivers/spi/spi-cadence-quadspi.c William Qiu 2023-06-02 1729 cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks);
6bbd49e32d407d drivers/spi/spi-cadence-quadspi.c William Qiu 2023-06-02 @1730 if (cqspi->num_clks < 0) {
6bbd49e32d407d drivers/spi/spi-cadence-quadspi.c William Qiu 2023-06-02 1731 dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks);
6bbd49e32d407d drivers/spi/spi-cadence-quadspi.c William Qiu 2023-06-02 1732 return -EINVAL;
6bbd49e32d407d drivers/spi/spi-cadence-quadspi.c William Qiu 2023-06-02 1733 }
6bbd49e32d407d drivers/spi/spi-cadence-quadspi.c William Qiu 2023-06-02 1734
6bbd49e32d407d drivers/spi/spi-cadence-quadspi.c William Qiu 2023-06-02 1735 ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
6bbd49e32d407d drivers/spi/spi-cadence-quadspi.c William Qiu 2023-06-02 1736 if (ret)
6bbd49e32d407d drivers/spi/spi-cadence-quadspi.c William Qiu 2023-06-02 1737 dev_err(dev, "Cannot enable clock clks\n");
6bbd49e32d407d drivers/spi/spi-cadence-quadspi.c William Qiu 2023-06-02 1738
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1739 rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1740 if (IS_ERR(rstc_ref)) {
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1741 ret = PTR_ERR(rstc_ref);
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1742 dev_err(dev, "Cannot get QSPI REF reset.\n");
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1743 goto probe_reset_failed;
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1744 }
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1745 reset_control_assert(rstc_ref);
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1746 reset_control_deassert(rstc_ref);
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1747 }
47fef94afeae2a drivers/spi/spi-cadence-quadspi.c William Qiu 2023-03-02 1748
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1749 reset_control_assert(rstc);
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1750 reset_control_deassert(rstc);
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1751
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1752 reset_control_assert(rstc_ocp);
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1753 reset_control_deassert(rstc_ocp);
8d1336c241bdad drivers/mtd/spi-nor/cadence-quadspi.c Dinh Nguyen 2019-06-13 1754
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1755 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
3a5c09c8d1ed9a drivers/spi/spi-cadence-quadspi.c Pratyush Yadav 2020-12-23 1756 master->max_speed_hz = cqspi->master_ref_clk_hz;
98d948eb833104 drivers/spi/spi-cadence-quadspi.c Dinh Nguyen 2021-11-08 1757
98d948eb833104 drivers/spi/spi-cadence-quadspi.c Dinh Nguyen 2021-11-08 1758 /* write completion is supported by default */
98d948eb833104 drivers/spi/spi-cadence-quadspi.c Dinh Nguyen 2021-11-08 1759 cqspi->wr_completion = true;
98d948eb833104 drivers/spi/spi-cadence-quadspi.c Dinh Nguyen 2021-11-08 1760
2cc788387497d1 drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2019-02-12 1761 ddata = of_device_get_match_data(dev);
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1762 if (ddata) {
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1763 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
f453f293979fb6 drivers/spi/spi-cadence-quadspi.c Pratyush Yadav 2020-12-23 1764 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
61dc8493bae9ba drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2017-10-03 1765 cqspi->master_ref_clk_hz);
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1766 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
f453f293979fb6 drivers/spi/spi-cadence-quadspi.c Pratyush Yadav 2020-12-23 1767 master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
e8c51b164355c1 drivers/spi/spi-cadence-quadspi.c Dhruva Gole 2023-01-25 1768 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) {
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1769 cqspi->use_direct_mode = true;
e8c51b164355c1 drivers/spi/spi-cadence-quadspi.c Dhruva Gole 2023-01-25 1770 cqspi->use_direct_mode_wr = true;
e8c51b164355c1 drivers/spi/spi-cadence-quadspi.c Dhruva Gole 2023-01-25 1771 }
1a6f854f7daab1 drivers/spi/spi-cadence-quadspi.c Sai Krishna Potthuri 2021-09-24 1772 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
1a6f854f7daab1 drivers/spi/spi-cadence-quadspi.c Sai Krishna Potthuri 2021-09-24 1773 cqspi->use_dma_read = true;
98d948eb833104 drivers/spi/spi-cadence-quadspi.c Dinh Nguyen 2021-11-08 1774 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
98d948eb833104 drivers/spi/spi-cadence-quadspi.c Dinh Nguyen 2021-11-08 1775 cqspi->wr_completion = false;
9ee5b6d53b8c99 drivers/spi/spi-cadence-quadspi.c Niravkumar L Rabara 2022-08-13 1776 if (ddata->quirks & CQSPI_SLOW_SRAM)
9ee5b6d53b8c99 drivers/spi/spi-cadence-quadspi.c Niravkumar L Rabara 2022-08-13 1777 cqspi->slow_sram = true;
f5c2f9f9584353 drivers/spi/spi-cadence-quadspi.c Brad Larson 2023-05-15 1778 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR)
f5c2f9f9584353 drivers/spi/spi-cadence-quadspi.c Brad Larson 2023-05-15 1779 cqspi->apb_ahb_hazard = true;
1a6f854f7daab1 drivers/spi/spi-cadence-quadspi.c Sai Krishna Potthuri 2021-09-24 1780
09e393e3f13970 drivers/spi/spi-cadence-quadspi.c Sai Krishna Potthuri 2021-09-24 1781 if (of_device_is_compatible(pdev->dev.of_node,
1a6f854f7daab1 drivers/spi/spi-cadence-quadspi.c Sai Krishna Potthuri 2021-09-24 1782 "xlnx,versal-ospi-1.0"))
1a6f854f7daab1 drivers/spi/spi-cadence-quadspi.c Sai Krishna Potthuri 2021-09-24 1783 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1784 }
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1785
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1786 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1787 pdev->name, cqspi);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1788 if (ret) {
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1789 dev_err(dev, "Cannot request IRQ.\n");
c61088d1f99329 drivers/mtd/spi-nor/controllers/cadence-quadspi.c Vignesh Raghavendra 2020-06-01 1790 goto probe_reset_failed;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1791 }
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1792
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1793 cqspi_wait_idle(cqspi);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1794 cqspi_controller_init(cqspi);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1795 cqspi->current_cs = -1;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1796 cqspi->sclk = 0;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1797
b436fb7d29bfa4 drivers/spi/spi-cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-11-24 1798 master->num_chipselect = cqspi->num_chipselect;
b436fb7d29bfa4 drivers/spi/spi-cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-11-24 1799
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1800 ret = cqspi_setup_flash(cqspi);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1801 if (ret) {
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1802 dev_err(dev, "failed to setup flash parameters %d\n", ret);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1803 goto probe_setup_failed;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1804 }
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1805
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1806 if (cqspi->use_direct_mode) {
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1807 ret = cqspi_request_mmap_dma(cqspi);
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1808 if (ret == -EPROBE_DEFER)
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1809 goto probe_setup_failed;
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1810 }
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1811
606e5d40818498 drivers/spi/spi-cadence-quadspi.c Vaishnav Achath 2022-05-11 1812 ret = spi_register_master(master);
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1813 if (ret) {
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1814 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1815 goto probe_setup_failed;
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1816 }
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1817
a314f6367787ee drivers/mtd/spi-nor/controllers/cadence-quadspi.c Ramuthevar Vadivel Murugan 2020-06-01 1818 return 0;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1819 probe_setup_failed:
329864d35a7f49 drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2017-10-03 1820 cqspi_controller_enable(cqspi, 0);
c61088d1f99329 drivers/mtd/spi-nor/controllers/cadence-quadspi.c Vignesh Raghavendra 2020-06-01 1821 probe_reset_failed:
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1822 clk_disable_unprepare(cqspi->clk);
4892b374c9b797 drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2017-10-03 1823 probe_clk_failed:
4892b374c9b797 drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2017-10-03 1824 pm_runtime_put_sync(dev);
4d0ef0a1c35189 drivers/spi/spi-cadence-quadspi.c Zhang Qilong 2022-09-24 1825 probe_pm_failed:
4892b374c9b797 drivers/mtd/spi-nor/cadence-quadspi.c Vignesh R 2017-10-03 1826 pm_runtime_disable(dev);
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1827 return ret;
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1828 }
14062341053690 drivers/mtd/spi-nor/cadence-quadspi.c Graham Moore 2016-06-04 1829
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2023-08-04 19:04 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-02 8:49 [PATCH v2 0/3] Add initialization of clock for StarFive JH7110 SoC William Qiu
2023-06-02 8:49 ` William Qiu
2023-06-02 8:49 ` [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks " William Qiu
2023-06-02 8:49 ` William Qiu
2023-06-02 18:02 ` Conor Dooley
2023-06-02 18:02 ` Conor Dooley
2023-06-06 3:34 ` William Qiu
2023-06-06 3:34 ` William Qiu
2023-06-06 12:43 ` Krzysztof Kozlowski
2023-06-06 12:43 ` Krzysztof Kozlowski
2023-06-19 7:27 ` William Qiu
2023-06-19 7:27 ` William Qiu
2023-06-02 8:49 ` [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI William Qiu
2023-06-02 8:49 ` William Qiu
2023-06-02 12:33 ` kernel test robot
2023-06-02 12:33 ` kernel test robot
2023-06-06 3:32 ` William Qiu
2023-06-06 3:32 ` William Qiu
2023-06-15 7:57 ` kernel test robot
2023-06-02 8:49 ` [PATCH v2 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC William Qiu
2023-06-02 8:49 ` William Qiu
2023-08-04 19:04 ` (subset) [PATCH v2 0/3] Add initialization of clock " Mark Brown
2023-08-04 19:04 ` Mark Brown
2023-06-03 22:58 [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI kernel test robot
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