[PATCH 00/12] arm64: dts: ti: Fix up references to phandles

[PATCH 00/12] arm64: dts: ti: Fix up references to phandles

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

This set was caught by using: git grep '\s&' arch/arm64/boot/dts/ti/
and manually going through the list.

Nishanth Menon (12):
  arm64: dts: ti: k3-j721e-sk: Fixup reference to phandles array
  arm64: dts: ti: k3-j721e-som-p0/common-proc-board: Fixup reference to
    phandles array
  arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles
    array
  arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fixup reference to
    phandles array
  arm64: dts: ti: k3-j7200-som/common-proc-board: Fixup reference to
    phandles array
  arm64: dts: ti: k3-j721s2-common-proc-board: Fixup reference to
    phandles array
  arm64: dts: ti: k3-am625-sk: Fixup reference to phandles array
  arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array
  arm64: dts: ti: k3-am64-sk: Fixup reference to phandles array
  arm64: dts: ti: k3-am65-iot*: Fixup reference to phandles array
  arm64: dts: ti: k3-am654-base-board: Fixup reference to phandles array
  arm64: dts: ti: k3-am68-sk-base-board: Fixup reference to phandles
    array

 arch/arm64/boot/dts/ti/k3-am625-sk.dts        |  4 +--
 arch/arm64/boot/dts/ti/k3-am642-evm.dts       | 12 ++++----
 .../dts/ti/k3-am642-phyboard-electra-rdk.dts  |  2 +-
 arch/arm64/boot/dts/ti/k3-am642-sk.dts        | 12 ++++----
 .../boot/dts/ti/k3-am65-iot2050-common.dtsi   | 17 +++++------
 .../arm64/boot/dts/ti/k3-am654-base-board.dts |  4 +--
 .../dts/ti/k3-am6548-iot2050-advanced-m2.dts  | 18 +++++-------
 .../boot/dts/ti/k3-am68-sk-base-board.dts     |  2 +-
 .../dts/ti/k3-j7200-common-proc-board.dts     |  2 +-
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi   |  8 ++---
 .../boot/dts/ti/k3-j721e-beagleboneai64.dts   | 29 ++++++++++---------
 .../dts/ti/k3-j721e-common-proc-board.dts     |  4 +--
 arch/arm64/boot/dts/ti/k3-j721e-sk.dts        | 20 ++++++-------
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   | 18 ++++++------
 .../dts/ti/k3-j721s2-common-proc-board.dts    |  2 +-
 15 files changed, 76 insertions(+), 78 deletions(-)

-- 
2.40.0

[PATCH 00/12] arm64: dts: ti: Fix up references to phandles

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

This set was caught by using: git grep '\s&' arch/arm64/boot/dts/ti/
and manually going through the list.

Nishanth Menon (12):
  arm64: dts: ti: k3-j721e-sk: Fixup reference to phandles array
  arm64: dts: ti: k3-j721e-som-p0/common-proc-board: Fixup reference to
    phandles array
  arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles
    array
  arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fixup reference to
    phandles array
  arm64: dts: ti: k3-j7200-som/common-proc-board: Fixup reference to
    phandles array
  arm64: dts: ti: k3-j721s2-common-proc-board: Fixup reference to
    phandles array
  arm64: dts: ti: k3-am625-sk: Fixup reference to phandles array
  arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array
  arm64: dts: ti: k3-am64-sk: Fixup reference to phandles array
  arm64: dts: ti: k3-am65-iot*: Fixup reference to phandles array
  arm64: dts: ti: k3-am654-base-board: Fixup reference to phandles array
  arm64: dts: ti: k3-am68-sk-base-board: Fixup reference to phandles
    array

 arch/arm64/boot/dts/ti/k3-am625-sk.dts        |  4 +--
 arch/arm64/boot/dts/ti/k3-am642-evm.dts       | 12 ++++----
 .../dts/ti/k3-am642-phyboard-electra-rdk.dts  |  2 +-
 arch/arm64/boot/dts/ti/k3-am642-sk.dts        | 12 ++++----
 .../boot/dts/ti/k3-am65-iot2050-common.dtsi   | 17 +++++------
 .../arm64/boot/dts/ti/k3-am654-base-board.dts |  4 +--
 .../dts/ti/k3-am6548-iot2050-advanced-m2.dts  | 18 +++++-------
 .../boot/dts/ti/k3-am68-sk-base-board.dts     |  2 +-
 .../dts/ti/k3-j7200-common-proc-board.dts     |  2 +-
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi   |  8 ++---
 .../boot/dts/ti/k3-j721e-beagleboneai64.dts   | 29 ++++++++++---------
 .../dts/ti/k3-j721e-common-proc-board.dts     |  4 +--
 arch/arm64/boot/dts/ti/k3-j721e-sk.dts        | 20 ++++++-------
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   | 18 ++++++------
 .../dts/ti/k3-j721s2-common-proc-board.dts    |  2 +-
 15 files changed, 76 insertions(+), 78 deletions(-)

-- 
2.40.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 01/12] arm64: dts: ti: k3-j721e-sk: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index aba3bbb3849b..9945c4ab8abb 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -829,7 +829,7 @@ &tscadc1 {
 
 &mcu_cpsw {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
@@ -1056,55 +1056,55 @@ mbox_c71_0: mbox-c71-0 {
 };
 
 &mcu_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
 			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
 			<&main_r5fss1_core1_memory_region>;
 };
 
 &c66_0 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
 	memory-region = <&c66_0_dma_memory_region>,
 			<&c66_0_memory_region>;
 };
 
 &c66_1 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
 	memory-region = <&c66_1_dma_memory_region>,
 			<&c66_1_memory_region>;
 };
 
 &c71_0 {
-	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
 	memory-region = <&c71_0_dma_memory_region>,
 			<&c71_0_memory_region>;
 };
-- 
2.40.0

[PATCH 01/12] arm64: dts: ti: k3-j721e-sk: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index aba3bbb3849b..9945c4ab8abb 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -829,7 +829,7 @@ &tscadc1 {
 
 &mcu_cpsw {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
@@ -1056,55 +1056,55 @@ mbox_c71_0: mbox-c71-0 {
 };
 
 &mcu_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
 			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
 			<&main_r5fss1_core1_memory_region>;
 };
 
 &c66_0 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
 	memory-region = <&c66_0_dma_memory_region>,
 			<&c66_0_memory_region>;
 };
 
 &c66_1 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
 	memory-region = <&c66_1_dma_memory_region>,
 			<&c66_1_memory_region>;
 };
 
 &c71_0 {
-	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
 	memory-region = <&c71_0_dma_memory_region>,
 			<&c71_0_memory_region>;
 };
-- 
2.40.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 02/12] arm64: dts: ti: k3-j721e-som-p0/common-proc-board: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 .../boot/dts/ti/k3-j721e-common-proc-board.dts |  4 ++--
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi    | 18 +++++++++---------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 23f242ab6aa3..25111c86511f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -25,7 +25,7 @@ gpio_keys: gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
 		pinctrl-names = "default";
-		pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
+		pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
 
 		sw10: switch-10 {
 			label = "GPIO Key USER1";
@@ -701,7 +701,7 @@ exp5: gpio@20 {
 
 &mcu_cpsw {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 51a57d34ebea..a0be8d2edac6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -271,55 +271,55 @@ mbox_c71_0: mbox-c71-0 {
 };
 
 &mcu_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
 			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
 			<&main_r5fss1_core1_memory_region>;
 };
 
 &c66_0 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
 	memory-region = <&c66_0_dma_memory_region>,
 			<&c66_0_memory_region>;
 };
 
 &c66_1 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
 	memory-region = <&c66_1_dma_memory_region>,
 			<&c66_1_memory_region>;
 };
 
 &c71_0 {
-	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
 	memory-region = <&c71_0_dma_memory_region>,
 			<&c71_0_memory_region>;
 };
-- 
2.40.0

[PATCH 02/12] arm64: dts: ti: k3-j721e-som-p0/common-proc-board: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 .../boot/dts/ti/k3-j721e-common-proc-board.dts |  4 ++--
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi    | 18 +++++++++---------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 23f242ab6aa3..25111c86511f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -25,7 +25,7 @@ gpio_keys: gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
 		pinctrl-names = "default";
-		pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
+		pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
 
 		sw10: switch-10 {
 			label = "GPIO Key USER1";
@@ -701,7 +701,7 @@ exp5: gpio@20 {
 
 &mcu_cpsw {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 51a57d34ebea..a0be8d2edac6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -271,55 +271,55 @@ mbox_c71_0: mbox-c71-0 {
 };
 
 &mcu_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
 			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
 			<&main_r5fss1_core1_memory_region>;
 };
 
 &c66_0 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
 	memory-region = <&c66_0_dma_memory_region>,
 			<&c66_0_memory_region>;
 };
 
 &c66_1 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
 	memory-region = <&c66_1_dma_memory_region>,
 			<&c66_1_memory_region>;
 };
 
 &c71_0 {
-	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
 	memory-region = <&c71_0_dma_memory_region>,
 			<&c71_0_memory_region>;
 };
-- 
2.40.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 .../boot/dts/ti/k3-j721e-beagleboneai64.dts   | 29 ++++++++++---------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
index 37c24b077b6a..c13246a9ed8f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -593,7 +593,7 @@ &main_i2c0 {
 &main_i2c1 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>;
+	pinctrl-0 = <&main_i2c1_pins_default>, <&csi1_gpio_pins_default>;
 	clock-frequency = <400000>;
 };
 
@@ -623,7 +623,7 @@ &main_i2c4 {
 &main_i2c5 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>;
+	pinctrl-0 = <&main_i2c5_pins_default>, <&csi0_gpio_pins_default>;
 	clock-frequency = <400000>;
 };
 
@@ -639,7 +639,7 @@ &main_i2c6 {
 &wkup_i2c0 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
+	pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
 	clock-frequency = <400000>;
 
 	eeprom@50 {
@@ -680,7 +680,8 @@ &main_gpio7 {
 
 &wkup_gpio0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>;
+	pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>,
+		    <&mikro_bus_pins_default>;
 };
 
 &wkup_gpio1 {
@@ -759,7 +760,7 @@ serdes2_usb_link: phy@1 {
 
 &usbss1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>;
+	pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>;
 	ti,vbus-divider;
 };
 
@@ -1001,55 +1002,55 @@ mbox_c71_0: mbox-c71-0 {
 };
 
 &mcu_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
 			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
 			<&main_r5fss1_core1_memory_region>;
 };
 
 &c66_0 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
 	memory-region = <&c66_0_dma_memory_region>,
 			<&c66_0_memory_region>;
 };
 
 &c66_1 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
 	memory-region = <&c66_1_dma_memory_region>,
 			<&c66_1_memory_region>;
 };
 
 &c71_0 {
-	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
 	memory-region = <&c71_0_dma_memory_region>,
 			<&c71_0_memory_region>;
 };
-- 
2.40.0

[PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 .../boot/dts/ti/k3-j721e-beagleboneai64.dts   | 29 ++++++++++---------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
index 37c24b077b6a..c13246a9ed8f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -593,7 +593,7 @@ &main_i2c0 {
 &main_i2c1 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>;
+	pinctrl-0 = <&main_i2c1_pins_default>, <&csi1_gpio_pins_default>;
 	clock-frequency = <400000>;
 };
 
@@ -623,7 +623,7 @@ &main_i2c4 {
 &main_i2c5 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>;
+	pinctrl-0 = <&main_i2c5_pins_default>, <&csi0_gpio_pins_default>;
 	clock-frequency = <400000>;
 };
 
@@ -639,7 +639,7 @@ &main_i2c6 {
 &wkup_i2c0 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
+	pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
 	clock-frequency = <400000>;
 
 	eeprom@50 {
@@ -680,7 +680,8 @@ &main_gpio7 {
 
 &wkup_gpio0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>;
+	pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>,
+		    <&mikro_bus_pins_default>;
 };
 
 &wkup_gpio1 {
@@ -759,7 +760,7 @@ serdes2_usb_link: phy@1 {
 
 &usbss1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>;
+	pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>;
 	ti,vbus-divider;
 };
 
@@ -1001,55 +1002,55 @@ mbox_c71_0: mbox-c71-0 {
 };
 
 &mcu_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
 			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
 			<&main_r5fss1_core1_memory_region>;
 };
 
 &c66_0 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
 	memory-region = <&c66_0_dma_memory_region>,
 			<&c66_0_memory_region>;
 };
 
 &c66_1 {
-	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
 	memory-region = <&c66_1_dma_memory_region>,
 			<&c66_1_memory_region>;
 };
 
 &c71_0 {
-	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
 	memory-region = <&c71_0_dma_memory_region>,
 			<&c71_0_memory_region>;
 };
-- 
2.40.0


_______________________________________________
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[PATCH 04/12] arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.

Cc: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
index 8d3114d14a8b..2258c27e99e1 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
@@ -75,7 +75,7 @@ key-menu {
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
-		pinctrl-0 = <&leds_pins_default &user_leds_pins_default>;
+		pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
 
 		led-1 {
 			color = <LED_COLOR_ID_RED>;
-- 
2.40.0

[PATCH 04/12] arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.

Cc: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
index 8d3114d14a8b..2258c27e99e1 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
@@ -75,7 +75,7 @@ key-menu {
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
-		pinctrl-0 = <&leds_pins_default &user_leds_pins_default>;
+		pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
 
 		led-1 {
 			color = <LED_COLOR_ID_RED>;
-- 
2.40.0


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 05/12] arm64: dts: ti: k3-j7200-som/common-proc-board: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 2 +-
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi           | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 0cc0e1dc40c5..5ddb40bcda9e 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -192,7 +192,7 @@ &wkup_gpio1 {
 
 &mcu_cpsw {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index fa44ed4c17d5..f33212552bd9 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -174,25 +174,25 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 };
 
 &mcu_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
-- 
2.40.0

[PATCH 05/12] arm64: dts: ti: k3-j7200-som/common-proc-board: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 2 +-
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi           | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 0cc0e1dc40c5..5ddb40bcda9e 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -192,7 +192,7 @@ &wkup_gpio1 {
 
 &mcu_cpsw {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index fa44ed4c17d5..f33212552bd9 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -174,25 +174,25 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 };
 
 &mcu_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
-- 
2.40.0


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[PATCH 06/12] arm64: dts: ti: k3-j721s2-common-proc-board: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 1299c715f34c..0bb40dd8e485 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -304,7 +304,7 @@ &main_sdhci1 {
 
 &mcu_cpsw {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
-- 
2.40.0

[PATCH 06/12] arm64: dts: ti: k3-j721s2-common-proc-board: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 1299c715f34c..0bb40dd8e485 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -304,7 +304,7 @@ &main_sdhci1 {
 
 &mcu_cpsw {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
-- 
2.40.0


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[PATCH 07/12] arm64: dts: ti: k3-am625-sk: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am625-sk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
index 2a1adda9bff6..611837a89608 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
@@ -183,8 +183,8 @@ &sdhci1 {
 
 &cpsw3g {
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_rgmii1_pins_default
-		     &main_rgmii2_pins_default>;
+	pinctrl-0 = <&main_rgmii1_pins_default>,
+		    <&main_rgmii2_pins_default>;
 };
 
 &cpsw_port2 {
-- 
2.40.0

[PATCH 07/12] arm64: dts: ti: k3-am625-sk: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am625-sk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
index 2a1adda9bff6..611837a89608 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
@@ -183,8 +183,8 @@ &sdhci1 {
 
 &cpsw3g {
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_rgmii1_pins_default
-		     &main_rgmii2_pins_default>;
+	pinctrl-0 = <&main_rgmii1_pins_default>,
+		    <&main_rgmii2_pins_default>;
 };
 
 &cpsw_port2 {
-- 
2.40.0


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[PATCH 08/12] arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 91bdc6026d1f..fef68a778ac9 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -467,8 +467,8 @@ &usb0 {
 
 &cpsw3g {
 	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii1_pins_default
-		     &rgmii2_pins_default>;
+	pinctrl-0 = <&rgmii1_pins_default>,
+		    <&rgmii2_pins_default>;
 };
 
 &cpsw_port1 {
@@ -560,25 +560,25 @@ &mailbox0_cluster7 {
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
 			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
 			<&main_r5fss1_core1_memory_region>;
 };
-- 
2.40.0

[PATCH 08/12] arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 91bdc6026d1f..fef68a778ac9 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -467,8 +467,8 @@ &usb0 {
 
 &cpsw3g {
 	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii1_pins_default
-		     &rgmii2_pins_default>;
+	pinctrl-0 = <&rgmii1_pins_default>,
+		    <&rgmii2_pins_default>;
 };
 
 &cpsw_port1 {
@@ -560,25 +560,25 @@ &mailbox0_cluster7 {
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
 			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
 			<&main_r5fss1_core1_memory_region>;
 };
-- 
2.40.0


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[PATCH 09/12] arm64: dts: ti: k3-am64-sk: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index c12738133e20..bcdb7daa288c 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -461,8 +461,8 @@ &usb0 {
 
 &cpsw3g {
 	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii1_pins_default
-		     &rgmii2_pins_default>;
+	pinctrl-0 = <&rgmii1_pins_default>,
+		    <&rgmii2_pins_default>;
 };
 
 &cpsw_port1 {
@@ -559,25 +559,25 @@ &mailbox0_cluster7 {
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
 			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
 			<&main_r5fss1_core1_memory_region>;
 };
-- 
2.40.0

[PATCH 09/12] arm64: dts: ti: k3-am64-sk: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index c12738133e20..bcdb7daa288c 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -461,8 +461,8 @@ &usb0 {
 
 &cpsw3g {
 	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii1_pins_default
-		     &rgmii2_pins_default>;
+	pinctrl-0 = <&rgmii1_pins_default>,
+		    <&rgmii2_pins_default>;
 };
 
 &cpsw_port1 {
@@ -559,25 +559,25 @@ &mailbox0_cluster7 {
 };
 
 &main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
 			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
 			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
 			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
 			<&main_r5fss1_core1_memory_region>;
 };
-- 
2.40.0


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[PATCH 10/12] arm64: dts: ti: k3-am65-iot*: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Cc: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 .../boot/dts/ti/k3-am65-iot2050-common.dtsi    | 17 ++++++++---------
 .../dts/ti/k3-am6548-iot2050-advanced-m2.dts   | 18 ++++++++----------
 2 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 6b052a0ecfa1..bbbb5c169ccc 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -384,13 +384,12 @@ &main_gpio0 {
 
 &wkup_gpio0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <
-		&arduino_io_d2_to_d3_pins_default
-		&arduino_i2c_aio_switch_pins_default
-		&arduino_io_oe_pins_default
-		&push_button_pins_default
-		&db9_com_mode_pins_default
-	>;
+	pinctrl-0 =
+		<&arduino_io_d2_to_d3_pins_default>,
+		<&arduino_i2c_aio_switch_pins_default>,
+		<&arduino_io_oe_pins_default>,
+		<&push_button_pins_default>,
+		<&db9_com_mode_pins_default>;
 	gpio-line-names =
 		/* 0..9 */
 		"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
@@ -711,11 +710,11 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 &mcu_r5fss0_core0 {
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 };
 
 &mcu_r5fss0_core1 {
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
-	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
index d5e41bdc89c3..1fc93e0b3c9b 100644
--- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
+++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
@@ -66,20 +66,18 @@ AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7)  /* (C23) GPIO1_89 */
 
 &main_gpio0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <
-		&main_m2_pcie_mux_control
-		&arduino_io_d4_to_d9_pins_default
-	>;
+	pinctrl-0 =
+		<&main_m2_pcie_mux_control>,
+		<&arduino_io_d4_to_d9_pins_default>;
 };
 
 &main_gpio1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <
-		&main_m2_enable_pins_default
-		&main_pmx0_m2_config_pins_default
-		&main_pmx1_m2_config_pins_default
-		&cp2102n_reset_pin_default
-	>;
+	pinctrl-0 =
+		<&main_m2_enable_pins_default>,
+		<&main_pmx0_m2_config_pins_default>,
+		<&main_pmx1_m2_config_pins_default>,
+		<&cp2102n_reset_pin_default>;
 };
 
 /*
-- 
2.40.0

[PATCH 10/12] arm64: dts: ti: k3-am65-iot*: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Cc: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 .../boot/dts/ti/k3-am65-iot2050-common.dtsi    | 17 ++++++++---------
 .../dts/ti/k3-am6548-iot2050-advanced-m2.dts   | 18 ++++++++----------
 2 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 6b052a0ecfa1..bbbb5c169ccc 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -384,13 +384,12 @@ &main_gpio0 {
 
 &wkup_gpio0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <
-		&arduino_io_d2_to_d3_pins_default
-		&arduino_i2c_aio_switch_pins_default
-		&arduino_io_oe_pins_default
-		&push_button_pins_default
-		&db9_com_mode_pins_default
-	>;
+	pinctrl-0 =
+		<&arduino_io_d2_to_d3_pins_default>,
+		<&arduino_i2c_aio_switch_pins_default>,
+		<&arduino_io_oe_pins_default>,
+		<&push_button_pins_default>,
+		<&db9_com_mode_pins_default>;
 	gpio-line-names =
 		/* 0..9 */
 		"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
@@ -711,11 +710,11 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 &mcu_r5fss0_core0 {
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 };
 
 &mcu_r5fss0_core1 {
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
-	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
index d5e41bdc89c3..1fc93e0b3c9b 100644
--- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
+++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
@@ -66,20 +66,18 @@ AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7)  /* (C23) GPIO1_89 */
 
 &main_gpio0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <
-		&main_m2_pcie_mux_control
-		&arduino_io_d4_to_d9_pins_default
-	>;
+	pinctrl-0 =
+		<&main_m2_pcie_mux_control>,
+		<&arduino_io_d4_to_d9_pins_default>;
 };
 
 &main_gpio1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <
-		&main_m2_enable_pins_default
-		&main_pmx0_m2_config_pins_default
-		&main_pmx1_m2_config_pins_default
-		&cp2102n_reset_pin_default
-	>;
+	pinctrl-0 =
+		<&main_m2_enable_pins_default>,
+		<&main_pmx0_m2_config_pins_default>,
+		<&main_pmx1_m2_config_pins_default>,
+		<&cp2102n_reset_pin_default>;
 };
 
 /*
-- 
2.40.0


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[PATCH 11/12] arm64: dts: ti: k3-am654-base-board: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 615c2395484d..64f847383b04 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -481,13 +481,13 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 &mcu_r5fss0_core0 {
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 };
 
 &mcu_r5fss0_core1 {
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
-	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
 };
 
 &ospi0 {
-- 
2.40.0

[PATCH 11/12] arm64: dts: ti: k3-am654-base-board: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 615c2395484d..64f847383b04 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -481,13 +481,13 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 &mcu_r5fss0_core0 {
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
-	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
 };
 
 &mcu_r5fss0_core1 {
 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 			<&mcu_r5fss0_core1_memory_region>;
-	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+	mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
 };
 
 &ospi0 {
-- 
2.40.0


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[PATCH 12/12] arm64: dts: ti: k3-am68-sk-base-board: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
index 27a43a8ecffd..ae9116655a83 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
@@ -287,7 +287,7 @@ &main_sdhci1 {
 
 &mcu_cpsw {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
-- 
2.40.0

[PATCH 12/12] arm64: dts: ti: k3-am68-sk-base-board: Fixup reference to phandles array

[Nishanth Menon]

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
index 27a43a8ecffd..ae9116655a83 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
@@ -287,7 +287,7 @@ &main_sdhci1 {
 
 &mcu_cpsw {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
-- 
2.40.0


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Re: [PATCH 10/12] arm64: dts: ti: k3-am65-iot*: Fixup reference to phandles array

[Jan Kiszka]

On 01.06.23 17:26, Nishanth Menon wrote:
> When referring to array of phandles, using <> to separate the array
> entries is better notation as it makes potential errors with phandle and
> cell arguments easier to catch. Fix the outliers to be consistent with
> the rest of the usage.
> 
> Cc: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  .../boot/dts/ti/k3-am65-iot2050-common.dtsi    | 17 ++++++++---------
>  .../dts/ti/k3-am6548-iot2050-advanced-m2.dts   | 18 ++++++++----------
>  2 files changed, 16 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
> index 6b052a0ecfa1..bbbb5c169ccc 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
> @@ -384,13 +384,12 @@ &main_gpio0 {
>  
>  &wkup_gpio0 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <
> -		&arduino_io_d2_to_d3_pins_default
> -		&arduino_i2c_aio_switch_pins_default
> -		&arduino_io_oe_pins_default
> -		&push_button_pins_default
> -		&db9_com_mode_pins_default
> -	>;
> +	pinctrl-0 =
> +		<&arduino_io_d2_to_d3_pins_default>,
> +		<&arduino_i2c_aio_switch_pins_default>,
> +		<&arduino_io_oe_pins_default>,
> +		<&push_button_pins_default>,
> +		<&db9_com_mode_pins_default>;
>  	gpio-line-names =
>  		/* 0..9 */
>  		"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
> @@ -711,11 +710,11 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
>  &mcu_r5fss0_core0 {
>  	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
>  			<&mcu_r5fss0_core0_memory_region>;
> -	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
> +	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
>  };
>  
>  &mcu_r5fss0_core1 {
>  	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
>  			<&mcu_r5fss0_core1_memory_region>;
> -	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
> +	mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
> index d5e41bdc89c3..1fc93e0b3c9b 100644
> --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
> @@ -66,20 +66,18 @@ AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7)  /* (C23) GPIO1_89 */
>  
>  &main_gpio0 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <
> -		&main_m2_pcie_mux_control
> -		&arduino_io_d4_to_d9_pins_default
> -	>;
> +	pinctrl-0 =
> +		<&main_m2_pcie_mux_control>,
> +		<&arduino_io_d4_to_d9_pins_default>;
>  };
>  
>  &main_gpio1 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <
> -		&main_m2_enable_pins_default
> -		&main_pmx0_m2_config_pins_default
> -		&main_pmx1_m2_config_pins_default
> -		&cp2102n_reset_pin_default
> -	>;
> +	pinctrl-0 =
> +		<&main_m2_enable_pins_default>,
> +		<&main_pmx0_m2_config_pins_default>,
> +		<&main_pmx1_m2_config_pins_default>,
> +		<&cp2102n_reset_pin_default>;
>  };
>  
>  /*

Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>

Jan

-- 
Siemens AG, Technology
Competence Center Embedded Linux

Re: [PATCH 10/12] arm64: dts: ti: k3-am65-iot*: Fixup reference to phandles array

[Jan Kiszka]

On 01.06.23 17:26, Nishanth Menon wrote:
> When referring to array of phandles, using <> to separate the array
> entries is better notation as it makes potential errors with phandle and
> cell arguments easier to catch. Fix the outliers to be consistent with
> the rest of the usage.
> 
> Cc: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  .../boot/dts/ti/k3-am65-iot2050-common.dtsi    | 17 ++++++++---------
>  .../dts/ti/k3-am6548-iot2050-advanced-m2.dts   | 18 ++++++++----------
>  2 files changed, 16 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
> index 6b052a0ecfa1..bbbb5c169ccc 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
> @@ -384,13 +384,12 @@ &main_gpio0 {
>  
>  &wkup_gpio0 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <
> -		&arduino_io_d2_to_d3_pins_default
> -		&arduino_i2c_aio_switch_pins_default
> -		&arduino_io_oe_pins_default
> -		&push_button_pins_default
> -		&db9_com_mode_pins_default
> -	>;
> +	pinctrl-0 =
> +		<&arduino_io_d2_to_d3_pins_default>,
> +		<&arduino_i2c_aio_switch_pins_default>,
> +		<&arduino_io_oe_pins_default>,
> +		<&push_button_pins_default>,
> +		<&db9_com_mode_pins_default>;
>  	gpio-line-names =
>  		/* 0..9 */
>  		"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
> @@ -711,11 +710,11 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
>  &mcu_r5fss0_core0 {
>  	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
>  			<&mcu_r5fss0_core0_memory_region>;
> -	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
> +	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
>  };
>  
>  &mcu_r5fss0_core1 {
>  	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
>  			<&mcu_r5fss0_core1_memory_region>;
> -	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
> +	mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
> index d5e41bdc89c3..1fc93e0b3c9b 100644
> --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
> @@ -66,20 +66,18 @@ AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7)  /* (C23) GPIO1_89 */
>  
>  &main_gpio0 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <
> -		&main_m2_pcie_mux_control
> -		&arduino_io_d4_to_d9_pins_default
> -	>;
> +	pinctrl-0 =
> +		<&main_m2_pcie_mux_control>,
> +		<&arduino_io_d4_to_d9_pins_default>;
>  };
>  
>  &main_gpio1 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <
> -		&main_m2_enable_pins_default
> -		&main_pmx0_m2_config_pins_default
> -		&main_pmx1_m2_config_pins_default
> -		&cp2102n_reset_pin_default
> -	>;
> +	pinctrl-0 =
> +		<&main_m2_enable_pins_default>,
> +		<&main_pmx0_m2_config_pins_default>,
> +		<&main_pmx1_m2_config_pins_default>,
> +		<&cp2102n_reset_pin_default>;
>  };
>  
>  /*

Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>

Jan

-- 
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Competence Center Embedded Linux


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Re: [PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Kumar, Udit]

Hi Nishanth

On 6/1/2023 8:56 PM, Nishanth Menon wrote:
> When referring to array of phandles, using <> to separate the array
> entries is better notation as it makes potential errors with phandle and
> cell arguments easier to catch. Fix the outliers to be consistent with
> the rest of the usage.
>
> Cc: Robert Nelson <robertcnelson@gmail.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>   .../boot/dts/ti/k3-j721e-beagleboneai64.dts   | 29 ++++++++++---------
>   1 file changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> index 37c24b077b6a..c13246a9ed8f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> @@ -593,7 +593,7 @@ &main_i2c0 {
>   &main_i2c1 {
>   	status = "okay";
>   	pinctrl-names = "default";
> -	pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>;
> +	pinctrl-0 = <&main_i2c1_pins_default>, <&csi1_gpio_pins_default>;
>   	clock-frequency = <400000>;
>   };
>   
> @@ -623,7 +623,7 @@ &main_i2c4 {
>   &main_i2c5 {
>   	status = "okay";
>   	pinctrl-names = "default";
> -	pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>;
> +	pinctrl-0 = <&main_i2c5_pins_default>, <&csi0_gpio_pins_default>;
>   	clock-frequency = <400000>;
>   };
>   
> @@ -639,7 +639,7 @@ &main_i2c6 {
>   &wkup_i2c0 {
>   	status = "okay";
>   	pinctrl-names = "default";
> -	pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
> +	pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
>   	clock-frequency = <400000>;

Why we need more than 2 pio lines for i2c node ,


> [...]
>

Re: [PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Kumar, Udit]

Hi Nishanth

On 6/1/2023 8:56 PM, Nishanth Menon wrote:
> When referring to array of phandles, using <> to separate the array
> entries is better notation as it makes potential errors with phandle and
> cell arguments easier to catch. Fix the outliers to be consistent with
> the rest of the usage.
>
> Cc: Robert Nelson <robertcnelson@gmail.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>   .../boot/dts/ti/k3-j721e-beagleboneai64.dts   | 29 ++++++++++---------
>   1 file changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> index 37c24b077b6a..c13246a9ed8f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> @@ -593,7 +593,7 @@ &main_i2c0 {
>   &main_i2c1 {
>   	status = "okay";
>   	pinctrl-names = "default";
> -	pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>;
> +	pinctrl-0 = <&main_i2c1_pins_default>, <&csi1_gpio_pins_default>;
>   	clock-frequency = <400000>;
>   };
>   
> @@ -623,7 +623,7 @@ &main_i2c4 {
>   &main_i2c5 {
>   	status = "okay";
>   	pinctrl-names = "default";
> -	pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>;
> +	pinctrl-0 = <&main_i2c5_pins_default>, <&csi0_gpio_pins_default>;
>   	clock-frequency = <400000>;
>   };
>   
> @@ -639,7 +639,7 @@ &main_i2c6 {
>   &wkup_i2c0 {
>   	status = "okay";
>   	pinctrl-names = "default";
> -	pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
> +	pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
>   	clock-frequency = <400000>;

Why we need more than 2 pio lines for i2c node ,


> [...]
>

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Re: [PATCH 08/12] arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array

[Kumar, Udit]

Hi Nishanth

On 6/1/2023 8:56 PM, Nishanth Menon wrote:
> When referring to array of phandles, using <> to separate the array
> entries is better notation as it makes potential errors with phandle and
> cell arguments easier to catch. Fix the outliers to be consistent with
> the rest of the usage.
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 91bdc6026d1f..fef68a778ac9 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -467,8 +467,8 @@ &usb0 {
>   
>   &cpsw3g {
>   	pinctrl-names = "default";
> -	pinctrl-0 = <&rgmii1_pins_default
> -		     &rgmii2_pins_default>;
> +	pinctrl-0 = <&rgmii1_pins_default>,
> +		    <&rgmii2_pins_default>;


Please see, if  pinctrl-0 can be defined in one line, instead of two, to 
be inline with most of changes in this series.

> [..]

Re: [PATCH 08/12] arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array

[Kumar, Udit]

Hi Nishanth

On 6/1/2023 8:56 PM, Nishanth Menon wrote:
> When referring to array of phandles, using <> to separate the array
> entries is better notation as it makes potential errors with phandle and
> cell arguments easier to catch. Fix the outliers to be consistent with
> the rest of the usage.
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 91bdc6026d1f..fef68a778ac9 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -467,8 +467,8 @@ &usb0 {
>   
>   &cpsw3g {
>   	pinctrl-names = "default";
> -	pinctrl-0 = <&rgmii1_pins_default
> -		     &rgmii2_pins_default>;
> +	pinctrl-0 = <&rgmii1_pins_default>,
> +		    <&rgmii2_pins_default>;


Please see, if  pinctrl-0 can be defined in one line, instead of two, to 
be inline with most of changes in this series.

> [..]

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Re: [PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Nishanth Menon]

On 22:31-20230605, Kumar, Udit wrote:
[...]
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > index 37c24b077b6a..c13246a9ed8f 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
[...]
> > @@ -639,7 +639,7 @@ &main_i2c6 {
> >   &wkup_i2c0 {
> >   	status = "okay";
> >   	pinctrl-names = "default";
> > -	pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
> > +	pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
> >   	clock-frequency = <400000>;
> 
> Why we need more than 2 pio lines for i2c node ,

pio lines? I am not sure I understand. If you are suggesting
eeprom_wp_pins to be moved to the eeprom node, It is probably
un-related to this series, but OK, i think it is probably a valid
change (unless Robert sees a reason why he did it the way he did).

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Nishanth Menon]

On 22:31-20230605, Kumar, Udit wrote:
[...]
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > index 37c24b077b6a..c13246a9ed8f 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
[...]
> > @@ -639,7 +639,7 @@ &main_i2c6 {
> >   &wkup_i2c0 {
> >   	status = "okay";
> >   	pinctrl-names = "default";
> > -	pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
> > +	pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
> >   	clock-frequency = <400000>;
> 
> Why we need more than 2 pio lines for i2c node ,

pio lines? I am not sure I understand. If you are suggesting
eeprom_wp_pins to be moved to the eeprom node, It is probably
un-related to this series, but OK, i think it is probably a valid
change (unless Robert sees a reason why he did it the way he did).

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH 08/12] arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array

[Nishanth Menon]

On 22:32-20230605, Kumar, Udit wrote:
> Hi Nishanth
> 
> On 6/1/2023 8:56 PM, Nishanth Menon wrote:
> > When referring to array of phandles, using <> to separate the array
> > entries is better notation as it makes potential errors with phandle and
> > cell arguments easier to catch. Fix the outliers to be consistent with
> > the rest of the usage.
> > 
> > Signed-off-by: Nishanth Menon <nm@ti.com>
> > ---
> >   arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++------
> >   1 file changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> > index 91bdc6026d1f..fef68a778ac9 100644
> > --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> > +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> > @@ -467,8 +467,8 @@ &usb0 {
> >   &cpsw3g {
> >   	pinctrl-names = "default";
> > -	pinctrl-0 = <&rgmii1_pins_default
> > -		     &rgmii2_pins_default>;
> > +	pinctrl-0 = <&rgmii1_pins_default>,
> > +		    <&rgmii2_pins_default>;
> 
> 
> Please see, if  pinctrl-0 can be defined in one line, instead of two, to be
> inline with most of changes in this series.

OK. I think i can respin it with that style change included once other
comments flow in.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 08/12] arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array

[Nishanth Menon]

On 22:32-20230605, Kumar, Udit wrote:
> Hi Nishanth
> 
> On 6/1/2023 8:56 PM, Nishanth Menon wrote:
> > When referring to array of phandles, using <> to separate the array
> > entries is better notation as it makes potential errors with phandle and
> > cell arguments easier to catch. Fix the outliers to be consistent with
> > the rest of the usage.
> > 
> > Signed-off-by: Nishanth Menon <nm@ti.com>
> > ---
> >   arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++------
> >   1 file changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> > index 91bdc6026d1f..fef68a778ac9 100644
> > --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> > +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> > @@ -467,8 +467,8 @@ &usb0 {
> >   &cpsw3g {
> >   	pinctrl-names = "default";
> > -	pinctrl-0 = <&rgmii1_pins_default
> > -		     &rgmii2_pins_default>;
> > +	pinctrl-0 = <&rgmii1_pins_default>,
> > +		    <&rgmii2_pins_default>;
> 
> 
> Please see, if  pinctrl-0 can be defined in one line, instead of two, to be
> inline with most of changes in this series.

OK. I think i can respin it with that style change included once other
comments flow in.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Kumar, Udit]

Hi Nishanth,

On 6/6/2023 2:19 AM, Nishanth Menon wrote:
> On 22:31-20230605, Kumar, Udit wrote:
> [...]
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>> index 37c24b077b6a..c13246a9ed8f 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> [...]
>>> @@ -639,7 +639,7 @@ &main_i2c6 {
>>>    &wkup_i2c0 {
>>>    	status = "okay";
>>>    	pinctrl-names = "default";
>>> -	pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
>>> +	pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
>>>    	clock-frequency = <400000>;
>> Why we need more than 2 pio lines for i2c node ,
> pio lines? I am not sure I understand. If you are suggesting
> eeprom_wp_pins to be moved to the eeprom node, It is probably
> un-related to this series, but OK, i think it is probably a valid
> change (unless Robert sees a reason why he did it the way he did).

correct, I am suggesting to move  eeprom_wp_pins_default to eeprom node.

i2c needs 2 lines which are defined in wkup_i2c0_pins_default, Adding 
eeprom_wp_pins_default will not be true representation of i2c node.

It will be good to have similar changes in main_i2c1 and main_i2c5  node 
for csi0_gpio_pins_default and csi1_gpio_pins_default.

Re: [PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Kumar, Udit]

Hi Nishanth,

On 6/6/2023 2:19 AM, Nishanth Menon wrote:
> On 22:31-20230605, Kumar, Udit wrote:
> [...]
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>> index 37c24b077b6a..c13246a9ed8f 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> [...]
>>> @@ -639,7 +639,7 @@ &main_i2c6 {
>>>    &wkup_i2c0 {
>>>    	status = "okay";
>>>    	pinctrl-names = "default";
>>> -	pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
>>> +	pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
>>>    	clock-frequency = <400000>;
>> Why we need more than 2 pio lines for i2c node ,
> pio lines? I am not sure I understand. If you are suggesting
> eeprom_wp_pins to be moved to the eeprom node, It is probably
> un-related to this series, but OK, i think it is probably a valid
> change (unless Robert sees a reason why he did it the way he did).

correct, I am suggesting to move  eeprom_wp_pins_default to eeprom node.

i2c needs 2 lines which are defined in wkup_i2c0_pins_default, Adding 
eeprom_wp_pins_default will not be true representation of i2c node.

It will be good to have similar changes in main_i2c1 and main_i2c5  node 
for csi0_gpio_pins_default and csi1_gpio_pins_default.



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Re: [PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Nishanth Menon]

On 09:56-20230606, Kumar, Udit wrote:
> On 6/6/2023 2:19 AM, Nishanth Menon wrote:
> > On 22:31-20230605, Kumar, Udit wrote:
> > [...]
> > > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > > > index 37c24b077b6a..c13246a9ed8f 100644
> > > > --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > > > +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > [...]
> > > > @@ -639,7 +639,7 @@ &main_i2c6 {
> > > >    &wkup_i2c0 {
> > > >    	status = "okay";
> > > >    	pinctrl-names = "default";
> > > > -	pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
> > > > +	pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
> > > >    	clock-frequency = <400000>;
> > > Why we need more than 2 pio lines for i2c node ,
> > pio lines? I am not sure I understand. If you are suggesting
> > eeprom_wp_pins to be moved to the eeprom node, It is probably
> > un-related to this series, but OK, i think it is probably a valid
> > change (unless Robert sees a reason why he did it the way he did).
> 
> correct, I am suggesting to move  eeprom_wp_pins_default to eeprom node.
> 
> i2c needs 2 lines which are defined in wkup_i2c0_pins_default, Adding
> eeprom_wp_pins_default will not be true representation of i2c node.
> 
> It will be good to have similar changes in main_i2c1 and main_i2c5  node for
> csi0_gpio_pins_default and csi1_gpio_pins_default.

Robert: your opinion here?

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Nishanth Menon]

On 09:56-20230606, Kumar, Udit wrote:
> On 6/6/2023 2:19 AM, Nishanth Menon wrote:
> > On 22:31-20230605, Kumar, Udit wrote:
> > [...]
> > > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > > > index 37c24b077b6a..c13246a9ed8f 100644
> > > > --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > > > +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > [...]
> > > > @@ -639,7 +639,7 @@ &main_i2c6 {
> > > >    &wkup_i2c0 {
> > > >    	status = "okay";
> > > >    	pinctrl-names = "default";
> > > > -	pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
> > > > +	pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
> > > >    	clock-frequency = <400000>;
> > > Why we need more than 2 pio lines for i2c node ,
> > pio lines? I am not sure I understand. If you are suggesting
> > eeprom_wp_pins to be moved to the eeprom node, It is probably
> > un-related to this series, but OK, i think it is probably a valid
> > change (unless Robert sees a reason why he did it the way he did).
> 
> correct, I am suggesting to move  eeprom_wp_pins_default to eeprom node.
> 
> i2c needs 2 lines which are defined in wkup_i2c0_pins_default, Adding
> eeprom_wp_pins_default will not be true representation of i2c node.
> 
> It will be good to have similar changes in main_i2c1 and main_i2c5  node for
> csi0_gpio_pins_default and csi1_gpio_pins_default.

Robert: your opinion here?

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Robert Nelson]

On Mon, Jun 5, 2023 at 11:27 PM Kumar, Udit <u-kumar1@ti.com> wrote:
>
> Hi Nishanth,
>
> On 6/6/2023 2:19 AM, Nishanth Menon wrote:
> > On 22:31-20230605, Kumar, Udit wrote:
> > [...]
> >>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> >>> index 37c24b077b6a..c13246a9ed8f 100644
> >>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> >>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > [...]
> >>> @@ -639,7 +639,7 @@ &main_i2c6 {
> >>>    &wkup_i2c0 {
> >>>     status = "okay";
> >>>     pinctrl-names = "default";
> >>> -   pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
> >>> +   pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
> >>>     clock-frequency = <400000>;
> >> Why we need more than 2 pio lines for i2c node ,
> > pio lines? I am not sure I understand. If you are suggesting
> > eeprom_wp_pins to be moved to the eeprom node, It is probably
> > un-related to this series, but OK, i think it is probably a valid
> > change (unless Robert sees a reason why he did it the way he did).
>
> correct, I am suggesting to move  eeprom_wp_pins_default to eeprom node.
>
> i2c needs 2 lines which are defined in wkup_i2c0_pins_default, Adding
> eeprom_wp_pins_default will not be true representation of i2c node.
>
> It will be good to have similar changes in main_i2c1 and main_i2c5  node
> for csi0_gpio_pins_default and csi1_gpio_pins_default.

I agree, moving eeprom_wp_pins_default into the eeprom node itself is
much cleaner going forward.

While we may have a lot of historical situations in the git tree where
we just dumped all pin configurations into the base node, that's not
the best practice going forward today.

Regards,

-- 
Robert Nelson
https://rcn-ee.com/

Re: [PATCH 03/12] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

[Robert Nelson]

On Mon, Jun 5, 2023 at 11:27 PM Kumar, Udit <u-kumar1@ti.com> wrote:
>
> Hi Nishanth,
>
> On 6/6/2023 2:19 AM, Nishanth Menon wrote:
> > On 22:31-20230605, Kumar, Udit wrote:
> > [...]
> >>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> >>> index 37c24b077b6a..c13246a9ed8f 100644
> >>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> >>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> > [...]
> >>> @@ -639,7 +639,7 @@ &main_i2c6 {
> >>>    &wkup_i2c0 {
> >>>     status = "okay";
> >>>     pinctrl-names = "default";
> >>> -   pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
> >>> +   pinctrl-0 = <&wkup_i2c0_pins_default>, <&eeprom_wp_pins_default>;
> >>>     clock-frequency = <400000>;
> >> Why we need more than 2 pio lines for i2c node ,
> > pio lines? I am not sure I understand. If you are suggesting
> > eeprom_wp_pins to be moved to the eeprom node, It is probably
> > un-related to this series, but OK, i think it is probably a valid
> > change (unless Robert sees a reason why he did it the way he did).
>
> correct, I am suggesting to move  eeprom_wp_pins_default to eeprom node.
>
> i2c needs 2 lines which are defined in wkup_i2c0_pins_default, Adding
> eeprom_wp_pins_default will not be true representation of i2c node.
>
> It will be good to have similar changes in main_i2c1 and main_i2c5  node
> for csi0_gpio_pins_default and csi1_gpio_pins_default.

I agree, moving eeprom_wp_pins_default into the eeprom node itself is
much cleaner going forward.

While we may have a lot of historical situations in the git tree where
we just dumped all pin configurations into the base node, that's not
the best practice going forward today.

Regards,

-- 
Robert Nelson
https://rcn-ee.com/

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