* [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe
@ 2023-06-06 8:50 sai.gowtham.ch
2023-06-06 8:50 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
` (4 more replies)
0 siblings, 5 replies; 31+ messages in thread
From: sai.gowtham.ch @ 2023-06-06 8:50 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Sai Gowtham Ch (2):
lib/xe/xe_spin: Integrate igt_spin_new with Xe
tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
lib/igt_dummyload.c | 38 +++++++--
lib/igt_dummyload.h | 11 +++
lib/xe/xe_spin.c | 97 ++++++++++++++++++++++
lib/xe/xe_spin.h | 6 +-
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
6 files changed, 315 insertions(+), 6 deletions(-)
create mode 100644 tests/xe/xe_spin_batch.c
--
2.39.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe
2023-06-06 8:50 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
@ 2023-06-06 8:50 ` sai.gowtham.ch
2023-06-06 19:27 ` Zbigniew Kempczyński
2023-06-06 8:50 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
` (3 subsequent siblings)
4 siblings, 1 reply; 31+ messages in thread
From: sai.gowtham.ch @ 2023-06-06 8:50 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
lib/igt_dummyload.c | 38 +++++++++++++++---
lib/igt_dummyload.h | 11 +++++
lib/xe/xe_spin.c | 97 +++++++++++++++++++++++++++++++++++++++++++++
lib/xe/xe_spin.h | 6 ++-
4 files changed, 146 insertions(+), 6 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 740a58f3..0c2a2029 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -46,6 +46,7 @@
#include "intel_reg.h"
#include "ioctl_wrappers.h"
#include "sw_sync.h"
+#include "xe/xe_spin.h"
/**
* SECTION:igt_dummyload
@@ -447,7 +448,18 @@ spin_create(int fd, const struct igt_spin_factory *opts)
igt_spin_t *
__igt_spin_factory(int fd, const struct igt_spin_factory *opts)
{
- return spin_create(fd, opts);
+ if (is_xe_device(fd)) {
+ igt_spin_t *spin;
+
+ spin = xe_spin_create(fd, opts);
+
+ pthread_mutex_lock(&list_lock);
+ igt_list_add(&spin->link, &spin_list);
+ pthread_mutex_unlock(&list_lock);
+
+ return spin;
+ } else
+ return spin_create(fd, opts);
}
/**
@@ -467,6 +479,16 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
{
igt_spin_t *spin;
+ if (is_xe_device(fd)) {
+ spin = xe_spin_create(fd, opts);
+
+ pthread_mutex_lock(&list_lock);
+ igt_list_add(&spin->link, &spin_list);
+ pthread_mutex_unlock(&list_lock);
+
+ return spin;
+ }
+
if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine != ALL_ENGINES) {
unsigned int class;
@@ -597,8 +619,12 @@ void igt_spin_end(igt_spin_t *spin)
if (!spin)
return;
- igt_gettime(&spin->last_signal);
- sync_write(spin, MI_BATCH_BUFFER_END);
+ if (is_xe_device(spin->fd))
+ xe_spin_end(spin->xe_spin);
+ else {
+ igt_gettime(&spin->last_signal);
+ sync_write(spin, MI_BATCH_BUFFER_END);
+ }
}
static void __igt_spin_free(int fd, igt_spin_t *spin)
@@ -646,12 +672,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
{
if (!spin)
return;
-
pthread_mutex_lock(&list_lock);
igt_list_del(&spin->link);
pthread_mutex_unlock(&list_lock);
- __igt_spin_free(fd, spin);
+ if (is_xe_device(fd))
+ xe_spin_free(fd, spin);
+ else
+ __igt_spin_free(fd, spin);
}
void igt_terminate_spins(void)
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index b247ab02..bfeb489d 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -54,6 +54,8 @@ typedef struct igt_spin_factory {
unsigned int flags;
int fence;
uint64_t ahnd;
+ struct drm_xe_engine_class_instance *hwe;
+ uint32_t vm;
} igt_spin_factory_t;
typedef struct igt_spin {
@@ -83,6 +85,15 @@ typedef struct igt_spin {
#define SPIN_CLFLUSH (1 << 0)
struct igt_spin_factory opts;
+
+ struct xe_spin *xe_spin;
+ int fd;
+ size_t bo_size;
+ uint64_t address;
+ unsigned int engine;
+ uint32_t vm;
+ uint32_t syncobj;
+
} igt_spin_t;
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 856d0ba2..43b4e691 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -82,6 +82,103 @@ void xe_spin_end(struct xe_spin *spin)
spin->end = 0;
}
+/**
+ * xe_spin_create:
+ *@opt: controlling options such as allocator handle, engine, vmetc
+ *
+ * igt_spin_new for xe, xe_spin_create submits a batch using xe_spin_init
+ * which wraps around vm bind and unbinding the object associated to it.
+ * This returs a spinner after submitting a dummy load.
+ *
+ */
+igt_spin_t *
+xe_spin_create(int fd, const struct igt_spin_factory *opt)
+{
+ size_t bo_size = xe_get_default_alignment(fd);
+ uint64_t ahnd = opt->ahnd, addr;
+ struct igt_spin *spin;
+ struct xe_spin *xe_spin;
+ struct drm_xe_sync sync = {
+ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+ };
+ struct drm_xe_exec exec = {
+ .num_batch_buffer = 1,
+ .num_syncs = 1,
+ .syncs = to_user_pointer(&sync),
+ };
+
+ igt_assert(ahnd);
+ spin = calloc(1, sizeof(struct igt_spin));
+ igt_assert(spin);
+
+ spin->syncobj = syncobj_create(fd, 0);
+ spin->vm = opt->vm;
+ spin->engine = opt->engine;
+
+ if (!spin->vm)
+ spin->vm = xe_vm_create(fd, 0, 0);
+
+ if (!spin->engine) {
+
+ if (opt->hwe)
+ spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
+ else
+ spin->engine = xe_engine_create_class(fd, spin->vm, DRM_XE_ENGINE_CLASS_COPY);
+ }
+
+ spin->handle = xe_bo_create(fd, 0, spin->vm, bo_size);
+ xe_spin = xe_bo_map(fd, spin->handle, bo_size);
+ addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
+ xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
+
+ xe_spin_init(xe_spin, addr, true);
+ exec.engine_id = spin->engine;
+ exec.address = addr;
+ sync.handle = spin->syncobj;
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
+ xe_spin_wait_started(xe_spin);
+
+ spin->bo_size = bo_size;
+ spin->address = addr;
+ spin->xe_spin = xe_spin;
+ spin->fd = fd;
+ spin->opts = *opt;
+
+ return spin;
+}
+
+void xe_spin_sync_wait(int fd, struct igt_spin *spin)
+{
+ igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0, NULL));
+}
+
+/*
+ * xe_spin_free:
+ *@spin: spin state from igt_spin_new()
+ *
+ * Wrapper to free spinner whhich is triggered by xe_spin_create.
+ * which distroys vm, engine and unbinds the vm which is binded to
+ * the engine and bo.
+ *
+ */
+void xe_spin_free(int fd, struct igt_spin *spin)
+{
+ xe_spin_end(spin->xe_spin);
+ xe_spin_sync_wait(fd, spin);
+ xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
+ syncobj_destroy(fd, spin->syncobj);
+ gem_munmap(spin->xe_spin, spin->bo_size);
+ gem_close(fd, spin->handle);
+
+ if (!spin->opts.engine)
+ xe_engine_destroy(fd, spin->engine);
+
+ if (!spin->opts.vm)
+ xe_vm_destroy(fd, spin->vm);
+
+ free(spin);
+}
+
void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
struct xe_cork *cork)
{
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index 73f9a026..60f6e751 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -13,6 +13,7 @@
#include <stdbool.h>
#include "xe_query.h"
+#include "lib/igt_dummyload.h"
/* Mapped GPU object */
struct xe_spin {
@@ -21,11 +22,14 @@ struct xe_spin {
uint32_t start;
uint32_t end;
};
-
+void xe_spin_user_vm_engine(int fd, const struct igt_spin_factory *opt, struct igt_spin *spin);
+igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
bool xe_spin_started(struct xe_spin *spin);
+void xe_spin_sync_wait(int fd, struct igt_spin *spin);
void xe_spin_wait_started(struct xe_spin *spin);
void xe_spin_end(struct xe_spin *spin);
+void xe_spin_free(int fd, struct igt_spin *spin);
struct xe_cork {
struct xe_spin *spin;
--
2.39.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-06 8:50 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-06-06 8:50 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
@ 2023-06-06 8:50 ` sai.gowtham.ch
2023-06-06 20:00 ` Zbigniew Kempczyński
2023-06-06 10:12 ` [igt-dev] ✗ GitLab.Pipeline: warning for Integrate igt_spin_new with Xe (rev3) Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 31+ messages in thread
From: sai.gowtham.ch @ 2023-06-06 8:50 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
xe_spin_batch test exercises igt_spin_new submissions with different
combination.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
2 files changed, 169 insertions(+)
create mode 100644 tests/xe/xe_spin_batch.c
diff --git a/tests/meson.build b/tests/meson.build
index f71be1db..e794b75a 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -268,6 +268,7 @@ xe_progs = [
'xe_query',
'xe_vm',
'xe_waitfence',
+ 'xe_spin_batch',
]
msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..ac531110
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,168 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+
+/**
+ * TEST: Basic test for spin batch submissons.
+ *
+ * SUBTEST: spin-basic
+ * Description: Basic test to submit spin batch submissons on copy engine.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_basic(int fd)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST:Test for spin batch submissons.
+ *
+ * SUBTEST: spin-batch
+ * Description: Create vm and engine of hwe class and run the spinner on it.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ unsigned int engine;
+ uint32_t vm;
+ igt_spin_t *spin;
+
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_engine_create(fd, vm, hwe, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ xe_engine_destroy(fd, engine);
+ xe_vm_destroy(fd, vm);
+
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Basic test for spin batch submission on all hwe.
+ *
+ * SUBTEST: spin-basic-all
+ * Description: Basic test which validates the functionality of spinner on all hwe.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+static void spin_basic_all(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all (int fd, int gt, int class)
+{
+ uint64_t ahnd;
+ uint32_t engines[MAX_INSTANCE];
+ uint32_t vm[MAX_INSTANCE];
+ int i, num_placements = 0;
+ struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+ igt_spin_t *spin[MAX_INSTANCE];
+ struct drm_xe_engine_class_instance *hwe;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ xe_for_each_hw_engine(fd, hwe) {
+ if (hwe->engine_class != class || hwe->gt_id != gt)
+ continue;
+ eci[num_placements++] = *hwe;
+ }
+ if (num_placements < 2)
+ return;
+
+ for (i = 0; i < num_placements; i++) {
+ struct drm_xe_engine_create create;
+ vm[i] = xe_vm_create(fd, 0, 0);
+
+ create.vm_id = vm[i];
+ create.width = 1;
+ create.num_placements = num_placements;
+ create.instances = to_user_pointer(eci);
+
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+ &create), 0);
+ engines[i] = create.engine_id;
+ spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm[i]);
+ }
+
+ for (i = 0; i < num_placements; i++) {
+ igt_assert(spin[i]);
+ igt_spin_free(fd, spin[i]);
+ }
+ put_ahnd(ahnd);
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+ int gt, class;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("spin-basic")
+ spin_basic(fd);
+
+ igt_subtest("spin-batch")
+ xe_for_each_hw_engine(fd, hwe)
+ spin(fd, hwe);
+
+ igt_subtest("spin-basic-all")
+ xe_for_each_hw_engine(fd, hwe)
+ spin_basic_all(fd, hwe);
+
+ igt_subtest("spin-all") {
+ xe_for_each_gt(fd, gt)
+ xe_for_each_hw_engine_class(class)
+ spin_all(fd, gt, class);
+ }
+
+ igt_fixture {
+ xe_device_put(fd);
+ close(fd);
+ }
+}
--
2.39.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: warning for Integrate igt_spin_new with Xe (rev3)
2023-06-06 8:50 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-06-06 8:50 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
2023-06-06 8:50 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-06-06 10:12 ` Patchwork
2023-06-06 10:44 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2023-06-07 1:32 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2023-06-06 10:12 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
== Series Details ==
Series: Integrate igt_spin_new with Xe (rev3)
URL : https://patchwork.freedesktop.org/series/118837/
State : warning
== Summary ==
Pipeline status: FAILED.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/901001 for the overview.
build:tests-debian-meson-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/43179016):
Running with gitlab-runner 15.9.1 (d540b510)
on fdo-equinix-m3l-17 7f7FXSjW, system ID: s_1d7dfffdd4ac
section_start:1686046237:prepare_executor
Preparing the "docker" executor
Using Docker executor with image registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-mips:commit-1ed7ec6eddf08e43c1fed442c42ce431c2dbb0c1 ...
Authenticating with credentials from job payload (GitLab Registry)
Pulling docker image registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-mips:commit-1ed7ec6eddf08e43c1fed442c42ce431c2dbb0c1 ...
WARNING: Failed to pull image with policy "if-not-present": initializing source docker://registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-mips:commit-1ed7ec6eddf08e43c1fed442c42ce431c2dbb0c1: reading manifest commit-1ed7ec6eddf08e43c1fed442c42ce431c2dbb0c1 in harbor.freedesktop.org/cache/gfx-ci/igt-ci-tags/build-debian-mips: unknown: artifact cache/gfx-ci/igt-ci-tags/build-debian-mips:commit-1ed7ec6eddf08e43c1fed442c42ce431c2dbb0c1 not found (manager.go:237:4s)
section_end:1686046244:prepare_executor
ERROR: Job failed: failed to pull image "registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-mips:commit-1ed7ec6eddf08e43c1fed442c42ce431c2dbb0c1" with specified policies [if-not-present]: initializing source docker://registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-mips:commit-1ed7ec6eddf08e43c1fed442c42ce431c2dbb0c1: reading manifest commit-1ed7ec6eddf08e43c1fed442c42ce431c2dbb0c1 in harbor.freedesktop.org/cache/gfx-ci/igt-ci-tags/build-debian-mips: unknown: artifact cache/gfx-ci/igt-ci-tags/build-debian-mips:commit-1ed7ec6eddf08e43c1fed442c42ce431c2dbb0c1 not found (manager.go:237:4s)
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/901001
^ permalink raw reply [flat|nested] 31+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Integrate igt_spin_new with Xe (rev3)
2023-06-06 8:50 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
` (2 preceding siblings ...)
2023-06-06 10:12 ` [igt-dev] ✗ GitLab.Pipeline: warning for Integrate igt_spin_new with Xe (rev3) Patchwork
@ 2023-06-06 10:44 ` Patchwork
2023-06-07 1:32 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2023-06-06 10:44 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 7883 bytes --]
== Series Details ==
Series: Integrate igt_spin_new with Xe (rev3)
URL : https://patchwork.freedesktop.org/series/118837/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13235 -> IGTPW_9112
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/index.html
Participating hosts (40 -> 39)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_9112:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5}:
- {bat-adlp-11}: [PASS][1] -> [FAIL][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5.html
Known issues
------------
Here are the changes found in IGTPW_9112 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][3] ([i915#7077])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-rplp-1/igt@i915_pm_backlight@basic-brightness@edp-1.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: NOTRUN -> [DMESG-WARN][4] ([i915#7699])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [PASS][5] -> [ABORT][6] ([i915#7913] / [i915#7982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/bat-rpls-2/igt@i915_selftest@live@requests.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][7] ([i915#6687] / [i915#7978])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#7828])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-dg2-11/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- {bat-adlp-11}: [ABORT][9] ([i915#7953]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/bat-adlp-11/igt@i915_pm_rpm@basic-pci-d3-state.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-adlp-11/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_lrc:
- bat-dg2-11: [INCOMPLETE][11] ([i915#7609] / [i915#7913]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@migrate:
- bat-adlp-9: [DMESG-FAIL][13] ([i915#7699] / [i915#7913]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/bat-adlp-9/igt@i915_selftest@live@migrate.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-adlp-9/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][15] ([i915#4983] / [i915#7911] / [i915#7920]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/bat-rpls-1/igt@i915_selftest@live@requests.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [FAIL][17] ([fdo#103375]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][19] ([i915#7932]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
#### Warnings ####
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [ABORT][21] ([i915#4579] / [i915#8260]) -> [SKIP][22] ([i915#3555] / [i915#4579])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7319 -> IGTPW_9112
CI-20190529: 20190529
CI_DRM_13235: 98a84b63adc57ae6500c03f8076f94e5d5a1743b @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9112: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/index.html
IGT_7319: 2e1bcd49944452b5f9516eecee48e1fa3ae6a636 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@xe_spin_batch@spin-all
+igt@xe_spin_batch@spin-basic
+igt@xe_spin_batch@spin-basic-all
+igt@xe_spin_batch@spin-batch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/index.html
[-- Attachment #2: Type: text/html, Size: 8321 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe
2023-06-06 8:50 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
@ 2023-06-06 19:27 ` Zbigniew Kempczyński
2023-06-06 21:03 ` Ch, Sai Gowtham
0 siblings, 1 reply; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-06-06 19:27 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
On Tue, Jun 06, 2023 at 02:20:14PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> Extending the spin_create implementation and allocator handle support in xe,
> where it submits dummy work loads to engine. This Implementation is wrapped
> around vm_bind and unbind as we are supposed to do it manually for xe.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> lib/igt_dummyload.c | 38 +++++++++++++++---
> lib/igt_dummyload.h | 11 +++++
> lib/xe/xe_spin.c | 97 +++++++++++++++++++++++++++++++++++++++++++++
> lib/xe/xe_spin.h | 6 ++-
> 4 files changed, 146 insertions(+), 6 deletions(-)
>
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 740a58f3..0c2a2029 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -46,6 +46,7 @@
> #include "intel_reg.h"
> #include "ioctl_wrappers.h"
> #include "sw_sync.h"
> +#include "xe/xe_spin.h"
>
> /**
> * SECTION:igt_dummyload
> @@ -447,7 +448,18 @@ spin_create(int fd, const struct igt_spin_factory *opts)
> igt_spin_t *
> __igt_spin_factory(int fd, const struct igt_spin_factory *opts)
> {
> - return spin_create(fd, opts);
> + if (is_xe_device(fd)) {
> + igt_spin_t *spin;
> +
> + spin = xe_spin_create(fd, opts);
> +
> + pthread_mutex_lock(&list_lock);
> + igt_list_add(&spin->link, &spin_list);
> + pthread_mutex_unlock(&list_lock);
> +
> + return spin;
> + } else
> + return spin_create(fd, opts);
> }
>
> /**
> @@ -467,6 +479,16 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
> {
> igt_spin_t *spin;
>
> + if (is_xe_device(fd)) {
> + spin = xe_spin_create(fd, opts);
> +
> + pthread_mutex_lock(&list_lock);
> + igt_list_add(&spin->link, &spin_list);
> + pthread_mutex_unlock(&list_lock);
> +
> + return spin;
> + }
> +
> if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine != ALL_ENGINES) {
> unsigned int class;
>
> @@ -597,8 +619,12 @@ void igt_spin_end(igt_spin_t *spin)
> if (!spin)
> return;
>
> - igt_gettime(&spin->last_signal);
> - sync_write(spin, MI_BATCH_BUFFER_END);
> + if (is_xe_device(spin->fd))
Use { for both if/else sequence if any of it > 1 line.
> + xe_spin_end(spin->xe_spin);
This check may be called on already closed filedescriptor leading to SIGSEGV.
I was a little bit surprised so I've added some debugging info to find out
the reason:
Program received signal SIGINT, Interrupt.
0x00007ffff7d2c51a in __GI___clock_nanosleep (clock_id=<optimized out>, clock_id@entry=0, flags=flags@entry=0, req=req@entry=0x7fffffffe070,
rem=rem@entry=0x7fffffffe070) at ../sysdeps/unix/sysv/linux/clock_nanosleep.c:73
Download failed: Function not implemented. Continuing without source file ./time/../sysdeps/unix/sysv/linux/clock_nanosleep.c.
73 ../sysdeps/unix/sysv/linux/clock_nanosleep.c: No such file or directory.
(gdb) bt
#0 0x00007ffff7d2c51a in __GI___clock_nanosleep (clock_id=<optimized out>, clock_id@entry=0, flags=flags@entry=0, req=req@entry=0x7fffffffe070,
rem=rem@entry=0x7fffffffe070) at ../sysdeps/unix/sysv/linux/clock_nanosleep.c:73
#1 0x00007ffff7d31ac7 in __GI___nanosleep (req=req@entry=0x7fffffffe070, rem=rem@entry=0x7fffffffe070) at ../sysdeps/unix/sysv/linux/nanosleep.c:25
#2 0x00007ffff7d319fe in __sleep (seconds=0) at ../sysdeps/posix/sleep.c:55
#3 0x00007ffff7f35eca in igt_spin_end (spin=0x5555555978a0) at ../lib/igt_dummyload.c:627
#4 0x00007ffff7f36192 in igt_terminate_spins () at ../lib/igt_dummyload.c:703
#5 0x00007ffff7f2c230 in call_exit_handlers (sig=0) at ../lib/igt_core.c:2825
#6 0x00007ffff7f2c2ac in igt_atexit_handler () at ../lib/igt_core.c:2845
#7 0x00007ffff7c98147 in __run_exit_handlers (status=0, listp=0x7ffff7e34738 <__exit_funcs>, run_list_atexit=run_list_atexit@entry=true,
run_dtors=run_dtors@entry=true) at exit.c:108
#8 0x00007ffff7c982f0 in __GI_exit (status=<optimized out>) at exit.c:139
#9 0x00007ffff7f2b172 in igt_exit () at ../lib/igt_core.c:2319
#10 0x0000555555555e0b in main (argc=1, argv=0x7fffffffe2e8) at ../tests/xe/xe_spin_batch.c:157
(gdb) frame 3
#3 0x00007ffff7f35eca in igt_spin_end (spin=0x5555555978a0) at ../lib/igt_dummyload.c:627
627 sleep(100);
(gdb) print *spin
$1 = {link = {prev = 0x7ffff7fb2830 <spin_list>, next = 0x55555559a080}, handle = 10, poll_handle = 0, batch = 0x0, condition = 0x0, cmd_precondition = 0,
poll = 0x0, last_signal = {tv_sec = 0, tv_nsec = 0}, timer_thread = 0, timerfd = 0, out_fence = 0, obj = {{handle = 0, relocation_count = 0, relocs_ptr = 0,
alignment = 0, offset = 0, flags = 0, {rsvd1 = 0, pad_to_size = 0}, rsvd2 = 0}, {handle = 0, relocation_count = 0, relocs_ptr = 0, alignment = 0, offset = 0,
flags = 0, {rsvd1 = 0, pad_to_size = 0}, rsvd2 = 0}}, execbuf = {buffers_ptr = 0, buffer_count = 0, batch_start_offset = 0, batch_len = 0, DR1 = 0, DR4 = 0,
num_cliprects = 0, cliprects_ptr = 0, flags = 0, rsvd1 = 0, rsvd2 = 0}, flags = 0, opts = {ctx_id = 0, ctx = 0x0, dependency = 0, dependency_size = 0,
engine = 0, flags = 0, fence = 0, ahnd = 1, hwe = 0x5555555987c6, vm = 1}, xe_spin = 0x7ffff5844000, fd = 3, bo_size = 65536, address = 851968, engine = 10,
vm = 1, syncobj = 10}
I think the best is to cache 'driver' in the spinner during creation.
> + else {
> + igt_gettime(&spin->last_signal);
> + sync_write(spin, MI_BATCH_BUFFER_END);
> + }
> }
>
> static void __igt_spin_free(int fd, igt_spin_t *spin)
> @@ -646,12 +672,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
> {
> if (!spin)
> return;
> -
> pthread_mutex_lock(&list_lock);
> igt_list_del(&spin->link);
> pthread_mutex_unlock(&list_lock);
>
> - __igt_spin_free(fd, spin);
> + if (is_xe_device(fd))
> + xe_spin_free(fd, spin);
> + else
> + __igt_spin_free(fd, spin);
> }
>
> void igt_terminate_spins(void)
> diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
> index b247ab02..bfeb489d 100644
> --- a/lib/igt_dummyload.h
> +++ b/lib/igt_dummyload.h
> @@ -54,6 +54,8 @@ typedef struct igt_spin_factory {
> unsigned int flags;
> int fence;
> uint64_t ahnd;
> + struct drm_xe_engine_class_instance *hwe;
> + uint32_t vm;
> } igt_spin_factory_t;
>
> typedef struct igt_spin {
> @@ -83,6 +85,15 @@ typedef struct igt_spin {
> #define SPIN_CLFLUSH (1 << 0)
>
> struct igt_spin_factory opts;
> +
> + struct xe_spin *xe_spin;
> + int fd;
> + size_t bo_size;
> + uint64_t address;
> + unsigned int engine;
> + uint32_t vm;
> + uint32_t syncobj;
> +
> } igt_spin_t;
>
>
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 856d0ba2..43b4e691 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -82,6 +82,103 @@ void xe_spin_end(struct xe_spin *spin)
> spin->end = 0;
> }
>
> +/**
> + * xe_spin_create:
> + *@opt: controlling options such as allocator handle, engine, vmetc
> + *
> + * igt_spin_new for xe, xe_spin_create submits a batch using xe_spin_init
> + * which wraps around vm bind and unbinding the object associated to it.
> + * This returs a spinner after submitting a dummy load.
> + *
> + */
> +igt_spin_t *
> +xe_spin_create(int fd, const struct igt_spin_factory *opt)
> +{
> + size_t bo_size = xe_get_default_alignment(fd);
> + uint64_t ahnd = opt->ahnd, addr;
> + struct igt_spin *spin;
> + struct xe_spin *xe_spin;
> + struct drm_xe_sync sync = {
> + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> + };
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 1,
> + .syncs = to_user_pointer(&sync),
> + };
> +
> + igt_assert(ahnd);
> + spin = calloc(1, sizeof(struct igt_spin));
> + igt_assert(spin);
> +
> + spin->syncobj = syncobj_create(fd, 0);
> + spin->vm = opt->vm;
> + spin->engine = opt->engine;
> +
> + if (!spin->vm)
> + spin->vm = xe_vm_create(fd, 0, 0);
> +
> + if (!spin->engine) {
> +
Unnecessary blank line.
Rest looks fine for me.
I think one respin and I'll accept it.
--
Zbigniew
> + if (opt->hwe)
> + spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
> + else
> + spin->engine = xe_engine_create_class(fd, spin->vm, DRM_XE_ENGINE_CLASS_COPY);
> + }
> +
> + spin->handle = xe_bo_create(fd, 0, spin->vm, bo_size);
> + xe_spin = xe_bo_map(fd, spin->handle, bo_size);
> + addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
> + xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
> +
> + xe_spin_init(xe_spin, addr, true);
> + exec.engine_id = spin->engine;
> + exec.address = addr;
> + sync.handle = spin->syncobj;
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
> + xe_spin_wait_started(xe_spin);
> +
> + spin->bo_size = bo_size;
> + spin->address = addr;
> + spin->xe_spin = xe_spin;
> + spin->fd = fd;
> + spin->opts = *opt;
> +
> + return spin;
> +}
> +
> +void xe_spin_sync_wait(int fd, struct igt_spin *spin)
> +{
> + igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0, NULL));
> +}
> +
> +/*
> + * xe_spin_free:
> + *@spin: spin state from igt_spin_new()
> + *
> + * Wrapper to free spinner whhich is triggered by xe_spin_create.
> + * which distroys vm, engine and unbinds the vm which is binded to
> + * the engine and bo.
> + *
> + */
> +void xe_spin_free(int fd, struct igt_spin *spin)
> +{
> + xe_spin_end(spin->xe_spin);
> + xe_spin_sync_wait(fd, spin);
> + xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
> + syncobj_destroy(fd, spin->syncobj);
> + gem_munmap(spin->xe_spin, spin->bo_size);
> + gem_close(fd, spin->handle);
> +
> + if (!spin->opts.engine)
> + xe_engine_destroy(fd, spin->engine);
> +
> + if (!spin->opts.vm)
> + xe_vm_destroy(fd, spin->vm);
> +
> + free(spin);
> +}
> +
> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> struct xe_cork *cork)
> {
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index 73f9a026..60f6e751 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -13,6 +13,7 @@
> #include <stdbool.h>
>
> #include "xe_query.h"
> +#include "lib/igt_dummyload.h"
>
> /* Mapped GPU object */
> struct xe_spin {
> @@ -21,11 +22,14 @@ struct xe_spin {
> uint32_t start;
> uint32_t end;
> };
> -
> +void xe_spin_user_vm_engine(int fd, const struct igt_spin_factory *opt, struct igt_spin *spin);
> +igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
> void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
> bool xe_spin_started(struct xe_spin *spin);
> +void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> void xe_spin_wait_started(struct xe_spin *spin);
> void xe_spin_end(struct xe_spin *spin);
> +void xe_spin_free(int fd, struct igt_spin *spin);
>
> struct xe_cork {
> struct xe_spin *spin;
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-06 8:50 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-06-06 20:00 ` Zbigniew Kempczyński
0 siblings, 0 replies; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-06-06 20:00 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
On Tue, Jun 06, 2023 at 02:20:15PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> xe_spin_batch test exercises igt_spin_new submissions with different
> combination.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 169 insertions(+)
> create mode 100644 tests/xe/xe_spin_batch.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index f71be1db..e794b75a 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -268,6 +268,7 @@ xe_progs = [
> 'xe_query',
> 'xe_vm',
> 'xe_waitfence',
> + 'xe_spin_batch',
> ]
>
> msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..ac531110
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,168 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +
> +/**
> + * TEST: Basic test for spin batch submissons.
> + *
> + * SUBTEST: spin-basic
> + * Description: Basic test to submit spin batch submissons on copy engine.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_basic(int fd)
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST:Test for spin batch submissons.
> + *
> + * SUBTEST: spin-batch
> + * Description: Create vm and engine of hwe class and run the spinner on it.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + unsigned int engine;
> + uint32_t vm;
> + igt_spin_t *spin;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_engine_create(fd, vm, hwe, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + xe_engine_destroy(fd, engine);
> + xe_vm_destroy(fd, vm);
> +
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Basic test for spin batch submission on all hwe.
> + *
> + * SUBTEST: spin-basic-all
> + * Description: Basic test which validates the functionality of spinner on all hwe.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +static void spin_basic_all(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
Use igt_spin_new() instead __ version.
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
I think this test is not doing what it claims. BTW I've encountered
a bug related to not properly set alignment in allocator open helpers.
Fix was sent (https://patchwork.freedesktop.org/series/118955/), it has
to be merged before your series. Especially I want to change this subtest
to sth like that:
+static void spin_basic_all(int fd)
+{
+ struct drm_xe_engine_class_instance *hwe;
+ uint64_t ahnd;
+ uint32_t vm;
+ igt_spin_t **spin;
+ int i = 0;
+
+ vm = xe_vm_create(fd, 0, 0);
+ ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
+ spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
+
+ xe_for_each_hw_engine(fd, hwe) {
+ igt_debug("Run on engine: %s:%d\n",
+ xe_engine_class_string(hwe->engine_class), hwe->engine_instance);
+ spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
+ igt_assert(spin[i]);
+ i++;
+ }
+
+ igt_info("Try to end spins\n");
+
Those two lines politely frees the spinner:
+ //while (--i >= 0)
+ // igt_spin_free(fd, spin[i]);
But if not terminate spinners should stop them.
+ //igt_terminate_spins();
Play with the code above and see segmentation fault on igt exit.
+ put_ahnd(ahnd);
+ xe_vm_destroy(fd, vm);
+ free(spin);
+}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all (int fd, int gt, int class)
^ unnecessary space
> +{
> + uint64_t ahnd;
> + uint32_t engines[MAX_INSTANCE];
> + uint32_t vm[MAX_INSTANCE];
> + int i, num_placements = 0;
> + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> + igt_spin_t *spin[MAX_INSTANCE];
> + struct drm_xe_engine_class_instance *hwe;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + xe_for_each_hw_engine(fd, hwe) {
> + if (hwe->engine_class != class || hwe->gt_id != gt)
> + continue;
> + eci[num_placements++] = *hwe;
> + }
> + if (num_placements < 2)
> + return;
> +
> + for (i = 0; i < num_placements; i++) {
> + struct drm_xe_engine_create create;
Add blank line between declaration and the code.
Anyway above line is the reason I observed failure when you had luck.
> + vm[i] = xe_vm_create(fd, 0, 0);
> +
> + create.vm_id = vm[i];
> + create.width = 1;
> + create.num_placements = num_placements;
> + create.instances = to_user_pointer(eci);
> +
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> + &create), 0);
> + engines[i] = create.engine_id;
> + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm[i]);
Same, use igt_spin_new() here.
> + }
> +
> + for (i = 0; i < num_placements; i++) {
> + igt_assert(spin[i]);
> + igt_spin_free(fd, spin[i]);
> + }
You're not freeing vm[i]'s.
> + put_ahnd(ahnd);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> + int gt, class;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> + }
> +
> + igt_subtest("spin-basic")
> + spin_basic(fd);
> +
> + igt_subtest("spin-batch")
> + xe_for_each_hw_engine(fd, hwe)
> + spin(fd, hwe);
> +
> + igt_subtest("spin-basic-all")
> + xe_for_each_hw_engine(fd, hwe)
> + spin_basic_all(fd, hwe);
igt_subtest("spin-basic-all")
- xe_for_each_hw_engine(fd, hwe)
- spin_basic_all(fd, hwe);
+ spin_basic_all(fd);
According to above.
--
Zbigniew
> +
> + igt_subtest("spin-all") {
> + xe_for_each_gt(fd, gt)
> + xe_for_each_hw_engine_class(class)
> + spin_all(fd, gt, class);
> + }
> +
> + igt_fixture {
> + xe_device_put(fd);
> + close(fd);
> + }
> +}
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe
2023-06-06 19:27 ` Zbigniew Kempczyński
@ 2023-06-06 21:03 ` Ch, Sai Gowtham
0 siblings, 0 replies; 31+ messages in thread
From: Ch, Sai Gowtham @ 2023-06-06 21:03 UTC (permalink / raw)
To: Kempczynski, Zbigniew; +Cc: igt-dev
> -----Original Message-----
> From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
> Sent: Wednesday, June 7, 2023 12:57 AM
> To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
> Cc: igt-dev@lists.freedesktop.org
> Subject: Re: [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe
>
> On Tue, Jun 06, 2023 at 02:20:14PM +0530, sai.gowtham.ch@intel.com wrote:
> > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> >
> > Extending the spin_create implementation and allocator handle support
> > in xe, where it submits dummy work loads to engine. This
> > Implementation is wrapped around vm_bind and unbind as we are supposed to
> do it manually for xe.
> >
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > ---
> > lib/igt_dummyload.c | 38 +++++++++++++++--- lib/igt_dummyload.h | 11
> > +++++
> > lib/xe/xe_spin.c | 97 +++++++++++++++++++++++++++++++++++++++++++++
> > lib/xe/xe_spin.h | 6 ++-
> > 4 files changed, 146 insertions(+), 6 deletions(-)
> >
> > diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c index
> > 740a58f3..0c2a2029 100644
> > --- a/lib/igt_dummyload.c
> > +++ b/lib/igt_dummyload.c
> > @@ -46,6 +46,7 @@
> > #include "intel_reg.h"
> > #include "ioctl_wrappers.h"
> > #include "sw_sync.h"
> > +#include "xe/xe_spin.h"
> >
> > /**
> > * SECTION:igt_dummyload
> > @@ -447,7 +448,18 @@ spin_create(int fd, const struct igt_spin_factory
> > *opts) igt_spin_t * __igt_spin_factory(int fd, const struct
> > igt_spin_factory *opts) {
> > - return spin_create(fd, opts);
> > + if (is_xe_device(fd)) {
> > + igt_spin_t *spin;
> > +
> > + spin = xe_spin_create(fd, opts);
> > +
> > + pthread_mutex_lock(&list_lock);
> > + igt_list_add(&spin->link, &spin_list);
> > + pthread_mutex_unlock(&list_lock);
> > +
> > + return spin;
> > + } else
> > + return spin_create(fd, opts);
> > }
> >
> > /**
> > @@ -467,6 +479,16 @@ igt_spin_factory(int fd, const struct
> > igt_spin_factory *opts) {
> > igt_spin_t *spin;
> >
> > + if (is_xe_device(fd)) {
> > + spin = xe_spin_create(fd, opts);
> > +
> > + pthread_mutex_lock(&list_lock);
> > + igt_list_add(&spin->link, &spin_list);
> > + pthread_mutex_unlock(&list_lock);
> > +
> > + return spin;
> > + }
> > +
> > if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine !=
> ALL_ENGINES) {
> > unsigned int class;
> >
> > @@ -597,8 +619,12 @@ void igt_spin_end(igt_spin_t *spin)
> > if (!spin)
> > return;
> >
> > - igt_gettime(&spin->last_signal);
> > - sync_write(spin, MI_BATCH_BUFFER_END);
> > + if (is_xe_device(spin->fd))
>
> Use { for both if/else sequence if any of it > 1 line.
>
> > + xe_spin_end(spin->xe_spin);
>
> This check may be called on already closed filedescriptor leading to SIGSEGV.
> I was a little bit surprised so I've added some debugging info to find out the
> reason:
>
> Program received signal SIGINT, Interrupt.
> 0x00007ffff7d2c51a in __GI___clock_nanosleep (clock_id=<optimized out>,
> clock_id@entry=0, flags=flags@entry=0, req=req@entry=0x7fffffffe070,
> rem=rem@entry=0x7fffffffe070) at
> ../sysdeps/unix/sysv/linux/clock_nanosleep.c:73
> Download failed: Function not implemented. Continuing without source file
> ./time/../sysdeps/unix/sysv/linux/clock_nanosleep.c.
> 73 ../sysdeps/unix/sysv/linux/clock_nanosleep.c: No such file or directory.
> (gdb) bt
> #0 0x00007ffff7d2c51a in __GI___clock_nanosleep (clock_id=<optimized out>,
> clock_id@entry=0, flags=flags@entry=0, req=req@entry=0x7fffffffe070,
> rem=rem@entry=0x7fffffffe070) at
> ../sysdeps/unix/sysv/linux/clock_nanosleep.c:73
> #1 0x00007ffff7d31ac7 in __GI___nanosleep (req=req@entry=0x7fffffffe070,
> rem=rem@entry=0x7fffffffe070) at ../sysdeps/unix/sysv/linux/nanosleep.c:25
> #2 0x00007ffff7d319fe in __sleep (seconds=0) at ../sysdeps/posix/sleep.c:55
> #3 0x00007ffff7f35eca in igt_spin_end (spin=0x5555555978a0) at
> ../lib/igt_dummyload.c:627
> #4 0x00007ffff7f36192 in igt_terminate_spins () at ../lib/igt_dummyload.c:703
> #5 0x00007ffff7f2c230 in call_exit_handlers (sig=0) at ../lib/igt_core.c:2825
> #6 0x00007ffff7f2c2ac in igt_atexit_handler () at ../lib/igt_core.c:2845
> #7 0x00007ffff7c98147 in __run_exit_handlers (status=0, listp=0x7ffff7e34738
> <__exit_funcs>, run_list_atexit=run_list_atexit@entry=true,
> run_dtors=run_dtors@entry=true) at exit.c:108
> #8 0x00007ffff7c982f0 in __GI_exit (status=<optimized out>) at exit.c:139
> #9 0x00007ffff7f2b172 in igt_exit () at ../lib/igt_core.c:2319
> #10 0x0000555555555e0b in main (argc=1, argv=0x7fffffffe2e8) at
> ../tests/xe/xe_spin_batch.c:157
> (gdb) frame 3
> #3 0x00007ffff7f35eca in igt_spin_end (spin=0x5555555978a0) at
> ../lib/igt_dummyload.c:627
> 627 sleep(100);
> (gdb) print *spin
> $1 = {link = {prev = 0x7ffff7fb2830 <spin_list>, next = 0x55555559a080}, handle
> = 10, poll_handle = 0, batch = 0x0, condition = 0x0, cmd_precondition = 0,
> poll = 0x0, last_signal = {tv_sec = 0, tv_nsec = 0}, timer_thread = 0, timerfd = 0,
> out_fence = 0, obj = {{handle = 0, relocation_count = 0, relocs_ptr = 0,
> alignment = 0, offset = 0, flags = 0, {rsvd1 = 0, pad_to_size = 0}, rsvd2 = 0},
> {handle = 0, relocation_count = 0, relocs_ptr = 0, alignment = 0, offset = 0,
> flags = 0, {rsvd1 = 0, pad_to_size = 0}, rsvd2 = 0}}, execbuf = {buffers_ptr = 0,
> buffer_count = 0, batch_start_offset = 0, batch_len = 0, DR1 = 0, DR4 = 0,
> num_cliprects = 0, cliprects_ptr = 0, flags = 0, rsvd1 = 0, rsvd2 = 0}, flags = 0,
> opts = {ctx_id = 0, ctx = 0x0, dependency = 0, dependency_size = 0,
> engine = 0, flags = 0, fence = 0, ahnd = 1, hwe = 0x5555555987c6, vm = 1},
> xe_spin = 0x7ffff5844000, fd = 3, bo_size = 65536, address = 851968, engine =
> 10,
> vm = 1, syncobj = 10}
>
> I think the best is to cache 'driver' in the spinner during creation.
>
> > + else {
> > + igt_gettime(&spin->last_signal);
> > + sync_write(spin, MI_BATCH_BUFFER_END);
> > + }
> > }
> >
> > static void __igt_spin_free(int fd, igt_spin_t *spin) @@ -646,12
> > +672,14 @@ void igt_spin_free(int fd, igt_spin_t *spin) {
> > if (!spin)
> > return;
> > -
> > pthread_mutex_lock(&list_lock);
> > igt_list_del(&spin->link);
> > pthread_mutex_unlock(&list_lock);
> >
> > - __igt_spin_free(fd, spin);
> > + if (is_xe_device(fd))
> > + xe_spin_free(fd, spin);
> > + else
> > + __igt_spin_free(fd, spin);
> > }
> >
> > void igt_terminate_spins(void)
> > diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h index
> > b247ab02..bfeb489d 100644
> > --- a/lib/igt_dummyload.h
> > +++ b/lib/igt_dummyload.h
> > @@ -54,6 +54,8 @@ typedef struct igt_spin_factory {
> > unsigned int flags;
> > int fence;
> > uint64_t ahnd;
> > + struct drm_xe_engine_class_instance *hwe;
> > + uint32_t vm;
> > } igt_spin_factory_t;
> >
> > typedef struct igt_spin {
> > @@ -83,6 +85,15 @@ typedef struct igt_spin { #define SPIN_CLFLUSH (1
> > << 0)
> >
> > struct igt_spin_factory opts;
> > +
> > + struct xe_spin *xe_spin;
> > + int fd;
> > + size_t bo_size;
> > + uint64_t address;
> > + unsigned int engine;
> > + uint32_t vm;
> > + uint32_t syncobj;
> > +
> > } igt_spin_t;
> >
> >
> > diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c index
> > 856d0ba2..43b4e691 100644
> > --- a/lib/xe/xe_spin.c
> > +++ b/lib/xe/xe_spin.c
> > @@ -82,6 +82,103 @@ void xe_spin_end(struct xe_spin *spin)
> > spin->end = 0;
> > }
> >
> > +/**
> > + * xe_spin_create:
> > + *@opt: controlling options such as allocator handle, engine, vmetc
> > + *
> > + * igt_spin_new for xe, xe_spin_create submits a batch using
> > +xe_spin_init
> > + * which wraps around vm bind and unbinding the object associated to it.
> > + * This returs a spinner after submitting a dummy load.
> > + *
> > + */
> > +igt_spin_t *
> > +xe_spin_create(int fd, const struct igt_spin_factory *opt) {
> > + size_t bo_size = xe_get_default_alignment(fd);
> > + uint64_t ahnd = opt->ahnd, addr;
> > + struct igt_spin *spin;
> > + struct xe_spin *xe_spin;
> > + struct drm_xe_sync sync = {
> > + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> > + };
> > + struct drm_xe_exec exec = {
> > + .num_batch_buffer = 1,
> > + .num_syncs = 1,
> > + .syncs = to_user_pointer(&sync),
> > + };
> > +
> > + igt_assert(ahnd);
> > + spin = calloc(1, sizeof(struct igt_spin));
> > + igt_assert(spin);
> > +
> > + spin->syncobj = syncobj_create(fd, 0);
> > + spin->vm = opt->vm;
> > + spin->engine = opt->engine;
> > +
> > + if (!spin->vm)
> > + spin->vm = xe_vm_create(fd, 0, 0);
> > +
> > + if (!spin->engine) {
> > +
>
> Unnecessary blank line.
>
> Rest looks fine for me.
>
> I think one respin and I'll accept it.
>
Sure I'll resend the patch, with this minor fix of storing DRIVER to use it in igt_spin_end.
--
Gowtham
> --
> Zbigniew
>
> > + if (opt->hwe)
> > + spin->engine = xe_engine_create(fd, spin->vm, opt-
> >hwe, 0);
> > + else
> > + spin->engine = xe_engine_create_class(fd, spin->vm,
> DRM_XE_ENGINE_CLASS_COPY);
> > + }
> > +
> > + spin->handle = xe_bo_create(fd, 0, spin->vm, bo_size);
> > + xe_spin = xe_bo_map(fd, spin->handle, bo_size);
> > + addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size,
> 0, ALLOC_STRATEGY_LOW_TO_HIGH);
> > + xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
> > +
> > + xe_spin_init(xe_spin, addr, true);
> > + exec.engine_id = spin->engine;
> > + exec.address = addr;
> > + sync.handle = spin->syncobj;
> > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
> > + xe_spin_wait_started(xe_spin);
> > +
> > + spin->bo_size = bo_size;
> > + spin->address = addr;
> > + spin->xe_spin = xe_spin;
> > + spin->fd = fd;
> > + spin->opts = *opt;
> > +
> > + return spin;
> > +}
> > +
> > +void xe_spin_sync_wait(int fd, struct igt_spin *spin) {
> > + igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0, NULL));
> > +}
> > +
> > +/*
> > + * xe_spin_free:
> > + *@spin: spin state from igt_spin_new()
> > + *
> > + * Wrapper to free spinner whhich is triggered by xe_spin_create.
> > + * which distroys vm, engine and unbinds the vm which is binded to
> > + * the engine and bo.
> > + *
> > + */
> > +void xe_spin_free(int fd, struct igt_spin *spin) {
> > + xe_spin_end(spin->xe_spin);
> > + xe_spin_sync_wait(fd, spin);
> > + xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
> > + syncobj_destroy(fd, spin->syncobj);
> > + gem_munmap(spin->xe_spin, spin->bo_size);
> > + gem_close(fd, spin->handle);
> > +
> > + if (!spin->opts.engine)
> > + xe_engine_destroy(fd, spin->engine);
> > +
> > + if (!spin->opts.vm)
> > + xe_vm_destroy(fd, spin->vm);
> > +
> > + free(spin);
> > +}
> > +
> > void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> > struct xe_cork *cork)
> > {
> > diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h index
> > 73f9a026..60f6e751 100644
> > --- a/lib/xe/xe_spin.h
> > +++ b/lib/xe/xe_spin.h
> > @@ -13,6 +13,7 @@
> > #include <stdbool.h>
> >
> > #include "xe_query.h"
> > +#include "lib/igt_dummyload.h"
> >
> > /* Mapped GPU object */
> > struct xe_spin {
> > @@ -21,11 +22,14 @@ struct xe_spin {
> > uint32_t start;
> > uint32_t end;
> > };
> > -
> > +void xe_spin_user_vm_engine(int fd, const struct igt_spin_factory
> > +*opt, struct igt_spin *spin); igt_spin_t *xe_spin_create(int fd,
> > +const struct igt_spin_factory *opt);
> > void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
> > bool xe_spin_started(struct xe_spin *spin);
> > +void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> > void xe_spin_wait_started(struct xe_spin *spin); void
> > xe_spin_end(struct xe_spin *spin);
> > +void xe_spin_free(int fd, struct igt_spin *spin);
> >
> > struct xe_cork {
> > struct xe_spin *spin;
> > --
> > 2.39.1
> >
^ permalink raw reply [flat|nested] 31+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Integrate igt_spin_new with Xe (rev3)
2023-06-06 8:50 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
` (3 preceding siblings ...)
2023-06-06 10:44 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-06-07 1:32 ` Patchwork
4 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2023-06-07 1:32 UTC (permalink / raw)
To: Ch, Sai Gowtham; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 15939 bytes --]
== Series Details ==
Series: Integrate igt_spin_new with Xe (rev3)
URL : https://patchwork.freedesktop.org/series/118837/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13235_full -> IGTPW_9112_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/index.html
Participating hosts (8 -> 8)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_9112_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_fence@expired-history:
- {shard-dg1}: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-dg1-18/igt@gem_exec_fence@expired-history.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-dg1-14/igt@gem_exec_fence@expired-history.html
Known issues
------------
Here are the changes found in IGTPW_9112_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: NOTRUN -> [FAIL][3] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-glk7/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [PASS][4] -> [FAIL][5] ([i915#2842])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-apl1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-glk8/igt@gem_exec_fair@basic-pace@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-glk2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-glk5/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][9] -> [DMESG-FAIL][10] ([i915#5334])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl1/igt@i915_selftest@live@gt_heartbeat.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-apl6/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) +16 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-glk8/igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_mc_ccs.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][12] -> [FAIL][13] ([i915#4767])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [PASS][14] -> [FAIL][15] ([i915#79])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4579])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-glk6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4579]) +11 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-snb7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271]) +15 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-snb4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][19] ([i915#2842]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-apl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- {shard-rkl}: [FAIL][21] ([i915#2842]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-rkl-3/igt@gem_exec_fair@basic-pace@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-rkl-1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}: [DMESG-WARN][23] ([i915#4936] / [i915#5493]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][25] ([i915#5566]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-glk3/igt@gen9_exec_parse@allowed-single.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-glk7/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-dg1}: [SKIP][27] ([i915#1397]) -> [PASS][28] +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-dg1-17/igt@i915_pm_rpm@dpms-lpsp.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-dg1-19/igt@i915_pm_rpm@dpms-lpsp.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][29] ([i915#2346]) -> [PASS][30] +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- {shard-rkl}: [FAIL][31] ([i915#8292]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-rkl-3/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-rkl-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@prime_self_import@reimport-vs-gem_close-race:
- shard-apl: [FAIL][33] ([i915#7951]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl1/igt@prime_self_import@reimport-vs-gem_close-race.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-apl3/igt@prime_self_import@reimport-vs-gem_close-race.html
#### Warnings ####
* igt@kms_content_protection@mei_interface:
- shard-apl: [SKIP][35] ([fdo#109271] / [i915#4579]) -> [SKIP][36] ([fdo#109271])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl4/igt@kms_content_protection@mei_interface.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-apl1/igt@kms_content_protection@mei_interface.html
- shard-snb: [SKIP][37] ([fdo#109271] / [i915#4579]) -> [SKIP][38] ([fdo#109271])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-snb2/igt@kms_content_protection@mei_interface.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-snb4/igt@kms_content_protection@mei_interface.html
- shard-glk: [SKIP][39] ([fdo#109271] / [i915#4579]) -> [SKIP][40] ([fdo#109271])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-glk8/igt@kms_content_protection@mei_interface.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/shard-glk6/igt@kms_content_protection@mei_interface.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7951]: https://gitlab.freedesktop.org/drm/intel/issues/7951
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8229]: https://gitlab.freedesktop.org/drm/intel/issues/8229
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7319 -> IGTPW_9112
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13235: 98a84b63adc57ae6500c03f8076f94e5d5a1743b @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9112: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/index.html
IGT_7319: 2e1bcd49944452b5f9516eecee48e1fa3ae6a636 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9112/index.html
[-- Attachment #2: Type: text/html, Size: 12802 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-15 10:59 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-06-16 6:22 ` Zbigniew Kempczyński
0 siblings, 0 replies; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-06-16 6:22 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
On Thu, Jun 15, 2023 at 04:29:54PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> xe_spin_batch test exercises igt_spin_new submissions with different
> combination.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_spin_batch.c | 179 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 180 insertions(+)
> create mode 100644 tests/xe/xe_spin_batch.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index 61dcc076..85ea7e74 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -269,6 +269,7 @@ xe_progs = [
> 'xe_query',
> 'xe_vm',
> 'xe_waitfence',
> + 'xe_spin_batch',
> ]
>
> msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..b930bc7e
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,179 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +
> +/**
> + * TEST: Basic test for spin batch submissons.
> + *
> + * SUBTEST: spin-basic
> + * Description: Basic test to submit spin batch submissons on copy engine.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_basic(int fd)
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = igt_spin_new(fd, .ahnd = ahnd);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST:Test for spin batch submissons.
> + *
> + * SUBTEST: spin-batch
> + * Description: Create vm and engine of hwe class and run the spinner on it.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + unsigned int engine;
> + uint32_t vm;
> + igt_spin_t *spin;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_engine_create(fd, vm, hwe, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> +
> + igt_spin_free(fd, spin);
> + xe_engine_destroy(fd, engine);
> + xe_vm_destroy(fd, vm);
> +
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Basic test for spin batch submission on all hwe.
> + *
> + * SUBTEST: spin-basic-all
> + * Description: Basic test which validates the functionality of spinner on all hwe.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +static void spin_basic_all(int fd)
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + uint64_t ahnd;
> + uint32_t vm;
> + igt_spin_t **spin;
> + int i = 0;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
> + spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
> + xe_for_each_hw_engine(fd, hwe) {
> + igt_debug("Run on engine: %s:%d\n",
> + xe_engine_class_string(hwe->engine_class), hwe->engine_instance);
Just minor nit - invalid indentation. Try to not neglect this in the future.
I'm going to fix this before merge.
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
--
Zbigniew
> + spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
> + i++;
> + }
> +
> + while (--i >= 0)
> + igt_spin_free(fd, spin[i]);
> +
> + put_ahnd(ahnd);
> + xe_vm_destroy(fd, vm);
> + free(spin);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all(int fd, int gt, int class)
> +{
> + uint64_t ahnd;
> + uint32_t engines[MAX_INSTANCE], vm;
> + int i, num_placements = 0;
> + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> + igt_spin_t *spin[MAX_INSTANCE];
> + struct drm_xe_engine_class_instance *hwe;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + xe_for_each_hw_engine(fd, hwe) {
> + if (hwe->engine_class != class || hwe->gt_id != gt)
> + continue;
> + eci[num_placements++] = *hwe;
> + }
> + if (num_placements < 2)
> + return;
> + vm = xe_vm_create(fd, 0, 0);
> +
> + for (i = 0; i < num_placements; i++) {
> + struct drm_xe_engine_create create = {
> + .vm_id = vm,
> + .width = 1,
> + .num_placements = num_placements,
> + .instances = to_user_pointer(eci),
> + };
> +
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> + &create), 0);
> + engines[i] = create.engine_id;
> + spin[i] = igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm);
> + }
> +
> + for (i = 0; i < num_placements; i++) {
> + igt_spin_free(fd, spin[i]);
> + xe_engine_destroy(fd, engines[i]);
> + }
> +
> + put_ahnd(ahnd);
> + xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> + int gt, class;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> + }
> +
> + igt_subtest("spin-basic")
> + spin_basic(fd);
> +
> + igt_subtest("spin-batch")
> + xe_for_each_hw_engine(fd, hwe)
> + spin(fd, hwe);
> +
> + igt_subtest("spin-basic-all")
> + spin_basic_all(fd);
> +
> + igt_subtest("spin-all") {
> + xe_for_each_gt(fd, gt)
> + xe_for_each_hw_engine_class(class)
> + spin_all(fd, gt, class);
> + }
> +
> + igt_fixture {
> + xe_device_put(fd);
> + close(fd);
> + }
> +}
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-15 10:59 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
@ 2023-06-15 10:59 ` sai.gowtham.ch
2023-06-16 6:22 ` Zbigniew Kempczyński
0 siblings, 1 reply; 31+ messages in thread
From: sai.gowtham.ch @ 2023-06-15 10:59 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
xe_spin_batch test exercises igt_spin_new submissions with different
combination.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 179 +++++++++++++++++++++++++++++++++++++++
2 files changed, 180 insertions(+)
create mode 100644 tests/xe/xe_spin_batch.c
diff --git a/tests/meson.build b/tests/meson.build
index 61dcc076..85ea7e74 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -269,6 +269,7 @@ xe_progs = [
'xe_query',
'xe_vm',
'xe_waitfence',
+ 'xe_spin_batch',
]
msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..b930bc7e
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,179 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+
+/**
+ * TEST: Basic test for spin batch submissons.
+ *
+ * SUBTEST: spin-basic
+ * Description: Basic test to submit spin batch submissons on copy engine.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_basic(int fd)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = igt_spin_new(fd, .ahnd = ahnd);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST:Test for spin batch submissons.
+ *
+ * SUBTEST: spin-batch
+ * Description: Create vm and engine of hwe class and run the spinner on it.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ unsigned int engine;
+ uint32_t vm;
+ igt_spin_t *spin;
+
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_engine_create(fd, vm, hwe, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
+
+ igt_spin_free(fd, spin);
+ xe_engine_destroy(fd, engine);
+ xe_vm_destroy(fd, vm);
+
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Basic test for spin batch submission on all hwe.
+ *
+ * SUBTEST: spin-basic-all
+ * Description: Basic test which validates the functionality of spinner on all hwe.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+static void spin_basic_all(int fd)
+{
+ struct drm_xe_engine_class_instance *hwe;
+ uint64_t ahnd;
+ uint32_t vm;
+ igt_spin_t **spin;
+ int i = 0;
+
+ vm = xe_vm_create(fd, 0, 0);
+ ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
+ spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
+ xe_for_each_hw_engine(fd, hwe) {
+ igt_debug("Run on engine: %s:%d\n",
+ xe_engine_class_string(hwe->engine_class), hwe->engine_instance);
+ spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
+ i++;
+ }
+
+ while (--i >= 0)
+ igt_spin_free(fd, spin[i]);
+
+ put_ahnd(ahnd);
+ xe_vm_destroy(fd, vm);
+ free(spin);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all(int fd, int gt, int class)
+{
+ uint64_t ahnd;
+ uint32_t engines[MAX_INSTANCE], vm;
+ int i, num_placements = 0;
+ struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+ igt_spin_t *spin[MAX_INSTANCE];
+ struct drm_xe_engine_class_instance *hwe;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ xe_for_each_hw_engine(fd, hwe) {
+ if (hwe->engine_class != class || hwe->gt_id != gt)
+ continue;
+ eci[num_placements++] = *hwe;
+ }
+ if (num_placements < 2)
+ return;
+ vm = xe_vm_create(fd, 0, 0);
+
+ for (i = 0; i < num_placements; i++) {
+ struct drm_xe_engine_create create = {
+ .vm_id = vm,
+ .width = 1,
+ .num_placements = num_placements,
+ .instances = to_user_pointer(eci),
+ };
+
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+ &create), 0);
+ engines[i] = create.engine_id;
+ spin[i] = igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm);
+ }
+
+ for (i = 0; i < num_placements; i++) {
+ igt_spin_free(fd, spin[i]);
+ xe_engine_destroy(fd, engines[i]);
+ }
+
+ put_ahnd(ahnd);
+ xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+ int gt, class;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("spin-basic")
+ spin_basic(fd);
+
+ igt_subtest("spin-batch")
+ xe_for_each_hw_engine(fd, hwe)
+ spin(fd, hwe);
+
+ igt_subtest("spin-basic-all")
+ spin_basic_all(fd);
+
+ igt_subtest("spin-all") {
+ xe_for_each_gt(fd, gt)
+ xe_for_each_hw_engine_class(class)
+ spin_all(fd, gt, class);
+ }
+
+ igt_fixture {
+ xe_device_put(fd);
+ close(fd);
+ }
+}
--
2.39.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-13 12:42 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-06-14 17:43 ` Zbigniew Kempczyński
0 siblings, 0 replies; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-06-14 17:43 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
On Tue, Jun 13, 2023 at 06:12:47PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> xe_spin_batch test exercises igt_spin_new submissions with different
> combination.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_spin_batch.c | 182 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 183 insertions(+)
> create mode 100644 tests/xe/xe_spin_batch.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index f908ae88..454b0060 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -268,6 +268,7 @@ xe_progs = [
> 'xe_query',
> 'xe_vm',
> 'xe_waitfence',
> + 'xe_spin_batch',
> ]
>
> msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..435daaf6
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,182 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +
> +/**
> + * TEST: Basic test for spin batch submissons.
> + *
> + * SUBTEST: spin-basic
> + * Description: Basic test to submit spin batch submissons on copy engine.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_basic(int fd)
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd);
If you want directly use __igt_spin_new() ok, but I thought you want
to use igt_spin_new() here.
> + igt_assert(spin);
This assert is not necessary, you may drop it as you have assert
check in xe_spin_create() codepath which excludes returning spin == NULL:
xe_spin.c: xe_spin_create():
+ spin = calloc(1, sizeof(struct igt_spin));
+ igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST:Test for spin batch submissons.
> + *
> + * SUBTEST: spin-batch
> + * Description: Create vm and engine of hwe class and run the spinner on it.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + unsigned int engine;
> + uint32_t vm;
> + igt_spin_t *spin;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_engine_create(fd, vm, hwe, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> + igt_assert(spin);
You may drop this assert.
> +
> + igt_spin_free(fd, spin);
> + xe_engine_destroy(fd, engine);
> + xe_vm_destroy(fd, vm);
> +
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Basic test for spin batch submission on all hwe.
> + *
> + * SUBTEST: spin-basic-all
> + * Description: Basic test which validates the functionality of spinner on all hwe.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +static void spin_basic_all(int fd)
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + uint64_t ahnd;
> + uint32_t vm;
> + igt_spin_t **spin;
> + int i = 0;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
> + spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
> + xe_for_each_hw_engine(fd, hwe) {
> + igt_debug("Run on engine: %s:%d\n",
> + xe_engine_class_string(hwe->engine_class), hwe->engine_instance);
> + spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
> + igt_assert(spin[i]);
This assert as well.
> + i++;
> + }
> +
> + while (--i>=0)
Minor nit, use:
while (--i >= 0)
for better readability.
> + igt_spin_free(fd, spin[i]);
> +
> + put_ahnd(ahnd);
> + xe_vm_destroy(fd, vm);
> + free(spin);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all(int fd, int gt, int class)
> +{
> + uint64_t ahnd;
> + uint32_t engines[MAX_INSTANCE], vm;
> + int i, num_placements = 0;
> + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> + igt_spin_t *spin[MAX_INSTANCE];
> + struct drm_xe_engine_class_instance *hwe;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + xe_for_each_hw_engine(fd, hwe) {
> + if (hwe->engine_class != class || hwe->gt_id != gt)
> + continue;
> + eci[num_placements++] = *hwe;
> + }
> + if (num_placements < 2)
> + return;
> + vm = xe_vm_create(fd, 0, 0);
> +
> + for (i = 0; i < num_placements; i++) {
> + struct drm_xe_engine_create create = {
> + .vm_id = vm,
> + .width = 1,
> + .num_placements = num_placements,
> + .instances = to_user_pointer(eci),
> + };
> +
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> + &create), 0);
> + engines[i] = create.engine_id;
> + spin[i] = igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm);
> + }
> +
> + for (i = 0; i < num_placements; i++) {
> + igt_assert(spin[i]);
This assert is not necessary.
> + igt_spin_free(fd, spin[i]);
But you're not destroying the engines. They are not destroyed
in the spinner code as spinner is not its owner.
Add:
+ xe_engine_destroy(fd, engines[i]);
Other things looks good. Resubmit and likely you'll got my rb
in next turn.
--
Zbigniew
> + }
> +
> + put_ahnd(ahnd);
> + xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> + int gt, class;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> + }
> +
> + igt_subtest("spin-basic")
> + spin_basic(fd);
> +
> + igt_subtest("spin-batch")
> + xe_for_each_hw_engine(fd, hwe)
> + spin(fd, hwe);
> +
> + igt_subtest("spin-basic-all")
> + spin_basic_all(fd);
> +
> + igt_subtest("spin-all") {
> + xe_for_each_gt(fd, gt)
> + xe_for_each_hw_engine_class(class)
> + spin_all(fd, gt, class);
> + }
> +
> + igt_fixture {
> + xe_device_put(fd);
> + close(fd);
> + }
> +}
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-13 12:42 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
@ 2023-06-13 12:42 ` sai.gowtham.ch
2023-06-14 17:43 ` Zbigniew Kempczyński
0 siblings, 1 reply; 31+ messages in thread
From: sai.gowtham.ch @ 2023-06-13 12:42 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
xe_spin_batch test exercises igt_spin_new submissions with different
combination.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 182 +++++++++++++++++++++++++++++++++++++++
2 files changed, 183 insertions(+)
create mode 100644 tests/xe/xe_spin_batch.c
diff --git a/tests/meson.build b/tests/meson.build
index f908ae88..454b0060 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -268,6 +268,7 @@ xe_progs = [
'xe_query',
'xe_vm',
'xe_waitfence',
+ 'xe_spin_batch',
]
msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..435daaf6
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,182 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+
+/**
+ * TEST: Basic test for spin batch submissons.
+ *
+ * SUBTEST: spin-basic
+ * Description: Basic test to submit spin batch submissons on copy engine.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_basic(int fd)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST:Test for spin batch submissons.
+ *
+ * SUBTEST: spin-batch
+ * Description: Create vm and engine of hwe class and run the spinner on it.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ unsigned int engine;
+ uint32_t vm;
+ igt_spin_t *spin;
+
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_engine_create(fd, vm, hwe, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ xe_engine_destroy(fd, engine);
+ xe_vm_destroy(fd, vm);
+
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Basic test for spin batch submission on all hwe.
+ *
+ * SUBTEST: spin-basic-all
+ * Description: Basic test which validates the functionality of spinner on all hwe.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+static void spin_basic_all(int fd)
+{
+ struct drm_xe_engine_class_instance *hwe;
+ uint64_t ahnd;
+ uint32_t vm;
+ igt_spin_t **spin;
+ int i = 0;
+
+ vm = xe_vm_create(fd, 0, 0);
+ ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
+ spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
+ xe_for_each_hw_engine(fd, hwe) {
+ igt_debug("Run on engine: %s:%d\n",
+ xe_engine_class_string(hwe->engine_class), hwe->engine_instance);
+ spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
+ igt_assert(spin[i]);
+ i++;
+ }
+
+ while (--i>=0)
+ igt_spin_free(fd, spin[i]);
+
+ put_ahnd(ahnd);
+ xe_vm_destroy(fd, vm);
+ free(spin);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all(int fd, int gt, int class)
+{
+ uint64_t ahnd;
+ uint32_t engines[MAX_INSTANCE], vm;
+ int i, num_placements = 0;
+ struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+ igt_spin_t *spin[MAX_INSTANCE];
+ struct drm_xe_engine_class_instance *hwe;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ xe_for_each_hw_engine(fd, hwe) {
+ if (hwe->engine_class != class || hwe->gt_id != gt)
+ continue;
+ eci[num_placements++] = *hwe;
+ }
+ if (num_placements < 2)
+ return;
+ vm = xe_vm_create(fd, 0, 0);
+
+ for (i = 0; i < num_placements; i++) {
+ struct drm_xe_engine_create create = {
+ .vm_id = vm,
+ .width = 1,
+ .num_placements = num_placements,
+ .instances = to_user_pointer(eci),
+ };
+
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+ &create), 0);
+ engines[i] = create.engine_id;
+ spin[i] = igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm);
+ }
+
+ for (i = 0; i < num_placements; i++) {
+ igt_assert(spin[i]);
+ igt_spin_free(fd, spin[i]);
+ }
+
+ put_ahnd(ahnd);
+ xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+ int gt, class;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("spin-basic")
+ spin_basic(fd);
+
+ igt_subtest("spin-batch")
+ xe_for_each_hw_engine(fd, hwe)
+ spin(fd, hwe);
+
+ igt_subtest("spin-basic-all")
+ spin_basic_all(fd);
+
+ igt_subtest("spin-all") {
+ xe_for_each_gt(fd, gt)
+ xe_for_each_hw_engine_class(class)
+ spin_all(fd, gt, class);
+ }
+
+ igt_fixture {
+ xe_device_put(fd);
+ close(fd);
+ }
+}
--
2.39.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-12 8:59 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-06-12 18:46 ` Zbigniew Kempczyński
0 siblings, 0 replies; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-06-12 18:46 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
On Mon, Jun 12, 2023 at 02:29:48PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> xe_spin_batch test exercises igt_spin_new submissions with different
> combination.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_spin_batch.c | 180 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 181 insertions(+)
> create mode 100644 tests/xe/xe_spin_batch.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index f908ae88..454b0060 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -268,6 +268,7 @@ xe_progs = [
> 'xe_query',
> 'xe_vm',
> 'xe_waitfence',
> + 'xe_spin_batch',
> ]
>
> msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..6ce7e741
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,180 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +
> +/**
> + * TEST: Basic test for spin batch submissons.
> + *
> + * SUBTEST: spin-basic
> + * Description: Basic test to submit spin batch submissons on copy engine.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_basic(int fd)
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST:Test for spin batch submissons.
> + *
> + * SUBTEST: spin-batch
> + * Description: Create vm and engine of hwe class and run the spinner on it.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + unsigned int engine;
> + uint32_t vm;
> + igt_spin_t *spin;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_engine_create(fd, vm, hwe, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + xe_engine_destroy(fd, engine);
> + xe_vm_destroy(fd, vm);
> +
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Basic test for spin batch submission on all hwe.
> + *
> + * SUBTEST: spin-basic-all
> + * Description: Basic test which validates the functionality of spinner on all hwe.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +static void spin_basic_all(int fd)
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + uint64_t ahnd;
> + uint32_t vm;
> + igt_spin_t **spin;
> + int i = 0;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
> + spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
> + xe_for_each_hw_engine(fd, hwe) {
> + spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
> + igt_assert(spin[i]);
> + i++;
> + }
> +
> + while (--i>=0)
> + igt_spin_free(fd, spin[i]);
> +
> + put_ahnd(ahnd);
> + xe_vm_destroy(fd, vm);
> + free(spin);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all(int fd, int gt, int class)
> +{
> + uint64_t ahnd;
> + uint32_t engines[MAX_INSTANCE], vm;
> + int i, num_placements = 0;
> + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> + igt_spin_t *spin[MAX_INSTANCE];
> + struct drm_xe_engine_class_instance *hwe;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + xe_for_each_hw_engine(fd, hwe) {
> + if (hwe->engine_class != class || hwe->gt_id != gt)
> + continue;
> + eci[num_placements++] = *hwe;
> + }
> + if (num_placements < 2)
> + return;
> + vm = xe_vm_create(fd, 0, 0);
> +
> + for (i = 0; i < num_placements; i++) {
> + struct drm_xe_engine_create create;
This line is still buggy causing:
(xe_spin_batch:27808) CRITICAL: Failed assertion: igt_ioctl(fd, (((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0x40 + 0x06)) << 0) | ((((sizeof(struct drm_xe_engine_create)))) << ((0+8)+8))), &create) == 0
(xe_spin_batch:27808) CRITICAL: Last errno: 22, Invalid argument
Hint: it's on the stack
--
Zbigniew
> +
> + create.vm_id = vm;
> + create.width = 1;
> + create.num_placements = num_placements;
> + create.instances = to_user_pointer(eci);
> +
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> + &create), 0);
> + engines[i] = create.engine_id;
> + spin[i] = igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm);
> + }
> +
> + for (i = 0; i < num_placements; i++) {
> + igt_assert(spin[i]);
> + igt_spin_free(fd, spin[i]);
> + }
> +
> + put_ahnd(ahnd);
> + xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> + int gt, class;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> + }
> +
> + igt_subtest("spin-basic")
> + spin_basic(fd);
> +
> + igt_subtest("spin-batch")
> + xe_for_each_hw_engine(fd, hwe)
> + spin(fd, hwe);
> +
> + igt_subtest("spin-basic-all")
> + spin_basic_all(fd);
> +
> + igt_subtest("spin-all") {
> + xe_for_each_gt(fd, gt)
> + xe_for_each_hw_engine_class(class)
> + spin_all(fd, gt, class);
> + }
> +
> + igt_fixture {
> + xe_device_put(fd);
> + close(fd);
> + }
> +}
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-12 8:59 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
@ 2023-06-12 8:59 ` sai.gowtham.ch
2023-06-12 18:46 ` Zbigniew Kempczyński
0 siblings, 1 reply; 31+ messages in thread
From: sai.gowtham.ch @ 2023-06-12 8:59 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
xe_spin_batch test exercises igt_spin_new submissions with different
combination.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 180 +++++++++++++++++++++++++++++++++++++++
2 files changed, 181 insertions(+)
create mode 100644 tests/xe/xe_spin_batch.c
diff --git a/tests/meson.build b/tests/meson.build
index f908ae88..454b0060 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -268,6 +268,7 @@ xe_progs = [
'xe_query',
'xe_vm',
'xe_waitfence',
+ 'xe_spin_batch',
]
msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..6ce7e741
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,180 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+
+/**
+ * TEST: Basic test for spin batch submissons.
+ *
+ * SUBTEST: spin-basic
+ * Description: Basic test to submit spin batch submissons on copy engine.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_basic(int fd)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST:Test for spin batch submissons.
+ *
+ * SUBTEST: spin-batch
+ * Description: Create vm and engine of hwe class and run the spinner on it.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ unsigned int engine;
+ uint32_t vm;
+ igt_spin_t *spin;
+
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_engine_create(fd, vm, hwe, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ xe_engine_destroy(fd, engine);
+ xe_vm_destroy(fd, vm);
+
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Basic test for spin batch submission on all hwe.
+ *
+ * SUBTEST: spin-basic-all
+ * Description: Basic test which validates the functionality of spinner on all hwe.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+static void spin_basic_all(int fd)
+{
+ struct drm_xe_engine_class_instance *hwe;
+ uint64_t ahnd;
+ uint32_t vm;
+ igt_spin_t **spin;
+ int i = 0;
+
+ vm = xe_vm_create(fd, 0, 0);
+ ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC);
+ spin = malloc(sizeof(*spin) * xe_number_hw_engines(fd));
+ xe_for_each_hw_engine(fd, hwe) {
+ spin[i] = igt_spin_new(fd, .ahnd = ahnd, .vm = vm, .hwe = hwe);
+ igt_assert(spin[i]);
+ i++;
+ }
+
+ while (--i>=0)
+ igt_spin_free(fd, spin[i]);
+
+ put_ahnd(ahnd);
+ xe_vm_destroy(fd, vm);
+ free(spin);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all(int fd, int gt, int class)
+{
+ uint64_t ahnd;
+ uint32_t engines[MAX_INSTANCE], vm;
+ int i, num_placements = 0;
+ struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+ igt_spin_t *spin[MAX_INSTANCE];
+ struct drm_xe_engine_class_instance *hwe;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ xe_for_each_hw_engine(fd, hwe) {
+ if (hwe->engine_class != class || hwe->gt_id != gt)
+ continue;
+ eci[num_placements++] = *hwe;
+ }
+ if (num_placements < 2)
+ return;
+ vm = xe_vm_create(fd, 0, 0);
+
+ for (i = 0; i < num_placements; i++) {
+ struct drm_xe_engine_create create;
+
+ create.vm_id = vm;
+ create.width = 1;
+ create.num_placements = num_placements;
+ create.instances = to_user_pointer(eci);
+
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+ &create), 0);
+ engines[i] = create.engine_id;
+ spin[i] = igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm);
+ }
+
+ for (i = 0; i < num_placements; i++) {
+ igt_assert(spin[i]);
+ igt_spin_free(fd, spin[i]);
+ }
+
+ put_ahnd(ahnd);
+ xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+ int gt, class;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("spin-basic")
+ spin_basic(fd);
+
+ igt_subtest("spin-batch")
+ xe_for_each_hw_engine(fd, hwe)
+ spin(fd, hwe);
+
+ igt_subtest("spin-basic-all")
+ spin_basic_all(fd);
+
+ igt_subtest("spin-all") {
+ xe_for_each_gt(fd, gt)
+ xe_for_each_hw_engine_class(class)
+ spin_all(fd, gt, class);
+ }
+
+ igt_fixture {
+ xe_device_put(fd);
+ close(fd);
+ }
+}
--
2.39.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-05 13:24 ` Ch, Sai Gowtham
@ 2023-06-05 18:00 ` Zbigniew Kempczyński
0 siblings, 0 replies; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-06-05 18:00 UTC (permalink / raw)
To: Ch, Sai Gowtham; +Cc: igt-dev
On Mon, Jun 05, 2023 at 03:24:19PM +0200, Ch, Sai Gowtham wrote:
>
>
> > -----Original Message-----
> > From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
> > Sent: Monday, June 5, 2023 4:15 PM
> > To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
> > Cc: igt-dev@lists.freedesktop.org; Kumar, Janga Rahul
> > <janga.rahul.kumar@intel.com>; kamil.konieczny@linux.intel.com
> > Subject: Re: [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise
> > igt_spin_new for xe
> >
> > On Mon, Jun 05, 2023 at 01:28:11AM +0530, sai.gowtham.ch@intel.com wrote:
> > > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > >
> > > xe_spin_batch test exercises igt_spin_new submissions with different
> > > combination.
> >
> > On DG2:
> >
> > Starting subtest: spin-all
> > (xe_spin_batch:6866) CRITICAL: Test assertion failure function spin_all, file
> > ../tests/xe/xe_spin_batch.c:123:
> > (xe_spin_batch:6866) CRITICAL: Failed assertion: igt_ioctl(fd, (((2U|1U) <<
> > (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0x40 + 0x06)) << 0) | ((((sizeof(struct
> > drm_xe_engine_create)))) << ((0+8)+8))), &create) == 0
> > (xe_spin_batch:6866) CRITICAL: Last errno: 22, Invalid argument
> > (xe_spin_batch:6866) CRITICAL: error: -1 != 0 Stack trace:
> > #0 ../lib/igt_core.c:1963 __igt_fail_assert()
> > #1 ../tests/xe/xe_spin_batch.c:168 __igt_unique____real_main136()
> > #2 ../tests/xe/xe_spin_batch.c:136 main()
> > #3 ../csu/libc-start.c:332 __libc_start_main()
> > #4 [_start+0x2e]
> > Subtest spin-all failed.
> > **** DEBUG ****
> > (xe_spin_batch:6866) intel_allocator_reloc-DEBUG: Using reloc allocator
> > (xe_spin_batch:6866) CRITICAL: Test assertion failure function spin_all, file
> > ../tests/xe/xe_spin_batch.c:123:
> > (xe_spin_batch:6866) CRITICAL: Failed assertion: igt_ioctl(fd, (((2U|1U) <<
> > (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0x40 + 0x06)) << 0) | ((((sizeof(struct
> > drm_xe_engine_create)))) << ((0+8)+8))), &create) == 0
> > (xe_spin_batch:6866) CRITICAL: Last errno: 22, Invalid argument
> > (xe_spin_batch:6866) CRITICAL: error: -1 != 0
> > (xe_spin_batch:6866) igt_core-INFO: Stack trace:
> > (xe_spin_batch:6866) igt_core-INFO: #0 ../lib/igt_core.c:1963
> > __igt_fail_assert()
> > (xe_spin_batch:6866) igt_core-INFO: #1 ../tests/xe/xe_spin_batch.c:168
> > __igt_unique____real_main136()
> > (xe_spin_batch:6866) igt_core-INFO: #2 ../tests/xe/xe_spin_batch.c:136 main()
> > (xe_spin_batch:6866) igt_core-INFO: #3 ../csu/libc-start.c:332
> > __libc_start_main()
> > (xe_spin_batch:6866) igt_core-INFO: #4 [_start+0x2e]
> > **** END ****
> > Subtest spin-all: FAIL (0.014s)
> >
> > Please check.
> >
>
> Strange, Working fine for me.
>
> gta@DUT051DG2FRD:~/Gowtham/0106/igt-gpu-tools$ sudo ./build/tests/xe_spin_batch
> IGT-Version: 1.27.1-g41db4db7 (x86_64) (Linux: 6.3.0-xe-15052023+ x86_64)
> Opened device: /dev/dri/card0
> Starting subtest: spin-basic
> Subtest spin-basic: SUCCESS (0.008s)
> Starting subtest: spin-batch
> Subtest spin-batch: SUCCESS (0.061s)
> Starting subtest: spin-basic-all
> Subtest spin-basic-all: SUCCESS (0.075s)
> Starting subtest: spin-all
> Subtest spin-all: SUCCESS (0.028s)
>
May you run tools/lsgpu?
--
Zbigniew
> ---
> Gowtham
>
> > --
> > Zbigniew
> >
> >
> > >
> > > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > > ---
> > > tests/meson.build | 1 +
> > > tests/xe/xe_spin_batch.c | 168
> > > +++++++++++++++++++++++++++++++++++++++
> > > 2 files changed, 169 insertions(+)
> > > create mode 100644 tests/xe/xe_spin_batch.c
> > >
> > > diff --git a/tests/meson.build b/tests/meson.build index
> > > f71be1db..e794b75a 100644
> > > --- a/tests/meson.build
> > > +++ b/tests/meson.build
> > > @@ -268,6 +268,7 @@ xe_progs = [
> > > 'xe_query',
> > > 'xe_vm',
> > > 'xe_waitfence',
> > > + 'xe_spin_batch',
> > > ]
> > >
> > > msm_progs = [
> > > diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c new
> > > file mode 100644 index 00000000..ac531110
> > > --- /dev/null
> > > +++ b/tests/xe/xe_spin_batch.c
> > > @@ -0,0 +1,168 @@
> > > +#include "igt.h"
> > > +#include "lib/intel_reg.h"
> > > +#include "xe_drm.h"
> > > +#include "xe/xe_ioctl.h"
> > > +#include "xe/xe_query.h"
> > > +
> > > +#define MAX_INSTANCE 9
> > > +
> > > +/**
> > > + * TEST: Basic test for spin batch submissons.
> > > + *
> > > + * SUBTEST: spin-basic
> > > + * Description: Basic test to submit spin batch submissons on copy engine.
> > > + * Run type: FULL
> > > + * TODO: change ``'Run type' == FULL`` to a better category
> > > + *
> > > + */
> > > +
> > > +static void spin_basic(int fd)
> > > +{
> > > + uint64_t ahnd;
> > > + igt_spin_t *spin;
> > > +
> > > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > > + spin = __igt_spin_new(fd, .ahnd = ahnd);
> > > + igt_assert(spin);
> > > +
> > > + igt_spin_free(fd, spin);
> > > + put_ahnd(ahnd);
> > > +}
> > > +
> > > +/**
> > > + * TEST:Test for spin batch submissons.
> > > + *
> > > + * SUBTEST: spin-batch
> > > + * Description: Create vm and engine of hwe class and run the spinner on it.
> > > + * Run type: FULL
> > > + * TODO: change ``'Run type' == FULL`` to a better category
> > > + *
> > > + */
> > > +
> > > +static void spin(int fd, struct drm_xe_engine_class_instance *hwe) {
> > > + uint64_t ahnd;
> > > + unsigned int engine;
> > > + uint32_t vm;
> > > + igt_spin_t *spin;
> > > +
> > > + vm = xe_vm_create(fd, 0, 0);
> > > + engine = xe_engine_create(fd, vm, hwe, 0);
> > > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > > +
> > > + spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> > > + igt_assert(spin);
> > > +
> > > + igt_spin_free(fd, spin);
> > > + xe_engine_destroy(fd, engine);
> > > + xe_vm_destroy(fd, vm);
> > > +
> > > + put_ahnd(ahnd);
> > > +}
> > > +
> > > +/**
> > > + * TEST: Basic test for spin batch submission on all hwe.
> > > + *
> > > + * SUBTEST: spin-basic-all
> > > + * Description: Basic test which validates the functionality of spinner on all
> > hwe.
> > > + * Run type: FULL
> > > + * TODO: change ``'Run type' == FULL`` to a better category
> > > + *
> > > + */
> > > +static void spin_basic_all(int fd, struct
> > > +drm_xe_engine_class_instance *hwe) {
> > > + uint64_t ahnd;
> > > + igt_spin_t *spin;
> > > +
> > > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > > + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
> > > + igt_assert(spin);
> > > +
> > > + igt_spin_free(fd, spin);
> > > + put_ahnd(ahnd);
> > > +}
> > > +
> > > +/**
> > > + * TEST: Test for spin batch submissions.
> > > + * SUBTEST: spin-all
> > > + * Description: Spinner test to run on all the engines!
> > > + * Run type: FULL
> > > + * TODO: change ``'Run type' == FULL`` to a better category
> > > + *
> > > + */
> > > +
> > > +static void spin_all (int fd, int gt, int class) {
> > > + uint64_t ahnd;
> > > + uint32_t engines[MAX_INSTANCE];
> > > + uint32_t vm[MAX_INSTANCE];
> > > + int i, num_placements = 0;
> > > + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> > > + igt_spin_t *spin[MAX_INSTANCE];
> > > + struct drm_xe_engine_class_instance *hwe;
> > > +
> > > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > > +
> > > + xe_for_each_hw_engine(fd, hwe) {
> > > + if (hwe->engine_class != class || hwe->gt_id != gt)
> > > + continue;
> > > + eci[num_placements++] = *hwe;
> > > + }
> > > + if (num_placements < 2)
> > > + return;
> > > +
> > > + for (i = 0; i < num_placements; i++) {
> > > + struct drm_xe_engine_create create;
> > > + vm[i] = xe_vm_create(fd, 0, 0);
> > > +
> > > + create.vm_id = vm[i];
> > > + create.width = 1;
> > > + create.num_placements = num_placements;
> > > + create.instances = to_user_pointer(eci);
> > > +
> > > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> > > + &create), 0);
> > > + engines[i] = create.engine_id;
> > > + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i],
> > .vm = vm[i]);
> > > + }
> > > +
> > > + for (i = 0; i < num_placements; i++) {
> > > + igt_assert(spin[i]);
> > > + igt_spin_free(fd, spin[i]);
> > > + }
> > > + put_ahnd(ahnd);
> > > +}
> > > +
> > > +igt_main
> > > +{
> > > + struct drm_xe_engine_class_instance *hwe;
> > > + int fd;
> > > + int gt, class;
> > > +
> > > + igt_fixture {
> > > + fd = drm_open_driver(DRIVER_XE);
> > > + xe_device_get(fd);
> > > + }
> > > +
> > > + igt_subtest("spin-basic")
> > > + spin_basic(fd);
> > > +
> > > + igt_subtest("spin-batch")
> > > + xe_for_each_hw_engine(fd, hwe)
> > > + spin(fd, hwe);
> > > +
> > > + igt_subtest("spin-basic-all")
> > > + xe_for_each_hw_engine(fd, hwe)
> > > + spin_basic_all(fd, hwe);
> > > +
> > > + igt_subtest("spin-all") {
> > > + xe_for_each_gt(fd, gt)
> > > + xe_for_each_hw_engine_class(class)
> > > + spin_all(fd, gt, class);
> > > + }
> > > +
> > > + igt_fixture {
> > > + xe_device_put(fd);
> > > + close(fd);
> > > + }
> > > +}
> > > --
> > > 2.39.1
> > >
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-05 10:44 ` Zbigniew Kempczyński
@ 2023-06-05 13:24 ` Ch, Sai Gowtham
2023-06-05 18:00 ` Zbigniew Kempczyński
0 siblings, 1 reply; 31+ messages in thread
From: Ch, Sai Gowtham @ 2023-06-05 13:24 UTC (permalink / raw)
To: Kempczynski, Zbigniew; +Cc: igt-dev
> -----Original Message-----
> From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
> Sent: Monday, June 5, 2023 4:15 PM
> To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
> Cc: igt-dev@lists.freedesktop.org; Kumar, Janga Rahul
> <janga.rahul.kumar@intel.com>; kamil.konieczny@linux.intel.com
> Subject: Re: [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise
> igt_spin_new for xe
>
> On Mon, Jun 05, 2023 at 01:28:11AM +0530, sai.gowtham.ch@intel.com wrote:
> > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> >
> > xe_spin_batch test exercises igt_spin_new submissions with different
> > combination.
>
> On DG2:
>
> Starting subtest: spin-all
> (xe_spin_batch:6866) CRITICAL: Test assertion failure function spin_all, file
> ../tests/xe/xe_spin_batch.c:123:
> (xe_spin_batch:6866) CRITICAL: Failed assertion: igt_ioctl(fd, (((2U|1U) <<
> (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0x40 + 0x06)) << 0) | ((((sizeof(struct
> drm_xe_engine_create)))) << ((0+8)+8))), &create) == 0
> (xe_spin_batch:6866) CRITICAL: Last errno: 22, Invalid argument
> (xe_spin_batch:6866) CRITICAL: error: -1 != 0 Stack trace:
> #0 ../lib/igt_core.c:1963 __igt_fail_assert()
> #1 ../tests/xe/xe_spin_batch.c:168 __igt_unique____real_main136()
> #2 ../tests/xe/xe_spin_batch.c:136 main()
> #3 ../csu/libc-start.c:332 __libc_start_main()
> #4 [_start+0x2e]
> Subtest spin-all failed.
> **** DEBUG ****
> (xe_spin_batch:6866) intel_allocator_reloc-DEBUG: Using reloc allocator
> (xe_spin_batch:6866) CRITICAL: Test assertion failure function spin_all, file
> ../tests/xe/xe_spin_batch.c:123:
> (xe_spin_batch:6866) CRITICAL: Failed assertion: igt_ioctl(fd, (((2U|1U) <<
> (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0x40 + 0x06)) << 0) | ((((sizeof(struct
> drm_xe_engine_create)))) << ((0+8)+8))), &create) == 0
> (xe_spin_batch:6866) CRITICAL: Last errno: 22, Invalid argument
> (xe_spin_batch:6866) CRITICAL: error: -1 != 0
> (xe_spin_batch:6866) igt_core-INFO: Stack trace:
> (xe_spin_batch:6866) igt_core-INFO: #0 ../lib/igt_core.c:1963
> __igt_fail_assert()
> (xe_spin_batch:6866) igt_core-INFO: #1 ../tests/xe/xe_spin_batch.c:168
> __igt_unique____real_main136()
> (xe_spin_batch:6866) igt_core-INFO: #2 ../tests/xe/xe_spin_batch.c:136 main()
> (xe_spin_batch:6866) igt_core-INFO: #3 ../csu/libc-start.c:332
> __libc_start_main()
> (xe_spin_batch:6866) igt_core-INFO: #4 [_start+0x2e]
> **** END ****
> Subtest spin-all: FAIL (0.014s)
>
> Please check.
>
Strange, Working fine for me.
gta@DUT051DG2FRD:~/Gowtham/0106/igt-gpu-tools$ sudo ./build/tests/xe_spin_batch
IGT-Version: 1.27.1-g41db4db7 (x86_64) (Linux: 6.3.0-xe-15052023+ x86_64)
Opened device: /dev/dri/card0
Starting subtest: spin-basic
Subtest spin-basic: SUCCESS (0.008s)
Starting subtest: spin-batch
Subtest spin-batch: SUCCESS (0.061s)
Starting subtest: spin-basic-all
Subtest spin-basic-all: SUCCESS (0.075s)
Starting subtest: spin-all
Subtest spin-all: SUCCESS (0.028s)
---
Gowtham
> --
> Zbigniew
>
>
> >
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > ---
> > tests/meson.build | 1 +
> > tests/xe/xe_spin_batch.c | 168
> > +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 169 insertions(+)
> > create mode 100644 tests/xe/xe_spin_batch.c
> >
> > diff --git a/tests/meson.build b/tests/meson.build index
> > f71be1db..e794b75a 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -268,6 +268,7 @@ xe_progs = [
> > 'xe_query',
> > 'xe_vm',
> > 'xe_waitfence',
> > + 'xe_spin_batch',
> > ]
> >
> > msm_progs = [
> > diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c new
> > file mode 100644 index 00000000..ac531110
> > --- /dev/null
> > +++ b/tests/xe/xe_spin_batch.c
> > @@ -0,0 +1,168 @@
> > +#include "igt.h"
> > +#include "lib/intel_reg.h"
> > +#include "xe_drm.h"
> > +#include "xe/xe_ioctl.h"
> > +#include "xe/xe_query.h"
> > +
> > +#define MAX_INSTANCE 9
> > +
> > +/**
> > + * TEST: Basic test for spin batch submissons.
> > + *
> > + * SUBTEST: spin-basic
> > + * Description: Basic test to submit spin batch submissons on copy engine.
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin_basic(int fd)
> > +{
> > + uint64_t ahnd;
> > + igt_spin_t *spin;
> > +
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > + spin = __igt_spin_new(fd, .ahnd = ahnd);
> > + igt_assert(spin);
> > +
> > + igt_spin_free(fd, spin);
> > + put_ahnd(ahnd);
> > +}
> > +
> > +/**
> > + * TEST:Test for spin batch submissons.
> > + *
> > + * SUBTEST: spin-batch
> > + * Description: Create vm and engine of hwe class and run the spinner on it.
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin(int fd, struct drm_xe_engine_class_instance *hwe) {
> > + uint64_t ahnd;
> > + unsigned int engine;
> > + uint32_t vm;
> > + igt_spin_t *spin;
> > +
> > + vm = xe_vm_create(fd, 0, 0);
> > + engine = xe_engine_create(fd, vm, hwe, 0);
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> > + igt_assert(spin);
> > +
> > + igt_spin_free(fd, spin);
> > + xe_engine_destroy(fd, engine);
> > + xe_vm_destroy(fd, vm);
> > +
> > + put_ahnd(ahnd);
> > +}
> > +
> > +/**
> > + * TEST: Basic test for spin batch submission on all hwe.
> > + *
> > + * SUBTEST: spin-basic-all
> > + * Description: Basic test which validates the functionality of spinner on all
> hwe.
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +static void spin_basic_all(int fd, struct
> > +drm_xe_engine_class_instance *hwe) {
> > + uint64_t ahnd;
> > + igt_spin_t *spin;
> > +
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
> > + igt_assert(spin);
> > +
> > + igt_spin_free(fd, spin);
> > + put_ahnd(ahnd);
> > +}
> > +
> > +/**
> > + * TEST: Test for spin batch submissions.
> > + * SUBTEST: spin-all
> > + * Description: Spinner test to run on all the engines!
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin_all (int fd, int gt, int class) {
> > + uint64_t ahnd;
> > + uint32_t engines[MAX_INSTANCE];
> > + uint32_t vm[MAX_INSTANCE];
> > + int i, num_placements = 0;
> > + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> > + igt_spin_t *spin[MAX_INSTANCE];
> > + struct drm_xe_engine_class_instance *hwe;
> > +
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + xe_for_each_hw_engine(fd, hwe) {
> > + if (hwe->engine_class != class || hwe->gt_id != gt)
> > + continue;
> > + eci[num_placements++] = *hwe;
> > + }
> > + if (num_placements < 2)
> > + return;
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + struct drm_xe_engine_create create;
> > + vm[i] = xe_vm_create(fd, 0, 0);
> > +
> > + create.vm_id = vm[i];
> > + create.width = 1;
> > + create.num_placements = num_placements;
> > + create.instances = to_user_pointer(eci);
> > +
> > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> > + &create), 0);
> > + engines[i] = create.engine_id;
> > + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i],
> .vm = vm[i]);
> > + }
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + igt_assert(spin[i]);
> > + igt_spin_free(fd, spin[i]);
> > + }
> > + put_ahnd(ahnd);
> > +}
> > +
> > +igt_main
> > +{
> > + struct drm_xe_engine_class_instance *hwe;
> > + int fd;
> > + int gt, class;
> > +
> > + igt_fixture {
> > + fd = drm_open_driver(DRIVER_XE);
> > + xe_device_get(fd);
> > + }
> > +
> > + igt_subtest("spin-basic")
> > + spin_basic(fd);
> > +
> > + igt_subtest("spin-batch")
> > + xe_for_each_hw_engine(fd, hwe)
> > + spin(fd, hwe);
> > +
> > + igt_subtest("spin-basic-all")
> > + xe_for_each_hw_engine(fd, hwe)
> > + spin_basic_all(fd, hwe);
> > +
> > + igt_subtest("spin-all") {
> > + xe_for_each_gt(fd, gt)
> > + xe_for_each_hw_engine_class(class)
> > + spin_all(fd, gt, class);
> > + }
> > +
> > + igt_fixture {
> > + xe_device_put(fd);
> > + close(fd);
> > + }
> > +}
> > --
> > 2.39.1
> >
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-04 19:58 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-06-05 8:59 ` Kumar, Janga Rahul
@ 2023-06-05 10:44 ` Zbigniew Kempczyński
2023-06-05 13:24 ` Ch, Sai Gowtham
1 sibling, 1 reply; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-06-05 10:44 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
On Mon, Jun 05, 2023 at 01:28:11AM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> xe_spin_batch test exercises igt_spin_new submissions with different
> combination.
On DG2:
Starting subtest: spin-all
(xe_spin_batch:6866) CRITICAL: Test assertion failure function spin_all, file ../tests/xe/xe_spin_batch.c:123:
(xe_spin_batch:6866) CRITICAL: Failed assertion: igt_ioctl(fd, (((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0x40 + 0x06)) << 0) | ((((sizeof(struct drm_xe_engine_create)))) << ((0+8)+8))), &create) == 0
(xe_spin_batch:6866) CRITICAL: Last errno: 22, Invalid argument
(xe_spin_batch:6866) CRITICAL: error: -1 != 0
Stack trace:
#0 ../lib/igt_core.c:1963 __igt_fail_assert()
#1 ../tests/xe/xe_spin_batch.c:168 __igt_unique____real_main136()
#2 ../tests/xe/xe_spin_batch.c:136 main()
#3 ../csu/libc-start.c:332 __libc_start_main()
#4 [_start+0x2e]
Subtest spin-all failed.
**** DEBUG ****
(xe_spin_batch:6866) intel_allocator_reloc-DEBUG: Using reloc allocator
(xe_spin_batch:6866) CRITICAL: Test assertion failure function spin_all, file ../tests/xe/xe_spin_batch.c:123:
(xe_spin_batch:6866) CRITICAL: Failed assertion: igt_ioctl(fd, (((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0x40 + 0x06)) << 0) | ((((sizeof(struct drm_xe_engine_create)))) << ((0+8)+8))), &create) == 0
(xe_spin_batch:6866) CRITICAL: Last errno: 22, Invalid argument
(xe_spin_batch:6866) CRITICAL: error: -1 != 0
(xe_spin_batch:6866) igt_core-INFO: Stack trace:
(xe_spin_batch:6866) igt_core-INFO: #0 ../lib/igt_core.c:1963 __igt_fail_assert()
(xe_spin_batch:6866) igt_core-INFO: #1 ../tests/xe/xe_spin_batch.c:168 __igt_unique____real_main136()
(xe_spin_batch:6866) igt_core-INFO: #2 ../tests/xe/xe_spin_batch.c:136 main()
(xe_spin_batch:6866) igt_core-INFO: #3 ../csu/libc-start.c:332 __libc_start_main()
(xe_spin_batch:6866) igt_core-INFO: #4 [_start+0x2e]
**** END ****
Subtest spin-all: FAIL (0.014s)
Please check.
--
Zbigniew
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 169 insertions(+)
> create mode 100644 tests/xe/xe_spin_batch.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index f71be1db..e794b75a 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -268,6 +268,7 @@ xe_progs = [
> 'xe_query',
> 'xe_vm',
> 'xe_waitfence',
> + 'xe_spin_batch',
> ]
>
> msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..ac531110
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,168 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +
> +/**
> + * TEST: Basic test for spin batch submissons.
> + *
> + * SUBTEST: spin-basic
> + * Description: Basic test to submit spin batch submissons on copy engine.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_basic(int fd)
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST:Test for spin batch submissons.
> + *
> + * SUBTEST: spin-batch
> + * Description: Create vm and engine of hwe class and run the spinner on it.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + unsigned int engine;
> + uint32_t vm;
> + igt_spin_t *spin;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_engine_create(fd, vm, hwe, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + xe_engine_destroy(fd, engine);
> + xe_vm_destroy(fd, vm);
> +
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Basic test for spin batch submission on all hwe.
> + *
> + * SUBTEST: spin-basic-all
> + * Description: Basic test which validates the functionality of spinner on all hwe.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +static void spin_basic_all(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all (int fd, int gt, int class)
> +{
> + uint64_t ahnd;
> + uint32_t engines[MAX_INSTANCE];
> + uint32_t vm[MAX_INSTANCE];
> + int i, num_placements = 0;
> + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> + igt_spin_t *spin[MAX_INSTANCE];
> + struct drm_xe_engine_class_instance *hwe;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + xe_for_each_hw_engine(fd, hwe) {
> + if (hwe->engine_class != class || hwe->gt_id != gt)
> + continue;
> + eci[num_placements++] = *hwe;
> + }
> + if (num_placements < 2)
> + return;
> +
> + for (i = 0; i < num_placements; i++) {
> + struct drm_xe_engine_create create;
> + vm[i] = xe_vm_create(fd, 0, 0);
> +
> + create.vm_id = vm[i];
> + create.width = 1;
> + create.num_placements = num_placements;
> + create.instances = to_user_pointer(eci);
> +
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> + &create), 0);
> + engines[i] = create.engine_id;
> + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm[i]);
> + }
> +
> + for (i = 0; i < num_placements; i++) {
> + igt_assert(spin[i]);
> + igt_spin_free(fd, spin[i]);
> + }
> + put_ahnd(ahnd);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> + int gt, class;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> + }
> +
> + igt_subtest("spin-basic")
> + spin_basic(fd);
> +
> + igt_subtest("spin-batch")
> + xe_for_each_hw_engine(fd, hwe)
> + spin(fd, hwe);
> +
> + igt_subtest("spin-basic-all")
> + xe_for_each_hw_engine(fd, hwe)
> + spin_basic_all(fd, hwe);
> +
> + igt_subtest("spin-all") {
> + xe_for_each_gt(fd, gt)
> + xe_for_each_hw_engine_class(class)
> + spin_all(fd, gt, class);
> + }
> +
> + igt_fixture {
> + xe_device_put(fd);
> + close(fd);
> + }
> +}
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-04 19:58 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-06-05 8:59 ` Kumar, Janga Rahul
2023-06-05 10:44 ` Zbigniew Kempczyński
1 sibling, 0 replies; 31+ messages in thread
From: Kumar, Janga Rahul @ 2023-06-05 8:59 UTC (permalink / raw)
To: Ch, Sai Gowtham, igt-dev, Kempczynski, Zbigniew, kamil.konieczny
> -----Original Message-----
> From: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
> Sent: 05 June 2023 01:28
> To: igt-dev@lists.freedesktop.org; Kempczynski, Zbigniew
> <zbigniew.kempczynski@intel.com>; Ch, Sai Gowtham
> <sai.gowtham.ch@intel.com>; Kumar, Janga Rahul
> <janga.rahul.kumar@intel.com>; kamil.konieczny@linux.intel.com
> Subject: [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise
> igt_spin_new for xe
>
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> xe_spin_batch test exercises igt_spin_new submissions with different
> combination.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 169 insertions(+)
> create mode 100644 tests/xe/xe_spin_batch.c
>
> diff --git a/tests/meson.build b/tests/meson.build index f71be1db..e794b75a
> 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -268,6 +268,7 @@ xe_progs = [
> 'xe_query',
> 'xe_vm',
> 'xe_waitfence',
> + 'xe_spin_batch',
> ]
>
> msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c new file mode
> 100644 index 00000000..ac531110
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,168 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +
> +/**
> + * TEST: Basic test for spin batch submissons.
> + *
> + * SUBTEST: spin-basic
> + * Description: Basic test to submit spin batch submissons on copy engine.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_basic(int fd)
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST:Test for spin batch submissons.
> + *
> + * SUBTEST: spin-batch
> + * Description: Create vm and engine of hwe class and run the spinner on it.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe) {
> + uint64_t ahnd;
> + unsigned int engine;
> + uint32_t vm;
> + igt_spin_t *spin;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_engine_create(fd, vm, hwe, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + xe_engine_destroy(fd, engine);
> + xe_vm_destroy(fd, vm);
> +
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Basic test for spin batch submission on all hwe.
> + *
> + * SUBTEST: spin-basic-all
> + * Description: Basic test which validates the functionality of spinner on all
> hwe.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +static void spin_basic_all(int fd, struct drm_xe_engine_class_instance
> +*hwe) {
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all (int fd, int gt, int class) {
> + uint64_t ahnd;
> + uint32_t engines[MAX_INSTANCE];
> + uint32_t vm[MAX_INSTANCE];
> + int i, num_placements = 0;
> + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> + igt_spin_t *spin[MAX_INSTANCE];
> + struct drm_xe_engine_class_instance *hwe;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + xe_for_each_hw_engine(fd, hwe) {
> + if (hwe->engine_class != class || hwe->gt_id != gt)
> + continue;
> + eci[num_placements++] = *hwe;
> + }
> + if (num_placements < 2)
> + return;
> +
> + for (i = 0; i < num_placements; i++) {
> + struct drm_xe_engine_create create;
> + vm[i] = xe_vm_create(fd, 0, 0);
> +
> + create.vm_id = vm[i];
> + create.width = 1;
> + create.num_placements = num_placements;
> + create.instances = to_user_pointer(eci);
> +
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> + &create), 0);
> + engines[i] = create.engine_id;
> + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i],
> .vm = vm[i]);
> + }
> +
> + for (i = 0; i < num_placements; i++) {
> + igt_assert(spin[i]);
> + igt_spin_free(fd, spin[i]);
> + }
> + put_ahnd(ahnd);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> + int gt, class;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> + }
> +
> + igt_subtest("spin-basic")
> + spin_basic(fd);
> +
> + igt_subtest("spin-batch")
> + xe_for_each_hw_engine(fd, hwe)
> + spin(fd, hwe);
> +
> + igt_subtest("spin-basic-all")
> + xe_for_each_hw_engine(fd, hwe)
> + spin_basic_all(fd, hwe);
> +
> + igt_subtest("spin-all") {
> + xe_for_each_gt(fd, gt)
> + xe_for_each_hw_engine_class(class)
> + spin_all(fd, gt, class);
> + }
> +
> + igt_fixture {
> + xe_device_put(fd);
> + close(fd);
> + }
> +}
> --
> 2.39.1
LGTM,
Acked-by: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-04 19:58 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
@ 2023-06-04 19:58 ` sai.gowtham.ch
2023-06-05 8:59 ` Kumar, Janga Rahul
2023-06-05 10:44 ` Zbigniew Kempczyński
0 siblings, 2 replies; 31+ messages in thread
From: sai.gowtham.ch @ 2023-06-04 19:58 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch, janga.rahul.kumar,
kamil.konieczny
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
xe_spin_batch test exercises igt_spin_new submissions with different
combination.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
2 files changed, 169 insertions(+)
create mode 100644 tests/xe/xe_spin_batch.c
diff --git a/tests/meson.build b/tests/meson.build
index f71be1db..e794b75a 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -268,6 +268,7 @@ xe_progs = [
'xe_query',
'xe_vm',
'xe_waitfence',
+ 'xe_spin_batch',
]
msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..ac531110
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,168 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+
+/**
+ * TEST: Basic test for spin batch submissons.
+ *
+ * SUBTEST: spin-basic
+ * Description: Basic test to submit spin batch submissons on copy engine.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_basic(int fd)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST:Test for spin batch submissons.
+ *
+ * SUBTEST: spin-batch
+ * Description: Create vm and engine of hwe class and run the spinner on it.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ unsigned int engine;
+ uint32_t vm;
+ igt_spin_t *spin;
+
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_engine_create(fd, vm, hwe, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ xe_engine_destroy(fd, engine);
+ xe_vm_destroy(fd, vm);
+
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Basic test for spin batch submission on all hwe.
+ *
+ * SUBTEST: spin-basic-all
+ * Description: Basic test which validates the functionality of spinner on all hwe.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+static void spin_basic_all(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all (int fd, int gt, int class)
+{
+ uint64_t ahnd;
+ uint32_t engines[MAX_INSTANCE];
+ uint32_t vm[MAX_INSTANCE];
+ int i, num_placements = 0;
+ struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+ igt_spin_t *spin[MAX_INSTANCE];
+ struct drm_xe_engine_class_instance *hwe;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ xe_for_each_hw_engine(fd, hwe) {
+ if (hwe->engine_class != class || hwe->gt_id != gt)
+ continue;
+ eci[num_placements++] = *hwe;
+ }
+ if (num_placements < 2)
+ return;
+
+ for (i = 0; i < num_placements; i++) {
+ struct drm_xe_engine_create create;
+ vm[i] = xe_vm_create(fd, 0, 0);
+
+ create.vm_id = vm[i];
+ create.width = 1;
+ create.num_placements = num_placements;
+ create.instances = to_user_pointer(eci);
+
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+ &create), 0);
+ engines[i] = create.engine_id;
+ spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm[i]);
+ }
+
+ for (i = 0; i < num_placements; i++) {
+ igt_assert(spin[i]);
+ igt_spin_free(fd, spin[i]);
+ }
+ put_ahnd(ahnd);
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+ int gt, class;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("spin-basic")
+ spin_basic(fd);
+
+ igt_subtest("spin-batch")
+ xe_for_each_hw_engine(fd, hwe)
+ spin(fd, hwe);
+
+ igt_subtest("spin-basic-all")
+ xe_for_each_hw_engine(fd, hwe)
+ spin_basic_all(fd, hwe);
+
+ igt_subtest("spin-all") {
+ xe_for_each_gt(fd, gt)
+ xe_for_each_hw_engine_class(class)
+ spin_all(fd, gt, class);
+ }
+
+ igt_fixture {
+ xe_device_put(fd);
+ close(fd);
+ }
+}
--
2.39.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe
2023-06-04 19:16 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
@ 2023-06-04 19:16 ` sai.gowtham.ch
0 siblings, 0 replies; 31+ messages in thread
From: sai.gowtham.ch @ 2023-06-04 19:16 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch, janga.rahul.kumar,
kamil.konieczny
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
xe_spin_batch test exercises igt_spin_new submissions with different
combinations.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
2 files changed, 169 insertions(+)
create mode 100644 tests/xe/xe_spin_batch.c
diff --git a/tests/meson.build b/tests/meson.build
index f71be1db..e794b75a 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -268,6 +268,7 @@ xe_progs = [
'xe_query',
'xe_vm',
'xe_waitfence',
+ 'xe_spin_batch',
]
msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..ac531110
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,168 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+
+/**
+ * TEST: Basic test for spin batch submissons.
+ *
+ * SUBTEST: spin-basic
+ * Description: Basic test to submit spin batch submissons on copy engine.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_basic(int fd)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST:Test for spin batch submissons.
+ *
+ * SUBTEST: spin-batch
+ * Description: Create vm and engine of hwe class and run the spinner on it.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ unsigned int engine;
+ uint32_t vm;
+ igt_spin_t *spin;
+
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_engine_create(fd, vm, hwe, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ spin = igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ xe_engine_destroy(fd, engine);
+ xe_vm_destroy(fd, vm);
+
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Basic test for spin batch submission on all hwe.
+ *
+ * SUBTEST: spin-basic-all
+ * Description: Basic test which validates the functionality of spinner on all hwe.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+static void spin_basic_all(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all (int fd, int gt, int class)
+{
+ uint64_t ahnd;
+ uint32_t engines[MAX_INSTANCE];
+ uint32_t vm[MAX_INSTANCE];
+ int i, num_placements = 0;
+ struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+ igt_spin_t *spin[MAX_INSTANCE];
+ struct drm_xe_engine_class_instance *hwe;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ xe_for_each_hw_engine(fd, hwe) {
+ if (hwe->engine_class != class || hwe->gt_id != gt)
+ continue;
+ eci[num_placements++] = *hwe;
+ }
+ if (num_placements < 2)
+ return;
+
+ for (i = 0; i < num_placements; i++) {
+ struct drm_xe_engine_create create;
+ vm[i] = xe_vm_create(fd, 0, 0);
+
+ create.vm_id = vm[i];
+ create.width = 1;
+ create.num_placements = num_placements;
+ create.instances = to_user_pointer(eci);
+
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+ &create), 0);
+ engines[i] = create.engine_id;
+ spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm[i]);
+ }
+
+ for (i = 0; i < num_placements; i++) {
+ igt_assert(spin[i]);
+ igt_spin_free(fd, spin[i]);
+ }
+ put_ahnd(ahnd);
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+ int gt, class;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("spin-basic")
+ spin_basic(fd);
+
+ igt_subtest("spin-batch")
+ xe_for_each_hw_engine(fd, hwe)
+ spin(fd, hwe);
+
+ igt_subtest("spin-basic-all")
+ xe_for_each_hw_engine(fd, hwe)
+ spin_basic_all(fd, hwe);
+
+ igt_subtest("spin-all") {
+ xe_for_each_gt(fd, gt)
+ xe_for_each_hw_engine_class(class)
+ spin_all(fd, gt, class);
+ }
+
+ igt_fixture {
+ xe_device_put(fd);
+ close(fd);
+ }
+}
--
2.39.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-30 10:08 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-05-31 5:55 ` Zbigniew Kempczyński
0 siblings, 0 replies; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-05-31 5:55 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
On Tue, May 30, 2023 at 03:38:05PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> xe_spin_batch test exercises igt_spin_new submissions with different
> combinations.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 169 insertions(+)
> create mode 100644 tests/xe/xe_spin_batch.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index f71be1db..e794b75a 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -268,6 +268,7 @@ xe_progs = [
> 'xe_query',
> 'xe_vm',
> 'xe_waitfence',
> + 'xe_spin_batch',
> ]
>
> msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..55207eff
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,168 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +
> +/**
> + * TEST: Basic test for spin batch submissons.
> + *
> + * SUBTEST: spin-basic
> + * Description: Basic test to submit spin batch submissons.
Add information to which engine it will submit the spinner.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_basic(int fd)
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd);
Why not just igt_spin_new()?
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
Rest is ok.
> +
> +/**
> + * TEST:Test for spin batch submissons.
^ space.
> + *
> + * SUBTEST: spin-batch
> + * Description: Test to submit spin batch with engines and vm.
Maybe: Create vm and engine of hwe class and run the spinner on it.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + unsigned int engine;
> + uint32_t vm;
> + igt_spin_t *spin;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_engine_create(fd, vm, hwe, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + spin = __igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + xe_engine_destroy(fd, engine);
> + xe_vm_destroy(fd, vm);
> +
> + put_ahnd(ahnd);
> +}
Test itself looks good.
> +
> +/**
> + * TEST: Basic test for spin batch submission on all hwe.
> + *
> + * SUBTEST: spin-basic-all
> + * Description: Basic test which validates the functionality of spinner on all hwe.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +static void spin_basic_all(int fd, struct drm_xe_engine_class_instance *hwe)
^ ---- if for all what hwe is for here?
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
I would expect:
spin = igt_spin_new(fd, .ahnd = ahnd, .engine = ALL_ENGINES);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
^ what ! is for?
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all (int fd, int gt, int class)
^ unnecessary space
> +{
> + uint64_t ahnd;
> + uint32_t engines[MAX_INSTANCE];
> + uint32_t vm[MAX_INSTANCE];
You may use single vm here. Let's see how spinners will share
same address space.
> + int i, num_placements = 0;
> + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> + igt_spin_t *spin[MAX_INSTANCE];
> + struct drm_xe_engine_class_instance *hwe;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + xe_for_each_hw_engine(fd, hwe) {
> + if (hwe->engine_class != class || hwe->gt_id != gt)
> + continue;
> + eci[num_placements++] = *hwe;
> + }
What's your intention here? To run spinners on dedicated gt
and some class?
--
Zbigniew
> + if (num_placements < 2)
> + return;
> +
> + for (i = 0; i < num_placements; i++) {
> + struct drm_xe_engine_create create;
> + vm[i] = xe_vm_create(fd, 0, 0);
> +
> + create.vm_id = vm[i];
> + create.width = 1;
> + create.num_placements = num_placements;
> + create.instances = to_user_pointer(eci);
> +
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> + &create), 0);
> + engines[i] = create.engine_id;
> + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm[i]);
> + }
> +
> + for (i = 0; i < num_placements; i++) {
> + igt_assert(spin[i]);
> + igt_spin_free(fd, spin[i]);
> + }
> + put_ahnd(ahnd);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> + int gt, class;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> + }
> +
> + igt_subtest("spin-basic")
> + spin_basic(fd);
> +
> + igt_subtest("spin-batch")
> + xe_for_each_hw_engine(fd, hwe)
> + spin(fd, hwe);
> +
> + igt_subtest("spin-basic-all")
> + xe_for_each_hw_engine(fd, hwe)
> + spin_basic_all(fd, hwe);
> +
> + igt_subtest("spin-all") {
> + xe_for_each_gt(fd, gt)
> + xe_for_each_hw_engine_class(class)
> + spin_all(fd, gt, class);
> + }
> +
> + igt_fixture {
> + xe_device_put(fd);
> + close(fd);
> + }
> +}
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-29 11:02 ` Ch, Sai Gowtham
@ 2023-05-30 19:12 ` Zbigniew Kempczyński
0 siblings, 0 replies; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-05-30 19:12 UTC (permalink / raw)
To: Ch, Sai Gowtham; +Cc: igt-dev
On Mon, May 29, 2023 at 01:02:53PM +0200, Ch, Sai Gowtham wrote:
>
>
> > -----Original Message-----
> > From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
> > Sent: Monday, May 29, 2023 11:27 AM
> > To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
> > Cc: igt-dev@lists.freedesktop.org
> > Subject: Re: [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise
> > igt_spin_new for xe.
> >
> > On Thu, May 25, 2023 at 11:25:19AM +0530, sai.gowtham.ch@intel.com wrote:
> > > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > >
> > > xe_spin_batch test exercises basic igt_spin_new submissions and and
> > > with all engines.
> > >
> > > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > > ---
> > > tests/meson.build | 1 +
> > > tests/xe/xe_spin_batch.c | 138
> > > +++++++++++++++++++++++++++++++++++++++
> > > 2 files changed, 139 insertions(+)
> > > create mode 100644 tests/xe/xe_spin_batch.c
> > >
> > > diff --git a/tests/meson.build b/tests/meson.build index
> > > f71be1db..e794b75a 100644
> > > --- a/tests/meson.build
> > > +++ b/tests/meson.build
> > > @@ -268,6 +268,7 @@ xe_progs = [
> > > 'xe_query',
> > > 'xe_vm',
> > > 'xe_waitfence',
> > > + 'xe_spin_batch',
> > > ]
> > >
> > > msm_progs = [
> > > diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c new
> > > file mode 100644 index 00000000..1b216199
> > > --- /dev/null
> > > +++ b/tests/xe/xe_spin_batch.c
> > > @@ -0,0 +1,138 @@
> > > +#include "igt.h"
> > > +#include "lib/intel_reg.h"
> > > +#include "xe_drm.h"
> > > +#include "xe/xe_ioctl.h"
> > > +#include "xe/xe_query.h"
> > > +
> > > +#define MAX_INSTANCE 9
> > > +/**
> > > + * TEST:Test for spin batch submissons.
> > > + *
> > > + * SUBTEST: spin-batch
> > > + * Description: Test to submit spin batch with engines and vm.
> > > + * Run type: FULL
> > > + * TODO: change ``'Run type' == FULL`` to a better category
> > > + *
> > > + */
> > > +
> > > +static void spin(int fd, struct drm_xe_engine_class_instance *hwe) {
> > > + uint64_t ahnd;
> > > + unsigned int engine;
> > > + uint32_t vm;
> > > + igt_spin_t *spin;
> > > +
> > > + vm = xe_vm_create(fd, 0, 0);
> > > + engine = xe_engine_create(fd, vm, hwe, 0);
> > > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > > +
> > > + spin = __igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> > > + igt_assert(spin);
> > > +
> > > + igt_spin_free(fd, spin);
> >
> > You shouldn't imo destroy engine/vm inside igt_spin_free(). Caller is the owner
> > and they should stay intact.
> >
> > If instead .engine you'll pass .hwe you may create engine on top of vm (if
> > passed, if not create new one) and destroy in igt_spin_free().
> >
> > Resume: track the ownershipping.
> I'm handling this in igt_spin_free itself, if you look at the igt_spin_free code that I've sent for review I'm checking if it's passed from the igt test or
> Is it created inside the xe_spin_create, I'm not destroying engine and vm when it's passed from igt test.
So in this case you should destroy it in the test, otherwise it will
dangle when test is done.
--
Zbigniew
> >
> > > + put_ahnd(ahnd);
> > > +}
> > > +
> > > +/**
> > > + * TEST: Basic test for spin batch submission.
> > > + *
> > > + * SUBTEST: spin-basic
> > > + * Description: Basic test which validates the functionality of spinner.
> > > + * Run type: FULL
> > > + * TODO: change ``'Run type' == FULL`` to a better category
> > > + *
> > > + */
> > > +static void spin_basic(int fd, struct drm_xe_engine_class_instance
> > > +*hwe) {
> > > + uint64_t ahnd;
> > > + igt_spin_t *spin;
> > > +
> > > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > > + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
> > > + igt_assert(spin);
> > > +
> > > + igt_spin_free(fd, spin);
> > > + put_ahnd(ahnd);
> > > +}
> > > +
> > > +/**
> > > + * TEST: Test for spin batch submissions.
> > > + * SUBTEST: spin-all
> > > + * Description: Spinner test to run on all the engines!
> > > + * Run type: FULL
> > > + * TODO: change ``'Run type' == FULL`` to a better category
> > > + *
> > > + */
> > > +
> > > +static void spin_all (int fd, int gt, int class) {
> > > + uint64_t ahnd;
> > > + uint32_t engines[MAX_INSTANCE];
> > > + uint32_t vm[MAX_INSTANCE];
> > > + int i, num_placements = 0;
> > > + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> > > + igt_spin_t *spin[MAX_INSTANCE];
> > > + struct drm_xe_engine_class_instance *hwe;
> > > +
> > > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > > +
> > > + xe_for_each_hw_engine(fd, hwe) {
> > > + if (hwe->engine_class != class || hwe->gt_id != gt)
> > > + continue;
> > > + eci[num_placements++] = *hwe;
> > > + }
> > > + if (num_placements < 2)
> > > + return;
> > > +
> > > + for (i = 0; i < num_placements; i++) {
> > > + struct drm_xe_engine_create create;
> > > + vm[i] = xe_vm_create(fd, 0, 0);
> > > +
> > > + create.vm_id = vm[i];
> > > + create.width = 1;
> > > + create.num_placements = num_placements;
> > > + create.instances = to_user_pointer(eci);
> > > +
> > > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> > > + &create), 0);
> > > + engines[i] = create.engine_id;
> > > + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i],
> > .vm = vm[i]);
> > > + }
> > > +
> > > + for (i = 0; i < num_placements; i++) {
> > > + igt_assert(spin[i]);
> > > + igt_spin_free(fd, spin[i]);
> > > + }
> > > + put_ahnd(ahnd);
> > > +}
> > > +
> > > +igt_main
> > > +{
> > > + struct drm_xe_engine_class_instance *hwe;
> > > + int fd;
> > > + int gt, class;
> > > +
> > > + igt_fixture {
> > > + fd = drm_open_driver(DRIVER_XE);
> > > + xe_device_get(fd);
> > > + }
> > > +
> > > + igt_subtest("spin-batch")
> > > + xe_for_each_hw_engine(fd, hwe)
> > > + spin(fd, hwe);
> >
> > Test both variants: with engine/vm created in the test and passed via .engine +
> > .vm field and with passing .hwe only. Add also support for ALL_ENGINES flag.
> >
> I think spin-batch already covers that, it passes both engine and vm to igt_spin_new which are created in the test.
> And spin-basic passes only .hwe to igt_spin_new.
>
> Thanks,
> Gowtham
> > --
> > Zbigniew
> >
> > > +
> > > + igt_subtest("spin-basic")
> > > + xe_for_each_hw_engine(fd, hwe)
> > > + spin_basic(fd, hwe);
> > > +
> > > + igt_subtest("spin-all") {
> > > + xe_for_each_gt(fd, gt)
> > > + xe_for_each_hw_engine_class(class)
> > > + spin_all(fd, gt, class);
> > > + }
> > > +
> > > + igt_fixture {
> > > + xe_device_put(fd);
> > > + close(fd);
> > > + }
> > > +}
> > > --
> > > 2.39.1
> > >
^ permalink raw reply [flat|nested] 31+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-30 10:08 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
@ 2023-05-30 10:08 ` sai.gowtham.ch
2023-05-31 5:55 ` Zbigniew Kempczyński
0 siblings, 1 reply; 31+ messages in thread
From: sai.gowtham.ch @ 2023-05-30 10:08 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
xe_spin_batch test exercises igt_spin_new submissions with different
combinations.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 168 +++++++++++++++++++++++++++++++++++++++
2 files changed, 169 insertions(+)
create mode 100644 tests/xe/xe_spin_batch.c
diff --git a/tests/meson.build b/tests/meson.build
index f71be1db..e794b75a 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -268,6 +268,7 @@ xe_progs = [
'xe_query',
'xe_vm',
'xe_waitfence',
+ 'xe_spin_batch',
]
msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..55207eff
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,168 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+
+/**
+ * TEST: Basic test for spin batch submissons.
+ *
+ * SUBTEST: spin-basic
+ * Description: Basic test to submit spin batch submissons.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_basic(int fd)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST:Test for spin batch submissons.
+ *
+ * SUBTEST: spin-batch
+ * Description: Test to submit spin batch with engines and vm.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ unsigned int engine;
+ uint32_t vm;
+ igt_spin_t *spin;
+
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_engine_create(fd, vm, hwe, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ spin = __igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ xe_engine_destroy(fd, engine);
+ xe_vm_destroy(fd, vm);
+
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Basic test for spin batch submission on all hwe.
+ *
+ * SUBTEST: spin-basic-all
+ * Description: Basic test which validates the functionality of spinner on all hwe.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+static void spin_basic_all(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all (int fd, int gt, int class)
+{
+ uint64_t ahnd;
+ uint32_t engines[MAX_INSTANCE];
+ uint32_t vm[MAX_INSTANCE];
+ int i, num_placements = 0;
+ struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+ igt_spin_t *spin[MAX_INSTANCE];
+ struct drm_xe_engine_class_instance *hwe;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ xe_for_each_hw_engine(fd, hwe) {
+ if (hwe->engine_class != class || hwe->gt_id != gt)
+ continue;
+ eci[num_placements++] = *hwe;
+ }
+ if (num_placements < 2)
+ return;
+
+ for (i = 0; i < num_placements; i++) {
+ struct drm_xe_engine_create create;
+ vm[i] = xe_vm_create(fd, 0, 0);
+
+ create.vm_id = vm[i];
+ create.width = 1;
+ create.num_placements = num_placements;
+ create.instances = to_user_pointer(eci);
+
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+ &create), 0);
+ engines[i] = create.engine_id;
+ spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm[i]);
+ }
+
+ for (i = 0; i < num_placements; i++) {
+ igt_assert(spin[i]);
+ igt_spin_free(fd, spin[i]);
+ }
+ put_ahnd(ahnd);
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+ int gt, class;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("spin-basic")
+ spin_basic(fd);
+
+ igt_subtest("spin-batch")
+ xe_for_each_hw_engine(fd, hwe)
+ spin(fd, hwe);
+
+ igt_subtest("spin-basic-all")
+ xe_for_each_hw_engine(fd, hwe)
+ spin_basic_all(fd, hwe);
+
+ igt_subtest("spin-all") {
+ xe_for_each_gt(fd, gt)
+ xe_for_each_hw_engine_class(class)
+ spin_all(fd, gt, class);
+ }
+
+ igt_fixture {
+ xe_device_put(fd);
+ close(fd);
+ }
+}
--
2.39.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-29 5:57 ` Zbigniew Kempczyński
@ 2023-05-29 11:02 ` Ch, Sai Gowtham
2023-05-30 19:12 ` Zbigniew Kempczyński
0 siblings, 1 reply; 31+ messages in thread
From: Ch, Sai Gowtham @ 2023-05-29 11:02 UTC (permalink / raw)
To: Kempczynski, Zbigniew; +Cc: igt-dev
> -----Original Message-----
> From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
> Sent: Monday, May 29, 2023 11:27 AM
> To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
> Cc: igt-dev@lists.freedesktop.org
> Subject: Re: [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise
> igt_spin_new for xe.
>
> On Thu, May 25, 2023 at 11:25:19AM +0530, sai.gowtham.ch@intel.com wrote:
> > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> >
> > xe_spin_batch test exercises basic igt_spin_new submissions and and
> > with all engines.
> >
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > ---
> > tests/meson.build | 1 +
> > tests/xe/xe_spin_batch.c | 138
> > +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 139 insertions(+)
> > create mode 100644 tests/xe/xe_spin_batch.c
> >
> > diff --git a/tests/meson.build b/tests/meson.build index
> > f71be1db..e794b75a 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -268,6 +268,7 @@ xe_progs = [
> > 'xe_query',
> > 'xe_vm',
> > 'xe_waitfence',
> > + 'xe_spin_batch',
> > ]
> >
> > msm_progs = [
> > diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c new
> > file mode 100644 index 00000000..1b216199
> > --- /dev/null
> > +++ b/tests/xe/xe_spin_batch.c
> > @@ -0,0 +1,138 @@
> > +#include "igt.h"
> > +#include "lib/intel_reg.h"
> > +#include "xe_drm.h"
> > +#include "xe/xe_ioctl.h"
> > +#include "xe/xe_query.h"
> > +
> > +#define MAX_INSTANCE 9
> > +/**
> > + * TEST:Test for spin batch submissons.
> > + *
> > + * SUBTEST: spin-batch
> > + * Description: Test to submit spin batch with engines and vm.
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin(int fd, struct drm_xe_engine_class_instance *hwe) {
> > + uint64_t ahnd;
> > + unsigned int engine;
> > + uint32_t vm;
> > + igt_spin_t *spin;
> > +
> > + vm = xe_vm_create(fd, 0, 0);
> > + engine = xe_engine_create(fd, vm, hwe, 0);
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + spin = __igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> > + igt_assert(spin);
> > +
> > + igt_spin_free(fd, spin);
>
> You shouldn't imo destroy engine/vm inside igt_spin_free(). Caller is the owner
> and they should stay intact.
>
> If instead .engine you'll pass .hwe you may create engine on top of vm (if
> passed, if not create new one) and destroy in igt_spin_free().
>
> Resume: track the ownershipping.
I'm handling this in igt_spin_free itself, if you look at the igt_spin_free code that I've sent for review I'm checking if it's passed from the igt test or
Is it created inside the xe_spin_create, I'm not destroying engine and vm when it's passed from igt test.
>
> > + put_ahnd(ahnd);
> > +}
> > +
> > +/**
> > + * TEST: Basic test for spin batch submission.
> > + *
> > + * SUBTEST: spin-basic
> > + * Description: Basic test which validates the functionality of spinner.
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +static void spin_basic(int fd, struct drm_xe_engine_class_instance
> > +*hwe) {
> > + uint64_t ahnd;
> > + igt_spin_t *spin;
> > +
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
> > + igt_assert(spin);
> > +
> > + igt_spin_free(fd, spin);
> > + put_ahnd(ahnd);
> > +}
> > +
> > +/**
> > + * TEST: Test for spin batch submissions.
> > + * SUBTEST: spin-all
> > + * Description: Spinner test to run on all the engines!
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin_all (int fd, int gt, int class) {
> > + uint64_t ahnd;
> > + uint32_t engines[MAX_INSTANCE];
> > + uint32_t vm[MAX_INSTANCE];
> > + int i, num_placements = 0;
> > + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> > + igt_spin_t *spin[MAX_INSTANCE];
> > + struct drm_xe_engine_class_instance *hwe;
> > +
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + xe_for_each_hw_engine(fd, hwe) {
> > + if (hwe->engine_class != class || hwe->gt_id != gt)
> > + continue;
> > + eci[num_placements++] = *hwe;
> > + }
> > + if (num_placements < 2)
> > + return;
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + struct drm_xe_engine_create create;
> > + vm[i] = xe_vm_create(fd, 0, 0);
> > +
> > + create.vm_id = vm[i];
> > + create.width = 1;
> > + create.num_placements = num_placements;
> > + create.instances = to_user_pointer(eci);
> > +
> > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> > + &create), 0);
> > + engines[i] = create.engine_id;
> > + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i],
> .vm = vm[i]);
> > + }
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + igt_assert(spin[i]);
> > + igt_spin_free(fd, spin[i]);
> > + }
> > + put_ahnd(ahnd);
> > +}
> > +
> > +igt_main
> > +{
> > + struct drm_xe_engine_class_instance *hwe;
> > + int fd;
> > + int gt, class;
> > +
> > + igt_fixture {
> > + fd = drm_open_driver(DRIVER_XE);
> > + xe_device_get(fd);
> > + }
> > +
> > + igt_subtest("spin-batch")
> > + xe_for_each_hw_engine(fd, hwe)
> > + spin(fd, hwe);
>
> Test both variants: with engine/vm created in the test and passed via .engine +
> .vm field and with passing .hwe only. Add also support for ALL_ENGINES flag.
>
I think spin-batch already covers that, it passes both engine and vm to igt_spin_new which are created in the test.
And spin-basic passes only .hwe to igt_spin_new.
Thanks,
Gowtham
> --
> Zbigniew
>
> > +
> > + igt_subtest("spin-basic")
> > + xe_for_each_hw_engine(fd, hwe)
> > + spin_basic(fd, hwe);
> > +
> > + igt_subtest("spin-all") {
> > + xe_for_each_gt(fd, gt)
> > + xe_for_each_hw_engine_class(class)
> > + spin_all(fd, gt, class);
> > + }
> > +
> > + igt_fixture {
> > + xe_device_put(fd);
> > + close(fd);
> > + }
> > +}
> > --
> > 2.39.1
> >
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-25 5:55 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-05-29 5:57 ` Zbigniew Kempczyński
2023-05-29 11:02 ` Ch, Sai Gowtham
0 siblings, 1 reply; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-05-29 5:57 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
On Thu, May 25, 2023 at 11:25:19AM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> xe_spin_batch test exercises basic igt_spin_new submissions and
> and with all engines.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_spin_batch.c | 138 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 139 insertions(+)
> create mode 100644 tests/xe/xe_spin_batch.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index f71be1db..e794b75a 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -268,6 +268,7 @@ xe_progs = [
> 'xe_query',
> 'xe_vm',
> 'xe_waitfence',
> + 'xe_spin_batch',
> ]
>
> msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..1b216199
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,138 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +/**
> + * TEST:Test for spin batch submissons.
> + *
> + * SUBTEST: spin-batch
> + * Description: Test to submit spin batch with engines and vm.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + unsigned int engine;
> + uint32_t vm;
> + igt_spin_t *spin;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_engine_create(fd, vm, hwe, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + spin = __igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
You shouldn't imo destroy engine/vm inside igt_spin_free(). Caller
is the owner and they should stay intact.
If instead .engine you'll pass .hwe you may create engine on top
of vm (if passed, if not create new one) and destroy in igt_spin_free().
Resume: track the ownershipping.
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Basic test for spin batch submission.
> + *
> + * SUBTEST: spin-basic
> + * Description: Basic test which validates the functionality of spinner.
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +static void spin_basic(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + igt_spin_t *spin;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all (int fd, int gt, int class)
> +{
> + uint64_t ahnd;
> + uint32_t engines[MAX_INSTANCE];
> + uint32_t vm[MAX_INSTANCE];
> + int i, num_placements = 0;
> + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> + igt_spin_t *spin[MAX_INSTANCE];
> + struct drm_xe_engine_class_instance *hwe;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + xe_for_each_hw_engine(fd, hwe) {
> + if (hwe->engine_class != class || hwe->gt_id != gt)
> + continue;
> + eci[num_placements++] = *hwe;
> + }
> + if (num_placements < 2)
> + return;
> +
> + for (i = 0; i < num_placements; i++) {
> + struct drm_xe_engine_create create;
> + vm[i] = xe_vm_create(fd, 0, 0);
> +
> + create.vm_id = vm[i];
> + create.width = 1;
> + create.num_placements = num_placements;
> + create.instances = to_user_pointer(eci);
> +
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> + &create), 0);
> + engines[i] = create.engine_id;
> + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm[i]);
> + }
> +
> + for (i = 0; i < num_placements; i++) {
> + igt_assert(spin[i]);
> + igt_spin_free(fd, spin[i]);
> + }
> + put_ahnd(ahnd);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> + int gt, class;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> + }
> +
> + igt_subtest("spin-batch")
> + xe_for_each_hw_engine(fd, hwe)
> + spin(fd, hwe);
Test both variants: with engine/vm created in the test and passed
via .engine + .vm field and with passing .hwe only. Add also
support for ALL_ENGINES flag.
--
Zbigniew
> +
> + igt_subtest("spin-basic")
> + xe_for_each_hw_engine(fd, hwe)
> + spin_basic(fd, hwe);
> +
> + igt_subtest("spin-all") {
> + xe_for_each_gt(fd, gt)
> + xe_for_each_hw_engine_class(class)
> + spin_all(fd, gt, class);
> + }
> +
> + igt_fixture {
> + xe_device_put(fd);
> + close(fd);
> + }
> +}
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-25 5:55 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
@ 2023-05-25 5:55 ` sai.gowtham.ch
2023-05-29 5:57 ` Zbigniew Kempczyński
0 siblings, 1 reply; 31+ messages in thread
From: sai.gowtham.ch @ 2023-05-25 5:55 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
xe_spin_batch test exercises basic igt_spin_new submissions and
and with all engines.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 138 +++++++++++++++++++++++++++++++++++++++
2 files changed, 139 insertions(+)
create mode 100644 tests/xe/xe_spin_batch.c
diff --git a/tests/meson.build b/tests/meson.build
index f71be1db..e794b75a 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -268,6 +268,7 @@ xe_progs = [
'xe_query',
'xe_vm',
'xe_waitfence',
+ 'xe_spin_batch',
]
msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..1b216199
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,138 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+/**
+ * TEST:Test for spin batch submissons.
+ *
+ * SUBTEST: spin-batch
+ * Description: Test to submit spin batch with engines and vm.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ unsigned int engine;
+ uint32_t vm;
+ igt_spin_t *spin;
+
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_engine_create(fd, vm, hwe, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ spin = __igt_spin_new(fd, .ahnd = ahnd, .engine = engine, .vm = vm);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Basic test for spin batch submission.
+ *
+ * SUBTEST: spin-basic
+ * Description: Basic test which validates the functionality of spinner.
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+static void spin_basic(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ igt_spin_t *spin;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+ spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all (int fd, int gt, int class)
+{
+ uint64_t ahnd;
+ uint32_t engines[MAX_INSTANCE];
+ uint32_t vm[MAX_INSTANCE];
+ int i, num_placements = 0;
+ struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+ igt_spin_t *spin[MAX_INSTANCE];
+ struct drm_xe_engine_class_instance *hwe;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ xe_for_each_hw_engine(fd, hwe) {
+ if (hwe->engine_class != class || hwe->gt_id != gt)
+ continue;
+ eci[num_placements++] = *hwe;
+ }
+ if (num_placements < 2)
+ return;
+
+ for (i = 0; i < num_placements; i++) {
+ struct drm_xe_engine_create create;
+ vm[i] = xe_vm_create(fd, 0, 0);
+
+ create.vm_id = vm[i];
+ create.width = 1;
+ create.num_placements = num_placements;
+ create.instances = to_user_pointer(eci);
+
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+ &create), 0);
+ engines[i] = create.engine_id;
+ spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .engine = engines[i], .vm = vm[i]);
+ }
+
+ for (i = 0; i < num_placements; i++) {
+ igt_assert(spin[i]);
+ igt_spin_free(fd, spin[i]);
+ }
+ put_ahnd(ahnd);
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+ int gt, class;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("spin-batch")
+ xe_for_each_hw_engine(fd, hwe)
+ spin(fd, hwe);
+
+ igt_subtest("spin-basic")
+ xe_for_each_hw_engine(fd, hwe)
+ spin_basic(fd, hwe);
+
+ igt_subtest("spin-all") {
+ xe_for_each_gt(fd, gt)
+ xe_for_each_hw_engine_class(class)
+ spin_all(fd, gt, class);
+ }
+
+ igt_fixture {
+ xe_device_put(fd);
+ close(fd);
+ }
+}
--
2.39.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-24 7:11 ` Modem, Bhanuprakash
2023-05-24 19:47 ` Ch, Sai Gowtham
@ 2023-05-25 5:46 ` Zbigniew Kempczyński
1 sibling, 0 replies; 31+ messages in thread
From: Zbigniew Kempczyński @ 2023-05-25 5:46 UTC (permalink / raw)
To: Modem, Bhanuprakash; +Cc: igt-dev, sai.gowtham.ch
On Wed, May 24, 2023 at 12:41:09PM +0530, Modem, Bhanuprakash wrote:
>
> On Mon-22-05-2023 06:06 pm, sai.gowtham.ch@intel.com wrote:
> > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> >
> > xe_spin_batch test exercises basic igt_spin_new submissions and
> > and with all engines.
> >
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > ---
> > tests/meson.build | 1 +
> > tests/xe/xe_spin_batch.c | 113 +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 114 insertions(+)
> > create mode 100644 tests/xe/xe_spin_batch.c
> >
> > diff --git a/tests/meson.build b/tests/meson.build
> > index f71be1db..e794b75a 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -268,6 +268,7 @@ xe_progs = [
> > 'xe_query',
> > 'xe_vm',
> > 'xe_waitfence',
> > + 'xe_spin_batch',
> > ]
> > msm_progs = [
> > diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> > new file mode 100644
> > index 00000000..55fbca92
> > --- /dev/null
> > +++ b/tests/xe/xe_spin_batch.c
> > @@ -0,0 +1,113 @@
> > +#include "igt.h"
> > +#include "lib/intel_reg.h"
> > +#include "xe_drm.h"
> > +#include "xe/xe_ioctl.h"
> > +#include "xe/xe_query.h"
> > +
> > +#define MAX_INSTANCE 9
> > +/**
> > + * TEST: Basic test for spin batch submission.
> > + *
> > + * SUBTEST: spin-batch
> > + * Description: Simple test!
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> > +{
> > + uint64_t ahnd;
> > + unsigned int engine;
> > + uint32_t vm;
> > + igt_spin_t *spin;
> > +
> > + vm = xe_vm_create(fd, 0, 0);
> > + engine = xe_engine_create(fd, vm, hwe, 0);
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe, .engine = engine, .vm = vm);
> > + igt_assert(spin);
> > +
> > + igt_spin_free(fd, spin);
> > + put_ahnd(ahnd);
> > +}
> > +
> > +/**
> > + * TEST: Test for spin batch submissions.
> > + * SUBTEST: spin-all
> > + * Description: Spinner test to run on all the engines!
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin_all (int fd, int gt, int class)
> > +{
> > + uint64_t ahnd;
> > + uint32_t engines[MAX_INSTANCE];
> > + uint32_t vm[MAX_INSTANCE];
> > + int i, num_placements = 0;
> > + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> > + igt_spin_t *spin[MAX_INSTANCE];
> > + struct drm_xe_engine_class_instance *hwe;
> > +
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + xe_for_each_hw_engine(fd, hwe) {
> > + if (hwe->engine_class != class || hwe->gt_id != gt)
> > + continue;
> > + eci[num_placements++] = *hwe;
> > + }
> > + if (num_placements < 2)
> > + return;
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + struct drm_xe_engine_create create;
> > + vm[i] = xe_vm_create(fd, 0, 0);
> > +
> > + create.vm_id = vm[i];
> > + create.width = 1;
> > + create.num_placements = num_placements;
> > + create.instances = to_user_pointer(eci);
> > +
> > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> > + &create), 0);
> > + engines[i] = create.engine_id;
> > + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .hwe = eci, .engine = engines[i], .vm = vm[i]);
> > + }
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + igt_assert(spin[i]);
> > + igt_spin_free(fd, spin[i]);
> > + }
> > +}
> > +
> > +igt_main
> > +{
> > + struct drm_xe_engine_class_instance *hwe;
> > + int fd;
> > + int gt, class;
> > +
> > + igt_fixture {
> > + fd = drm_open_driver(DRIVER_XE);
> > + xe_device_get(fd);
> > + }
> > +
> > + igt_subtest("spin-batch")
> > + xe_for_each_hw_engine(fd, hwe)
>
> I think, this loop should be handled inside the xe spin helper (like
> spin_create()). Since KMS also trying to use the same helper & really don't
> care about hardware engines.
You mean to mimic ALL_ENGINES flag? Makes sense for me. Without flag we
may try to pick blitter as it should work on all platforms (if it won't
we may pick first engine from xe engines exposed to userspace).
--
Zbigniew
>
> - Bhanu
>
> > + spin(fd, hwe);
> > +
> > + igt_subtest("spin-all") {
> > + xe_for_each_gt(fd, gt)
> > + xe_for_each_hw_engine_class(class)
> > + spin_all(fd, gt, class);
> > + }
> > +
> > + igt_fixture {
> > + xe_device_put(fd);
> > + close(fd);
> > + }
> > +}
> > +
> > +
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-24 7:11 ` Modem, Bhanuprakash
@ 2023-05-24 19:47 ` Ch, Sai Gowtham
2023-05-25 5:46 ` Zbigniew Kempczyński
1 sibling, 0 replies; 31+ messages in thread
From: Ch, Sai Gowtham @ 2023-05-24 19:47 UTC (permalink / raw)
To: Modem, Bhanuprakash, igt-dev, Kempczynski, Zbigniew
> -----Original Message-----
> From: Modem, Bhanuprakash <bhanuprakash.modem@intel.com>
> Sent: Wednesday, May 24, 2023 12:41 PM
> To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; igt-
> dev@lists.freedesktop.org; Kempczynski, Zbigniew
> <zbigniew.kempczynski@intel.com>
> Subject: Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to
> exercise igt_spin_new for xe.
>
>
> On Mon-22-05-2023 06:06 pm, sai.gowtham.ch@intel.com wrote:
> > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> >
> > xe_spin_batch test exercises basic igt_spin_new submissions and and
> > with all engines.
> >
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > ---
> > tests/meson.build | 1 +
> > tests/xe/xe_spin_batch.c | 113
> +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 114 insertions(+)
> > create mode 100644 tests/xe/xe_spin_batch.c
> >
> > diff --git a/tests/meson.build b/tests/meson.build index
> > f71be1db..e794b75a 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -268,6 +268,7 @@ xe_progs = [
> > 'xe_query',
> > 'xe_vm',
> > 'xe_waitfence',
> > + 'xe_spin_batch',
> > ]
> >
> > msm_progs = [
> > diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c new
> > file mode 100644 index 00000000..55fbca92
> > --- /dev/null
> > +++ b/tests/xe/xe_spin_batch.c
> > @@ -0,0 +1,113 @@
> > +#include "igt.h"
> > +#include "lib/intel_reg.h"
> > +#include "xe_drm.h"
> > +#include "xe/xe_ioctl.h"
> > +#include "xe/xe_query.h"
> > +
> > +#define MAX_INSTANCE 9
> > +/**
> > + * TEST: Basic test for spin batch submission.
> > + *
> > + * SUBTEST: spin-batch
> > + * Description: Simple test!
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin(int fd, struct drm_xe_engine_class_instance *hwe) {
> > + uint64_t ahnd;
> > + unsigned int engine;
> > + uint32_t vm;
> > + igt_spin_t *spin;
> > +
> > + vm = xe_vm_create(fd, 0, 0);
> > + engine = xe_engine_create(fd, vm, hwe, 0);
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe, .engine = engine,
> .vm = vm);
> > + igt_assert(spin);
> > +
> > + igt_spin_free(fd, spin);
> > + put_ahnd(ahnd);
> > +}
> > +
> > +/**
> > + * TEST: Test for spin batch submissions.
> > + * SUBTEST: spin-all
> > + * Description: Spinner test to run on all the engines!
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin_all (int fd, int gt, int class) {
> > + uint64_t ahnd;
> > + uint32_t engines[MAX_INSTANCE];
> > + uint32_t vm[MAX_INSTANCE];
> > + int i, num_placements = 0;
> > + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> > + igt_spin_t *spin[MAX_INSTANCE];
> > + struct drm_xe_engine_class_instance *hwe;
> > +
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + xe_for_each_hw_engine(fd, hwe) {
> > + if (hwe->engine_class != class || hwe->gt_id != gt)
> > + continue;
> > + eci[num_placements++] = *hwe;
> > + }
> > + if (num_placements < 2)
> > + return;
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + struct drm_xe_engine_create create;
> > + vm[i] = xe_vm_create(fd, 0, 0);
> > +
> > + create.vm_id = vm[i];
> > + create.width = 1;
> > + create.num_placements = num_placements;
> > + create.instances = to_user_pointer(eci);
> > +
> > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> > + &create), 0);
> > + engines[i] = create.engine_id;
> > + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .hwe = eci, .engine =
> engines[i], .vm = vm[i]);
> > + }
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + igt_assert(spin[i]);
> > + igt_spin_free(fd, spin[i]);
> > + }
> > +}
> > +
> > +igt_main
> > +{
> > + struct drm_xe_engine_class_instance *hwe;
> > + int fd;
> > + int gt, class;
> > +
> > + igt_fixture {
> > + fd = drm_open_driver(DRIVER_XE);
> > + xe_device_get(fd);
> > + }
> > +
> > + igt_subtest("spin-batch")
> > + xe_for_each_hw_engine(fd, hwe)
>
> I think, this loop should be handled inside the xe spin helper (like spin_create()).
> Since KMS also trying to use the same helper & really don't care about hardware
> engines.
>
That would be tricky because we need hwe for engine, I just tried something like below, however it's throwing an errno : 16, Device or resource busy while doing xe_vm_bind.
igt_spin_t *
__igt_spin_factory(int fd, const struct igt_spin_factory *opts)
{
if (is_xe_device(fd)) {
struct drm_xe_engine_class_instance *hwe;
igt_spin_t *spin;
xe_for_each_hw_engine(fd, hwe)
spin = xe_spin_create(fd, opts, hwe);
-----
Gowtham
> - Bhanu
>
> > + spin(fd, hwe);
> > +
> > + igt_subtest("spin-all") {
> > + xe_for_each_gt(fd, gt)
> > + xe_for_each_hw_engine_class(class)
> > + spin_all(fd, gt, class);
> > + }
> > +
> > + igt_fixture {
> > + xe_device_put(fd);
> > + close(fd);
> > + }
> > +}
> > +
> > +
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-05-24 7:11 ` Modem, Bhanuprakash
2023-05-24 19:47 ` Ch, Sai Gowtham
2023-05-25 5:46 ` Zbigniew Kempczyński
0 siblings, 2 replies; 31+ messages in thread
From: Modem, Bhanuprakash @ 2023-05-24 7:11 UTC (permalink / raw)
To: sai.gowtham.ch, igt-dev, zbigniew.kempczynski
On Mon-22-05-2023 06:06 pm, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> xe_spin_batch test exercises basic igt_spin_new submissions and
> and with all engines.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_spin_batch.c | 113 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 114 insertions(+)
> create mode 100644 tests/xe/xe_spin_batch.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index f71be1db..e794b75a 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -268,6 +268,7 @@ xe_progs = [
> 'xe_query',
> 'xe_vm',
> 'xe_waitfence',
> + 'xe_spin_batch',
> ]
>
> msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..55fbca92
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,113 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +/**
> + * TEST: Basic test for spin batch submission.
> + *
> + * SUBTEST: spin-batch
> + * Description: Simple test!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + unsigned int engine;
> + uint32_t vm;
> + igt_spin_t *spin;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_engine_create(fd, vm, hwe, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe, .engine = engine, .vm = vm);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all (int fd, int gt, int class)
> +{
> + uint64_t ahnd;
> + uint32_t engines[MAX_INSTANCE];
> + uint32_t vm[MAX_INSTANCE];
> + int i, num_placements = 0;
> + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> + igt_spin_t *spin[MAX_INSTANCE];
> + struct drm_xe_engine_class_instance *hwe;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + xe_for_each_hw_engine(fd, hwe) {
> + if (hwe->engine_class != class || hwe->gt_id != gt)
> + continue;
> + eci[num_placements++] = *hwe;
> + }
> + if (num_placements < 2)
> + return;
> +
> + for (i = 0; i < num_placements; i++) {
> + struct drm_xe_engine_create create;
> + vm[i] = xe_vm_create(fd, 0, 0);
> +
> + create.vm_id = vm[i];
> + create.width = 1;
> + create.num_placements = num_placements;
> + create.instances = to_user_pointer(eci);
> +
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> + &create), 0);
> + engines[i] = create.engine_id;
> + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .hwe = eci, .engine = engines[i], .vm = vm[i]);
> + }
> +
> + for (i = 0; i < num_placements; i++) {
> + igt_assert(spin[i]);
> + igt_spin_free(fd, spin[i]);
> + }
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> + int gt, class;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> + }
> +
> + igt_subtest("spin-batch")
> + xe_for_each_hw_engine(fd, hwe)
I think, this loop should be handled inside the xe spin helper (like
spin_create()). Since KMS also trying to use the same helper & really
don't care about hardware engines.
- Bhanu
> + spin(fd, hwe);
> +
> + igt_subtest("spin-all") {
> + xe_for_each_gt(fd, gt)
> + xe_for_each_hw_engine_class(class)
> + spin_all(fd, gt, class);
> + }
> +
> + igt_fixture {
> + xe_device_put(fd);
> + close(fd);
> + }
> +}
> +
> +
^ permalink raw reply [flat|nested] 31+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-22 12:36 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
@ 2023-05-22 12:36 ` sai.gowtham.ch
2023-05-24 7:11 ` Modem, Bhanuprakash
0 siblings, 1 reply; 31+ messages in thread
From: sai.gowtham.ch @ 2023-05-22 12:36 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
xe_spin_batch test exercises basic igt_spin_new submissions and
and with all engines.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 113 +++++++++++++++++++++++++++++++++++++++
2 files changed, 114 insertions(+)
create mode 100644 tests/xe/xe_spin_batch.c
diff --git a/tests/meson.build b/tests/meson.build
index f71be1db..e794b75a 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -268,6 +268,7 @@ xe_progs = [
'xe_query',
'xe_vm',
'xe_waitfence',
+ 'xe_spin_batch',
]
msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..55fbca92
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,113 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+/**
+ * TEST: Basic test for spin batch submission.
+ *
+ * SUBTEST: spin-batch
+ * Description: Simple test!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ unsigned int engine;
+ uint32_t vm;
+ igt_spin_t *spin;
+
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_engine_create(fd, vm, hwe, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe, .engine = engine, .vm = vm);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all (int fd, int gt, int class)
+{
+ uint64_t ahnd;
+ uint32_t engines[MAX_INSTANCE];
+ uint32_t vm[MAX_INSTANCE];
+ int i, num_placements = 0;
+ struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+ igt_spin_t *spin[MAX_INSTANCE];
+ struct drm_xe_engine_class_instance *hwe;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ xe_for_each_hw_engine(fd, hwe) {
+ if (hwe->engine_class != class || hwe->gt_id != gt)
+ continue;
+ eci[num_placements++] = *hwe;
+ }
+ if (num_placements < 2)
+ return;
+
+ for (i = 0; i < num_placements; i++) {
+ struct drm_xe_engine_create create;
+ vm[i] = xe_vm_create(fd, 0, 0);
+
+ create.vm_id = vm[i];
+ create.width = 1;
+ create.num_placements = num_placements;
+ create.instances = to_user_pointer(eci);
+
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+ &create), 0);
+ engines[i] = create.engine_id;
+ spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .hwe = eci, .engine = engines[i], .vm = vm[i]);
+ }
+
+ for (i = 0; i < num_placements; i++) {
+ igt_assert(spin[i]);
+ igt_spin_free(fd, spin[i]);
+ }
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+ int gt, class;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("spin-batch")
+ xe_for_each_hw_engine(fd, hwe)
+ spin(fd, hwe);
+
+ igt_subtest("spin-all") {
+ xe_for_each_gt(fd, gt)
+ xe_for_each_hw_engine_class(class)
+ spin_all(fd, gt, class);
+ }
+
+ igt_fixture {
+ xe_device_put(fd);
+ close(fd);
+ }
+}
+
+
--
2.39.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
end of thread, other threads:[~2023-06-16 6:22 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
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2023-06-06 8:50 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-06-06 8:50 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
2023-06-06 19:27 ` Zbigniew Kempczyński
2023-06-06 21:03 ` Ch, Sai Gowtham
2023-06-06 8:50 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-06-06 20:00 ` Zbigniew Kempczyński
2023-06-06 10:12 ` [igt-dev] ✗ GitLab.Pipeline: warning for Integrate igt_spin_new with Xe (rev3) Patchwork
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2023-06-15 10:59 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-06-15 10:59 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-06-16 6:22 ` Zbigniew Kempczyński
2023-06-13 12:42 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-06-13 12:42 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-06-14 17:43 ` Zbigniew Kempczyński
2023-06-12 8:59 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-06-12 8:59 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-06-12 18:46 ` Zbigniew Kempczyński
2023-06-04 19:58 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-06-04 19:58 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-06-05 8:59 ` Kumar, Janga Rahul
2023-06-05 10:44 ` Zbigniew Kempczyński
2023-06-05 13:24 ` Ch, Sai Gowtham
2023-06-05 18:00 ` Zbigniew Kempczyński
2023-06-04 19:16 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-06-04 19:16 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-05-30 10:08 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-05-30 10:08 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-05-31 5:55 ` Zbigniew Kempczyński
2023-05-25 5:55 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-05-25 5:55 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-05-29 5:57 ` Zbigniew Kempczyński
2023-05-29 11:02 ` Ch, Sai Gowtham
2023-05-30 19:12 ` Zbigniew Kempczyński
2023-05-22 12:36 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-05-24 7:11 ` Modem, Bhanuprakash
2023-05-24 19:47 ` Ch, Sai Gowtham
2023-05-25 5:46 ` Zbigniew Kempczyński
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