* [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
Posting again, a couple of patches were merged and accounted for review
comments from last time.
Thanks,
Nick
Nicholas Piggin (12):
powerpc: Report instruction address and MSR in unhandled exception
error
powerpc: Add some checking to exception handler install
powerpc: Abstract H_CEDE calls into a sleep functions
powerpc: Add ISA v3.1 (POWER10) support to SPR test
powerpc: Extract some common helpers and defines to headers
powerpc/sprs: Specify SPRs with data rather than code
powerpc/spapr_vpa: Add basic VPA tests
powerpc: Expand exception handler vector granularity
powerpc: Add support for more interrupts including HV interrupts
powerpc: Discover runtime load address dynamically
powerpc: Support powernv machine with QEMU TCG
powerpc/sprs: Test hypervisor registers on powernv machine
lib/powerpc/asm/handlers.h | 2 +-
lib/powerpc/asm/hcall.h | 1 +
lib/powerpc/asm/ppc_asm.h | 9 +
lib/powerpc/asm/processor.h | 55 ++-
lib/powerpc/handlers.c | 10 +-
lib/powerpc/hcall.c | 4 +-
lib/powerpc/io.c | 27 +-
lib/powerpc/io.h | 6 +
lib/powerpc/processor.c | 79 ++++-
lib/powerpc/setup.c | 8 +-
lib/ppc64/asm/opal.h | 15 +
lib/ppc64/asm/vpa.h | 62 ++++
lib/ppc64/opal-calls.S | 46 +++
lib/ppc64/opal.c | 74 +++++
powerpc/Makefile.ppc64 | 4 +-
powerpc/cstart64.S | 105 ++++--
powerpc/run | 35 +-
powerpc/spapr_hcall.c | 9 +-
powerpc/spapr_vpa.c | 172 ++++++++++
powerpc/sprs.c | 645 ++++++++++++++++++++++++++----------
powerpc/tm.c | 20 +-
powerpc/unittests.cfg | 3 +
22 files changed, 1133 insertions(+), 258 deletions(-)
create mode 100644 lib/ppc64/asm/opal.h
create mode 100644 lib/ppc64/asm/vpa.h
create mode 100644 lib/ppc64/opal-calls.S
create mode 100644 lib/ppc64/opal.c
create mode 100644 powerpc/spapr_vpa.c
--
2.40.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
Posting again, a couple of patches were merged and accounted for review
comments from last time.
Thanks,
Nick
Nicholas Piggin (12):
powerpc: Report instruction address and MSR in unhandled exception
error
powerpc: Add some checking to exception handler install
powerpc: Abstract H_CEDE calls into a sleep functions
powerpc: Add ISA v3.1 (POWER10) support to SPR test
powerpc: Extract some common helpers and defines to headers
powerpc/sprs: Specify SPRs with data rather than code
powerpc/spapr_vpa: Add basic VPA tests
powerpc: Expand exception handler vector granularity
powerpc: Add support for more interrupts including HV interrupts
powerpc: Discover runtime load address dynamically
powerpc: Support powernv machine with QEMU TCG
powerpc/sprs: Test hypervisor registers on powernv machine
lib/powerpc/asm/handlers.h | 2 +-
lib/powerpc/asm/hcall.h | 1 +
lib/powerpc/asm/ppc_asm.h | 9 +
lib/powerpc/asm/processor.h | 55 ++-
lib/powerpc/handlers.c | 10 +-
lib/powerpc/hcall.c | 4 +-
lib/powerpc/io.c | 27 +-
lib/powerpc/io.h | 6 +
lib/powerpc/processor.c | 79 ++++-
lib/powerpc/setup.c | 8 +-
lib/ppc64/asm/opal.h | 15 +
lib/ppc64/asm/vpa.h | 62 ++++
lib/ppc64/opal-calls.S | 46 +++
lib/ppc64/opal.c | 74 +++++
powerpc/Makefile.ppc64 | 4 +-
powerpc/cstart64.S | 105 ++++--
powerpc/run | 35 +-
powerpc/spapr_hcall.c | 9 +-
powerpc/spapr_vpa.c | 172 ++++++++++
powerpc/sprs.c | 645 ++++++++++++++++++++++++++----------
powerpc/tm.c | 20 +-
powerpc/unittests.cfg | 3 +
22 files changed, 1133 insertions(+), 258 deletions(-)
create mode 100644 lib/ppc64/asm/opal.h
create mode 100644 lib/ppc64/asm/vpa.h
create mode 100644 lib/ppc64/opal-calls.S
create mode 100644 lib/ppc64/opal.c
create mode 100644 powerpc/spapr_vpa.c
--
2.40.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 01/12] powerpc: Report instruction address and MSR in unhandled exception error
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v3:
- New patch
lib/powerpc/processor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
index ec85b9d8..05b4b04f 100644
--- a/lib/powerpc/processor.c
+++ b/lib/powerpc/processor.c
@@ -38,7 +38,7 @@ void do_handle_exception(struct pt_regs *regs)
return;
}
- printf("unhandled cpu exception %#lx\n", regs->trap);
+ printf("unhandled cpu exception %#lx at NIA:0x%016lx MSR:0x%016lx\n", regs->trap, regs->nip, regs->msr);
abort();
}
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 01/12] powerpc: Report instruction address and MSR in unhandled exception error
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v3:
- New patch
lib/powerpc/processor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
index ec85b9d8..05b4b04f 100644
--- a/lib/powerpc/processor.c
+++ b/lib/powerpc/processor.c
@@ -38,7 +38,7 @@ void do_handle_exception(struct pt_regs *regs)
return;
}
- printf("unhandled cpu exception %#lx\n", regs->trap);
+ printf("unhandled cpu exception %#lx at NIA:0x%016lx MSR:0x%016lx\n", regs->trap, regs->nip, regs->msr);
abort();
}
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 02/12] powerpc: Add some checking to exception handler install
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
Check to ensure exception handlers are not being overwritten or
invalid exception numbers are used.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v3:
- Simplified code as suggested by Thomas.
lib/powerpc/processor.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
index 05b4b04f..0550e4fc 100644
--- a/lib/powerpc/processor.c
+++ b/lib/powerpc/processor.c
@@ -19,12 +19,16 @@ static struct {
void handle_exception(int trap, void (*func)(struct pt_regs *, void *),
void * data)
{
+ assert(!(trap & ~0xf00));
+
trap >>= 8;
- if (trap < 16) {
- handlers[trap].func = func;
- handlers[trap].data = data;
+ if (func && handlers[trap].func) {
+ printf("exception handler installed twice %#x\n", trap);
+ abort();
}
+ handlers[trap].func = func;
+ handlers[trap].data = data;
}
void do_handle_exception(struct pt_regs *regs)
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 02/12] powerpc: Add some checking to exception handler install
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
Check to ensure exception handlers are not being overwritten or
invalid exception numbers are used.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v3:
- Simplified code as suggested by Thomas.
lib/powerpc/processor.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
index 05b4b04f..0550e4fc 100644
--- a/lib/powerpc/processor.c
+++ b/lib/powerpc/processor.c
@@ -19,12 +19,16 @@ static struct {
void handle_exception(int trap, void (*func)(struct pt_regs *, void *),
void * data)
{
+ assert(!(trap & ~0xf00));
+
trap >>= 8;
- if (trap < 16) {
- handlers[trap].func = func;
- handlers[trap].data = data;
+ if (func && handlers[trap].func) {
+ printf("exception handler installed twice %#x\n", trap);
+ abort();
}
+ handlers[trap].func = func;
+ handlers[trap].data = data;
}
void do_handle_exception(struct pt_regs *regs)
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 03/12] powerpc: Abstract H_CEDE calls into a sleep functions
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
This consolidates several implementations, and it no longer leaves
MSR[EE] enabled after the decrementer interrupt is handled, but
rather disables it on return.
The handler no longer allows a continuous ticking, but rather dec
has to be re-armed and EE re-enabled (e.g., via H_CEDE hcall) each
time.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
lib/powerpc/asm/handlers.h | 2 +-
lib/powerpc/asm/ppc_asm.h | 1 +
lib/powerpc/asm/processor.h | 7 ++++++
lib/powerpc/handlers.c | 10 ++++-----
lib/powerpc/processor.c | 43 +++++++++++++++++++++++++++++++++++++
powerpc/sprs.c | 6 +-----
powerpc/tm.c | 20 +----------------
7 files changed, 58 insertions(+), 31 deletions(-)
diff --git a/lib/powerpc/asm/handlers.h b/lib/powerpc/asm/handlers.h
index 64ba727a..e4a0cd45 100644
--- a/lib/powerpc/asm/handlers.h
+++ b/lib/powerpc/asm/handlers.h
@@ -3,6 +3,6 @@
#include <asm/ptrace.h>
-void dec_except_handler(struct pt_regs *regs, void *data);
+void dec_handler_oneshot(struct pt_regs *regs, void *data);
#endif /* _ASMPOWERPC_HANDLERS_H_ */
diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h
index 1b85f6bb..6299ff53 100644
--- a/lib/powerpc/asm/ppc_asm.h
+++ b/lib/powerpc/asm/ppc_asm.h
@@ -36,6 +36,7 @@
#endif /* __BYTE_ORDER__ */
/* Machine State Register definitions: */
+#define MSR_EE_BIT 15 /* External Interrupts Enable */
#define MSR_SF_BIT 63 /* 64-bit mode */
#endif /* _ASMPOWERPC_PPC_ASM_H */
diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h
index ac001e18..ebfeff2b 100644
--- a/lib/powerpc/asm/processor.h
+++ b/lib/powerpc/asm/processor.h
@@ -20,6 +20,8 @@ static inline uint64_t get_tb(void)
extern void delay(uint64_t cycles);
extern void udelay(uint64_t us);
+extern void sleep_tb(uint64_t cycles);
+extern void usleep(uint64_t us);
static inline void mdelay(uint64_t ms)
{
@@ -27,4 +29,9 @@ static inline void mdelay(uint64_t ms)
udelay(1000);
}
+static inline void msleep(uint64_t ms)
+{
+ usleep(ms * 1000);
+}
+
#endif /* _ASMPOWERPC_PROCESSOR_H_ */
diff --git a/lib/powerpc/handlers.c b/lib/powerpc/handlers.c
index c8721e0a..296f14ff 100644
--- a/lib/powerpc/handlers.c
+++ b/lib/powerpc/handlers.c
@@ -9,15 +9,13 @@
#include <libcflat.h>
#include <asm/handlers.h>
#include <asm/ptrace.h>
+#include <asm/ppc_asm.h>
/*
* Generic handler for decrementer exceptions (0x900)
- * Just reset the decrementer back to the value specified when registering the
- * handler
+ * Return with MSR[EE] disabled.
*/
-void dec_except_handler(struct pt_regs *regs __unused, void *data)
+void dec_handler_oneshot(struct pt_regs *regs, void *data)
{
- uint64_t dec = *((uint64_t *) data);
-
- asm volatile ("mtdec %0" : : "r" (dec));
+ regs->msr &= ~(1UL << MSR_EE_BIT);
}
diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
index 0550e4fc..aaf45b68 100644
--- a/lib/powerpc/processor.c
+++ b/lib/powerpc/processor.c
@@ -10,6 +10,8 @@
#include <asm/ptrace.h>
#include <asm/setup.h>
#include <asm/barrier.h>
+#include <asm/hcall.h>
+#include <asm/handlers.h>
static struct {
void (*func)(struct pt_regs *, void *data);
@@ -58,3 +60,44 @@ void udelay(uint64_t us)
{
delay((us * tb_hz) / 1000000);
}
+
+void sleep_tb(uint64_t cycles)
+{
+ uint64_t start, end, now;
+
+ start = now = get_tb();
+ end = start + cycles;
+
+ while (end > now) {
+ uint64_t left = end - now;
+
+ /* TODO: Could support large decrementer */
+ if (left > 0x7fffffff)
+ left = 0x7fffffff;
+
+ /* DEC won't fire until H_CEDE is called because EE=0 */
+ asm volatile ("mtdec %0" : : "r" (left));
+ handle_exception(0x900, &dec_handler_oneshot, NULL);
+ /*
+ * H_CEDE is called with MSR[EE] clear and enables it as part
+ * of the hcall, returning with EE enabled. The dec interrupt
+ * is then taken immediately and the handler disables EE.
+ *
+ * If H_CEDE returned for any other interrupt than dec
+ * expiring, that is considered an unhandled interrupt and
+ * the test case would be stopped.
+ */
+ if (hcall(H_CEDE) != H_SUCCESS) {
+ printf("H_CEDE failed\n");
+ abort();
+ }
+ handle_exception(0x900, NULL, NULL);
+
+ now = get_tb();
+ }
+}
+
+void usleep(uint64_t us)
+{
+ sleep_tb((us * tb_hz) / 1000000);
+}
diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index 5cc1cd16..ba4ddee4 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -254,7 +254,6 @@ int main(int argc, char **argv)
0x1234567890ABCDEFULL, 0xFEDCBA0987654321ULL,
-1ULL,
};
- static uint64_t decr = 0x7FFFFFFF; /* Max value */
for (i = 1; i < argc; i++) {
if (!strcmp(argv[i], "-w")) {
@@ -288,10 +287,7 @@ int main(int argc, char **argv)
if (pause) {
migrate_once();
} else {
- puts("Sleeping...\n");
- handle_exception(0x900, &dec_except_handler, &decr);
- asm volatile ("mtdec %0" : : "r" (0x3FFFFFFF));
- hcall(H_CEDE);
+ msleep(2000);
}
get_sprs(after);
diff --git a/powerpc/tm.c b/powerpc/tm.c
index 65cacdf5..7fa91636 100644
--- a/powerpc/tm.c
+++ b/powerpc/tm.c
@@ -48,17 +48,6 @@ static int count_cpus_with_tm(void)
return available;
}
-static int h_cede(void)
-{
- register uint64_t r3 asm("r3") = H_CEDE;
-
- asm volatile ("sc 1" : "+r"(r3) :
- : "r0", "r4", "r5", "r6", "r7", "r8", "r9",
- "r10", "r11", "r12", "xer", "ctr", "cc");
-
- return r3;
-}
-
/*
* Enable transactional memory
* Returns: FALSE - Failure
@@ -95,14 +84,10 @@ static bool enable_tm(void)
static void test_h_cede_tm(int argc, char **argv)
{
int i;
- static uint64_t decr = 0x3FFFFF; /* ~10ms */
if (argc > 2)
report_abort("Unsupported argument: '%s'", argv[2]);
- handle_exception(0x900, &dec_except_handler, &decr);
- asm volatile ("mtdec %0" : : "r" (decr));
-
if (!start_all_cpus(halt, 0))
report_abort("Failed to start secondary cpus");
@@ -120,10 +105,7 @@ static void test_h_cede_tm(int argc, char **argv)
"bf 2,1b" : : : "cr0");
for (i = 0; i < 500; i++) {
- uint64_t rval = h_cede();
-
- if (rval != H_SUCCESS)
- break;
+ msleep(10);
mdelay(5);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 03/12] powerpc: Abstract H_CEDE calls into a sleep functions
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
This consolidates several implementations, and it no longer leaves
MSR[EE] enabled after the decrementer interrupt is handled, but
rather disables it on return.
The handler no longer allows a continuous ticking, but rather dec
has to be re-armed and EE re-enabled (e.g., via H_CEDE hcall) each
time.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
lib/powerpc/asm/handlers.h | 2 +-
lib/powerpc/asm/ppc_asm.h | 1 +
lib/powerpc/asm/processor.h | 7 ++++++
lib/powerpc/handlers.c | 10 ++++-----
lib/powerpc/processor.c | 43 +++++++++++++++++++++++++++++++++++++
powerpc/sprs.c | 6 +-----
powerpc/tm.c | 20 +----------------
7 files changed, 58 insertions(+), 31 deletions(-)
diff --git a/lib/powerpc/asm/handlers.h b/lib/powerpc/asm/handlers.h
index 64ba727a..e4a0cd45 100644
--- a/lib/powerpc/asm/handlers.h
+++ b/lib/powerpc/asm/handlers.h
@@ -3,6 +3,6 @@
#include <asm/ptrace.h>
-void dec_except_handler(struct pt_regs *regs, void *data);
+void dec_handler_oneshot(struct pt_regs *regs, void *data);
#endif /* _ASMPOWERPC_HANDLERS_H_ */
diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h
index 1b85f6bb..6299ff53 100644
--- a/lib/powerpc/asm/ppc_asm.h
+++ b/lib/powerpc/asm/ppc_asm.h
@@ -36,6 +36,7 @@
#endif /* __BYTE_ORDER__ */
/* Machine State Register definitions: */
+#define MSR_EE_BIT 15 /* External Interrupts Enable */
#define MSR_SF_BIT 63 /* 64-bit mode */
#endif /* _ASMPOWERPC_PPC_ASM_H */
diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h
index ac001e18..ebfeff2b 100644
--- a/lib/powerpc/asm/processor.h
+++ b/lib/powerpc/asm/processor.h
@@ -20,6 +20,8 @@ static inline uint64_t get_tb(void)
extern void delay(uint64_t cycles);
extern void udelay(uint64_t us);
+extern void sleep_tb(uint64_t cycles);
+extern void usleep(uint64_t us);
static inline void mdelay(uint64_t ms)
{
@@ -27,4 +29,9 @@ static inline void mdelay(uint64_t ms)
udelay(1000);
}
+static inline void msleep(uint64_t ms)
+{
+ usleep(ms * 1000);
+}
+
#endif /* _ASMPOWERPC_PROCESSOR_H_ */
diff --git a/lib/powerpc/handlers.c b/lib/powerpc/handlers.c
index c8721e0a..296f14ff 100644
--- a/lib/powerpc/handlers.c
+++ b/lib/powerpc/handlers.c
@@ -9,15 +9,13 @@
#include <libcflat.h>
#include <asm/handlers.h>
#include <asm/ptrace.h>
+#include <asm/ppc_asm.h>
/*
* Generic handler for decrementer exceptions (0x900)
- * Just reset the decrementer back to the value specified when registering the
- * handler
+ * Return with MSR[EE] disabled.
*/
-void dec_except_handler(struct pt_regs *regs __unused, void *data)
+void dec_handler_oneshot(struct pt_regs *regs, void *data)
{
- uint64_t dec = *((uint64_t *) data);
-
- asm volatile ("mtdec %0" : : "r" (dec));
+ regs->msr &= ~(1UL << MSR_EE_BIT);
}
diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
index 0550e4fc..aaf45b68 100644
--- a/lib/powerpc/processor.c
+++ b/lib/powerpc/processor.c
@@ -10,6 +10,8 @@
#include <asm/ptrace.h>
#include <asm/setup.h>
#include <asm/barrier.h>
+#include <asm/hcall.h>
+#include <asm/handlers.h>
static struct {
void (*func)(struct pt_regs *, void *data);
@@ -58,3 +60,44 @@ void udelay(uint64_t us)
{
delay((us * tb_hz) / 1000000);
}
+
+void sleep_tb(uint64_t cycles)
+{
+ uint64_t start, end, now;
+
+ start = now = get_tb();
+ end = start + cycles;
+
+ while (end > now) {
+ uint64_t left = end - now;
+
+ /* TODO: Could support large decrementer */
+ if (left > 0x7fffffff)
+ left = 0x7fffffff;
+
+ /* DEC won't fire until H_CEDE is called because EE=0 */
+ asm volatile ("mtdec %0" : : "r" (left));
+ handle_exception(0x900, &dec_handler_oneshot, NULL);
+ /*
+ * H_CEDE is called with MSR[EE] clear and enables it as part
+ * of the hcall, returning with EE enabled. The dec interrupt
+ * is then taken immediately and the handler disables EE.
+ *
+ * If H_CEDE returned for any other interrupt than dec
+ * expiring, that is considered an unhandled interrupt and
+ * the test case would be stopped.
+ */
+ if (hcall(H_CEDE) != H_SUCCESS) {
+ printf("H_CEDE failed\n");
+ abort();
+ }
+ handle_exception(0x900, NULL, NULL);
+
+ now = get_tb();
+ }
+}
+
+void usleep(uint64_t us)
+{
+ sleep_tb((us * tb_hz) / 1000000);
+}
diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index 5cc1cd16..ba4ddee4 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -254,7 +254,6 @@ int main(int argc, char **argv)
0x1234567890ABCDEFULL, 0xFEDCBA0987654321ULL,
-1ULL,
};
- static uint64_t decr = 0x7FFFFFFF; /* Max value */
for (i = 1; i < argc; i++) {
if (!strcmp(argv[i], "-w")) {
@@ -288,10 +287,7 @@ int main(int argc, char **argv)
if (pause) {
migrate_once();
} else {
- puts("Sleeping...\n");
- handle_exception(0x900, &dec_except_handler, &decr);
- asm volatile ("mtdec %0" : : "r" (0x3FFFFFFF));
- hcall(H_CEDE);
+ msleep(2000);
}
get_sprs(after);
diff --git a/powerpc/tm.c b/powerpc/tm.c
index 65cacdf5..7fa91636 100644
--- a/powerpc/tm.c
+++ b/powerpc/tm.c
@@ -48,17 +48,6 @@ static int count_cpus_with_tm(void)
return available;
}
-static int h_cede(void)
-{
- register uint64_t r3 asm("r3") = H_CEDE;
-
- asm volatile ("sc 1" : "+r"(r3) :
- : "r0", "r4", "r5", "r6", "r7", "r8", "r9",
- "r10", "r11", "r12", "xer", "ctr", "cc");
-
- return r3;
-}
-
/*
* Enable transactional memory
* Returns: FALSE - Failure
@@ -95,14 +84,10 @@ static bool enable_tm(void)
static void test_h_cede_tm(int argc, char **argv)
{
int i;
- static uint64_t decr = 0x3FFFFF; /* ~10ms */
if (argc > 2)
report_abort("Unsupported argument: '%s'", argv[2]);
- handle_exception(0x900, &dec_except_handler, &decr);
- asm volatile ("mtdec %0" : : "r" (decr));
-
if (!start_all_cpus(halt, 0))
report_abort("Failed to start secondary cpus");
@@ -120,10 +105,7 @@ static void test_h_cede_tm(int argc, char **argv)
"bf 2,1b" : : : "cr0");
for (i = 0; i < 500; i++) {
- uint64_t rval = h_cede();
-
- if (rval != H_SUCCESS)
- break;
+ msleep(10);
mdelay(5);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 04/12] powerpc: Add ISA v3.1 (POWER10) support to SPR test
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
This is a very basic detection that does not include all new SPRs.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
powerpc/sprs.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index ba4ddee4..6ee6dba6 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -117,6 +117,15 @@ static void set_sprs_book3s_300(uint64_t val)
mtspr(823, val); /* PSSCR */
}
+/* SPRs from Power ISA Version 3.1B */
+static void set_sprs_book3s_31(uint64_t val)
+{
+ set_sprs_book3s_207(val);
+ mtspr(48, val); /* PIDR */
+ /* 3.1 removes TIDR */
+ mtspr(823, val); /* PSSCR */
+}
+
static void set_sprs(uint64_t val)
{
uint32_t pvr = mfspr(287); /* Processor Version Register */
@@ -137,6 +146,9 @@ static void set_sprs(uint64_t val)
case 0x4e: /* POWER9 */
set_sprs_book3s_300(val);
break;
+ case 0x80: /* POWER10 */
+ set_sprs_book3s_31(val);
+ break;
default:
puts("Warning: Unknown processor version!\n");
}
@@ -220,6 +232,13 @@ static void get_sprs_book3s_300(uint64_t *v)
v[823] = mfspr(823); /* PSSCR */
}
+static void get_sprs_book3s_31(uint64_t *v)
+{
+ get_sprs_book3s_207(v);
+ v[48] = mfspr(48); /* PIDR */
+ v[823] = mfspr(823); /* PSSCR */
+}
+
static void get_sprs(uint64_t *v)
{
uint32_t pvr = mfspr(287); /* Processor Version Register */
@@ -240,6 +259,9 @@ static void get_sprs(uint64_t *v)
case 0x4e: /* POWER9 */
get_sprs_book3s_300(v);
break;
+ case 0x80: /* POWER10 */
+ get_sprs_book3s_31(v);
+ break;
}
}
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 04/12] powerpc: Add ISA v3.1 (POWER10) support to SPR test
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
This is a very basic detection that does not include all new SPRs.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
powerpc/sprs.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index ba4ddee4..6ee6dba6 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -117,6 +117,15 @@ static void set_sprs_book3s_300(uint64_t val)
mtspr(823, val); /* PSSCR */
}
+/* SPRs from Power ISA Version 3.1B */
+static void set_sprs_book3s_31(uint64_t val)
+{
+ set_sprs_book3s_207(val);
+ mtspr(48, val); /* PIDR */
+ /* 3.1 removes TIDR */
+ mtspr(823, val); /* PSSCR */
+}
+
static void set_sprs(uint64_t val)
{
uint32_t pvr = mfspr(287); /* Processor Version Register */
@@ -137,6 +146,9 @@ static void set_sprs(uint64_t val)
case 0x4e: /* POWER9 */
set_sprs_book3s_300(val);
break;
+ case 0x80: /* POWER10 */
+ set_sprs_book3s_31(val);
+ break;
default:
puts("Warning: Unknown processor version!\n");
}
@@ -220,6 +232,13 @@ static void get_sprs_book3s_300(uint64_t *v)
v[823] = mfspr(823); /* PSSCR */
}
+static void get_sprs_book3s_31(uint64_t *v)
+{
+ get_sprs_book3s_207(v);
+ v[48] = mfspr(48); /* PIDR */
+ v[823] = mfspr(823); /* PSSCR */
+}
+
static void get_sprs(uint64_t *v)
{
uint32_t pvr = mfspr(287); /* Processor Version Register */
@@ -240,6 +259,9 @@ static void get_sprs(uint64_t *v)
case 0x4e: /* POWER9 */
get_sprs_book3s_300(v);
break;
+ case 0x80: /* POWER10 */
+ get_sprs_book3s_31(v);
+ break;
}
}
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 05/12] powerpc: Extract some common helpers and defines to headers
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
Move some common helpers and defines to processor.h.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
lib/powerpc/asm/processor.h | 38 +++++++++++++++++++++++++++++++++----
powerpc/spapr_hcall.c | 9 +--------
powerpc/sprs.c | 9 ---------
3 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h
index ebfeff2b..4ad6612b 100644
--- a/lib/powerpc/asm/processor.h
+++ b/lib/powerpc/asm/processor.h
@@ -9,13 +9,43 @@ void handle_exception(int trap, void (*func)(struct pt_regs *, void *), void *);
void do_handle_exception(struct pt_regs *regs);
#endif /* __ASSEMBLY__ */
-static inline uint64_t get_tb(void)
+#define SPR_TB 0x10c
+#define SPR_SPRG0 0x110
+#define SPR_SPRG1 0x111
+#define SPR_SPRG2 0x112
+#define SPR_SPRG3 0x113
+
+static inline uint64_t mfspr(int nr)
{
- uint64_t tb;
+ uint64_t ret;
+
+ asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr) : "memory");
+
+ return ret;
+}
- asm volatile ("mfspr %[tb],268" : [tb] "=r" (tb));
+static inline void mtspr(int nr, uint64_t val)
+{
+ asm volatile("mtspr %0,%1" : : "i"(nr), "r"(val) : "memory");
+}
+
+static inline uint64_t mfmsr(void)
+{
+ uint64_t msr;
- return tb;
+ asm volatile ("mfmsr %[msr]" : [msr] "=r" (msr) :: "memory");
+
+ return msr;
+}
+
+static inline void mtmsr(uint64_t msr)
+{
+ asm volatile ("mtmsrd %[msr]" :: [msr] "r" (msr) : "memory");
+}
+
+static inline uint64_t get_tb(void)
+{
+ return mfspr(SPR_TB);
}
extern void delay(uint64_t cycles);
diff --git a/powerpc/spapr_hcall.c b/powerpc/spapr_hcall.c
index 823a574a..0d0f25af 100644
--- a/powerpc/spapr_hcall.c
+++ b/powerpc/spapr_hcall.c
@@ -9,20 +9,13 @@
#include <util.h>
#include <alloc.h>
#include <asm/hcall.h>
+#include <asm/processor.h>
#define PAGE_SIZE 4096
#define H_ZERO_PAGE (1UL << (63-48))
#define H_COPY_PAGE (1UL << (63-49))
-#define mfspr(nr) ({ \
- uint64_t ret; \
- asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr)); \
- ret; \
-})
-
-#define SPR_SPRG0 0x110
-
/**
* Test the H_SET_SPRG0 h-call by setting some values and checking whether
* the SPRG0 register contains the correct values afterwards
diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index 6ee6dba6..57e487ce 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -28,15 +28,6 @@
#include <asm/processor.h>
#include <asm/barrier.h>
-#define mfspr(nr) ({ \
- uint64_t ret; \
- asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr)); \
- ret; \
-})
-
-#define mtspr(nr, val) \
- asm volatile("mtspr %0,%1" : : "i"(nr), "r"(val))
-
uint64_t before[1024], after[1024];
/* Common SPRs for all PowerPC CPUs */
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 05/12] powerpc: Extract some common helpers and defines to headers
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
Move some common helpers and defines to processor.h.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
lib/powerpc/asm/processor.h | 38 +++++++++++++++++++++++++++++++++----
powerpc/spapr_hcall.c | 9 +--------
powerpc/sprs.c | 9 ---------
3 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h
index ebfeff2b..4ad6612b 100644
--- a/lib/powerpc/asm/processor.h
+++ b/lib/powerpc/asm/processor.h
@@ -9,13 +9,43 @@ void handle_exception(int trap, void (*func)(struct pt_regs *, void *), void *);
void do_handle_exception(struct pt_regs *regs);
#endif /* __ASSEMBLY__ */
-static inline uint64_t get_tb(void)
+#define SPR_TB 0x10c
+#define SPR_SPRG0 0x110
+#define SPR_SPRG1 0x111
+#define SPR_SPRG2 0x112
+#define SPR_SPRG3 0x113
+
+static inline uint64_t mfspr(int nr)
{
- uint64_t tb;
+ uint64_t ret;
+
+ asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr) : "memory");
+
+ return ret;
+}
- asm volatile ("mfspr %[tb],268" : [tb] "=r" (tb));
+static inline void mtspr(int nr, uint64_t val)
+{
+ asm volatile("mtspr %0,%1" : : "i"(nr), "r"(val) : "memory");
+}
+
+static inline uint64_t mfmsr(void)
+{
+ uint64_t msr;
- return tb;
+ asm volatile ("mfmsr %[msr]" : [msr] "=r" (msr) :: "memory");
+
+ return msr;
+}
+
+static inline void mtmsr(uint64_t msr)
+{
+ asm volatile ("mtmsrd %[msr]" :: [msr] "r" (msr) : "memory");
+}
+
+static inline uint64_t get_tb(void)
+{
+ return mfspr(SPR_TB);
}
extern void delay(uint64_t cycles);
diff --git a/powerpc/spapr_hcall.c b/powerpc/spapr_hcall.c
index 823a574a..0d0f25af 100644
--- a/powerpc/spapr_hcall.c
+++ b/powerpc/spapr_hcall.c
@@ -9,20 +9,13 @@
#include <util.h>
#include <alloc.h>
#include <asm/hcall.h>
+#include <asm/processor.h>
#define PAGE_SIZE 4096
#define H_ZERO_PAGE (1UL << (63-48))
#define H_COPY_PAGE (1UL << (63-49))
-#define mfspr(nr) ({ \
- uint64_t ret; \
- asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr)); \
- ret; \
-})
-
-#define SPR_SPRG0 0x110
-
/**
* Test the H_SET_SPRG0 h-call by setting some values and checking whether
* the SPRG0 register contains the correct values afterwards
diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index 6ee6dba6..57e487ce 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -28,15 +28,6 @@
#include <asm/processor.h>
#include <asm/barrier.h>
-#define mfspr(nr) ({ \
- uint64_t ret; \
- asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr)); \
- ret; \
-})
-
-#define mtspr(nr, val) \
- asm volatile("mtspr %0,%1" : : "i"(nr), "r"(val))
-
uint64_t before[1024], after[1024];
/* Common SPRs for all PowerPC CPUs */
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 06/12] powerpc/sprs: Specify SPRs with data rather than code
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
A significant rework that builds an array of 'struct spr', where each
element describes an SPR. This makes various metadata about the SPR
like name and access type easier to carry and use.
Hypervisor privileged registers are described despite not being used
at the moment for completeness, but also the code might one day be
reused for a hypervisor-privileged test.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
This ended up a little over-engineered perhaps, but there are lots of
SPRs, lots of access types, lots of changes between processor and ISA
versions, and lots of places they are implemented and used, so lots of
room for mistakes. There is not a good system in place to easily
see that userspace, supervisor, etc., switches perform all the right
SPR context switching so this is a nice test case to have. The sprs test
quickly caught a few QEMU TCG SPR bugs which really motivated me to
improve the SPR coverage.
---
powerpc/sprs.c | 643 ++++++++++++++++++++++++++++++++++---------------
1 file changed, 450 insertions(+), 193 deletions(-)
diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index 57e487ce..d5664201 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -28,231 +28,465 @@
#include <asm/processor.h>
#include <asm/barrier.h>
-uint64_t before[1024], after[1024];
-
-/* Common SPRs for all PowerPC CPUs */
-static void set_sprs_common(uint64_t val)
+/* "Indirect" mfspr/mtspr which accept a non-constant spr number */
+static uint64_t __mfspr(unsigned spr)
{
- mtspr(9, val); /* CTR */
- // mtspr(273, val); /* SPRG1 */ /* Used by our exception handler */
- mtspr(274, val); /* SPRG2 */
- mtspr(275, val); /* SPRG3 */
+ uint64_t tmp;
+ uint64_t ret;
+
+ asm volatile(
+" bcl 20, 31, 1f \n"
+"1: mflr %0 \n"
+" addi %0, %0, (2f-1b) \n"
+" add %0, %0, %2 \n"
+" mtctr %0 \n"
+" bctr \n"
+"2: \n"
+".LSPR=0 \n"
+".rept 1024 \n"
+" mfspr %1, .LSPR \n"
+" b 3f \n"
+" .LSPR=.LSPR+1 \n"
+".endr \n"
+"3: \n"
+ : "=&r"(tmp),
+ "=r"(ret)
+ : "r"(spr*8) /* 8 bytes per 'mfspr ; b' block */
+ : "lr", "ctr");
+
+ return ret;
}
-/* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */
-static void set_sprs_book3s_201(uint64_t val)
+static void __mtspr(unsigned spr, uint64_t val)
{
- mtspr(18, val); /* DSISR */
- mtspr(19, val); /* DAR */
- mtspr(152, val); /* CTRL */
- mtspr(256, val); /* VRSAVE */
- mtspr(786, val); /* MMCRA */
- mtspr(795, val); /* MMCR0 */
- mtspr(798, val); /* MMCR1 */
+ uint64_t tmp;
+
+ asm volatile(
+" bcl 20, 31, 1f \n"
+"1: mflr %0 \n"
+" addi %0, %0, (2f-1b) \n"
+" add %0, %0, %2 \n"
+" mtctr %0 \n"
+" bctr \n"
+"2: \n"
+".LSPR=0 \n"
+".rept 1024 \n"
+" mtspr .LSPR, %1 \n"
+" b 3f \n"
+" .LSPR=.LSPR+1 \n"
+".endr \n"
+"3: \n"
+ : "=&r"(tmp)
+ : "r"(val),
+ "r"(spr*8) /* 8 bytes per 'mfspr ; b' block */
+ : "lr", "ctr", "xer");
}
+static uint64_t before[1024], after[1024];
+
+#define SPR_PR_READ 0x0001
+#define SPR_PR_WRITE 0x0002
+#define SPR_OS_READ 0x0010
+#define SPR_OS_WRITE 0x0020
+#define SPR_HV_READ 0x0100
+#define SPR_HV_WRITE 0x0200
+
+#define RW 0x333
+#define RO 0x111
+#define WO 0x222
+#define OS_RW 0x330
+#define OS_RO 0x110
+#define OS_WO 0x220
+#define HV_RW 0x300
+#define HV_RO 0x100
+#define HV_WO 0x200
+
+#define SPR_ASYNC 0x1000 /* May be updated asynchronously */
+#define SPR_INT 0x2000 /* May be updated by synchronous interrupt */
+#define SPR_HARNESS 0x4000 /* Test harness uses the register */
+
+struct spr {
+ const char *name;
+ uint8_t width;
+ uint16_t access;
+ uint16_t type;
+};
+
+/* SPRs common denominator back to PowerPC Operating Environment Architecture */
+static const struct spr sprs_common[1024] = {
+ [1] = {"XER", 64, RW, SPR_HARNESS, }, /* Compiler */
+ [8] = {"LR", 64, RW, SPR_HARNESS, }, /* Compiler, mfspr/mtspr */
+ [9] = {"CTR", 64, RW, SPR_HARNESS, }, /* Compiler, mfspr/mtspr */
+ [18] = {"DSISR", 32, OS_RW, SPR_INT, },
+ [19] = {"DAR", 64, OS_RW, SPR_INT, },
+ [26] = {"SRR0", 64, OS_RW, SPR_INT, },
+ [27] = {"SRR1", 64, OS_RW, SPR_INT, },
+[268] = {"TB", 64, RO , SPR_ASYNC, },
+[269] = {"TBU", 32, RO, SPR_ASYNC, },
+[272] = {"SPRG0", 64, OS_RW, SPR_HARNESS, }, /* Int stack */
+[273] = {"SPRG1", 64, OS_RW, SPR_HARNESS, }, /* Scratch */
+[274] = {"SPRG2", 64, OS_RW, },
+[275] = {"SPRG3", 64, OS_RW, },
+[287] = {"PVR", 32, OS_RO, },
+};
+
+/* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */
+static const struct spr sprs_201[1024] = {
+ [22] = {"DEC", 32, OS_RW, SPR_ASYNC, },
+ [25] = {"SDR1", 64, HV_RW | OS_RO, },
+ [29] = {"ACCR", 64, OS_RW, },
+[136] = {"CTRL", 32, RO, },
+[152] = {"CTRL", 32, OS_WO, },
+[259] = {"SPRG3", 64, RO, },
+/* ASR, EAR omitted */
+[268] = {"TB", 64, RO, },
+[269] = {"TBU", 32, RO, },
+[284] = {"TBL", 32, HV_WO, },
+[285] = {"TBU", 32, HV_WO, },
+[310] = {"HDEC", 32, HV_RW, },
+[1013]= {"DABR", 64, HV_RW | OS_RO, },
+[1023]= {"PIR", 32, OS_RO, },
+};
+
+static const struct spr sprs_970_pmu[1024] = {
+/* POWER4+ PMU, should find PPC970 and confirm */
+[770] = {"MMCRA", 64, RO, },
+[771] = {"PMC1", 32, RO, },
+[772] = {"PMC2", 32, RO, },
+[773] = {"PMC3", 32, RO, },
+[774] = {"PMC4", 32, RO, },
+[775] = {"PMC5", 32, RO, },
+[776] = {"PMC6", 32, RO, },
+[777] = {"PMC7", 32, RO, },
+[778] = {"PMC8", 32, RO, },
+[779] = {"MMCR0", 64, RO, },
+[780] = {"SIAR", 64, RO, },
+[781] = {"SDAR", 64, RO, },
+[782] = {"MMCR1", 64, RO, },
+[786] = {"MMCRA", 64, OS_RW, },
+[787] = {"PMC1", 32, OS_RW, },
+[788] = {"PMC2", 32, OS_RW, },
+[789] = {"PMC3", 32, OS_RW, },
+[790] = {"PMC4", 32, OS_RW, },
+[791] = {"PMC5", 32, OS_RW, },
+[792] = {"PMC6", 32, OS_RW, },
+[793] = {"PMC7", 32, OS_RW, },
+[794] = {"PMC8", 32, OS_RW, },
+[795] = {"MMCR0", 64, OS_RW, },
+[796] = {"SIAR", 64, OS_RW, },
+[797] = {"SDAR", 64, OS_RW, },
+[798] = {"MMCR1", 64, OS_RW, },
+};
+
+/* These are common SPRs from 2.07S onward (POWER CPUs that support KVM HV) */
+static const struct spr sprs_power_common[1024] = {
+ [3] = {"DSCR", 64, RW, },
+ [13] = {"AMR", 64, RW, },
+ [17] = {"DSCR", 64, OS_RW, },
+ [28] = {"CFAR", 64, OS_RW, SPR_ASYNC, }, /* Effectively async */
+ [29] = {"AMR", 64, OS_RW, },
+ [61] = {"IAMR", 64, OS_RW, },
+[136] = {"CTRL", 32, RO, },
+[152] = {"CTRL", 32, OS_WO, },
+[153] = {"FSCR", 64, OS_RW, },
+[157] = {"UAMOR", 64, OS_RW, },
+[159] = {"PSPB", 32, OS_RW, },
+[176] = {"DPDES", 64, HV_RW | OS_RO, },
+[180] = {"DAWR0", 64, HV_RW, },
+[186] = {"RPR", 64, HV_RW, },
+[187] = {"CIABR", 64, HV_RW, },
+[188] = {"DAWRX0", 32, HV_RW, },
+[190] = {"HFSCR", 64, HV_RW, },
+[256] = {"VRSAVE", 32, RW, },
+[259] = {"SPRG3", 64, RO, },
+[284] = {"TBL", 32, HV_WO, },
+[285] = {"TBU", 32, HV_WO, },
+[286] = {"TBU40", 64, HV_WO, },
+[304] = {"HSPRG0", 64, HV_RW, },
+[305] = {"HSPRG1", 64, HV_RW, },
+[306] = {"HDSISR", 32, HV_RW, SPR_INT, },
+[307] = {"HDAR", 64, HV_RW, SPR_INT, },
+[308] = {"SPURR", 64, HV_RW | OS_RO, SPR_ASYNC, },
+[309] = {"PURR", 64, HV_RW | OS_RO, SPR_ASYNC, },
+[313] = {"HRMOR", 64, HV_RW, },
+[314] = {"HSRR0", 64, HV_RW, SPR_INT, },
+[315] = {"HSRR1", 64, HV_RW, SPR_INT, },
+[318] = {"LPCR", 64, HV_RW, },
+[319] = {"LPIDR", 32, HV_RW, },
+[336] = {"HMER", 64, HV_RW, },
+[337] = {"HMEER", 64, HV_RW, },
+[338] = {"PCR", 64, HV_RW, },
+[349] = {"AMOR", 64, HV_RW, },
+[446] = {"TIR", 64, OS_RO, },
+[800] = {"BESCRS", 64, RW, },
+[801] = {"BESCRSU", 32, RW, },
+[802] = {"BESCRR", 64, RW, },
+[803] = {"BESCRRU", 32, RW, },
+[804] = {"EBBHR", 64, RW, },
+[805] = {"EBBRR", 64, RW, },
+[806] = {"BESCR", 64, RW, },
+[815] = {"TAR", 64, RW, },
+[848] = {"IC", 64, HV_RW | OS_RO, SPR_ASYNC, },
+[849] = {"VTB", 64, HV_RW | OS_RO, SPR_ASYNC, },
+[896] = {"PPR", 64, RW, },
+[898] = {"PPR32", 32, RW, },
+[1023]= {"PIR", 32, OS_RO, },
+};
+
+static const struct spr sprs_tm[1024] = {
+#if 0
+ /* XXX: leave these out until enabling TM facility (and more testing) */
+[128] = {"TFHAR", 64, RW, },
+[129] = {"TFIAR", 64, RW, },
+[130] = {"TEXASR", 64, RW, },
+[131] = {"TEXASRU", 32, RW, },
+#endif
+};
+
/* SPRs from PowerISA 2.07 Book III-S */
-static void set_sprs_book3s_207(uint64_t val)
-{
- mtspr(3, val); /* DSCR */
- mtspr(13, val); /* AMR */
- mtspr(17, val); /* DSCR */
- mtspr(18, val); /* DSISR */
- mtspr(19, val); /* DAR */
- mtspr(29, val); /* AMR */
- mtspr(61, val); /* IAMR */
- // mtspr(152, val); /* CTRL */ /* TODO: Needs a fix in KVM */
- mtspr(153, val); /* FSCR */
- mtspr(157, val); /* UAMOR */
- mtspr(159, val); /* PSPB */
- mtspr(256, val); /* VRSAVE */
- // mtspr(272, val); /* SPRG0 */ /* Used by our exception handler */
- mtspr(769, val); /* MMCR2 */
- mtspr(770, val); /* MMCRA */
- mtspr(771, val); /* PMC1 */
- mtspr(772, val); /* PMC2 */
- mtspr(773, val); /* PMC3 */
- mtspr(774, val); /* PMC4 */
- mtspr(775, val); /* PMC5 */
- mtspr(776, val); /* PMC6 */
- mtspr(779, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */
- mtspr(784, val); /* SIER */
- mtspr(785, val); /* MMCR2 */
- mtspr(786, val); /* MMCRA */
- mtspr(787, val); /* PMC1 */
- mtspr(788, val); /* PMC2 */
- mtspr(789, val); /* PMC3 */
- mtspr(790, val); /* PMC4 */
- mtspr(791, val); /* PMC5 */
- mtspr(792, val); /* PMC6 */
- mtspr(795, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */
- mtspr(796, val); /* SIAR */
- mtspr(797, val); /* SDAR */
- mtspr(798, val); /* MMCR1 */
- mtspr(800, val); /* BESCRS */
- mtspr(801, val); /* BESCCRSU */
- mtspr(802, val); /* BESCRR */
- mtspr(803, val); /* BESCRRU */
- mtspr(804, val); /* EBBHR */
- mtspr(805, val); /* EBBRR */
- mtspr(806, val); /* BESCR */
- mtspr(815, val); /* TAR */
-}
+static const struct spr sprs_207[1024] = {
+ [22] = {"DEC", 32, OS_RW, SPR_ASYNC, },
+ [25] = {"SDR1", 64, HV_RW, },
+[177] = {"DHDES", 64, HV_RW, },
+[283] = {"CIR", 32, OS_RO, },
+[310] = {"HDEC", 32, HV_RW, SPR_ASYNC, },
+[312] = {"RMOR", 64, HV_RW, },
+[339] = {"HEIR", 32, HV_RW, },
+};
/* SPRs from PowerISA 3.00 Book III */
-static void set_sprs_book3s_300(uint64_t val)
-{
- set_sprs_book3s_207(val);
- mtspr(48, val); /* PIDR */
- mtspr(144, val); /* TIDR */
- mtspr(823, val); /* PSSCR */
-}
+static const struct spr sprs_300[1024] = {
+ [22] = {"DEC", 64, OS_RW, SPR_ASYNC, },
+ [48] = {"PIDR", 32, OS_RW, },
+[144] = {"TIDR", 64, OS_RW, },
+[283] = {"CIR", 32, OS_RO, },
+[310] = {"HDEC", 64, HV_RW, SPR_ASYNC, },
+[339] = {"HEIR", 32, HV_RW, },
+[464] = {"PTCR", 64, HV_RW, },
+[816] = {"ASDR", 64, HV_RW, SPR_INT},
+[823] = {"PSSCR", 64, OS_RW, },
+[855] = {"PSSCR", 64, HV_RW, },
+};
-/* SPRs from Power ISA Version 3.1B */
-static void set_sprs_book3s_31(uint64_t val)
-{
- set_sprs_book3s_207(val);
- mtspr(48, val); /* PIDR */
- /* 3.1 removes TIDR */
- mtspr(823, val); /* PSSCR */
-}
+/* SPRs from PowerISA 3.1B Book III */
+static const struct spr sprs_31[1024] = {
+ [22] = {"DEC", 64, OS_RW, SPR_ASYNC, },
+ [48] = {"PIDR", 32, OS_RW, },
+[181] = {"DAWR1", 64, HV_RW, },
+[189] = {"DAWRX1", 32, HV_RW, },
+[310] = {"HDEC", 64, HV_RW, SPR_ASYNC, },
+[339] = {"HEIR", 64, HV_RW, },
+[455] = {"HDEXCR", 32, RO, },
+[464] = {"PTCR", 64, HV_RW, },
+[468] = {"HASHKEYR", 64, OS_RW, },
+[469] = {"HASHPKEYR", 64, HV_RW, },
+[471] = {"HDEXCR", 64, HV_RW, },
+[812] = {"DEXCR", 32, RO, },
+[816] = {"ASDR", 64, HV_RW, SPR_INT, },
+[823] = {"PSSCR", 64, OS_RW, },
+[828] = {"DEXCR", 64, OS_RW, },
+[855] = {"PSSCR", 64, HV_RW, },
+};
-static void set_sprs(uint64_t val)
+/* SPRs POWER9, POWER10 User Manual */
+static const struct spr sprs_power9_10[1024] = {
+[276] = {"SPRC", 64, HV_RW, },
+[266] = {"SPRD", 64, HV_RW, },
+[317] = {"TFMR", 64, HV_RW, },
+[799] = {"IMC", 64, HV_RW, },
+[850] = {"LDBAR", 64, HV_RO, },
+[851] = {"MMCRC", 32, HV_RW, },
+[853] = {"PMSR", 32, HV_RO, },
+[861] = {"L2QOSR", 64, HV_WO, },
+[881] = {"TRIG1", 64, OS_WO, },
+[882] = {"TRIG2", 64, OS_WO, },
+[884] = {"PMCR", 64, HV_RW, },
+[885] = {"RWMR", 64, HV_RW, },
+[895] = {"WORT", 64, OS_RW, }, /* UM says 18-bits! */
+[921] = {"TSCR", 32, HV_RW, },
+[922] = {"TTR", 64, HV_RW, },
+[1006]= {"TRACE", 64, WO, },
+[1008]= {"HID", 64, HV_RW, },
+};
+
+/* This covers POWER8 and POWER9 PMUs */
+static const struct spr sprs_power_common_pmu[1024] = {
+[768] = {"SIER", 64, RO, },
+[769] = {"MMCR2", 64, RW, },
+[770] = {"MMCRA", 64, RW, },
+[771] = {"PMC1", 32, RW, },
+[772] = {"PMC2", 32, RW, },
+[773] = {"PMC3", 32, RW, },
+[774] = {"PMC4", 32, RW, },
+[775] = {"PMC5", 32, RW, },
+[776] = {"PMC6", 32, RW, },
+[779] = {"MMCR0", 64, RW, },
+[780] = {"SIAR", 64, RO, },
+[781] = {"SDAR", 64, RO, },
+[782] = {"MMCR1", 64, RO, },
+[784] = {"SIER", 64, OS_RW, },
+[785] = {"MMCR2", 64, OS_RW, },
+[786] = {"MMCRA", 64, OS_RW, },
+[787] = {"PMC1", 32, OS_RW, },
+[788] = {"PMC2", 32, OS_RW, },
+[789] = {"PMC3", 32, OS_RW, },
+[790] = {"PMC4", 32, OS_RW, },
+[791] = {"PMC5", 32, OS_RW, },
+[792] = {"PMC6", 32, OS_RW, },
+[795] = {"MMCR0", 64, OS_RW, },
+[796] = {"SIAR", 64, OS_RW, },
+[797] = {"SDAR", 64, OS_RW, },
+[798] = {"MMCR1", 64, OS_RW, },
+};
+
+static const struct spr sprs_power10_pmu[1024] = {
+[736] = {"SEIR2", 64, RO, },
+[737] = {"SEIR3", 64, RO, },
+[738] = {"MMCR3", 64, RO, },
+[752] = {"SEIR2", 64, OS_RW, },
+[753] = {"SEIR3", 64, OS_RW, },
+[754] = {"MMCR3", 64, OS_RW, },
+};
+
+static struct spr sprs[1024];
+
+static void setup_sprs(void)
{
uint32_t pvr = mfspr(287); /* Processor Version Register */
+ int i;
- set_sprs_common(val);
+ for (i = 0; i < 1024; i++) {
+ if (sprs_common[i].name) {
+ memcpy(&sprs[i], &sprs_common[i], sizeof(struct spr));
+ }
+ }
switch (pvr >> 16) {
case 0x39: /* PPC970 */
case 0x3C: /* PPC970FX */
case 0x44: /* PPC970MP */
- set_sprs_book3s_201(val);
+ for (i = 0; i < 1024; i++) {
+ if (sprs_power_common[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr));
+ }
+ if (sprs_201[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_201[i], sizeof(struct spr));
+ }
+ if (sprs_970_pmu[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr));
+ }
+ }
break;
+
case 0x4b: /* POWER8E */
case 0x4c: /* POWER8NVL */
case 0x4d: /* POWER8 */
- set_sprs_book3s_207(val);
+ for (i = 0; i < 1024; i++) {
+ if (sprs_power_common[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr));
+ }
+ if (sprs_207[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_207[i], sizeof(struct spr));
+ }
+ if (sprs_tm[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_tm[i], sizeof(struct spr));
+ }
+ if (sprs_power_common_pmu[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr));
+ }
+ }
break;
+
case 0x4e: /* POWER9 */
- set_sprs_book3s_300(val);
+ for (i = 0; i < 1024; i++) {
+ if (sprs_power_common[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr));
+ }
+ if (sprs_300[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_300[i], sizeof(struct spr));
+ }
+ if (sprs_tm[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_tm[i], sizeof(struct spr));
+ }
+ if (sprs_power9_10[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power9_10[i], sizeof(struct spr));
+ }
+ if (sprs_power_common_pmu[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr));
+ }
+ }
break;
- case 0x80: /* POWER10 */
- set_sprs_book3s_31(val);
+
+ case 0x80: /* POWER10 */
+ for (i = 0; i < 1024; i++) {
+ if (sprs_power_common[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr));
+ }
+ if (sprs_31[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_31[i], sizeof(struct spr));
+ }
+ if (sprs_power9_10[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power9_10[i], sizeof(struct spr));
+ }
+ if (sprs_power_common_pmu[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr));
+ }
+ if (sprs_power10_pmu[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power10_pmu[i], sizeof(struct spr));
+ }
+ }
break;
+
default:
- puts("Warning: Unknown processor version!\n");
+ memcpy(sprs, sprs_common, sizeof(sprs));
+ puts("Warning: Unknown processor version, falling back to common SPRs!\n");
+ break;
}
}
-static void get_sprs_common(uint64_t *v)
-{
- v[9] = mfspr(9); /* CTR */
- // v[273] = mfspr(273); /* SPRG1 */ /* Used by our exception handler */
- v[274] = mfspr(274); /* SPRG2 */
- v[275] = mfspr(275); /* SPRG3 */
-}
-
-static void get_sprs_book3s_201(uint64_t *v)
-{
- v[18] = mfspr(18); /* DSISR */
- v[19] = mfspr(19); /* DAR */
- v[136] = mfspr(136); /* CTRL */
- v[256] = mfspr(256); /* VRSAVE */
- v[786] = mfspr(786); /* MMCRA */
- v[795] = mfspr(795); /* MMCR0 */
- v[798] = mfspr(798); /* MMCR1 */
-}
-
-static void get_sprs_book3s_207(uint64_t *v)
-{
- v[3] = mfspr(3); /* DSCR */
- v[13] = mfspr(13); /* AMR */
- v[17] = mfspr(17); /* DSCR */
- v[18] = mfspr(18); /* DSISR */
- v[19] = mfspr(19); /* DAR */
- v[29] = mfspr(29); /* AMR */
- v[61] = mfspr(61); /* IAMR */
- // v[136] = mfspr(136); /* CTRL */ /* TODO: Needs a fix in KVM */
- v[153] = mfspr(153); /* FSCR */
- v[157] = mfspr(157); /* UAMOR */
- v[159] = mfspr(159); /* PSPB */
- v[256] = mfspr(256); /* VRSAVE */
- v[259] = mfspr(259); /* SPRG3 (read only) */
- // v[272] = mfspr(272); /* SPRG0 */ /* Used by our exception handler */
- v[769] = mfspr(769); /* MMCR2 */
- v[770] = mfspr(770); /* MMCRA */
- v[771] = mfspr(771); /* PMC1 */
- v[772] = mfspr(772); /* PMC2 */
- v[773] = mfspr(773); /* PMC3 */
- v[774] = mfspr(774); /* PMC4 */
- v[775] = mfspr(775); /* PMC5 */
- v[776] = mfspr(776); /* PMC6 */
- v[779] = mfspr(779); /* MMCR0 */
- v[780] = mfspr(780); /* SIAR (read only) */
- v[781] = mfspr(781); /* SDAR (read only) */
- v[782] = mfspr(782); /* MMCR1 (read only) */
- v[784] = mfspr(784); /* SIER */
- v[785] = mfspr(785); /* MMCR2 */
- v[786] = mfspr(786); /* MMCRA */
- v[787] = mfspr(787); /* PMC1 */
- v[788] = mfspr(788); /* PMC2 */
- v[789] = mfspr(789); /* PMC3 */
- v[790] = mfspr(790); /* PMC4 */
- v[791] = mfspr(791); /* PMC5 */
- v[792] = mfspr(792); /* PMC6 */
- v[795] = mfspr(795); /* MMCR0 */
- v[796] = mfspr(796); /* SIAR */
- v[797] = mfspr(797); /* SDAR */
- v[798] = mfspr(798); /* MMCR1 */
- v[800] = mfspr(800); /* BESCRS */
- v[801] = mfspr(801); /* BESCCRSU */
- v[802] = mfspr(802); /* BESCRR */
- v[803] = mfspr(803); /* BESCRRU */
- v[804] = mfspr(804); /* EBBHR */
- v[805] = mfspr(805); /* EBBRR */
- v[806] = mfspr(806); /* BESCR */
- v[815] = mfspr(815); /* TAR */
-}
-
-static void get_sprs_book3s_300(uint64_t *v)
+static void get_sprs(uint64_t *v)
{
- get_sprs_book3s_207(v);
- v[48] = mfspr(48); /* PIDR */
- v[144] = mfspr(144); /* TIDR */
- v[823] = mfspr(823); /* PSSCR */
-}
+ int i;
-static void get_sprs_book3s_31(uint64_t *v)
-{
- get_sprs_book3s_207(v);
- v[48] = mfspr(48); /* PIDR */
- v[823] = mfspr(823); /* PSSCR */
+ for (i = 0; i < 1024; i++) {
+ if (!(sprs[i].access & SPR_OS_READ))
+ continue;
+ v[i] = __mfspr(i);
+ }
}
-static void get_sprs(uint64_t *v)
+static void set_sprs(uint64_t val)
{
- uint32_t pvr = mfspr(287); /* Processor Version Register */
-
- get_sprs_common(v);
+ int i;
- switch (pvr >> 16) {
- case 0x39: /* PPC970 */
- case 0x3C: /* PPC970FX */
- case 0x44: /* PPC970MP */
- get_sprs_book3s_201(v);
- break;
- case 0x4b: /* POWER8E */
- case 0x4c: /* POWER8NVL */
- case 0x4d: /* POWER8 */
- get_sprs_book3s_207(v);
- break;
- case 0x4e: /* POWER9 */
- get_sprs_book3s_300(v);
- break;
- case 0x80: /* POWER10 */
- get_sprs_book3s_31(v);
- break;
+ for (i = 0; i < 1024; i++) {
+ if (!(sprs[i].access & SPR_OS_WRITE))
+ continue;
+ if (sprs[i].type & SPR_HARNESS)
+ continue;
+ if (!strcmp(sprs[i].name, "MMCR0")) {
+ /* XXX: could use a comment or better abstraction! */
+ __mtspr(i, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070);
+ } else {
+ __mtspr(i, val);
+ }
}
}
@@ -289,7 +523,9 @@ int main(int argc, char **argv)
}
}
- printf("Settings SPRs to %#lx...\n", pat);
+ setup_sprs();
+
+ printf("Setting SPRs to 0x%lx...\n", pat);
set_sprs(pat);
memset(before, 0, sizeof(before));
@@ -301,16 +537,37 @@ int main(int argc, char **argv)
migrate_once();
} else {
msleep(2000);
+
+ /* Taking a dec updates SRR0, SRR1, SPRG1, so don't fail. */
+ sprs[26].type |= SPR_ASYNC;
+ sprs[27].type |= SPR_ASYNC;
+ sprs[273].type |= SPR_ASYNC;
}
get_sprs(after);
puts("Checking SPRs...\n");
for (i = 0; i < 1024; i++) {
- if (before[i] != 0 || after[i] != 0)
- report(before[i] == after[i],
- "SPR %d:\t%#018lx <==> %#018lx", i, before[i],
- after[i]);
+ bool pass = true;
+
+ if (!(sprs[i].access & SPR_OS_READ))
+ continue;
+
+ if (sprs[i].width == 32) {
+ if (before[i] >> 32)
+ pass = false;
+ }
+ if (!(sprs[i].type & SPR_ASYNC) && (before[i] != after[i]))
+ pass = false;
+
+ if (sprs[i].width == 32 && !(before[i] >> 32) && !(after[i] >> 32))
+ report(pass, "%-10s(%4d):\t 0x%08lx <==> 0x%08lx",
+ sprs[i].name, i,
+ before[i], after[i]);
+ else
+ report(pass, "%-10s(%4d):\t0x%016lx <==> 0x%016lx",
+ sprs[i].name, i,
+ before[i], after[i]);
}
return report_summary();
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 06/12] powerpc/sprs: Specify SPRs with data rather than code
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
A significant rework that builds an array of 'struct spr', where each
element describes an SPR. This makes various metadata about the SPR
like name and access type easier to carry and use.
Hypervisor privileged registers are described despite not being used
at the moment for completeness, but also the code might one day be
reused for a hypervisor-privileged test.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
This ended up a little over-engineered perhaps, but there are lots of
SPRs, lots of access types, lots of changes between processor and ISA
versions, and lots of places they are implemented and used, so lots of
room for mistakes. There is not a good system in place to easily
see that userspace, supervisor, etc., switches perform all the right
SPR context switching so this is a nice test case to have. The sprs test
quickly caught a few QEMU TCG SPR bugs which really motivated me to
improve the SPR coverage.
---
powerpc/sprs.c | 643 ++++++++++++++++++++++++++++++++++---------------
1 file changed, 450 insertions(+), 193 deletions(-)
diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index 57e487ce..d5664201 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -28,231 +28,465 @@
#include <asm/processor.h>
#include <asm/barrier.h>
-uint64_t before[1024], after[1024];
-
-/* Common SPRs for all PowerPC CPUs */
-static void set_sprs_common(uint64_t val)
+/* "Indirect" mfspr/mtspr which accept a non-constant spr number */
+static uint64_t __mfspr(unsigned spr)
{
- mtspr(9, val); /* CTR */
- // mtspr(273, val); /* SPRG1 */ /* Used by our exception handler */
- mtspr(274, val); /* SPRG2 */
- mtspr(275, val); /* SPRG3 */
+ uint64_t tmp;
+ uint64_t ret;
+
+ asm volatile(
+" bcl 20, 31, 1f \n"
+"1: mflr %0 \n"
+" addi %0, %0, (2f-1b) \n"
+" add %0, %0, %2 \n"
+" mtctr %0 \n"
+" bctr \n"
+"2: \n"
+".LSPR=0 \n"
+".rept 1024 \n"
+" mfspr %1, .LSPR \n"
+" b 3f \n"
+" .LSPR=.LSPR+1 \n"
+".endr \n"
+"3: \n"
+ : "=&r"(tmp),
+ "=r"(ret)
+ : "r"(spr*8) /* 8 bytes per 'mfspr ; b' block */
+ : "lr", "ctr");
+
+ return ret;
}
-/* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */
-static void set_sprs_book3s_201(uint64_t val)
+static void __mtspr(unsigned spr, uint64_t val)
{
- mtspr(18, val); /* DSISR */
- mtspr(19, val); /* DAR */
- mtspr(152, val); /* CTRL */
- mtspr(256, val); /* VRSAVE */
- mtspr(786, val); /* MMCRA */
- mtspr(795, val); /* MMCR0 */
- mtspr(798, val); /* MMCR1 */
+ uint64_t tmp;
+
+ asm volatile(
+" bcl 20, 31, 1f \n"
+"1: mflr %0 \n"
+" addi %0, %0, (2f-1b) \n"
+" add %0, %0, %2 \n"
+" mtctr %0 \n"
+" bctr \n"
+"2: \n"
+".LSPR=0 \n"
+".rept 1024 \n"
+" mtspr .LSPR, %1 \n"
+" b 3f \n"
+" .LSPR=.LSPR+1 \n"
+".endr \n"
+"3: \n"
+ : "=&r"(tmp)
+ : "r"(val),
+ "r"(spr*8) /* 8 bytes per 'mfspr ; b' block */
+ : "lr", "ctr", "xer");
}
+static uint64_t before[1024], after[1024];
+
+#define SPR_PR_READ 0x0001
+#define SPR_PR_WRITE 0x0002
+#define SPR_OS_READ 0x0010
+#define SPR_OS_WRITE 0x0020
+#define SPR_HV_READ 0x0100
+#define SPR_HV_WRITE 0x0200
+
+#define RW 0x333
+#define RO 0x111
+#define WO 0x222
+#define OS_RW 0x330
+#define OS_RO 0x110
+#define OS_WO 0x220
+#define HV_RW 0x300
+#define HV_RO 0x100
+#define HV_WO 0x200
+
+#define SPR_ASYNC 0x1000 /* May be updated asynchronously */
+#define SPR_INT 0x2000 /* May be updated by synchronous interrupt */
+#define SPR_HARNESS 0x4000 /* Test harness uses the register */
+
+struct spr {
+ const char *name;
+ uint8_t width;
+ uint16_t access;
+ uint16_t type;
+};
+
+/* SPRs common denominator back to PowerPC Operating Environment Architecture */
+static const struct spr sprs_common[1024] = {
+ [1] = {"XER", 64, RW, SPR_HARNESS, }, /* Compiler */
+ [8] = {"LR", 64, RW, SPR_HARNESS, }, /* Compiler, mfspr/mtspr */
+ [9] = {"CTR", 64, RW, SPR_HARNESS, }, /* Compiler, mfspr/mtspr */
+ [18] = {"DSISR", 32, OS_RW, SPR_INT, },
+ [19] = {"DAR", 64, OS_RW, SPR_INT, },
+ [26] = {"SRR0", 64, OS_RW, SPR_INT, },
+ [27] = {"SRR1", 64, OS_RW, SPR_INT, },
+[268] = {"TB", 64, RO , SPR_ASYNC, },
+[269] = {"TBU", 32, RO, SPR_ASYNC, },
+[272] = {"SPRG0", 64, OS_RW, SPR_HARNESS, }, /* Int stack */
+[273] = {"SPRG1", 64, OS_RW, SPR_HARNESS, }, /* Scratch */
+[274] = {"SPRG2", 64, OS_RW, },
+[275] = {"SPRG3", 64, OS_RW, },
+[287] = {"PVR", 32, OS_RO, },
+};
+
+/* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */
+static const struct spr sprs_201[1024] = {
+ [22] = {"DEC", 32, OS_RW, SPR_ASYNC, },
+ [25] = {"SDR1", 64, HV_RW | OS_RO, },
+ [29] = {"ACCR", 64, OS_RW, },
+[136] = {"CTRL", 32, RO, },
+[152] = {"CTRL", 32, OS_WO, },
+[259] = {"SPRG3", 64, RO, },
+/* ASR, EAR omitted */
+[268] = {"TB", 64, RO, },
+[269] = {"TBU", 32, RO, },
+[284] = {"TBL", 32, HV_WO, },
+[285] = {"TBU", 32, HV_WO, },
+[310] = {"HDEC", 32, HV_RW, },
+[1013]= {"DABR", 64, HV_RW | OS_RO, },
+[1023]= {"PIR", 32, OS_RO, },
+};
+
+static const struct spr sprs_970_pmu[1024] = {
+/* POWER4+ PMU, should find PPC970 and confirm */
+[770] = {"MMCRA", 64, RO, },
+[771] = {"PMC1", 32, RO, },
+[772] = {"PMC2", 32, RO, },
+[773] = {"PMC3", 32, RO, },
+[774] = {"PMC4", 32, RO, },
+[775] = {"PMC5", 32, RO, },
+[776] = {"PMC6", 32, RO, },
+[777] = {"PMC7", 32, RO, },
+[778] = {"PMC8", 32, RO, },
+[779] = {"MMCR0", 64, RO, },
+[780] = {"SIAR", 64, RO, },
+[781] = {"SDAR", 64, RO, },
+[782] = {"MMCR1", 64, RO, },
+[786] = {"MMCRA", 64, OS_RW, },
+[787] = {"PMC1", 32, OS_RW, },
+[788] = {"PMC2", 32, OS_RW, },
+[789] = {"PMC3", 32, OS_RW, },
+[790] = {"PMC4", 32, OS_RW, },
+[791] = {"PMC5", 32, OS_RW, },
+[792] = {"PMC6", 32, OS_RW, },
+[793] = {"PMC7", 32, OS_RW, },
+[794] = {"PMC8", 32, OS_RW, },
+[795] = {"MMCR0", 64, OS_RW, },
+[796] = {"SIAR", 64, OS_RW, },
+[797] = {"SDAR", 64, OS_RW, },
+[798] = {"MMCR1", 64, OS_RW, },
+};
+
+/* These are common SPRs from 2.07S onward (POWER CPUs that support KVM HV) */
+static const struct spr sprs_power_common[1024] = {
+ [3] = {"DSCR", 64, RW, },
+ [13] = {"AMR", 64, RW, },
+ [17] = {"DSCR", 64, OS_RW, },
+ [28] = {"CFAR", 64, OS_RW, SPR_ASYNC, }, /* Effectively async */
+ [29] = {"AMR", 64, OS_RW, },
+ [61] = {"IAMR", 64, OS_RW, },
+[136] = {"CTRL", 32, RO, },
+[152] = {"CTRL", 32, OS_WO, },
+[153] = {"FSCR", 64, OS_RW, },
+[157] = {"UAMOR", 64, OS_RW, },
+[159] = {"PSPB", 32, OS_RW, },
+[176] = {"DPDES", 64, HV_RW | OS_RO, },
+[180] = {"DAWR0", 64, HV_RW, },
+[186] = {"RPR", 64, HV_RW, },
+[187] = {"CIABR", 64, HV_RW, },
+[188] = {"DAWRX0", 32, HV_RW, },
+[190] = {"HFSCR", 64, HV_RW, },
+[256] = {"VRSAVE", 32, RW, },
+[259] = {"SPRG3", 64, RO, },
+[284] = {"TBL", 32, HV_WO, },
+[285] = {"TBU", 32, HV_WO, },
+[286] = {"TBU40", 64, HV_WO, },
+[304] = {"HSPRG0", 64, HV_RW, },
+[305] = {"HSPRG1", 64, HV_RW, },
+[306] = {"HDSISR", 32, HV_RW, SPR_INT, },
+[307] = {"HDAR", 64, HV_RW, SPR_INT, },
+[308] = {"SPURR", 64, HV_RW | OS_RO, SPR_ASYNC, },
+[309] = {"PURR", 64, HV_RW | OS_RO, SPR_ASYNC, },
+[313] = {"HRMOR", 64, HV_RW, },
+[314] = {"HSRR0", 64, HV_RW, SPR_INT, },
+[315] = {"HSRR1", 64, HV_RW, SPR_INT, },
+[318] = {"LPCR", 64, HV_RW, },
+[319] = {"LPIDR", 32, HV_RW, },
+[336] = {"HMER", 64, HV_RW, },
+[337] = {"HMEER", 64, HV_RW, },
+[338] = {"PCR", 64, HV_RW, },
+[349] = {"AMOR", 64, HV_RW, },
+[446] = {"TIR", 64, OS_RO, },
+[800] = {"BESCRS", 64, RW, },
+[801] = {"BESCRSU", 32, RW, },
+[802] = {"BESCRR", 64, RW, },
+[803] = {"BESCRRU", 32, RW, },
+[804] = {"EBBHR", 64, RW, },
+[805] = {"EBBRR", 64, RW, },
+[806] = {"BESCR", 64, RW, },
+[815] = {"TAR", 64, RW, },
+[848] = {"IC", 64, HV_RW | OS_RO, SPR_ASYNC, },
+[849] = {"VTB", 64, HV_RW | OS_RO, SPR_ASYNC, },
+[896] = {"PPR", 64, RW, },
+[898] = {"PPR32", 32, RW, },
+[1023]= {"PIR", 32, OS_RO, },
+};
+
+static const struct spr sprs_tm[1024] = {
+#if 0
+ /* XXX: leave these out until enabling TM facility (and more testing) */
+[128] = {"TFHAR", 64, RW, },
+[129] = {"TFIAR", 64, RW, },
+[130] = {"TEXASR", 64, RW, },
+[131] = {"TEXASRU", 32, RW, },
+#endif
+};
+
/* SPRs from PowerISA 2.07 Book III-S */
-static void set_sprs_book3s_207(uint64_t val)
-{
- mtspr(3, val); /* DSCR */
- mtspr(13, val); /* AMR */
- mtspr(17, val); /* DSCR */
- mtspr(18, val); /* DSISR */
- mtspr(19, val); /* DAR */
- mtspr(29, val); /* AMR */
- mtspr(61, val); /* IAMR */
- // mtspr(152, val); /* CTRL */ /* TODO: Needs a fix in KVM */
- mtspr(153, val); /* FSCR */
- mtspr(157, val); /* UAMOR */
- mtspr(159, val); /* PSPB */
- mtspr(256, val); /* VRSAVE */
- // mtspr(272, val); /* SPRG0 */ /* Used by our exception handler */
- mtspr(769, val); /* MMCR2 */
- mtspr(770, val); /* MMCRA */
- mtspr(771, val); /* PMC1 */
- mtspr(772, val); /* PMC2 */
- mtspr(773, val); /* PMC3 */
- mtspr(774, val); /* PMC4 */
- mtspr(775, val); /* PMC5 */
- mtspr(776, val); /* PMC6 */
- mtspr(779, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */
- mtspr(784, val); /* SIER */
- mtspr(785, val); /* MMCR2 */
- mtspr(786, val); /* MMCRA */
- mtspr(787, val); /* PMC1 */
- mtspr(788, val); /* PMC2 */
- mtspr(789, val); /* PMC3 */
- mtspr(790, val); /* PMC4 */
- mtspr(791, val); /* PMC5 */
- mtspr(792, val); /* PMC6 */
- mtspr(795, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */
- mtspr(796, val); /* SIAR */
- mtspr(797, val); /* SDAR */
- mtspr(798, val); /* MMCR1 */
- mtspr(800, val); /* BESCRS */
- mtspr(801, val); /* BESCCRSU */
- mtspr(802, val); /* BESCRR */
- mtspr(803, val); /* BESCRRU */
- mtspr(804, val); /* EBBHR */
- mtspr(805, val); /* EBBRR */
- mtspr(806, val); /* BESCR */
- mtspr(815, val); /* TAR */
-}
+static const struct spr sprs_207[1024] = {
+ [22] = {"DEC", 32, OS_RW, SPR_ASYNC, },
+ [25] = {"SDR1", 64, HV_RW, },
+[177] = {"DHDES", 64, HV_RW, },
+[283] = {"CIR", 32, OS_RO, },
+[310] = {"HDEC", 32, HV_RW, SPR_ASYNC, },
+[312] = {"RMOR", 64, HV_RW, },
+[339] = {"HEIR", 32, HV_RW, },
+};
/* SPRs from PowerISA 3.00 Book III */
-static void set_sprs_book3s_300(uint64_t val)
-{
- set_sprs_book3s_207(val);
- mtspr(48, val); /* PIDR */
- mtspr(144, val); /* TIDR */
- mtspr(823, val); /* PSSCR */
-}
+static const struct spr sprs_300[1024] = {
+ [22] = {"DEC", 64, OS_RW, SPR_ASYNC, },
+ [48] = {"PIDR", 32, OS_RW, },
+[144] = {"TIDR", 64, OS_RW, },
+[283] = {"CIR", 32, OS_RO, },
+[310] = {"HDEC", 64, HV_RW, SPR_ASYNC, },
+[339] = {"HEIR", 32, HV_RW, },
+[464] = {"PTCR", 64, HV_RW, },
+[816] = {"ASDR", 64, HV_RW, SPR_INT},
+[823] = {"PSSCR", 64, OS_RW, },
+[855] = {"PSSCR", 64, HV_RW, },
+};
-/* SPRs from Power ISA Version 3.1B */
-static void set_sprs_book3s_31(uint64_t val)
-{
- set_sprs_book3s_207(val);
- mtspr(48, val); /* PIDR */
- /* 3.1 removes TIDR */
- mtspr(823, val); /* PSSCR */
-}
+/* SPRs from PowerISA 3.1B Book III */
+static const struct spr sprs_31[1024] = {
+ [22] = {"DEC", 64, OS_RW, SPR_ASYNC, },
+ [48] = {"PIDR", 32, OS_RW, },
+[181] = {"DAWR1", 64, HV_RW, },
+[189] = {"DAWRX1", 32, HV_RW, },
+[310] = {"HDEC", 64, HV_RW, SPR_ASYNC, },
+[339] = {"HEIR", 64, HV_RW, },
+[455] = {"HDEXCR", 32, RO, },
+[464] = {"PTCR", 64, HV_RW, },
+[468] = {"HASHKEYR", 64, OS_RW, },
+[469] = {"HASHPKEYR", 64, HV_RW, },
+[471] = {"HDEXCR", 64, HV_RW, },
+[812] = {"DEXCR", 32, RO, },
+[816] = {"ASDR", 64, HV_RW, SPR_INT, },
+[823] = {"PSSCR", 64, OS_RW, },
+[828] = {"DEXCR", 64, OS_RW, },
+[855] = {"PSSCR", 64, HV_RW, },
+};
-static void set_sprs(uint64_t val)
+/* SPRs POWER9, POWER10 User Manual */
+static const struct spr sprs_power9_10[1024] = {
+[276] = {"SPRC", 64, HV_RW, },
+[266] = {"SPRD", 64, HV_RW, },
+[317] = {"TFMR", 64, HV_RW, },
+[799] = {"IMC", 64, HV_RW, },
+[850] = {"LDBAR", 64, HV_RO, },
+[851] = {"MMCRC", 32, HV_RW, },
+[853] = {"PMSR", 32, HV_RO, },
+[861] = {"L2QOSR", 64, HV_WO, },
+[881] = {"TRIG1", 64, OS_WO, },
+[882] = {"TRIG2", 64, OS_WO, },
+[884] = {"PMCR", 64, HV_RW, },
+[885] = {"RWMR", 64, HV_RW, },
+[895] = {"WORT", 64, OS_RW, }, /* UM says 18-bits! */
+[921] = {"TSCR", 32, HV_RW, },
+[922] = {"TTR", 64, HV_RW, },
+[1006]= {"TRACE", 64, WO, },
+[1008]= {"HID", 64, HV_RW, },
+};
+
+/* This covers POWER8 and POWER9 PMUs */
+static const struct spr sprs_power_common_pmu[1024] = {
+[768] = {"SIER", 64, RO, },
+[769] = {"MMCR2", 64, RW, },
+[770] = {"MMCRA", 64, RW, },
+[771] = {"PMC1", 32, RW, },
+[772] = {"PMC2", 32, RW, },
+[773] = {"PMC3", 32, RW, },
+[774] = {"PMC4", 32, RW, },
+[775] = {"PMC5", 32, RW, },
+[776] = {"PMC6", 32, RW, },
+[779] = {"MMCR0", 64, RW, },
+[780] = {"SIAR", 64, RO, },
+[781] = {"SDAR", 64, RO, },
+[782] = {"MMCR1", 64, RO, },
+[784] = {"SIER", 64, OS_RW, },
+[785] = {"MMCR2", 64, OS_RW, },
+[786] = {"MMCRA", 64, OS_RW, },
+[787] = {"PMC1", 32, OS_RW, },
+[788] = {"PMC2", 32, OS_RW, },
+[789] = {"PMC3", 32, OS_RW, },
+[790] = {"PMC4", 32, OS_RW, },
+[791] = {"PMC5", 32, OS_RW, },
+[792] = {"PMC6", 32, OS_RW, },
+[795] = {"MMCR0", 64, OS_RW, },
+[796] = {"SIAR", 64, OS_RW, },
+[797] = {"SDAR", 64, OS_RW, },
+[798] = {"MMCR1", 64, OS_RW, },
+};
+
+static const struct spr sprs_power10_pmu[1024] = {
+[736] = {"SEIR2", 64, RO, },
+[737] = {"SEIR3", 64, RO, },
+[738] = {"MMCR3", 64, RO, },
+[752] = {"SEIR2", 64, OS_RW, },
+[753] = {"SEIR3", 64, OS_RW, },
+[754] = {"MMCR3", 64, OS_RW, },
+};
+
+static struct spr sprs[1024];
+
+static void setup_sprs(void)
{
uint32_t pvr = mfspr(287); /* Processor Version Register */
+ int i;
- set_sprs_common(val);
+ for (i = 0; i < 1024; i++) {
+ if (sprs_common[i].name) {
+ memcpy(&sprs[i], &sprs_common[i], sizeof(struct spr));
+ }
+ }
switch (pvr >> 16) {
case 0x39: /* PPC970 */
case 0x3C: /* PPC970FX */
case 0x44: /* PPC970MP */
- set_sprs_book3s_201(val);
+ for (i = 0; i < 1024; i++) {
+ if (sprs_power_common[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr));
+ }
+ if (sprs_201[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_201[i], sizeof(struct spr));
+ }
+ if (sprs_970_pmu[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr));
+ }
+ }
break;
+
case 0x4b: /* POWER8E */
case 0x4c: /* POWER8NVL */
case 0x4d: /* POWER8 */
- set_sprs_book3s_207(val);
+ for (i = 0; i < 1024; i++) {
+ if (sprs_power_common[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr));
+ }
+ if (sprs_207[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_207[i], sizeof(struct spr));
+ }
+ if (sprs_tm[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_tm[i], sizeof(struct spr));
+ }
+ if (sprs_power_common_pmu[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr));
+ }
+ }
break;
+
case 0x4e: /* POWER9 */
- set_sprs_book3s_300(val);
+ for (i = 0; i < 1024; i++) {
+ if (sprs_power_common[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr));
+ }
+ if (sprs_300[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_300[i], sizeof(struct spr));
+ }
+ if (sprs_tm[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_tm[i], sizeof(struct spr));
+ }
+ if (sprs_power9_10[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power9_10[i], sizeof(struct spr));
+ }
+ if (sprs_power_common_pmu[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr));
+ }
+ }
break;
- case 0x80: /* POWER10 */
- set_sprs_book3s_31(val);
+
+ case 0x80: /* POWER10 */
+ for (i = 0; i < 1024; i++) {
+ if (sprs_power_common[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr));
+ }
+ if (sprs_31[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_31[i], sizeof(struct spr));
+ }
+ if (sprs_power9_10[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power9_10[i], sizeof(struct spr));
+ }
+ if (sprs_power_common_pmu[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr));
+ }
+ if (sprs_power10_pmu[i].name) {
+ assert(!sprs[i].name);
+ memcpy(&sprs[i], &sprs_power10_pmu[i], sizeof(struct spr));
+ }
+ }
break;
+
default:
- puts("Warning: Unknown processor version!\n");
+ memcpy(sprs, sprs_common, sizeof(sprs));
+ puts("Warning: Unknown processor version, falling back to common SPRs!\n");
+ break;
}
}
-static void get_sprs_common(uint64_t *v)
-{
- v[9] = mfspr(9); /* CTR */
- // v[273] = mfspr(273); /* SPRG1 */ /* Used by our exception handler */
- v[274] = mfspr(274); /* SPRG2 */
- v[275] = mfspr(275); /* SPRG3 */
-}
-
-static void get_sprs_book3s_201(uint64_t *v)
-{
- v[18] = mfspr(18); /* DSISR */
- v[19] = mfspr(19); /* DAR */
- v[136] = mfspr(136); /* CTRL */
- v[256] = mfspr(256); /* VRSAVE */
- v[786] = mfspr(786); /* MMCRA */
- v[795] = mfspr(795); /* MMCR0 */
- v[798] = mfspr(798); /* MMCR1 */
-}
-
-static void get_sprs_book3s_207(uint64_t *v)
-{
- v[3] = mfspr(3); /* DSCR */
- v[13] = mfspr(13); /* AMR */
- v[17] = mfspr(17); /* DSCR */
- v[18] = mfspr(18); /* DSISR */
- v[19] = mfspr(19); /* DAR */
- v[29] = mfspr(29); /* AMR */
- v[61] = mfspr(61); /* IAMR */
- // v[136] = mfspr(136); /* CTRL */ /* TODO: Needs a fix in KVM */
- v[153] = mfspr(153); /* FSCR */
- v[157] = mfspr(157); /* UAMOR */
- v[159] = mfspr(159); /* PSPB */
- v[256] = mfspr(256); /* VRSAVE */
- v[259] = mfspr(259); /* SPRG3 (read only) */
- // v[272] = mfspr(272); /* SPRG0 */ /* Used by our exception handler */
- v[769] = mfspr(769); /* MMCR2 */
- v[770] = mfspr(770); /* MMCRA */
- v[771] = mfspr(771); /* PMC1 */
- v[772] = mfspr(772); /* PMC2 */
- v[773] = mfspr(773); /* PMC3 */
- v[774] = mfspr(774); /* PMC4 */
- v[775] = mfspr(775); /* PMC5 */
- v[776] = mfspr(776); /* PMC6 */
- v[779] = mfspr(779); /* MMCR0 */
- v[780] = mfspr(780); /* SIAR (read only) */
- v[781] = mfspr(781); /* SDAR (read only) */
- v[782] = mfspr(782); /* MMCR1 (read only) */
- v[784] = mfspr(784); /* SIER */
- v[785] = mfspr(785); /* MMCR2 */
- v[786] = mfspr(786); /* MMCRA */
- v[787] = mfspr(787); /* PMC1 */
- v[788] = mfspr(788); /* PMC2 */
- v[789] = mfspr(789); /* PMC3 */
- v[790] = mfspr(790); /* PMC4 */
- v[791] = mfspr(791); /* PMC5 */
- v[792] = mfspr(792); /* PMC6 */
- v[795] = mfspr(795); /* MMCR0 */
- v[796] = mfspr(796); /* SIAR */
- v[797] = mfspr(797); /* SDAR */
- v[798] = mfspr(798); /* MMCR1 */
- v[800] = mfspr(800); /* BESCRS */
- v[801] = mfspr(801); /* BESCCRSU */
- v[802] = mfspr(802); /* BESCRR */
- v[803] = mfspr(803); /* BESCRRU */
- v[804] = mfspr(804); /* EBBHR */
- v[805] = mfspr(805); /* EBBRR */
- v[806] = mfspr(806); /* BESCR */
- v[815] = mfspr(815); /* TAR */
-}
-
-static void get_sprs_book3s_300(uint64_t *v)
+static void get_sprs(uint64_t *v)
{
- get_sprs_book3s_207(v);
- v[48] = mfspr(48); /* PIDR */
- v[144] = mfspr(144); /* TIDR */
- v[823] = mfspr(823); /* PSSCR */
-}
+ int i;
-static void get_sprs_book3s_31(uint64_t *v)
-{
- get_sprs_book3s_207(v);
- v[48] = mfspr(48); /* PIDR */
- v[823] = mfspr(823); /* PSSCR */
+ for (i = 0; i < 1024; i++) {
+ if (!(sprs[i].access & SPR_OS_READ))
+ continue;
+ v[i] = __mfspr(i);
+ }
}
-static void get_sprs(uint64_t *v)
+static void set_sprs(uint64_t val)
{
- uint32_t pvr = mfspr(287); /* Processor Version Register */
-
- get_sprs_common(v);
+ int i;
- switch (pvr >> 16) {
- case 0x39: /* PPC970 */
- case 0x3C: /* PPC970FX */
- case 0x44: /* PPC970MP */
- get_sprs_book3s_201(v);
- break;
- case 0x4b: /* POWER8E */
- case 0x4c: /* POWER8NVL */
- case 0x4d: /* POWER8 */
- get_sprs_book3s_207(v);
- break;
- case 0x4e: /* POWER9 */
- get_sprs_book3s_300(v);
- break;
- case 0x80: /* POWER10 */
- get_sprs_book3s_31(v);
- break;
+ for (i = 0; i < 1024; i++) {
+ if (!(sprs[i].access & SPR_OS_WRITE))
+ continue;
+ if (sprs[i].type & SPR_HARNESS)
+ continue;
+ if (!strcmp(sprs[i].name, "MMCR0")) {
+ /* XXX: could use a comment or better abstraction! */
+ __mtspr(i, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070);
+ } else {
+ __mtspr(i, val);
+ }
}
}
@@ -289,7 +523,9 @@ int main(int argc, char **argv)
}
}
- printf("Settings SPRs to %#lx...\n", pat);
+ setup_sprs();
+
+ printf("Setting SPRs to 0x%lx...\n", pat);
set_sprs(pat);
memset(before, 0, sizeof(before));
@@ -301,16 +537,37 @@ int main(int argc, char **argv)
migrate_once();
} else {
msleep(2000);
+
+ /* Taking a dec updates SRR0, SRR1, SPRG1, so don't fail. */
+ sprs[26].type |= SPR_ASYNC;
+ sprs[27].type |= SPR_ASYNC;
+ sprs[273].type |= SPR_ASYNC;
}
get_sprs(after);
puts("Checking SPRs...\n");
for (i = 0; i < 1024; i++) {
- if (before[i] != 0 || after[i] != 0)
- report(before[i] == after[i],
- "SPR %d:\t%#018lx <==> %#018lx", i, before[i],
- after[i]);
+ bool pass = true;
+
+ if (!(sprs[i].access & SPR_OS_READ))
+ continue;
+
+ if (sprs[i].width == 32) {
+ if (before[i] >> 32)
+ pass = false;
+ }
+ if (!(sprs[i].type & SPR_ASYNC) && (before[i] != after[i]))
+ pass = false;
+
+ if (sprs[i].width == 32 && !(before[i] >> 32) && !(after[i] >> 32))
+ report(pass, "%-10s(%4d):\t 0x%08lx <==> 0x%08lx",
+ sprs[i].name, i,
+ before[i], after[i]);
+ else
+ report(pass, "%-10s(%4d):\t0x%016lx <==> 0x%016lx",
+ sprs[i].name, i,
+ before[i], after[i]);
}
return report_summary();
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 07/12] powerpc/spapr_vpa: Add basic VPA tests
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
The VPA is an optional memory structure shared between the hypervisor
and operating system, defined by PAPR. This test defines the structure
and adds registration, deregistration, and a few simple sanity tests.
[Thanks to Thomas Huth for suggesting many of the test cases.]
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
lib/powerpc/asm/hcall.h | 1 +
lib/ppc64/asm/vpa.h | 62 +++++++++++++++
powerpc/Makefile.ppc64 | 2 +-
powerpc/spapr_vpa.c | 172 ++++++++++++++++++++++++++++++++++++++++
powerpc/unittests.cfg | 3 +
5 files changed, 239 insertions(+), 1 deletion(-)
create mode 100644 lib/ppc64/asm/vpa.h
create mode 100644 powerpc/spapr_vpa.c
diff --git a/lib/powerpc/asm/hcall.h b/lib/powerpc/asm/hcall.h
index 1173feaa..e0f5009e 100644
--- a/lib/powerpc/asm/hcall.h
+++ b/lib/powerpc/asm/hcall.h
@@ -18,6 +18,7 @@
#define H_SET_SPRG0 0x24
#define H_SET_DABR 0x28
#define H_PAGE_INIT 0x2c
+#define H_REGISTER_VPA 0xDC
#define H_CEDE 0xE0
#define H_GET_TERM_CHAR 0x54
#define H_PUT_TERM_CHAR 0x58
diff --git a/lib/ppc64/asm/vpa.h b/lib/ppc64/asm/vpa.h
new file mode 100644
index 00000000..11dde018
--- /dev/null
+++ b/lib/ppc64/asm/vpa.h
@@ -0,0 +1,62 @@
+#ifndef _ASMPOWERPC_VPA_H_
+#define _ASMPOWERPC_VPA_H_
+/*
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+
+#ifndef __ASSEMBLY__
+
+struct vpa {
+ uint32_t descriptor;
+ uint16_t size;
+ uint8_t reserved1[3];
+ uint8_t status;
+ uint8_t reserved2[14];
+ uint32_t fru_node_id;
+ uint32_t fru_proc_id;
+ uint8_t reserved3[56];
+ uint8_t vhpn_change_counters[8];
+ uint8_t reserved4[80];
+ uint8_t cede_latency;
+ uint8_t maintain_ebb;
+ uint8_t reserved5[6];
+ uint8_t dtl_enable_mask;
+ uint8_t dedicated_cpu_donate;
+ uint8_t maintain_fpr;
+ uint8_t maintain_pmc;
+ uint8_t reserved6[28];
+ uint64_t idle_estimate_purr;
+ uint8_t reserved7[28];
+ uint16_t maintain_nr_slb;
+ uint8_t idle;
+ uint8_t maintain_vmx;
+ uint32_t vp_dispatch_count;
+ uint32_t vp_dispatch_dispersion;
+ uint64_t vp_fault_count;
+ uint64_t vp_fault_tb;
+ uint64_t purr_exprop_idle;
+ uint64_t spurr_exprop_idle;
+ uint64_t purr_exprop_busy;
+ uint64_t spurr_exprop_busy;
+ uint64_t purr_donate_idle;
+ uint64_t spurr_donate_idle;
+ uint64_t purr_donate_busy;
+ uint64_t spurr_donate_busy;
+ uint64_t vp_wait3_tb;
+ uint64_t vp_wait2_tb;
+ uint64_t vp_wait1_tb;
+ uint64_t purr_exprop_adjunct_busy;
+ uint64_t spurr_exprop_adjunct_busy;
+ uint32_t supervisor_pagein_count;
+ uint8_t reserved8[4];
+ uint64_t purr_exprop_adjunct_idle;
+ uint64_t spurr_exprop_adjunct_idle;
+ uint64_t adjunct_insns_executed;
+ uint8_t reserved9[120];
+ uint64_t dtl_index;
+ uint8_t reserved10[96];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASMPOWERPC_VPA_H_ */
diff --git a/powerpc/Makefile.ppc64 b/powerpc/Makefile.ppc64
index ea684470..b0ed2b10 100644
--- a/powerpc/Makefile.ppc64
+++ b/powerpc/Makefile.ppc64
@@ -19,7 +19,7 @@ reloc.o = $(TEST_DIR)/reloc64.o
OBJDIRS += lib/ppc64
# ppc64 specific tests
-tests =
+tests = $(TEST_DIR)/spapr_vpa.elf
include $(SRCDIR)/$(TEST_DIR)/Makefile.common
diff --git a/powerpc/spapr_vpa.c b/powerpc/spapr_vpa.c
new file mode 100644
index 00000000..5586eb8d
--- /dev/null
+++ b/powerpc/spapr_vpa.c
@@ -0,0 +1,172 @@
+/*
+ * Test sPAPR "Per Virtual Processor Area" and H_REGISTER_VPA hypervisor call
+ * (also known as VPA, also known as lppaca in the Linux pseries kernel).
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include <libcflat.h>
+#include <libfdt/libfdt.h>
+#include <devicetree.h>
+#include <util.h>
+#include <alloc.h>
+#include <asm/processor.h>
+#include <asm/setup.h>
+#include <asm/hcall.h>
+#include <asm/vpa.h>
+#include <asm/io.h> /* for endian accessors */
+
+static int verbose;
+
+static void print_vpa(struct vpa *vpa)
+{
+ printf("VPA\n");
+ printf("descriptor: 0x%08x\n", be32_to_cpu(vpa->descriptor));
+ printf("size: 0x%04x\n", be16_to_cpu(vpa->size));
+ printf("status: 0x%02x\n", vpa->status);
+ printf("fru_node_id: 0x%08x\n", be32_to_cpu(vpa->fru_node_id));
+ printf("fru_proc_id: 0x%08x\n", be32_to_cpu(vpa->fru_proc_id));
+ printf("vhpn_change_counters: 0x%02x %02x %02x %02x %02x %02x %02x %02x\n", vpa->vhpn_change_counters[0], vpa->vhpn_change_counters[1], vpa->vhpn_change_counters[2], vpa->vhpn_change_counters[3], vpa->vhpn_change_counters[4], vpa->vhpn_change_counters[5], vpa->vhpn_change_counters[6], vpa->vhpn_change_counters[7]);
+ printf("vp_dispatch_count: 0x%08x\n", be32_to_cpu(vpa->vp_dispatch_count));
+ printf("vp_dispatch_dispersion: 0x%08x\n", be32_to_cpu(vpa->vp_dispatch_dispersion));
+ printf("vp_fault_count: 0x%08lx\n", be64_to_cpu(vpa->vp_fault_count));
+ printf("vp_fault_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_fault_tb));
+ printf("purr_exprop_idle: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_idle));
+ printf("spurr_exprop_idle: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_idle));
+ printf("purr_exprop_busy: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_busy));
+ printf("spurr_exprop_busy: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_busy));
+ printf("purr_donate_idle: 0x%08lx\n", be64_to_cpu(vpa->purr_donate_idle));
+ printf("spurr_donate_idle: 0x%08lx\n", be64_to_cpu(vpa->spurr_donate_idle));
+ printf("purr_donate_busy: 0x%08lx\n", be64_to_cpu(vpa->purr_donate_busy));
+ printf("spurr_donate_busy: 0x%08lx\n", be64_to_cpu(vpa->spurr_donate_busy));
+ printf("vp_wait3_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_wait3_tb));
+ printf("vp_wait2_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_wait2_tb));
+ printf("vp_wait1_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_wait1_tb));
+ printf("purr_exprop_adjunct_busy: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_adjunct_busy));
+ printf("spurr_exprop_adjunct_busy: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_adjunct_busy));
+ printf("purr_exprop_adjunct_idle: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_adjunct_idle));
+ printf("spurr_exprop_adjunct_idle: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_adjunct_idle));
+ printf("adjunct_insns_executed: 0x%08lx\n", be64_to_cpu(vpa->adjunct_insns_executed));
+ printf("dtl_index: 0x%08lx\n", be64_to_cpu(vpa->dtl_index));
+}
+
+#define SUBFUNC_RESERVED (0ULL << 45)
+#define SUBFUNC_REGISTER (1ULL << 45)
+#define SUBFUNC_DEREGISTER (5ULL << 45)
+
+/**
+ * Test the H_REGISTER_VPA h-call register/deregister calls.
+ */
+static void test_register_vpa(void)
+{
+ struct vpa *vpa;
+ uint32_t cpuid = fdt_boot_cpuid_phys(dt_fdt());
+ int rc;
+
+ report_prefix_push("H_REGISTER_VPA");
+
+ vpa = memalign(4096, sizeof(*vpa));
+
+ memset(vpa, 0, sizeof(*vpa));
+
+ vpa->size = cpu_to_be16(sizeof(*vpa));
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_RESERVED, cpuid, vpa);
+ report(rc == H_PARAMETER, "Reserved sub-function fails with H_PARAMETER");
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, 0xbadbad, vpa);
+ report(rc == H_PARAMETER, "Register with invalid proc-no fails");
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, (void *)vpa + 8);
+ report(rc == H_PARAMETER, "Register with VPA not cacheline aligned fails");
+
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, (void *)vpa + 4096 - 128);
+ report(rc == H_PARAMETER, "Register with VPA spanning 4096 bytes fails");
+
+ vpa->size = cpu_to_be16(632);
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, (void *)vpa);
+ report(rc == H_PARAMETER, "Register with VPA size < 640 bytes fails");
+ vpa->size = cpu_to_be16(sizeof(*vpa));
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, PHYSICAL_END);
+ report(rc == H_PARAMETER, "Register with VPA outside guest real memory fails");
+
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, vpa);
+ report(rc == H_SUCCESS, "VPA registered");
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, cpuid, NULL);
+ report(rc == H_SUCCESS, "VPA deregistered");
+
+ /*
+ * From PAPR: "note no check is made that a valid VPA registration
+ * exists".
+ */
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, cpuid, NULL);
+ report(rc == H_SUCCESS, "Deregister succeeds with no VPA registered");
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, 0xbadbad, NULL);
+ report(rc == H_PARAMETER, "Deregister with invalid proc-no fails");
+
+ report_prefix_pop();
+}
+
+/**
+ * Test some VPA fields.
+ */
+static void test_vpa(void)
+{
+ struct vpa *vpa;
+ uint32_t cpuid = fdt_boot_cpuid_phys(dt_fdt());
+ int disp_count1, disp_count2;
+ int rc;
+
+ report_prefix_push("VPA");
+
+ vpa = memalign(4096, sizeof(*vpa));
+
+ memset(vpa, 0, sizeof(*vpa));
+
+ vpa->size = cpu_to_be16(sizeof(*vpa));
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, vpa);
+ if (rc != H_SUCCESS) {
+ report_skip("VPA could not be registered");
+ return;
+ }
+
+ if (verbose)
+ print_vpa(vpa);
+
+ disp_count1 = be32_to_cpu(vpa->vp_dispatch_count);
+ report(disp_count1 % 2 == 0, "Dispatch count is even while running");
+ msleep(100);
+ disp_count2 = be32_to_cpu(vpa->vp_dispatch_count);
+ report(disp_count1 != disp_count2, "Dispatch count increments over H_CEDE");
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, cpuid, vpa);
+ if (rc != H_SUCCESS)
+ report_fail("Could not deregister after registration");
+
+ disp_count1 = be32_to_cpu(vpa->vp_dispatch_count);
+ report(disp_count1 % 2 == 1, "Dispatch count is odd after deregister");
+
+ report_prefix_pop();
+}
+
+int main(int argc, char *argv[])
+{
+ int i;
+
+ for (i = 1; i < argc; i++) {
+ if (strcmp(argv[i], "-v") == 0) {
+ verbose = 1;
+ }
+ }
+
+ test_register_vpa();
+
+ test_vpa();
+
+ return report_summary();
+}
diff --git a/powerpc/unittests.cfg b/powerpc/unittests.cfg
index e206a225..dd5f361c 100644
--- a/powerpc/unittests.cfg
+++ b/powerpc/unittests.cfg
@@ -39,6 +39,9 @@ groups = selftest
[spapr_hcall]
file = spapr_hcall.elf
+[spapr_vpa]
+file = spapr_vpa.elf
+
[rtas-get-time-of-day]
file = rtas.elf
timeout = 5
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 07/12] powerpc/spapr_vpa: Add basic VPA tests
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
The VPA is an optional memory structure shared between the hypervisor
and operating system, defined by PAPR. This test defines the structure
and adds registration, deregistration, and a few simple sanity tests.
[Thanks to Thomas Huth for suggesting many of the test cases.]
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
lib/powerpc/asm/hcall.h | 1 +
lib/ppc64/asm/vpa.h | 62 +++++++++++++++
powerpc/Makefile.ppc64 | 2 +-
powerpc/spapr_vpa.c | 172 ++++++++++++++++++++++++++++++++++++++++
powerpc/unittests.cfg | 3 +
5 files changed, 239 insertions(+), 1 deletion(-)
create mode 100644 lib/ppc64/asm/vpa.h
create mode 100644 powerpc/spapr_vpa.c
diff --git a/lib/powerpc/asm/hcall.h b/lib/powerpc/asm/hcall.h
index 1173feaa..e0f5009e 100644
--- a/lib/powerpc/asm/hcall.h
+++ b/lib/powerpc/asm/hcall.h
@@ -18,6 +18,7 @@
#define H_SET_SPRG0 0x24
#define H_SET_DABR 0x28
#define H_PAGE_INIT 0x2c
+#define H_REGISTER_VPA 0xDC
#define H_CEDE 0xE0
#define H_GET_TERM_CHAR 0x54
#define H_PUT_TERM_CHAR 0x58
diff --git a/lib/ppc64/asm/vpa.h b/lib/ppc64/asm/vpa.h
new file mode 100644
index 00000000..11dde018
--- /dev/null
+++ b/lib/ppc64/asm/vpa.h
@@ -0,0 +1,62 @@
+#ifndef _ASMPOWERPC_VPA_H_
+#define _ASMPOWERPC_VPA_H_
+/*
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+
+#ifndef __ASSEMBLY__
+
+struct vpa {
+ uint32_t descriptor;
+ uint16_t size;
+ uint8_t reserved1[3];
+ uint8_t status;
+ uint8_t reserved2[14];
+ uint32_t fru_node_id;
+ uint32_t fru_proc_id;
+ uint8_t reserved3[56];
+ uint8_t vhpn_change_counters[8];
+ uint8_t reserved4[80];
+ uint8_t cede_latency;
+ uint8_t maintain_ebb;
+ uint8_t reserved5[6];
+ uint8_t dtl_enable_mask;
+ uint8_t dedicated_cpu_donate;
+ uint8_t maintain_fpr;
+ uint8_t maintain_pmc;
+ uint8_t reserved6[28];
+ uint64_t idle_estimate_purr;
+ uint8_t reserved7[28];
+ uint16_t maintain_nr_slb;
+ uint8_t idle;
+ uint8_t maintain_vmx;
+ uint32_t vp_dispatch_count;
+ uint32_t vp_dispatch_dispersion;
+ uint64_t vp_fault_count;
+ uint64_t vp_fault_tb;
+ uint64_t purr_exprop_idle;
+ uint64_t spurr_exprop_idle;
+ uint64_t purr_exprop_busy;
+ uint64_t spurr_exprop_busy;
+ uint64_t purr_donate_idle;
+ uint64_t spurr_donate_idle;
+ uint64_t purr_donate_busy;
+ uint64_t spurr_donate_busy;
+ uint64_t vp_wait3_tb;
+ uint64_t vp_wait2_tb;
+ uint64_t vp_wait1_tb;
+ uint64_t purr_exprop_adjunct_busy;
+ uint64_t spurr_exprop_adjunct_busy;
+ uint32_t supervisor_pagein_count;
+ uint8_t reserved8[4];
+ uint64_t purr_exprop_adjunct_idle;
+ uint64_t spurr_exprop_adjunct_idle;
+ uint64_t adjunct_insns_executed;
+ uint8_t reserved9[120];
+ uint64_t dtl_index;
+ uint8_t reserved10[96];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASMPOWERPC_VPA_H_ */
diff --git a/powerpc/Makefile.ppc64 b/powerpc/Makefile.ppc64
index ea684470..b0ed2b10 100644
--- a/powerpc/Makefile.ppc64
+++ b/powerpc/Makefile.ppc64
@@ -19,7 +19,7 @@ reloc.o = $(TEST_DIR)/reloc64.o
OBJDIRS += lib/ppc64
# ppc64 specific tests
-tests =
+tests = $(TEST_DIR)/spapr_vpa.elf
include $(SRCDIR)/$(TEST_DIR)/Makefile.common
diff --git a/powerpc/spapr_vpa.c b/powerpc/spapr_vpa.c
new file mode 100644
index 00000000..5586eb8d
--- /dev/null
+++ b/powerpc/spapr_vpa.c
@@ -0,0 +1,172 @@
+/*
+ * Test sPAPR "Per Virtual Processor Area" and H_REGISTER_VPA hypervisor call
+ * (also known as VPA, also known as lppaca in the Linux pseries kernel).
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include <libcflat.h>
+#include <libfdt/libfdt.h>
+#include <devicetree.h>
+#include <util.h>
+#include <alloc.h>
+#include <asm/processor.h>
+#include <asm/setup.h>
+#include <asm/hcall.h>
+#include <asm/vpa.h>
+#include <asm/io.h> /* for endian accessors */
+
+static int verbose;
+
+static void print_vpa(struct vpa *vpa)
+{
+ printf("VPA\n");
+ printf("descriptor: 0x%08x\n", be32_to_cpu(vpa->descriptor));
+ printf("size: 0x%04x\n", be16_to_cpu(vpa->size));
+ printf("status: 0x%02x\n", vpa->status);
+ printf("fru_node_id: 0x%08x\n", be32_to_cpu(vpa->fru_node_id));
+ printf("fru_proc_id: 0x%08x\n", be32_to_cpu(vpa->fru_proc_id));
+ printf("vhpn_change_counters: 0x%02x %02x %02x %02x %02x %02x %02x %02x\n", vpa->vhpn_change_counters[0], vpa->vhpn_change_counters[1], vpa->vhpn_change_counters[2], vpa->vhpn_change_counters[3], vpa->vhpn_change_counters[4], vpa->vhpn_change_counters[5], vpa->vhpn_change_counters[6], vpa->vhpn_change_counters[7]);
+ printf("vp_dispatch_count: 0x%08x\n", be32_to_cpu(vpa->vp_dispatch_count));
+ printf("vp_dispatch_dispersion: 0x%08x\n", be32_to_cpu(vpa->vp_dispatch_dispersion));
+ printf("vp_fault_count: 0x%08lx\n", be64_to_cpu(vpa->vp_fault_count));
+ printf("vp_fault_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_fault_tb));
+ printf("purr_exprop_idle: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_idle));
+ printf("spurr_exprop_idle: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_idle));
+ printf("purr_exprop_busy: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_busy));
+ printf("spurr_exprop_busy: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_busy));
+ printf("purr_donate_idle: 0x%08lx\n", be64_to_cpu(vpa->purr_donate_idle));
+ printf("spurr_donate_idle: 0x%08lx\n", be64_to_cpu(vpa->spurr_donate_idle));
+ printf("purr_donate_busy: 0x%08lx\n", be64_to_cpu(vpa->purr_donate_busy));
+ printf("spurr_donate_busy: 0x%08lx\n", be64_to_cpu(vpa->spurr_donate_busy));
+ printf("vp_wait3_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_wait3_tb));
+ printf("vp_wait2_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_wait2_tb));
+ printf("vp_wait1_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_wait1_tb));
+ printf("purr_exprop_adjunct_busy: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_adjunct_busy));
+ printf("spurr_exprop_adjunct_busy: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_adjunct_busy));
+ printf("purr_exprop_adjunct_idle: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_adjunct_idle));
+ printf("spurr_exprop_adjunct_idle: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_adjunct_idle));
+ printf("adjunct_insns_executed: 0x%08lx\n", be64_to_cpu(vpa->adjunct_insns_executed));
+ printf("dtl_index: 0x%08lx\n", be64_to_cpu(vpa->dtl_index));
+}
+
+#define SUBFUNC_RESERVED (0ULL << 45)
+#define SUBFUNC_REGISTER (1ULL << 45)
+#define SUBFUNC_DEREGISTER (5ULL << 45)
+
+/**
+ * Test the H_REGISTER_VPA h-call register/deregister calls.
+ */
+static void test_register_vpa(void)
+{
+ struct vpa *vpa;
+ uint32_t cpuid = fdt_boot_cpuid_phys(dt_fdt());
+ int rc;
+
+ report_prefix_push("H_REGISTER_VPA");
+
+ vpa = memalign(4096, sizeof(*vpa));
+
+ memset(vpa, 0, sizeof(*vpa));
+
+ vpa->size = cpu_to_be16(sizeof(*vpa));
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_RESERVED, cpuid, vpa);
+ report(rc == H_PARAMETER, "Reserved sub-function fails with H_PARAMETER");
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, 0xbadbad, vpa);
+ report(rc == H_PARAMETER, "Register with invalid proc-no fails");
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, (void *)vpa + 8);
+ report(rc == H_PARAMETER, "Register with VPA not cacheline aligned fails");
+
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, (void *)vpa + 4096 - 128);
+ report(rc == H_PARAMETER, "Register with VPA spanning 4096 bytes fails");
+
+ vpa->size = cpu_to_be16(632);
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, (void *)vpa);
+ report(rc == H_PARAMETER, "Register with VPA size < 640 bytes fails");
+ vpa->size = cpu_to_be16(sizeof(*vpa));
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, PHYSICAL_END);
+ report(rc == H_PARAMETER, "Register with VPA outside guest real memory fails");
+
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, vpa);
+ report(rc == H_SUCCESS, "VPA registered");
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, cpuid, NULL);
+ report(rc == H_SUCCESS, "VPA deregistered");
+
+ /*
+ * From PAPR: "note no check is made that a valid VPA registration
+ * exists".
+ */
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, cpuid, NULL);
+ report(rc == H_SUCCESS, "Deregister succeeds with no VPA registered");
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, 0xbadbad, NULL);
+ report(rc == H_PARAMETER, "Deregister with invalid proc-no fails");
+
+ report_prefix_pop();
+}
+
+/**
+ * Test some VPA fields.
+ */
+static void test_vpa(void)
+{
+ struct vpa *vpa;
+ uint32_t cpuid = fdt_boot_cpuid_phys(dt_fdt());
+ int disp_count1, disp_count2;
+ int rc;
+
+ report_prefix_push("VPA");
+
+ vpa = memalign(4096, sizeof(*vpa));
+
+ memset(vpa, 0, sizeof(*vpa));
+
+ vpa->size = cpu_to_be16(sizeof(*vpa));
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, vpa);
+ if (rc != H_SUCCESS) {
+ report_skip("VPA could not be registered");
+ return;
+ }
+
+ if (verbose)
+ print_vpa(vpa);
+
+ disp_count1 = be32_to_cpu(vpa->vp_dispatch_count);
+ report(disp_count1 % 2 == 0, "Dispatch count is even while running");
+ msleep(100);
+ disp_count2 = be32_to_cpu(vpa->vp_dispatch_count);
+ report(disp_count1 != disp_count2, "Dispatch count increments over H_CEDE");
+
+ rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, cpuid, vpa);
+ if (rc != H_SUCCESS)
+ report_fail("Could not deregister after registration");
+
+ disp_count1 = be32_to_cpu(vpa->vp_dispatch_count);
+ report(disp_count1 % 2 == 1, "Dispatch count is odd after deregister");
+
+ report_prefix_pop();
+}
+
+int main(int argc, char *argv[])
+{
+ int i;
+
+ for (i = 1; i < argc; i++) {
+ if (strcmp(argv[i], "-v") == 0) {
+ verbose = 1;
+ }
+ }
+
+ test_register_vpa();
+
+ test_vpa();
+
+ return report_summary();
+}
diff --git a/powerpc/unittests.cfg b/powerpc/unittests.cfg
index e206a225..dd5f361c 100644
--- a/powerpc/unittests.cfg
+++ b/powerpc/unittests.cfg
@@ -39,6 +39,9 @@ groups = selftest
[spapr_hcall]
file = spapr_hcall.elf
+[spapr_vpa]
+file = spapr_vpa.elf
+
[rtas-get-time-of-day]
file = rtas.elf
timeout = 5
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 08/12] powerpc: Expand exception handler vector granularity
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
Exception handlers are currently indexed in units of 0x100, but
powerpc can have vectors that are aligned to as little as 0x20
bytes. Increase granularity of the handler functions before
adding support for those vectors.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v3:
- Fix typo [Thomas]
lib/powerpc/processor.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
index aaf45b68..64d7ae01 100644
--- a/lib/powerpc/processor.c
+++ b/lib/powerpc/processor.c
@@ -16,19 +16,25 @@
static struct {
void (*func)(struct pt_regs *, void *data);
void *data;
-} handlers[16];
+} handlers[128];
+/*
+ * Exception handlers span from 0x100 to 0x1000 and can have a granularity
+ * of 0x20 bytes in some cases. Indexing spans 0-0x1000 with 0x20 increments
+ * resulting in 128 slots.
+ */
void handle_exception(int trap, void (*func)(struct pt_regs *, void *),
void * data)
{
- assert(!(trap & ~0xf00));
+ assert(!(trap & ~0xfe0));
- trap >>= 8;
+ trap >>= 5;
if (func && handlers[trap].func) {
printf("exception handler installed twice %#x\n", trap);
abort();
}
+
handlers[trap].func = func;
handlers[trap].data = data;
}
@@ -37,9 +43,9 @@ void do_handle_exception(struct pt_regs *regs)
{
unsigned char v;
- v = regs->trap >> 8;
+ v = regs->trap >> 5;
- if (v < 16 && handlers[v].func) {
+ if (v < 128 && handlers[v].func) {
handlers[v].func(regs, handlers[v].data);
return;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 08/12] powerpc: Expand exception handler vector granularity
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
Exception handlers are currently indexed in units of 0x100, but
powerpc can have vectors that are aligned to as little as 0x20
bytes. Increase granularity of the handler functions before
adding support for those vectors.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v3:
- Fix typo [Thomas]
lib/powerpc/processor.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
index aaf45b68..64d7ae01 100644
--- a/lib/powerpc/processor.c
+++ b/lib/powerpc/processor.c
@@ -16,19 +16,25 @@
static struct {
void (*func)(struct pt_regs *, void *data);
void *data;
-} handlers[16];
+} handlers[128];
+/*
+ * Exception handlers span from 0x100 to 0x1000 and can have a granularity
+ * of 0x20 bytes in some cases. Indexing spans 0-0x1000 with 0x20 increments
+ * resulting in 128 slots.
+ */
void handle_exception(int trap, void (*func)(struct pt_regs *, void *),
void * data)
{
- assert(!(trap & ~0xf00));
+ assert(!(trap & ~0xfe0));
- trap >>= 8;
+ trap >>= 5;
if (func && handlers[trap].func) {
printf("exception handler installed twice %#x\n", trap);
abort();
}
+
handlers[trap].func = func;
handlers[trap].data = data;
}
@@ -37,9 +43,9 @@ void do_handle_exception(struct pt_regs *regs)
{
unsigned char v;
- v = regs->trap >> 8;
+ v = regs->trap >> 5;
- if (v < 16 && handlers[v].func) {
+ if (v < 128 && handlers[v].func) {
handlers[v].func(regs, handlers[v].data);
return;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 09/12] powerpc: Add support for more interrupts including HV interrupts
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
Interrupt vectors were not being populated for all architected
interrupt types, which could lead to crashes rather than a message for
unhandled interrupts.
0x20 sized vectors require some reworking of the code to fit. This
also adds support for HV / HSRR type interrupts which will be used in
a later change.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v3:
- Build fix [Joel]
lib/powerpc/asm/ppc_asm.h | 3 ++
powerpc/cstart64.S | 79 ++++++++++++++++++++++++++++++++-------
2 files changed, 68 insertions(+), 14 deletions(-)
diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h
index 6299ff53..46b4be00 100644
--- a/lib/powerpc/asm/ppc_asm.h
+++ b/lib/powerpc/asm/ppc_asm.h
@@ -35,6 +35,9 @@
#endif /* __BYTE_ORDER__ */
+#define SPR_HSRR0 0x13A
+#define SPR_HSRR1 0x13B
+
/* Machine State Register definitions: */
#define MSR_EE_BIT 15 /* External Interrupts Enable */
#define MSR_SF_BIT 63 /* 64-bit mode */
diff --git a/powerpc/cstart64.S b/powerpc/cstart64.S
index 34e39341..b7514100 100644
--- a/powerpc/cstart64.S
+++ b/powerpc/cstart64.S
@@ -184,14 +184,6 @@ call_handler:
mfcr r0
std r0,_CCR(r1)
- /* nip and msr */
-
- mfsrr0 r0
- std r0, _NIP(r1)
-
- mfsrr1 r0
- std r0, _MSR(r1)
-
/* restore TOC pointer */
LOAD_REG_IMMEDIATE(r31, SPAPR_KERNEL_LOAD_ADDR)
@@ -238,6 +230,7 @@ call_handler:
.section .text.ex
+/* [H]VECTOR must not be more than 8 instructions to fit in 0x20 vectors */
.macro VECTOR vec
. = \vec
@@ -246,19 +239,28 @@ call_handler:
subi r1,r1, INT_FRAME_SIZE
/* save r0 and ctr to call generic handler */
-
SAVE_GPR(0,r1)
- mfctr r0
- std r0,_CTR(r1)
+ li r0,\vec
+ std r0,_TRAP(r1)
- ld r0, P_HANDLER(0)
- mtctr r0
+ b handler_trampoline
+.endm
+
+.macro HVECTOR vec
+ . = \vec
+
+ mtsprg1 r1 /* save r1 */
+ mfsprg0 r1 /* get exception stack address */
+ subi r1,r1, INT_FRAME_SIZE
+
+ /* save r0 and ctr to call generic handler */
+ SAVE_GPR(0,r1)
li r0,\vec
std r0,_TRAP(r1)
- bctr
+ b handler_htrampoline
.endm
. = 0x100
@@ -268,12 +270,61 @@ __start_interrupts:
VECTOR(0x100)
VECTOR(0x200)
VECTOR(0x300)
+VECTOR(0x380)
VECTOR(0x400)
+VECTOR(0x480)
VECTOR(0x500)
VECTOR(0x600)
VECTOR(0x700)
VECTOR(0x800)
VECTOR(0x900)
+HVECTOR(0x980)
+VECTOR(0xa00)
+VECTOR(0xc00)
+VECTOR(0xd00)
+HVECTOR(0xe00)
+HVECTOR(0xe20)
+HVECTOR(0xe40)
+HVECTOR(0xe60)
+HVECTOR(0xe80)
+HVECTOR(0xea0)
+VECTOR(0xf00)
+VECTOR(0xf20)
+VECTOR(0xf40)
+VECTOR(0xf60)
+HVECTOR(0xf80)
+
+handler_trampoline:
+ mfctr r0
+ std r0,_CTR(r1)
+
+ ld r0, P_HANDLER(0)
+ mtctr r0
+
+ /* nip and msr */
+ mfsrr0 r0
+ std r0, _NIP(r1)
+
+ mfsrr1 r0
+ std r0, _MSR(r1)
+
+ bctr
+
+handler_htrampoline:
+ mfctr r0
+ std r0,_CTR(r1)
+
+ ld r0, P_HANDLER(0)
+ mtctr r0
+
+ /* nip and msr */
+ mfspr r0, SPR_HSRR0
+ std r0, _NIP(r1)
+
+ mfspr r0, SPR_HSRR1
+ std r0, _MSR(r1)
+
+ bctr
.align 7
.globl __end_interrupts
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 09/12] powerpc: Add support for more interrupts including HV interrupts
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
Interrupt vectors were not being populated for all architected
interrupt types, which could lead to crashes rather than a message for
unhandled interrupts.
0x20 sized vectors require some reworking of the code to fit. This
also adds support for HV / HSRR type interrupts which will be used in
a later change.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v3:
- Build fix [Joel]
lib/powerpc/asm/ppc_asm.h | 3 ++
powerpc/cstart64.S | 79 ++++++++++++++++++++++++++++++++-------
2 files changed, 68 insertions(+), 14 deletions(-)
diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h
index 6299ff53..46b4be00 100644
--- a/lib/powerpc/asm/ppc_asm.h
+++ b/lib/powerpc/asm/ppc_asm.h
@@ -35,6 +35,9 @@
#endif /* __BYTE_ORDER__ */
+#define SPR_HSRR0 0x13A
+#define SPR_HSRR1 0x13B
+
/* Machine State Register definitions: */
#define MSR_EE_BIT 15 /* External Interrupts Enable */
#define MSR_SF_BIT 63 /* 64-bit mode */
diff --git a/powerpc/cstart64.S b/powerpc/cstart64.S
index 34e39341..b7514100 100644
--- a/powerpc/cstart64.S
+++ b/powerpc/cstart64.S
@@ -184,14 +184,6 @@ call_handler:
mfcr r0
std r0,_CCR(r1)
- /* nip and msr */
-
- mfsrr0 r0
- std r0, _NIP(r1)
-
- mfsrr1 r0
- std r0, _MSR(r1)
-
/* restore TOC pointer */
LOAD_REG_IMMEDIATE(r31, SPAPR_KERNEL_LOAD_ADDR)
@@ -238,6 +230,7 @@ call_handler:
.section .text.ex
+/* [H]VECTOR must not be more than 8 instructions to fit in 0x20 vectors */
.macro VECTOR vec
. = \vec
@@ -246,19 +239,28 @@ call_handler:
subi r1,r1, INT_FRAME_SIZE
/* save r0 and ctr to call generic handler */
-
SAVE_GPR(0,r1)
- mfctr r0
- std r0,_CTR(r1)
+ li r0,\vec
+ std r0,_TRAP(r1)
- ld r0, P_HANDLER(0)
- mtctr r0
+ b handler_trampoline
+.endm
+
+.macro HVECTOR vec
+ . = \vec
+
+ mtsprg1 r1 /* save r1 */
+ mfsprg0 r1 /* get exception stack address */
+ subi r1,r1, INT_FRAME_SIZE
+
+ /* save r0 and ctr to call generic handler */
+ SAVE_GPR(0,r1)
li r0,\vec
std r0,_TRAP(r1)
- bctr
+ b handler_htrampoline
.endm
. = 0x100
@@ -268,12 +270,61 @@ __start_interrupts:
VECTOR(0x100)
VECTOR(0x200)
VECTOR(0x300)
+VECTOR(0x380)
VECTOR(0x400)
+VECTOR(0x480)
VECTOR(0x500)
VECTOR(0x600)
VECTOR(0x700)
VECTOR(0x800)
VECTOR(0x900)
+HVECTOR(0x980)
+VECTOR(0xa00)
+VECTOR(0xc00)
+VECTOR(0xd00)
+HVECTOR(0xe00)
+HVECTOR(0xe20)
+HVECTOR(0xe40)
+HVECTOR(0xe60)
+HVECTOR(0xe80)
+HVECTOR(0xea0)
+VECTOR(0xf00)
+VECTOR(0xf20)
+VECTOR(0xf40)
+VECTOR(0xf60)
+HVECTOR(0xf80)
+
+handler_trampoline:
+ mfctr r0
+ std r0,_CTR(r1)
+
+ ld r0, P_HANDLER(0)
+ mtctr r0
+
+ /* nip and msr */
+ mfsrr0 r0
+ std r0, _NIP(r1)
+
+ mfsrr1 r0
+ std r0, _MSR(r1)
+
+ bctr
+
+handler_htrampoline:
+ mfctr r0
+ std r0,_CTR(r1)
+
+ ld r0, P_HANDLER(0)
+ mtctr r0
+
+ /* nip and msr */
+ mfspr r0, SPR_HSRR0
+ std r0, _NIP(r1)
+
+ mfspr r0, SPR_HSRR1
+ std r0, _MSR(r1)
+
+ bctr
.align 7
.globl __end_interrupts
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 10/12] powerpc: Discover runtime load address dynamically
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
The next change will load the kernels at different addresses depending
on test options, so this needs to be reverted back to dynamic
discovery.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
powerpc/cstart64.S | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/powerpc/cstart64.S b/powerpc/cstart64.S
index b7514100..e18ae9a2 100644
--- a/powerpc/cstart64.S
+++ b/powerpc/cstart64.S
@@ -33,9 +33,14 @@ start:
* We were loaded at QEMU's kernel load address, but we're not
* allowed to link there due to how QEMU deals with linker VMAs,
* so we just linked at zero. This means the first thing to do is
- * to find our stack and toc, and then do a relocate.
+ * to find our stack and toc, and then do a relocate. powernv and
+ * pseries load addresses are not the same, so find the address
+ * dynamically:
*/
- LOAD_REG_IMMEDIATE(r31, SPAPR_KERNEL_LOAD_ADDR)
+ bl 0f
+0: mflr r31
+ subi r31, r31, 0b - start /* QEMU's kernel load address */
+
ld r1, (p_stack - start)(r31)
ld r2, (p_toc - start)(r31)
add r1, r1, r31
@@ -114,8 +119,11 @@ p_toc: .llong tocptr
p_dyn: .llong dynamic_start
.text
+start_text:
.align 3
+p_toc_text: .llong tocptr
+.align 3
.globl hcall
hcall:
sc 1
@@ -185,9 +193,10 @@ call_handler:
std r0,_CCR(r1)
/* restore TOC pointer */
-
- LOAD_REG_IMMEDIATE(r31, SPAPR_KERNEL_LOAD_ADDR)
- ld r2, (p_toc - start)(r31)
+ bl 0f
+0: mflr r31
+ subi r31, r31, 0b - start_text
+ ld r2, (p_toc_text - start_text)(r31)
/* FIXME: build stack frame */
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 10/12] powerpc: Discover runtime load address dynamically
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
The next change will load the kernels at different addresses depending
on test options, so this needs to be reverted back to dynamic
discovery.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
powerpc/cstart64.S | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/powerpc/cstart64.S b/powerpc/cstart64.S
index b7514100..e18ae9a2 100644
--- a/powerpc/cstart64.S
+++ b/powerpc/cstart64.S
@@ -33,9 +33,14 @@ start:
* We were loaded at QEMU's kernel load address, but we're not
* allowed to link there due to how QEMU deals with linker VMAs,
* so we just linked at zero. This means the first thing to do is
- * to find our stack and toc, and then do a relocate.
+ * to find our stack and toc, and then do a relocate. powernv and
+ * pseries load addresses are not the same, so find the address
+ * dynamically:
*/
- LOAD_REG_IMMEDIATE(r31, SPAPR_KERNEL_LOAD_ADDR)
+ bl 0f
+0: mflr r31
+ subi r31, r31, 0b - start /* QEMU's kernel load address */
+
ld r1, (p_stack - start)(r31)
ld r2, (p_toc - start)(r31)
add r1, r1, r31
@@ -114,8 +119,11 @@ p_toc: .llong tocptr
p_dyn: .llong dynamic_start
.text
+start_text:
.align 3
+p_toc_text: .llong tocptr
+.align 3
.globl hcall
hcall:
sc 1
@@ -185,9 +193,10 @@ call_handler:
std r0,_CCR(r1)
/* restore TOC pointer */
-
- LOAD_REG_IMMEDIATE(r31, SPAPR_KERNEL_LOAD_ADDR)
- ld r2, (p_toc - start)(r31)
+ bl 0f
+0: mflr r31
+ subi r31, r31, 0b - start_text
+ ld r2, (p_toc_text - start_text)(r31)
/* FIXME: build stack frame */
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 11/12] powerpc: Support powernv machine with QEMU TCG
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm
Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth,
Cédric Le Goater
This is a basic first pass at powernv support using OPAL (skiboot)
firmware.
The ACCEL is a bit clunky, defaulting to kvm for powernv machine, which
isn't right and has to be manually overridden. It also does not yet run
in the run_tests.sh batch process, more work is needed to exclude
certain tests (e.g., rtas) and adjust parameters (e.g., increase memory
size) to allow powernv to work. For now it can run single test cases.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v3:
- Typo fix [Thomas]
lib/powerpc/asm/ppc_asm.h | 5 +++
lib/powerpc/asm/processor.h | 10 +++++
lib/powerpc/hcall.c | 4 +-
lib/powerpc/io.c | 27 +++++++++++++-
lib/powerpc/io.h | 6 +++
lib/powerpc/processor.c | 10 +++++
lib/powerpc/setup.c | 8 ++--
lib/ppc64/asm/opal.h | 15 ++++++++
lib/ppc64/opal-calls.S | 46 +++++++++++++++++++++++
lib/ppc64/opal.c | 74 +++++++++++++++++++++++++++++++++++++
powerpc/Makefile.ppc64 | 2 +
powerpc/cstart64.S | 7 ++++
powerpc/run | 35 ++++++++++++++++--
13 files changed, 238 insertions(+), 11 deletions(-)
create mode 100644 lib/ppc64/asm/opal.h
create mode 100644 lib/ppc64/opal-calls.S
create mode 100644 lib/ppc64/opal.c
diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h
index 46b4be00..63f11d13 100644
--- a/lib/powerpc/asm/ppc_asm.h
+++ b/lib/powerpc/asm/ppc_asm.h
@@ -39,7 +39,12 @@
#define SPR_HSRR1 0x13B
/* Machine State Register definitions: */
+#define MSR_LE_BIT 0
#define MSR_EE_BIT 15 /* External Interrupts Enable */
+#define MSR_HV_BIT 60 /* Hypervisor mode */
#define MSR_SF_BIT 63 /* 64-bit mode */
+#define SPR_HSRR0 0x13A
+#define SPR_HSRR1 0x13B
+
#endif /* _ASMPOWERPC_PPC_ASM_H */
diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h
index 4ad6612b..9b318c3e 100644
--- a/lib/powerpc/asm/processor.h
+++ b/lib/powerpc/asm/processor.h
@@ -3,6 +3,7 @@
#include <libcflat.h>
#include <asm/ptrace.h>
+#include <asm/ppc_asm.h>
#ifndef __ASSEMBLY__
void handle_exception(int trap, void (*func)(struct pt_regs *, void *), void *);
@@ -43,6 +44,15 @@ static inline void mtmsr(uint64_t msr)
asm volatile ("mtmsrd %[msr]" :: [msr] "r" (msr) : "memory");
}
+/*
+ * This returns true on PowerNV / OPAL machines which run in hypervisor
+ * mode. False on pseries / PAPR machines that run in guest mode.
+ */
+static inline bool machine_is_powernv(void)
+{
+ return !!(mfmsr() & (1ULL << MSR_HV_BIT));
+}
+
static inline uint64_t get_tb(void)
{
return mfspr(SPR_TB);
diff --git a/lib/powerpc/hcall.c b/lib/powerpc/hcall.c
index 711cb1b0..37e52f54 100644
--- a/lib/powerpc/hcall.c
+++ b/lib/powerpc/hcall.c
@@ -25,7 +25,7 @@ int hcall_have_broken_sc1(void)
return r3 == (unsigned long)H_PRIVILEGE;
}
-void putchar(int c)
+void papr_putchar(int c)
{
unsigned long vty = 0; /* 0 == default */
unsigned long nr_chars = 1;
@@ -34,7 +34,7 @@ void putchar(int c)
hcall(H_PUT_TERM_CHAR, vty, nr_chars, chars);
}
-int __getchar(void)
+int __papr_getchar(void)
{
register unsigned long r3 asm("r3") = H_GET_TERM_CHAR;
register unsigned long r4 asm("r4") = 0; /* 0 == default vty */
diff --git a/lib/powerpc/io.c b/lib/powerpc/io.c
index a381688b..ab7bb843 100644
--- a/lib/powerpc/io.c
+++ b/lib/powerpc/io.c
@@ -9,13 +9,33 @@
#include <asm/spinlock.h>
#include <asm/rtas.h>
#include <asm/setup.h>
+#include <asm/processor.h>
#include "io.h"
static struct spinlock print_lock;
+void putchar(int c)
+{
+ if (machine_is_powernv())
+ opal_putchar(c);
+ else
+ papr_putchar(c);
+}
+
+int __getchar(void)
+{
+ if (machine_is_powernv())
+ return __opal_getchar();
+ else
+ return __papr_getchar();
+}
+
void io_init(void)
{
- rtas_init();
+ if (machine_is_powernv())
+ assert(!opal_init());
+ else
+ rtas_init();
}
void puts(const char *s)
@@ -38,7 +58,10 @@ void exit(int code)
// FIXME: change this print-exit/rtas-poweroff to chr_testdev_exit(),
// maybe by plugging chr-testdev into a spapr-vty.
printf("\nEXIT: STATUS=%d\n", ((code) << 1) | 1);
- rtas_power_off();
+ if (machine_is_powernv())
+ opal_power_off();
+ else
+ rtas_power_off();
halt(code);
__builtin_unreachable();
}
diff --git a/lib/powerpc/io.h b/lib/powerpc/io.h
index d4f21ba1..943bf142 100644
--- a/lib/powerpc/io.h
+++ b/lib/powerpc/io.h
@@ -8,6 +8,12 @@
#define _POWERPC_IO_H_
extern void io_init(void);
+extern int opal_init(void);
+extern void opal_power_off(void);
extern void putchar(int c);
+extern void opal_putchar(int c);
+extern void papr_putchar(int c);
+extern int __opal_getchar(void);
+extern int __papr_getchar(void);
#endif
diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
index 64d7ae01..58fea8cf 100644
--- a/lib/powerpc/processor.c
+++ b/lib/powerpc/processor.c
@@ -71,6 +71,16 @@ void sleep_tb(uint64_t cycles)
{
uint64_t start, end, now;
+ if (machine_is_powernv()) {
+ /*
+ * Could use 'stop' to sleep here which would be interesting.
+ * stop with ESL=0 should be simple enough, ESL=1 would require
+ * SRESET based wakeup which is more involved.
+ */
+ delay(cycles);
+ return;
+ }
+
start = now = get_tb();
end = start + cycles;
diff --git a/lib/powerpc/setup.c b/lib/powerpc/setup.c
index 1be4c030..dd758db4 100644
--- a/lib/powerpc/setup.c
+++ b/lib/powerpc/setup.c
@@ -18,6 +18,7 @@
#include <argv.h>
#include <asm/setup.h>
#include <asm/page.h>
+#include <asm/processor.h>
#include <asm/hcall.h>
#include "io.h"
@@ -97,12 +98,13 @@ static void cpu_init(void)
tb_hz = params.tb_hz;
/* Interrupt Endianness */
-
+ if (!machine_is_powernv()) {
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
- hcall(H_SET_MODE, 1, 4, 0, 0);
+ hcall(H_SET_MODE, 1, 4, 0, 0);
#else
- hcall(H_SET_MODE, 0, 4, 0, 0);
+ hcall(H_SET_MODE, 0, 4, 0, 0);
#endif
+ }
}
static void mem_init(phys_addr_t freemem_start)
diff --git a/lib/ppc64/asm/opal.h b/lib/ppc64/asm/opal.h
new file mode 100644
index 00000000..7b1299f7
--- /dev/null
+++ b/lib/ppc64/asm/opal.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef _ASMPPC64_HCALL_H_
+#define _ASMPPC64_HCALL_H_
+
+#define OPAL_SUCCESS 0
+
+#define OPAL_CONSOLE_WRITE 1
+#define OPAL_CONSOLE_READ 2
+#define OPAL_CEC_POWER_DOWN 5
+#define OPAL_POLL_EVENTS 10
+#define OPAL_REINIT_CPUS 70
+# define OPAL_REINIT_CPUS_HILE_BE (1 << 0)
+# define OPAL_REINIT_CPUS_HILE_LE (1 << 1)
+
+#endif
diff --git a/lib/ppc64/opal-calls.S b/lib/ppc64/opal-calls.S
new file mode 100644
index 00000000..1833358c
--- /dev/null
+++ b/lib/ppc64/opal-calls.S
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2016 IBM Corporation.
+ */
+
+#include <asm/ppc_asm.h>
+
+ .text
+ .globl opal_call
+opal_call:
+ mr r0,r3
+ mr r3,r4
+ mr r4,r5
+ mr r5,r6
+ mr r6,r7
+ mflr r11
+ std r11,16(r1)
+ mfcr r12
+ stw r12,8(r1)
+ mr r13,r2
+
+ /* Set opal return address */
+ LOAD_REG_ADDR(r11, opal_return)
+ mtlr r11
+ mfmsr r12
+
+ /* switch to BE when we enter OPAL */
+ li r11,(1 << MSR_LE_BIT)
+ andc r12,r12,r11
+ mtspr SPR_HSRR1,r12
+
+ /* load the opal call entry point and base */
+ LOAD_REG_ADDR(r11, opal)
+ ld r12,8(r11)
+ ld r2,0(r11)
+ mtspr SPR_HSRR0,r12
+ hrfid
+
+opal_return:
+ FIXUP_ENDIAN
+ mr r2,r13;
+ lwz r11,8(r1);
+ ld r12,16(r1)
+ mtcr r11;
+ mtlr r12
+ blr
diff --git a/lib/ppc64/opal.c b/lib/ppc64/opal.c
new file mode 100644
index 00000000..84ab97b8
--- /dev/null
+++ b/lib/ppc64/opal.c
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * OPAL call helpers
+ */
+#include <asm/opal.h>
+#include <libcflat.h>
+#include <libfdt/libfdt.h>
+#include <devicetree.h>
+#include <asm/io.h>
+#include "../powerpc/io.h"
+
+struct opal {
+ uint64_t base;
+ uint64_t entry;
+} opal;
+
+extern int64_t opal_call(int64_t token, int64_t arg1, int64_t arg2, int64_t arg3);
+
+int opal_init(void)
+{
+ const struct fdt_property *prop;
+ int node, len;
+
+ node = fdt_path_offset(dt_fdt(), "/ibm,opal");
+ if (node < 0)
+ return -1;
+
+ prop = fdt_get_property(dt_fdt(), node, "opal-base-address", &len);
+ if (!prop)
+ return -1;
+ opal.base = fdt64_to_cpu(*(uint64_t *)prop->data);
+
+ prop = fdt_get_property(dt_fdt(), node, "opal-entry-address", &len);
+ if (!prop)
+ return -1;
+ opal.entry = fdt64_to_cpu(*(uint64_t *)prop->data);
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+ if (opal_call(OPAL_REINIT_CPUS, OPAL_REINIT_CPUS_HILE_LE, 0, 0) != OPAL_SUCCESS)
+ return -1;
+#endif
+
+ return 0;
+}
+
+extern void opal_power_off(void)
+{
+ opal_call(OPAL_CEC_POWER_DOWN, 0, 0, 0);
+ while (true)
+ opal_call(OPAL_POLL_EVENTS, 0, 0, 0);
+}
+
+void opal_putchar(int c)
+{
+ unsigned long vty = 0; /* 0 == default */
+ unsigned long nr_chars = cpu_to_be64(1);
+ char ch = c;
+
+ opal_call(OPAL_CONSOLE_WRITE, (int64_t)vty, (int64_t)&nr_chars, (int64_t)&ch);
+}
+
+int __opal_getchar(void)
+{
+ unsigned long vty = 0; /* 0 == default */
+ unsigned long nr_chars = cpu_to_be64(1);
+ char ch;
+ int rc;
+
+ rc = opal_call(OPAL_CONSOLE_READ, (int64_t)vty, (int64_t)&nr_chars, (int64_t)&ch);
+ if (rc != OPAL_SUCCESS)
+ return -1;
+
+ return ch;
+}
diff --git a/powerpc/Makefile.ppc64 b/powerpc/Makefile.ppc64
index b0ed2b10..06a7cf67 100644
--- a/powerpc/Makefile.ppc64
+++ b/powerpc/Makefile.ppc64
@@ -17,6 +17,8 @@ cstart.o = $(TEST_DIR)/cstart64.o
reloc.o = $(TEST_DIR)/reloc64.o
OBJDIRS += lib/ppc64
+cflatobjs += lib/ppc64/opal.o
+cflatobjs += lib/ppc64/opal-calls.o
# ppc64 specific tests
tests = $(TEST_DIR)/spapr_vpa.elf
diff --git a/powerpc/cstart64.S b/powerpc/cstart64.S
index e18ae9a2..185ebad5 100644
--- a/powerpc/cstart64.S
+++ b/powerpc/cstart64.S
@@ -92,6 +92,13 @@ start:
sync
isync
+ /* powernv machine does not check broken_sc1 */
+ mfmsr r3
+ li r4,1
+ sldi r4,r4,MSR_HV_BIT
+ and. r3,r3,r4
+ bne 1f
+
/* patch sc1 if needed */
bl hcall_have_broken_sc1
cmpwi r3, 0
diff --git a/powerpc/run b/powerpc/run
index ee38e075..f4ddd39c 100755
--- a/powerpc/run
+++ b/powerpc/run
@@ -1,5 +1,14 @@
#!/usr/bin/env bash
+get_qemu_machine ()
+{
+ if [ "$MACHINE" ]; then
+ echo $MACHINE
+ else
+ echo pseries
+ fi
+}
+
if [ -z "$KUT_STANDALONE" ]; then
if [ ! -f config.mak ]; then
echo "run ./configure && make first. See ./configure -h"
@@ -12,17 +21,35 @@ fi
ACCEL=$(get_qemu_accelerator) ||
exit $?
+MACHINE=$(get_qemu_machine) ||
+ exit $?
+
+if [[ "$MACHINE" == "powernv"* ]] && [ "$ACCEL" = "kvm" ]; then
+ echo "PowerNV machine does not support KVM. ACCEL=tcg must be specified."
+ exit 2
+fi
+
qemu=$(search_qemu_binary) ||
exit $?
-if ! $qemu -machine '?' 2>&1 | grep 'pseries' > /dev/null; then
- echo "$qemu doesn't support pSeries ('-machine pseries'). Exiting."
+if ! $qemu -machine '?' 2>&1 | grep $MACHINE > /dev/null; then
+ echo "$qemu doesn't support '-machine $MACHINE'. Exiting."
exit 2
fi
-M='-machine pseries'
+M="-machine $MACHINE"
M+=",accel=$ACCEL"
-command="$qemu -nodefaults $M -bios $FIRMWARE"
+B=""
+if [[ "$MACHINE" == "pseries"* ]] ; then
+ B+="-bios $FIRMWARE"
+fi
+
+D=""
+if [[ "$MACHINE" == "powernv"* ]] ; then
+ D+="-device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10"
+fi
+
+command="$qemu -nodefaults $M $B $D"
command+=" -display none -serial stdio -kernel"
command="$(migration_cmd) $(timeout_cmd) $command"
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 11/12] powerpc: Support powernv machine with QEMU TCG
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm
Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Cédric Le Goater,
Nicholas Piggin
This is a basic first pass at powernv support using OPAL (skiboot)
firmware.
The ACCEL is a bit clunky, defaulting to kvm for powernv machine, which
isn't right and has to be manually overridden. It also does not yet run
in the run_tests.sh batch process, more work is needed to exclude
certain tests (e.g., rtas) and adjust parameters (e.g., increase memory
size) to allow powernv to work. For now it can run single test cases.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v3:
- Typo fix [Thomas]
lib/powerpc/asm/ppc_asm.h | 5 +++
lib/powerpc/asm/processor.h | 10 +++++
lib/powerpc/hcall.c | 4 +-
lib/powerpc/io.c | 27 +++++++++++++-
lib/powerpc/io.h | 6 +++
lib/powerpc/processor.c | 10 +++++
lib/powerpc/setup.c | 8 ++--
lib/ppc64/asm/opal.h | 15 ++++++++
lib/ppc64/opal-calls.S | 46 +++++++++++++++++++++++
lib/ppc64/opal.c | 74 +++++++++++++++++++++++++++++++++++++
powerpc/Makefile.ppc64 | 2 +
powerpc/cstart64.S | 7 ++++
powerpc/run | 35 ++++++++++++++++--
13 files changed, 238 insertions(+), 11 deletions(-)
create mode 100644 lib/ppc64/asm/opal.h
create mode 100644 lib/ppc64/opal-calls.S
create mode 100644 lib/ppc64/opal.c
diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h
index 46b4be00..63f11d13 100644
--- a/lib/powerpc/asm/ppc_asm.h
+++ b/lib/powerpc/asm/ppc_asm.h
@@ -39,7 +39,12 @@
#define SPR_HSRR1 0x13B
/* Machine State Register definitions: */
+#define MSR_LE_BIT 0
#define MSR_EE_BIT 15 /* External Interrupts Enable */
+#define MSR_HV_BIT 60 /* Hypervisor mode */
#define MSR_SF_BIT 63 /* 64-bit mode */
+#define SPR_HSRR0 0x13A
+#define SPR_HSRR1 0x13B
+
#endif /* _ASMPOWERPC_PPC_ASM_H */
diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h
index 4ad6612b..9b318c3e 100644
--- a/lib/powerpc/asm/processor.h
+++ b/lib/powerpc/asm/processor.h
@@ -3,6 +3,7 @@
#include <libcflat.h>
#include <asm/ptrace.h>
+#include <asm/ppc_asm.h>
#ifndef __ASSEMBLY__
void handle_exception(int trap, void (*func)(struct pt_regs *, void *), void *);
@@ -43,6 +44,15 @@ static inline void mtmsr(uint64_t msr)
asm volatile ("mtmsrd %[msr]" :: [msr] "r" (msr) : "memory");
}
+/*
+ * This returns true on PowerNV / OPAL machines which run in hypervisor
+ * mode. False on pseries / PAPR machines that run in guest mode.
+ */
+static inline bool machine_is_powernv(void)
+{
+ return !!(mfmsr() & (1ULL << MSR_HV_BIT));
+}
+
static inline uint64_t get_tb(void)
{
return mfspr(SPR_TB);
diff --git a/lib/powerpc/hcall.c b/lib/powerpc/hcall.c
index 711cb1b0..37e52f54 100644
--- a/lib/powerpc/hcall.c
+++ b/lib/powerpc/hcall.c
@@ -25,7 +25,7 @@ int hcall_have_broken_sc1(void)
return r3 == (unsigned long)H_PRIVILEGE;
}
-void putchar(int c)
+void papr_putchar(int c)
{
unsigned long vty = 0; /* 0 == default */
unsigned long nr_chars = 1;
@@ -34,7 +34,7 @@ void putchar(int c)
hcall(H_PUT_TERM_CHAR, vty, nr_chars, chars);
}
-int __getchar(void)
+int __papr_getchar(void)
{
register unsigned long r3 asm("r3") = H_GET_TERM_CHAR;
register unsigned long r4 asm("r4") = 0; /* 0 == default vty */
diff --git a/lib/powerpc/io.c b/lib/powerpc/io.c
index a381688b..ab7bb843 100644
--- a/lib/powerpc/io.c
+++ b/lib/powerpc/io.c
@@ -9,13 +9,33 @@
#include <asm/spinlock.h>
#include <asm/rtas.h>
#include <asm/setup.h>
+#include <asm/processor.h>
#include "io.h"
static struct spinlock print_lock;
+void putchar(int c)
+{
+ if (machine_is_powernv())
+ opal_putchar(c);
+ else
+ papr_putchar(c);
+}
+
+int __getchar(void)
+{
+ if (machine_is_powernv())
+ return __opal_getchar();
+ else
+ return __papr_getchar();
+}
+
void io_init(void)
{
- rtas_init();
+ if (machine_is_powernv())
+ assert(!opal_init());
+ else
+ rtas_init();
}
void puts(const char *s)
@@ -38,7 +58,10 @@ void exit(int code)
// FIXME: change this print-exit/rtas-poweroff to chr_testdev_exit(),
// maybe by plugging chr-testdev into a spapr-vty.
printf("\nEXIT: STATUS=%d\n", ((code) << 1) | 1);
- rtas_power_off();
+ if (machine_is_powernv())
+ opal_power_off();
+ else
+ rtas_power_off();
halt(code);
__builtin_unreachable();
}
diff --git a/lib/powerpc/io.h b/lib/powerpc/io.h
index d4f21ba1..943bf142 100644
--- a/lib/powerpc/io.h
+++ b/lib/powerpc/io.h
@@ -8,6 +8,12 @@
#define _POWERPC_IO_H_
extern void io_init(void);
+extern int opal_init(void);
+extern void opal_power_off(void);
extern void putchar(int c);
+extern void opal_putchar(int c);
+extern void papr_putchar(int c);
+extern int __opal_getchar(void);
+extern int __papr_getchar(void);
#endif
diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
index 64d7ae01..58fea8cf 100644
--- a/lib/powerpc/processor.c
+++ b/lib/powerpc/processor.c
@@ -71,6 +71,16 @@ void sleep_tb(uint64_t cycles)
{
uint64_t start, end, now;
+ if (machine_is_powernv()) {
+ /*
+ * Could use 'stop' to sleep here which would be interesting.
+ * stop with ESL=0 should be simple enough, ESL=1 would require
+ * SRESET based wakeup which is more involved.
+ */
+ delay(cycles);
+ return;
+ }
+
start = now = get_tb();
end = start + cycles;
diff --git a/lib/powerpc/setup.c b/lib/powerpc/setup.c
index 1be4c030..dd758db4 100644
--- a/lib/powerpc/setup.c
+++ b/lib/powerpc/setup.c
@@ -18,6 +18,7 @@
#include <argv.h>
#include <asm/setup.h>
#include <asm/page.h>
+#include <asm/processor.h>
#include <asm/hcall.h>
#include "io.h"
@@ -97,12 +98,13 @@ static void cpu_init(void)
tb_hz = params.tb_hz;
/* Interrupt Endianness */
-
+ if (!machine_is_powernv()) {
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
- hcall(H_SET_MODE, 1, 4, 0, 0);
+ hcall(H_SET_MODE, 1, 4, 0, 0);
#else
- hcall(H_SET_MODE, 0, 4, 0, 0);
+ hcall(H_SET_MODE, 0, 4, 0, 0);
#endif
+ }
}
static void mem_init(phys_addr_t freemem_start)
diff --git a/lib/ppc64/asm/opal.h b/lib/ppc64/asm/opal.h
new file mode 100644
index 00000000..7b1299f7
--- /dev/null
+++ b/lib/ppc64/asm/opal.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef _ASMPPC64_HCALL_H_
+#define _ASMPPC64_HCALL_H_
+
+#define OPAL_SUCCESS 0
+
+#define OPAL_CONSOLE_WRITE 1
+#define OPAL_CONSOLE_READ 2
+#define OPAL_CEC_POWER_DOWN 5
+#define OPAL_POLL_EVENTS 10
+#define OPAL_REINIT_CPUS 70
+# define OPAL_REINIT_CPUS_HILE_BE (1 << 0)
+# define OPAL_REINIT_CPUS_HILE_LE (1 << 1)
+
+#endif
diff --git a/lib/ppc64/opal-calls.S b/lib/ppc64/opal-calls.S
new file mode 100644
index 00000000..1833358c
--- /dev/null
+++ b/lib/ppc64/opal-calls.S
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2016 IBM Corporation.
+ */
+
+#include <asm/ppc_asm.h>
+
+ .text
+ .globl opal_call
+opal_call:
+ mr r0,r3
+ mr r3,r4
+ mr r4,r5
+ mr r5,r6
+ mr r6,r7
+ mflr r11
+ std r11,16(r1)
+ mfcr r12
+ stw r12,8(r1)
+ mr r13,r2
+
+ /* Set opal return address */
+ LOAD_REG_ADDR(r11, opal_return)
+ mtlr r11
+ mfmsr r12
+
+ /* switch to BE when we enter OPAL */
+ li r11,(1 << MSR_LE_BIT)
+ andc r12,r12,r11
+ mtspr SPR_HSRR1,r12
+
+ /* load the opal call entry point and base */
+ LOAD_REG_ADDR(r11, opal)
+ ld r12,8(r11)
+ ld r2,0(r11)
+ mtspr SPR_HSRR0,r12
+ hrfid
+
+opal_return:
+ FIXUP_ENDIAN
+ mr r2,r13;
+ lwz r11,8(r1);
+ ld r12,16(r1)
+ mtcr r11;
+ mtlr r12
+ blr
diff --git a/lib/ppc64/opal.c b/lib/ppc64/opal.c
new file mode 100644
index 00000000..84ab97b8
--- /dev/null
+++ b/lib/ppc64/opal.c
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * OPAL call helpers
+ */
+#include <asm/opal.h>
+#include <libcflat.h>
+#include <libfdt/libfdt.h>
+#include <devicetree.h>
+#include <asm/io.h>
+#include "../powerpc/io.h"
+
+struct opal {
+ uint64_t base;
+ uint64_t entry;
+} opal;
+
+extern int64_t opal_call(int64_t token, int64_t arg1, int64_t arg2, int64_t arg3);
+
+int opal_init(void)
+{
+ const struct fdt_property *prop;
+ int node, len;
+
+ node = fdt_path_offset(dt_fdt(), "/ibm,opal");
+ if (node < 0)
+ return -1;
+
+ prop = fdt_get_property(dt_fdt(), node, "opal-base-address", &len);
+ if (!prop)
+ return -1;
+ opal.base = fdt64_to_cpu(*(uint64_t *)prop->data);
+
+ prop = fdt_get_property(dt_fdt(), node, "opal-entry-address", &len);
+ if (!prop)
+ return -1;
+ opal.entry = fdt64_to_cpu(*(uint64_t *)prop->data);
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+ if (opal_call(OPAL_REINIT_CPUS, OPAL_REINIT_CPUS_HILE_LE, 0, 0) != OPAL_SUCCESS)
+ return -1;
+#endif
+
+ return 0;
+}
+
+extern void opal_power_off(void)
+{
+ opal_call(OPAL_CEC_POWER_DOWN, 0, 0, 0);
+ while (true)
+ opal_call(OPAL_POLL_EVENTS, 0, 0, 0);
+}
+
+void opal_putchar(int c)
+{
+ unsigned long vty = 0; /* 0 == default */
+ unsigned long nr_chars = cpu_to_be64(1);
+ char ch = c;
+
+ opal_call(OPAL_CONSOLE_WRITE, (int64_t)vty, (int64_t)&nr_chars, (int64_t)&ch);
+}
+
+int __opal_getchar(void)
+{
+ unsigned long vty = 0; /* 0 == default */
+ unsigned long nr_chars = cpu_to_be64(1);
+ char ch;
+ int rc;
+
+ rc = opal_call(OPAL_CONSOLE_READ, (int64_t)vty, (int64_t)&nr_chars, (int64_t)&ch);
+ if (rc != OPAL_SUCCESS)
+ return -1;
+
+ return ch;
+}
diff --git a/powerpc/Makefile.ppc64 b/powerpc/Makefile.ppc64
index b0ed2b10..06a7cf67 100644
--- a/powerpc/Makefile.ppc64
+++ b/powerpc/Makefile.ppc64
@@ -17,6 +17,8 @@ cstart.o = $(TEST_DIR)/cstart64.o
reloc.o = $(TEST_DIR)/reloc64.o
OBJDIRS += lib/ppc64
+cflatobjs += lib/ppc64/opal.o
+cflatobjs += lib/ppc64/opal-calls.o
# ppc64 specific tests
tests = $(TEST_DIR)/spapr_vpa.elf
diff --git a/powerpc/cstart64.S b/powerpc/cstart64.S
index e18ae9a2..185ebad5 100644
--- a/powerpc/cstart64.S
+++ b/powerpc/cstart64.S
@@ -92,6 +92,13 @@ start:
sync
isync
+ /* powernv machine does not check broken_sc1 */
+ mfmsr r3
+ li r4,1
+ sldi r4,r4,MSR_HV_BIT
+ and. r3,r3,r4
+ bne 1f
+
/* patch sc1 if needed */
bl hcall_have_broken_sc1
cmpwi r3, 0
diff --git a/powerpc/run b/powerpc/run
index ee38e075..f4ddd39c 100755
--- a/powerpc/run
+++ b/powerpc/run
@@ -1,5 +1,14 @@
#!/usr/bin/env bash
+get_qemu_machine ()
+{
+ if [ "$MACHINE" ]; then
+ echo $MACHINE
+ else
+ echo pseries
+ fi
+}
+
if [ -z "$KUT_STANDALONE" ]; then
if [ ! -f config.mak ]; then
echo "run ./configure && make first. See ./configure -h"
@@ -12,17 +21,35 @@ fi
ACCEL=$(get_qemu_accelerator) ||
exit $?
+MACHINE=$(get_qemu_machine) ||
+ exit $?
+
+if [[ "$MACHINE" == "powernv"* ]] && [ "$ACCEL" = "kvm" ]; then
+ echo "PowerNV machine does not support KVM. ACCEL=tcg must be specified."
+ exit 2
+fi
+
qemu=$(search_qemu_binary) ||
exit $?
-if ! $qemu -machine '?' 2>&1 | grep 'pseries' > /dev/null; then
- echo "$qemu doesn't support pSeries ('-machine pseries'). Exiting."
+if ! $qemu -machine '?' 2>&1 | grep $MACHINE > /dev/null; then
+ echo "$qemu doesn't support '-machine $MACHINE'. Exiting."
exit 2
fi
-M='-machine pseries'
+M="-machine $MACHINE"
M+=",accel=$ACCEL"
-command="$qemu -nodefaults $M -bios $FIRMWARE"
+B=""
+if [[ "$MACHINE" == "pseries"* ]] ; then
+ B+="-bios $FIRMWARE"
+fi
+
+D=""
+if [[ "$MACHINE" == "powernv"* ]] ; then
+ D+="-device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10"
+fi
+
+command="$qemu -nodefaults $M $B $D"
command+=" -display none -serial stdio -kernel"
command="$(migration_cmd) $(timeout_cmd) $command"
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 12/12] powerpc/sprs: Test hypervisor registers on powernv machine
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-08 7:58 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Nicholas Piggin, linuxppc-dev, Laurent Vivier, Thomas Huth
This enables HV privilege registers to be tested with the powernv
machine.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
powerpc/sprs.c | 33 +++++++++++++++++++++++++--------
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index d5664201..07a4e759 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -199,16 +199,16 @@ static const struct spr sprs_power_common[1024] = {
[190] = {"HFSCR", 64, HV_RW, },
[256] = {"VRSAVE", 32, RW, },
[259] = {"SPRG3", 64, RO, },
-[284] = {"TBL", 32, HV_WO, },
-[285] = {"TBU", 32, HV_WO, },
-[286] = {"TBU40", 64, HV_WO, },
+[284] = {"TBL", 32, HV_WO, }, /* Things can go a bit wonky with */
+[285] = {"TBU", 32, HV_WO, }, /* Timebase changing. Should save */
+[286] = {"TBU40", 64, HV_WO, }, /* and restore it. */
[304] = {"HSPRG0", 64, HV_RW, },
[305] = {"HSPRG1", 64, HV_RW, },
[306] = {"HDSISR", 32, HV_RW, SPR_INT, },
[307] = {"HDAR", 64, HV_RW, SPR_INT, },
[308] = {"SPURR", 64, HV_RW | OS_RO, SPR_ASYNC, },
[309] = {"PURR", 64, HV_RW | OS_RO, SPR_ASYNC, },
-[313] = {"HRMOR", 64, HV_RW, },
+[313] = {"HRMOR", 64, HV_RW, SPR_HARNESS, }, /* Harness can't cope with HRMOR changing */
[314] = {"HSRR0", 64, HV_RW, SPR_INT, },
[315] = {"HSRR1", 64, HV_RW, SPR_INT, },
[318] = {"LPCR", 64, HV_RW, },
@@ -306,7 +306,7 @@ static const struct spr sprs_power9_10[1024] = {
[921] = {"TSCR", 32, HV_RW, },
[922] = {"TTR", 64, HV_RW, },
[1006]= {"TRACE", 64, WO, },
-[1008]= {"HID", 64, HV_RW, },
+[1008]= {"HID", 64, HV_RW, SPR_HARNESS, }, /* At least HILE would be unhelpful to change */
};
/* This covers POWER8 and POWER9 PMUs */
@@ -350,6 +350,22 @@ static const struct spr sprs_power10_pmu[1024] = {
static struct spr sprs[1024];
+static bool spr_read_perms(int spr)
+{
+ if (machine_is_powernv())
+ return !!(sprs[spr].access & SPR_HV_READ);
+ else
+ return !!(sprs[spr].access & SPR_OS_READ);
+}
+
+static bool spr_write_perms(int spr)
+{
+ if (machine_is_powernv())
+ return !!(sprs[spr].access & SPR_HV_WRITE);
+ else
+ return !!(sprs[spr].access & SPR_OS_WRITE);
+}
+
static void setup_sprs(void)
{
uint32_t pvr = mfspr(287); /* Processor Version Register */
@@ -466,7 +482,7 @@ static void get_sprs(uint64_t *v)
int i;
for (i = 0; i < 1024; i++) {
- if (!(sprs[i].access & SPR_OS_READ))
+ if (!spr_read_perms(i))
continue;
v[i] = __mfspr(i);
}
@@ -477,8 +493,9 @@ static void set_sprs(uint64_t val)
int i;
for (i = 0; i < 1024; i++) {
- if (!(sprs[i].access & SPR_OS_WRITE))
+ if (!spr_write_perms(i))
continue;
+
if (sprs[i].type & SPR_HARNESS)
continue;
if (!strcmp(sprs[i].name, "MMCR0")) {
@@ -550,7 +567,7 @@ int main(int argc, char **argv)
for (i = 0; i < 1024; i++) {
bool pass = true;
- if (!(sprs[i].access & SPR_OS_READ))
+ if (!spr_read_perms(i))
continue;
if (sprs[i].width == 32) {
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [kvm-unit-tests v4 12/12] powerpc/sprs: Test hypervisor registers on powernv machine
@ 2023-06-08 7:58 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-08 7:58 UTC (permalink / raw)
To: kvm; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, Nicholas Piggin
This enables HV privilege registers to be tested with the powernv
machine.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
powerpc/sprs.c | 33 +++++++++++++++++++++++++--------
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index d5664201..07a4e759 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -199,16 +199,16 @@ static const struct spr sprs_power_common[1024] = {
[190] = {"HFSCR", 64, HV_RW, },
[256] = {"VRSAVE", 32, RW, },
[259] = {"SPRG3", 64, RO, },
-[284] = {"TBL", 32, HV_WO, },
-[285] = {"TBU", 32, HV_WO, },
-[286] = {"TBU40", 64, HV_WO, },
+[284] = {"TBL", 32, HV_WO, }, /* Things can go a bit wonky with */
+[285] = {"TBU", 32, HV_WO, }, /* Timebase changing. Should save */
+[286] = {"TBU40", 64, HV_WO, }, /* and restore it. */
[304] = {"HSPRG0", 64, HV_RW, },
[305] = {"HSPRG1", 64, HV_RW, },
[306] = {"HDSISR", 32, HV_RW, SPR_INT, },
[307] = {"HDAR", 64, HV_RW, SPR_INT, },
[308] = {"SPURR", 64, HV_RW | OS_RO, SPR_ASYNC, },
[309] = {"PURR", 64, HV_RW | OS_RO, SPR_ASYNC, },
-[313] = {"HRMOR", 64, HV_RW, },
+[313] = {"HRMOR", 64, HV_RW, SPR_HARNESS, }, /* Harness can't cope with HRMOR changing */
[314] = {"HSRR0", 64, HV_RW, SPR_INT, },
[315] = {"HSRR1", 64, HV_RW, SPR_INT, },
[318] = {"LPCR", 64, HV_RW, },
@@ -306,7 +306,7 @@ static const struct spr sprs_power9_10[1024] = {
[921] = {"TSCR", 32, HV_RW, },
[922] = {"TTR", 64, HV_RW, },
[1006]= {"TRACE", 64, WO, },
-[1008]= {"HID", 64, HV_RW, },
+[1008]= {"HID", 64, HV_RW, SPR_HARNESS, }, /* At least HILE would be unhelpful to change */
};
/* This covers POWER8 and POWER9 PMUs */
@@ -350,6 +350,22 @@ static const struct spr sprs_power10_pmu[1024] = {
static struct spr sprs[1024];
+static bool spr_read_perms(int spr)
+{
+ if (machine_is_powernv())
+ return !!(sprs[spr].access & SPR_HV_READ);
+ else
+ return !!(sprs[spr].access & SPR_OS_READ);
+}
+
+static bool spr_write_perms(int spr)
+{
+ if (machine_is_powernv())
+ return !!(sprs[spr].access & SPR_HV_WRITE);
+ else
+ return !!(sprs[spr].access & SPR_OS_WRITE);
+}
+
static void setup_sprs(void)
{
uint32_t pvr = mfspr(287); /* Processor Version Register */
@@ -466,7 +482,7 @@ static void get_sprs(uint64_t *v)
int i;
for (i = 0; i < 1024; i++) {
- if (!(sprs[i].access & SPR_OS_READ))
+ if (!spr_read_perms(i))
continue;
v[i] = __mfspr(i);
}
@@ -477,8 +493,9 @@ static void set_sprs(uint64_t val)
int i;
for (i = 0; i < 1024; i++) {
- if (!(sprs[i].access & SPR_OS_WRITE))
+ if (!spr_write_perms(i))
continue;
+
if (sprs[i].type & SPR_HARNESS)
continue;
if (!strcmp(sprs[i].name, "MMCR0")) {
@@ -550,7 +567,7 @@ int main(int argc, char **argv)
for (i = 0; i < 1024; i++) {
bool pass = true;
- if (!(sprs[i].access & SPR_OS_READ))
+ if (!spr_read_perms(i))
continue;
if (sprs[i].width == 32) {
--
2.40.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-14 1:09 ` Joel Stanley
-1 siblings, 0 replies; 42+ messages in thread
From: Joel Stanley @ 2023-06-14 1:09 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: kvm, Laurent Vivier, Thomas Huth, linuxppc-dev
On Thu, 8 Jun 2023 at 07:58, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> Posting again, a couple of patches were merged and accounted for review
> comments from last time.
I saw some failures in the spr tests running on a power9 powernv system:
$ TESTNAME=sprs TIMEOUT=90s ACCEL= ./powerpc/run powerpc/sprs.elf -smp
1 |grep FAIL
FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
$ MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL=
./powerpc/run powerpc/sprs.elf -smp 1 -append '-w' | grep FAIL
FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402244
FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001001
FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
FAIL: PIR (1023): 0x00000010 <==> 0x00000049
Linux 6.2.0-20-generic
QEMU emulator version 7.2.0 (Debian 1:7.2+dfsg-5ubuntu2)
On a power8 powernv:
MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL= ./powerpc/run
powerpc/sprs.elf -smp 1 -append '-w' |grep FAIL
FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402234
FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001000
FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
FAIL: PIR (1023): 0x00000060 <==> 0x00000030
Linux 5.4.0-146-generic
QEMU emulator version 4.2.1 (Debian 1:4.2-3ubuntu6.26)
Cheers,
Joel
>
> Thanks,
> Nick
>
> Nicholas Piggin (12):
> powerpc: Report instruction address and MSR in unhandled exception
> error
> powerpc: Add some checking to exception handler install
> powerpc: Abstract H_CEDE calls into a sleep functions
> powerpc: Add ISA v3.1 (POWER10) support to SPR test
> powerpc: Extract some common helpers and defines to headers
> powerpc/sprs: Specify SPRs with data rather than code
> powerpc/spapr_vpa: Add basic VPA tests
> powerpc: Expand exception handler vector granularity
> powerpc: Add support for more interrupts including HV interrupts
> powerpc: Discover runtime load address dynamically
> powerpc: Support powernv machine with QEMU TCG
> powerpc/sprs: Test hypervisor registers on powernv machine
>
> lib/powerpc/asm/handlers.h | 2 +-
> lib/powerpc/asm/hcall.h | 1 +
> lib/powerpc/asm/ppc_asm.h | 9 +
> lib/powerpc/asm/processor.h | 55 ++-
> lib/powerpc/handlers.c | 10 +-
> lib/powerpc/hcall.c | 4 +-
> lib/powerpc/io.c | 27 +-
> lib/powerpc/io.h | 6 +
> lib/powerpc/processor.c | 79 ++++-
> lib/powerpc/setup.c | 8 +-
> lib/ppc64/asm/opal.h | 15 +
> lib/ppc64/asm/vpa.h | 62 ++++
> lib/ppc64/opal-calls.S | 46 +++
> lib/ppc64/opal.c | 74 +++++
> powerpc/Makefile.ppc64 | 4 +-
> powerpc/cstart64.S | 105 ++++--
> powerpc/run | 35 +-
> powerpc/spapr_hcall.c | 9 +-
> powerpc/spapr_vpa.c | 172 ++++++++++
> powerpc/sprs.c | 645 ++++++++++++++++++++++++++----------
> powerpc/tm.c | 20 +-
> powerpc/unittests.cfg | 3 +
> 22 files changed, 1133 insertions(+), 258 deletions(-)
> create mode 100644 lib/ppc64/asm/opal.h
> create mode 100644 lib/ppc64/asm/vpa.h
> create mode 100644 lib/ppc64/opal-calls.S
> create mode 100644 lib/ppc64/opal.c
> create mode 100644 powerpc/spapr_vpa.c
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
@ 2023-06-14 1:09 ` Joel Stanley
0 siblings, 0 replies; 42+ messages in thread
From: Joel Stanley @ 2023-06-14 1:09 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: Laurent Vivier, Thomas Huth, linuxppc-dev, kvm
On Thu, 8 Jun 2023 at 07:58, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> Posting again, a couple of patches were merged and accounted for review
> comments from last time.
I saw some failures in the spr tests running on a power9 powernv system:
$ TESTNAME=sprs TIMEOUT=90s ACCEL= ./powerpc/run powerpc/sprs.elf -smp
1 |grep FAIL
FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
$ MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL=
./powerpc/run powerpc/sprs.elf -smp 1 -append '-w' | grep FAIL
FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402244
FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001001
FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
FAIL: PIR (1023): 0x00000010 <==> 0x00000049
Linux 6.2.0-20-generic
QEMU emulator version 7.2.0 (Debian 1:7.2+dfsg-5ubuntu2)
On a power8 powernv:
MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL= ./powerpc/run
powerpc/sprs.elf -smp 1 -append '-w' |grep FAIL
FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402234
FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001000
FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
FAIL: PIR (1023): 0x00000060 <==> 0x00000030
Linux 5.4.0-146-generic
QEMU emulator version 4.2.1 (Debian 1:4.2-3ubuntu6.26)
Cheers,
Joel
>
> Thanks,
> Nick
>
> Nicholas Piggin (12):
> powerpc: Report instruction address and MSR in unhandled exception
> error
> powerpc: Add some checking to exception handler install
> powerpc: Abstract H_CEDE calls into a sleep functions
> powerpc: Add ISA v3.1 (POWER10) support to SPR test
> powerpc: Extract some common helpers and defines to headers
> powerpc/sprs: Specify SPRs with data rather than code
> powerpc/spapr_vpa: Add basic VPA tests
> powerpc: Expand exception handler vector granularity
> powerpc: Add support for more interrupts including HV interrupts
> powerpc: Discover runtime load address dynamically
> powerpc: Support powernv machine with QEMU TCG
> powerpc/sprs: Test hypervisor registers on powernv machine
>
> lib/powerpc/asm/handlers.h | 2 +-
> lib/powerpc/asm/hcall.h | 1 +
> lib/powerpc/asm/ppc_asm.h | 9 +
> lib/powerpc/asm/processor.h | 55 ++-
> lib/powerpc/handlers.c | 10 +-
> lib/powerpc/hcall.c | 4 +-
> lib/powerpc/io.c | 27 +-
> lib/powerpc/io.h | 6 +
> lib/powerpc/processor.c | 79 ++++-
> lib/powerpc/setup.c | 8 +-
> lib/ppc64/asm/opal.h | 15 +
> lib/ppc64/asm/vpa.h | 62 ++++
> lib/ppc64/opal-calls.S | 46 +++
> lib/ppc64/opal.c | 74 +++++
> powerpc/Makefile.ppc64 | 4 +-
> powerpc/cstart64.S | 105 ++++--
> powerpc/run | 35 +-
> powerpc/spapr_hcall.c | 9 +-
> powerpc/spapr_vpa.c | 172 ++++++++++
> powerpc/sprs.c | 645 ++++++++++++++++++++++++++----------
> powerpc/tm.c | 20 +-
> powerpc/unittests.cfg | 3 +
> 22 files changed, 1133 insertions(+), 258 deletions(-)
> create mode 100644 lib/ppc64/asm/opal.h
> create mode 100644 lib/ppc64/asm/vpa.h
> create mode 100644 lib/ppc64/opal-calls.S
> create mode 100644 lib/ppc64/opal.c
> create mode 100644 powerpc/spapr_vpa.c
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
2023-06-14 1:09 ` Joel Stanley
@ 2023-06-15 3:02 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-15 3:02 UTC (permalink / raw)
To: Joel Stanley
Cc: kvm, Laurent Vivier, Thomas Huth, linuxppc-dev, qemu-ppc, qemu-devel
On Wed Jun 14, 2023 at 11:09 AM AEST, Joel Stanley wrote:
> On Thu, 8 Jun 2023 at 07:58, Nicholas Piggin <npiggin@gmail.com> wrote:
> >
> > Posting again, a couple of patches were merged and accounted for review
> > comments from last time.
>
> I saw some failures in the spr tests running on a power9 powernv system:
>
> $ TESTNAME=sprs TIMEOUT=90s ACCEL= ./powerpc/run powerpc/sprs.elf -smp
> 1 |grep FAIL
> FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
This is just TCG machine? I'm not sure why WORT fails, AFAIKS it's the
same on POWER8 and doesn't do anything just a simple register. I think
on real hardware WORT may not have any bits implemented on POWER9
though.
> $ MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL=
> ./powerpc/run powerpc/sprs.elf -smp 1 -append '-w' | grep FAIL
> FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402244
> FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001001
> FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
> FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
> FAIL: PIR (1023): 0x00000010 <==> 0x00000049
>
> Linux 6.2.0-20-generic
> QEMU emulator version 7.2.0 (Debian 1:7.2+dfsg-5ubuntu2)
>
> On a power8 powernv:
>
> MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL= ./powerpc/run
> powerpc/sprs.elf -smp 1 -append '-w' |grep FAIL
> FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402234
> FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001000
> FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
> FAIL: PIR (1023): 0x00000060 <==> 0x00000030
Hmm, seems we take some interrupt over migration test that is not
accounted for (could check the address in SRR0 to see where it is).
Either need to prevent that interrupt or avoid failing on SRR0/1 on
this test.
Interesting about CTRL, I wonder if that not migrating correctly.
PIR looks like a migration issue as well, it can't be changed so
destination CPU has got a different PIR. I would be inclined to
leave those as failing to remind us to look into them.
I'll take a look at the others though.
Thanks,
Nick
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
@ 2023-06-15 3:02 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-06-15 3:02 UTC (permalink / raw)
To: Joel Stanley
Cc: Laurent Vivier, Thomas Huth, kvm, qemu-devel, qemu-ppc, linuxppc-dev
On Wed Jun 14, 2023 at 11:09 AM AEST, Joel Stanley wrote:
> On Thu, 8 Jun 2023 at 07:58, Nicholas Piggin <npiggin@gmail.com> wrote:
> >
> > Posting again, a couple of patches were merged and accounted for review
> > comments from last time.
>
> I saw some failures in the spr tests running on a power9 powernv system:
>
> $ TESTNAME=sprs TIMEOUT=90s ACCEL= ./powerpc/run powerpc/sprs.elf -smp
> 1 |grep FAIL
> FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
This is just TCG machine? I'm not sure why WORT fails, AFAIKS it's the
same on POWER8 and doesn't do anything just a simple register. I think
on real hardware WORT may not have any bits implemented on POWER9
though.
> $ MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL=
> ./powerpc/run powerpc/sprs.elf -smp 1 -append '-w' | grep FAIL
> FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402244
> FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001001
> FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
> FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
> FAIL: PIR (1023): 0x00000010 <==> 0x00000049
>
> Linux 6.2.0-20-generic
> QEMU emulator version 7.2.0 (Debian 1:7.2+dfsg-5ubuntu2)
>
> On a power8 powernv:
>
> MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL= ./powerpc/run
> powerpc/sprs.elf -smp 1 -append '-w' |grep FAIL
> FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402234
> FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001000
> FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
> FAIL: PIR (1023): 0x00000060 <==> 0x00000030
Hmm, seems we take some interrupt over migration test that is not
accounted for (could check the address in SRR0 to see where it is).
Either need to prevent that interrupt or avoid failing on SRR0/1 on
this test.
Interesting about CTRL, I wonder if that not migrating correctly.
PIR looks like a migration issue as well, it can't be changed so
destination CPU has got a different PIR. I would be inclined to
leave those as failing to remind us to look into them.
I'll take a look at the others though.
Thanks,
Nick
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
2023-06-15 3:02 ` Nicholas Piggin
@ 2023-06-15 8:11 ` Joel Stanley
-1 siblings, 0 replies; 42+ messages in thread
From: Joel Stanley @ 2023-06-15 8:11 UTC (permalink / raw)
To: Nicholas Piggin
Cc: kvm, Laurent Vivier, Thomas Huth, linuxppc-dev, qemu-ppc, qemu-devel
On Thu, 15 Jun 2023 at 03:02, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> On Wed Jun 14, 2023 at 11:09 AM AEST, Joel Stanley wrote:
> > On Thu, 8 Jun 2023 at 07:58, Nicholas Piggin <npiggin@gmail.com> wrote:
> > >
> > > Posting again, a couple of patches were merged and accounted for review
> > > comments from last time.
> >
> > I saw some failures in the spr tests running on a power9 powernv system:
> >
> > $ TESTNAME=sprs TIMEOUT=90s ACCEL= ./powerpc/run powerpc/sprs.elf -smp
> > 1 |grep FAIL
> > FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
>
> This is just TCG machine? I'm not sure why WORT fails, AFAIKS it's the
> same on POWER8 and doesn't do anything just a simple register. I think
> on real hardware WORT may not have any bits implemented on POWER9
> though.
Yeah, just the TCG machine. Now that you point it out all of the
failures I reported are for ACCEL=<blank>, so they are running in tcg
mode.
run_migration timeout -k 1s --foreground 90s
/usr/bin/qemu-system-ppc64 -nodefaults -machine pseries,accel=tcg
-bios powerpc/boot_rom.bin -display none -serial stdio -kernel
powerpc/sprs.elf -smp 1 -append -w # -initrd /tmp/tmp.61XhbvCGcb
>
> > $ MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL=
> > ./powerpc/run powerpc/sprs.elf -smp 1 -append '-w' | grep FAIL
> > FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402244
> > FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001001
> > FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
> > FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
> > FAIL: PIR (1023): 0x00000010 <==> 0x00000049
> >
> > Linux 6.2.0-20-generic
> > QEMU emulator version 7.2.0 (Debian 1:7.2+dfsg-5ubuntu2)
> >
> > On a power8 powernv:
> >
> > MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL= ./powerpc/run
> > powerpc/sprs.elf -smp 1 -append '-w' |grep FAIL
> > FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402234
> > FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001000
> > FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
> > FAIL: PIR (1023): 0x00000060 <==> 0x00000030
>
> Hmm, seems we take some interrupt over migration test that is not
> accounted for (could check the address in SRR0 to see where it is).
> Either need to prevent that interrupt or avoid failing on SRR0/1 on
> this test.
>
> Interesting about CTRL, I wonder if that not migrating correctly.
> PIR looks like a migration issue as well, it can't be changed so
> destination CPU has got a different PIR. I would be inclined to
> leave those as failing to remind us to look into them.
>
> I'll take a look at the others though.
>
> Thanks,
> Nick
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
@ 2023-06-15 8:11 ` Joel Stanley
0 siblings, 0 replies; 42+ messages in thread
From: Joel Stanley @ 2023-06-15 8:11 UTC (permalink / raw)
To: Nicholas Piggin
Cc: Laurent Vivier, Thomas Huth, kvm, qemu-devel, qemu-ppc, linuxppc-dev
On Thu, 15 Jun 2023 at 03:02, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> On Wed Jun 14, 2023 at 11:09 AM AEST, Joel Stanley wrote:
> > On Thu, 8 Jun 2023 at 07:58, Nicholas Piggin <npiggin@gmail.com> wrote:
> > >
> > > Posting again, a couple of patches were merged and accounted for review
> > > comments from last time.
> >
> > I saw some failures in the spr tests running on a power9 powernv system:
> >
> > $ TESTNAME=sprs TIMEOUT=90s ACCEL= ./powerpc/run powerpc/sprs.elf -smp
> > 1 |grep FAIL
> > FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
>
> This is just TCG machine? I'm not sure why WORT fails, AFAIKS it's the
> same on POWER8 and doesn't do anything just a simple register. I think
> on real hardware WORT may not have any bits implemented on POWER9
> though.
Yeah, just the TCG machine. Now that you point it out all of the
failures I reported are for ACCEL=<blank>, so they are running in tcg
mode.
run_migration timeout -k 1s --foreground 90s
/usr/bin/qemu-system-ppc64 -nodefaults -machine pseries,accel=tcg
-bios powerpc/boot_rom.bin -display none -serial stdio -kernel
powerpc/sprs.elf -smp 1 -append -w # -initrd /tmp/tmp.61XhbvCGcb
>
> > $ MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL=
> > ./powerpc/run powerpc/sprs.elf -smp 1 -append '-w' | grep FAIL
> > FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402244
> > FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001001
> > FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
> > FAIL: WORT ( 895): 0x00000000c0deba80 <==> 0x0000000000000000
> > FAIL: PIR (1023): 0x00000010 <==> 0x00000049
> >
> > Linux 6.2.0-20-generic
> > QEMU emulator version 7.2.0 (Debian 1:7.2+dfsg-5ubuntu2)
> >
> > On a power8 powernv:
> >
> > MIGRATION=yes TESTNAME=sprs-migration TIMEOUT=90s ACCEL= ./powerpc/run
> > powerpc/sprs.elf -smp 1 -append '-w' |grep FAIL
> > FAIL: SRR0 ( 26): 0xcafefacec0debabc <==> 0x0000000000402234
> > FAIL: SRR1 ( 27): 0xc0000006409ebab6 <==> 0x8000000000001000
> > FAIL: CTRL ( 136): 0x00000000 <==> 0x00008001
> > FAIL: PIR (1023): 0x00000060 <==> 0x00000030
>
> Hmm, seems we take some interrupt over migration test that is not
> accounted for (could check the address in SRR0 to see where it is).
> Either need to prevent that interrupt or avoid failing on SRR0/1 on
> this test.
>
> Interesting about CTRL, I wonder if that not migrating correctly.
> PIR looks like a migration issue as well, it can't be changed so
> destination CPU has got a different PIR. I would be inclined to
> leave those as failing to remind us to look into them.
>
> I'll take a look at the others though.
>
> Thanks,
> Nick
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 01/12] powerpc: Report instruction address and MSR in unhandled exception error
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-21 14:53 ` Thomas Huth
-1 siblings, 0 replies; 42+ messages in thread
From: Thomas Huth @ 2023-06-21 14:53 UTC (permalink / raw)
To: Nicholas Piggin, kvm; +Cc: Laurent Vivier, linuxppc-dev
On 08/06/2023 09.58, Nicholas Piggin wrote:
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> Since v3:
> - New patch
>
> lib/powerpc/processor.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
> index ec85b9d8..05b4b04f 100644
> --- a/lib/powerpc/processor.c
> +++ b/lib/powerpc/processor.c
> @@ -38,7 +38,7 @@ void do_handle_exception(struct pt_regs *regs)
> return;
> }
>
> - printf("unhandled cpu exception %#lx\n", regs->trap);
> + printf("unhandled cpu exception %#lx at NIA:0x%016lx MSR:0x%016lx\n", regs->trap, regs->nip, regs->msr);
<bikeshedding> Why NIA and not NIP ? </bikeshedding>
Thomas
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 01/12] powerpc: Report instruction address and MSR in unhandled exception error
@ 2023-06-21 14:53 ` Thomas Huth
0 siblings, 0 replies; 42+ messages in thread
From: Thomas Huth @ 2023-06-21 14:53 UTC (permalink / raw)
To: Nicholas Piggin, kvm; +Cc: linuxppc-dev, Laurent Vivier
On 08/06/2023 09.58, Nicholas Piggin wrote:
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> Since v3:
> - New patch
>
> lib/powerpc/processor.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
> index ec85b9d8..05b4b04f 100644
> --- a/lib/powerpc/processor.c
> +++ b/lib/powerpc/processor.c
> @@ -38,7 +38,7 @@ void do_handle_exception(struct pt_regs *regs)
> return;
> }
>
> - printf("unhandled cpu exception %#lx\n", regs->trap);
> + printf("unhandled cpu exception %#lx at NIA:0x%016lx MSR:0x%016lx\n", regs->trap, regs->nip, regs->msr);
<bikeshedding> Why NIA and not NIP ? </bikeshedding>
Thomas
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 02/12] powerpc: Add some checking to exception handler install
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-06-21 14:54 ` Thomas Huth
-1 siblings, 0 replies; 42+ messages in thread
From: Thomas Huth @ 2023-06-21 14:54 UTC (permalink / raw)
To: Nicholas Piggin, kvm; +Cc: Laurent Vivier, linuxppc-dev
On 08/06/2023 09.58, Nicholas Piggin wrote:
> Check to ensure exception handlers are not being overwritten or
> invalid exception numbers are used.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> Since v3:
> - Simplified code as suggested by Thomas.
>
> lib/powerpc/processor.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
> index 05b4b04f..0550e4fc 100644
> --- a/lib/powerpc/processor.c
> +++ b/lib/powerpc/processor.c
> @@ -19,12 +19,16 @@ static struct {
> void handle_exception(int trap, void (*func)(struct pt_regs *, void *),
> void * data)
> {
> + assert(!(trap & ~0xf00));
> +
> trap >>= 8;
>
> - if (trap < 16) {
> - handlers[trap].func = func;
> - handlers[trap].data = data;
> + if (func && handlers[trap].func) {
> + printf("exception handler installed twice %#x\n", trap);
> + abort();
> }
> + handlers[trap].func = func;
> + handlers[trap].data = data;
> }
>
> void do_handle_exception(struct pt_regs *regs)
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 02/12] powerpc: Add some checking to exception handler install
@ 2023-06-21 14:54 ` Thomas Huth
0 siblings, 0 replies; 42+ messages in thread
From: Thomas Huth @ 2023-06-21 14:54 UTC (permalink / raw)
To: Nicholas Piggin, kvm; +Cc: linuxppc-dev, Laurent Vivier
On 08/06/2023 09.58, Nicholas Piggin wrote:
> Check to ensure exception handlers are not being overwritten or
> invalid exception numbers are used.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> Since v3:
> - Simplified code as suggested by Thomas.
>
> lib/powerpc/processor.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
> index 05b4b04f..0550e4fc 100644
> --- a/lib/powerpc/processor.c
> +++ b/lib/powerpc/processor.c
> @@ -19,12 +19,16 @@ static struct {
> void handle_exception(int trap, void (*func)(struct pt_regs *, void *),
> void * data)
> {
> + assert(!(trap & ~0xf00));
> +
> trap >>= 8;
>
> - if (trap < 16) {
> - handlers[trap].func = func;
> - handlers[trap].data = data;
> + if (func && handlers[trap].func) {
> + printf("exception handler installed twice %#x\n", trap);
> + abort();
> }
> + handlers[trap].func = func;
> + handlers[trap].data = data;
> }
>
> void do_handle_exception(struct pt_regs *regs)
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 03/12] powerpc: Abstract H_CEDE calls into a sleep functions
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-07-03 13:13 ` Thomas Huth
-1 siblings, 0 replies; 42+ messages in thread
From: Thomas Huth @ 2023-07-03 13:13 UTC (permalink / raw)
To: Nicholas Piggin, kvm; +Cc: linuxppc-dev, Laurent Vivier
On 08/06/2023 09.58, Nicholas Piggin wrote:
> This consolidates several implementations, and it no longer leaves
> MSR[EE] enabled after the decrementer interrupt is handled, but
> rather disables it on return.
>
> The handler no longer allows a continuous ticking, but rather dec
> has to be re-armed and EE re-enabled (e.g., via H_CEDE hcall) each
> time.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> lib/powerpc/asm/handlers.h | 2 +-
> lib/powerpc/asm/ppc_asm.h | 1 +
> lib/powerpc/asm/processor.h | 7 ++++++
> lib/powerpc/handlers.c | 10 ++++-----
> lib/powerpc/processor.c | 43 +++++++++++++++++++++++++++++++++++++
> powerpc/sprs.c | 6 +-----
> powerpc/tm.c | 20 +----------------
> 7 files changed, 58 insertions(+), 31 deletions(-)
>
> diff --git a/lib/powerpc/asm/handlers.h b/lib/powerpc/asm/handlers.h
> index 64ba727a..e4a0cd45 100644
> --- a/lib/powerpc/asm/handlers.h
> +++ b/lib/powerpc/asm/handlers.h
> @@ -3,6 +3,6 @@
>
> #include <asm/ptrace.h>
>
> -void dec_except_handler(struct pt_regs *regs, void *data);
> +void dec_handler_oneshot(struct pt_regs *regs, void *data);
>
> #endif /* _ASMPOWERPC_HANDLERS_H_ */
> diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h
> index 1b85f6bb..6299ff53 100644
> --- a/lib/powerpc/asm/ppc_asm.h
> +++ b/lib/powerpc/asm/ppc_asm.h
> @@ -36,6 +36,7 @@
> #endif /* __BYTE_ORDER__ */
>
> /* Machine State Register definitions: */
> +#define MSR_EE_BIT 15 /* External Interrupts Enable */
> #define MSR_SF_BIT 63 /* 64-bit mode */
>
> #endif /* _ASMPOWERPC_PPC_ASM_H */
> diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h
> index ac001e18..ebfeff2b 100644
> --- a/lib/powerpc/asm/processor.h
> +++ b/lib/powerpc/asm/processor.h
> @@ -20,6 +20,8 @@ static inline uint64_t get_tb(void)
>
> extern void delay(uint64_t cycles);
> extern void udelay(uint64_t us);
> +extern void sleep_tb(uint64_t cycles);
> +extern void usleep(uint64_t us);
>
> static inline void mdelay(uint64_t ms)
> {
> @@ -27,4 +29,9 @@ static inline void mdelay(uint64_t ms)
> udelay(1000);
> }
>
> +static inline void msleep(uint64_t ms)
> +{
> + usleep(ms * 1000);
> +}
> +
> #endif /* _ASMPOWERPC_PROCESSOR_H_ */
> diff --git a/lib/powerpc/handlers.c b/lib/powerpc/handlers.c
> index c8721e0a..296f14ff 100644
> --- a/lib/powerpc/handlers.c
> +++ b/lib/powerpc/handlers.c
> @@ -9,15 +9,13 @@
> #include <libcflat.h>
> #include <asm/handlers.h>
> #include <asm/ptrace.h>
> +#include <asm/ppc_asm.h>
>
> /*
> * Generic handler for decrementer exceptions (0x900)
> - * Just reset the decrementer back to the value specified when registering the
> - * handler
> + * Return with MSR[EE] disabled.
> */
> -void dec_except_handler(struct pt_regs *regs __unused, void *data)
> +void dec_handler_oneshot(struct pt_regs *regs, void *data)
> {
> - uint64_t dec = *((uint64_t *) data);
> -
> - asm volatile ("mtdec %0" : : "r" (dec));
> + regs->msr &= ~(1UL << MSR_EE_BIT);
> }
> diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
> index 0550e4fc..aaf45b68 100644
> --- a/lib/powerpc/processor.c
> +++ b/lib/powerpc/processor.c
> @@ -10,6 +10,8 @@
> #include <asm/ptrace.h>
> #include <asm/setup.h>
> #include <asm/barrier.h>
> +#include <asm/hcall.h>
> +#include <asm/handlers.h>
>
> static struct {
> void (*func)(struct pt_regs *, void *data);
> @@ -58,3 +60,44 @@ void udelay(uint64_t us)
> {
> delay((us * tb_hz) / 1000000);
> }
> +
> +void sleep_tb(uint64_t cycles)
> +{
> + uint64_t start, end, now;
> +
> + start = now = get_tb();
> + end = start + cycles;
> +
> + while (end > now) {
> + uint64_t left = end - now;
> +
> + /* TODO: Could support large decrementer */
> + if (left > 0x7fffffff)
> + left = 0x7fffffff;
> +
> + /* DEC won't fire until H_CEDE is called because EE=0 */
> + asm volatile ("mtdec %0" : : "r" (left));
> + handle_exception(0x900, &dec_handler_oneshot, NULL);
> + /*
> + * H_CEDE is called with MSR[EE] clear and enables it as part
> + * of the hcall, returning with EE enabled. The dec interrupt
> + * is then taken immediately and the handler disables EE.
> + *
> + * If H_CEDE returned for any other interrupt than dec
> + * expiring, that is considered an unhandled interrupt and
> + * the test case would be stopped.
> + */
> + if (hcall(H_CEDE) != H_SUCCESS) {
> + printf("H_CEDE failed\n");
> + abort();
> + }
> + handle_exception(0x900, NULL, NULL);
> +
> + now = get_tb();
> + }
> +}
> +
> +void usleep(uint64_t us)
> +{
> + sleep_tb((us * tb_hz) / 1000000);
> +}
> diff --git a/powerpc/sprs.c b/powerpc/sprs.c
> index 5cc1cd16..ba4ddee4 100644
> --- a/powerpc/sprs.c
> +++ b/powerpc/sprs.c
> @@ -254,7 +254,6 @@ int main(int argc, char **argv)
> 0x1234567890ABCDEFULL, 0xFEDCBA0987654321ULL,
> -1ULL,
> };
> - static uint64_t decr = 0x7FFFFFFF; /* Max value */
>
> for (i = 1; i < argc; i++) {
> if (!strcmp(argv[i], "-w")) {
> @@ -288,10 +287,7 @@ int main(int argc, char **argv)
> if (pause) {
> migrate_once();
> } else {
> - puts("Sleeping...\n");
> - handle_exception(0x900, &dec_except_handler, &decr);
> - asm volatile ("mtdec %0" : : "r" (0x3FFFFFFF));
> - hcall(H_CEDE);
> + msleep(2000);
> }
>
> get_sprs(after);
> diff --git a/powerpc/tm.c b/powerpc/tm.c
> index 65cacdf5..7fa91636 100644
> --- a/powerpc/tm.c
> +++ b/powerpc/tm.c
> @@ -48,17 +48,6 @@ static int count_cpus_with_tm(void)
> return available;
> }
>
> -static int h_cede(void)
> -{
> - register uint64_t r3 asm("r3") = H_CEDE;
> -
> - asm volatile ("sc 1" : "+r"(r3) :
> - : "r0", "r4", "r5", "r6", "r7", "r8", "r9",
> - "r10", "r11", "r12", "xer", "ctr", "cc");
> -
> - return r3;
> -}
> -
> /*
> * Enable transactional memory
> * Returns: FALSE - Failure
> @@ -95,14 +84,10 @@ static bool enable_tm(void)
> static void test_h_cede_tm(int argc, char **argv)
> {
> int i;
> - static uint64_t decr = 0x3FFFFF; /* ~10ms */
>
> if (argc > 2)
> report_abort("Unsupported argument: '%s'", argv[2]);
>
> - handle_exception(0x900, &dec_except_handler, &decr);
> - asm volatile ("mtdec %0" : : "r" (decr));
> -
> if (!start_all_cpus(halt, 0))
> report_abort("Failed to start secondary cpus");
>
> @@ -120,10 +105,7 @@ static void test_h_cede_tm(int argc, char **argv)
> "bf 2,1b" : : : "cr0");
>
> for (i = 0; i < 500; i++) {
> - uint64_t rval = h_cede();
> -
> - if (rval != H_SUCCESS)
> - break;
> + msleep(10);
> mdelay(5);
msleep() directly followed by an mdelay() looks weird now. Do we still need
the mdelay()? Or could we maybe at least get a comment here why there are
now two different delaying calls here?
Thomas
> }
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 03/12] powerpc: Abstract H_CEDE calls into a sleep functions
@ 2023-07-03 13:13 ` Thomas Huth
0 siblings, 0 replies; 42+ messages in thread
From: Thomas Huth @ 2023-07-03 13:13 UTC (permalink / raw)
To: Nicholas Piggin, kvm; +Cc: Laurent Vivier, linuxppc-dev
On 08/06/2023 09.58, Nicholas Piggin wrote:
> This consolidates several implementations, and it no longer leaves
> MSR[EE] enabled after the decrementer interrupt is handled, but
> rather disables it on return.
>
> The handler no longer allows a continuous ticking, but rather dec
> has to be re-armed and EE re-enabled (e.g., via H_CEDE hcall) each
> time.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> lib/powerpc/asm/handlers.h | 2 +-
> lib/powerpc/asm/ppc_asm.h | 1 +
> lib/powerpc/asm/processor.h | 7 ++++++
> lib/powerpc/handlers.c | 10 ++++-----
> lib/powerpc/processor.c | 43 +++++++++++++++++++++++++++++++++++++
> powerpc/sprs.c | 6 +-----
> powerpc/tm.c | 20 +----------------
> 7 files changed, 58 insertions(+), 31 deletions(-)
>
> diff --git a/lib/powerpc/asm/handlers.h b/lib/powerpc/asm/handlers.h
> index 64ba727a..e4a0cd45 100644
> --- a/lib/powerpc/asm/handlers.h
> +++ b/lib/powerpc/asm/handlers.h
> @@ -3,6 +3,6 @@
>
> #include <asm/ptrace.h>
>
> -void dec_except_handler(struct pt_regs *regs, void *data);
> +void dec_handler_oneshot(struct pt_regs *regs, void *data);
>
> #endif /* _ASMPOWERPC_HANDLERS_H_ */
> diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h
> index 1b85f6bb..6299ff53 100644
> --- a/lib/powerpc/asm/ppc_asm.h
> +++ b/lib/powerpc/asm/ppc_asm.h
> @@ -36,6 +36,7 @@
> #endif /* __BYTE_ORDER__ */
>
> /* Machine State Register definitions: */
> +#define MSR_EE_BIT 15 /* External Interrupts Enable */
> #define MSR_SF_BIT 63 /* 64-bit mode */
>
> #endif /* _ASMPOWERPC_PPC_ASM_H */
> diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h
> index ac001e18..ebfeff2b 100644
> --- a/lib/powerpc/asm/processor.h
> +++ b/lib/powerpc/asm/processor.h
> @@ -20,6 +20,8 @@ static inline uint64_t get_tb(void)
>
> extern void delay(uint64_t cycles);
> extern void udelay(uint64_t us);
> +extern void sleep_tb(uint64_t cycles);
> +extern void usleep(uint64_t us);
>
> static inline void mdelay(uint64_t ms)
> {
> @@ -27,4 +29,9 @@ static inline void mdelay(uint64_t ms)
> udelay(1000);
> }
>
> +static inline void msleep(uint64_t ms)
> +{
> + usleep(ms * 1000);
> +}
> +
> #endif /* _ASMPOWERPC_PROCESSOR_H_ */
> diff --git a/lib/powerpc/handlers.c b/lib/powerpc/handlers.c
> index c8721e0a..296f14ff 100644
> --- a/lib/powerpc/handlers.c
> +++ b/lib/powerpc/handlers.c
> @@ -9,15 +9,13 @@
> #include <libcflat.h>
> #include <asm/handlers.h>
> #include <asm/ptrace.h>
> +#include <asm/ppc_asm.h>
>
> /*
> * Generic handler for decrementer exceptions (0x900)
> - * Just reset the decrementer back to the value specified when registering the
> - * handler
> + * Return with MSR[EE] disabled.
> */
> -void dec_except_handler(struct pt_regs *regs __unused, void *data)
> +void dec_handler_oneshot(struct pt_regs *regs, void *data)
> {
> - uint64_t dec = *((uint64_t *) data);
> -
> - asm volatile ("mtdec %0" : : "r" (dec));
> + regs->msr &= ~(1UL << MSR_EE_BIT);
> }
> diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c
> index 0550e4fc..aaf45b68 100644
> --- a/lib/powerpc/processor.c
> +++ b/lib/powerpc/processor.c
> @@ -10,6 +10,8 @@
> #include <asm/ptrace.h>
> #include <asm/setup.h>
> #include <asm/barrier.h>
> +#include <asm/hcall.h>
> +#include <asm/handlers.h>
>
> static struct {
> void (*func)(struct pt_regs *, void *data);
> @@ -58,3 +60,44 @@ void udelay(uint64_t us)
> {
> delay((us * tb_hz) / 1000000);
> }
> +
> +void sleep_tb(uint64_t cycles)
> +{
> + uint64_t start, end, now;
> +
> + start = now = get_tb();
> + end = start + cycles;
> +
> + while (end > now) {
> + uint64_t left = end - now;
> +
> + /* TODO: Could support large decrementer */
> + if (left > 0x7fffffff)
> + left = 0x7fffffff;
> +
> + /* DEC won't fire until H_CEDE is called because EE=0 */
> + asm volatile ("mtdec %0" : : "r" (left));
> + handle_exception(0x900, &dec_handler_oneshot, NULL);
> + /*
> + * H_CEDE is called with MSR[EE] clear and enables it as part
> + * of the hcall, returning with EE enabled. The dec interrupt
> + * is then taken immediately and the handler disables EE.
> + *
> + * If H_CEDE returned for any other interrupt than dec
> + * expiring, that is considered an unhandled interrupt and
> + * the test case would be stopped.
> + */
> + if (hcall(H_CEDE) != H_SUCCESS) {
> + printf("H_CEDE failed\n");
> + abort();
> + }
> + handle_exception(0x900, NULL, NULL);
> +
> + now = get_tb();
> + }
> +}
> +
> +void usleep(uint64_t us)
> +{
> + sleep_tb((us * tb_hz) / 1000000);
> +}
> diff --git a/powerpc/sprs.c b/powerpc/sprs.c
> index 5cc1cd16..ba4ddee4 100644
> --- a/powerpc/sprs.c
> +++ b/powerpc/sprs.c
> @@ -254,7 +254,6 @@ int main(int argc, char **argv)
> 0x1234567890ABCDEFULL, 0xFEDCBA0987654321ULL,
> -1ULL,
> };
> - static uint64_t decr = 0x7FFFFFFF; /* Max value */
>
> for (i = 1; i < argc; i++) {
> if (!strcmp(argv[i], "-w")) {
> @@ -288,10 +287,7 @@ int main(int argc, char **argv)
> if (pause) {
> migrate_once();
> } else {
> - puts("Sleeping...\n");
> - handle_exception(0x900, &dec_except_handler, &decr);
> - asm volatile ("mtdec %0" : : "r" (0x3FFFFFFF));
> - hcall(H_CEDE);
> + msleep(2000);
> }
>
> get_sprs(after);
> diff --git a/powerpc/tm.c b/powerpc/tm.c
> index 65cacdf5..7fa91636 100644
> --- a/powerpc/tm.c
> +++ b/powerpc/tm.c
> @@ -48,17 +48,6 @@ static int count_cpus_with_tm(void)
> return available;
> }
>
> -static int h_cede(void)
> -{
> - register uint64_t r3 asm("r3") = H_CEDE;
> -
> - asm volatile ("sc 1" : "+r"(r3) :
> - : "r0", "r4", "r5", "r6", "r7", "r8", "r9",
> - "r10", "r11", "r12", "xer", "ctr", "cc");
> -
> - return r3;
> -}
> -
> /*
> * Enable transactional memory
> * Returns: FALSE - Failure
> @@ -95,14 +84,10 @@ static bool enable_tm(void)
> static void test_h_cede_tm(int argc, char **argv)
> {
> int i;
> - static uint64_t decr = 0x3FFFFF; /* ~10ms */
>
> if (argc > 2)
> report_abort("Unsupported argument: '%s'", argv[2]);
>
> - handle_exception(0x900, &dec_except_handler, &decr);
> - asm volatile ("mtdec %0" : : "r" (decr));
> -
> if (!start_all_cpus(halt, 0))
> report_abort("Failed to start secondary cpus");
>
> @@ -120,10 +105,7 @@ static void test_h_cede_tm(int argc, char **argv)
> "bf 2,1b" : : : "cr0");
>
> for (i = 0; i < 500; i++) {
> - uint64_t rval = h_cede();
> -
> - if (rval != H_SUCCESS)
> - break;
> + msleep(10);
> mdelay(5);
msleep() directly followed by an mdelay() looks weird now. Do we still need
the mdelay()? Or could we maybe at least get a comment here why there are
now two different delaying calls here?
Thomas
> }
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
2023-06-08 7:58 ` Nicholas Piggin
@ 2023-07-03 13:27 ` Thomas Huth
-1 siblings, 0 replies; 42+ messages in thread
From: Thomas Huth @ 2023-07-03 13:27 UTC (permalink / raw)
To: Nicholas Piggin, kvm; +Cc: linuxppc-dev, Laurent Vivier
On 08/06/2023 09.58, Nicholas Piggin wrote:
> Posting again, a couple of patches were merged and accounted for review
> comments from last time.
Sorry for not being very responsive ... it's been a busy month.
Anyway, I've now merged the first 5 patches and the VPA test since they look
fine to me.
As Joel already wrote, there is an issue with the sprs patch, I also get an
error with the PIR register on the P8 box that I have access to as soon as I
apply the "Specify SPRs with data rather than code" patch. It would be good
to get that problem resolved before merging the remaining patches...
Thomas
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
@ 2023-07-03 13:27 ` Thomas Huth
0 siblings, 0 replies; 42+ messages in thread
From: Thomas Huth @ 2023-07-03 13:27 UTC (permalink / raw)
To: Nicholas Piggin, kvm; +Cc: Laurent Vivier, linuxppc-dev
On 08/06/2023 09.58, Nicholas Piggin wrote:
> Posting again, a couple of patches were merged and accounted for review
> comments from last time.
Sorry for not being very responsive ... it's been a busy month.
Anyway, I've now merged the first 5 patches and the VPA test since they look
fine to me.
As Joel already wrote, there is an issue with the sprs patch, I also get an
error with the PIR register on the P8 box that I have access to as soon as I
apply the "Specify SPRs with data rather than code" patch. It would be good
to get that problem resolved before merging the remaining patches...
Thomas
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
2023-07-03 13:27 ` Thomas Huth
@ 2023-07-30 10:10 ` Nicholas Piggin
-1 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-07-30 10:10 UTC (permalink / raw)
To: Thomas Huth, kvm; +Cc: linuxppc-dev, Laurent Vivier
On Mon Jul 3, 2023 at 11:27 PM AEST, Thomas Huth wrote:
> On 08/06/2023 09.58, Nicholas Piggin wrote:
> > Posting again, a couple of patches were merged and accounted for review
> > comments from last time.
>
> Sorry for not being very responsive ... it's been a busy month.
Hah that's okay, I'll say the same thing. I was meaning to get
back to Joel and your comments but lots on all of a sudden, sigh.
> Anyway, I've now merged the first 5 patches and the VPA test since they look
> fine to me.
>
> As Joel already wrote, there is an issue with the sprs patch, I also get an
> error with the PIR register on the P8 box that I have access to as soon as I
> apply the "Specify SPRs with data rather than code" patch. It would be good
> to get that problem resolved before merging the remaining patches...
Thanks for this, yes needs a bit more polish. I'll try to get to
it now that qemu is mostly done for 8.1.
Thanks,
Nick
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support
@ 2023-07-30 10:10 ` Nicholas Piggin
0 siblings, 0 replies; 42+ messages in thread
From: Nicholas Piggin @ 2023-07-30 10:10 UTC (permalink / raw)
To: Thomas Huth, kvm; +Cc: Laurent Vivier, linuxppc-dev
On Mon Jul 3, 2023 at 11:27 PM AEST, Thomas Huth wrote:
> On 08/06/2023 09.58, Nicholas Piggin wrote:
> > Posting again, a couple of patches were merged and accounted for review
> > comments from last time.
>
> Sorry for not being very responsive ... it's been a busy month.
Hah that's okay, I'll say the same thing. I was meaning to get
back to Joel and your comments but lots on all of a sudden, sigh.
> Anyway, I've now merged the first 5 patches and the VPA test since they look
> fine to me.
>
> As Joel already wrote, there is an issue with the sprs patch, I also get an
> error with the PIR register on the P8 box that I have access to as soon as I
> apply the "Specify SPRs with data rather than code" patch. It would be good
> to get that problem resolved before merging the remaining patches...
Thanks for this, yes needs a bit more polish. I'll try to get to
it now that qemu is mostly done for 8.1.
Thanks,
Nick
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2023-07-30 10:11 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-08 7:58 [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-08 7:58 ` [kvm-unit-tests v4 01/12] powerpc: Report instruction address and MSR in unhandled exception error Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-21 14:53 ` Thomas Huth
2023-06-21 14:53 ` Thomas Huth
2023-06-08 7:58 ` [kvm-unit-tests v4 02/12] powerpc: Add some checking to exception handler install Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-21 14:54 ` Thomas Huth
2023-06-21 14:54 ` Thomas Huth
2023-06-08 7:58 ` [kvm-unit-tests v4 03/12] powerpc: Abstract H_CEDE calls into a sleep functions Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-07-03 13:13 ` Thomas Huth
2023-07-03 13:13 ` Thomas Huth
2023-06-08 7:58 ` [kvm-unit-tests v4 04/12] powerpc: Add ISA v3.1 (POWER10) support to SPR test Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-08 7:58 ` [kvm-unit-tests v4 05/12] powerpc: Extract some common helpers and defines to headers Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-08 7:58 ` [kvm-unit-tests v4 06/12] powerpc/sprs: Specify SPRs with data rather than code Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-08 7:58 ` [kvm-unit-tests v4 07/12] powerpc/spapr_vpa: Add basic VPA tests Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-08 7:58 ` [kvm-unit-tests v4 08/12] powerpc: Expand exception handler vector granularity Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-08 7:58 ` [kvm-unit-tests v4 09/12] powerpc: Add support for more interrupts including HV interrupts Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-08 7:58 ` [kvm-unit-tests v4 10/12] powerpc: Discover runtime load address dynamically Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-08 7:58 ` [kvm-unit-tests v4 11/12] powerpc: Support powernv machine with QEMU TCG Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-08 7:58 ` [kvm-unit-tests v4 12/12] powerpc/sprs: Test hypervisor registers on powernv machine Nicholas Piggin
2023-06-08 7:58 ` Nicholas Piggin
2023-06-14 1:09 ` [kvm-unit-tests v4 00/12] powerpc: updates, P10, PNV support Joel Stanley
2023-06-14 1:09 ` Joel Stanley
2023-06-15 3:02 ` Nicholas Piggin
2023-06-15 3:02 ` Nicholas Piggin
2023-06-15 8:11 ` Joel Stanley
2023-06-15 8:11 ` Joel Stanley
2023-07-03 13:27 ` Thomas Huth
2023-07-03 13:27 ` Thomas Huth
2023-07-30 10:10 ` Nicholas Piggin
2023-07-30 10:10 ` Nicholas Piggin
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