* [PATCH v2 0/6] target/riscv: Add support for BF16 extensions
@ 2023-06-15 6:32 Weiwei Li
2023-06-15 6:32 ` [PATCH v2 1/6] target/riscv: Add properties " Weiwei Li
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Weiwei Li @ 2023-06-15 6:32 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Specification for BF16 extensions can be found in:
https://github.com/riscv/riscv-bfloat16
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-bf16-upstream-v2
v2:
* Update dependancy check for BF16 extensions in patch 1 and patch 4
* Update encodings for BF16 instructions in patch 2,3,4
* Add disas support for BF16 instructions in patch 6
Weiwei Li (6):
target/riscv: Add properties for BF16 extensions
target/riscv: Add support for Zfbfmin extension
target/riscv: Add support for Zvfbfmin extension
target/riscv: Add support for Zvfbfwma extension
target/riscv: Expose properties for BF16 extensions
target/riscv: Add disas support for BF16 extensions
disas/riscv.c | 44 ++++++
target/riscv/cpu.c | 27 ++++
target/riscv/cpu_cfg.h | 3 +
target/riscv/fpu_helper.c | 12 ++
target/riscv/helper.h | 10 ++
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvbf16.c.inc | 175 +++++++++++++++++++++
target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +-
target/riscv/translate.c | 1 +
target/riscv/vector_helper.c | 17 ++
10 files changed, 307 insertions(+), 6 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvbf16.c.inc
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions
2023-06-15 6:32 [PATCH v2 0/6] target/riscv: Add support for BF16 extensions Weiwei Li
@ 2023-06-15 6:32 ` Weiwei Li
2023-06-15 12:58 ` Rob Bradford
2023-07-03 3:05 ` Alistair Francis
2023-06-15 6:32 ` [PATCH v2 2/6] target/riscv: Add support for Zfbfmin extension Weiwei Li
` (4 subsequent siblings)
5 siblings, 2 replies; 12+ messages in thread
From: Weiwei Li @ 2023-06-15 6:32 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
Add require check for BF16 extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 20 ++++++++++++++++++++
target/riscv/cpu_cfg.h | 3 +++
2 files changed, 23 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 881bddf393..dc6b2f72f6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1059,6 +1059,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
+ error_setg(errp, "Zfbfmin extension depends on F extension");
+ return;
+ }
+
if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
error_setg(errp, "D extension requires F extension");
return;
@@ -1109,6 +1114,21 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
+ error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
+ error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
+ error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
+ return;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_zhinx) {
cpu->cfg.ext_zhinxmin = true;
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index c4a627d335..7d16f32720 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -75,6 +75,7 @@ struct RISCVCPUConfig {
bool ext_svpbmt;
bool ext_zdinx;
bool ext_zawrs;
+ bool ext_zfbfmin;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zfinx;
@@ -84,6 +85,8 @@ struct RISCVCPUConfig {
bool ext_zve64f;
bool ext_zve64d;
bool ext_zmmul;
+ bool ext_zvfbfmin;
+ bool ext_zvfbfwma;
bool ext_zvfh;
bool ext_zvfhmin;
bool ext_smaia;
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 2/6] target/riscv: Add support for Zfbfmin extension
2023-06-15 6:32 [PATCH v2 0/6] target/riscv: Add support for BF16 extensions Weiwei Li
2023-06-15 6:32 ` [PATCH v2 1/6] target/riscv: Add properties " Weiwei Li
@ 2023-06-15 6:32 ` Weiwei Li
2023-06-15 6:32 ` [PATCH v2 3/6] target/riscv: Add support for Zvfbfmin extension Weiwei Li
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Weiwei Li @ 2023-06-15 6:32 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li, Richard Henderson
Add trans_* and helper function for Zfbfmin instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/fpu_helper.c | 12 +++++
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvbf16.c.inc | 53 ++++++++++++++++++++++
target/riscv/insn_trans/trans_rvzfh.c.inc | 12 ++---
target/riscv/translate.c | 1 +
6 files changed, 80 insertions(+), 6 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvbf16.c.inc
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 5dd14d8390..eb5ee5c4c9 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -593,3 +593,15 @@ uint64_t helper_fcvt_d_h(CPURISCVState *env, uint64_t rs1)
float16 frs1 = check_nanbox_h(env, rs1);
return float16_to_float64(frs1, true, &env->fp_status);
}
+
+uint64_t helper_fcvt_bf16_s(CPURISCVState *env, uint64_t rs1)
+{
+ float32 frs1 = check_nanbox_s(env, rs1);
+ return nanbox_h(env, float32_to_bfloat16(frs1, &env->fp_status));
+}
+
+uint64_t helper_fcvt_s_bf16(CPURISCVState *env, uint64_t rs1)
+{
+ float16 frs1 = check_nanbox_h(env, rs1);
+ return nanbox_s(env, bfloat16_to_float32(frs1, &env->fp_status));
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 98e97810fd..ef8487f1ee 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1153,3 +1153,7 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
/* Zce helper */
DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32)
+
+/* BF16 functions */
+DEF_HELPER_FLAGS_2(fcvt_bf16_s, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_s_bf16, TCG_CALL_NO_RWG, i64, env, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 73d5d1b045..45fdcad185 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -908,3 +908,7 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
# *** RV32 Zicond Standard Extension ***
czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r
czero_nez 0000111 ..... ..... 111 ..... 0110011 @r
+
+# *** Zfbfmin Standard Extension ***
+fcvt_bf16_s 0100010 01000 ..... ... ..... 1010011 @r2_rm
+fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
new file mode 100644
index 0000000000..8cafde505f
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -0,0 +1,53 @@
+/*
+ * RISC-V translation routines for the BF16 Standard Extensions.
+ *
+ * Copyright (c) 2020-2023 PLCT Lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZFBFMIN(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zfbfmin) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFBFMIN(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_bf16_s(dest, cpu_env, src1);
+ gen_set_fpr_hs(ctx, a->rd, dest);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fcvt_s_bf16 *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFBFMIN(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_bf16(dest, cpu_env, src1);
+ gen_set_fpr_hs(ctx, a->rd, dest);
+ mark_fs_dirty(ctx);
+ return true;
+}
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 74dde37ff7..8b1e2519bb 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -28,8 +28,8 @@
} \
} while (0)
-#define REQUIRE_ZFHMIN(ctx) do { \
- if (!ctx->cfg_ptr->ext_zfhmin) { \
+#define REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zfhmin && !ctx->cfg_ptr->ext_zfbfmin) { \
return false; \
} \
} while (0)
@@ -46,7 +46,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
TCGv t0;
REQUIRE_FPU;
- REQUIRE_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -69,7 +69,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
TCGv t0;
REQUIRE_FPU;
- REQUIRE_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -574,7 +574,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a)
static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
{
REQUIRE_FPU;
- REQUIRE_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
@@ -594,7 +594,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
{
REQUIRE_FPU;
- REQUIRE_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8a33da811e..0ce2b97ba5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1108,6 +1108,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
#include "insn_trans/trans_svinval.c.inc"
+#include "insn_trans/trans_rvbf16.c.inc"
#include "decode-xthead.c.inc"
#include "insn_trans/trans_xthead.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 3/6] target/riscv: Add support for Zvfbfmin extension
2023-06-15 6:32 [PATCH v2 0/6] target/riscv: Add support for BF16 extensions Weiwei Li
2023-06-15 6:32 ` [PATCH v2 1/6] target/riscv: Add properties " Weiwei Li
2023-06-15 6:32 ` [PATCH v2 2/6] target/riscv: Add support for Zfbfmin extension Weiwei Li
@ 2023-06-15 6:32 ` Weiwei Li
2023-06-15 6:33 ` [PATCH v2 4/6] target/riscv: Add support for Zvfbfwma extension Weiwei Li
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Weiwei Li @ 2023-06-15 6:32 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li, Richard Henderson
Add trans_* and helper function for Zvfbfmin instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 3 +
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvbf16.c.inc | 64 ++++++++++++++++++++++
target/riscv/vector_helper.c | 6 ++
4 files changed, 77 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ef8487f1ee..fc48853e07 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1157,3 +1157,6 @@ DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32)
/* BF16 functions */
DEF_HELPER_FLAGS_2(fcvt_bf16_s, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_s_bf16, TCG_CALL_NO_RWG, i64, env, i64)
+
+DEF_HELPER_5(vfncvtbf16_f_f_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 45fdcad185..10d001f14d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -912,3 +912,7 @@ czero_nez 0000111 ..... ..... 111 ..... 0110011 @r
# *** Zfbfmin Standard Extension ***
fcvt_bf16_s 0100010 01000 ..... ... ..... 1010011 @r2_rm
fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm
+
+# *** Zvfbfmin Standard Extension ***
+vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm
+vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
index 8cafde505f..f794a3f745 100644
--- a/target/riscv/insn_trans/trans_rvbf16.c.inc
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -22,6 +22,12 @@
} \
} while (0)
+#define REQUIRE_ZVFBFMIN(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zvfbfmin) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a)
{
REQUIRE_FPU;
@@ -51,3 +57,61 @@ static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fcvt_s_bf16 *a)
mark_fs_dirty(ctx);
return true;
}
+
+static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZVFBFMIN(ctx);
+
+ if (opfv_narrow_check(ctx, a) && (ctx->sew == MO_16)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+
+ gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
+ tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
+ vreg_ofs(ctx, a->rs2), cpu_env,
+ ctx->cfg_ptr->vlen / 8,
+ ctx->cfg_ptr->vlen / 8, data,
+ gen_helper_vfncvtbf16_f_f_w);
+ mark_vs_dirty(ctx);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZVFBFMIN(ctx);
+
+ if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+
+ gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
+ tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
+ vreg_ofs(ctx, a->rs2), cpu_env,
+ ctx->cfg_ptr->vlen / 8,
+ ctx->cfg_ptr->vlen / 8, data,
+ gen_helper_vfwcvtbf16_f_f_v);
+ mark_vs_dirty(ctx);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 1e06e7447c..4d2bd42155 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4535,6 +4535,9 @@ RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64)
GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 4)
GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 8)
+RVVCALL(OPFVV1, vfwcvtbf16_f_f_v, WOP_UU_H, H4, H2, bfloat16_to_float32)
+GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v, 4)
+
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
#define NOP_UU_B uint8_t, uint16_t, uint32_t
@@ -4581,6 +4584,9 @@ RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2)
GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
+RVVCALL(OPFVV1, vfncvtbf16_f_f_w, NOP_UU_H, H2, H4, float32_to_bfloat16)
+GEN_VEXT_V_ENV(vfncvtbf16_f_f_w, 2)
+
/*
* Vector Reduction Operations
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 4/6] target/riscv: Add support for Zvfbfwma extension
2023-06-15 6:32 [PATCH v2 0/6] target/riscv: Add support for BF16 extensions Weiwei Li
` (2 preceding siblings ...)
2023-06-15 6:32 ` [PATCH v2 3/6] target/riscv: Add support for Zvfbfmin extension Weiwei Li
@ 2023-06-15 6:33 ` Weiwei Li
2023-06-15 6:33 ` [PATCH v2 5/6] target/riscv: Expose properties for BF16 extensions Weiwei Li
2023-06-15 6:33 ` [PATCH v2 6/6] target/riscv: Add disas support " Weiwei Li
5 siblings, 0 replies; 12+ messages in thread
From: Weiwei Li @ 2023-06-15 6:33 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li, Richard Henderson
Add trans_* and helper function for Zvfbfwma instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvbf16.c.inc | 58 ++++++++++++++++++++++
target/riscv/vector_helper.c | 11 ++++
4 files changed, 76 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index fc48853e07..3170b8daa6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1160,3 +1160,6 @@ DEF_HELPER_FLAGS_2(fcvt_s_bf16, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_5(vfncvtbf16_f_f_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 10d001f14d..8c5d293f07 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -916,3 +916,7 @@ fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm
# *** Zvfbfmin Standard Extension ***
vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm
vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm
+
+# *** Zvfbfwma Standard Extension ***
+vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm
+vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
index f794a3f745..911bc29908 100644
--- a/target/riscv/insn_trans/trans_rvbf16.c.inc
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -28,6 +28,12 @@
} \
} while (0)
+#define REQUIRE_ZVFBFWMA(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zvfbfwma) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a)
{
REQUIRE_FPU;
@@ -115,3 +121,55 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
}
return false;
}
+
+static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZVFBFWMA(ctx);
+
+ if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
+ vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+
+ gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
+ tcg_gen_gvec_4_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
+ vreg_ofs(ctx, a->rs1),
+ vreg_ofs(ctx, a->rs2), cpu_env,
+ ctx->cfg_ptr->vlen / 8,
+ ctx->cfg_ptr->vlen / 8, data,
+ gen_helper_vfwmaccbf16_vv);
+ mark_vs_dirty(ctx);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+static bool trans_vfwmaccbf16_vf(DisasContext *ctx, arg_vfwmaccbf16_vf *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZVFBFWMA(ctx);
+
+ if (require_rvv(ctx) && (ctx->sew == MO_16) && vext_check_isa_ill(ctx) &&
+ vext_check_ds(ctx, a->rd, a->rs2, a->vm)) {
+ uint32_t data = 0;
+
+ gen_set_rm(ctx, RISCV_FRM_DYN);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
+ return opfvf_trans(a->rd, a->rs1, a->rs2, data,
+ gen_helper_vfwmaccbf16_vf, ctx);
+ }
+
+ return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 4d2bd42155..71bb9b4457 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3554,6 +3554,17 @@ RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32)
GEN_VEXT_VF(vfwmacc_vf_h, 4)
GEN_VEXT_VF(vfwmacc_vf_w, 8)
+static uint32_t fwmaccbf16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
+{
+ return float32_muladd(bfloat16_to_float32(a, s),
+ bfloat16_to_float32(b, s), d, 0, s);
+}
+
+RVVCALL(OPFVV3, vfwmaccbf16_vv, WOP_UUU_H, H4, H2, H2, fwmaccbf16)
+GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4)
+RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmacc16)
+GEN_VEXT_VF(vfwmaccbf16_vf, 4)
+
static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 5/6] target/riscv: Expose properties for BF16 extensions
2023-06-15 6:32 [PATCH v2 0/6] target/riscv: Add support for BF16 extensions Weiwei Li
` (3 preceding siblings ...)
2023-06-15 6:33 ` [PATCH v2 4/6] target/riscv: Add support for Zvfbfwma extension Weiwei Li
@ 2023-06-15 6:33 ` Weiwei Li
2023-06-15 6:33 ` [PATCH v2 6/6] target/riscv: Add disas support " Weiwei Li
5 siblings, 0 replies; 12+ messages in thread
From: Weiwei Li @ 2023-06-15 6:33 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dc6b2f72f6..feb0ee5e6f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -83,6 +83,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
+ ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx),
@@ -114,6 +115,8 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
+ ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
+ ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
@@ -1703,6 +1706,10 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
+ DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false),
+ DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
+ DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
+
DEFINE_PROP_END_OF_LIST(),
};
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 6/6] target/riscv: Add disas support for BF16 extensions
2023-06-15 6:32 [PATCH v2 0/6] target/riscv: Add support for BF16 extensions Weiwei Li
` (4 preceding siblings ...)
2023-06-15 6:33 ` [PATCH v2 5/6] target/riscv: Expose properties for BF16 extensions Weiwei Li
@ 2023-06-15 6:33 ` Weiwei Li
2023-07-03 3:08 ` Alistair Francis
5 siblings, 1 reply; 12+ messages in thread
From: Weiwei Li @ 2023-06-15 6:33 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
disas/riscv.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 5005364aba..44ea69315c 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -964,6 +964,16 @@ typedef enum {
rv_op_cm_jalt = 788,
rv_op_czero_eqz = 789,
rv_op_czero_nez = 790,
+ rv_op_fcvt_bf16_s = 791,
+ rv_op_fcvt_s_bf16 = 792,
+ rv_op_vfncvtbf16_f_f_w = 793,
+ rv_op_vfwcvtbf16_f_f_v = 794,
+ rv_op_vfwmaccbf16_vv = 795,
+ rv_op_vfwmaccbf16_vf = 796,
+ rv_op_flh = 797,
+ rv_op_fsh = 798,
+ rv_op_fmv_h_x = 799,
+ rv_op_fmv_x_h = 800,
} rv_op;
/* structures */
@@ -2168,6 +2178,16 @@ const rv_opcode_data opcode_data[] = {
{ "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
{ "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
+ { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
+ { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
+ { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -2643,6 +2663,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_vloxei8_v; break;
}
break;
+ case 1: op = rv_op_flh; break;
case 2: op = rv_op_flw; break;
case 3: op = rv_op_fld; break;
case 4: op = rv_op_flq; break;
@@ -2846,6 +2867,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_vsoxei8_v; break;
}
break;
+ case 1: op = rv_op_fsh; break;
case 2: op = rv_op_fsw; break;
case 3: op = rv_op_fsd; break;
case 4: op = rv_op_fsq; break;
@@ -3123,6 +3145,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
switch ((inst >> 20) & 0b11111) {
case 1: op = rv_op_fcvt_s_d; break;
case 3: op = rv_op_fcvt_s_q; break;
+ case 6: op = rv_op_fcvt_s_bf16; break;
}
break;
case 33:
@@ -3131,6 +3154,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_fcvt_d_q; break;
}
break;
+ case 34:
+ switch (((inst >> 20) & 0b11111)) {
+ case 8: op = rv_op_fcvt_bf16_s; break;
+ }
+ break;
case 35:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_q_s; break;
@@ -3235,6 +3263,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1: op = rv_op_fclass_d; break;
}
break;
+ case 114:
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
+ case 0: op = rv_op_fmv_x_h; break;
+ }
+ break;
case 115:
switch (((inst >> 17) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
@@ -3254,6 +3288,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0: op = rv_op_fmv_d_x; break;
}
break;
+ case 122:
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
+ case 0: op = rv_op_fmv_h_x; break;
+ }
+ break;
case 123:
switch (((inst >> 17) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
@@ -3350,6 +3390,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 10: op = rv_op_vfwcvt_f_xu_v; break;
case 11: op = rv_op_vfwcvt_f_x_v; break;
case 12: op = rv_op_vfwcvt_f_f_v; break;
+ case 13: op = rv_op_vfwcvtbf16_f_f_v; break;
case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
case 16: op = rv_op_vfncvt_xu_f_w; break;
@@ -3360,6 +3401,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 21: op = rv_op_vfncvt_rod_f_f_w; break;
case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
+ case 29: op = rv_op_vfncvtbf16_f_f_w; break;
}
break;
case 19:
@@ -3391,6 +3433,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 52: op = rv_op_vfwadd_wv; break;
case 54: op = rv_op_vfwsub_wv; break;
case 56: op = rv_op_vfwmul_vv; break;
+ case 59: op = rv_op_vfwmaccbf16_vv; break;
case 60: op = rv_op_vfwmacc_vv; break;
case 61: op = rv_op_vfwnmacc_vv; break;
case 62: op = rv_op_vfwmsac_vv; break;
@@ -3629,6 +3672,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 52: op = rv_op_vfwadd_wf; break;
case 54: op = rv_op_vfwsub_wf; break;
case 56: op = rv_op_vfwmul_vf; break;
+ case 59: op = rv_op_vfwmaccbf16_vf; break;
case 60: op = rv_op_vfwmacc_vf; break;
case 61: op = rv_op_vfwnmacc_vf; break;
case 62: op = rv_op_vfwmsac_vf; break;
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions
2023-06-15 6:32 ` [PATCH v2 1/6] target/riscv: Add properties " Weiwei Li
@ 2023-06-15 12:58 ` Rob Bradford
2023-06-15 13:14 ` Weiwei Li
2023-07-03 3:05 ` Alistair Francis
1 sibling, 1 reply; 12+ messages in thread
From: Rob Bradford @ 2023-06-15 12:58 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser
On Thu, 2023-06-15 at 14:32 +0800, Weiwei Li wrote:
> Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
> Add require check for BF16 extensions.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.c | 20 ++++++++++++++++++++
> target/riscv/cpu_cfg.h | 3 +++
> 2 files changed, 23 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 881bddf393..dc6b2f72f6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1059,6 +1059,11 @@ void
> riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
> + error_setg(errp, "Zfbfmin extension depends on F
> extension");
> + return;
> + }
> +
> if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
> error_setg(errp, "D extension requires F extension");
> return;
> @@ -1109,6 +1114,21 @@ void
> riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
> + error_setg(errp, "Zvfbfmin extension depends on Zfbfmin
> extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
> + error_setg(errp, "Zvfbfmin extension depends on Zve32f
> extension");
> + return;
> + }
I don't think this is correct - from the spec:
"This extension [Zvfbfmin] depends on the Zfbfmin extension and either
the "V" extension or the Zve32f embedded vector extension."
So this should be:
+ if (cpu->cfg.ext_zvfbfmin && !(cpu->cfg.ext_zve32f || cpu-
>cfg.ext_v) {
+ error_setg(errp, "Zvfbfmin extension depends on Zve32f or V
extension");
+ return;
+ }
Cheers,
Rob
> +
> + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
> + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin
> extension");
> + return;
> + }
> +
> /* Set the ISA extensions, checks should have happened above */
> if (cpu->cfg.ext_zhinx) {
> cpu->cfg.ext_zhinxmin = true;
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index c4a627d335..7d16f32720 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -75,6 +75,7 @@ struct RISCVCPUConfig {
> bool ext_svpbmt;
> bool ext_zdinx;
> bool ext_zawrs;
> + bool ext_zfbfmin;
> bool ext_zfh;
> bool ext_zfhmin;
> bool ext_zfinx;
> @@ -84,6 +85,8 @@ struct RISCVCPUConfig {
> bool ext_zve64f;
> bool ext_zve64d;
> bool ext_zmmul;
> + bool ext_zvfbfmin;
> + bool ext_zvfbfwma;
> bool ext_zvfh;
> bool ext_zvfhmin;
> bool ext_smaia;
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions
2023-06-15 12:58 ` Rob Bradford
@ 2023-06-15 13:14 ` Weiwei Li
2023-06-15 15:00 ` Rob Bradford
0 siblings, 1 reply; 12+ messages in thread
From: Weiwei Li @ 2023-06-15 13:14 UTC (permalink / raw)
To: Rob Bradford, qemu-riscv, qemu-devel
Cc: liweiwei, palmer, alistair.francis, bin.meng, dbarboza,
zhiwei_liu, wangjunqiang, lazyparser
On 2023/6/15 20:58, Rob Bradford wrote:
> On Thu, 2023-06-15 at 14:32 +0800, Weiwei Li wrote:
>> Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
>> Add require check for BF16 extensions.
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> target/riscv/cpu.c | 20 ++++++++++++++++++++
>> target/riscv/cpu_cfg.h | 3 +++
>> 2 files changed, 23 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 881bddf393..dc6b2f72f6 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -1059,6 +1059,11 @@ void
>> riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>> return;
>> }
>>
>> + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
>> + error_setg(errp, "Zfbfmin extension depends on F
>> extension");
>> + return;
>> + }
>> +
>> if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
>> error_setg(errp, "D extension requires F extension");
>> return;
>> @@ -1109,6 +1114,21 @@ void
>> riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>> return;
>> }
>>
>> + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
>> + error_setg(errp, "Zvfbfmin extension depends on Zfbfmin
>> extension");
>> + return;
>> + }
>> +
>> + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
>> + error_setg(errp, "Zvfbfmin extension depends on Zve32f
>> extension");
>> + return;
>> + }
> I don't think this is correct - from the spec:
>
> "This extension [Zvfbfmin] depends on the Zfbfmin extension and either
> the "V" extension or the Zve32f embedded vector extension."
>
> So this should be:
>
> + if (cpu->cfg.ext_zvfbfmin && !(cpu->cfg.ext_zve32f || cpu-
>> cfg.ext_v) {
> + error_setg(errp, "Zvfbfmin extension depends on Zve32f or V
> extension");
> + return;
> + }
Zve32f will be enabled when V is enabled. So we can simply check Zve32f
here.
Regards,
Weiwei Li
> Cheers,
>
> Rob
>
>> +
>> + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
>> + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin
>> extension");
>> + return;
>> + }
>> +
>> /* Set the ISA extensions, checks should have happened above */
>> if (cpu->cfg.ext_zhinx) {
>> cpu->cfg.ext_zhinxmin = true;
>> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
>> index c4a627d335..7d16f32720 100644
>> --- a/target/riscv/cpu_cfg.h
>> +++ b/target/riscv/cpu_cfg.h
>> @@ -75,6 +75,7 @@ struct RISCVCPUConfig {
>> bool ext_svpbmt;
>> bool ext_zdinx;
>> bool ext_zawrs;
>> + bool ext_zfbfmin;
>> bool ext_zfh;
>> bool ext_zfhmin;
>> bool ext_zfinx;
>> @@ -84,6 +85,8 @@ struct RISCVCPUConfig {
>> bool ext_zve64f;
>> bool ext_zve64d;
>> bool ext_zmmul;
>> + bool ext_zvfbfmin;
>> + bool ext_zvfbfwma;
>> bool ext_zvfh;
>> bool ext_zvfhmin;
>> bool ext_smaia;
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions
2023-06-15 13:14 ` Weiwei Li
@ 2023-06-15 15:00 ` Rob Bradford
0 siblings, 0 replies; 12+ messages in thread
From: Rob Bradford @ 2023-06-15 15:00 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser
On Thu, 2023-06-15 at 21:14 +0800, Weiwei Li wrote:
>
> On 2023/6/15 20:58, Rob Bradford wrote:
> > On Thu, 2023-06-15 at 14:32 +0800, Weiwei Li wrote:
> > > Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
> > > Add require check for BF16 extensions.
> > >
> > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> > > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> > > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> > > ---
> > > target/riscv/cpu.c | 20 ++++++++++++++++++++
> > > target/riscv/cpu_cfg.h | 3 +++
> > > 2 files changed, 23 insertions(+)
> > >
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index 881bddf393..dc6b2f72f6 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -1059,6 +1059,11 @@ void
> > > riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> > > return;
> > > }
> > >
> > > + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
> > > + error_setg(errp, "Zfbfmin extension depends on F
> > > extension");
> > > + return;
> > > + }
> > > +
> > > if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
> > > error_setg(errp, "D extension requires F extension");
> > > return;
> > > @@ -1109,6 +1114,21 @@ void
> > > riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> > > return;
> > > }
> > >
> > > + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
> > > + error_setg(errp, "Zvfbfmin extension depends on Zfbfmin
> > > extension");
> > > + return;
> > > + }
> > > +
> > > + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
> > > + error_setg(errp, "Zvfbfmin extension depends on Zve32f
> > > extension");
> > > + return;
> > > + }
> > I don't think this is correct - from the spec:
> >
> > "This extension [Zvfbfmin] depends on the Zfbfmin extension and
> > either
> > the "V" extension or the Zve32f embedded vector extension."
> >
> > So this should be:
> >
> > + if (cpu->cfg.ext_zvfbfmin && !(cpu->cfg.ext_zve32f || cpu-
> > > cfg.ext_v) {
> > + error_setg(errp, "Zvfbfmin extension depends on Zve32f or
> > V
> > extension");
> > + return;
> > + }
>
> Zve32f will be enabled when V is enabled. So we can simply check
> Zve32f
> here.
Great, thank you for the clarification - I missed that this this
enforced directly above.
Cheers,
Rob
>
> Regards,
>
> Weiwei Li
>
> > Cheers,
> >
> > Rob
> >
> > > +
> > > + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
> > > + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin
> > > extension");
> > > + return;
> > > + }
> > > +
> > > /* Set the ISA extensions, checks should have happened
> > > above */
> > > if (cpu->cfg.ext_zhinx) {
> > > cpu->cfg.ext_zhinxmin = true;
> > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> > > index c4a627d335..7d16f32720 100644
> > > --- a/target/riscv/cpu_cfg.h
> > > +++ b/target/riscv/cpu_cfg.h
> > > @@ -75,6 +75,7 @@ struct RISCVCPUConfig {
> > > bool ext_svpbmt;
> > > bool ext_zdinx;
> > > bool ext_zawrs;
> > > + bool ext_zfbfmin;
> > > bool ext_zfh;
> > > bool ext_zfhmin;
> > > bool ext_zfinx;
> > > @@ -84,6 +85,8 @@ struct RISCVCPUConfig {
> > > bool ext_zve64f;
> > > bool ext_zve64d;
> > > bool ext_zmmul;
> > > + bool ext_zvfbfmin;
> > > + bool ext_zvfbfwma;
> > > bool ext_zvfh;
> > > bool ext_zvfhmin;
> > > bool ext_smaia;
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions
2023-06-15 6:32 ` [PATCH v2 1/6] target/riscv: Add properties " Weiwei Li
2023-06-15 12:58 ` Rob Bradford
@ 2023-07-03 3:05 ` Alistair Francis
1 sibling, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2023-07-03 3:05 UTC (permalink / raw)
To: Weiwei Li
Cc: qemu-riscv, qemu-devel, palmer, alistair.francis, bin.meng,
dbarboza, zhiwei_liu, wangjunqiang, lazyparser
On Thu, Jun 15, 2023 at 4:34 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
> Add require check for BF16 extensions.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 20 ++++++++++++++++++++
> target/riscv/cpu_cfg.h | 3 +++
> 2 files changed, 23 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 881bddf393..dc6b2f72f6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1059,6 +1059,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
> + error_setg(errp, "Zfbfmin extension depends on F extension");
> + return;
> + }
> +
> if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
> error_setg(errp, "D extension requires F extension");
> return;
> @@ -1109,6 +1114,21 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
> + error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
> + error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
> + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
> + return;
> + }
> +
> /* Set the ISA extensions, checks should have happened above */
> if (cpu->cfg.ext_zhinx) {
> cpu->cfg.ext_zhinxmin = true;
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index c4a627d335..7d16f32720 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -75,6 +75,7 @@ struct RISCVCPUConfig {
> bool ext_svpbmt;
> bool ext_zdinx;
> bool ext_zawrs;
> + bool ext_zfbfmin;
> bool ext_zfh;
> bool ext_zfhmin;
> bool ext_zfinx;
> @@ -84,6 +85,8 @@ struct RISCVCPUConfig {
> bool ext_zve64f;
> bool ext_zve64d;
> bool ext_zmmul;
> + bool ext_zvfbfmin;
> + bool ext_zvfbfwma;
> bool ext_zvfh;
> bool ext_zvfhmin;
> bool ext_smaia;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 6/6] target/riscv: Add disas support for BF16 extensions
2023-06-15 6:33 ` [PATCH v2 6/6] target/riscv: Add disas support " Weiwei Li
@ 2023-07-03 3:08 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2023-07-03 3:08 UTC (permalink / raw)
To: Weiwei Li
Cc: qemu-riscv, qemu-devel, palmer, alistair.francis, bin.meng,
dbarboza, zhiwei_liu, wangjunqiang, lazyparser
On Thu, Jun 15, 2023 at 4:36 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
I have applied the first 5 patches, do you mind rebasing this patch
and resending it?
Alistair
> ---
> disas/riscv.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 5005364aba..44ea69315c 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -964,6 +964,16 @@ typedef enum {
> rv_op_cm_jalt = 788,
> rv_op_czero_eqz = 789,
> rv_op_czero_nez = 790,
> + rv_op_fcvt_bf16_s = 791,
> + rv_op_fcvt_s_bf16 = 792,
> + rv_op_vfncvtbf16_f_f_w = 793,
> + rv_op_vfwcvtbf16_f_f_v = 794,
> + rv_op_vfwmaccbf16_vv = 795,
> + rv_op_vfwmaccbf16_vf = 796,
> + rv_op_flh = 797,
> + rv_op_fsh = 798,
> + rv_op_fmv_h_x = 799,
> + rv_op_fmv_x_h = 800,
> } rv_op;
>
> /* structures */
> @@ -2168,6 +2178,16 @@ const rv_opcode_data opcode_data[] = {
> { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
> { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> + { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> + { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> + { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> + { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> + { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
> + { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
> + { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
> + { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
> + { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
> + { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> };
>
> /* CSR names */
> @@ -2643,6 +2663,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 3: op = rv_op_vloxei8_v; break;
> }
> break;
> + case 1: op = rv_op_flh; break;
> case 2: op = rv_op_flw; break;
> case 3: op = rv_op_fld; break;
> case 4: op = rv_op_flq; break;
> @@ -2846,6 +2867,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 3: op = rv_op_vsoxei8_v; break;
> }
> break;
> + case 1: op = rv_op_fsh; break;
> case 2: op = rv_op_fsw; break;
> case 3: op = rv_op_fsd; break;
> case 4: op = rv_op_fsq; break;
> @@ -3123,6 +3145,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> switch ((inst >> 20) & 0b11111) {
> case 1: op = rv_op_fcvt_s_d; break;
> case 3: op = rv_op_fcvt_s_q; break;
> + case 6: op = rv_op_fcvt_s_bf16; break;
> }
> break;
> case 33:
> @@ -3131,6 +3154,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 3: op = rv_op_fcvt_d_q; break;
> }
> break;
> + case 34:
> + switch (((inst >> 20) & 0b11111)) {
> + case 8: op = rv_op_fcvt_bf16_s; break;
> + }
> + break;
> case 35:
> switch ((inst >> 20) & 0b11111) {
> case 0: op = rv_op_fcvt_q_s; break;
> @@ -3235,6 +3263,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 1: op = rv_op_fclass_d; break;
> }
> break;
> + case 114:
> + switch (((inst >> 17) & 0b11111000) |
> + ((inst >> 12) & 0b00000111)) {
> + case 0: op = rv_op_fmv_x_h; break;
> + }
> + break;
> case 115:
> switch (((inst >> 17) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> @@ -3254,6 +3288,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 0: op = rv_op_fmv_d_x; break;
> }
> break;
> + case 122:
> + switch (((inst >> 17) & 0b11111000) |
> + ((inst >> 12) & 0b00000111)) {
> + case 0: op = rv_op_fmv_h_x; break;
> + }
> + break;
> case 123:
> switch (((inst >> 17) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> @@ -3350,6 +3390,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 10: op = rv_op_vfwcvt_f_xu_v; break;
> case 11: op = rv_op_vfwcvt_f_x_v; break;
> case 12: op = rv_op_vfwcvt_f_f_v; break;
> + case 13: op = rv_op_vfwcvtbf16_f_f_v; break;
> case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
> case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
> case 16: op = rv_op_vfncvt_xu_f_w; break;
> @@ -3360,6 +3401,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 21: op = rv_op_vfncvt_rod_f_f_w; break;
> case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
> case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
> + case 29: op = rv_op_vfncvtbf16_f_f_w; break;
> }
> break;
> case 19:
> @@ -3391,6 +3433,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 52: op = rv_op_vfwadd_wv; break;
> case 54: op = rv_op_vfwsub_wv; break;
> case 56: op = rv_op_vfwmul_vv; break;
> + case 59: op = rv_op_vfwmaccbf16_vv; break;
> case 60: op = rv_op_vfwmacc_vv; break;
> case 61: op = rv_op_vfwnmacc_vv; break;
> case 62: op = rv_op_vfwmsac_vv; break;
> @@ -3629,6 +3672,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 52: op = rv_op_vfwadd_wf; break;
> case 54: op = rv_op_vfwsub_wf; break;
> case 56: op = rv_op_vfwmul_vf; break;
> + case 59: op = rv_op_vfwmaccbf16_vf; break;
> case 60: op = rv_op_vfwmacc_vf; break;
> case 61: op = rv_op_vfwnmacc_vf; break;
> case 62: op = rv_op_vfwmsac_vf; break;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-07-03 3:10 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-15 6:32 [PATCH v2 0/6] target/riscv: Add support for BF16 extensions Weiwei Li
2023-06-15 6:32 ` [PATCH v2 1/6] target/riscv: Add properties " Weiwei Li
2023-06-15 12:58 ` Rob Bradford
2023-06-15 13:14 ` Weiwei Li
2023-06-15 15:00 ` Rob Bradford
2023-07-03 3:05 ` Alistair Francis
2023-06-15 6:32 ` [PATCH v2 2/6] target/riscv: Add support for Zfbfmin extension Weiwei Li
2023-06-15 6:32 ` [PATCH v2 3/6] target/riscv: Add support for Zvfbfmin extension Weiwei Li
2023-06-15 6:33 ` [PATCH v2 4/6] target/riscv: Add support for Zvfbfwma extension Weiwei Li
2023-06-15 6:33 ` [PATCH v2 5/6] target/riscv: Expose properties for BF16 extensions Weiwei Li
2023-06-15 6:33 ` [PATCH v2 6/6] target/riscv: Add disas support " Weiwei Li
2023-07-03 3:08 ` Alistair Francis
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