* [PATCH V3 0/6] Update GCC clocks for QDU1000 and QRU1000 SoCs
@ 2023-07-06 10:50 Imran Shaik
2023-07-06 10:50 ` [PATCH V3 1/6] dt-bindings: clock: " Imran Shaik
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Imran Shaik @ 2023-07-06 10:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Imran Shaik, Melody Olvera,
Dmitry Baryshkov, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Jagadeesh Kona, Satya Priya Kakitapalli,
Ajit Pandey
Update GCC clocks and add support for GDSCs for QDU1000 and QRU1000 SoCs.
Changes since v2:
- Split the gcc clkref clock changes as per the review comments
Changes since v1:
- Dropped the v2 variant compatible changes
- Update tha maintainers list
- Split the GCC driver patch as per the review comments
Previous series:
v2 - https://patchwork.kernel.org/project/linux-arm-msm/list/?series=760862
v1 - https://patchwork.kernel.org/project/linux-arm-msm/list/?series=757828
Imran Shaik (6):
dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling
clk: qcom: gcc-qdu1000: Fix clkref clocks handling
clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version
clk: qcom: gcc-qdu1000: Add support for GDSCs
clk: qcom: gcc-qdu1000: Update the RCGs ops
.../bindings/clock/qcom,qdu1000-gcc.yaml | 3 +-
drivers/clk/qcom/gcc-qdu1000.c | 159 ++++++++++++------
include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +-
3 files changed, 110 insertions(+), 56 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V3 1/6] dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
2023-07-06 10:50 [PATCH V3 0/6] Update GCC clocks for QDU1000 and QRU1000 SoCs Imran Shaik
@ 2023-07-06 10:50 ` Imran Shaik
2023-07-06 10:50 ` [PATCH V3 2/6] clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling Imran Shaik
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Imran Shaik @ 2023-07-06 10:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Imran Shaik, Melody Olvera,
Dmitry Baryshkov, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Jagadeesh Kona, Satya Priya Kakitapalli,
Ajit Pandey, Rob Herring
Update the qcom GCC clock bindings for QDU1000 and QRU1000 SoCs.
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes since v2:
- None
Changes since v1:
- Removed the v2 variant compatible string changes
- Updated the maintainers list
Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 3 ++-
include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
index 767a9d03aa32..d712b1a87e25 100644
--- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
maintainers:
- - Melody Olvera <quic_molvera@quicinc.com>
+ - Taniya Das <quic_tdas@quicinc.com>
+ - Imran Shaik <quic_imrashai@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h
index ddbc6b825e80..2fd36cbfddbb 100644
--- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h
+++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
@@ -138,6 +138,8 @@
#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128
#define GCC_PCIE_0_PIPE_CLK_SRC 129
#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130
+#define GCC_GPLL1_OUT_EVEN 131
+#define GCC_DDRSS_ECPRI_GSI_CLK 132
/* GCC resets */
#define GCC_ECPRI_CC_BCR 0
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V3 2/6] clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling
2023-07-06 10:50 [PATCH V3 0/6] Update GCC clocks for QDU1000 and QRU1000 SoCs Imran Shaik
2023-07-06 10:50 ` [PATCH V3 1/6] dt-bindings: clock: " Imran Shaik
@ 2023-07-06 10:50 ` Imran Shaik
2023-07-06 10:50 ` [PATCH V3 3/6] clk: qcom: gcc-qdu1000: Fix clkref clocks handling Imran Shaik
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Imran Shaik @ 2023-07-06 10:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Imran Shaik, Melody Olvera,
Dmitry Baryshkov, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Jagadeesh Kona, Satya Priya Kakitapalli,
Ajit Pandey
Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops
implementation to let the clock framework automatically park the clock
at XO when the clock is switched off and restore the parent when the
clock is switched on.
Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Changes since v2:
- Updated the commit text
Changes since v1:
- Newly added
drivers/clk/qcom/gcc-qdu1000.c | 23 ++++++-----------------
1 file changed, 6 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 5051769ad90c..c00d26a3e6df 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -370,16 +370,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_TCXO_IDX },
};
-static const struct parent_map gcc_parent_map_7[] = {
- { P_PCIE_0_PIPE_CLK, 0 },
- { P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_7[] = {
- { .index = DT_PCIE_0_PIPE_CLK_IDX },
- { .index = DT_TCXO_IDX },
-};
-
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@@ -439,16 +429,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
},
};
-static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
+static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x9d064,
- .shift = 0,
- .width = 2,
- .parent_map = gcc_parent_map_7,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk_src",
- .parent_data = gcc_parent_data_7,
- .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_0_PIPE_CLK_IDX,
+ },
+ .num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V3 3/6] clk: qcom: gcc-qdu1000: Fix clkref clocks handling
2023-07-06 10:50 [PATCH V3 0/6] Update GCC clocks for QDU1000 and QRU1000 SoCs Imran Shaik
2023-07-06 10:50 ` [PATCH V3 1/6] dt-bindings: clock: " Imran Shaik
2023-07-06 10:50 ` [PATCH V3 2/6] clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling Imran Shaik
@ 2023-07-06 10:50 ` Imran Shaik
2023-07-06 10:50 ` [PATCH V3 4/6] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version Imran Shaik
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Imran Shaik @ 2023-07-06 10:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Imran Shaik, Melody Olvera,
Dmitry Baryshkov, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Jagadeesh Kona, Satya Priya Kakitapalli,
Ajit Pandey
Fix the gcc clkref clock ops and update the halt_check as per the
latest hw version of QDU1000 and QRU1000 SoCs.
Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
Changes since v2:
- Split the patch as per the review comments
- Newly added
drivers/clk/qcom/gcc-qdu1000.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index c00d26a3e6df..8df7b7983968 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -1447,14 +1447,13 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
static struct clk_branch gcc_pcie_0_clkref_en = {
.halt_reg = 0x9c004,
- .halt_bit = 31,
- .halt_check = BRANCH_HALT_ENABLE,
+ .halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_clkref_en",
- .ops = &clk_branch_ops,
+ .ops = &clk_branch2_ops,
},
},
};
@@ -2274,14 +2273,13 @@ static struct clk_branch gcc_tsc_etu_clk = {
static struct clk_branch gcc_usb2_clkref_en = {
.halt_reg = 0x9c008,
- .halt_bit = 31,
- .halt_check = BRANCH_HALT_ENABLE,
+ .halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb2_clkref_en",
- .ops = &clk_branch_ops,
+ .ops = &clk_branch2_ops,
},
},
};
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V3 4/6] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version
2023-07-06 10:50 [PATCH V3 0/6] Update GCC clocks for QDU1000 and QRU1000 SoCs Imran Shaik
` (2 preceding siblings ...)
2023-07-06 10:50 ` [PATCH V3 3/6] clk: qcom: gcc-qdu1000: Fix clkref clocks handling Imran Shaik
@ 2023-07-06 10:50 ` Imran Shaik
2023-07-15 13:20 ` Konrad Dybcio
2023-07-06 10:50 ` [PATCH V3 5/6] clk: qcom: gcc-qdu1000: Add support for GDSCs Imran Shaik
2023-07-06 10:50 ` [PATCH V3 6/6] clk: qcom: gcc-qdu1000: Update the RCGs ops Imran Shaik
5 siblings, 1 reply; 11+ messages in thread
From: Imran Shaik @ 2023-07-06 10:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Imran Shaik, Melody Olvera,
Dmitry Baryshkov, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Jagadeesh Kona, Satya Priya Kakitapalli,
Ajit Pandey
Update the GCC clocks as per the latest hw version of QDU1000 and
QRU100 SoCs.
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
Changes since v2:
- Split the patch as per the review comments
- Newly added
drivers/clk/qcom/gcc-qdu1000.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 8df7b7983968..991fb2bc97e9 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = {
},
};
+static struct clk_branch gcc_ddrss_ecpri_gsi_clk = {
+ .halt_reg = 0x54298,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x54298,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x54298,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ddrss_ecpri_gsi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_ecpri_ahb_clk = {
.halt_reg = 0x3a008,
.halt_check = BRANCH_HALT_VOTED,
@@ -2521,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = {
[GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr,
[GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
+ [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
+ [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,
};
static const struct qcom_reset_map gcc_qdu1000_resets[] = {
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V3 5/6] clk: qcom: gcc-qdu1000: Add support for GDSCs
2023-07-06 10:50 [PATCH V3 0/6] Update GCC clocks for QDU1000 and QRU1000 SoCs Imran Shaik
` (3 preceding siblings ...)
2023-07-06 10:50 ` [PATCH V3 4/6] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version Imran Shaik
@ 2023-07-06 10:50 ` Imran Shaik
2023-07-06 10:50 ` [PATCH V3 6/6] clk: qcom: gcc-qdu1000: Update the RCGs ops Imran Shaik
5 siblings, 0 replies; 11+ messages in thread
From: Imran Shaik @ 2023-07-06 10:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Imran Shaik, Melody Olvera,
Dmitry Baryshkov, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Jagadeesh Kona, Satya Priya Kakitapalli,
Ajit Pandey
Add the GDSCs support for QDU1000 and QRU1000 SoCs.
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Changes since v2:
- None
Changes since v1:
- Newly added
drivers/clk/qcom/gcc-qdu1000.c | 42 ++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 991fb2bc97e9..718c34dca6e8 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -17,6 +17,7 @@
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
+#include "gdsc.h"
#include "reset.h"
enum {
@@ -2409,6 +2410,39 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
},
};
+static struct gdsc pcie_0_gdsc = {
+ .gdscr = 0x9d004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "gcc_pcie_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie_0_phy_gdsc = {
+ .gdscr = 0x7c004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .pd = {
+ .name = "gcc_pcie_0_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb30_prim_gdsc = {
+ .gdscr = 0x49004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "gcc_usb30_prim_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *gcc_qdu1000_clocks[] = {
[GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr,
[GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr,
@@ -2545,6 +2579,12 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = {
[GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,
};
+static struct gdsc *gcc_qdu1000_gdscs[] = {
+ [PCIE_0_GDSC] = &pcie_0_gdsc,
+ [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,
+ [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
+};
+
static const struct qcom_reset_map gcc_qdu1000_resets[] = {
[GCC_ECPRI_CC_BCR] = { 0x3e000 },
[GCC_ECPRI_SS_BCR] = { 0x3a000 },
@@ -2606,6 +2646,8 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = {
.num_clks = ARRAY_SIZE(gcc_qdu1000_clocks),
.resets = gcc_qdu1000_resets,
.num_resets = ARRAY_SIZE(gcc_qdu1000_resets),
+ .gdscs = gcc_qdu1000_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs),
};
static const struct of_device_id gcc_qdu1000_match_table[] = {
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V3 6/6] clk: qcom: gcc-qdu1000: Update the RCGs ops
2023-07-06 10:50 [PATCH V3 0/6] Update GCC clocks for QDU1000 and QRU1000 SoCs Imran Shaik
` (4 preceding siblings ...)
2023-07-06 10:50 ` [PATCH V3 5/6] clk: qcom: gcc-qdu1000: Add support for GDSCs Imran Shaik
@ 2023-07-06 10:50 ` Imran Shaik
2023-07-06 14:16 ` Dmitry Baryshkov
5 siblings, 1 reply; 11+ messages in thread
From: Imran Shaik @ 2023-07-06 10:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Imran Shaik, Melody Olvera,
Dmitry Baryshkov, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Jagadeesh Kona, Satya Priya Kakitapalli,
Ajit Pandey
Update the SDCC clock RCG ops to floor_ops to avoid overclocking issues
and remaining RCGs to shared_ops to park them at safe clock(XO) during
disable.
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Changes since v2:
- None
Changes since v1:
- Newly added
drivers/clk/qcom/gcc-qdu1000.c | 62 +++++++++++++++++-----------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 718c34dca6e8..de35cdc93732 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -475,7 +475,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = {
.name = "gcc_aggre_noc_ecpri_dma_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -495,7 +495,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = {
.name = "gcc_aggre_noc_ecpri_gsi_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -514,7 +514,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -528,7 +528,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -542,7 +542,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -561,7 +561,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -600,7 +600,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -622,7 +622,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
@@ -638,7 +638,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -654,7 +654,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -670,7 +670,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -686,7 +686,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -707,7 +707,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -723,7 +723,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -739,7 +739,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -755,7 +755,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -771,7 +771,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -787,7 +787,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -803,7 +803,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -819,7 +819,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -851,7 +851,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@@ -867,7 +867,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src = {
.name = "gcc_sdcc5_apps_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -922,7 +922,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = {
.name = "gcc_sdcc5_ice_core_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -936,7 +936,7 @@ static struct clk_rcg2 gcc_sm_bus_xo_clk_src = {
.name = "gcc_sm_bus_xo_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -955,7 +955,7 @@ static struct clk_rcg2 gcc_tsc_clk_src = {
.name = "gcc_tsc_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -975,7 +975,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -989,7 +989,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -1003,7 +1003,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V3 6/6] clk: qcom: gcc-qdu1000: Update the RCGs ops
2023-07-06 10:50 ` [PATCH V3 6/6] clk: qcom: gcc-qdu1000: Update the RCGs ops Imran Shaik
@ 2023-07-06 14:16 ` Dmitry Baryshkov
2023-07-14 5:19 ` Imran Shaik
0 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2023-07-06 14:16 UTC (permalink / raw)
To: Imran Shaik, Andy Gross, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Melody Olvera, linux-arm-msm,
linux-clk, devicetree, linux-kernel, Jagadeesh Kona,
Satya Priya Kakitapalli, Ajit Pandey
On 06/07/2023 13:50, Imran Shaik wrote:
> Update the SDCC clock RCG ops to floor_ops to avoid overclocking issues
Split, please.
> and remaining RCGs to shared_ops to park them at safe clock(XO) during
> disable.
Why are you doing this, is there any issue? Previously we had only a
several clocks implemented this way, which were really shared with other
subsystems (this is the where name _shared_ops comes from).
>
> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> Changes since v2:
> - None
> Changes since v1:
> - Newly added
>
> drivers/clk/qcom/gcc-qdu1000.c | 62 +++++++++++++++++-----------------
> 1 file changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
> index 718c34dca6e8..de35cdc93732 100644
> --- a/drivers/clk/qcom/gcc-qdu1000.c
> +++ b/drivers/clk/qcom/gcc-qdu1000.c
> @@ -475,7 +475,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = {
> .name = "gcc_aggre_noc_ecpri_dma_clk_src",
> .parent_data = gcc_parent_data_4,
> .num_parents = ARRAY_SIZE(gcc_parent_data_4),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -495,7 +495,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = {
> .name = "gcc_aggre_noc_ecpri_gsi_clk_src",
> .parent_data = gcc_parent_data_5,
> .num_parents = ARRAY_SIZE(gcc_parent_data_5),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -514,7 +514,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
> .name = "gcc_gp1_clk_src",
> .parent_data = gcc_parent_data_1,
> .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -528,7 +528,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
> .name = "gcc_gp2_clk_src",
> .parent_data = gcc_parent_data_1,
> .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -542,7 +542,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
> .name = "gcc_gp3_clk_src",
> .parent_data = gcc_parent_data_1,
> .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -561,7 +561,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
> .name = "gcc_pcie_0_aux_clk_src",
> .parent_data = gcc_parent_data_3,
> .num_parents = ARRAY_SIZE(gcc_parent_data_3),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
> .name = "gcc_pcie_0_phy_rchng_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -600,7 +600,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
> .name = "gcc_pdm2_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -622,7 +622,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s0_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
> @@ -638,7 +638,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s1_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
> @@ -654,7 +654,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s2_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
> @@ -670,7 +670,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s3_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
> @@ -686,7 +686,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s4_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
> @@ -707,7 +707,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s5_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
> @@ -723,7 +723,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s6_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
> @@ -739,7 +739,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s7_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
> @@ -755,7 +755,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
> .name = "gcc_qupv3_wrap1_s0_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
> @@ -771,7 +771,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
> .name = "gcc_qupv3_wrap1_s1_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
> @@ -787,7 +787,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
> .name = "gcc_qupv3_wrap1_s2_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
> @@ -803,7 +803,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
> .name = "gcc_qupv3_wrap1_s3_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
> @@ -819,7 +819,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
> .name = "gcc_qupv3_wrap1_s4_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
> @@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
> .name = "gcc_qupv3_wrap1_s5_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
> @@ -851,7 +851,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
> .name = "gcc_qupv3_wrap1_s6_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
> @@ -867,7 +867,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
> .name = "gcc_qupv3_wrap1_s7_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
> @@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src = {
> .name = "gcc_sdcc5_apps_clk_src",
> .parent_data = gcc_parent_data_8,
> .num_parents = ARRAY_SIZE(gcc_parent_data_8),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_floor_ops,
> },
> };
>
> @@ -922,7 +922,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = {
> .name = "gcc_sdcc5_ice_core_clk_src",
> .parent_data = gcc_parent_data_2,
> .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_floor_ops,
> },
> };
>
> @@ -936,7 +936,7 @@ static struct clk_rcg2 gcc_sm_bus_xo_clk_src = {
> .name = "gcc_sm_bus_xo_clk_src",
> .parent_data = gcc_parent_data_2,
> .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -955,7 +955,7 @@ static struct clk_rcg2 gcc_tsc_clk_src = {
> .name = "gcc_tsc_clk_src",
> .parent_data = gcc_parent_data_9,
> .num_parents = ARRAY_SIZE(gcc_parent_data_9),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -975,7 +975,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
> .name = "gcc_usb30_prim_master_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -989,7 +989,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
> .name = "gcc_usb30_prim_mock_utmi_clk_src",
> .parent_data = gcc_parent_data_0,
> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -1003,7 +1003,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
> .name = "gcc_usb3_prim_phy_aux_clk_src",
> .parent_data = gcc_parent_data_3,
> .num_parents = ARRAY_SIZE(gcc_parent_data_3),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V3 6/6] clk: qcom: gcc-qdu1000: Update the RCGs ops
2023-07-06 14:16 ` Dmitry Baryshkov
@ 2023-07-14 5:19 ` Imran Shaik
0 siblings, 0 replies; 11+ messages in thread
From: Imran Shaik @ 2023-07-14 5:19 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Melody Olvera, linux-arm-msm,
linux-clk, devicetree, linux-kernel, Jagadeesh Kona,
Satya Priya Kakitapalli, Ajit Pandey
On 7/6/2023 7:46 PM, Dmitry Baryshkov wrote:
> On 06/07/2023 13:50, Imran Shaik wrote:
>> Update the SDCC clock RCG ops to floor_ops to avoid overclocking issues
>
> Split, please.
>
Sure, will split this patch in next series.
>> and remaining RCGs to shared_ops to park them at safe clock(XO) during
>> disable.
>
> Why are you doing this, is there any issue? Previously we had only a
> several clocks implemented this way, which were really shared with other
> subsystems (this is the where name _shared_ops comes from).
>
From our clock hardware side, the expectation is to park the RCGs at XO
for most of the clocks and the shared_ops is the closest implementation
for the same. Hence updating the RCG ops to clk_rcg2_shared_ops.
Thanks,
Imran
>>
>> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> Changes since v2:
>> - None
>> Changes since v1:
>> - Newly added
>>
>> drivers/clk/qcom/gcc-qdu1000.c | 62 +++++++++++++++++-----------------
>> 1 file changed, 31 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/gcc-qdu1000.c
>> b/drivers/clk/qcom/gcc-qdu1000.c
>> index 718c34dca6e8..de35cdc93732 100644
>> --- a/drivers/clk/qcom/gcc-qdu1000.c
>> +++ b/drivers/clk/qcom/gcc-qdu1000.c
>> @@ -475,7 +475,7 @@ static struct clk_rcg2
>> gcc_aggre_noc_ecpri_dma_clk_src = {
>> .name = "gcc_aggre_noc_ecpri_dma_clk_src",
>> .parent_data = gcc_parent_data_4,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_4),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -495,7 +495,7 @@ static struct clk_rcg2
>> gcc_aggre_noc_ecpri_gsi_clk_src = {
>> .name = "gcc_aggre_noc_ecpri_gsi_clk_src",
>> .parent_data = gcc_parent_data_5,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_5),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -514,7 +514,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
>> .name = "gcc_gp1_clk_src",
>> .parent_data = gcc_parent_data_1,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -528,7 +528,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
>> .name = "gcc_gp2_clk_src",
>> .parent_data = gcc_parent_data_1,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -542,7 +542,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
>> .name = "gcc_gp3_clk_src",
>> .parent_data = gcc_parent_data_1,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -561,7 +561,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
>> .name = "gcc_pcie_0_aux_clk_src",
>> .parent_data = gcc_parent_data_3,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_3),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -581,7 +581,7 @@ static struct clk_rcg2
>> gcc_pcie_0_phy_rchng_clk_src = {
>> .name = "gcc_pcie_0_phy_rchng_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -600,7 +600,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
>> .name = "gcc_pdm2_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -622,7 +622,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap0_s0_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s0_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
>> @@ -638,7 +638,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap0_s1_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s1_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
>> @@ -654,7 +654,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap0_s2_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s2_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
>> @@ -670,7 +670,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap0_s3_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s3_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
>> @@ -686,7 +686,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap0_s4_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s4_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
>> @@ -707,7 +707,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap0_s5_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s5_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
>> @@ -723,7 +723,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap0_s6_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s6_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
>> @@ -739,7 +739,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap0_s7_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s7_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
>> @@ -755,7 +755,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap1_s0_clk_src_init = {
>> .name = "gcc_qupv3_wrap1_s0_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
>> @@ -771,7 +771,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap1_s1_clk_src_init = {
>> .name = "gcc_qupv3_wrap1_s1_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
>> @@ -787,7 +787,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap1_s2_clk_src_init = {
>> .name = "gcc_qupv3_wrap1_s2_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
>> @@ -803,7 +803,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap1_s3_clk_src_init = {
>> .name = "gcc_qupv3_wrap1_s3_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
>> @@ -819,7 +819,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap1_s4_clk_src_init = {
>> .name = "gcc_qupv3_wrap1_s4_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
>> @@ -835,7 +835,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap1_s5_clk_src_init = {
>> .name = "gcc_qupv3_wrap1_s5_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
>> @@ -851,7 +851,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap1_s6_clk_src_init = {
>> .name = "gcc_qupv3_wrap1_s6_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
>> @@ -867,7 +867,7 @@ static struct clk_init_data
>> gcc_qupv3_wrap1_s7_clk_src_init = {
>> .name = "gcc_qupv3_wrap1_s7_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>> static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
>> @@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src = {
>> .name = "gcc_sdcc5_apps_clk_src",
>> .parent_data = gcc_parent_data_8,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_8),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_floor_ops,
>> },
>> };
>> @@ -922,7 +922,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = {
>> .name = "gcc_sdcc5_ice_core_clk_src",
>> .parent_data = gcc_parent_data_2,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_floor_ops,
>> },
>> };
>> @@ -936,7 +936,7 @@ static struct clk_rcg2 gcc_sm_bus_xo_clk_src = {
>> .name = "gcc_sm_bus_xo_clk_src",
>> .parent_data = gcc_parent_data_2,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -955,7 +955,7 @@ static struct clk_rcg2 gcc_tsc_clk_src = {
>> .name = "gcc_tsc_clk_src",
>> .parent_data = gcc_parent_data_9,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_9),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -975,7 +975,7 @@ static struct clk_rcg2
>> gcc_usb30_prim_master_clk_src = {
>> .name = "gcc_usb30_prim_master_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -989,7 +989,7 @@ static struct clk_rcg2
>> gcc_usb30_prim_mock_utmi_clk_src = {
>> .name = "gcc_usb30_prim_mock_utmi_clk_src",
>> .parent_data = gcc_parent_data_0,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>> @@ -1003,7 +1003,7 @@ static struct clk_rcg2
>> gcc_usb3_prim_phy_aux_clk_src = {
>> .name = "gcc_usb3_prim_phy_aux_clk_src",
>> .parent_data = gcc_parent_data_3,
>> .num_parents = ARRAY_SIZE(gcc_parent_data_3),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V3 4/6] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version
2023-07-06 10:50 ` [PATCH V3 4/6] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version Imran Shaik
@ 2023-07-15 13:20 ` Konrad Dybcio
2023-07-17 6:04 ` Imran Shaik
0 siblings, 1 reply; 11+ messages in thread
From: Konrad Dybcio @ 2023-07-15 13:20 UTC (permalink / raw)
To: Imran Shaik, Andy Gross, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Melody Olvera, Dmitry Baryshkov,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
Jagadeesh Kona, Satya Priya Kakitapalli, Ajit Pandey
On 6.07.2023 12:50, Imran Shaik wrote:
> Update the GCC clocks as per the latest hw version of QDU1000 and
> QRU100 SoCs.
>
> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
> ---
> Changes since v2:
> - Split the patch as per the review comments
> - Newly added
>
> drivers/clk/qcom/gcc-qdu1000.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
> index 8df7b7983968..991fb2bc97e9 100644
> --- a/drivers/clk/qcom/gcc-qdu1000.c
> +++ b/drivers/clk/qcom/gcc-qdu1000.c
> @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = {
> },
> };
>
> +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = {
> + .halt_reg = 0x54298,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x54298,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x54298,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gcc_ddrss_ecpri_gsi_clk",
> + .parent_hws = (const struct clk_hw*[]) {
> + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_aon_ops,
> + },
> + },
> +};
> +
> static struct clk_branch gcc_ecpri_ahb_clk = {
> .halt_reg = 0x3a008,
> .halt_check = BRANCH_HALT_VOTED,
> @@ -2521,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = {
> [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr,
> [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
> [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
> + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
Looks like you split it too much.. this clock is not being defined in this patch.
Konrad
> + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,
> };
>
> static const struct qcom_reset_map gcc_qdu1000_resets[] = {
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V3 4/6] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version
2023-07-15 13:20 ` Konrad Dybcio
@ 2023-07-17 6:04 ` Imran Shaik
0 siblings, 0 replies; 11+ messages in thread
From: Imran Shaik @ 2023-07-17 6:04 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Taniya Das, Melody Olvera, Dmitry Baryshkov,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
Jagadeesh Kona, Satya Priya Kakitapalli, Ajit Pandey
On 7/15/2023 6:50 PM, Konrad Dybcio wrote:
> On 6.07.2023 12:50, Imran Shaik wrote:
>> Update the GCC clocks as per the latest hw version of QDU1000 and
>> QRU100 SoCs.
>>
>> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
>> ---
>> Changes since v2:
>> - Split the patch as per the review comments
>> - Newly added
>>
>> drivers/clk/qcom/gcc-qdu1000.c | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
>> index 8df7b7983968..991fb2bc97e9 100644
>> --- a/drivers/clk/qcom/gcc-qdu1000.c
>> +++ b/drivers/clk/qcom/gcc-qdu1000.c
>> @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = {
>> },
>> };
>>
>> +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = {
>> + .halt_reg = 0x54298,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x54298,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x54298,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_ddrss_ecpri_gsi_clk",
>> + .parent_hws = (const struct clk_hw*[]) {
>> + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_aon_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_branch gcc_ecpri_ahb_clk = {
>> .halt_reg = 0x3a008,
>> .halt_check = BRANCH_HALT_VOTED,
>> @@ -2521,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = {
>> [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr,
>> [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
>> [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
>> + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
> Looks like you split it too much.. this clock is not being defined in this patch.
>
> Konrad
This clock was already defined in the initial gcc changes and now adding
it to gcc_qdu1000_clocks[] to register it with the clock framework.
Thanks,
Imran
>> + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,
>> };
>>
>> static const struct qcom_reset_map gcc_qdu1000_resets[] = {
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-07-17 6:04 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-06 10:50 [PATCH V3 0/6] Update GCC clocks for QDU1000 and QRU1000 SoCs Imran Shaik
2023-07-06 10:50 ` [PATCH V3 1/6] dt-bindings: clock: " Imran Shaik
2023-07-06 10:50 ` [PATCH V3 2/6] clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling Imran Shaik
2023-07-06 10:50 ` [PATCH V3 3/6] clk: qcom: gcc-qdu1000: Fix clkref clocks handling Imran Shaik
2023-07-06 10:50 ` [PATCH V3 4/6] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version Imran Shaik
2023-07-15 13:20 ` Konrad Dybcio
2023-07-17 6:04 ` Imran Shaik
2023-07-06 10:50 ` [PATCH V3 5/6] clk: qcom: gcc-qdu1000: Add support for GDSCs Imran Shaik
2023-07-06 10:50 ` [PATCH V3 6/6] clk: qcom: gcc-qdu1000: Update the RCGs ops Imran Shaik
2023-07-06 14:16 ` Dmitry Baryshkov
2023-07-14 5:19 ` Imran Shaik
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