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* [PATCH 1/2] drm/amdgpu/gfx9: move update_spm_vmid() out of rlc_init()
@ 2023-07-06 18:55 Alex Deucher
  2023-07-06 18:55 ` [PATCH 2/2] drm/amdgpu/gfx10: " Alex Deucher
  2023-07-07  8:31 ` [PATCH 1/2] drm/amdgpu/gfx9: " Christian König
  0 siblings, 2 replies; 3+ messages in thread
From: Alex Deucher @ 2023-07-06 18:55 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher

rlc_init() is part of sw_init() so it should not touch hardware.
Additionally, calling the rlc update_spm_vmid() callback
directly invokes a gfx on/off cycle which could result in
powergating being enabled before hw init is complete.  Split
update_spm_vmid() into an internal implementation for local
use without gfxoff interaction and then the rlc callback
which includes gfxoff handling.  lbpw_init also touches
hardware so mvoe that to rlc_resume as well.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 34 ++++++++++++---------------
 1 file changed, 15 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d654bdd2037c9..7d992e4730db1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -762,6 +762,8 @@ static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
 				     void *inject_if, uint32_t instance_mask);
 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev);
+static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,
+					      unsigned vmid);
 
 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
 				uint64_t queue_mask)
@@ -1669,22 +1671,6 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 			return r;
 	}
 
-	switch (adev->ip_versions[GC_HWIP][0]) {
-	case IP_VERSION(9, 2, 2):
-	case IP_VERSION(9, 1, 0):
-		gfx_v9_0_init_lbpw(adev);
-		break;
-	case IP_VERSION(9, 4, 0):
-		gfx_v9_4_init_lbpw(adev);
-		break;
-	default:
-		break;
-	}
-
-	/* init spm vmid with 0xf */
-	if (adev->gfx.rlc.funcs->update_spm_vmid)
-		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
-
 	return 0;
 }
 
@@ -2944,12 +2930,14 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
 	switch (adev->ip_versions[GC_HWIP][0]) {
 	case IP_VERSION(9, 2, 2):
 	case IP_VERSION(9, 1, 0):
+		gfx_v9_0_init_lbpw(adev);
 		if (amdgpu_lbpw == 0)
 			gfx_v9_0_enable_lbpw(adev, false);
 		else
 			gfx_v9_0_enable_lbpw(adev, true);
 		break;
 	case IP_VERSION(9, 4, 0):
+		gfx_v9_4_init_lbpw(adev);
 		if (amdgpu_lbpw > 0)
 			gfx_v9_0_enable_lbpw(adev, true);
 		else
@@ -2959,6 +2947,8 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
 		break;
 	}
 
+	gfx_v9_0_update_spm_vmid_internal(adev, 0xf);
+
 	adev->gfx.rlc.funcs->start(adev);
 
 	return 0;
@@ -4883,12 +4873,11 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 	return 0;
 }
 
-static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,
+					      unsigned vmid)
 {
 	u32 reg, data;
 
-	amdgpu_gfx_off_ctrl(adev, false);
-
 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
 	if (amdgpu_sriov_is_pp_one_vf(adev))
 		data = RREG32_NO_KIQ(reg);
@@ -4902,6 +4891,13 @@ static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
 		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
 	else
 		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+}
+
+static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+{
+	amdgpu_gfx_off_ctrl(adev, false);
+
+	gfx_v9_0_update_spm_vmid_internal(adev, vmid);
 
 	amdgpu_gfx_off_ctrl(adev, true);
 }
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* [PATCH 2/2] drm/amdgpu/gfx10: move update_spm_vmid() out of rlc_init()
  2023-07-06 18:55 [PATCH 1/2] drm/amdgpu/gfx9: move update_spm_vmid() out of rlc_init() Alex Deucher
@ 2023-07-06 18:55 ` Alex Deucher
  2023-07-07  8:31 ` [PATCH 1/2] drm/amdgpu/gfx9: " Christian König
  1 sibling, 0 replies; 3+ messages in thread
From: Alex Deucher @ 2023-07-06 18:55 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher

rlc_init() is part of sw_init() so it should not touch hardware.
Additionally, calling the rlc update_spm_vmid() callback
directly invokes a gfx on/off cycle which could result in
powergating being enabled before hw init is complete.  Split
update_spm_vmid() into an internal implementation for local
use without gfxoff interaction and then the rlc callback
which includes gfxoff handling.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 91261ed489257..1b188aeba6515 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3506,6 +3506,8 @@ static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
 					   uint16_t pasid, uint32_t flush_type,
 					   bool all_hub, uint8_t dst_sel);
+static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
+					       unsigned vmid);
 
 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 {
@@ -4187,11 +4189,6 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
 			return r;
 	}
 
-	/* init spm vmid with 0xf */
-	if (adev->gfx.rlc.funcs->update_spm_vmid)
-		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
-
-
 	return 0;
 }
 
@@ -5169,6 +5166,8 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
 
 		gfx_v10_0_init_csb(adev);
 
+		gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
+
 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
 			gfx_v10_0_rlc_enable_srm(adev);
 	} else {
@@ -5199,6 +5198,8 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
 
 		gfx_v10_0_init_csb(adev);
 
+		gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
+
 		adev->gfx.rlc.funcs->start(adev);
 
 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
@@ -5207,6 +5208,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
 				return r;
 		}
 	}
+
 	return 0;
 }
 
@@ -7907,12 +7909,11 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 	return 0;
 }
 
-static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
+					       unsigned vmid)
 {
 	u32 reg, data;
 
-	amdgpu_gfx_off_ctrl(adev, false);
-
 	/* not for *_SOC15 */
 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
 	if (amdgpu_sriov_is_pp_one_vf(adev))
@@ -7927,6 +7928,13 @@ static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
 		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
 	else
 		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+}
+
+static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+{
+	amdgpu_gfx_off_ctrl(adev, false);
+
+	gfx_v10_0_update_spm_vmid_internal(adev, vmid);
 
 	amdgpu_gfx_off_ctrl(adev, true);
 }
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu/gfx9: move update_spm_vmid() out of rlc_init()
  2023-07-06 18:55 [PATCH 1/2] drm/amdgpu/gfx9: move update_spm_vmid() out of rlc_init() Alex Deucher
  2023-07-06 18:55 ` [PATCH 2/2] drm/amdgpu/gfx10: " Alex Deucher
@ 2023-07-07  8:31 ` Christian König
  1 sibling, 0 replies; 3+ messages in thread
From: Christian König @ 2023-07-07  8:31 UTC (permalink / raw)
  To: Alex Deucher, amd-gfx

Am 06.07.23 um 20:55 schrieb Alex Deucher:
> rlc_init() is part of sw_init() so it should not touch hardware.
> Additionally, calling the rlc update_spm_vmid() callback
> directly invokes a gfx on/off cycle which could result in
> powergating being enabled before hw init is complete.  Split
> update_spm_vmid() into an internal implementation for local
> use without gfxoff interaction and then the rlc callback
> which includes gfxoff handling.  lbpw_init also touches
> hardware so mvoe that to rlc_resume as well.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Acked-by: Christian König <christian.koenig@amd.com> for the series.

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 34 ++++++++++++---------------
>   1 file changed, 15 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index d654bdd2037c9..7d992e4730db1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -762,6 +762,8 @@ static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
>   static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
>   				     void *inject_if, uint32_t instance_mask);
>   static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev);
> +static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,
> +					      unsigned vmid);
>   
>   static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
>   				uint64_t queue_mask)
> @@ -1669,22 +1671,6 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
>   			return r;
>   	}
>   
> -	switch (adev->ip_versions[GC_HWIP][0]) {
> -	case IP_VERSION(9, 2, 2):
> -	case IP_VERSION(9, 1, 0):
> -		gfx_v9_0_init_lbpw(adev);
> -		break;
> -	case IP_VERSION(9, 4, 0):
> -		gfx_v9_4_init_lbpw(adev);
> -		break;
> -	default:
> -		break;
> -	}
> -
> -	/* init spm vmid with 0xf */
> -	if (adev->gfx.rlc.funcs->update_spm_vmid)
> -		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
> -
>   	return 0;
>   }
>   
> @@ -2944,12 +2930,14 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
>   	switch (adev->ip_versions[GC_HWIP][0]) {
>   	case IP_VERSION(9, 2, 2):
>   	case IP_VERSION(9, 1, 0):
> +		gfx_v9_0_init_lbpw(adev);
>   		if (amdgpu_lbpw == 0)
>   			gfx_v9_0_enable_lbpw(adev, false);
>   		else
>   			gfx_v9_0_enable_lbpw(adev, true);
>   		break;
>   	case IP_VERSION(9, 4, 0):
> +		gfx_v9_4_init_lbpw(adev);
>   		if (amdgpu_lbpw > 0)
>   			gfx_v9_0_enable_lbpw(adev, true);
>   		else
> @@ -2959,6 +2947,8 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
>   		break;
>   	}
>   
> +	gfx_v9_0_update_spm_vmid_internal(adev, 0xf);
> +
>   	adev->gfx.rlc.funcs->start(adev);
>   
>   	return 0;
> @@ -4883,12 +4873,11 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
>   	return 0;
>   }
>   
> -static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
> +static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,
> +					      unsigned vmid)
>   {
>   	u32 reg, data;
>   
> -	amdgpu_gfx_off_ctrl(adev, false);
> -
>   	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
>   	if (amdgpu_sriov_is_pp_one_vf(adev))
>   		data = RREG32_NO_KIQ(reg);
> @@ -4902,6 +4891,13 @@ static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
>   		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
>   	else
>   		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
> +}
> +
> +static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
> +{
> +	amdgpu_gfx_off_ctrl(adev, false);
> +
> +	gfx_v9_0_update_spm_vmid_internal(adev, vmid);
>   
>   	amdgpu_gfx_off_ctrl(adev, true);
>   }


^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-07-07  8:31 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-06 18:55 [PATCH 1/2] drm/amdgpu/gfx9: move update_spm_vmid() out of rlc_init() Alex Deucher
2023-07-06 18:55 ` [PATCH 2/2] drm/amdgpu/gfx10: " Alex Deucher
2023-07-07  8:31 ` [PATCH 1/2] drm/amdgpu/gfx9: " Christian König

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