* [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux
@ 2023-07-07 10:50 Hal Feng
2023-07-07 10:50 ` [PATCH v1 1/5] clk: starfive: jh7110: Separate the PLL driver Hal Feng
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Hal Feng @ 2023-07-07 10:50 UTC (permalink / raw)
To: Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
Hal Feng
Cc: u-boot
The clock dt-bindings and DT nodes are not consistent with Linux now.
Let's sync them with Linux, so the same dtb can work for Linux & U-Boot.
To achieve this goal, the PLL clock driver is separated and some clock
IDs conversion is needed in clock drivers.
For the motivation, please see the discussion in the link below.
[1] https://patchwork.kernel.org/project/linux-riscv/patch/20230512022036.97987-2-xingyu.wu@starfivetech.com/
Xingyu Wu (5):
clk: starfive: jh7110: Separate the PLL driver
riscv: dts: jh7110: Add PLL clock controller node
riscv: dts: jh7110: Add clock source from PLL
dt-bindings: clock: jh7110: Modify clock id to be same with Linux
clk: starfive: jh7110: Add of_xlate ops and macros for clock id
conversion
.../dts/jh7110-starfive-visionfive-2.dtsi | 6 +-
arch/riscv/dts/jh7110-u-boot.dtsi | 1 -
arch/riscv/dts/jh7110.dtsi | 16 +-
drivers/clk/starfive/clk-jh7110-pll.c | 103 +++++-
drivers/clk/starfive/clk-jh7110.c | 306 +++++++++++-------
drivers/clk/starfive/clk.h | 58 +---
.../dt-bindings/clock/starfive,jh7110-crg.h | 101 +++---
7 files changed, 365 insertions(+), 226 deletions(-)
base-commit: e1bebc16e1d9aa0ddd56c53c0b781f7186dce557
--
2.38.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v1 1/5] clk: starfive: jh7110: Separate the PLL driver
2023-07-07 10:50 [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Hal Feng
@ 2023-07-07 10:50 ` Hal Feng
2023-07-24 5:14 ` Leo Liang
2023-07-07 10:50 ` [PATCH v1 2/5] riscv: dts: jh7110: Add PLL clock controller node Hal Feng
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Hal Feng @ 2023-07-07 10:50 UTC (permalink / raw)
To: Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
Hal Feng
Cc: u-boot
From: Xingyu Wu <xingyu.wu@starfivetech.com>
Drop the PLL part in SYSCRG driver and separate to be a single
PLL driver of which the compatible is "starfive,jh7110-pll".
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/clk/starfive/clk-jh7110-pll.c | 86 +++++++++++++++++++++++++--
drivers/clk/starfive/clk-jh7110.c | 25 +-------
drivers/clk/starfive/clk.h | 57 ------------------
3 files changed, 84 insertions(+), 84 deletions(-)
delete mode 100644 drivers/clk/starfive/clk.h
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c
index 02e6d9000e..48c08bbe95 100644
--- a/drivers/clk/starfive/clk-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -3,6 +3,7 @@
* Copyright (C) 2022-23 StarFive Technology Co., Ltd.
*
* Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ * Xingyu Wu <xingyu.wu@starfivetech.com>
*/
#include <common.h>
@@ -11,13 +12,13 @@
#include <clk-uclass.h>
#include <div64.h>
#include <dm/device.h>
+#include <dm/read.h>
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
-#include "clk.h"
-
#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx"
#define PLL_PD_OFF 1
@@ -30,6 +31,45 @@
#define CLK_DDR_BUS_PLL1_DIV4 2
#define CLK_DDR_BUS_PLL1_DIV8 3
+enum starfive_pll_type {
+ PLL0 = 0,
+ PLL1,
+ PLL2,
+ PLL_MAX = PLL2
+};
+
+struct starfive_pllx_rate {
+ u64 rate;
+ u32 prediv;
+ u32 fbdiv;
+ u32 frac;
+};
+
+struct starfive_pllx_offset {
+ u32 pd;
+ u32 prediv;
+ u32 fbdiv;
+ u32 frac;
+ u32 postdiv1;
+ u32 dacpd;
+ u32 dsmpd;
+ u32 pd_mask;
+ u32 prediv_mask;
+ u32 fbdiv_mask;
+ u32 frac_mask;
+ u32 postdiv1_mask;
+ u32 dacpd_mask;
+ u32 dsmpd_mask;
+};
+
+struct starfive_pllx_clk {
+ enum starfive_pll_type type;
+ const struct starfive_pllx_offset *offset;
+ const struct starfive_pllx_rate *rate_table;
+ int rate_count;
+ int flags;
+};
+
struct clk_jh7110_pllx {
struct clk clk;
void __iomem *base;
@@ -271,7 +311,7 @@ static ulong jh7110_pllx_set_rate(struct clk *clk, ulong drate)
return jh7110_pllx_recalc_rate(clk);
}
-static const struct clk_ops clk_jh7110_ops = {
+static const struct clk_ops jh7110_clk_pllx_ops = {
.set_rate = jh7110_pllx_set_rate,
.get_rate = jh7110_pllx_recalc_rate,
};
@@ -314,8 +354,46 @@ struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
return clk;
}
+/* PLLx clock implementation */
U_BOOT_DRIVER(jh7110_clk_pllx) = {
.name = UBOOT_DM_CLK_JH7110_PLLX,
.id = UCLASS_CLK,
- .ops = &clk_jh7110_ops,
+ .ops = &jh7110_clk_pllx_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+static int jh7110_pll_clk_probe(struct udevice *dev)
+{
+ void __iomem *reg = (void __iomem *)dev_read_addr_ptr(dev->parent);
+ fdt_addr_t sysreg = ofnode_get_addr(ofnode_by_compatible(ofnode_null(),
+ "starfive,jh7110-syscrg"));
+
+ if (sysreg == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ clk_dm(JH7110_SYSCLK_PLL0_OUT,
+ starfive_jh7110_pll("pll0_out", "oscillator", reg,
+ (void __iomem *)sysreg, &starfive_jh7110_pll0));
+ clk_dm(JH7110_SYSCLK_PLL1_OUT,
+ starfive_jh7110_pll("pll1_out", "oscillator", reg,
+ (void __iomem *)sysreg, &starfive_jh7110_pll1));
+ clk_dm(JH7110_SYSCLK_PLL2_OUT,
+ starfive_jh7110_pll("pll2_out", "oscillator", reg,
+ (void __iomem *)sysreg, &starfive_jh7110_pll2));
+
+ return 0;
+}
+
+static const struct udevice_id jh7110_pll_clk_of_match[] = {
+ { .compatible = "starfive,jh7110-pll", },
+ { }
+};
+
+/* PLL clk device */
+U_BOOT_DRIVER(jh7110_pll_clk) = {
+ .name = "jh7110_pll_clk",
+ .id = UCLASS_CLK,
+ .of_match = jh7110_pll_clk_of_match,
+ .probe = jh7110_pll_clk_probe,
+ .ops = &ccf_clk_ops,
};
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index a74b70906a..d2aea8d7d1 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -3,6 +3,7 @@
* Copyright (C) 2022-23 StarFive Technology Co., Ltd.
*
* Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ * Xingyu Wu <xingyu.wu@starfivetech.com>
*/
#include <common.h>
@@ -16,8 +17,6 @@
#include <log.h>
#include <linux/clk-provider.h>
-#include "clk.h"
-
#define STARFIVE_CLK_ENABLE_SHIFT 31 /* [31] */
#define STARFIVE_CLK_INVERT_SHIFT 30 /* [30] */
#define STARFIVE_CLK_MUX_SHIFT 24 /* [29:24] */
@@ -230,28 +229,8 @@ static struct clk *starfive_clk_gate_divider(void __iomem *reg,
static int jh7110_syscrg_init(struct udevice *dev)
{
struct jh7110_clk_priv *priv = dev_get_priv(dev);
- struct ofnode_phandle_args args;
- fdt_addr_t addr;
struct clk *pclk;
- int ret;
-
- ret = ofnode_parse_phandle_with_args(dev->node_, "starfive,sys-syscon", NULL, 0, 0, &args);
- if (ret)
- return ret;
-
- addr = ofnode_get_addr(args.node);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- clk_dm(JH7110_SYSCLK_PLL0_OUT,
- starfive_jh7110_pll("pll0_out", "oscillator", (void __iomem *)addr,
- priv->reg, &starfive_jh7110_pll0));
- clk_dm(JH7110_SYSCLK_PLL1_OUT,
- starfive_jh7110_pll("pll1_out", "oscillator", (void __iomem *)addr,
- priv->reg, &starfive_jh7110_pll1));
- clk_dm(JH7110_SYSCLK_PLL2_OUT,
- starfive_jh7110_pll("pll2_out", "oscillator", (void __iomem *)addr,
- priv->reg, &starfive_jh7110_pll2));
+
clk_dm(JH7110_SYSCLK_CPU_ROOT,
starfive_clk_mux(priv->reg, "cpu_root",
OFFSET(JH7110_SYSCLK_CPU_ROOT), 1,
diff --git a/drivers/clk/starfive/clk.h b/drivers/clk/starfive/clk.h
deleted file mode 100644
index 4dee12fe89..0000000000
--- a/drivers/clk/starfive/clk.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2022 Starfive, Inc.
- * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
- *
- */
-
-#ifndef __CLK_STARFIVE_H
-#define __CLK_STARFIVE_H
-
-enum starfive_pll_type {
- PLL0 = 0,
- PLL1,
- PLL2,
- PLL_MAX = PLL2
-};
-
-struct starfive_pllx_rate {
- u64 rate;
- u32 prediv;
- u32 fbdiv;
- u32 frac;
-};
-
-struct starfive_pllx_offset {
- u32 pd;
- u32 prediv;
- u32 fbdiv;
- u32 frac;
- u32 postdiv1;
- u32 dacpd;
- u32 dsmpd;
- u32 pd_mask;
- u32 prediv_mask;
- u32 fbdiv_mask;
- u32 frac_mask;
- u32 postdiv1_mask;
- u32 dacpd_mask;
- u32 dsmpd_mask;
-};
-
-struct starfive_pllx_clk {
- enum starfive_pll_type type;
- const struct starfive_pllx_offset *offset;
- const struct starfive_pllx_rate *rate_table;
- int rate_count;
- int flags;
-};
-
-extern struct starfive_pllx_clk starfive_jh7110_pll0;
-extern struct starfive_pllx_clk starfive_jh7110_pll1;
-extern struct starfive_pllx_clk starfive_jh7110_pll2;
-
-struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
- void __iomem *base, void __iomem *sysreg,
- const struct starfive_pllx_clk *pll_clk);
-#endif
--
2.38.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 2/5] riscv: dts: jh7110: Add PLL clock controller node
2023-07-07 10:50 [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Hal Feng
2023-07-07 10:50 ` [PATCH v1 1/5] clk: starfive: jh7110: Separate the PLL driver Hal Feng
@ 2023-07-07 10:50 ` Hal Feng
2023-07-24 5:15 ` Leo Liang
2023-07-07 10:50 ` [PATCH v1 3/5] riscv: dts: jh7110: Add clock source from PLL Hal Feng
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Hal Feng @ 2023-07-07 10:50 UTC (permalink / raw)
To: Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
Hal Feng
Cc: u-boot
From: Xingyu Wu <xingyu.wu@starfivetech.com>
Add child node about PLL clock controller in sys_syscon node.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/dts/jh7110.dtsi | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..3e5bddccc5 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -491,8 +491,14 @@
};
sys_syscon: sys_syscon@13030000 {
- compatible = "starfive,jh7110-sys-syscon","syscon";
+ compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd";
reg = <0x0 0x13030000 0x0 0x1000>;
+
+ pllclk: clock-controller {
+ compatible = "starfive,jh7110-pll";
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
};
sysgpio: pinctrl@13040000 {
--
2.38.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 3/5] riscv: dts: jh7110: Add clock source from PLL
2023-07-07 10:50 [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Hal Feng
2023-07-07 10:50 ` [PATCH v1 1/5] clk: starfive: jh7110: Separate the PLL driver Hal Feng
2023-07-07 10:50 ` [PATCH v1 2/5] riscv: dts: jh7110: Add PLL clock controller node Hal Feng
@ 2023-07-07 10:50 ` Hal Feng
2023-07-24 5:15 ` Leo Liang
2023-07-07 10:50 ` [PATCH v1 4/5] dt-bindings: clock: jh7110: Modify clock id to be same with Linux Hal Feng
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Hal Feng @ 2023-07-07 10:50 UTC (permalink / raw)
To: Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
Hal Feng
Cc: u-boot
From: Xingyu Wu <xingyu.wu@starfivetech.com>
Change the PLL clock source from syscrg to sys_syscon child node.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 +++---
arch/riscv/dts/jh7110-u-boot.dtsi | 1 -
arch/riscv/dts/jh7110.dtsi | 8 ++++++--
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..fe8ae4ebee 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -305,9 +305,9 @@
<&syscrg JH7110_SYSCLK_BUS_ROOT>,
<&syscrg JH7110_SYSCLK_PERH_ROOT>,
<&syscrg JH7110_SYSCLK_QSPI_REF>;
- assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>,
- <&syscrg JH7110_SYSCLK_PLL2_OUT>,
- <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+ assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>,
+ <&pllclk JH7110_SYSCLK_PLL2_OUT>,
+ <&pllclk JH7110_SYSCLK_PLL2_OUT>,
<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
assigned-clock-rates = <0>, <0>, <0>, <0>;
};
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index c22119518c..2f560e7296 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -83,7 +83,6 @@
&syscrg {
bootph-pre-ram;
- starfive,sys-syscon = <&sys_syscon>;
};
&stgcrg {
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 3e5bddccc5..20433c766f 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -480,12 +480,16 @@
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
- <&tdm_ext>, <&mclk_ext>;
+ <&tdm_ext>, <&mclk_ext>,
+ <&pllclk JH7110_SYSCLK_PLL0_OUT>,
+ <&pllclk JH7110_SYSCLK_PLL1_OUT>,
+ <&pllclk JH7110_SYSCLK_PLL2_OUT>;
clock-names = "osc", "gmac1_rmii_refin",
"gmac1_rgmii_rxin",
"i2stx_bclk_ext", "i2stx_lrck_ext",
"i2srx_bclk_ext", "i2srx_lrck_ext",
- "tdm_ext", "mclk_ext";
+ "tdm_ext", "mclk_ext",
+ "pll0_out", "pll1_out", "pll2_out";
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.38.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 4/5] dt-bindings: clock: jh7110: Modify clock id to be same with Linux
2023-07-07 10:50 [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Hal Feng
` (2 preceding siblings ...)
2023-07-07 10:50 ` [PATCH v1 3/5] riscv: dts: jh7110: Add clock source from PLL Hal Feng
@ 2023-07-07 10:50 ` Hal Feng
2023-07-24 5:15 ` Leo Liang
2023-07-07 10:50 ` [PATCH v1 5/5] clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion Hal Feng
2023-07-11 9:09 ` [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Torsten Duwe
5 siblings, 1 reply; 13+ messages in thread
From: Hal Feng @ 2023-07-07 10:50 UTC (permalink / raw)
To: Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
Hal Feng
Cc: u-boot
From: Xingyu Wu <xingyu.wu@starfivetech.com>
The clock id needs to be changed to be consistent with Linux.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../dt-bindings/clock/starfive,jh7110-crg.h | 101 +++++++++---------
1 file changed, 51 insertions(+), 50 deletions(-)
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index 77b70e7a83..b51e3829ff 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -8,6 +8,11 @@
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
+#define JH7110_SYSCLK_PLL0_OUT 0
+#define JH7110_SYSCLK_PLL1_OUT 1
+#define JH7110_SYSCLK_PLL2_OUT 2
+#define JH7110_PLLCLK_END 3
+
#define JH7110_SYSCLK_CPU_ROOT 0
#define JH7110_SYSCLK_CPU_CORE 1
#define JH7110_SYSCLK_CPU_BUS 2
@@ -199,59 +204,55 @@
#define JH7110_SYSCLK_TDM_CLK_TDM_N 188
#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
-#define JH7110_SYSCLK_PLL0_OUT 190
-#define JH7110_SYSCLK_PLL1_OUT 191
-#define JH7110_SYSCLK_PLL2_OUT 192
-
-#define JH7110_SYSCLK_END 193
+#define JH7110_SYSCLK_END 190
-#define JH7110_AONCLK_OSC_DIV4 (JH7110_SYSCLK_END + 0)
-#define JH7110_AONCLK_APB_FUNC (JH7110_SYSCLK_END + 1)
-#define JH7110_AONCLK_GMAC0_AHB (JH7110_SYSCLK_END + 2)
-#define JH7110_AONCLK_GMAC0_AXI (JH7110_SYSCLK_END + 3)
-#define JH7110_AONCLK_GMAC0_RMII_RTX (JH7110_SYSCLK_END + 4)
-#define JH7110_AONCLK_GMAC0_TX (JH7110_SYSCLK_END + 5)
-#define JH7110_AONCLK_GMAC0_TX_INV (JH7110_SYSCLK_END + 6)
-#define JH7110_AONCLK_GMAC0_RX (JH7110_SYSCLK_END + 7)
-#define JH7110_AONCLK_GMAC0_RX_INV (JH7110_SYSCLK_END + 8)
-#define JH7110_AONCLK_OTPC_APB (JH7110_SYSCLK_END + 9)
-#define JH7110_AONCLK_RTC_APB (JH7110_SYSCLK_END + 10)
-#define JH7110_AONCLK_RTC_INTERNAL (JH7110_SYSCLK_END + 11)
-#define JH7110_AONCLK_RTC_32K (JH7110_SYSCLK_END + 12)
-#define JH7110_AONCLK_RTC_CAL (JH7110_SYSCLK_END + 13)
+#define JH7110_AONCLK_OSC_DIV4 0
+#define JH7110_AONCLK_APB_FUNC 1
+#define JH7110_AONCLK_GMAC0_AHB 2
+#define JH7110_AONCLK_GMAC0_AXI 3
+#define JH7110_AONCLK_GMAC0_RMII_RTX 4
+#define JH7110_AONCLK_GMAC0_TX 5
+#define JH7110_AONCLK_GMAC0_TX_INV 6
+#define JH7110_AONCLK_GMAC0_RX 7
+#define JH7110_AONCLK_GMAC0_RX_INV 8
+#define JH7110_AONCLK_OTPC_APB 9
+#define JH7110_AONCLK_RTC_APB 10
+#define JH7110_AONCLK_RTC_INTERNAL 11
+#define JH7110_AONCLK_RTC_32K 12
+#define JH7110_AONCLK_RTC_CAL 13
-#define JH7110_AONCLK_END (JH7110_SYSCLK_END + 14)
+#define JH7110_AONCLK_END 14
-#define JH7110_STGCLK_HIFI4_CORE (JH7110_AONCLK_END + 0)
-#define JH7110_STGCLK_USB_APB (JH7110_AONCLK_END + 1)
-#define JH7110_STGCLK_USB_UTMI_APB (JH7110_AONCLK_END + 2)
-#define JH7110_STGCLK_USB_AXI (JH7110_AONCLK_END + 3)
-#define JH7110_STGCLK_USB_LPM (JH7110_AONCLK_END + 4)
-#define JH7110_STGCLK_USB_STB (JH7110_AONCLK_END + 5)
-#define JH7110_STGCLK_USB_APP_125 (JH7110_AONCLK_END + 6)
-#define JH7110_STGCLK_USB_REFCLK (JH7110_AONCLK_END + 7)
-#define JH7110_STGCLK_PCIE0_AXI (JH7110_AONCLK_END + 8)
-#define JH7110_STGCLK_PCIE0_APB (JH7110_AONCLK_END + 9)
-#define JH7110_STGCLK_PCIE0_TL (JH7110_AONCLK_END + 10)
-#define JH7110_STGCLK_PCIE1_AXI (JH7110_AONCLK_END + 11)
-#define JH7110_STGCLK_PCIE1_APB (JH7110_AONCLK_END + 12)
-#define JH7110_STGCLK_PCIE1_TL (JH7110_AONCLK_END + 13)
-#define JH7110_STGCLK_PCIE01_MAIN (JH7110_AONCLK_END + 14)
-#define JH7110_STGCLK_SEC_HCLK (JH7110_AONCLK_END + 15)
-#define JH7110_STGCLK_SEC_MISCAHB (JH7110_AONCLK_END + 16)
-#define JH7110_STGCLK_MTRX_GRP0_MAIN (JH7110_AONCLK_END + 17)
-#define JH7110_STGCLK_MTRX_GRP0_BUS (JH7110_AONCLK_END + 18)
-#define JH7110_STGCLK_MTRX_GRP0_STG (JH7110_AONCLK_END + 19)
-#define JH7110_STGCLK_MTRX_GRP1_MAIN (JH7110_AONCLK_END + 20)
-#define JH7110_STGCLK_MTRX_GRP1_BUS (JH7110_AONCLK_END + 21)
-#define JH7110_STGCLK_MTRX_GRP1_STG (JH7110_AONCLK_END + 22)
-#define JH7110_STGCLK_MTRX_GRP1_HIFI (JH7110_AONCLK_END + 23)
-#define JH7110_STGCLK_E2_RTC (JH7110_AONCLK_END + 24)
-#define JH7110_STGCLK_E2_CORE (JH7110_AONCLK_END + 25)
-#define JH7110_STGCLK_E2_DBG (JH7110_AONCLK_END + 26)
-#define JH7110_STGCLK_DMA1P_AXI (JH7110_AONCLK_END + 27)
-#define JH7110_STGCLK_DMA1P_AHB (JH7110_AONCLK_END + 28)
+#define JH7110_STGCLK_HIFI4_CORE 0
+#define JH7110_STGCLK_USB_APB 1
+#define JH7110_STGCLK_USB_UTMI_APB 2
+#define JH7110_STGCLK_USB_AXI 3
+#define JH7110_STGCLK_USB_LPM 4
+#define JH7110_STGCLK_USB_STB 5
+#define JH7110_STGCLK_USB_APP_125 6
+#define JH7110_STGCLK_USB_REFCLK 7
+#define JH7110_STGCLK_PCIE0_AXI 8
+#define JH7110_STGCLK_PCIE0_APB 9
+#define JH7110_STGCLK_PCIE0_TL 10
+#define JH7110_STGCLK_PCIE1_AXI 11
+#define JH7110_STGCLK_PCIE1_APB 12
+#define JH7110_STGCLK_PCIE1_TL 13
+#define JH7110_STGCLK_PCIE01_MAIN 14
+#define JH7110_STGCLK_SEC_HCLK 15
+#define JH7110_STGCLK_SEC_MISCAHB 16
+#define JH7110_STGCLK_MTRX_GRP0_MAIN 17
+#define JH7110_STGCLK_MTRX_GRP0_BUS 18
+#define JH7110_STGCLK_MTRX_GRP0_STG 19
+#define JH7110_STGCLK_MTRX_GRP1_MAIN 20
+#define JH7110_STGCLK_MTRX_GRP1_BUS 21
+#define JH7110_STGCLK_MTRX_GRP1_STG 22
+#define JH7110_STGCLK_MTRX_GRP1_HIFI 23
+#define JH7110_STGCLK_E2_RTC 24
+#define JH7110_STGCLK_E2_CORE 25
+#define JH7110_STGCLK_E2_DBG 26
+#define JH7110_STGCLK_DMA1P_AXI 27
+#define JH7110_STGCLK_DMA1P_AHB 28
-#define JH7110_STGCLK_END (JH7110_AONCLK_END + 29)
+#define JH7110_STGCLK_END 29
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
--
2.38.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 5/5] clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion
2023-07-07 10:50 [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Hal Feng
` (3 preceding siblings ...)
2023-07-07 10:50 ` [PATCH v1 4/5] dt-bindings: clock: jh7110: Modify clock id to be same with Linux Hal Feng
@ 2023-07-07 10:50 ` Hal Feng
2023-07-24 5:16 ` Leo Liang
2023-07-11 9:09 ` [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Torsten Duwe
5 siblings, 1 reply; 13+ messages in thread
From: Hal Feng @ 2023-07-07 10:50 UTC (permalink / raw)
To: Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
Hal Feng
Cc: u-boot
From: Xingyu Wu <xingyu.wu@starfivetech.com>
Modify the drivers to add of_xlate ops and transform clock id.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/clk/starfive/clk-jh7110-pll.c | 29 ++-
drivers/clk/starfive/clk-jh7110.c | 287 +++++++++++++++++---------
drivers/clk/starfive/clk.h | 25 +++
3 files changed, 235 insertions(+), 106 deletions(-)
create mode 100644 drivers/clk/starfive/clk.h
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c
index 48c08bbe95..57c9660f08 100644
--- a/drivers/clk/starfive/clk-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -19,6 +19,8 @@
#include <linux/delay.h>
#include <linux/err.h>
+#include "clk.h"
+
#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx"
#define PLL_PD_OFF 1
@@ -31,6 +33,8 @@
#define CLK_DDR_BUS_PLL1_DIV4 2
#define CLK_DDR_BUS_PLL1_DIV8 3
+#define JH7110_PLL_ID_TRANS(id) ((id) + JH7110_EXTCLK_END)
+
enum starfive_pll_type {
PLL0 = 0,
PLL1,
@@ -371,29 +375,46 @@ static int jh7110_pll_clk_probe(struct udevice *dev)
if (sysreg == FDT_ADDR_T_NONE)
return -EINVAL;
- clk_dm(JH7110_SYSCLK_PLL0_OUT,
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT),
starfive_jh7110_pll("pll0_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll0));
- clk_dm(JH7110_SYSCLK_PLL1_OUT,
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT),
starfive_jh7110_pll("pll1_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll1));
- clk_dm(JH7110_SYSCLK_PLL2_OUT,
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT),
starfive_jh7110_pll("pll2_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll2));
return 0;
}
+static int jh7110_pll_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+ if (args->args_count > 1) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args_count)
+ clk->id = JH7110_PLL_ID_TRANS(args->args[0]);
+ else
+ clk->id = 0;
+
+ return 0;
+}
+
static const struct udevice_id jh7110_pll_clk_of_match[] = {
{ .compatible = "starfive,jh7110-pll", },
{ }
};
+JH7110_CLK_OPS(pll);
+
/* PLL clk device */
U_BOOT_DRIVER(jh7110_pll_clk) = {
.name = "jh7110_pll_clk",
.id = UCLASS_CLK,
.of_match = jh7110_pll_clk_of_match,
.probe = jh7110_pll_clk_probe,
- .ops = &ccf_clk_ops,
+ .ops = &jh7110_pll_clk_ops,
};
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index d2aea8d7d1..31aaf3340f 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -17,14 +17,18 @@
#include <log.h>
#include <linux/clk-provider.h>
+#include "clk.h"
+
#define STARFIVE_CLK_ENABLE_SHIFT 31 /* [31] */
#define STARFIVE_CLK_INVERT_SHIFT 30 /* [30] */
#define STARFIVE_CLK_MUX_SHIFT 24 /* [29:24] */
#define STARFIVE_CLK_DIV_SHIFT 0 /* [23:0] */
#define OFFSET(id) ((id) * 4)
-#define AONOFFSET(id) (((id) - JH7110_SYSCLK_END) * 4)
-#define STGOFFSET(id) (((id) - JH7110_AONCLK_END) * 4)
+
+#define JH7110_SYS_ID_TRANS(id) ((id) + JH7110_PLLCLK_END + JH7110_EXTCLK_END)
+#define JH7110_AON_ID_TRANS(id) ((id) + JH7110_SYS_ID_TRANS(JH7110_SYSCLK_END))
+#define JH7110_STG_ID_TRANS(id) ((id) + JH7110_AON_ID_TRANS(JH7110_AONCLK_END))
typedef int (*jh1710_init_fn)(struct udevice *dev);
@@ -231,202 +235,202 @@ static int jh7110_syscrg_init(struct udevice *dev)
struct jh7110_clk_priv *priv = dev_get_priv(dev);
struct clk *pclk;
- clk_dm(JH7110_SYSCLK_CPU_ROOT,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_CPU_ROOT),
starfive_clk_mux(priv->reg, "cpu_root",
OFFSET(JH7110_SYSCLK_CPU_ROOT), 1,
cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
- clk_dm(JH7110_SYSCLK_CPU_CORE,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_CPU_CORE),
starfive_clk_divider(priv->reg,
"cpu_core", "cpu_root",
OFFSET(JH7110_SYSCLK_CPU_CORE), 3));
- clk_dm(JH7110_SYSCLK_CPU_BUS,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_CPU_BUS),
starfive_clk_divider(priv->reg,
"cpu_bus", "cpu_core",
OFFSET(JH7110_SYSCLK_CPU_BUS), 2));
- clk_dm(JH7110_SYSCLK_PERH_ROOT,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_PERH_ROOT),
starfive_clk_composite(priv->reg,
"perh_root",
perh_root_sels, ARRAY_SIZE(perh_root_sels),
OFFSET(JH7110_SYSCLK_PERH_ROOT), 1, 0, 2));
- clk_dm(JH7110_SYSCLK_BUS_ROOT,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_BUS_ROOT),
starfive_clk_mux(priv->reg, "bus_root",
OFFSET(JH7110_SYSCLK_BUS_ROOT), 1,
bus_root_sels, ARRAY_SIZE(bus_root_sels)));
- clk_dm(JH7110_SYSCLK_NOCSTG_BUS,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_NOCSTG_BUS),
starfive_clk_divider(priv->reg,
"nocstg_bus", "bus_root",
OFFSET(JH7110_SYSCLK_NOCSTG_BUS), 3));
- clk_dm(JH7110_SYSCLK_AXI_CFG0,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_AXI_CFG0),
starfive_clk_divider(priv->reg,
"axi_cfg0", "bus_root",
OFFSET(JH7110_SYSCLK_AXI_CFG0), 2));
- clk_dm(JH7110_SYSCLK_STG_AXIAHB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_STG_AXIAHB),
starfive_clk_divider(priv->reg,
"stg_axiahb", "axi_cfg0",
OFFSET(JH7110_SYSCLK_STG_AXIAHB), 2));
- clk_dm(JH7110_SYSCLK_AHB0,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_AHB0),
starfive_clk_gate(priv->reg,
"ahb0", "stg_axiahb",
OFFSET(JH7110_SYSCLK_AHB0)));
- clk_dm(JH7110_SYSCLK_AHB1,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_AHB1),
starfive_clk_gate(priv->reg,
"ahb1", "stg_axiahb",
OFFSET(JH7110_SYSCLK_AHB1)));
- clk_dm(JH7110_SYSCLK_APB_BUS,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_APB_BUS),
starfive_clk_divider(priv->reg,
"apb_bus", "stg_axiahb",
OFFSET(JH7110_SYSCLK_APB_BUS), 4));
- clk_dm(JH7110_SYSCLK_APB0,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_APB0),
starfive_clk_gate(priv->reg,
"apb0", "apb_bus",
OFFSET(JH7110_SYSCLK_APB0)));
- clk_dm(JH7110_SYSCLK_QSPI_AHB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_QSPI_AHB),
starfive_clk_gate(priv->reg,
"qspi_ahb", "ahb1",
OFFSET(JH7110_SYSCLK_QSPI_AHB)));
- clk_dm(JH7110_SYSCLK_QSPI_APB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_QSPI_APB),
starfive_clk_gate(priv->reg,
"qspi_apb", "apb_bus",
OFFSET(JH7110_SYSCLK_QSPI_APB)));
- clk_dm(JH7110_SYSCLK_QSPI_REF_SRC,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_QSPI_REF_SRC),
starfive_clk_divider(priv->reg,
"qspi_ref_src", "pll0_out",
OFFSET(JH7110_SYSCLK_QSPI_REF_SRC), 5));
- clk_dm(JH7110_SYSCLK_QSPI_REF,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_QSPI_REF),
starfive_clk_composite(priv->reg,
"qspi_ref",
qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
OFFSET(JH7110_SYSCLK_QSPI_REF), 1, 1, 0));
- clk_dm(JH7110_SYSCLK_SDIO0_AHB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_SDIO0_AHB),
starfive_clk_gate(priv->reg,
"sdio0_ahb", "ahb0",
OFFSET(JH7110_SYSCLK_SDIO0_AHB)));
- clk_dm(JH7110_SYSCLK_SDIO1_AHB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_SDIO1_AHB),
starfive_clk_gate(priv->reg,
"sdio1_ahb", "ahb0",
OFFSET(JH7110_SYSCLK_SDIO1_AHB)));
- clk_dm(JH7110_SYSCLK_SDIO0_SDCARD,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_SDIO0_SDCARD),
starfive_clk_fix_parent_composite(priv->reg,
"sdio0_sdcard", "axi_cfg0",
OFFSET(JH7110_SYSCLK_SDIO0_SDCARD), 0, 1, 4));
- clk_dm(JH7110_SYSCLK_SDIO1_SDCARD,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_SDIO1_SDCARD),
starfive_clk_fix_parent_composite(priv->reg,
"sdio1_sdcard", "axi_cfg0",
OFFSET(JH7110_SYSCLK_SDIO1_SDCARD), 0, 1, 4));
- clk_dm(JH7110_SYSCLK_USB_125M,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_USB_125M),
starfive_clk_divider(priv->reg,
"usb_125m", "pll0_out",
OFFSET(JH7110_SYSCLK_USB_125M), 4));
- clk_dm(JH7110_SYSCLK_NOC_BUS_STG_AXI,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_NOC_BUS_STG_AXI),
starfive_clk_gate(priv->reg,
"noc_bus_stg_axi", "nocstg_bus",
OFFSET(JH7110_SYSCLK_NOC_BUS_STG_AXI)));
- clk_dm(JH7110_SYSCLK_GMAC1_AHB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_AHB),
starfive_clk_gate(priv->reg,
"gmac1_ahb", "ahb0",
OFFSET(JH7110_SYSCLK_GMAC1_AHB)));
- clk_dm(JH7110_SYSCLK_GMAC1_AXI,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_AXI),
starfive_clk_gate(priv->reg,
"gmac1_axi", "stg_axiahb",
OFFSET(JH7110_SYSCLK_GMAC1_AXI)));
- clk_dm(JH7110_SYSCLK_GMAC_SRC,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC_SRC),
starfive_clk_divider(priv->reg,
"gmac_src", "pll0_out",
OFFSET(JH7110_SYSCLK_GMAC_SRC), 3));
- clk_dm(JH7110_SYSCLK_GMAC1_GTXCLK,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_GTXCLK),
starfive_clk_divider(priv->reg,
"gmac1_gtxclk", "pll0_out",
OFFSET(JH7110_SYSCLK_GMAC1_GTXCLK), 4));
- clk_dm(JH7110_SYSCLK_GMAC1_GTXC,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_GTXC),
starfive_clk_gate(priv->reg,
"gmac1_gtxc", "gmac1_gtxclk",
OFFSET(JH7110_SYSCLK_GMAC1_GTXC)));
- clk_dm(JH7110_SYSCLK_GMAC1_RMII_RTX,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_RMII_RTX),
starfive_clk_divider(priv->reg,
"gmac1_rmii_rtx", "gmac1-rmii-refin-clock",
OFFSET(JH7110_SYSCLK_GMAC1_RMII_RTX), 5));
- clk_dm(JH7110_SYSCLK_GMAC1_PTP,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_PTP),
starfive_clk_gate_divider(priv->reg,
"gmac1_ptp", "gmac_src",
OFFSET(JH7110_SYSCLK_GMAC1_PTP), 5));
- clk_dm(JH7110_SYSCLK_GMAC1_RX,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_RX),
starfive_clk_mux(priv->reg, "gmac1_rx",
OFFSET(JH7110_SYSCLK_GMAC1_RX), 1,
gmac1_rx_sels, ARRAY_SIZE(gmac1_rx_sels)));
- clk_dm(JH7110_SYSCLK_GMAC1_TX,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_TX),
starfive_clk_composite(priv->reg,
"gmac1_tx",
gmac1_tx_sels, ARRAY_SIZE(gmac1_tx_sels),
OFFSET(JH7110_SYSCLK_GMAC1_TX), 1, 1, 0));
- clk_dm(JH7110_SYSCLK_GMAC1_TX_INV,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC1_TX_INV),
starfive_clk_inv(priv->reg,
"gmac1_tx_inv", "gmac1_tx",
OFFSET(JH7110_SYSCLK_GMAC1_TX_INV)));
- clk_dm(JH7110_SYSCLK_GMAC0_GTXCLK,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC0_GTXCLK),
starfive_clk_gate_divider(priv->reg,
"gmac0_gtxclk", "pll0_out",
OFFSET(JH7110_SYSCLK_GMAC0_GTXCLK), 4));
- clk_dm(JH7110_SYSCLK_GMAC0_PTP,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC0_PTP),
starfive_clk_gate_divider(priv->reg,
"gmac0_ptp", "gmac_src",
OFFSET(JH7110_SYSCLK_GMAC0_PTP), 5));
- clk_dm(JH7110_SYSCLK_GMAC0_GTXC,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_GMAC0_GTXC),
starfive_clk_gate(priv->reg,
"gmac0_gtxc", "gmac0_gtxclk",
OFFSET(JH7110_SYSCLK_GMAC0_GTXC)));
- clk_dm(JH7110_SYSCLK_UART0_APB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART0_APB),
starfive_clk_gate(priv->reg,
"uart0_apb", "apb0",
OFFSET(JH7110_SYSCLK_UART0_APB)));
- clk_dm(JH7110_SYSCLK_UART0_CORE,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART0_CORE),
starfive_clk_gate(priv->reg,
"uart0_core", "oscillator",
OFFSET(JH7110_SYSCLK_UART0_CORE)));
- clk_dm(JH7110_SYSCLK_UART1_APB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART1_APB),
starfive_clk_gate(priv->reg,
"uart1_apb", "apb0",
OFFSET(JH7110_SYSCLK_UART1_APB)));
- clk_dm(JH7110_SYSCLK_UART1_CORE,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART1_CORE),
starfive_clk_gate(priv->reg,
"uart1_core", "oscillator",
OFFSET(JH7110_SYSCLK_UART1_CORE)));
- clk_dm(JH7110_SYSCLK_UART2_APB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART2_APB),
starfive_clk_gate(priv->reg,
"uart2_apb", "apb0",
OFFSET(JH7110_SYSCLK_UART2_APB)));
- clk_dm(JH7110_SYSCLK_UART2_CORE,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART2_CORE),
starfive_clk_gate(priv->reg,
"uart2_core", "oscillator",
OFFSET(JH7110_SYSCLK_UART2_CORE)));
- clk_dm(JH7110_SYSCLK_UART3_APB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART3_APB),
starfive_clk_gate(priv->reg,
"uart3_apb", "apb0",
OFFSET(JH7110_SYSCLK_UART3_APB)));
- clk_dm(JH7110_SYSCLK_UART3_CORE,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART3_CORE),
starfive_clk_gate_divider(priv->reg,
"uart3_core", "perh_root",
OFFSET(JH7110_SYSCLK_UART3_CORE), 8));
- clk_dm(JH7110_SYSCLK_UART4_APB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART4_APB),
starfive_clk_gate(priv->reg,
"uart4_apb", "apb0",
OFFSET(JH7110_SYSCLK_UART4_APB)));
- clk_dm(JH7110_SYSCLK_UART4_CORE,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART4_CORE),
starfive_clk_gate_divider(priv->reg,
"uart4_core", "perh_root",
OFFSET(JH7110_SYSCLK_UART4_CORE), 8));
- clk_dm(JH7110_SYSCLK_UART5_APB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART5_APB),
starfive_clk_gate(priv->reg,
"uart5_apb", "apb0",
OFFSET(JH7110_SYSCLK_UART5_APB)));
- clk_dm(JH7110_SYSCLK_UART5_CORE,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_UART5_CORE),
starfive_clk_gate_divider(priv->reg,
"uart5_core", "perh_root",
OFFSET(JH7110_SYSCLK_UART5_CORE), 8));
- clk_dm(JH7110_SYSCLK_I2C2_APB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_I2C2_APB),
starfive_clk_gate(priv->reg,
"i2c2_apb", "apb0",
OFFSET(JH7110_SYSCLK_I2C2_APB)));
- clk_dm(JH7110_SYSCLK_I2C5_APB,
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_I2C5_APB),
starfive_clk_gate(priv->reg,
"i2c5_apb", "apb0",
OFFSET(JH7110_SYSCLK_I2C5_APB)));
@@ -442,39 +446,39 @@ static int jh7110_aoncrg_init(struct udevice *dev)
{
struct jh7110_clk_priv *priv = dev_get_priv(dev);
- clk_dm(JH7110_AONCLK_OSC_DIV4,
+ clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_OSC_DIV4),
starfive_clk_divider(priv->reg,
"osc_div4", "oscillator",
- AONOFFSET(JH7110_AONCLK_OSC_DIV4), 5));
- clk_dm(JH7110_AONCLK_APB_FUNC,
+ OFFSET(JH7110_AONCLK_OSC_DIV4), 5));
+ clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_APB_FUNC),
starfive_clk_mux(priv->reg, "apb_func",
- AONOFFSET(JH7110_AONCLK_APB_FUNC), 1,
+ OFFSET(JH7110_AONCLK_APB_FUNC), 1,
apb_func_sels, ARRAY_SIZE(apb_func_sels)));
- clk_dm(JH7110_AONCLK_GMAC0_AHB,
+ clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_GMAC0_AHB),
starfive_clk_gate(priv->reg,
"gmac0_ahb", "stg_axiahb",
- AONOFFSET(JH7110_AONCLK_GMAC0_AHB)));
- clk_dm(JH7110_AONCLK_GMAC0_AXI,
+ OFFSET(JH7110_AONCLK_GMAC0_AHB)));
+ clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_GMAC0_AXI),
starfive_clk_gate(priv->reg,
"gmac0_axi", "stg_axiahb",
- AONOFFSET(JH7110_AONCLK_GMAC0_AXI)));
- clk_dm(JH7110_AONCLK_GMAC0_RMII_RTX,
+ OFFSET(JH7110_AONCLK_GMAC0_AXI)));
+ clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_GMAC0_RMII_RTX),
starfive_clk_divider(priv->reg,
"gmac0_rmii_rtx", "gmac0-rmii-refin-clock",
- AONOFFSET(JH7110_AONCLK_GMAC0_RMII_RTX), 5));
- clk_dm(JH7110_AONCLK_GMAC0_TX,
+ OFFSET(JH7110_AONCLK_GMAC0_RMII_RTX), 5));
+ clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_GMAC0_TX),
starfive_clk_composite(priv->reg,
"gmac0_tx", gmac0_tx_sels,
ARRAY_SIZE(gmac0_tx_sels),
- AONOFFSET(JH7110_AONCLK_GMAC0_TX), 1, 1, 0));
- clk_dm(JH7110_AONCLK_GMAC0_TX_INV,
+ OFFSET(JH7110_AONCLK_GMAC0_TX), 1, 1, 0));
+ clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_GMAC0_TX_INV),
starfive_clk_inv(priv->reg,
"gmac0_tx_inv", "gmac0_tx",
- AONOFFSET(JH7110_AONCLK_GMAC0_TX_INV)));
- clk_dm(JH7110_AONCLK_OTPC_APB,
+ OFFSET(JH7110_AONCLK_GMAC0_TX_INV)));
+ clk_dm(JH7110_AON_ID_TRANS(JH7110_AONCLK_OTPC_APB),
starfive_clk_gate(priv->reg,
"otpc_apb", "apb_bus",
- AONOFFSET(JH7110_AONCLK_OTPC_APB)));
+ OFFSET(JH7110_AONCLK_OTPC_APB)));
return 0;
}
@@ -483,57 +487,57 @@ static int jh7110_stgcrg_init(struct udevice *dev)
{
struct jh7110_clk_priv *priv = dev_get_priv(dev);
- clk_dm(JH7110_STGCLK_USB_APB,
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB),
starfive_clk_gate(priv->reg,
"usb_apb", "apb_bus",
- STGOFFSET(JH7110_STGCLK_USB_APB)));
- clk_dm(JH7110_STGCLK_USB_UTMI_APB,
+ OFFSET(JH7110_STGCLK_USB_APB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_UTMI_APB),
starfive_clk_gate(priv->reg,
"usb_utmi_apb", "apb_bus",
- STGOFFSET(JH7110_STGCLK_USB_UTMI_APB)));
- clk_dm(JH7110_STGCLK_USB_AXI,
+ OFFSET(JH7110_STGCLK_USB_UTMI_APB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_AXI),
starfive_clk_gate(priv->reg,
"usb_axi", "stg_axiahb",
- STGOFFSET(JH7110_STGCLK_USB_AXI)));
- clk_dm(JH7110_STGCLK_USB_LPM,
+ OFFSET(JH7110_STGCLK_USB_AXI)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_LPM),
starfive_clk_gate_divider(priv->reg,
"usb_lpm", "oscillator",
- STGOFFSET(JH7110_STGCLK_USB_LPM), 2));
- clk_dm(JH7110_STGCLK_USB_STB,
+ OFFSET(JH7110_STGCLK_USB_LPM), 2));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_STB),
starfive_clk_gate_divider(priv->reg,
"usb_stb", "oscillator",
- STGOFFSET(JH7110_STGCLK_USB_STB), 3));
- clk_dm(JH7110_STGCLK_USB_APP_125,
+ OFFSET(JH7110_STGCLK_USB_STB), 3));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APP_125),
starfive_clk_gate(priv->reg,
"usb_app_125", "usb_125m",
- STGOFFSET(JH7110_STGCLK_USB_APP_125)));
- clk_dm(JH7110_STGCLK_USB_REFCLK,
+ OFFSET(JH7110_STGCLK_USB_APP_125)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_REFCLK),
starfive_clk_divider(priv->reg, "usb_refclk", "oscillator",
- STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2));
- clk_dm(JH7110_STGCLK_PCIE0_AXI,
+ OFFSET(JH7110_STGCLK_USB_REFCLK), 2));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI),
starfive_clk_gate(priv->reg,
"pcie0_axi", "stg_axiahb",
- STGOFFSET(JH7110_STGCLK_PCIE0_AXI)));
- clk_dm(JH7110_STGCLK_PCIE0_APB,
+ OFFSET(JH7110_STGCLK_PCIE0_AXI)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_APB),
starfive_clk_gate(priv->reg,
"pcie0_apb", "apb_bus",
- STGOFFSET(JH7110_STGCLK_PCIE0_APB)));
- clk_dm(JH7110_STGCLK_PCIE0_TL,
+ OFFSET(JH7110_STGCLK_PCIE0_APB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_TL),
starfive_clk_gate(priv->reg,
"pcie0_tl", "stg_axiahb",
- STGOFFSET(JH7110_STGCLK_PCIE0_TL)));
- clk_dm(JH7110_STGCLK_PCIE1_AXI,
+ OFFSET(JH7110_STGCLK_PCIE0_TL)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI),
starfive_clk_gate(priv->reg,
"pcie1_axi", "stg_axiahb",
- STGOFFSET(JH7110_STGCLK_PCIE1_AXI)));
- clk_dm(JH7110_STGCLK_PCIE1_APB,
+ OFFSET(JH7110_STGCLK_PCIE1_AXI)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_APB),
starfive_clk_gate(priv->reg,
"pcie1_apb", "apb_bus",
- STGOFFSET(JH7110_STGCLK_PCIE1_APB)));
- clk_dm(JH7110_STGCLK_PCIE1_TL,
+ OFFSET(JH7110_STGCLK_PCIE1_APB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_TL),
starfive_clk_gate(priv->reg,
"pcie1_tl", "stg_axiahb",
- STGOFFSET(JH7110_STGCLK_PCIE1_TL)));
+ OFFSET(JH7110_STGCLK_PCIE1_TL)));
return 0;
}
@@ -558,25 +562,104 @@ static int jh7110_clk_bind(struct udevice *dev)
dev_ofnode(dev), NULL);
}
-static const struct udevice_id jh7110_clk_of_match[] = {
+static int jh7110_sys_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+ if (args->args_count > 1) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args_count)
+ clk->id = JH7110_SYS_ID_TRANS(args->args[0]);
+ else
+ clk->id = 0;
+
+ return 0;
+}
+
+static int jh7110_aon_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+ if (args->args_count > 1) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args_count)
+ clk->id = JH7110_AON_ID_TRANS(args->args[0]);
+ else
+ clk->id = 0;
+
+ return 0;
+}
+
+static int jh7110_stg_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+ if (args->args_count > 1) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args_count)
+ clk->id = JH7110_STG_ID_TRANS(args->args[0]);
+ else
+ clk->id = 0;
+
+ return 0;
+}
+
+static const struct udevice_id jh7110_sys_clk_of_match[] = {
{ .compatible = "starfive,jh7110-syscrg",
.data = (ulong)&jh7110_syscrg_init
},
- { .compatible = "starfive,jh7110-stgcrg",
- .data = (ulong)&jh7110_stgcrg_init
- },
+ { }
+};
+
+JH7110_CLK_OPS(sys);
+
+U_BOOT_DRIVER(jh7110_sys_clk) = {
+ .name = "jh7110_sys_clk",
+ .id = UCLASS_CLK,
+ .of_match = jh7110_sys_clk_of_match,
+ .probe = jh7110_clk_probe,
+ .ops = &jh7110_sys_clk_ops,
+ .priv_auto = sizeof(struct jh7110_clk_priv),
+ .bind = jh7110_clk_bind,
+};
+
+static const struct udevice_id jh7110_aon_clk_of_match[] = {
{ .compatible = "starfive,jh7110-aoncrg",
.data = (ulong)&jh7110_aoncrg_init
},
{ }
};
-U_BOOT_DRIVER(jh7110_clk) = {
- .name = "jh7110_clk",
+JH7110_CLK_OPS(aon);
+
+U_BOOT_DRIVER(jh7110_aon_clk) = {
+ .name = "jh7110_aon_clk",
+ .id = UCLASS_CLK,
+ .of_match = jh7110_aon_clk_of_match,
+ .probe = jh7110_clk_probe,
+ .ops = &jh7110_aon_clk_ops,
+ .priv_auto = sizeof(struct jh7110_clk_priv),
+ .bind = jh7110_clk_bind,
+};
+
+static const struct udevice_id jh7110_stg_clk_of_match[] = {
+ { .compatible = "starfive,jh7110-stgcrg",
+ .data = (ulong)&jh7110_stgcrg_init
+ },
+ { }
+};
+
+JH7110_CLK_OPS(stg);
+
+U_BOOT_DRIVER(jh7110_stg_clk) = {
+ .name = "jh7110_stg_clk",
.id = UCLASS_CLK,
- .of_match = jh7110_clk_of_match,
+ .of_match = jh7110_stg_clk_of_match,
.probe = jh7110_clk_probe,
- .ops = &ccf_clk_ops,
+ .ops = &jh7110_stg_clk_ops,
.priv_auto = sizeof(struct jh7110_clk_priv),
- .bind = jh7110_clk_bind,
+ .bind = jh7110_clk_bind,
};
diff --git a/drivers/clk/starfive/clk.h b/drivers/clk/starfive/clk.h
new file mode 100644
index 0000000000..9d20ed0bba
--- /dev/null
+++ b/drivers/clk/starfive/clk.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#ifndef __CLK_STARFIVE_H
+#define __CLK_STARFIVE_H
+
+/* the number of fixed clocks in DTS */
+#define JH7110_EXTCLK_END 12
+
+#define _JH7110_CLK_OPS(_name) \
+static const struct clk_ops jh7110_##_name##_clk_ops = { \
+ .set_rate = ccf_clk_set_rate, \
+ .get_rate = ccf_clk_get_rate, \
+ .set_parent = ccf_clk_set_parent, \
+ .enable = ccf_clk_enable, \
+ .disable = ccf_clk_disable, \
+ .of_xlate = jh7110_##_name##_clk_of_xlate, \
+}
+
+#define JH7110_CLK_OPS(name) _JH7110_CLK_OPS(name)
+
+#endif
--
2.38.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux
2023-07-07 10:50 [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Hal Feng
` (4 preceding siblings ...)
2023-07-07 10:50 ` [PATCH v1 5/5] clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion Hal Feng
@ 2023-07-11 9:09 ` Torsten Duwe
2023-07-12 7:13 ` Hal Feng
5 siblings, 1 reply; 13+ messages in thread
From: Torsten Duwe @ 2023-07-11 9:09 UTC (permalink / raw)
To: Hal Feng
Cc: Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Conor Dooley,
Yanhong Wang, Emil Renner Berthing, Xingyu Wu, u-boot
On Fri, 7 Jul 2023 18:50:06 +0800
Hal Feng <hal.feng@starfivetech.com> wrote:
> The clock dt-bindings and DT nodes are not consistent with Linux now.
> Let's sync them with Linux, so the same dtb can work for Linux & U-Boot.
>
> To achieve this goal, the PLL clock driver is separated and some clock
> IDs conversion is needed in clock drivers.
>
> For the motivation, please see the discussion in the link below.
>
> [1] https://patchwork.kernel.org/project/linux-riscv/patch/20230512022036.97987-2-xingyu.wu@starfivetech.com/
>
> Xingyu Wu (5):
> clk: starfive: jh7110: Separate the PLL driver
> riscv: dts: jh7110: Add PLL clock controller node
> riscv: dts: jh7110: Add clock source from PLL
> dt-bindings: clock: jh7110: Modify clock id to be same with Linux
> clk: starfive: jh7110: Add of_xlate ops and macros for clock id
> conversion
For better bisectability, I would have put patch 2 first, then merged 1&3,
then merged 4&5. This way U-Boot should compile and boot after each patch
(I think, untested ;) But given the rapid development of the platform,
I'm fine with inclusion of the series as-is; as it does not affect other
targets.
I'm also wondering whether the symbolic clock number constants should be
synced, too. But that's also a minor issue, as long as they expand to yield
the same numbers.
For the series:
Reviewed-by: Torsten Duwe <duwe@suse.de>
Torsten
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux
2023-07-11 9:09 ` [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Torsten Duwe
@ 2023-07-12 7:13 ` Hal Feng
0 siblings, 0 replies; 13+ messages in thread
From: Hal Feng @ 2023-07-12 7:13 UTC (permalink / raw)
To: Torsten Duwe
Cc: Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Conor Dooley,
Yanhong Wang, Emil Renner Berthing, Xingyu Wu, u-boot
On Tue, 11 Jul 2023 11:09:23 +0200, Torsten Duwe wrote:
> On Fri, 7 Jul 2023 18:50:06 +0800
> Hal Feng <hal.feng@starfivetech.com> wrote:
>
>> The clock dt-bindings and DT nodes are not consistent with Linux now.
>> Let's sync them with Linux, so the same dtb can work for Linux & U-Boot.
>>
>> To achieve this goal, the PLL clock driver is separated and some clock
>> IDs conversion is needed in clock drivers.
>>
>> For the motivation, please see the discussion in the link below.
>>
>> [1] https://patchwork.kernel.org/project/linux-riscv/patch/20230512022036.97987-2-xingyu.wu@starfivetech.com/
>>
>> Xingyu Wu (5):
>> clk: starfive: jh7110: Separate the PLL driver
>> riscv: dts: jh7110: Add PLL clock controller node
>> riscv: dts: jh7110: Add clock source from PLL
>> dt-bindings: clock: jh7110: Modify clock id to be same with Linux
>> clk: starfive: jh7110: Add of_xlate ops and macros for clock id
>> conversion
>
> For better bisectability, I would have put patch 2 first, then merged 1&3,
> then merged 4&5. This way U-Boot should compile and boot after each patch
> (I think, untested ;) But given the rapid development of the platform,
Yes, it will get better bisectability if we do so, but it is not a good
coding style as we merge the driver changes and the DT changes in one patch.
Does someone else have any suggestions?
> I'm fine with inclusion of the series as-is; as it does not affect other
> targets.
>
> I'm also wondering whether the symbolic clock number constants should be
> synced, too. But that's also a minor issue, as long as they expand to yield
> the same numbers.
Good catch. The main difference is the definitions of PLL and STG. You can
simply compare them with the definitions in linux [1] in the link below.
[1] https://github.com/starfive-tech/linux/blob/JH7110_VisionFive2_upstream/include/dt-bindings/clock/starfive%2Cjh7110-crg.h
I will sync them in the next version.
>
> For the series:
>
> Reviewed-by: Torsten Duwe <duwe@suse.de>
Thanks for your review.
Best regards,
Hal
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 1/5] clk: starfive: jh7110: Separate the PLL driver
2023-07-07 10:50 ` [PATCH v1 1/5] clk: starfive: jh7110: Separate the PLL driver Hal Feng
@ 2023-07-24 5:14 ` Leo Liang
0 siblings, 0 replies; 13+ messages in thread
From: Leo Liang @ 2023-07-24 5:14 UTC (permalink / raw)
To: Hal Feng
Cc: Lukasz Majewski, Sean Anderson, Rick Chen, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
u-boot
On Fri, Jul 07, 2023 at 06:50:07PM +0800, Hal Feng wrote:
> From: Xingyu Wu <xingyu.wu@starfivetech.com>
>
> Drop the PLL part in SYSCRG driver and separate to be a single
> PLL driver of which the compatible is "starfive,jh7110-pll".
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> drivers/clk/starfive/clk-jh7110-pll.c | 86 +++++++++++++++++++++++++--
> drivers/clk/starfive/clk-jh7110.c | 25 +-------
> drivers/clk/starfive/clk.h | 57 ------------------
> 3 files changed, 84 insertions(+), 84 deletions(-)
> delete mode 100644 drivers/clk/starfive/clk.h
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 2/5] riscv: dts: jh7110: Add PLL clock controller node
2023-07-07 10:50 ` [PATCH v1 2/5] riscv: dts: jh7110: Add PLL clock controller node Hal Feng
@ 2023-07-24 5:15 ` Leo Liang
0 siblings, 0 replies; 13+ messages in thread
From: Leo Liang @ 2023-07-24 5:15 UTC (permalink / raw)
To: Hal Feng
Cc: Lukasz Majewski, Sean Anderson, Rick Chen, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
u-boot
On Fri, Jul 07, 2023 at 06:50:08PM +0800, Hal Feng wrote:
> From: Xingyu Wu <xingyu.wu@starfivetech.com>
>
> Add child node about PLL clock controller in sys_syscon node.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/dts/jh7110.dtsi | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 3/5] riscv: dts: jh7110: Add clock source from PLL
2023-07-07 10:50 ` [PATCH v1 3/5] riscv: dts: jh7110: Add clock source from PLL Hal Feng
@ 2023-07-24 5:15 ` Leo Liang
0 siblings, 0 replies; 13+ messages in thread
From: Leo Liang @ 2023-07-24 5:15 UTC (permalink / raw)
To: Hal Feng
Cc: Lukasz Majewski, Sean Anderson, Rick Chen, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
u-boot
On Fri, Jul 07, 2023 at 06:50:09PM +0800, Hal Feng wrote:
> From: Xingyu Wu <xingyu.wu@starfivetech.com>
>
> Change the PLL clock source from syscrg to sys_syscon child node.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 +++---
> arch/riscv/dts/jh7110-u-boot.dtsi | 1 -
> arch/riscv/dts/jh7110.dtsi | 8 ++++++--
> 3 files changed, 9 insertions(+), 6 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 4/5] dt-bindings: clock: jh7110: Modify clock id to be same with Linux
2023-07-07 10:50 ` [PATCH v1 4/5] dt-bindings: clock: jh7110: Modify clock id to be same with Linux Hal Feng
@ 2023-07-24 5:15 ` Leo Liang
0 siblings, 0 replies; 13+ messages in thread
From: Leo Liang @ 2023-07-24 5:15 UTC (permalink / raw)
To: Hal Feng
Cc: Lukasz Majewski, Sean Anderson, Rick Chen, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
u-boot
On Fri, Jul 07, 2023 at 06:50:10PM +0800, Hal Feng wrote:
> From: Xingyu Wu <xingyu.wu@starfivetech.com>
>
> The clock id needs to be changed to be consistent with Linux.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../dt-bindings/clock/starfive,jh7110-crg.h | 101 +++++++++---------
> 1 file changed, 51 insertions(+), 50 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 5/5] clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion
2023-07-07 10:50 ` [PATCH v1 5/5] clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion Hal Feng
@ 2023-07-24 5:16 ` Leo Liang
0 siblings, 0 replies; 13+ messages in thread
From: Leo Liang @ 2023-07-24 5:16 UTC (permalink / raw)
To: Hal Feng
Cc: Lukasz Majewski, Sean Anderson, Rick Chen, Torsten Duwe,
Conor Dooley, Yanhong Wang, Emil Renner Berthing, Xingyu Wu,
u-boot
On Fri, Jul 07, 2023 at 06:50:11PM +0800, Hal Feng wrote:
> From: Xingyu Wu <xingyu.wu@starfivetech.com>
>
> Modify the drivers to add of_xlate ops and transform clock id.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> drivers/clk/starfive/clk-jh7110-pll.c | 29 ++-
> drivers/clk/starfive/clk-jh7110.c | 287 +++++++++++++++++---------
> drivers/clk/starfive/clk.h | 25 +++
> 3 files changed, 235 insertions(+), 106 deletions(-)
> create mode 100644 drivers/clk/starfive/clk.h
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-07-24 5:16 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-07 10:50 [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Hal Feng
2023-07-07 10:50 ` [PATCH v1 1/5] clk: starfive: jh7110: Separate the PLL driver Hal Feng
2023-07-24 5:14 ` Leo Liang
2023-07-07 10:50 ` [PATCH v1 2/5] riscv: dts: jh7110: Add PLL clock controller node Hal Feng
2023-07-24 5:15 ` Leo Liang
2023-07-07 10:50 ` [PATCH v1 3/5] riscv: dts: jh7110: Add clock source from PLL Hal Feng
2023-07-24 5:15 ` Leo Liang
2023-07-07 10:50 ` [PATCH v1 4/5] dt-bindings: clock: jh7110: Modify clock id to be same with Linux Hal Feng
2023-07-24 5:15 ` Leo Liang
2023-07-07 10:50 ` [PATCH v1 5/5] clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion Hal Feng
2023-07-24 5:16 ` Leo Liang
2023-07-11 9:09 ` [PATCH v1 0/5] Make the clock dt-bindings and DT nodes consistent with Linux Torsten Duwe
2023-07-12 7:13 ` Hal Feng
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