* [PATCH] dt-bindings: RISC-V: Re-word the I extension binding
@ 2023-07-11 22:52 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2023-07-11 22:52 UTC (permalink / raw)
To: Conor Dooley; +Cc: linux-riscv, devicetree, Palmer Dabbelt
I'd argue this changes the definition of the I binding, as there was
more than just the counters that got split out (CSRs and fence.i at
least). We haven't released these bindings yet, so IIUC it's OK to
change the definition still.
I think this matches the original intent, or at least what the
implementation does.
Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..31ec244bd32f 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -67,13 +67,11 @@ properties:
anyOf:
# single letter extensions, in canonical order
- const: i
- description: |
- The base integer instruction set, as ratified in the 20191213
- version of the unprivileged ISA specification.
-
- This does not include Chapter 10, "Counters", which was moved into
- the Zicntr and Zihpm extensions after the ratification of the
- 20191213 version of the unprivileged specification.
+ description:
+ The base integer instruction set, as specified by the 2.2
+ version of the unprivileged ISA specification, formally known as
+ the user-level ISA. This definition of I includes various
+ extensions that were later split out.
- const: m
description:
--
2.40.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] dt-bindings: RISC-V: Re-word the I extension binding
@ 2023-07-11 22:52 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2023-07-11 22:52 UTC (permalink / raw)
To: Conor Dooley; +Cc: linux-riscv, devicetree, Palmer Dabbelt
I'd argue this changes the definition of the I binding, as there was
more than just the counters that got split out (CSRs and fence.i at
least). We haven't released these bindings yet, so IIUC it's OK to
change the definition still.
I think this matches the original intent, or at least what the
implementation does.
Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..31ec244bd32f 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -67,13 +67,11 @@ properties:
anyOf:
# single letter extensions, in canonical order
- const: i
- description: |
- The base integer instruction set, as ratified in the 20191213
- version of the unprivileged ISA specification.
-
- This does not include Chapter 10, "Counters", which was moved into
- the Zicntr and Zihpm extensions after the ratification of the
- 20191213 version of the unprivileged specification.
+ description:
+ The base integer instruction set, as specified by the 2.2
+ version of the unprivileged ISA specification, formally known as
+ the user-level ISA. This definition of I includes various
+ extensions that were later split out.
- const: m
description:
--
2.40.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] dt-bindings: RISC-V: Re-word the I extension binding
2023-07-11 22:52 ` Palmer Dabbelt
@ 2023-07-11 23:28 ` Stefan O'Rear
-1 siblings, 0 replies; 6+ messages in thread
From: Stefan O'Rear @ 2023-07-11 23:28 UTC (permalink / raw)
To: Palmer Dabbelt, Conor Dooley; +Cc: linux-riscv, devicetree
On Tue, Jul 11, 2023, at 6:52 PM, Palmer Dabbelt wrote:
> I'd argue this changes the definition of the I binding, as there was
> more than just the counters that got split out (CSRs and fence.i at
> least). We haven't released these bindings yet, so IIUC it's OK to
> change the definition still.
>
> I think this matches the original intent, or at least what the
> implementation does.
>
> Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 12 +++++-------
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml
> b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cc1f546fdbdc..31ec244bd32f 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -67,13 +67,11 @@ properties:
> anyOf:
> # single letter extensions, in canonical order
> - const: i
> - description: |
> - The base integer instruction set, as ratified in the
> 20191213
> - version of the unprivileged ISA specification.
> -
> - This does not include Chapter 10, "Counters", which was
> moved into
> - the Zicntr and Zihpm extensions after the ratification of
> the
> - 20191213 version of the unprivileged specification.
> + description:
> + The base integer instruction set, as specified by the 2.2
> + version of the unprivileged ISA specification, formally
> known as
> + the user-level ISA. This definition of I includes various
> + extensions that were later split out.
Nitpick: the 2.2 unprivileged ISA uses the pre-ratification memory model
(essentially Alpha), which is much weaker than the memory model in 20191213.
-s
>
> - const: m
> description:
> --
> 2.40.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dt-bindings: RISC-V: Re-word the I extension binding
@ 2023-07-11 23:28 ` Stefan O'Rear
0 siblings, 0 replies; 6+ messages in thread
From: Stefan O'Rear @ 2023-07-11 23:28 UTC (permalink / raw)
To: Palmer Dabbelt, Conor Dooley; +Cc: linux-riscv, devicetree
On Tue, Jul 11, 2023, at 6:52 PM, Palmer Dabbelt wrote:
> I'd argue this changes the definition of the I binding, as there was
> more than just the counters that got split out (CSRs and fence.i at
> least). We haven't released these bindings yet, so IIUC it's OK to
> change the definition still.
>
> I think this matches the original intent, or at least what the
> implementation does.
>
> Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 12 +++++-------
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml
> b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cc1f546fdbdc..31ec244bd32f 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -67,13 +67,11 @@ properties:
> anyOf:
> # single letter extensions, in canonical order
> - const: i
> - description: |
> - The base integer instruction set, as ratified in the
> 20191213
> - version of the unprivileged ISA specification.
> -
> - This does not include Chapter 10, "Counters", which was
> moved into
> - the Zicntr and Zihpm extensions after the ratification of
> the
> - 20191213 version of the unprivileged specification.
> + description:
> + The base integer instruction set, as specified by the 2.2
> + version of the unprivileged ISA specification, formally
> known as
> + the user-level ISA. This definition of I includes various
> + extensions that were later split out.
Nitpick: the 2.2 unprivileged ISA uses the pre-ratification memory model
(essentially Alpha), which is much weaker than the memory model in 20191213.
-s
>
> - const: m
> description:
> --
> 2.40.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dt-bindings: RISC-V: Re-word the I extension binding
2023-07-11 22:52 ` Palmer Dabbelt
@ 2023-07-12 15:04 ` Conor Dooley
-1 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2023-07-12 15:04 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: linux-riscv, devicetree
[-- Attachment #1: Type: text/plain, Size: 2456 bytes --]
On Tue, Jul 11, 2023 at 03:52:12PM -0700, Palmer Dabbelt wrote:
> I'd argue this changes the definition of the I binding, as there was
> more than just the counters that got split out (CSRs and fence.i at
> least). We haven't released these bindings yet, so IIUC it's OK to
> change the definition still.
>
> I think this matches the original intent, or at least what the
> implementation does.
Depends on what you consider "original". My intent with these new
bindings was to deliberately exclude from `i` things that are already in
extensions at the time of writing, so that when an platform shows up
that decided not to implement them, it does not need a special case
added.
I'm fine with doing it this way though, if that is what you want, but
what do you mean by "the implementation does"? To align the
implementation with the meaning in the current binding, would we need
to refuse harts in riscv_early_of_processor_hartid() in Linux?
>
> Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 12 +++++-------
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cc1f546fdbdc..31ec244bd32f 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -67,13 +67,11 @@ properties:
> anyOf:
> # single letter extensions, in canonical order
> - const: i
> - description: |
> - The base integer instruction set, as ratified in the 20191213
> - version of the unprivileged ISA specification.
> -
> - This does not include Chapter 10, "Counters", which was moved into
> - the Zicntr and Zihpm extensions after the ratification of the
> - 20191213 version of the unprivileged specification.
> + description:
> + The base integer instruction set, as specified by the 2.2
> + version of the unprivileged ISA specification, formally known as
> + the user-level ISA. This definition of I includes various
> + extensions that were later split out.
>
> - const: m
> description:
> --
> 2.40.1
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dt-bindings: RISC-V: Re-word the I extension binding
@ 2023-07-12 15:04 ` Conor Dooley
0 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2023-07-12 15:04 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: linux-riscv, devicetree
[-- Attachment #1.1: Type: text/plain, Size: 2456 bytes --]
On Tue, Jul 11, 2023 at 03:52:12PM -0700, Palmer Dabbelt wrote:
> I'd argue this changes the definition of the I binding, as there was
> more than just the counters that got split out (CSRs and fence.i at
> least). We haven't released these bindings yet, so IIUC it's OK to
> change the definition still.
>
> I think this matches the original intent, or at least what the
> implementation does.
Depends on what you consider "original". My intent with these new
bindings was to deliberately exclude from `i` things that are already in
extensions at the time of writing, so that when an platform shows up
that decided not to implement them, it does not need a special case
added.
I'm fine with doing it this way though, if that is what you want, but
what do you mean by "the implementation does"? To align the
implementation with the meaning in the current binding, would we need
to refuse harts in riscv_early_of_processor_hartid() in Linux?
>
> Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 12 +++++-------
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cc1f546fdbdc..31ec244bd32f 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -67,13 +67,11 @@ properties:
> anyOf:
> # single letter extensions, in canonical order
> - const: i
> - description: |
> - The base integer instruction set, as ratified in the 20191213
> - version of the unprivileged ISA specification.
> -
> - This does not include Chapter 10, "Counters", which was moved into
> - the Zicntr and Zihpm extensions after the ratification of the
> - 20191213 version of the unprivileged specification.
> + description:
> + The base integer instruction set, as specified by the 2.2
> + version of the unprivileged ISA specification, formally known as
> + the user-level ISA. This definition of I includes various
> + extensions that were later split out.
>
> - const: m
> description:
> --
> 2.40.1
>
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-07-12 15:04 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-11 22:52 [PATCH] dt-bindings: RISC-V: Re-word the I extension binding Palmer Dabbelt
2023-07-11 22:52 ` Palmer Dabbelt
2023-07-11 23:28 ` Stefan O'Rear
2023-07-11 23:28 ` Stefan O'Rear
2023-07-12 15:04 ` Conor Dooley
2023-07-12 15:04 ` Conor Dooley
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