* [PATCH 0/2] target/riscv: add missing riscv,isa strings
@ 2023-07-20 13:24 Daniel Henrique Barboza
2023-07-20 13:24 ` [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string Daniel Henrique Barboza
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Daniel Henrique Barboza @ 2023-07-20 13:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, Daniel Henrique Barboza
Hi,
Found these 2 instances while working in more 8.2 material.
I believe both are safe for freeze but I won't lose my sleep if we
decide to postpone it.
Daniel Henrique Barboza (2):
target/riscv/cpu.c: add zmmul isa string
target/riscv/cpu.c: add smepmp isa string
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
--
2.41.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string 2023-07-20 13:24 [PATCH 0/2] target/riscv: add missing riscv,isa strings Daniel Henrique Barboza @ 2023-07-20 13:24 ` Daniel Henrique Barboza 2023-07-21 1:37 ` Weiwei Li 2023-07-23 22:40 ` Alistair Francis 2023-07-20 13:24 ` [PATCH 2/2] target/riscv/cpu.c: add smepmp " Daniel Henrique Barboza 2023-07-24 2:51 ` [PATCH 0/2] target/riscv: add missing riscv,isa strings Alistair Francis 2 siblings, 2 replies; 10+ messages in thread From: Daniel Henrique Barboza @ 2023-07-20 13:24 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu, palmer, Daniel Henrique Barboza zmmul was promoted from experimental to ratified in commit 6d00ffad4e95. Add a riscv,isa string for it. Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental properties") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9339c0241d..d64ac07558 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -88,6 +88,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), + ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), -- 2.41.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string 2023-07-20 13:24 ` [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string Daniel Henrique Barboza @ 2023-07-21 1:37 ` Weiwei Li 2023-07-23 22:40 ` Alistair Francis 1 sibling, 0 replies; 10+ messages in thread From: Weiwei Li @ 2023-07-21 1:37 UTC (permalink / raw) To: Daniel Henrique Barboza, qemu-devel Cc: liweiwei, qemu-riscv, alistair.francis, bmeng, zhiwei_liu, palmer On 2023/7/20 21:24, Daniel Henrique Barboza wrote: > zmmul was promoted from experimental to ratified in commit 6d00ffad4e95. > Add a riscv,isa string for it. > > Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental properties") > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Weiwei Li > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 9339c0241d..d64ac07558 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -88,6 +88,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), > ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), > + ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), > ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), > ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), > ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string 2023-07-20 13:24 ` [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string Daniel Henrique Barboza 2023-07-21 1:37 ` Weiwei Li @ 2023-07-23 22:40 ` Alistair Francis 1 sibling, 0 replies; 10+ messages in thread From: Alistair Francis @ 2023-07-23 22:40 UTC (permalink / raw) To: Daniel Henrique Barboza Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu, palmer On Thu, Jul 20, 2023 at 11:25 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > zmmul was promoted from experimental to ratified in commit 6d00ffad4e95. > Add a riscv,isa string for it. > > Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental properties") > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 9339c0241d..d64ac07558 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -88,6 +88,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), > ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), > + ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), > ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), > ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), > ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), > -- > 2.41.0 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/2] target/riscv/cpu.c: add smepmp isa string 2023-07-20 13:24 [PATCH 0/2] target/riscv: add missing riscv,isa strings Daniel Henrique Barboza 2023-07-20 13:24 ` [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string Daniel Henrique Barboza @ 2023-07-20 13:24 ` Daniel Henrique Barboza 2023-07-21 1:37 ` Weiwei Li ` (2 more replies) 2023-07-24 2:51 ` [PATCH 0/2] target/riscv: add missing riscv,isa strings Alistair Francis 2 siblings, 3 replies; 10+ messages in thread From: Daniel Henrique Barboza @ 2023-07-20 13:24 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu, palmer, Daniel Henrique Barboza The cpu->cfg.epmp extension is still experimental, but it already has a 'smepmp' riscv,isa string. Add it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d64ac07558..8c9acadd3b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -130,6 +130,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), -- 2.41.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] target/riscv/cpu.c: add smepmp isa string 2023-07-20 13:24 ` [PATCH 2/2] target/riscv/cpu.c: add smepmp " Daniel Henrique Barboza @ 2023-07-21 1:37 ` Weiwei Li 2023-07-23 22:41 ` Alistair Francis 2023-07-24 2:49 ` Alistair Francis 2 siblings, 0 replies; 10+ messages in thread From: Weiwei Li @ 2023-07-21 1:37 UTC (permalink / raw) To: Daniel Henrique Barboza, qemu-devel Cc: liweiwei, qemu-riscv, alistair.francis, bmeng, zhiwei_liu, palmer On 2023/7/20 21:24, Daniel Henrique Barboza wrote: > The cpu->cfg.epmp extension is still experimental, but it already has a > 'smepmp' riscv,isa string. Add it. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Weiwei Li > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d64ac07558..8c9acadd3b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -130,6 +130,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] target/riscv/cpu.c: add smepmp isa string 2023-07-20 13:24 ` [PATCH 2/2] target/riscv/cpu.c: add smepmp " Daniel Henrique Barboza 2023-07-21 1:37 ` Weiwei Li @ 2023-07-23 22:41 ` Alistair Francis 2023-07-24 2:49 ` Alistair Francis 2 siblings, 0 replies; 10+ messages in thread From: Alistair Francis @ 2023-07-23 22:41 UTC (permalink / raw) To: Daniel Henrique Barboza Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu, palmer On Thu, Jul 20, 2023 at 11:26 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > The cpu->cfg.epmp extension is still experimental, but it already has a > 'smepmp' riscv,isa string. Add it. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d64ac07558..8c9acadd3b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -130,6 +130,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > -- > 2.41.0 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] target/riscv/cpu.c: add smepmp isa string 2023-07-20 13:24 ` [PATCH 2/2] target/riscv/cpu.c: add smepmp " Daniel Henrique Barboza 2023-07-21 1:37 ` Weiwei Li 2023-07-23 22:41 ` Alistair Francis @ 2023-07-24 2:49 ` Alistair Francis 2 siblings, 0 replies; 10+ messages in thread From: Alistair Francis @ 2023-07-24 2:49 UTC (permalink / raw) To: Daniel Henrique Barboza Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu, palmer On Thu, Jul 20, 2023 at 11:26 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > The cpu->cfg.epmp extension is still experimental, but it already has a > 'smepmp' riscv,isa string. Add it. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d64ac07558..8c9acadd3b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -130,6 +130,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > -- > 2.41.0 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/2] target/riscv: add missing riscv,isa strings 2023-07-20 13:24 [PATCH 0/2] target/riscv: add missing riscv,isa strings Daniel Henrique Barboza 2023-07-20 13:24 ` [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string Daniel Henrique Barboza 2023-07-20 13:24 ` [PATCH 2/2] target/riscv/cpu.c: add smepmp " Daniel Henrique Barboza @ 2023-07-24 2:51 ` Alistair Francis 2023-07-24 12:12 ` Daniel Henrique Barboza 2 siblings, 1 reply; 10+ messages in thread From: Alistair Francis @ 2023-07-24 2:51 UTC (permalink / raw) To: Daniel Henrique Barboza Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu, palmer On Thu, Jul 20, 2023 at 11:25 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Hi, > > Found these 2 instances while working in more 8.2 material. > > I believe both are safe for freeze but I won't lose my sleep if we > decide to postpone it. I wasn't going to squeeze them into the freeze > > Daniel Henrique Barboza (2): > target/riscv/cpu.c: add zmmul isa string > target/riscv/cpu.c: add smepmp isa string Do you mind rebasing :) https://github.com/alistair23/qemu/tree/riscv-to-apply.next Alistair > > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > -- > 2.41.0 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/2] target/riscv: add missing riscv,isa strings 2023-07-24 2:51 ` [PATCH 0/2] target/riscv: add missing riscv,isa strings Alistair Francis @ 2023-07-24 12:12 ` Daniel Henrique Barboza 0 siblings, 0 replies; 10+ messages in thread From: Daniel Henrique Barboza @ 2023-07-24 12:12 UTC (permalink / raw) To: Alistair Francis Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu, palmer On 7/23/23 23:51, Alistair Francis wrote: > On Thu, Jul 20, 2023 at 11:25 PM Daniel Henrique Barboza > <dbarboza@ventanamicro.com> wrote: >> >> Hi, >> >> Found these 2 instances while working in more 8.2 material. >> >> I believe both are safe for freeze but I won't lose my sleep if we >> decide to postpone it. > > I wasn't going to squeeze them into the freeze > >> >> Daniel Henrique Barboza (2): >> target/riscv/cpu.c: add zmmul isa string >> target/riscv/cpu.c: add smepmp isa string > > Do you mind rebasing :) > https://github.com/alistair23/qemu/tree/riscv-to-apply.next :) Thanks! Daniel > > Alistair > >> >> target/riscv/cpu.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> -- >> 2.41.0 >> >> ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-07-24 12:14 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-07-20 13:24 [PATCH 0/2] target/riscv: add missing riscv,isa strings Daniel Henrique Barboza 2023-07-20 13:24 ` [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string Daniel Henrique Barboza 2023-07-21 1:37 ` Weiwei Li 2023-07-23 22:40 ` Alistair Francis 2023-07-20 13:24 ` [PATCH 2/2] target/riscv/cpu.c: add smepmp " Daniel Henrique Barboza 2023-07-21 1:37 ` Weiwei Li 2023-07-23 22:41 ` Alistair Francis 2023-07-24 2:49 ` Alistair Francis 2023-07-24 2:51 ` [PATCH 0/2] target/riscv: add missing riscv,isa strings Alistair Francis 2023-07-24 12:12 ` Daniel Henrique Barboza
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