From: Tinghan Shen <tinghan.shen@mediatek.com> To: Bjorn Andersson <andersson@kernel.org>, Mathieu Poirier <mathieu.poirier@linaro.org>, Rob Herring <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, "Tinghan Shen" <tinghan.shen@mediatek.com> Cc: <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com> Subject: [PATCH v15 10/13] remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout Date: Fri, 21 Jul 2023 10:41:29 +0800 [thread overview] Message-ID: <20230721024132.6548-11-tinghan.shen@mediatek.com> (raw) In-Reply-To: <20230721024132.6548-1-tinghan.shen@mediatek.com> The MT8195 SCP core 1 watchdog timeout needs to be handled in the SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout IRQ is wired on the same IRQ entry for core 0 watchdog timeout. MT8195 SCP has a watchdog status register to identify the watchdog timeout source when IRQ triggered. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/remoteproc/mtk_common.h | 5 +++++ drivers/remoteproc/mtk_scp.c | 25 ++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 3d6b53b9f374..6d7736a031f7 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -55,6 +55,10 @@ #define MT8192_CORE0_WDT_IRQ 0x10030 #define MT8192_CORE0_WDT_CFG 0x10034 +#define MT8195_SYS_STATUS 0x4004 +#define MT8195_CORE0_WDT BIT(16) +#define MT8195_CORE1_WDT BIT(17) + #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) #define MT8195_CPU1_SRAM_PD 0x1084 @@ -63,6 +67,7 @@ #define MT8195_CORE1_SW_RSTN_CLR 0x20000 #define MT8195_CORE1_SW_RSTN_SET 0x20004 #define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_IRQ 0x20030 #define MT8195_CORE1_WDT_CFG 0x20034 #define MT8195_SEC_CTRL 0x85000 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index d1d0d7fb574c..fcd1dd9b3580 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -222,6 +222,29 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + } else { + u32 reason = readl(scp->cluster->reg_base + MT8195_SYS_STATUS); + + if (reason & MT8195_CORE0_WDT) + writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ); + + if (reason & MT8195_CORE1_WDT) + writel(1, scp->cluster->reg_base + MT8195_CORE1_WDT_IRQ); + + scp_wdt_handler(scp, reason); + } + + writel(scp_to_host, scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR); +} + static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -1250,7 +1273,7 @@ static const struct mtk_scp_of_data mt8192_of_data = { static const struct mtk_scp_of_data mt8195_of_data = { .scp_clk_get = mt8195_scp_clk_get, .scp_before_load = mt8195_scp_before_load, - .scp_irq_handler = mt8192_scp_irq_handler, + .scp_irq_handler = mt8195_scp_irq_handler, .scp_reset_assert = mt8192_scp_reset_assert, .scp_reset_deassert = mt8192_scp_reset_deassert, .scp_stop = mt8195_scp_stop, -- 2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Tinghan Shen <tinghan.shen@mediatek.com> To: Bjorn Andersson <andersson@kernel.org>, Mathieu Poirier <mathieu.poirier@linaro.org>, Rob Herring <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, "Tinghan Shen" <tinghan.shen@mediatek.com> Cc: <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com> Subject: [PATCH v15 10/13] remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout Date: Fri, 21 Jul 2023 10:41:29 +0800 [thread overview] Message-ID: <20230721024132.6548-11-tinghan.shen@mediatek.com> (raw) In-Reply-To: <20230721024132.6548-1-tinghan.shen@mediatek.com> The MT8195 SCP core 1 watchdog timeout needs to be handled in the SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout IRQ is wired on the same IRQ entry for core 0 watchdog timeout. MT8195 SCP has a watchdog status register to identify the watchdog timeout source when IRQ triggered. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/remoteproc/mtk_common.h | 5 +++++ drivers/remoteproc/mtk_scp.c | 25 ++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 3d6b53b9f374..6d7736a031f7 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -55,6 +55,10 @@ #define MT8192_CORE0_WDT_IRQ 0x10030 #define MT8192_CORE0_WDT_CFG 0x10034 +#define MT8195_SYS_STATUS 0x4004 +#define MT8195_CORE0_WDT BIT(16) +#define MT8195_CORE1_WDT BIT(17) + #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) #define MT8195_CPU1_SRAM_PD 0x1084 @@ -63,6 +67,7 @@ #define MT8195_CORE1_SW_RSTN_CLR 0x20000 #define MT8195_CORE1_SW_RSTN_SET 0x20004 #define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_IRQ 0x20030 #define MT8195_CORE1_WDT_CFG 0x20034 #define MT8195_SEC_CTRL 0x85000 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index d1d0d7fb574c..fcd1dd9b3580 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -222,6 +222,29 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + } else { + u32 reason = readl(scp->cluster->reg_base + MT8195_SYS_STATUS); + + if (reason & MT8195_CORE0_WDT) + writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ); + + if (reason & MT8195_CORE1_WDT) + writel(1, scp->cluster->reg_base + MT8195_CORE1_WDT_IRQ); + + scp_wdt_handler(scp, reason); + } + + writel(scp_to_host, scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR); +} + static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -1250,7 +1273,7 @@ static const struct mtk_scp_of_data mt8192_of_data = { static const struct mtk_scp_of_data mt8195_of_data = { .scp_clk_get = mt8195_scp_clk_get, .scp_before_load = mt8195_scp_before_load, - .scp_irq_handler = mt8192_scp_irq_handler, + .scp_irq_handler = mt8195_scp_irq_handler, .scp_reset_assert = mt8192_scp_reset_assert, .scp_reset_deassert = mt8192_scp_reset_deassert, .scp_stop = mt8195_scp_stop, -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-07-21 2:42 UTC|newest] Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-07-21 2:41 [PATCH v15 00/13] Add support for MT8195 SCP 2nd core Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-21 2:41 ` [PATCH v15 01/13] dt-bindings: remoteproc: mediatek: Improve the rpmsg subnode definition Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-21 2:41 ` [PATCH v15 02/13] arm64: dts: mediatek: Update the node name of SCP rpmsg subnode Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-21 2:41 ` [PATCH v15 03/13] dt-bindings: remoteproc: mediatek: Support MT8195 dual-core SCP Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-21 2:41 ` [PATCH v15 04/13] remoteproc: mediatek: Add MT8195 SCP core 1 operations Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-21 2:41 ` [PATCH v15 05/13] remoteproc: mediatek: Extract SCP common registers Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-25 19:56 ` Mathieu Poirier 2023-07-21 2:41 ` [PATCH v15 06/13] remoteproc: mediatek: Probe SCP cluster on single-core SCP Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-21 2:41 ` [PATCH v15 07/13] remoteproc: mediatek: Probe SCP cluster on multi-core SCP Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-25 19:59 ` Mathieu Poirier 2023-07-26 2:55 ` TingHan Shen (沈廷翰) 2023-07-21 2:41 ` [PATCH v15 08/13] remoteproc: mediatek: Remove dependency of MT8195 SCP L2TCM power control on dual-core SCP Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-25 20:05 ` Mathieu Poirier 2023-07-21 2:41 ` [PATCH v15 09/13] remoteproc: mediatek: Setup MT8195 SCP core 1 SRAM offset Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen [this message] 2023-07-21 2:41 ` [PATCH v15 10/13] remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout Tinghan Shen 2023-07-21 2:41 ` [PATCH v15 11/13] remoteproc: mediatek: Report watchdog crash to all cores Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-21 2:41 ` [PATCH v15 12/13] remoteproc: mediatek: Refine ipi handler error message Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-21 2:41 ` [PATCH v15 13/13] arm64: dts: mediatek: mt8195: Add SCP 2nd core Tinghan Shen 2023-07-21 2:41 ` Tinghan Shen 2023-07-25 20:34 ` [PATCH v15 00/13] Add support for MT8195 " Mathieu Poirier
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230721024132.6548-11-tinghan.shen@mediatek.com \ --to=tinghan.shen@mediatek.com \ --cc=Project_Global_Chrome_Upstream_Group@mediatek.com \ --cc=andersson@kernel.org \ --cc=angelogioacchino.delregno@collabora.com \ --cc=conor+dt@kernel.org \ --cc=devicetree@vger.kernel.org \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-mediatek@lists.infradead.org \ --cc=linux-remoteproc@vger.kernel.org \ --cc=mathieu.poirier@linaro.org \ --cc=matthias.bgg@gmail.com \ --cc=robh+dt@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.