[PATCH 0/3] pll-video0 notifier for v6.5+

[PATCH 0/3] pll-video0 notifier for v6.5+

[Frank Oltmanns]

Hi Icenowy,

it is my understanding that you are the original author of the following
patches are in Ondřej's 6.4 branch [1] [2] [3] but not in his 6.5
branch. I assume it is because of merge conflicts as the part about
setting the parent has already been fixed in the 6.5 release candidates.

Therefore I've removed those parts and adopted the commit message of
PATCH 2. I've removed your SoB, because I think you'd need to sign of
the revised version. Especially patch 2 has become a bit simpler and I'm
wondering if it makes sense to try to upstream the three patches now.
What do you think?

Thank you for your amazing work!

Best regards,
  Frank

[1]: https://github.com/megous/linux/commit/2cd3d57adf83e2d091baed77e1aafc01d545d123
[2]: https://github.com/megous/linux/commit/c9c7bfe22f0fefdfc1dc2ce84b452964112399d7
[3]: https://github.com/megous/linux/commit/e19ccee10a8492535b6cda1ba97cccc2074d6e65

Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
---
Icenowy Zheng (3):
      clk: sunxi-ng: add support for rate resetting notifier
      clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes
      drm/sun4i: tcon: hand over the duty to keep TCON0 clock to CCU on A64

 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
 drivers/clk/sunxi-ng/ccu_common.c     | 22 ++++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu_common.h     | 12 ++++++++++++
 drivers/gpu/drm/sun4i/sun4i_tcon.c    | 15 +++++++++++++--
 drivers/gpu/drm/sun4i/sun4i_tcon.h    |  1 +
 5 files changed, 63 insertions(+), 2 deletions(-)
---
base-commit: 1cf5c37ee3c2334a964c65e52b4e0c59b4332d7c
change-id: 20230807-a64_pll_video0_notifier-164cbc78b341

Best regards,
-- 
Frank Oltmanns <frank@oltmanns.dev>

[PATCH 0/3] pll-video0 notifier for v6.5+

[Frank Oltmanns]

Hi Icenowy,

it is my understanding that you are the original author of the following
patches are in Ondřej's 6.4 branch [1] [2] [3] but not in his 6.5
branch. I assume it is because of merge conflicts as the part about
setting the parent has already been fixed in the 6.5 release candidates.

Therefore I've removed those parts and adopted the commit message of
PATCH 2. I've removed your SoB, because I think you'd need to sign of
the revised version. Especially patch 2 has become a bit simpler and I'm
wondering if it makes sense to try to upstream the three patches now.
What do you think?

Thank you for your amazing work!

Best regards,
  Frank

[1]: https://github.com/megous/linux/commit/2cd3d57adf83e2d091baed77e1aafc01d545d123
[2]: https://github.com/megous/linux/commit/c9c7bfe22f0fefdfc1dc2ce84b452964112399d7
[3]: https://github.com/megous/linux/commit/e19ccee10a8492535b6cda1ba97cccc2074d6e65

Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
---
Icenowy Zheng (3):
      clk: sunxi-ng: add support for rate resetting notifier
      clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes
      drm/sun4i: tcon: hand over the duty to keep TCON0 clock to CCU on A64

 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
 drivers/clk/sunxi-ng/ccu_common.c     | 22 ++++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu_common.h     | 12 ++++++++++++
 drivers/gpu/drm/sun4i/sun4i_tcon.c    | 15 +++++++++++++--
 drivers/gpu/drm/sun4i/sun4i_tcon.h    |  1 +
 5 files changed, 63 insertions(+), 2 deletions(-)
---
base-commit: 1cf5c37ee3c2334a964c65e52b4e0c59b4332d7c
change-id: 20230807-a64_pll_video0_notifier-164cbc78b341

Best regards,
-- 
Frank Oltmanns <frank@oltmanns.dev>

[PATCH 1/3] clk: sunxi-ng: add support for rate resetting notifier

[Frank Oltmanns]

From: Icenowy Zheng <icenowy@aosc.io>

In some situaitons, we will want a clock rate be kept while its parent
can change, for example, to make dual-head work on A64, TCON0 clock
needs to be kept for LCD display and its parent (or grandparent)
PLL-Video0 need to be changed for HDMI display. (There's a quirk on A64
that HDMI PHY can only use PLL-Video0, not PLL-Video1).

Add a notifier helper to create such kind of rate keeping notifier by
reset the rate after the parent changed.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/clk/sunxi-ng/ccu_common.c | 22 ++++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu_common.h | 12 ++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 8d28a7a079d0..434fa46ad460 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -87,6 +87,28 @@ int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb)
 }
 EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, SUNXI_CCU);
 
+static int ccu_rate_reset_notifier_cb(struct notifier_block *nb,
+				      unsigned long event, void *data)
+{
+	struct ccu_rate_reset_nb *rate_reset = to_ccu_rate_reset_nb(nb);
+
+	if (event == PRE_RATE_CHANGE) {
+		rate_reset->saved_rate = clk_get_rate(rate_reset->target_clk);
+	} else if (event == POST_RATE_CHANGE) {
+		clk_set_rate(rate_reset->target_clk, rate_reset->saved_rate);
+	}
+
+	return NOTIFY_DONE;
+}
+
+int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb *rate_reset_nb)
+{
+	rate_reset_nb->clk_nb.notifier_call = ccu_rate_reset_notifier_cb;
+
+	return clk_notifier_register(rate_reset_nb->common->hw.clk,
+				     &rate_reset_nb->clk_nb);
+}
+
 static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev,
 			   struct device_node *node, void __iomem *reg,
 			   const struct sunxi_ccu_desc *desc)
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index fbf16c6b896d..6b0b05fae123 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -69,4 +69,16 @@ int devm_sunxi_ccu_probe(struct device *dev, void __iomem *reg,
 void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
 			const struct sunxi_ccu_desc *desc);
 
+struct ccu_rate_reset_nb {
+	struct notifier_block	clk_nb;
+	struct ccu_common	*common;
+
+	struct clk		*target_clk;
+	unsigned long		saved_rate;
+};
+
+#define to_ccu_rate_reset_nb(_nb) container_of(_nb, struct ccu_rate_reset_nb, clk_nb)
+
+int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb *rate_reset_nb);
+
 #endif /* _COMMON_H_ */

-- 
2.41.0

[PATCH 1/3] clk: sunxi-ng: add support for rate resetting notifier

[Frank Oltmanns]

From: Icenowy Zheng <icenowy@aosc.io>

In some situaitons, we will want a clock rate be kept while its parent
can change, for example, to make dual-head work on A64, TCON0 clock
needs to be kept for LCD display and its parent (or grandparent)
PLL-Video0 need to be changed for HDMI display. (There's a quirk on A64
that HDMI PHY can only use PLL-Video0, not PLL-Video1).

Add a notifier helper to create such kind of rate keeping notifier by
reset the rate after the parent changed.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/clk/sunxi-ng/ccu_common.c | 22 ++++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu_common.h | 12 ++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 8d28a7a079d0..434fa46ad460 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -87,6 +87,28 @@ int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb)
 }
 EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, SUNXI_CCU);
 
+static int ccu_rate_reset_notifier_cb(struct notifier_block *nb,
+				      unsigned long event, void *data)
+{
+	struct ccu_rate_reset_nb *rate_reset = to_ccu_rate_reset_nb(nb);
+
+	if (event == PRE_RATE_CHANGE) {
+		rate_reset->saved_rate = clk_get_rate(rate_reset->target_clk);
+	} else if (event == POST_RATE_CHANGE) {
+		clk_set_rate(rate_reset->target_clk, rate_reset->saved_rate);
+	}
+
+	return NOTIFY_DONE;
+}
+
+int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb *rate_reset_nb)
+{
+	rate_reset_nb->clk_nb.notifier_call = ccu_rate_reset_notifier_cb;
+
+	return clk_notifier_register(rate_reset_nb->common->hw.clk,
+				     &rate_reset_nb->clk_nb);
+}
+
 static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev,
 			   struct device_node *node, void __iomem *reg,
 			   const struct sunxi_ccu_desc *desc)
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index fbf16c6b896d..6b0b05fae123 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -69,4 +69,16 @@ int devm_sunxi_ccu_probe(struct device *dev, void __iomem *reg,
 void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
 			const struct sunxi_ccu_desc *desc);
 
+struct ccu_rate_reset_nb {
+	struct notifier_block	clk_nb;
+	struct ccu_common	*common;
+
+	struct clk		*target_clk;
+	unsigned long		saved_rate;
+};
+
+#define to_ccu_rate_reset_nb(_nb) container_of(_nb, struct ccu_rate_reset_nb, clk_nb)
+
+int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb *rate_reset_nb);
+
 #endif /* _COMMON_H_ */

-- 
2.41.0

[PATCH 2/3] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes

[Frank Oltmanns]

From: Icenowy Zheng <icenowy@aosc.io>

Notify TCON0 clock (and in consequence PLL-MIPI by CLK_SET_RATE_PARENT)
to reset when PLL-Video0 changes (because of HDMI PHY clk which is a
child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way we can
get clock tree to satisfy both pipelines.
---
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index ef567775fc95..93beedb0428e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
 	.bypass_index	= 1, /* index of 24 MHz oscillator */
 };
 
+/*
+ * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH, tcon0 clock will
+ * conflict with HDMI PHY clock which is on another display pipeline.
+ *
+ * Therefore, a notifier is required to restore the rate of TCON0 when the rate
+ * of PLL-Video0 changed.
+ */
+static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb = {
+	.common		= &pll_video0_clk.common,
+};
+
 static int sun50i_a64_ccu_probe(struct platform_device *pdev)
 {
 	void __iomem *reg;
@@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
 	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
 				  &sun50i_a64_cpu_nb);
 
+	/* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed */
+	sun50i_a64_pll_video0_reset_tcon0_nb.target_clk = tcon0_clk.common.hw.clk;
+	ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset_tcon0_nb);
+
 	return 0;
 }
 

-- 
2.41.0

[PATCH 2/3] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes

[Frank Oltmanns]

From: Icenowy Zheng <icenowy@aosc.io>

Notify TCON0 clock (and in consequence PLL-MIPI by CLK_SET_RATE_PARENT)
to reset when PLL-Video0 changes (because of HDMI PHY clk which is a
child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way we can
get clock tree to satisfy both pipelines.
---
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index ef567775fc95..93beedb0428e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
 	.bypass_index	= 1, /* index of 24 MHz oscillator */
 };
 
+/*
+ * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH, tcon0 clock will
+ * conflict with HDMI PHY clock which is on another display pipeline.
+ *
+ * Therefore, a notifier is required to restore the rate of TCON0 when the rate
+ * of PLL-Video0 changed.
+ */
+static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb = {
+	.common		= &pll_video0_clk.common,
+};
+
 static int sun50i_a64_ccu_probe(struct platform_device *pdev)
 {
 	void __iomem *reg;
@@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
 	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
 				  &sun50i_a64_cpu_nb);
 
+	/* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed */
+	sun50i_a64_pll_video0_reset_tcon0_nb.target_clk = tcon0_clk.common.hw.clk;
+	ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset_tcon0_nb);
+
 	return 0;
 }
 

-- 
2.41.0

[PATCH 3/3] drm/sun4i: tcon: hand over the duty to keep TCON0 clock to CCU on A64

[Frank Oltmanns]

From: Icenowy Zheng <icenowy@aosc.io>

As the A64 CCU driver has already the ability to keep TCON0 clock stable
when HDMI changes its parent's clock, do not protect TCON0 clock on A64
in the TCON driver to allow PLL-Video0 gets changed by HDMI (the CCU
will then restore the TCON0 clock rate).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 15 +++++++++++++--
 drivers/gpu/drm/sun4i/sun4i_tcon.h |  1 +
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c44d5f3350d1..6f2d544c5f29 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -110,9 +110,11 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
 
 	if (enabled) {
 		clk_prepare_enable(clk);
-		clk_rate_exclusive_get(clk);
+		if (!tcon->quirks->clk_kept_by_ccu)
+			clk_rate_exclusive_get(clk);
 	} else {
-		clk_rate_exclusive_put(clk);
+		if (!tcon->quirks->clk_kept_by_ccu)
+			clk_rate_exclusive_put(clk);
 		clk_disable_unprepare(clk);
 	}
 }
@@ -1562,6 +1564,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
 	.supports_lvds		= true,
 };
 
+static const struct sun4i_tcon_quirks sun50i_a64_lcd_quirks = {
+	.supports_lvds		= true,
+	.has_channel_0		= true,
+	.clk_kept_by_ccu	= true,
+	.dclk_min_div		= 1,
+	.setup_lvds_phy		= sun6i_tcon_setup_lvds_phy,
+};
+
 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
 	.supports_lvds		= true,
 	.has_channel_0		= true,
@@ -1620,6 +1630,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
 	{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
 	{ .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
 	{ .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
+	{ .compatible = "allwinner,sun50i-a64-tcon-lcd", .data = &sun50i_a64_lcd_quirks },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 864d70b9d242..7ba3df9e27df 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -250,6 +250,7 @@ struct sun4i_tcon_quirks {
 	bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
 	bool	supports_lvds;   /* Does the TCON support an LVDS output? */
 	bool	polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
+	bool	clk_kept_by_ccu; /* On A64 we rely on CCU to keep TCON0 clock stable */
 	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */
 
 	/* callback to handle tcon muxing options */

-- 
2.41.0

[PATCH 3/3] drm/sun4i: tcon: hand over the duty to keep TCON0 clock to CCU on A64

[Frank Oltmanns]

From: Icenowy Zheng <icenowy@aosc.io>

As the A64 CCU driver has already the ability to keep TCON0 clock stable
when HDMI changes its parent's clock, do not protect TCON0 clock on A64
in the TCON driver to allow PLL-Video0 gets changed by HDMI (the CCU
will then restore the TCON0 clock rate).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 15 +++++++++++++--
 drivers/gpu/drm/sun4i/sun4i_tcon.h |  1 +
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c44d5f3350d1..6f2d544c5f29 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -110,9 +110,11 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
 
 	if (enabled) {
 		clk_prepare_enable(clk);
-		clk_rate_exclusive_get(clk);
+		if (!tcon->quirks->clk_kept_by_ccu)
+			clk_rate_exclusive_get(clk);
 	} else {
-		clk_rate_exclusive_put(clk);
+		if (!tcon->quirks->clk_kept_by_ccu)
+			clk_rate_exclusive_put(clk);
 		clk_disable_unprepare(clk);
 	}
 }
@@ -1562,6 +1564,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
 	.supports_lvds		= true,
 };
 
+static const struct sun4i_tcon_quirks sun50i_a64_lcd_quirks = {
+	.supports_lvds		= true,
+	.has_channel_0		= true,
+	.clk_kept_by_ccu	= true,
+	.dclk_min_div		= 1,
+	.setup_lvds_phy		= sun6i_tcon_setup_lvds_phy,
+};
+
 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
 	.supports_lvds		= true,
 	.has_channel_0		= true,
@@ -1620,6 +1630,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
 	{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
 	{ .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
 	{ .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
+	{ .compatible = "allwinner,sun50i-a64-tcon-lcd", .data = &sun50i_a64_lcd_quirks },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 864d70b9d242..7ba3df9e27df 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -250,6 +250,7 @@ struct sun4i_tcon_quirks {
 	bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
 	bool	supports_lvds;   /* Does the TCON support an LVDS output? */
 	bool	polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
+	bool	clk_kept_by_ccu; /* On A64 we rely on CCU to keep TCON0 clock stable */
 	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */
 
 	/* callback to handle tcon muxing options */

-- 
2.41.0

Re: [PATCH 1/3] clk: sunxi-ng: add support for rate resetting notifier

[Icenowy Zheng]

在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
> From: Icenowy Zheng <icenowy@aosc.io>
> 
> In some situaitons, we will want a clock rate be kept while its
> parent
> can change, for example, to make dual-head work on A64, TCON0 clock
> needs to be kept for LCD display and its parent (or grandparent)
> PLL-Video0 need to be changed for HDMI display. (There's a quirk on
> A64
> that HDMI PHY can only use PLL-Video0, not PLL-Video1).
> 
> Add a notifier helper to create such kind of rate keeping notifier by
> reset the rate after the parent changed.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  drivers/clk/sunxi-ng/ccu_common.c | 22 ++++++++++++++++++++++
>  drivers/clk/sunxi-ng/ccu_common.h | 12 ++++++++++++
>  2 files changed, 34 insertions(+)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-
> ng/ccu_common.c
> index 8d28a7a079d0..434fa46ad460 100644
> --- a/drivers/clk/sunxi-ng/ccu_common.c
> +++ b/drivers/clk/sunxi-ng/ccu_common.c
> @@ -87,6 +87,28 @@ int ccu_pll_notifier_register(struct ccu_pll_nb
> *pll_nb)
>  }
>  EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, SUNXI_CCU);
>  
> +static int ccu_rate_reset_notifier_cb(struct notifier_block *nb,
> +                                     unsigned long event, void
> *data)
> +{
> +       struct ccu_rate_reset_nb *rate_reset =
> to_ccu_rate_reset_nb(nb);
> +
> +       if (event == PRE_RATE_CHANGE) {
> +               rate_reset->saved_rate = clk_get_rate(rate_reset-
> >target_clk);

In fact I think we should have a better way to save the intended clock
rate ;-)

> +       } else if (event == POST_RATE_CHANGE) {
> +               clk_set_rate(rate_reset->target_clk, rate_reset-
> >saved_rate);
> +       }
> +
> +       return NOTIFY_DONE;
> +}
> +
> +int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb
> *rate_reset_nb)
> +{
> +       rate_reset_nb->clk_nb.notifier_call =
> ccu_rate_reset_notifier_cb;
> +
> +       return clk_notifier_register(rate_reset_nb->common->hw.clk,
> +                                    &rate_reset_nb->clk_nb);
> +}
> +
>  static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device
> *dev,
>                            struct device_node *node, void __iomem
> *reg,
>                            const struct sunxi_ccu_desc *desc)
> diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-
> ng/ccu_common.h
> index fbf16c6b896d..6b0b05fae123 100644
> --- a/drivers/clk/sunxi-ng/ccu_common.h
> +++ b/drivers/clk/sunxi-ng/ccu_common.h
> @@ -69,4 +69,16 @@ int devm_sunxi_ccu_probe(struct device *dev, void
> __iomem *reg,
>  void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
>                         const struct sunxi_ccu_desc *desc);
>  
> +struct ccu_rate_reset_nb {
> +       struct notifier_block   clk_nb;
> +       struct ccu_common       *common;
> +
> +       struct clk              *target_clk;
> +       unsigned long           saved_rate;
> +};
> +
> +#define to_ccu_rate_reset_nb(_nb) container_of(_nb, struct
> ccu_rate_reset_nb, clk_nb)
> +
> +int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb
> *rate_reset_nb);
> +
>  #endif /* _COMMON_H_ */
> 

Re: [PATCH 1/3] clk: sunxi-ng: add support for rate resetting notifier

[Icenowy Zheng]

在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
> From: Icenowy Zheng <icenowy@aosc.io>
> 
> In some situaitons, we will want a clock rate be kept while its
> parent
> can change, for example, to make dual-head work on A64, TCON0 clock
> needs to be kept for LCD display and its parent (or grandparent)
> PLL-Video0 need to be changed for HDMI display. (There's a quirk on
> A64
> that HDMI PHY can only use PLL-Video0, not PLL-Video1).
> 
> Add a notifier helper to create such kind of rate keeping notifier by
> reset the rate after the parent changed.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  drivers/clk/sunxi-ng/ccu_common.c | 22 ++++++++++++++++++++++
>  drivers/clk/sunxi-ng/ccu_common.h | 12 ++++++++++++
>  2 files changed, 34 insertions(+)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-
> ng/ccu_common.c
> index 8d28a7a079d0..434fa46ad460 100644
> --- a/drivers/clk/sunxi-ng/ccu_common.c
> +++ b/drivers/clk/sunxi-ng/ccu_common.c
> @@ -87,6 +87,28 @@ int ccu_pll_notifier_register(struct ccu_pll_nb
> *pll_nb)
>  }
>  EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, SUNXI_CCU);
>  
> +static int ccu_rate_reset_notifier_cb(struct notifier_block *nb,
> +                                     unsigned long event, void
> *data)
> +{
> +       struct ccu_rate_reset_nb *rate_reset =
> to_ccu_rate_reset_nb(nb);
> +
> +       if (event == PRE_RATE_CHANGE) {
> +               rate_reset->saved_rate = clk_get_rate(rate_reset-
> >target_clk);

In fact I think we should have a better way to save the intended clock
rate ;-)

> +       } else if (event == POST_RATE_CHANGE) {
> +               clk_set_rate(rate_reset->target_clk, rate_reset-
> >saved_rate);
> +       }
> +
> +       return NOTIFY_DONE;
> +}
> +
> +int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb
> *rate_reset_nb)
> +{
> +       rate_reset_nb->clk_nb.notifier_call =
> ccu_rate_reset_notifier_cb;
> +
> +       return clk_notifier_register(rate_reset_nb->common->hw.clk,
> +                                    &rate_reset_nb->clk_nb);
> +}
> +
>  static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device
> *dev,
>                            struct device_node *node, void __iomem
> *reg,
>                            const struct sunxi_ccu_desc *desc)
> diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-
> ng/ccu_common.h
> index fbf16c6b896d..6b0b05fae123 100644
> --- a/drivers/clk/sunxi-ng/ccu_common.h
> +++ b/drivers/clk/sunxi-ng/ccu_common.h
> @@ -69,4 +69,16 @@ int devm_sunxi_ccu_probe(struct device *dev, void
> __iomem *reg,
>  void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
>                         const struct sunxi_ccu_desc *desc);
>  
> +struct ccu_rate_reset_nb {
> +       struct notifier_block   clk_nb;
> +       struct ccu_common       *common;
> +
> +       struct clk              *target_clk;
> +       unsigned long           saved_rate;
> +};
> +
> +#define to_ccu_rate_reset_nb(_nb) container_of(_nb, struct
> ccu_rate_reset_nb, clk_nb)
> +
> +int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb
> *rate_reset_nb);
> +
>  #endif /* _COMMON_H_ */
> 

Re: [PATCH 2/3] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes

[Icenowy Zheng]

在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
> From: Icenowy Zheng <icenowy@aosc.io>
> 
> Notify TCON0 clock (and in consequence PLL-MIPI by
> CLK_SET_RATE_PARENT)
> to reset when PLL-Video0 changes (because of HDMI PHY clk which is a
> child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way we
> can
> get clock tree to satisfy both pipelines.

Well for fixing one's patch that contains SoB, use the following
format:

Signed-off-by: A <a@a.local>
[B: fixed something]
Signed-off-by: B <b@b.local>

> ---
>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> index ef567775fc95..93beedb0428e 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> @@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
>         .bypass_index   = 1, /* index of 24 MHz oscillator */
>  };
>  
> +/*
> + * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH, tcon0
> clock will
> + * conflict with HDMI PHY clock which is on another display
> pipeline.
> + *
> + * Therefore, a notifier is required to restore the rate of TCON0
> when the rate
> + * of PLL-Video0 changed.
> + */
> +static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb
> = {
> +       .common         = &pll_video0_clk.common,
> +};
> +
>  static int sun50i_a64_ccu_probe(struct platform_device *pdev)
>  {
>         void __iomem *reg;
> @@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct
> platform_device *pdev)
>         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
>                                   &sun50i_a64_cpu_nb);
>  
> +       /* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed
> */
> +       sun50i_a64_pll_video0_reset_tcon0_nb.target_clk =
> tcon0_clk.common.hw.clk;
> +       ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset
> _tcon0_nb);
> +
>         return 0;
>  }
>  
> 

Re: [PATCH 2/3] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes

[Icenowy Zheng]

在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
> From: Icenowy Zheng <icenowy@aosc.io>
> 
> Notify TCON0 clock (and in consequence PLL-MIPI by
> CLK_SET_RATE_PARENT)
> to reset when PLL-Video0 changes (because of HDMI PHY clk which is a
> child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way we
> can
> get clock tree to satisfy both pipelines.

Well for fixing one's patch that contains SoB, use the following
format:

Signed-off-by: A <a@a.local>
[B: fixed something]
Signed-off-by: B <b@b.local>

> ---
>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> index ef567775fc95..93beedb0428e 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> @@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
>         .bypass_index   = 1, /* index of 24 MHz oscillator */
>  };
>  
> +/*
> + * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH, tcon0
> clock will
> + * conflict with HDMI PHY clock which is on another display
> pipeline.
> + *
> + * Therefore, a notifier is required to restore the rate of TCON0
> when the rate
> + * of PLL-Video0 changed.
> + */
> +static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb
> = {
> +       .common         = &pll_video0_clk.common,
> +};
> +
>  static int sun50i_a64_ccu_probe(struct platform_device *pdev)
>  {
>         void __iomem *reg;
> @@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct
> platform_device *pdev)
>         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
>                                   &sun50i_a64_cpu_nb);
>  
> +       /* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed
> */
> +       sun50i_a64_pll_video0_reset_tcon0_nb.target_clk =
> tcon0_clk.common.hw.clk;
> +       ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset
> _tcon0_nb);
> +
>         return 0;
>  }
>  
> 

Re: [PATCH 2/3] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes

[Frank Oltmanns]

On 2023-08-07 at 17:43:52 +0800, Icenowy Zheng <uwu@icenowy.me> wrote:
> 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
>> From: Icenowy Zheng <icenowy@aosc.io>
>>
>> Notify TCON0 clock (and in consequence PLL-MIPI by
>> CLK_SET_RATE_PARENT)
>> to reset when PLL-Video0 changes (because of HDMI PHY clk which is a
>> child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way we
>> can
>> get clock tree to satisfy both pipelines.
>
> Well for fixing one's patch that contains SoB, use the following
> format:
>
> Signed-off-by: A <a@a.local>
> [B: fixed something]
> Signed-off-by: B <b@b.local>

Ah, okay. Will do. But I keep A in the "From: " line, correct?

Thanks,
  Frank

>> ---
>>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
>>  1 file changed, 15 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> index ef567775fc95..93beedb0428e 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> @@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
>>         .bypass_index   = 1, /* index of 24 MHz oscillator */
>>  };
>>  
>> +/*
>> + * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH, tcon0
>> clock will
>> + * conflict with HDMI PHY clock which is on another display
>> pipeline.
>> + *
>> + * Therefore, a notifier is required to restore the rate of TCON0
>> when the rate
>> + * of PLL-Video0 changed.
>> + */
>> +static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb
>> = {
>> +       .common         = &pll_video0_clk.common,
>> +};
>> +
>>  static int sun50i_a64_ccu_probe(struct platform_device *pdev)
>>  {
>>         void __iomem *reg;
>> @@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct
>> platform_device *pdev)
>>         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
>>                                   &sun50i_a64_cpu_nb);
>>  
>> +       /* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed
>> */
>> +       sun50i_a64_pll_video0_reset_tcon0_nb.target_clk =
>> tcon0_clk.common.hw.clk;
>> +       ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset
>> _tcon0_nb);
>> +
>>         return 0;
>>  }
>>  
>>

Re: [PATCH 2/3] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes

[Frank Oltmanns]

On 2023-08-07 at 17:43:52 +0800, Icenowy Zheng <uwu@icenowy.me> wrote:
> 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
>> From: Icenowy Zheng <icenowy@aosc.io>
>>
>> Notify TCON0 clock (and in consequence PLL-MIPI by
>> CLK_SET_RATE_PARENT)
>> to reset when PLL-Video0 changes (because of HDMI PHY clk which is a
>> child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way we
>> can
>> get clock tree to satisfy both pipelines.
>
> Well for fixing one's patch that contains SoB, use the following
> format:
>
> Signed-off-by: A <a@a.local>
> [B: fixed something]
> Signed-off-by: B <b@b.local>

Ah, okay. Will do. But I keep A in the "From: " line, correct?

Thanks,
  Frank

>> ---
>>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
>>  1 file changed, 15 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> index ef567775fc95..93beedb0428e 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> @@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
>>         .bypass_index   = 1, /* index of 24 MHz oscillator */
>>  };
>>  
>> +/*
>> + * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH, tcon0
>> clock will
>> + * conflict with HDMI PHY clock which is on another display
>> pipeline.
>> + *
>> + * Therefore, a notifier is required to restore the rate of TCON0
>> when the rate
>> + * of PLL-Video0 changed.
>> + */
>> +static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb
>> = {
>> +       .common         = &pll_video0_clk.common,
>> +};
>> +
>>  static int sun50i_a64_ccu_probe(struct platform_device *pdev)
>>  {
>>         void __iomem *reg;
>> @@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct
>> platform_device *pdev)
>>         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
>>                                   &sun50i_a64_cpu_nb);
>>  
>> +       /* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed
>> */
>> +       sun50i_a64_pll_video0_reset_tcon0_nb.target_clk =
>> tcon0_clk.common.hw.clk;
>> +       ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset
>> _tcon0_nb);
>> +
>>         return 0;
>>  }
>>  
>>

Re: [PATCH 1/3] clk: sunxi-ng: add support for rate resetting notifier

[Frank Oltmanns]

On 2023-08-07 at 17:42:22 +0800, Icenowy Zheng <uwu@icenowy.me> wrote:
> 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
>> From: Icenowy Zheng <icenowy@aosc.io>
>>
>> In some situaitons, we will want a clock rate be kept while its
>> parent
>> can change, for example, to make dual-head work on A64, TCON0 clock
>> needs to be kept for LCD display and its parent (or grandparent)
>> PLL-Video0 need to be changed for HDMI display. (There's a quirk on
>> A64
>> that HDMI PHY can only use PLL-Video0, not PLL-Video1).
>>
>> Add a notifier helper to create such kind of rate keeping notifier by
>> reset the rate after the parent changed.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>>  drivers/clk/sunxi-ng/ccu_common.c | 22 ++++++++++++++++++++++
>>  drivers/clk/sunxi-ng/ccu_common.h | 12 ++++++++++++
>>  2 files changed, 34 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-
>> ng/ccu_common.c
>> index 8d28a7a079d0..434fa46ad460 100644
>> --- a/drivers/clk/sunxi-ng/ccu_common.c
>> +++ b/drivers/clk/sunxi-ng/ccu_common.c
>> @@ -87,6 +87,28 @@ int ccu_pll_notifier_register(struct ccu_pll_nb
>> *pll_nb)
>>  }
>>  EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, SUNXI_CCU);
>>  
>> +static int ccu_rate_reset_notifier_cb(struct notifier_block *nb,
>> +                                     unsigned long event, void
>> *data)
>> +{
>> +       struct ccu_rate_reset_nb *rate_reset =
>> to_ccu_rate_reset_nb(nb);
>> +
>> +       if (event == PRE_RATE_CHANGE) {
>> +               rate_reset->saved_rate = clk_get_rate(rate_reset-
>> >target_clk);
>
> In fact I think we should have a better way to save the intended clock
> rate ;-)
>

Are you referring to struct clk_core's clk_req member [1]? Maxime Ripard
also mentioned it to me [2]? Or do you have something else in mind?

Note that I have a patchset on the way [3], that will improve rate
selection for pll-video0 and its descendants. I'll double-check if that
improves the situation in a way so that the clk_get_rate() might be good
enough.

Thanks,
  Frank

[1]: https://elixir.bootlin.com/linux/latest/source/drivers/clk/clk.c#L68
[2]: https://lore.kernel.org/linux-clk/xcgmqvdoip53yao4sfoznnppauhmsmdablwoewh43zjv3bhidp@d7pxqohxydve/
[3]: https://lore.kernel.org/linux-clk/20230806-pll-mipi_set_rate_parent-v5-0-db4f5ca33fc3@oltmanns.dev/

>
>> +       } else if (event == POST_RATE_CHANGE) {
>> +               clk_set_rate(rate_reset->target_clk, rate_reset-
>> >saved_rate);
>> +       }
>> +
>> +       return NOTIFY_DONE;
>> +}
>> +
>> +int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb
>> *rate_reset_nb)
>> +{
>> +       rate_reset_nb->clk_nb.notifier_call =
>> ccu_rate_reset_notifier_cb;
>> +
>> +       return clk_notifier_register(rate_reset_nb->common->hw.clk,
>> +                                    &rate_reset_nb->clk_nb);
>> +}
>> +
>>  static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device
>> *dev,
>>                            struct device_node *node, void __iomem
>> *reg,
>>                            const struct sunxi_ccu_desc *desc)
>> diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-
>> ng/ccu_common.h
>> index fbf16c6b896d..6b0b05fae123 100644
>> --- a/drivers/clk/sunxi-ng/ccu_common.h
>> +++ b/drivers/clk/sunxi-ng/ccu_common.h
>> @@ -69,4 +69,16 @@ int devm_sunxi_ccu_probe(struct device *dev, void
>> __iomem *reg,
>>  void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
>>                         const struct sunxi_ccu_desc *desc);
>>  
>> +struct ccu_rate_reset_nb {
>> +       struct notifier_block   clk_nb;
>> +       struct ccu_common       *common;
>> +
>> +       struct clk              *target_clk;
>> +       unsigned long           saved_rate;
>> +};
>> +
>> +#define to_ccu_rate_reset_nb(_nb) container_of(_nb, struct
>> ccu_rate_reset_nb, clk_nb)
>> +
>> +int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb
>> *rate_reset_nb);
>> +
>>  #endif /* _COMMON_H_ */
>>

Re: [PATCH 1/3] clk: sunxi-ng: add support for rate resetting notifier

[Frank Oltmanns]

On 2023-08-07 at 17:42:22 +0800, Icenowy Zheng <uwu@icenowy.me> wrote:
> 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
>> From: Icenowy Zheng <icenowy@aosc.io>
>>
>> In some situaitons, we will want a clock rate be kept while its
>> parent
>> can change, for example, to make dual-head work on A64, TCON0 clock
>> needs to be kept for LCD display and its parent (or grandparent)
>> PLL-Video0 need to be changed for HDMI display. (There's a quirk on
>> A64
>> that HDMI PHY can only use PLL-Video0, not PLL-Video1).
>>
>> Add a notifier helper to create such kind of rate keeping notifier by
>> reset the rate after the parent changed.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>>  drivers/clk/sunxi-ng/ccu_common.c | 22 ++++++++++++++++++++++
>>  drivers/clk/sunxi-ng/ccu_common.h | 12 ++++++++++++
>>  2 files changed, 34 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-
>> ng/ccu_common.c
>> index 8d28a7a079d0..434fa46ad460 100644
>> --- a/drivers/clk/sunxi-ng/ccu_common.c
>> +++ b/drivers/clk/sunxi-ng/ccu_common.c
>> @@ -87,6 +87,28 @@ int ccu_pll_notifier_register(struct ccu_pll_nb
>> *pll_nb)
>>  }
>>  EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, SUNXI_CCU);
>>  
>> +static int ccu_rate_reset_notifier_cb(struct notifier_block *nb,
>> +                                     unsigned long event, void
>> *data)
>> +{
>> +       struct ccu_rate_reset_nb *rate_reset =
>> to_ccu_rate_reset_nb(nb);
>> +
>> +       if (event == PRE_RATE_CHANGE) {
>> +               rate_reset->saved_rate = clk_get_rate(rate_reset-
>> >target_clk);
>
> In fact I think we should have a better way to save the intended clock
> rate ;-)
>

Are you referring to struct clk_core's clk_req member [1]? Maxime Ripard
also mentioned it to me [2]? Or do you have something else in mind?

Note that I have a patchset on the way [3], that will improve rate
selection for pll-video0 and its descendants. I'll double-check if that
improves the situation in a way so that the clk_get_rate() might be good
enough.

Thanks,
  Frank

[1]: https://elixir.bootlin.com/linux/latest/source/drivers/clk/clk.c#L68
[2]: https://lore.kernel.org/linux-clk/xcgmqvdoip53yao4sfoznnppauhmsmdablwoewh43zjv3bhidp@d7pxqohxydve/
[3]: https://lore.kernel.org/linux-clk/20230806-pll-mipi_set_rate_parent-v5-0-db4f5ca33fc3@oltmanns.dev/

>
>> +       } else if (event == POST_RATE_CHANGE) {
>> +               clk_set_rate(rate_reset->target_clk, rate_reset-
>> >saved_rate);
>> +       }
>> +
>> +       return NOTIFY_DONE;
>> +}
>> +
>> +int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb
>> *rate_reset_nb)
>> +{
>> +       rate_reset_nb->clk_nb.notifier_call =
>> ccu_rate_reset_notifier_cb;
>> +
>> +       return clk_notifier_register(rate_reset_nb->common->hw.clk,
>> +                                    &rate_reset_nb->clk_nb);
>> +}
>> +
>>  static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device
>> *dev,
>>                            struct device_node *node, void __iomem
>> *reg,
>>                            const struct sunxi_ccu_desc *desc)
>> diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-
>> ng/ccu_common.h
>> index fbf16c6b896d..6b0b05fae123 100644
>> --- a/drivers/clk/sunxi-ng/ccu_common.h
>> +++ b/drivers/clk/sunxi-ng/ccu_common.h
>> @@ -69,4 +69,16 @@ int devm_sunxi_ccu_probe(struct device *dev, void
>> __iomem *reg,
>>  void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
>>                         const struct sunxi_ccu_desc *desc);
>>  
>> +struct ccu_rate_reset_nb {
>> +       struct notifier_block   clk_nb;
>> +       struct ccu_common       *common;
>> +
>> +       struct clk              *target_clk;
>> +       unsigned long           saved_rate;
>> +};
>> +
>> +#define to_ccu_rate_reset_nb(_nb) container_of(_nb, struct
>> ccu_rate_reset_nb, clk_nb)
>> +
>> +int ccu_rate_reset_notifier_register(struct ccu_rate_reset_nb
>> *rate_reset_nb);
>> +
>>  #endif /* _COMMON_H_ */
>>

Re: [PATCH 2/3] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes

[Icenowy Zheng]

在 2023-08-07星期一的 11:48 +0200，Frank Oltmanns写道：
> 
> On 2023-08-07 at 17:43:52 +0800, Icenowy Zheng <uwu@icenowy.me>
> wrote:
> > 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
> > > From: Icenowy Zheng <icenowy@aosc.io>
> > > 
> > > Notify TCON0 clock (and in consequence PLL-MIPI by
> > > CLK_SET_RATE_PARENT)
> > > to reset when PLL-Video0 changes (because of HDMI PHY clk which
> > > is a
> > > child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way
> > > we
> > > can
> > > get clock tree to satisfy both pipelines.
> > 
> > Well for fixing one's patch that contains SoB, use the following
> > format:
> > 
> > Signed-off-by: A <a@a.local>
> > [B: fixed something]
> > Signed-off-by: B <b@b.local>
> 
> Ah, okay. Will do. But I keep A in the "From: " line, correct?

Yes.

> 
> Thanks,
>   Frank
> 
> > > ---
> > >  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
> > >  1 file changed, 15 insertions(+)
> > > 
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > index ef567775fc95..93beedb0428e 100644
> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > @@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb =
> > > {
> > >         .bypass_index   = 1, /* index of 24 MHz oscillator */
> > >  };
> > >  
> > > +/*
> > > + * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH,
> > > tcon0
> > > clock will
> > > + * conflict with HDMI PHY clock which is on another display
> > > pipeline.
> > > + *
> > > + * Therefore, a notifier is required to restore the rate of
> > > TCON0
> > > when the rate
> > > + * of PLL-Video0 changed.
> > > + */
> > > +static struct ccu_rate_reset_nb
> > > sun50i_a64_pll_video0_reset_tcon0_nb
> > > = {
> > > +       .common         = &pll_video0_clk.common,
> > > +};
> > > +
> > >  static int sun50i_a64_ccu_probe(struct platform_device *pdev)
> > >  {
> > >         void __iomem *reg;
> > > @@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct
> > > platform_device *pdev)
> > >         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
> > >                                   &sun50i_a64_cpu_nb);
> > >  
> > > +       /* Reset the rate of TCON0 clock when PLL-VIDEO0 is
> > > changed
> > > */
> > > +       sun50i_a64_pll_video0_reset_tcon0_nb.target_clk =
> > > tcon0_clk.common.hw.clk;
> > > +       ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_r
> > > eset
> > > _tcon0_nb);
> > > +
> > >         return 0;
> > >  }
> > >  
> > > 

Re: [PATCH 2/3] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes

[Icenowy Zheng]

在 2023-08-07星期一的 11:48 +0200，Frank Oltmanns写道：
> 
> On 2023-08-07 at 17:43:52 +0800, Icenowy Zheng <uwu@icenowy.me>
> wrote:
> > 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
> > > From: Icenowy Zheng <icenowy@aosc.io>
> > > 
> > > Notify TCON0 clock (and in consequence PLL-MIPI by
> > > CLK_SET_RATE_PARENT)
> > > to reset when PLL-Video0 changes (because of HDMI PHY clk which
> > > is a
> > > child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way
> > > we
> > > can
> > > get clock tree to satisfy both pipelines.
> > 
> > Well for fixing one's patch that contains SoB, use the following
> > format:
> > 
> > Signed-off-by: A <a@a.local>
> > [B: fixed something]
> > Signed-off-by: B <b@b.local>
> 
> Ah, okay. Will do. But I keep A in the "From: " line, correct?

Yes.

> 
> Thanks,
>   Frank
> 
> > > ---
> > >  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
> > >  1 file changed, 15 insertions(+)
> > > 
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > index ef567775fc95..93beedb0428e 100644
> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > @@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb =
> > > {
> > >         .bypass_index   = 1, /* index of 24 MHz oscillator */
> > >  };
> > >  
> > > +/*
> > > + * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH,
> > > tcon0
> > > clock will
> > > + * conflict with HDMI PHY clock which is on another display
> > > pipeline.
> > > + *
> > > + * Therefore, a notifier is required to restore the rate of
> > > TCON0
> > > when the rate
> > > + * of PLL-Video0 changed.
> > > + */
> > > +static struct ccu_rate_reset_nb
> > > sun50i_a64_pll_video0_reset_tcon0_nb
> > > = {
> > > +       .common         = &pll_video0_clk.common,
> > > +};
> > > +
> > >  static int sun50i_a64_ccu_probe(struct platform_device *pdev)
> > >  {
> > >         void __iomem *reg;
> > > @@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct
> > > platform_device *pdev)
> > >         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
> > >                                   &sun50i_a64_cpu_nb);
> > >  
> > > +       /* Reset the rate of TCON0 clock when PLL-VIDEO0 is
> > > changed
> > > */
> > > +       sun50i_a64_pll_video0_reset_tcon0_nb.target_clk =
> > > tcon0_clk.common.hw.clk;
> > > +       ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_r
> > > eset
> > > _tcon0_nb);
> > > +
> > >         return 0;
> > >  }
> > >  
> > > 

Re: [PATCH 0/3] pll-video0 notifier for v6.5+

[Chen-Yu Tsai]

On Mon, Aug 7, 2023 at 5:36 PM Frank Oltmanns <frank@oltmanns.dev> wrote:
>
> Hi Icenowy,
>
> it is my understanding that you are the original author of the following
> patches are in Ondřej's 6.4 branch [1] [2] [3] but not in his 6.5
> branch. I assume it is because of merge conflicts as the part about
> setting the parent has already been fixed in the 6.5 release candidates.
>
> Therefore I've removed those parts and adopted the commit message of
> PATCH 2. I've removed your SoB, because I think you'd need to sign of
> the revised version. Especially patch 2 has become a bit simpler and I'm
> wondering if it makes sense to try to upstream the three patches now.
> What do you think?
>
> Thank you for your amazing work!
>
> Best regards,
>   Frank

Please send to all maintainers and relevant mailing lists (as given
by get_maintainers.pl).


> [1]: https://github.com/megous/linux/commit/2cd3d57adf83e2d091baed77e1aafc01d545d123
> [2]: https://github.com/megous/linux/commit/c9c7bfe22f0fefdfc1dc2ce84b452964112399d7
> [3]: https://github.com/megous/linux/commit/e19ccee10a8492535b6cda1ba97cccc2074d6e65
>
> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
> ---
> Icenowy Zheng (3):
>       clk: sunxi-ng: add support for rate resetting notifier
>       clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes
>       drm/sun4i: tcon: hand over the duty to keep TCON0 clock to CCU on A64
>
>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
>  drivers/clk/sunxi-ng/ccu_common.c     | 22 ++++++++++++++++++++++
>  drivers/clk/sunxi-ng/ccu_common.h     | 12 ++++++++++++
>  drivers/gpu/drm/sun4i/sun4i_tcon.c    | 15 +++++++++++++--
>  drivers/gpu/drm/sun4i/sun4i_tcon.h    |  1 +
>  5 files changed, 63 insertions(+), 2 deletions(-)
> ---
> base-commit: 1cf5c37ee3c2334a964c65e52b4e0c59b4332d7c
> change-id: 20230807-a64_pll_video0_notifier-164cbc78b341
>
> Best regards,
> --
> Frank Oltmanns <frank@oltmanns.dev>
>
>

Re: [PATCH 0/3] pll-video0 notifier for v6.5+

[Chen-Yu Tsai]

On Mon, Aug 7, 2023 at 5:36 PM Frank Oltmanns <frank@oltmanns.dev> wrote:
>
> Hi Icenowy,
>
> it is my understanding that you are the original author of the following
> patches are in Ondřej's 6.4 branch [1] [2] [3] but not in his 6.5
> branch. I assume it is because of merge conflicts as the part about
> setting the parent has already been fixed in the 6.5 release candidates.
>
> Therefore I've removed those parts and adopted the commit message of
> PATCH 2. I've removed your SoB, because I think you'd need to sign of
> the revised version. Especially patch 2 has become a bit simpler and I'm
> wondering if it makes sense to try to upstream the three patches now.
> What do you think?
>
> Thank you for your amazing work!
>
> Best regards,
>   Frank

Please send to all maintainers and relevant mailing lists (as given
by get_maintainers.pl).


> [1]: https://github.com/megous/linux/commit/2cd3d57adf83e2d091baed77e1aafc01d545d123
> [2]: https://github.com/megous/linux/commit/c9c7bfe22f0fefdfc1dc2ce84b452964112399d7
> [3]: https://github.com/megous/linux/commit/e19ccee10a8492535b6cda1ba97cccc2074d6e65
>
> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
> ---
> Icenowy Zheng (3):
>       clk: sunxi-ng: add support for rate resetting notifier
>       clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes
>       drm/sun4i: tcon: hand over the duty to keep TCON0 clock to CCU on A64
>
>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
>  drivers/clk/sunxi-ng/ccu_common.c     | 22 ++++++++++++++++++++++
>  drivers/clk/sunxi-ng/ccu_common.h     | 12 ++++++++++++
>  drivers/gpu/drm/sun4i/sun4i_tcon.c    | 15 +++++++++++++--
>  drivers/gpu/drm/sun4i/sun4i_tcon.h    |  1 +
>  5 files changed, 63 insertions(+), 2 deletions(-)
> ---
> base-commit: 1cf5c37ee3c2334a964c65e52b4e0c59b4332d7c
> change-id: 20230807-a64_pll_video0_notifier-164cbc78b341
>
> Best regards,
> --
> Frank Oltmanns <frank@oltmanns.dev>
>
>

Re: [PATCH 0/3] pll-video0 notifier for v6.5+

[Frank Oltmanns]

On 2023-08-10 at 21:18:12 +0800, Chen-Yu Tsai <wens@kernel.org> wrote:
> On Mon, Aug 7, 2023 at 5:36 PM Frank Oltmanns <frank@oltmanns.dev> wrote:
>>
>> Hi Icenowy,
>>
>> it is my understanding that you are the original author of the following
>> patches are in Ondřej's 6.4 branch [1] [2] [3] but not in his 6.5
>> branch. I assume it is because of merge conflicts as the part about
>> setting the parent has already been fixed in the 6.5 release candidates.
>>
>> Therefore I've removed those parts and adopted the commit message of
>> PATCH 2. I've removed your SoB, because I think you'd need to sign of
>> the revised version. Especially patch 2 has become a bit simpler and I'm
>> wondering if it makes sense to try to upstream the three patches now.
>> What do you think?
>>
>> Thank you for your amazing work!
>>
>> Best regards,
>>   Frank
>
> Please send to all maintainers and relevant mailing lists (as given
> by get_maintainers.pl).
>

Thank you for pointing this out. This was actually intended as an RFC
specifically for Icenowy, but I forgot to mark it as such.

Furthermore, I decided to cc the two lists because I had trouble
receiving Icenowy's mails in the past and I wanted to make sure I could
at least browse the archives for responses.

I'll take more care next time.

Thanks,
  Frank

>
>
>> [1]: https://github.com/megous/linux/commit/2cd3d57adf83e2d091baed77e1aafc01d545d123
>> [2]: https://github.com/megous/linux/commit/c9c7bfe22f0fefdfc1dc2ce84b452964112399d7
>> [3]: https://github.com/megous/linux/commit/e19ccee10a8492535b6cda1ba97cccc2074d6e65
>>
>> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
>> ---
>> Icenowy Zheng (3):
>>       clk: sunxi-ng: add support for rate resetting notifier
>>       clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes
>>       drm/sun4i: tcon: hand over the duty to keep TCON0 clock to CCU on A64
>>
>>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
>>  drivers/clk/sunxi-ng/ccu_common.c     | 22 ++++++++++++++++++++++
>>  drivers/clk/sunxi-ng/ccu_common.h     | 12 ++++++++++++
>>  drivers/gpu/drm/sun4i/sun4i_tcon.c    | 15 +++++++++++++--
>>  drivers/gpu/drm/sun4i/sun4i_tcon.h    |  1 +
>>  5 files changed, 63 insertions(+), 2 deletions(-)
>> ---
>> base-commit: 1cf5c37ee3c2334a964c65e52b4e0c59b4332d7c
>> change-id: 20230807-a64_pll_video0_notifier-164cbc78b341
>>
>> Best regards,
>> --
>> Frank Oltmanns <frank@oltmanns.dev>
>>
>>

Re: [PATCH 0/3] pll-video0 notifier for v6.5+

[Frank Oltmanns]

On 2023-08-10 at 21:18:12 +0800, Chen-Yu Tsai <wens@kernel.org> wrote:
> On Mon, Aug 7, 2023 at 5:36 PM Frank Oltmanns <frank@oltmanns.dev> wrote:
>>
>> Hi Icenowy,
>>
>> it is my understanding that you are the original author of the following
>> patches are in Ondřej's 6.4 branch [1] [2] [3] but not in his 6.5
>> branch. I assume it is because of merge conflicts as the part about
>> setting the parent has already been fixed in the 6.5 release candidates.
>>
>> Therefore I've removed those parts and adopted the commit message of
>> PATCH 2. I've removed your SoB, because I think you'd need to sign of
>> the revised version. Especially patch 2 has become a bit simpler and I'm
>> wondering if it makes sense to try to upstream the three patches now.
>> What do you think?
>>
>> Thank you for your amazing work!
>>
>> Best regards,
>>   Frank
>
> Please send to all maintainers and relevant mailing lists (as given
> by get_maintainers.pl).
>

Thank you for pointing this out. This was actually intended as an RFC
specifically for Icenowy, but I forgot to mark it as such.

Furthermore, I decided to cc the two lists because I had trouble
receiving Icenowy's mails in the past and I wanted to make sure I could
at least browse the archives for responses.

I'll take more care next time.

Thanks,
  Frank

>
>
>> [1]: https://github.com/megous/linux/commit/2cd3d57adf83e2d091baed77e1aafc01d545d123
>> [2]: https://github.com/megous/linux/commit/c9c7bfe22f0fefdfc1dc2ce84b452964112399d7
>> [3]: https://github.com/megous/linux/commit/e19ccee10a8492535b6cda1ba97cccc2074d6e65
>>
>> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
>> ---
>> Icenowy Zheng (3):
>>       clk: sunxi-ng: add support for rate resetting notifier
>>       clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes
>>       drm/sun4i: tcon: hand over the duty to keep TCON0 clock to CCU on A64
>>
>>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
>>  drivers/clk/sunxi-ng/ccu_common.c     | 22 ++++++++++++++++++++++
>>  drivers/clk/sunxi-ng/ccu_common.h     | 12 ++++++++++++
>>  drivers/gpu/drm/sun4i/sun4i_tcon.c    | 15 +++++++++++++--
>>  drivers/gpu/drm/sun4i/sun4i_tcon.h    |  1 +
>>  5 files changed, 63 insertions(+), 2 deletions(-)
>> ---
>> base-commit: 1cf5c37ee3c2334a964c65e52b4e0c59b4332d7c
>> change-id: 20230807-a64_pll_video0_notifier-164cbc78b341
>>
>> Best regards,
>> --
>> Frank Oltmanns <frank@oltmanns.dev>
>>
>>

Re: [PATCH 2/3] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes

[Frank Oltmanns]

On 2023-08-07 at 18:22:26 +0800, Icenowy Zheng <uwu@icenowy.me> wrote:
> 在 2023-08-07星期一的 11:48 +0200，Frank Oltmanns写道：
>>
>> On 2023-08-07 at 17:43:52 +0800, Icenowy Zheng <uwu@icenowy.me>
>> wrote:
>> > 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
>> > > From: Icenowy Zheng <icenowy@aosc.io>
>> > >
>> > > Notify TCON0 clock (and in consequence PLL-MIPI by
>> > > CLK_SET_RATE_PARENT)
>> > > to reset when PLL-Video0 changes (because of HDMI PHY clk which
>> > > is a
>> > > child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way
>> > > we
>> > > can
>> > > get clock tree to satisfy both pipelines.
>> >
>> > Well for fixing one's patch that contains SoB, use the following
>> > format:
>> >
>> > Signed-off-by: A <a@a.local>
>> > [B: fixed something]
>> > Signed-off-by: B <b@b.local>
>>
>> Ah, okay. Will do. But I keep A in the "From: " line, correct?
>
> Yes.
>

One more thing: You seem to be using a new mail address. Do you want me
to replace the "From" and SoB's with the new address?

Thanks,
  Frank

>
>>
>> Thanks,
>>   Frank
>>
>> > > ---
>> > >  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
>> > >  1 file changed, 15 insertions(+)
>> > >
>> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> > > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> > > index ef567775fc95..93beedb0428e 100644
>> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> > > @@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb =
>> > > {
>> > >         .bypass_index   = 1, /* index of 24 MHz oscillator */
>> > >  };
>> > >  
>> > > +/*
>> > > + * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH,
>> > > tcon0
>> > > clock will
>> > > + * conflict with HDMI PHY clock which is on another display
>> > > pipeline.
>> > > + *
>> > > + * Therefore, a notifier is required to restore the rate of
>> > > TCON0
>> > > when the rate
>> > > + * of PLL-Video0 changed.
>> > > + */
>> > > +static struct ccu_rate_reset_nb
>> > > sun50i_a64_pll_video0_reset_tcon0_nb
>> > > = {
>> > > +       .common         = &pll_video0_clk.common,
>> > > +};
>> > > +
>> > >  static int sun50i_a64_ccu_probe(struct platform_device *pdev)
>> > >  {
>> > >         void __iomem *reg;
>> > > @@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct
>> > > platform_device *pdev)
>> > >         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
>> > >                                   &sun50i_a64_cpu_nb);
>> > >  
>> > > +       /* Reset the rate of TCON0 clock when PLL-VIDEO0 is
>> > > changed
>> > > */
>> > > +       sun50i_a64_pll_video0_reset_tcon0_nb.target_clk =
>> > > tcon0_clk.common.hw.clk;
>> > > +       ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_r
>> > > eset
>> > > _tcon0_nb);
>> > > +
>> > >         return 0;
>> > >  }
>> > >  
>> > >

Re: [PATCH 2/3] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes

[Frank Oltmanns]

On 2023-08-07 at 18:22:26 +0800, Icenowy Zheng <uwu@icenowy.me> wrote:
> 在 2023-08-07星期一的 11:48 +0200，Frank Oltmanns写道：
>>
>> On 2023-08-07 at 17:43:52 +0800, Icenowy Zheng <uwu@icenowy.me>
>> wrote:
>> > 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
>> > > From: Icenowy Zheng <icenowy@aosc.io>
>> > >
>> > > Notify TCON0 clock (and in consequence PLL-MIPI by
>> > > CLK_SET_RATE_PARENT)
>> > > to reset when PLL-Video0 changes (because of HDMI PHY clk which
>> > > is a
>> > > child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way
>> > > we
>> > > can
>> > > get clock tree to satisfy both pipelines.
>> >
>> > Well for fixing one's patch that contains SoB, use the following
>> > format:
>> >
>> > Signed-off-by: A <a@a.local>
>> > [B: fixed something]
>> > Signed-off-by: B <b@b.local>
>>
>> Ah, okay. Will do. But I keep A in the "From: " line, correct?
>
> Yes.
>

One more thing: You seem to be using a new mail address. Do you want me
to replace the "From" and SoB's with the new address?

Thanks,
  Frank

>
>>
>> Thanks,
>>   Frank
>>
>> > > ---
>> > >  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
>> > >  1 file changed, 15 insertions(+)
>> > >
>> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> > > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> > > index ef567775fc95..93beedb0428e 100644
>> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> > > @@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb =
>> > > {
>> > >         .bypass_index   = 1, /* index of 24 MHz oscillator */
>> > >  };
>> > >  
>> > > +/*
>> > > + * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH,
>> > > tcon0
>> > > clock will
>> > > + * conflict with HDMI PHY clock which is on another display
>> > > pipeline.
>> > > + *
>> > > + * Therefore, a notifier is required to restore the rate of
>> > > TCON0
>> > > when the rate
>> > > + * of PLL-Video0 changed.
>> > > + */
>> > > +static struct ccu_rate_reset_nb
>> > > sun50i_a64_pll_video0_reset_tcon0_nb
>> > > = {
>> > > +       .common         = &pll_video0_clk.common,
>> > > +};
>> > > +
>> > >  static int sun50i_a64_ccu_probe(struct platform_device *pdev)
>> > >  {
>> > >         void __iomem *reg;
>> > > @@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct
>> > > platform_device *pdev)
>> > >         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
>> > >                                   &sun50i_a64_cpu_nb);
>> > >  
>> > > +       /* Reset the rate of TCON0 clock when PLL-VIDEO0 is
>> > > changed
>> > > */
>> > > +       sun50i_a64_pll_video0_reset_tcon0_nb.target_clk =
>> > > tcon0_clk.common.hw.clk;
>> > > +       ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_r
>> > > eset
>> > > _tcon0_nb);
>> > > +
>> > >         return 0;
>> > >  }
>> > >  
>> > >