[PATCH v3 0/6] Add loongarch32 mode for loongarch64-softmmu

[PATCH v3 0/6] Add loongarch32 mode for loongarch64-softmmu

[Jiajie Chen]

This patch series allow qemu-system-loongarch64 to emulate a LoongArch32
machine. A mode enum is added to CPUArchState to select LA32 or LA64 at
runtime. A new CPU model is added for loongarch32. Initial GDB support
is added.

Changes since v2:

- Fix typo in previous commit
- Fix VPPN width in TLBEHI/TLBREHI

Changes since v1:

- No longer create a separate qemu-system-loongarch32 executable, but
  allow user to run loongarch32 emulation using qemu-system-loongarch64
- Add loongarch32 cpu support for virt machine

Full changes:

Jiajie Chen (6):
  target/loongarch: Add loongarch32 mode for loongarch64-softmmu
  target/loongarch: Add loongarch32 cpu la132
  target/loongarch: Add GDB support for loongarch32 mode
  target/loongarch: Support LoongArch32 TLB entry
  target/loongarch: Support LoongArch32 DMW
  target/loongarch: Support LoongArch32 VPPN

 configs/targets/loongarch64-softmmu.mak |  2 +-
 gdb-xml/loongarch-base32.xml            | 45 ++++++++++++++++
 hw/loongarch/virt.c                     |  5 --
 target/loongarch/cpu-csr.h              | 22 ++++----
 target/loongarch/cpu.c                  | 51 +++++++++++++++++-
 target/loongarch/cpu.h                  | 18 +++++++
 target/loongarch/gdbstub.c              | 32 ++++++++---
 target/loongarch/tlb_helper.c           | 71 ++++++++++++++++++++-----
 8 files changed, 209 insertions(+), 37 deletions(-)
 create mode 100644 gdb-xml/loongarch-base32.xml

-- 
2.39.2

[PATCH v3 1/6] target/loongarch: Add loongarch32 mode for loongarch64-softmmu

[Jiajie Chen]

This commit adds loongarch32 mode to loongarch64-softmmu.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 target/loongarch/cpu.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index fa371ca8ba..43c73e6363 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -272,9 +272,16 @@ struct LoongArchTLB {
 };
 typedef struct LoongArchTLB LoongArchTLB;
 
+/* Current LoongArch mode */
+typedef enum LoongArchMode {
+    LA32 = 0,
+    LA64 = 1,
+} LoongArchMode;
+
 typedef struct CPUArchState {
     uint64_t gpr[32];
     uint64_t pc;
+    LoongArchMode mode;
 
     fpr_t fpr[32];
     float_status fp_status;
-- 
2.39.2

[PATCH v3 2/6] target/loongarch: Add loongarch32 cpu la132

[Jiajie Chen]

Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 hw/loongarch/virt.c    |  5 -----
 target/loongarch/cpu.c | 41 +++++++++++++++++++++++++++++++++++++++++
 target/loongarch/cpu.h | 11 +++++++++++
 3 files changed, 52 insertions(+), 5 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index e19b042ce8..af15bf5aaa 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -798,11 +798,6 @@ static void loongarch_init(MachineState *machine)
         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
     }
 
-    if (!strstr(cpu_model, "la464")) {
-        error_report("LoongArch/TCG needs cpu type la464");
-        exit(1);
-    }
-
     if (ram_size < 1 * GiB) {
         error_report("ram_size must be greater than 1G.");
         exit(1);
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ad93ecac92..d31efe86da 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -362,6 +362,8 @@ static void loongarch_la464_initfn(Object *obj)
     CPULoongArchState *env = &cpu->env;
     int i;
 
+    env->mode = LA64;
+
     for (i = 0; i < 21; i++) {
         env->cpucfg[i] = 0x0;
     }
@@ -439,6 +441,20 @@ static void loongarch_la464_initfn(Object *obj)
     env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
 }
 
+static void loongarch_la132_initfn(Object *obj)
+{
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    CPULoongArchState *env = &cpu->env;
+
+    env->mode = LA32;
+
+    cpu->dtb_compatible = "loongarch,Loongson-3C103";
+
+    uint32_t data = 0;
+    data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
+    env->cpucfg[1] = data;
+}
+
 static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
 {
     const char *typename = object_class_get_name(OBJECT_CLASS(data));
@@ -732,6 +748,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
 #endif
 }
 
+static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
+{
+}
+
 #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
     { \
         .parent = TYPE_LOONGARCH_CPU, \
@@ -754,3 +774,24 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
 };
 
 DEFINE_TYPES(loongarch_cpu_type_infos)
+
+#define DEFINE_LOONGARCH32_CPU_TYPE(model, initfn) \
+    { \
+        .parent = TYPE_LOONGARCH32_CPU, \
+        .instance_init = initfn, \
+        .name = LOONGARCH_CPU_TYPE_NAME(model), \
+    }
+
+static const TypeInfo loongarch32_cpu_type_infos[] = {
+    {
+        .name = TYPE_LOONGARCH32_CPU,
+        .parent = TYPE_LOONGARCH_CPU,
+        .instance_size = sizeof(LoongArchCPU),
+
+        .abstract = true,
+        .class_size = sizeof(LoongArchCPUClass),
+        .class_init = loongarch32_cpu_class_init,
+    },
+    DEFINE_LOONGARCH32_CPU_TYPE("la132", loongarch_la132_initfn),
+};
+DEFINE_TYPES(loongarch32_cpu_type_infos)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 43c73e6363..f1907cddc5 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -404,6 +404,17 @@ struct LoongArchCPUClass {
     ResettablePhases parent_phases;
 };
 
+#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
+typedef struct LoongArch32CPUClass LoongArch32CPUClass;
+DECLARE_CLASS_CHECKERS(LoongArch32CPUClass, LOONGARCH32_CPU,
+                       TYPE_LOONGARCH32_CPU)
+
+struct LoongArch32CPUClass {
+    /*< private >*/
+    LoongArchCPUClass parent_class;
+    /*< public >*/
+};
+
 /*
  * LoongArch CPUs has 4 privilege levels.
  * 0 for kernel mode, 3 for user mode.
-- 
2.39.2

[PATCH v3 3/6] target/loongarch: Add GDB support for loongarch32 mode

[Jiajie Chen]

GPRs and PC are 32-bit wide in loongarch32 mode.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 configs/targets/loongarch64-softmmu.mak |  2 +-
 gdb-xml/loongarch-base32.xml            | 45 +++++++++++++++++++++++++
 target/loongarch/cpu.c                  | 10 +++++-
 target/loongarch/gdbstub.c              | 32 ++++++++++++++----
 4 files changed, 80 insertions(+), 9 deletions(-)
 create mode 100644 gdb-xml/loongarch-base32.xml

diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
index 9abc99056f..f23780fdd8 100644
--- a/configs/targets/loongarch64-softmmu.mak
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -1,5 +1,5 @@
 TARGET_ARCH=loongarch64
 TARGET_BASE_ARCH=loongarch
 TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
+TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
 TARGET_NEED_FDT=y
diff --git a/gdb-xml/loongarch-base32.xml b/gdb-xml/loongarch-base32.xml
new file mode 100644
index 0000000000..af47bbd3da
--- /dev/null
+++ b/gdb-xml/loongarch-base32.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2022 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.loongarch.base">
+  <reg name="r0" bitsize="32" type="uint32" group="general"/>
+  <reg name="r1" bitsize="32" type="code_ptr" group="general"/>
+  <reg name="r2" bitsize="32" type="data_ptr" group="general"/>
+  <reg name="r3" bitsize="32" type="data_ptr" group="general"/>
+  <reg name="r4" bitsize="32" type="uint32" group="general"/>
+  <reg name="r5" bitsize="32" type="uint32" group="general"/>
+  <reg name="r6" bitsize="32" type="uint32" group="general"/>
+  <reg name="r7" bitsize="32" type="uint32" group="general"/>
+  <reg name="r8" bitsize="32" type="uint32" group="general"/>
+  <reg name="r9" bitsize="32" type="uint32" group="general"/>
+  <reg name="r10" bitsize="32" type="uint32" group="general"/>
+  <reg name="r11" bitsize="32" type="uint32" group="general"/>
+  <reg name="r12" bitsize="32" type="uint32" group="general"/>
+  <reg name="r13" bitsize="32" type="uint32" group="general"/>
+  <reg name="r14" bitsize="32" type="uint32" group="general"/>
+  <reg name="r15" bitsize="32" type="uint32" group="general"/>
+  <reg name="r16" bitsize="32" type="uint32" group="general"/>
+  <reg name="r17" bitsize="32" type="uint32" group="general"/>
+  <reg name="r18" bitsize="32" type="uint32" group="general"/>
+  <reg name="r19" bitsize="32" type="uint32" group="general"/>
+  <reg name="r20" bitsize="32" type="uint32" group="general"/>
+  <reg name="r21" bitsize="32" type="uint32" group="general"/>
+  <reg name="r22" bitsize="32" type="data_ptr" group="general"/>
+  <reg name="r23" bitsize="32" type="uint32" group="general"/>
+  <reg name="r24" bitsize="32" type="uint32" group="general"/>
+  <reg name="r25" bitsize="32" type="uint32" group="general"/>
+  <reg name="r26" bitsize="32" type="uint32" group="general"/>
+  <reg name="r27" bitsize="32" type="uint32" group="general"/>
+  <reg name="r28" bitsize="32" type="uint32" group="general"/>
+  <reg name="r29" bitsize="32" type="uint32" group="general"/>
+  <reg name="r30" bitsize="32" type="uint32" group="general"/>
+  <reg name="r31" bitsize="32" type="uint32" group="general"/>
+  <reg name="orig_a0" bitsize="32" type="uint32" group="general"/>
+  <reg name="pc" bitsize="32" type="code_ptr" group="general"/>
+  <reg name="badv" bitsize="32" type="code_ptr" group="general"/>
+</feature>
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index d31efe86da..ee6d45f1b0 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -710,7 +710,13 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
 
 static gchar *loongarch_gdb_arch_name(CPUState *cs)
 {
-    return g_strdup("loongarch64");
+    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+    CPULoongArchState *env = &cpu->env;
+    if (env->mode == LA64) {
+        return g_strdup("loongarch64");
+    } else {
+        return g_strdup("loongarch32");
+    }
 }
 
 static void loongarch_cpu_class_init(ObjectClass *c, void *data)
@@ -750,6 +756,8 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
 
 static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
 {
+    CPUClass *cc = CPU_CLASS(c);
+    cc->gdb_core_xml_file = "loongarch-base32.xml";
 }
 
 #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 0752fff924..7c82204e92 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -34,16 +34,25 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(cs);
     CPULoongArchState *env = &cpu->env;
+    uint64_t val;
 
     if (0 <= n && n < 32) {
-        return gdb_get_regl(mem_buf, env->gpr[n]);
+        val = env->gpr[n];
     } else if (n == 32) {
         /* orig_a0 */
-        return gdb_get_regl(mem_buf, 0);
+        val = 0;
     } else if (n == 33) {
-        return gdb_get_regl(mem_buf, env->pc);
+        val = env->pc;
     } else if (n == 34) {
-        return gdb_get_regl(mem_buf, env->CSR_BADV);
+        val = env->CSR_BADV;
+    }
+
+    if (0 <= n && n <= 34) {
+        if (env->mode == LA64) {
+            return gdb_get_reg64(mem_buf, val);
+        } else {
+            return gdb_get_reg32(mem_buf, val);
+        }
     }
     return 0;
 }
@@ -52,15 +61,24 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(cs);
     CPULoongArchState *env = &cpu->env;
-    target_ulong tmp = ldtul_p(mem_buf);
+    target_ulong tmp;
+    int read_length;
     int length = 0;
 
+    if (env->mode == LA64) {
+        tmp = ldq_p(mem_buf);
+        read_length = 8;
+    } else {
+        tmp = ldl_p(mem_buf);
+        read_length = 4;
+    }
+
     if (0 <= n && n < 32) {
         env->gpr[n] = tmp;
-        length = sizeof(target_ulong);
+        length = read_length;
     } else if (n == 33) {
         env->pc = tmp;
-        length = sizeof(target_ulong);
+        length = read_length;
     }
     return length;
 }
-- 
2.39.2

[PATCH v3 4/6] target/loongarch: Support LoongArch32 TLB entry

[Jiajie Chen]

The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 target/loongarch/cpu-csr.h    |  9 +++++----
 target/loongarch/tlb_helper.c | 17 ++++++++++++-----
 2 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index f8f24032cb..48ed2e0632 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
 FIELD(TLBENTRY, PLV, 2, 2)
 FIELD(TLBENTRY, MAT, 4, 2)
 FIELD(TLBENTRY, G, 6, 1)
-FIELD(TLBENTRY, PPN, 12, 36)
-FIELD(TLBENTRY, NR, 61, 1)
-FIELD(TLBENTRY, NX, 62, 1)
-FIELD(TLBENTRY, RPLV, 63, 1)
+FIELD(TLBENTRY_32, PPN, 8, 24)
+FIELD(TLBENTRY_64, PPN, 12, 36)
+FIELD(TLBENTRY_64, NR, 61, 1)
+FIELD(TLBENTRY_64, NX, 62, 1)
+FIELD(TLBENTRY_64, RPLV, 63, 1)
 
 #define LOONGARCH_CSR_ASID           0x18 /* Address space identifier */
 FIELD(CSR_ASID, ASID, 0, 10)
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 6e00190547..690c6ef25f 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -48,10 +48,17 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
     tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
     tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
     tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
-    tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
-    tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
-    tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
-    tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
+    if (env->mode == LA64) {
+        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
+        tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
+        tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
+        tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
+    } else {
+        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
+        tlb_nx = 0;
+        tlb_nr = 0;
+        tlb_rplv = 0;
+    }
 
     /* Check access rights */
     if (!tlb_v) {
@@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
      * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
      * need adjust.
      */
-    *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
+    *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
                 (address & MAKE_64BIT_MASK(0, tlb_ps));
     *prot = PAGE_READ;
     if (tlb_d) {
-- 
2.39.2

[PATCH v3 5/6] target/loongarch: Support LoongArch32 DMW

[Jiajie Chen]

LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 target/loongarch/cpu-csr.h    |  7 +++----
 target/loongarch/tlb_helper.c | 31 ++++++++++++++++++++++++++++---
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 48ed2e0632..b93f99a9ef 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -188,10 +188,9 @@ FIELD(CSR_DMW, PLV1, 1, 1)
 FIELD(CSR_DMW, PLV2, 2, 1)
 FIELD(CSR_DMW, PLV3, 3, 1)
 FIELD(CSR_DMW, MAT, 4, 2)
-FIELD(CSR_DMW, VSEG, 60, 4)
-
-#define dmw_va2pa(va) \
-    (va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS))
+FIELD(CSR_DMW_32, PSEG, 25, 3)
+FIELD(CSR_DMW_32, VSEG, 29, 3)
+FIELD(CSR_DMW_64, VSEG, 60, 4)
 
 /* Debug CSRs */
 #define LOONGARCH_CSR_DBG            0x500 /* debug config */
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 690c6ef25f..cf6f5863f9 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -173,6 +173,18 @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
     return TLBRET_NOMATCH;
 }
 
+static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
+                        target_ulong dmw)
+{
+    if (env->mode == LA64) {
+        return va & TARGET_PHYS_MASK;
+    } else {
+        uint32_t pseg = FIELD_EX32(dmw, CSR_DMW_32, PSEG);
+        return (va & MAKE_64BIT_MASK(0, R_CSR_DMW_32_VSEG_SHIFT)) | \
+            (pseg << R_CSR_DMW_32_VSEG_SHIFT);
+    }
+}
+
 static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
                                 int *prot, target_ulong address,
                                 MMUAccessType access_type, int mmu_idx)
@@ -184,6 +196,11 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
     uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
     uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
 
+    /* Truncate high 32 bits for LA32 */
+    if (env->mode == LA32) {
+        address = (uint32_t)address;
+    }
+
     /* Check PG and DA */
     if (da & !pg) {
         *physical = address & TARGET_PHYS_MASK;
@@ -192,12 +209,20 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
     }
 
     plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
-    base_v = address >> R_CSR_DMW_VSEG_SHIFT;
+    if (env->mode == LA64) {
+        base_v = address >> R_CSR_DMW_64_VSEG_SHIFT;
+    } else {
+        base_v = address >> R_CSR_DMW_32_VSEG_SHIFT;
+    }
     /* Check direct map window */
     for (int i = 0; i < 4; i++) {
-        base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG);
+        if (env->mode == LA64) {
+            base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_64, VSEG);
+        } else {
+            base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_32, VSEG);
+        }
         if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
-            *physical = dmw_va2pa(address);
+            *physical = dmw_va2pa(env, address, env->CSR_DMW[i]);
             *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
             return TLBRET_MATCH;
         }
-- 
2.39.2

[PATCH v3 6/6] target/loongarch: Support LoongArch32 VPPN

[Jiajie Chen]

VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 target/loongarch/cpu-csr.h    |  6 ++++--
 target/loongarch/tlb_helper.c | 23 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index b93f99a9ef..9501a969af 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -57,7 +57,8 @@ FIELD(CSR_TLBIDX, PS, 24, 6)
 FIELD(CSR_TLBIDX, NE, 31, 1)
 
 #define LOONGARCH_CSR_TLBEHI         0x11 /* TLB EntryHi */
-FIELD(CSR_TLBEHI, VPPN, 13, 35)
+FIELD(CSR_TLBEHI_32, VPPN, 13, 35)
+FIELD(CSR_TLBEHI_64, VPPN, 13, 19)
 
 #define LOONGARCH_CSR_TLBELO0        0x12 /* TLB EntryLo0 */
 #define LOONGARCH_CSR_TLBELO1        0x13 /* TLB EntryLo1 */
@@ -164,7 +165,8 @@ FIELD(CSR_TLBRERA, PC, 2, 62)
 #define LOONGARCH_CSR_TLBRELO1       0x8d /* TLB refill entrylo1 */
 #define LOONGARCH_CSR_TLBREHI        0x8e /* TLB refill entryhi */
 FIELD(CSR_TLBREHI, PS, 0, 6)
-FIELD(CSR_TLBREHI, VPPN, 13, 35)
+FIELD(CSR_TLBREHI_32, VPPN, 13, 35)
+FIELD(CSR_TLBREHI_64, VPPN, 13, 19)
 #define LOONGARCH_CSR_TLBRPRMD       0x8f /* TLB refill mode info */
 FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
 FIELD(CSR_TLBRPRMD, PIE, 2, 1)
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index cf6f5863f9..7926c40252 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -305,8 +305,13 @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
 
     if (tlb_error == TLBRET_NOMATCH) {
         env->CSR_TLBRBADV = address;
-        env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN,
-                                      extract64(address, 13, 35));
+        if (env->mode == LA64) {
+            env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_64,
+                                        VPPN, extract64(address, 13, 35));
+        } else {
+            env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_32,
+                                        VPPN, extract64(address, 13, 19));
+        }
     } else {
         if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
             env->CSR_BADV = address;
@@ -371,12 +376,20 @@ static void fill_tlb_entry(CPULoongArchState *env, int index)
 
     if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
         csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
-        csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN);
+        if (env->mode == LA64) {
+            csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN);
+        } else {
+            csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN);
+        }
         lo0 = env->CSR_TLBRELO0;
         lo1 = env->CSR_TLBRELO1;
     } else {
         csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
-        csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI, VPPN);
+        if (env->mode == LA64) {
+            csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN);
+        } else {
+            csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN);
+        }
         lo0 = env->CSR_TLBELO0;
         lo1 = env->CSR_TLBELO1;
     }
@@ -496,7 +509,7 @@ void helper_tlbfill(CPULoongArchState *env)
 
     if (pagesize == stlb_ps) {
         /* Only write into STLB bits [47:13] */
-        address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_VPPN_SHIFT);
+        address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT);
 
         /* Choose one set ramdomly */
         set = get_random_tlb(0, 7);
-- 
2.39.2

Re: [PATCH v3 6/6] target/loongarch: Support LoongArch32 VPPN

[Jiajie Chen]

On 2023/8/7 17:45, Jiajie Chen wrote:
> VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
>   target/loongarch/cpu-csr.h    |  6 ++++--
>   target/loongarch/tlb_helper.c | 23 ++++++++++++++++++-----
>   2 files changed, 22 insertions(+), 7 deletions(-)
>
> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
> index b93f99a9ef..9501a969af 100644
> --- a/target/loongarch/cpu-csr.h
> +++ b/target/loongarch/cpu-csr.h
> @@ -57,7 +57,8 @@ FIELD(CSR_TLBIDX, PS, 24, 6)
>   FIELD(CSR_TLBIDX, NE, 31, 1)
>   
>   #define LOONGARCH_CSR_TLBEHI         0x11 /* TLB EntryHi */
> -FIELD(CSR_TLBEHI, VPPN, 13, 35)
> +FIELD(CSR_TLBEHI_32, VPPN, 13, 35)
> +FIELD(CSR_TLBEHI_64, VPPN, 13, 19)
Sorry, the bit width is wrong.
>   
>   #define LOONGARCH_CSR_TLBELO0        0x12 /* TLB EntryLo0 */
>   #define LOONGARCH_CSR_TLBELO1        0x13 /* TLB EntryLo1 */
> @@ -164,7 +165,8 @@ FIELD(CSR_TLBRERA, PC, 2, 62)
>   #define LOONGARCH_CSR_TLBRELO1       0x8d /* TLB refill entrylo1 */
>   #define LOONGARCH_CSR_TLBREHI        0x8e /* TLB refill entryhi */
>   FIELD(CSR_TLBREHI, PS, 0, 6)
> -FIELD(CSR_TLBREHI, VPPN, 13, 35)
> +FIELD(CSR_TLBREHI_32, VPPN, 13, 35)
> +FIELD(CSR_TLBREHI_64, VPPN, 13, 19)
>   #define LOONGARCH_CSR_TLBRPRMD       0x8f /* TLB refill mode info */
>   FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
>   FIELD(CSR_TLBRPRMD, PIE, 2, 1)
> diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
> index cf6f5863f9..7926c40252 100644
> --- a/target/loongarch/tlb_helper.c
> +++ b/target/loongarch/tlb_helper.c
> @@ -305,8 +305,13 @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
>   
>       if (tlb_error == TLBRET_NOMATCH) {
>           env->CSR_TLBRBADV = address;
> -        env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN,
> -                                      extract64(address, 13, 35));
> +        if (env->mode == LA64) {
> +            env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_64,
> +                                        VPPN, extract64(address, 13, 35));
> +        } else {
> +            env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_32,
> +                                        VPPN, extract64(address, 13, 19));
> +        }
>       } else {
>           if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
>               env->CSR_BADV = address;
> @@ -371,12 +376,20 @@ static void fill_tlb_entry(CPULoongArchState *env, int index)
>   
>       if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
>           csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
> -        csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN);
> +        if (env->mode == LA64) {
> +            csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN);
> +        } else {
> +            csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN);
> +        }
>           lo0 = env->CSR_TLBRELO0;
>           lo1 = env->CSR_TLBRELO1;
>       } else {
>           csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
> -        csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI, VPPN);
> +        if (env->mode == LA64) {
> +            csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN);
> +        } else {
> +            csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN);
> +        }
>           lo0 = env->CSR_TLBELO0;
>           lo1 = env->CSR_TLBELO1;
>       }
> @@ -496,7 +509,7 @@ void helper_tlbfill(CPULoongArchState *env)
>   
>       if (pagesize == stlb_ps) {
>           /* Only write into STLB bits [47:13] */
> -        address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_VPPN_SHIFT);
> +        address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT);
>   
>           /* Choose one set ramdomly */
>           set = get_random_tlb(0, 7);

Re: [PATCH v3 2/6] target/loongarch: Add loongarch32 cpu la132

[WANG Xuerui]

Hi,

On 2023/8/7 17:45, Jiajie Chen wrote:
> Add la132 as a loongarch32 cpu type and allow virt machine to be used
> with la132 instead of la464.
> 
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
>   hw/loongarch/virt.c    |  5 -----
>   target/loongarch/cpu.c | 41 +++++++++++++++++++++++++++++++++++++++++
>   target/loongarch/cpu.h | 11 +++++++++++
>   3 files changed, 52 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
> index e19b042ce8..af15bf5aaa 100644
> --- a/hw/loongarch/virt.c
> +++ b/hw/loongarch/virt.c
> @@ -798,11 +798,6 @@ static void loongarch_init(MachineState *machine)
>           cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
>       }
>   
> -    if (!strstr(cpu_model, "la464")) {
> -        error_report("LoongArch/TCG needs cpu type la464");
> -        exit(1);
> -    }
> -
>       if (ram_size < 1 * GiB) {
>           error_report("ram_size must be greater than 1G.");
>           exit(1);
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index ad93ecac92..d31efe86da 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -362,6 +362,8 @@ static void loongarch_la464_initfn(Object *obj)
>       CPULoongArchState *env = &cpu->env;
>       int i;
>   
> +    env->mode = LA64;
> +
>       for (i = 0; i < 21; i++) {
>           env->cpucfg[i] = 0x0;
>       }
> @@ -439,6 +441,20 @@ static void loongarch_la464_initfn(Object *obj)
>       env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
>   }
>   
> +static void loongarch_la132_initfn(Object *obj)
> +{
> +    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> +    CPULoongArchState *env = &cpu->env;
> +
> +    env->mode = LA32;
> +
> +    cpu->dtb_compatible = "loongarch,Loongson-3C103";

"3C103"? I assume you want something like "1C300" or "1Axxx", at least 
something prefixed with "1"...

Re: [PATCH v3 2/6] target/loongarch: Add loongarch32 cpu la132

[Jiajie Chen]

On 2023/8/7 17:54, WANG Xuerui wrote:
> Hi,
>
> On 2023/8/7 17:45, Jiajie Chen wrote:
>> Add la132 as a loongarch32 cpu type and allow virt machine to be used
>> with la132 instead of la464.
>>
>> Signed-off-by: Jiajie Chen <c@jia.je>
>> ---
>>   hw/loongarch/virt.c    |  5 -----
>>   target/loongarch/cpu.c | 41 +++++++++++++++++++++++++++++++++++++++++
>>   target/loongarch/cpu.h | 11 +++++++++++
>>   3 files changed, 52 insertions(+), 5 deletions(-)
>>
>> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
>> index e19b042ce8..af15bf5aaa 100644
>> --- a/hw/loongarch/virt.c
>> +++ b/hw/loongarch/virt.c
>> @@ -798,11 +798,6 @@ static void loongarch_init(MachineState *machine)
>>           cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
>>       }
>>   -    if (!strstr(cpu_model, "la464")) {
>> -        error_report("LoongArch/TCG needs cpu type la464");
>> -        exit(1);
>> -    }
>> -
>>       if (ram_size < 1 * GiB) {
>>           error_report("ram_size must be greater than 1G.");
>>           exit(1);
>> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
>> index ad93ecac92..d31efe86da 100644
>> --- a/target/loongarch/cpu.c
>> +++ b/target/loongarch/cpu.c
>> @@ -362,6 +362,8 @@ static void loongarch_la464_initfn(Object *obj)
>>       CPULoongArchState *env = &cpu->env;
>>       int i;
>>   +    env->mode = LA64;
>> +
>>       for (i = 0; i < 21; i++) {
>>           env->cpucfg[i] = 0x0;
>>       }
>> @@ -439,6 +441,20 @@ static void loongarch_la464_initfn(Object *obj)
>>       env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
>>   }
>>   +static void loongarch_la132_initfn(Object *obj)
>> +{
>> +    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
>> +    CPULoongArchState *env = &cpu->env;
>> +
>> +    env->mode = LA32;
>> +
>> +    cpu->dtb_compatible = "loongarch,Loongson-3C103";
>
> "3C103"? I assume you want something like "1C300" or "1Axxx", at least 
> something prefixed with "1"...

You are right, I was meant to write "1C103"..

Re: [PATCH v3 6/6] target/loongarch: Support LoongArch32 VPPN

[gaosong]

在 2023/8/7 下午5:45, Jiajie Chen 写道:
> VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
> 
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
>   target/loongarch/cpu-csr.h    |  6 ++++--
>   target/loongarch/tlb_helper.c | 23 ++++++++++++++++++-----
>   2 files changed, 22 insertions(+), 7 deletions(-)
> 
> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
> index b93f99a9ef..9501a969af 100644
> --- a/target/loongarch/cpu-csr.h
> +++ b/target/loongarch/cpu-csr.h
> @@ -57,7 +57,8 @@ FIELD(CSR_TLBIDX, PS, 24, 6)
>   FIELD(CSR_TLBIDX, NE, 31, 1)
>   
>   #define LOONGARCH_CSR_TLBEHI         0x11 /* TLB EntryHi */
> -FIELD(CSR_TLBEHI, VPPN, 13, 35)
> +FIELD(CSR_TLBEHI_32, VPPN, 13, 35)
> +FIELD(CSR_TLBEHI_64, VPPN, 13, 19)
> 

FIELD(CSR_TLBEHI_32, VPPN, 13, 19)
FIELD(CSR_TLBEHI_64, VPPN, 13, 35)

>   #define LOONGARCH_CSR_TLBELO0        0x12 /* TLB EntryLo0 */
>   #define LOONGARCH_CSR_TLBELO1        0x13 /* TLB EntryLo1 */
> @@ -164,7 +165,8 @@ FIELD(CSR_TLBRERA, PC, 2, 62)
>   #define LOONGARCH_CSR_TLBRELO1       0x8d /* TLB refill entrylo1 */
>   #define LOONGARCH_CSR_TLBREHI        0x8e /* TLB refill entryhi */
>   FIELD(CSR_TLBREHI, PS, 0, 6)
> -FIELD(CSR_TLBREHI, VPPN, 13, 35)
> +FIELD(CSR_TLBREHI_32, VPPN, 13, 35)
> +FIELD(CSR_TLBREHI_64, VPPN, 13, 19)

FIELD(CSR_TLBREHI_32, VPPN, 13, 19)
FIELD(CSR_TLBREHI_64, VPPN, 13, 35)

We should test booting a 64 bit kernel or system,
and adding a 32bit example in patch0 would be more useful.


Thanks.
Song Gao

>   #define LOONGARCH_CSR_TLBRPRMD       0x8f /* TLB refill mode info */
>   FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
>   FIELD(CSR_TLBRPRMD, PIE, 2, 1)
> diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
> index cf6f5863f9..7926c40252 100644
> --- a/target/loongarch/tlb_helper.c
> +++ b/target/loongarch/tlb_helper.c
> @@ -305,8 +305,13 @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
>   
>       if (tlb_error == TLBRET_NOMATCH) {
>           env->CSR_TLBRBADV = address;
> -        env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN,
> -                                      extract64(address, 13, 35));
> +        if (env->mode == LA64) {
> +            env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_64,
> +                                        VPPN, extract64(address, 13, 35));
> +        } else {
> +            env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_32,
> +                                        VPPN, extract64(address, 13, 19));
> +        }
>       } else {
>           if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
>               env->CSR_BADV = address;
> @@ -371,12 +376,20 @@ static void fill_tlb_entry(CPULoongArchState *env, int index)
>   
>       if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
>           csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
> -        csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN);
> +        if (env->mode == LA64) {
> +            csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN);
> +        } else {
> +            csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN);
> +        }
>           lo0 = env->CSR_TLBRELO0;
>           lo1 = env->CSR_TLBRELO1;
>       } else {
>           csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
> -        csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI, VPPN);
> +        if (env->mode == LA64) {
> +            csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN);
> +        } else {
> +            csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN);
> +        }
>           lo0 = env->CSR_TLBELO0;
>           lo1 = env->CSR_TLBELO1;
>       }
> @@ -496,7 +509,7 @@ void helper_tlbfill(CPULoongArchState *env)
>   
>       if (pagesize == stlb_ps) {
>           /* Only write into STLB bits [47:13] */
> -        address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_VPPN_SHIFT);
> +        address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT);
>   
>           /* Choose one set ramdomly */
>           set = get_random_tlb(0, 7);
> 

Re: [PATCH v3 6/6] target/loongarch: Support LoongArch32 VPPN

[Jiajie Chen]

On 2023/8/7 19:53, gaosong wrote:
> 在 2023/8/7 下午5:45, Jiajie Chen 写道:
>> VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
>>
>> Signed-off-by: Jiajie Chen <c@jia.je>
>> ---
>>   target/loongarch/cpu-csr.h    |  6 ++++--
>>   target/loongarch/tlb_helper.c | 23 ++++++++++++++++++-----
>>   2 files changed, 22 insertions(+), 7 deletions(-)
>>
>> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
>> index b93f99a9ef..9501a969af 100644
>> --- a/target/loongarch/cpu-csr.h
>> +++ b/target/loongarch/cpu-csr.h
>> @@ -57,7 +57,8 @@ FIELD(CSR_TLBIDX, PS, 24, 6)
>>   FIELD(CSR_TLBIDX, NE, 31, 1)
>>     #define LOONGARCH_CSR_TLBEHI         0x11 /* TLB EntryHi */
>> -FIELD(CSR_TLBEHI, VPPN, 13, 35)
>> +FIELD(CSR_TLBEHI_32, VPPN, 13, 35)
>> +FIELD(CSR_TLBEHI_64, VPPN, 13, 19)
>>
>
> FIELD(CSR_TLBEHI_32, VPPN, 13, 19)
> FIELD(CSR_TLBEHI_64, VPPN, 13, 35)
Thanks for correction.
>
>>   #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
>>   #define LOONGARCH_CSR_TLBELO1        0x13 /* TLB EntryLo1 */
>> @@ -164,7 +165,8 @@ FIELD(CSR_TLBRERA, PC, 2, 62)
>>   #define LOONGARCH_CSR_TLBRELO1       0x8d /* TLB refill entrylo1 */
>>   #define LOONGARCH_CSR_TLBREHI        0x8e /* TLB refill entryhi */
>>   FIELD(CSR_TLBREHI, PS, 0, 6)
>> -FIELD(CSR_TLBREHI, VPPN, 13, 35)
>> +FIELD(CSR_TLBREHI_32, VPPN, 13, 35)
>> +FIELD(CSR_TLBREHI_64, VPPN, 13, 19)
>
> FIELD(CSR_TLBREHI_32, VPPN, 13, 19)
> FIELD(CSR_TLBREHI_64, VPPN, 13, 35)
Thanks for correction.
>
> We should test booting a 64 bit kernel or system,
> and adding a 32bit example in patch0 would be more useful.
I have tested booting a bare-metal supervisor: 
https://github.com/jiegec/supervisor-la32.
>
>
> Thanks.
> Song Gao
>
>>   #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
>>   FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
>>   FIELD(CSR_TLBRPRMD, PIE, 2, 1)
>> diff --git a/target/loongarch/tlb_helper.c 
>> b/target/loongarch/tlb_helper.c
>> index cf6f5863f9..7926c40252 100644
>> --- a/target/loongarch/tlb_helper.c
>> +++ b/target/loongarch/tlb_helper.c
>> @@ -305,8 +305,13 @@ static void 
>> raise_mmu_exception(CPULoongArchState *env, target_ulong address,
>>         if (tlb_error == TLBRET_NOMATCH) {
>>           env->CSR_TLBRBADV = address;
>> -        env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, 
>> VPPN,
>> -                                      extract64(address, 13, 35));
>> +        if (env->mode == LA64) {
>> +            env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, 
>> CSR_TLBREHI_64,
>> +                                        VPPN, extract64(address, 13, 
>> 35));
>> +        } else {
>> +            env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, 
>> CSR_TLBREHI_32,
>> +                                        VPPN, extract64(address, 13, 
>> 19));
>> +        }
>>       } else {
>>           if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
>>               env->CSR_BADV = address;
>> @@ -371,12 +376,20 @@ static void fill_tlb_entry(CPULoongArchState 
>> *env, int index)
>>         if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
>>           csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
>> -        csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN);
>> +        if (env->mode == LA64) {
>> +            csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, 
>> VPPN);
>> +        } else {
>> +            csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, 
>> VPPN);
>> +        }
>>           lo0 = env->CSR_TLBRELO0;
>>           lo1 = env->CSR_TLBRELO1;
>>       } else {
>>           csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
>> -        csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI, VPPN);
>> +        if (env->mode == LA64) {
>> +            csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, 
>> VPPN);
>> +        } else {
>> +            csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, 
>> VPPN);
>> +        }
>>           lo0 = env->CSR_TLBELO0;
>>           lo1 = env->CSR_TLBELO1;
>>       }
>> @@ -496,7 +509,7 @@ void helper_tlbfill(CPULoongArchState *env)
>>         if (pagesize == stlb_ps) {
>>           /* Only write into STLB bits [47:13] */
>> -        address = entryhi & ~MAKE_64BIT_MASK(0, 
>> R_CSR_TLBEHI_VPPN_SHIFT);
>> +        address = entryhi & ~MAKE_64BIT_MASK(0, 
>> R_CSR_TLBEHI_64_VPPN_SHIFT);
>>             /* Choose one set ramdomly */
>>           set = get_random_tlb(0, 7);
>>
>

Re: [PATCH v3 1/6] target/loongarch: Add loongarch32 mode for loongarch64-softmmu

[Richard Henderson]

On 8/7/23 02:45, Jiajie Chen wrote:
> This commit adds loongarch32 mode to loongarch64-softmmu.
> 
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
>   target/loongarch/cpu.h | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index fa371ca8ba..43c73e6363 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -272,9 +272,16 @@ struct LoongArchTLB {
>   };
>   typedef struct LoongArchTLB LoongArchTLB;
>   
> +/* Current LoongArch mode */
> +typedef enum LoongArchMode {
> +    LA32 = 0,
> +    LA64 = 1,
> +} LoongArchMode;
> +
>   typedef struct CPUArchState {
>       uint64_t gpr[32];
>       uint64_t pc;
> +    LoongArchMode mode;

This is not how the hardware works.
This data is stored in CPUCFG.1.ARCH.


r~

Re: [PATCH v3 1/6] target/loongarch: Add loongarch32 mode for loongarch64-softmmu

[Jiajie Chen]

On 2023/8/7 23:13, Richard Henderson wrote:
> On 8/7/23 02:45, Jiajie Chen wrote:
>> This commit adds loongarch32 mode to loongarch64-softmmu.
>>
>> Signed-off-by: Jiajie Chen <c@jia.je>
>> ---
>>   target/loongarch/cpu.h | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
>> index fa371ca8ba..43c73e6363 100644
>> --- a/target/loongarch/cpu.h
>> +++ b/target/loongarch/cpu.h
>> @@ -272,9 +272,16 @@ struct LoongArchTLB {
>>   };
>>   typedef struct LoongArchTLB LoongArchTLB;
>>   +/* Current LoongArch mode */
>> +typedef enum LoongArchMode {
>> +    LA32 = 0,
>> +    LA64 = 1,
>> +} LoongArchMode;
>> +
>>   typedef struct CPUArchState {
>>       uint64_t gpr[32];
>>       uint64_t pc;
>> +    LoongArchMode mode;
>
> This is not how the hardware works.
> This data is stored in CPUCFG.1.ARCH.
Okay, I will change to use CFGCFG.1.ARCH instead in v4.
>
>
> r~

Re: [PATCH v3 2/6] target/loongarch: Add loongarch32 cpu la132

[Richard Henderson]

On 8/7/23 02:45, Jiajie Chen wrote:
> Add la132 as a loongarch32 cpu type and allow virt machine to be used
> with la132 instead of la464.
> 
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
>   hw/loongarch/virt.c    |  5 -----
>   target/loongarch/cpu.c | 41 +++++++++++++++++++++++++++++++++++++++++
>   target/loongarch/cpu.h | 11 +++++++++++
>   3 files changed, 52 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
> index e19b042ce8..af15bf5aaa 100644
> --- a/hw/loongarch/virt.c
> +++ b/hw/loongarch/virt.c
> @@ -798,11 +798,6 @@ static void loongarch_init(MachineState *machine)
>           cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
>       }
>   
> -    if (!strstr(cpu_model, "la464")) {
> -        error_report("LoongArch/TCG needs cpu type la464");
> -        exit(1);
> -    }
> -
>       if (ram_size < 1 * GiB) {
>           error_report("ram_size must be greater than 1G.");
>           exit(1);
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index ad93ecac92..d31efe86da 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -362,6 +362,8 @@ static void loongarch_la464_initfn(Object *obj)
>       CPULoongArchState *env = &cpu->env;
>       int i;
>   
> +    env->mode = LA64;
> +
>       for (i = 0; i < 21; i++) {
>           env->cpucfg[i] = 0x0;
>       }
> @@ -439,6 +441,20 @@ static void loongarch_la464_initfn(Object *obj)
>       env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
>   }
>   
> +static void loongarch_la132_initfn(Object *obj)
> +{
> +    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> +    CPULoongArchState *env = &cpu->env;
> +
> +    env->mode = LA32;
> +
> +    cpu->dtb_compatible = "loongarch,Loongson-3C103";
> +
> +    uint32_t data = 0;
> +    data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
> +    env->cpucfg[1] = data;
> +}

This is missing quite a lot of other initialization.  I would expect this to look more 
like loongarch_la464_initfn with quite a lot of CPUCFG settings.

This patch should be sorted after support for LA32 is added to the translator, so that 
when bisecting it is not possible to select this cpu when support is not present.


r~

Re: [PATCH v3 3/6] target/loongarch: Add GDB support for loongarch32 mode

[Richard Henderson]

On 8/7/23 02:45, Jiajie Chen wrote:
> GPRs and PC are 32-bit wide in loongarch32 mode.
> 
> Signed-off-by: Jiajie Chen<c@jia.je>
> ---
>   configs/targets/loongarch64-softmmu.mak |  2 +-
>   gdb-xml/loongarch-base32.xml            | 45 +++++++++++++++++++++++++
>   target/loongarch/cpu.c                  | 10 +++++-
>   target/loongarch/gdbstub.c              | 32 ++++++++++++++----
>   4 files changed, 80 insertions(+), 9 deletions(-)
>   create mode 100644 gdb-xml/loongarch-base32.xml

With the test for LA64 vs LA32 corrected,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

You may wish to use a small inline function for testing the mode.


r~

Re: [PATCH v3 0/6] Add loongarch32 mode for loongarch64-softmmu

[Richard Henderson]

On 8/7/23 02:44, Jiajie Chen wrote:
> This patch series allow qemu-system-loongarch64 to emulate a LoongArch32
> machine. A mode enum is added to CPUArchState to select LA32 or LA64 at
> runtime. A new CPU model is added for loongarch32. Initial GDB support
> is added.
> 
> Changes since v2:
> 
> - Fix typo in previous commit
> - Fix VPPN width in TLBEHI/TLBREHI
> 
> Changes since v1:
> 
> - No longer create a separate qemu-system-loongarch32 executable, but
>    allow user to run loongarch32 emulation using qemu-system-loongarch64
> - Add loongarch32 cpu support for virt machine
> 
> Full changes:
> 
> Jiajie Chen (6):
>    target/loongarch: Add loongarch32 mode for loongarch64-softmmu
>    target/loongarch: Add loongarch32 cpu la132
>    target/loongarch: Add GDB support for loongarch32 mode
>    target/loongarch: Support LoongArch32 TLB entry
>    target/loongarch: Support LoongArch32 DMW
>    target/loongarch: Support LoongArch32 VPPN

There are changes missing for the translator.

All of the doubleword (D) instructions must be rejected in LA32 mode.

Virtual addresses must be zero-extended from 32 bits in 32-bit addressing mode.

I see a note about VA32L1/VA32L2/VA32L3 in CSR.MISC enabling 32-bit address mode for LA64. 
  You would want to implement this with a HW_FLAGS bit which indicates to the translator 
whether 32-bit addressing is enabled in the current mode.  This would always be true for 
LA32, and from MISC for the current priv level for LA64.

There are changes to BL, JIRL and PCADD* to sign-extend in 32-bit address mode.

What happened to the PWCH adjustment from v1?


r~

Re: [PATCH v3 4/6] target/loongarch: Support LoongArch32 TLB entry

[Richard Henderson]

On 8/7/23 02:45, Jiajie Chen wrote:
> The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
> zero in LoongArch32.
> 
> Signed-off-by: Jiajie Chen<c@jia.je>
> ---
>   target/loongarch/cpu-csr.h    |  9 +++++----
>   target/loongarch/tlb_helper.c | 17 ++++++++++++-----
>   2 files changed, 17 insertions(+), 9 deletions(-)

With the test for LA64 vs LA32 corrected,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v3 0/6] Add loongarch32 mode for loongarch64-softmmu

[Jiajie Chen]

On 2023/8/7 23:40, Richard Henderson wrote:
> On 8/7/23 02:44, Jiajie Chen wrote:
>> This patch series allow qemu-system-loongarch64 to emulate a LoongArch32
>> machine. A mode enum is added to CPUArchState to select LA32 or LA64 at
>> runtime. A new CPU model is added for loongarch32. Initial GDB support
>> is added.
>>
>> Changes since v2:
>>
>> - Fix typo in previous commit
>> - Fix VPPN width in TLBEHI/TLBREHI
>>
>> Changes since v1:
>>
>> - No longer create a separate qemu-system-loongarch32 executable, but
>>    allow user to run loongarch32 emulation using qemu-system-loongarch64
>> - Add loongarch32 cpu support for virt machine
>>
>> Full changes:
>>
>> Jiajie Chen (6):
>>    target/loongarch: Add loongarch32 mode for loongarch64-softmmu
>>    target/loongarch: Add loongarch32 cpu la132
>>    target/loongarch: Add GDB support for loongarch32 mode
>>    target/loongarch: Support LoongArch32 TLB entry
>>    target/loongarch: Support LoongArch32 DMW
>>    target/loongarch: Support LoongArch32 VPPN
>
> There are changes missing for the translator.
>
> All of the doubleword (D) instructions must be rejected in LA32 mode.
I was trying to do this, but I failed to figure out how to read the 
current cpucfg when translating instructions to TCP ops. This problem 
applies to the mode-specific behavior below: VA32L1, BL, JIRL, PCADD*, 
PWCH etc.
>
> Virtual addresses must be zero-extended from 32 bits in 32-bit 
> addressing mode.
It is done in the TLB change.
>
> I see a note about VA32L1/VA32L2/VA32L3 in CSR.MISC enabling 32-bit 
> address mode for LA64.  You would want to implement this with a 
> HW_FLAGS bit which indicates to the translator whether 32-bit 
> addressing is enabled in the current mode.  This would always be true 
> for LA32, and from MISC for the current priv level for LA64.
>
> There are changes to BL, JIRL and PCADD* to sign-extend in 32-bit 
> address mode.
>
> What happened to the PWCH adjustment from v1?
>
>
> r~

Re: [PATCH v3 5/6] target/loongarch: Support LoongArch32 DMW

[Richard Henderson]

On 8/7/23 02:45, Jiajie Chen wrote:
> LA32 uses a different encoding for CSR.DMW and a new direct mapping
> mechanism.
> 
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
>   target/loongarch/cpu-csr.h    |  7 +++----
>   target/loongarch/tlb_helper.c | 31 ++++++++++++++++++++++++++++---
>   2 files changed, 31 insertions(+), 7 deletions(-)
> 
> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
> index 48ed2e0632..b93f99a9ef 100644
> --- a/target/loongarch/cpu-csr.h
> +++ b/target/loongarch/cpu-csr.h
> @@ -188,10 +188,9 @@ FIELD(CSR_DMW, PLV1, 1, 1)
>   FIELD(CSR_DMW, PLV2, 2, 1)
>   FIELD(CSR_DMW, PLV3, 3, 1)
>   FIELD(CSR_DMW, MAT, 4, 2)
> -FIELD(CSR_DMW, VSEG, 60, 4)
> -
> -#define dmw_va2pa(va) \
> -    (va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS))
> +FIELD(CSR_DMW_32, PSEG, 25, 3)
> +FIELD(CSR_DMW_32, VSEG, 29, 3)
> +FIELD(CSR_DMW_64, VSEG, 60, 4)
>   
>   /* Debug CSRs */
>   #define LOONGARCH_CSR_DBG            0x500 /* debug config */
> diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
> index 690c6ef25f..cf6f5863f9 100644
> --- a/target/loongarch/tlb_helper.c
> +++ b/target/loongarch/tlb_helper.c
> @@ -173,6 +173,18 @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
>       return TLBRET_NOMATCH;
>   }
>   
> +static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
> +                        target_ulong dmw)
> +{
> +    if (env->mode == LA64) {
> +        return va & TARGET_PHYS_MASK;
> +    } else {
> +        uint32_t pseg = FIELD_EX32(dmw, CSR_DMW_32, PSEG);
> +        return (va & MAKE_64BIT_MASK(0, R_CSR_DMW_32_VSEG_SHIFT)) | \
> +            (pseg << R_CSR_DMW_32_VSEG_SHIFT);
> +    }
> +}
> +
>   static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
>                                   int *prot, target_ulong address,
>                                   MMUAccessType access_type, int mmu_idx)
> @@ -184,6 +196,11 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
>       uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
>       uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
>   
> +    /* Truncate high 32 bits for LA32 */
> +    if (env->mode == LA32) {
> +        address = (uint32_t)address;
> +    }

You need to do this in the translator, because this also depends on VA32L* and the current 
priv level.

Otherwise the window manipulation looks correct.


r~

Re: [PATCH v3 0/6] Add loongarch32 mode for loongarch64-softmmu

[Richard Henderson]

On 8/7/23 08:43, Jiajie Chen wrote:
>> There are changes missing for the translator.
>>
>> All of the doubleword (D) instructions must be rejected in LA32 mode.
> I was trying to do this, but I failed to figure out how to read the current cpucfg when 
> translating instructions to TCP ops. This problem applies to the mode-specific behavior 
> below: VA32L1, BL, JIRL, PCADD*, PWCH etc.

Because the CPUCFG values are constant, you may read them in 
loongarch_tr_init_disas_context and save the value in DisasContext.  This is sufficient 
for LA32 vs LA64.

But virtual address width should be in HW_FLAGS and may be read from ctx->base.tb->flags. 
You may wish to simplify usage throughout the translation routines by extracting a 'bool 
va32' in loongarch_tr_init_disas_context.


r~

Re: [PATCH v3 0/6] Add loongarch32 mode for loongarch64-softmmu

[Jiajie Chen]

On 2023/8/7 23:56, Richard Henderson wrote:
> On 8/7/23 08:43, Jiajie Chen wrote:
>>> There are changes missing for the translator.
>>>
>>> All of the doubleword (D) instructions must be rejected in LA32 mode.
>> I was trying to do this, but I failed to figure out how to read the 
>> current cpucfg when translating instructions to TCP ops. This problem 
>> applies to the mode-specific behavior below: VA32L1, BL, JIRL, 
>> PCADD*, PWCH etc.
>
> Because the CPUCFG values are constant, you may read them in 
> loongarch_tr_init_disas_context and save the value in DisasContext.  
> This is sufficient for LA32 vs LA64.
>
> But virtual address width should be in HW_FLAGS and may be read from 
> ctx->base.tb->flags. You may wish to simplify usage throughout the 
> translation routines by extracting a 'bool va32' in 
> loongarch_tr_init_disas_context.
Thank you very much, I will rewrite the code to use this approach.
>
>
> r~

Re: [PATCH v3 5/6] target/loongarch: Support LoongArch32 DMW

[Jiajie Chen]

On 2023/8/7 23:50, Richard Henderson wrote:
> On 8/7/23 02:45, Jiajie Chen wrote:
>> LA32 uses a different encoding for CSR.DMW and a new direct mapping
>> mechanism.
>>
>> Signed-off-by: Jiajie Chen <c@jia.je>
>> ---
>>   target/loongarch/cpu-csr.h    |  7 +++----
>>   target/loongarch/tlb_helper.c | 31 ++++++++++++++++++++++++++++---
>>   2 files changed, 31 insertions(+), 7 deletions(-)
>>
>> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
>> index 48ed2e0632..b93f99a9ef 100644
>> --- a/target/loongarch/cpu-csr.h
>> +++ b/target/loongarch/cpu-csr.h
>> @@ -188,10 +188,9 @@ FIELD(CSR_DMW, PLV1, 1, 1)
>>   FIELD(CSR_DMW, PLV2, 2, 1)
>>   FIELD(CSR_DMW, PLV3, 3, 1)
>>   FIELD(CSR_DMW, MAT, 4, 2)
>> -FIELD(CSR_DMW, VSEG, 60, 4)
>> -
>> -#define dmw_va2pa(va) \
>> -    (va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS))
>> +FIELD(CSR_DMW_32, PSEG, 25, 3)
>> +FIELD(CSR_DMW_32, VSEG, 29, 3)
>> +FIELD(CSR_DMW_64, VSEG, 60, 4)
>>     /* Debug CSRs */
>>   #define LOONGARCH_CSR_DBG            0x500 /* debug config */
>> diff --git a/target/loongarch/tlb_helper.c 
>> b/target/loongarch/tlb_helper.c
>> index 690c6ef25f..cf6f5863f9 100644
>> --- a/target/loongarch/tlb_helper.c
>> +++ b/target/loongarch/tlb_helper.c
>> @@ -173,6 +173,18 @@ static int 
>> loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
>>       return TLBRET_NOMATCH;
>>   }
>>   +static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
>> +                        target_ulong dmw)
>> +{
>> +    if (env->mode == LA64) {
>> +        return va & TARGET_PHYS_MASK;
>> +    } else {
>> +        uint32_t pseg = FIELD_EX32(dmw, CSR_DMW_32, PSEG);
>> +        return (va & MAKE_64BIT_MASK(0, R_CSR_DMW_32_VSEG_SHIFT)) | \
>> +            (pseg << R_CSR_DMW_32_VSEG_SHIFT);
>> +    }
>> +}
>> +
>>   static int get_physical_address(CPULoongArchState *env, hwaddr 
>> *physical,
>>                                   int *prot, target_ulong address,
>>                                   MMUAccessType access_type, int 
>> mmu_idx)
>> @@ -184,6 +196,11 @@ static int 
>> get_physical_address(CPULoongArchState *env, hwaddr *physical,
>>       uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
>>       uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
>>   +    /* Truncate high 32 bits for LA32 */
>> +    if (env->mode == LA32) {
>> +        address = (uint32_t)address;
>> +    }
>
> You need to do this in the translator, because this also depends on 
> VA32L* and the current priv level.
Could you please elaborate on this? I am checking LA32 and VA32L* in 
get_physical_address() currently, the current priv level is read from 
mmu_idx(or alternatively, read from env->CSR_CRMD), and I am unsure how 
to do this in the translator.
>
> Otherwise the window manipulation looks correct.
>
>
> r~

Re: [PATCH v3 5/6] target/loongarch: Support LoongArch32 DMW

[Richard Henderson]

On 8/7/23 10:32, Jiajie Chen wrote:
>>>       uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
>>>       uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
>>>   +    /* Truncate high 32 bits for LA32 */
>>> +    if (env->mode == LA32) {
>>> +        address = (uint32_t)address;
>>> +    }
>>
>> You need to do this in the translator, because this also depends on VA32L* and the 
>> current priv level.
> Could you please elaborate on this? I am checking LA32 and VA32L* in 
> get_physical_address() currently, the current priv level is read from mmu_idx(or 
> alternatively, read from env->CSR_CRMD), and I am unsure how to do this in the translator.

In insn_trans/trans_memory.c.inc, gen_load, we compute the address,


>     TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
> 
>     if (a->imm) {
>         TCGv temp = tcg_temp_new();
>         tcg_gen_addi_tl(temp, addr, a->imm);
>         addr = temp;
>     }

One would use

     if (ctx->va32) {
         tcg_gen_ext32u_tl(temp, addr);
         addr = temp;
     }

to zero-extend the address.  You would want to create no more than one temporary for the 
entire computation.

You would need to modify all of the places which generate an address for tcg_gen_qemu_*: 
gen_load*, gen_store*, gen_ldptr, gen_stptr.  Also trans_fmemory.c.inc and trans_lsx.c.inc.

I would strongly suggest creating helper functions, so that all of the addition and 
extension is done in one place, and not in lots of places as we do now.

If this sounds like more work than just changing get_physical_address, and it is.  But it 
works better with the softmmu tlb.  If you clear upper bits late, then you get false 
conflicts in the tlb, and extra tlb fills.



r~