* [igt-dev] [PATCH i-g-t v2 0/2] lib/xe_spin: introduced fixed duration xe_spin
@ 2023-08-18 10:21 Marcin Bernatowicz
2023-08-18 10:21 ` [igt-dev] [PATCH i-g-t v2 1/2] lib/xe_spin: fixed duration xe_spin capability Marcin Bernatowicz
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Marcin Bernatowicz @ 2023-08-18 10:21 UTC (permalink / raw)
To: igt-dev
Introduced struct xe_spin_opts for xe_spin initialization,
adjusted tests to new xe_spin_init signature.
Extended spinner with fixed duration capability. It allows
to prepare fixed duration (ex. 10ms) workloads and take workloads/second
measurements, a handy utility for scheduling tests.
Basic test for xe_spin with fixed duration.
v2: - added asserts in div64_u64_round_up, duration_to_ctx_ticks,
simplified loop_addr (Zbyszek)
- added xe_spin_init_opts macro (Zbyszek)
- corrected patch title (Kamil)
- Added assert for expected spinner duration. (Zbyszek)
A median of 5x100ms spins duration is computed, which should
satisfy CI runs, although better accuracy is achieved with
disabled logging (echo 0 > /sys/module/drm/parameters/debug).
Marcin Bernatowicz (2):
lib/xe_spin: fixed duration xe_spin capability
tests/xe_spin_batch: spin-fixed-duration
lib/xe/xe_spin.c | 121 ++++++++++++++++++++++++++++++------
lib/xe/xe_spin.h | 27 +++++++-
tests/xe/xe_dma_buf_sync.c | 6 +-
tests/xe/xe_exec_balancer.c | 9 ++-
tests/xe/xe_exec_reset.c | 24 ++++---
tests/xe/xe_exec_threads.c | 7 ++-
tests/xe/xe_spin_batch.c | 72 +++++++++++++++++++++
tests/xe/xe_vm.c | 9 +--
8 files changed, 230 insertions(+), 45 deletions(-)
--
2.30.2
^ permalink raw reply [flat|nested] 11+ messages in thread* [igt-dev] [PATCH i-g-t v2 1/2] lib/xe_spin: fixed duration xe_spin capability 2023-08-18 10:21 [igt-dev] [PATCH i-g-t v2 0/2] lib/xe_spin: introduced fixed duration xe_spin Marcin Bernatowicz @ 2023-08-18 10:21 ` Marcin Bernatowicz 2023-08-18 10:21 ` [igt-dev] [PATCH i-g-t v2 2/2] tests/xe_spin_batch: spin-fixed-duration Marcin Bernatowicz ` (5 subsequent siblings) 6 siblings, 0 replies; 11+ messages in thread From: Marcin Bernatowicz @ 2023-08-18 10:21 UTC (permalink / raw) To: igt-dev Introduced struct xe_spin_opts for xe_spin initialization, adjusted tests to new xe_spin_init signature. Extended spinner with fixed duration capability. It allows to prepare fixed duration (ex. 10ms) workloads and take workloads/second measurements, a handy utility for scheduling tests. v2: - added asserts in div64_u64_round_up, duration_to_ctx_ticks, simplified loop_addr (Zbyszek) - added xe_spin_init_opts macro (Zbyszek) - corrected patch title (Kamil) Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> --- lib/xe/xe_spin.c | 121 ++++++++++++++++++++++++++++++------ lib/xe/xe_spin.h | 27 +++++++- tests/xe/xe_dma_buf_sync.c | 6 +- tests/xe/xe_exec_balancer.c | 9 ++- tests/xe/xe_exec_reset.c | 24 ++++--- tests/xe/xe_exec_threads.c | 7 ++- tests/xe/xe_vm.c | 9 +-- 7 files changed, 158 insertions(+), 45 deletions(-) diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c index cd9c1a7d3..6cd2ae281 100644 --- a/lib/xe/xe_spin.c +++ b/lib/xe/xe_spin.c @@ -16,41 +16,130 @@ #include "xe_ioctl.h" #include "xe_spin.h" +static uint32_t read_timestamp_frequency(int fd, int gt_id) +{ + struct xe_device *dev = xe_device_get(fd); + + igt_assert(dev && dev->gts && dev->gts->num_gt); + igt_assert(gt_id >= 0 && gt_id <= dev->gts->num_gt); + + return dev->gts->gts[gt_id].clock_freq; +} + +static uint64_t div64_u64_round_up(const uint64_t x, const uint64_t y) +{ + igt_assert(y > 0); + + return (x + y - 1) / y; +} + +/** + * duration_to_ctx_ticks: + * @fd: opened device + * @gt_id: tile id + * @duration_ns: duration in nanoseconds to be converted to context timestamp ticks + * @return: duration converted to context timestamp ticks. + */ +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t duration_ns) +{ + uint32_t f = read_timestamp_frequency(fd, gt_id); + uint64_t ctx_ticks = div64_u64_round_up(duration_ns * f, NSEC_PER_SEC); + + igt_assert_lt_u64(ctx_ticks, XE_SPIN_MAX_CTX_TICKS); + + return ctx_ticks; +} + +#define MI_SRM_CS_MMIO (1 << 19) +#define MI_LRI_CS_MMIO (1 << 19) +#define MI_LRR_DST_CS_MMIO (1 << 19) +#define MI_LRR_SRC_CS_MMIO (1 << 18) +#define CTX_TIMESTAMP 0x3a8; +#define CS_GPR(x) (0x600 + 8 * (x)) +enum { START_TS, NOW_TS }; + /** * xe_spin_init: * @spin: pointer to mapped bo in which spinner code will be written - * @addr: offset of spinner within vm - * @preempt: allow spinner to be preempted or not + * @opts: pointer to spinner initialization options */ -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt) +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts) { - uint64_t batch_offset = (char *)&spin->batch - (char *)spin; - uint64_t batch_addr = addr + batch_offset; - uint64_t start_offset = (char *)&spin->start - (char *)spin; - uint64_t start_addr = addr + start_offset; - uint64_t end_offset = (char *)&spin->end - (char *)spin; - uint64_t end_addr = addr + end_offset; + uint64_t loop_addr; + uint64_t start_addr = opts->addr + offsetof(struct xe_spin, start); + uint64_t end_addr = opts->addr + offsetof(struct xe_spin, end); + uint64_t ticks_delta_addr = opts->addr + offsetof(struct xe_spin, ticks_delta); + uint64_t pad_addr = opts->addr + offsetof(struct xe_spin, pad); int b = 0; spin->start = 0; spin->end = 0xffffffff; + spin->ticks_delta = 0; + + if (opts->ctx_ticks) { + /* store start timestamp */ + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; + spin->batch[b++] = CS_GPR(START_TS) + 4; + spin->batch[b++] = 0; + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; + spin->batch[b++] = CTX_TIMESTAMP; + spin->batch[b++] = CS_GPR(START_TS); + } + + loop_addr = opts->addr + b * sizeof(uint32_t); spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; spin->batch[b++] = start_addr; spin->batch[b++] = start_addr >> 32; spin->batch[b++] = 0xc0ffee; - if (preempt) + if (opts->preempt) spin->batch[b++] = (0x5 << 23); + if (opts->ctx_ticks) { + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; + spin->batch[b++] = CS_GPR(NOW_TS) + 4; + spin->batch[b++] = 0; + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; + spin->batch[b++] = CTX_TIMESTAMP; + spin->batch[b++] = CS_GPR(NOW_TS); + + /* delta = now - start; inverted to match COND_BBE */ + spin->batch[b++] = MI_MATH(4); + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + spin->batch[b++] = MI_MATH_SUB; + spin->batch[b++] = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + /* Save delta for reading by COND_BBE */ + spin->batch[b++] = MI_STORE_REGISTER_MEM | MI_SRM_CS_MMIO | 2; + spin->batch[b++] = CS_GPR(NOW_TS); + spin->batch[b++] = ticks_delta_addr; + spin->batch[b++] = ticks_delta_addr >> 32; + + /* Delay between SRM and COND_BBE to post the writes */ + for (int n = 0; n < 8; n++) { + spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; + spin->batch[b++] = pad_addr; + spin->batch[b++] = pad_addr >> 32; + spin->batch[b++] = 0xc0ffee; + } + + /* Break if delta [time elapsed] > ns */ + spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; + spin->batch[b++] = ~(opts->ctx_ticks); + spin->batch[b++] = ticks_delta_addr; + spin->batch[b++] = ticks_delta_addr >> 32; + } + spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; spin->batch[b++] = 0; spin->batch[b++] = end_addr; spin->batch[b++] = end_addr >> 32; spin->batch[b++] = MI_BATCH_BUFFER_START | 1 << 8 | 1; - spin->batch[b++] = batch_addr; - spin->batch[b++] = batch_addr >> 32; + spin->batch[b++] = loop_addr; + spin->batch[b++] = loop_addr >> 32; igt_assert(b <= ARRAY_SIZE(spin->batch)); } @@ -132,11 +221,7 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt) addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size); - if (!(opt->flags & IGT_SPIN_NO_PREEMPTION)) - xe_spin_init(xe_spin, addr, true); - else - xe_spin_init(xe_spin, addr, false); - + xe_spin_init_opts(xe_spin, .addr = addr, .preempt = !(opt->flags & IGT_SPIN_NO_PREEMPTION)); exec.exec_queue_id = spin->engine; exec.address = addr; sync.handle = spin->syncobj; @@ -211,7 +296,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe, exec_queue = xe_exec_queue_create(fd, vm, hwe, 0); syncobj = syncobj_create(fd, 0); - xe_spin_init(spin, addr, true); + xe_spin_init_opts(spin, .addr = addr, .preempt = true); exec.exec_queue_id = exec_queue; exec.address = addr; sync.handle = syncobj; diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h index c84db175d..f1abc1102 100644 --- a/lib/xe/xe_spin.h +++ b/lib/xe/xe_spin.h @@ -15,15 +15,38 @@ #include "xe_query.h" #include "lib/igt_dummyload.h" +#define XE_SPIN_MAX_CTX_TICKS UINT32_MAX - 1000 + +/** struct xe_spin_opts + * + * @addr: offset of spinner within vm + * @preempt: allow spinner to be preempted or not + * @ctx_ticks: number of ticks after which spinner is stopped, applied if > 0 + * + * Used to initialize struct xe_spin spinner behavior. + */ +struct xe_spin_opts { + uint64_t addr; + bool preempt; + uint32_t ctx_ticks; +}; + /* Mapped GPU object */ struct xe_spin { - uint32_t batch[16]; + uint32_t batch[128]; uint64_t pad; uint32_t start; uint32_t end; + uint32_t ticks_delta; }; + igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt); -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt); +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns); +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts); + +#define xe_spin_init_opts(fd, ...) \ + xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__})) + bool xe_spin_started(struct xe_spin *spin); void xe_spin_sync_wait(int fd, struct igt_spin *spin); void xe_spin_wait_started(struct xe_spin *spin); diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c index 29d675154..627f4c1e5 100644 --- a/tests/xe/xe_dma_buf_sync.c +++ b/tests/xe/xe_dma_buf_sync.c @@ -144,7 +144,6 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, uint64_t sdi_offset = (char *)&data[i]->data - (char *)data[i]; uint64_t sdi_addr = addr + sdi_offset; uint64_t spin_offset = (char *)&data[i]->spin - (char *)data[i]; - uint64_t spin_addr = addr + spin_offset; struct drm_xe_sync sync[2] = { { .flags = DRM_XE_SYNC_SYNCOBJ, }, { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }, @@ -153,14 +152,15 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, .num_batch_buffer = 1, .syncs = to_user_pointer(sync), }; + struct xe_spin_opts spin_opts = { .addr = addr + spin_offset, .preempt = true }; uint32_t syncobj; int b = 0; int sync_fd; /* Write spinner on FD[0] */ - xe_spin_init(&data[i]->spin, spin_addr, true); + xe_spin_init(&data[i]->spin, &spin_opts); exec.exec_queue_id = exec_queue[0]; - exec.address = spin_addr; + exec.address = spin_opts.addr; xe_exec(fd[0], &exec); /* Export prime BO as sync file and veify business */ diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c index f364a4b7a..d7d8dd8fb 100644 --- a/tests/xe/xe_exec_balancer.c +++ b/tests/xe/xe_exec_balancer.c @@ -52,6 +52,7 @@ static void test_all_active(int fd, int gt, int class) struct { struct xe_spin spin; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; struct drm_xe_engine_class_instance *hwe; struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; int i, num_placements = 0; @@ -90,16 +91,14 @@ static void test_all_active(int fd, int gt, int class) xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); for (i = 0; i < num_placements; i++) { - uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = addr + spin_offset; - - xe_spin_init(&data[i].spin, spin_addr, false); + spin_opts.addr = addr + (char *)&data[i].spin - (char *)data; + xe_spin_init(&data[i].spin, &spin_opts); sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; sync[1].flags |= DRM_XE_SYNC_SIGNAL; sync[1].handle = syncobjs[i]; exec.exec_queue_id = exec_queues[i]; - exec.address = spin_addr; + exec.address = spin_opts.addr; xe_exec(fd, &exec); xe_spin_wait_started(&data[i].spin); } diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c index a2d33baf1..be6bbada6 100644 --- a/tests/xe/xe_exec_reset.c +++ b/tests/xe/xe_exec_reset.c @@ -44,6 +44,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) size_t bo_size; uint32_t bo = 0; struct xe_spin *spin; + struct xe_spin_opts spin_opts = { .addr = addr, .preempt = false }; vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); bo_size = sizeof(*spin); @@ -60,7 +61,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) sync[0].handle = syncobj_create(fd, 0); xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); - xe_spin_init(spin, addr, false); + xe_spin_init(spin, &spin_opts); sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; sync[1].flags |= DRM_XE_SYNC_SIGNAL; @@ -165,6 +166,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; struct drm_xe_engine_class_instance *hwe; struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; int i, j, b, num_placements = 0, bad_batches = 1; @@ -236,7 +238,6 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = base_addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = base_addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = base_addr + sdi_offset; uint64_t exec_addr; @@ -247,8 +248,9 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, batches[j] = batch_addr; if (i < bad_batches) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = base_addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; @@ -368,6 +370,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; int i, b; igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); @@ -417,15 +420,15 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = base_addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = base_addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = base_addr + sdi_offset; uint64_t exec_addr; int e = i % n_exec_queues; if (!i) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = base_addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; @@ -539,6 +542,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t exec_sync; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; int i, b; igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); @@ -593,15 +597,15 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = base_addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = base_addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = base_addr + sdi_offset; uint64_t exec_addr; int e = i % n_exec_queues; if (!i) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = base_addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c index e64c1639a..ff4ebc280 100644 --- a/tests/xe/xe_exec_threads.c +++ b/tests/xe/xe_exec_threads.c @@ -486,6 +486,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; int i, j, b, hang_exec_queue = n_exec_queues / 2; bool owns_vm = false, owns_fd = false; @@ -562,15 +563,15 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = addr + sdi_offset; uint64_t exec_addr; int e = i % n_exec_queues; if (flags & HANG && e == hang_exec_queue && i == e) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c index e42c04e33..87604a407 100644 --- a/tests/xe/xe_vm.c +++ b/tests/xe/xe_vm.c @@ -727,6 +727,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = true }; int i, b; vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); @@ -755,14 +756,14 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = addr + sdi_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = addr + spin_offset; int e = i; if (i == 0) { - /* Cork 1st exec_queue with a spinner */ - xe_spin_init(&data[i].spin, spin_addr, true); + /* Cork 1st engine with a spinner */ + spin_opts.addr = addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); exec.exec_queue_id = exec_queues[e]; - exec.address = spin_addr; + exec.address = spin_opts.addr; sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; sync[1].flags |= DRM_XE_SYNC_SIGNAL; sync[1].handle = syncobjs[e]; -- 2.30.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v2 2/2] tests/xe_spin_batch: spin-fixed-duration 2023-08-18 10:21 [igt-dev] [PATCH i-g-t v2 0/2] lib/xe_spin: introduced fixed duration xe_spin Marcin Bernatowicz 2023-08-18 10:21 ` [igt-dev] [PATCH i-g-t v2 1/2] lib/xe_spin: fixed duration xe_spin capability Marcin Bernatowicz @ 2023-08-18 10:21 ` Marcin Bernatowicz 2023-08-18 11:10 ` [igt-dev] ✗ GitLab.Pipeline: warning for lib/xe_spin: introduced fixed duration xe_spin Patchwork ` (4 subsequent siblings) 6 siblings, 0 replies; 11+ messages in thread From: Marcin Bernatowicz @ 2023-08-18 10:21 UTC (permalink / raw) To: igt-dev Basic test for xe_spin with fixed duration. v2: Added assert for expected spinner duration. (Zbyszek) A median of 5x100ms spins duration is computed, which should satisfy CI runs, although better accuracy is achieved with disabled logging (echo 0 > /sys/module/drm/parameters/debug). Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> --- tests/xe/xe_spin_batch.c | 72 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c index 26f9daf36..6dcd89558 100644 --- a/tests/xe/xe_spin_batch.c +++ b/tests/xe/xe_spin_batch.c @@ -1,8 +1,10 @@ #include "igt.h" +#include "igt_syncobj.h" #include "lib/intel_reg.h" #include "xe_drm.h" #include "xe/xe_ioctl.h" #include "xe/xe_query.h" +#include "xe/xe_spin.h" /** * TEST: Tests for spin batch submissons. @@ -138,6 +140,73 @@ static void spin_all(int fd, int gt, int class) xe_vm_destroy(fd, vm); } +/** + * SUBTEST: spin-fixed-duration + * Description: Basic test which validates the functionality of xe_spin with fixed duration. + * Run type: FULL + */ +static void xe_spin_fixed_duration(int fd) +{ + uint64_t ahnd; + uint32_t vm; + unsigned int exec_queue; + uint32_t bo; + size_t bo_size; + struct xe_spin *spin; + uint64_t spin_addr; + struct drm_xe_sync sync = { + .handle = syncobj_create(fd, 0), + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, + }; + struct drm_xe_exec exec = { + .num_batch_buffer = 1, + .num_syncs = 1, + .syncs = to_user_pointer(&sync), + }; + struct timespec tv; + const uint64_t duration_ns = NSEC_PER_SEC / 10; /* 100ms */ + double elapsed_ms; + int i; + igt_stats_t stats; + + vm = xe_vm_create(fd, 0, 0); + exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC); + bo_size = ALIGN(sizeof(*spin) + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); + bo = xe_bo_create(fd, 0, vm, bo_size); + spin = xe_bo_map(fd, bo, bo_size); + spin_addr = intel_allocator_alloc_with_strategy(ahnd, bo, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); + xe_vm_bind_sync(fd, vm, bo, 0, spin_addr, bo_size); + xe_spin_init_opts(spin, .addr = spin_addr, + .preempt = true, + .ctx_ticks = duration_to_ctx_ticks(fd, 0, duration_ns)); + exec.address = spin_addr; + exec.exec_queue_id = exec_queue; + +#define NSAMPLES 5 + igt_stats_init_with_size(&stats, NSAMPLES); + for (i = 0; i < NSAMPLES; ++i) { + igt_gettime(&tv); + xe_exec(fd, &exec); + xe_spin_wait_started(spin); + igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL)); + igt_stats_push_float(&stats, igt_nsec_elapsed(&tv) * 1e-6); + syncobj_reset(fd, &sync.handle, 1); + igt_debug("i=%d %.2fms\n", i, stats.values_f[i]); + } + elapsed_ms = igt_stats_get_median(&stats); + igt_info("%.0fms spin took %.2fms (median)\n", duration_ns * 1e-6, elapsed_ms); + igt_assert(elapsed_ms < duration_ns * 1.5e-6 && elapsed_ms > duration_ns * 0.5e-6); + + xe_vm_unbind_sync(fd, vm, 0, spin_addr, bo_size); + syncobj_destroy(fd, sync.handle); + gem_munmap(spin, bo_size); + gem_close(fd, bo); + xe_exec_queue_destroy(fd, exec_queue); + xe_vm_destroy(fd, vm); + put_ahnd(ahnd); +} + igt_main { struct drm_xe_engine_class_instance *hwe; @@ -163,6 +232,9 @@ igt_main spin_all(fd, gt, class); } + igt_subtest("spin-fixed-duration") + xe_spin_fixed_duration(fd); + igt_fixture drm_close_driver(fd); } -- 2.30.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: warning for lib/xe_spin: introduced fixed duration xe_spin 2023-08-18 10:21 [igt-dev] [PATCH i-g-t v2 0/2] lib/xe_spin: introduced fixed duration xe_spin Marcin Bernatowicz 2023-08-18 10:21 ` [igt-dev] [PATCH i-g-t v2 1/2] lib/xe_spin: fixed duration xe_spin capability Marcin Bernatowicz 2023-08-18 10:21 ` [igt-dev] [PATCH i-g-t v2 2/2] tests/xe_spin_batch: spin-fixed-duration Marcin Bernatowicz @ 2023-08-18 11:10 ` Patchwork 2023-08-18 11:29 ` [igt-dev] ○ CI.xeBAT: info " Patchwork ` (3 subsequent siblings) 6 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2023-08-18 11:10 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev == Series Details == Series: lib/xe_spin: introduced fixed duration xe_spin URL : https://patchwork.freedesktop.org/series/122624/ State : warning == Summary == Pipeline status: FAILED. see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/964649 for the overview. containers:igt has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/47656458): Downloading artifacts for build:tests-fedora (47656443)... Downloading artifacts from coordinator... ok host=gitlab.freedesktop.org id=47656443 responseStatus=200 OK token=64_MB1tt section_end:1692356964:download_artifacts section_start:1692356964:step_script Executing "step_script" stage of the job script Using docker image sha256:594aa868d31ee3304dee8cae8a3433c89a6fcfcf6c7d420c04cce22f60147176 for registry.freedesktop.org/wayland/ci-templates/buildah:2019-08-13.0 with digest registry.freedesktop.org/wayland/ci-templates/buildah@sha256:7dbcf22cd2c1c7d49db0dc7b4ab207c3d6a4a09bd81cc3b71a688d3727d8749f ... $ /host/bin/curl -s -L --cacert /host/ca-certificates.crt --retry 4 -f --retry-delay 60 https://gitlab.freedesktop.org/freedesktop/helm-gitlab-infra/-/raw/main/runner-gating/runner-gating.sh | sh Checking if the user of the pipeline is allowed... Checking if the job's project is part of a well-known group... Thank you for contributing to freedesktop.org $ podman login -u gitlab-ci-token -p $CI_JOB_TOKEN $CI_REGISTRY Login Succeeded! $ .gitlab-ci/pull-or-rebuild.sh igt Dockerfile igt Error: could not get runtime: error configuring CNI network plugin: could not create new watcher too many open files section_end:1692356965:step_script section_start:1692356965:cleanup_file_variables Cleaning up project directory and file based variables section_end:1692356966:cleanup_file_variables ERROR: Job failed: exit code 1 == Logs == For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/964649 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] ○ CI.xeBAT: info for lib/xe_spin: introduced fixed duration xe_spin 2023-08-18 10:21 [igt-dev] [PATCH i-g-t v2 0/2] lib/xe_spin: introduced fixed duration xe_spin Marcin Bernatowicz ` (2 preceding siblings ...) 2023-08-18 11:10 ` [igt-dev] ✗ GitLab.Pipeline: warning for lib/xe_spin: introduced fixed duration xe_spin Patchwork @ 2023-08-18 11:29 ` Patchwork 2023-08-18 11:43 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 6 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2023-08-18 11:29 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 334 bytes --] == Series Details == Series: lib/xe_spin: introduced fixed duration xe_spin URL : https://patchwork.freedesktop.org/series/122624/ State : info == Summary == Participating hosts: bat-atsm-2 bat-dg2-oem2 bat-adlp-7 Missing hosts results[0]: Results: [IGTPW_9621](https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9621/index.html) [-- Attachment #2: Type: text/html, Size: 844 bytes --] ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for lib/xe_spin: introduced fixed duration xe_spin 2023-08-18 10:21 [igt-dev] [PATCH i-g-t v2 0/2] lib/xe_spin: introduced fixed duration xe_spin Marcin Bernatowicz ` (3 preceding siblings ...) 2023-08-18 11:29 ` [igt-dev] ○ CI.xeBAT: info " Patchwork @ 2023-08-18 11:43 ` Patchwork 2023-08-19 16:59 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 0/3] " Marcin Bernatowicz 6 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2023-08-18 11:43 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 2893 bytes --] == Series Details == Series: lib/xe_spin: introduced fixed duration xe_spin URL : https://patchwork.freedesktop.org/series/122624/ State : success == Summary == CI Bug Log - changes from CI_DRM_13536 -> IGTPW_9621 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/index.html Participating hosts (38 -> 37) ------------------------------ Missing (1): fi-snb-2520m Known issues ------------ Here are the changes found in IGTPW_9621 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@hangcheck: - fi-skl-guc: [PASS][1] -> [DMESG-FAIL][2] ([i915#8723]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/fi-skl-guc/igt@i915_selftest@live@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/fi-skl-guc/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [PASS][3] -> [DMESG-WARN][4] ([i915#7699]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/bat-dg2-11/igt@i915_selftest@live@migrate.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/bat-dg2-11/igt@i915_selftest@live@migrate.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1: - bat-rplp-1: [PASS][5] -> [ABORT][6] ([i915#8442] / [i915#8668]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html #### Warnings #### * igt@i915_module_load@load: - bat-adlp-11: [DMESG-WARN][7] ([i915#4423]) -> [ABORT][8] ([i915#4423]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/bat-adlp-11/igt@i915_module_load@load.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/bat-adlp-11/igt@i915_module_load@load.html [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#8723]: https://gitlab.freedesktop.org/drm/intel/issues/8723 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7444 -> IGTPW_9621 CI-20190529: 20190529 CI_DRM_13536: 7a825a06c6ee60a6586ddf8b4adb03ea5262bda7 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_9621: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/index.html IGT_7444: 7444 Testlist changes ---------------- +igt@xe_spin_batch@spin-fixed-duration == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/index.html [-- Attachment #2: Type: text/html, Size: 3630 bytes --] ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for lib/xe_spin: introduced fixed duration xe_spin 2023-08-18 10:21 [igt-dev] [PATCH i-g-t v2 0/2] lib/xe_spin: introduced fixed duration xe_spin Marcin Bernatowicz ` (4 preceding siblings ...) 2023-08-18 11:43 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork @ 2023-08-19 16:59 ` Patchwork 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 0/3] " Marcin Bernatowicz 6 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2023-08-19 16:59 UTC (permalink / raw) To: Bernatowicz, Marcin; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 79729 bytes --] == Series Details == Series: lib/xe_spin: introduced fixed duration xe_spin URL : https://patchwork.freedesktop.org/series/122624/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13536_full -> IGTPW_9621_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_9621_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_9621_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/index.html Participating hosts (9 -> 9) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_9621_full: ### IGT changes ### #### Possible regressions #### * igt@gem_ppgtt@shrink-vs-evict-any: - shard-rkl: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-rkl-7/igt@gem_ppgtt@shrink-vs-evict-any.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-2/igt@gem_ppgtt@shrink-vs-evict-any.html Known issues ------------ Here are the changes found in IGTPW_9621_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@blit-reloc-purge-cache: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#8411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@api_intel_bb@blit-reloc-purge-cache.html - shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8411]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-5/igt@api_intel_bb@blit-reloc-purge-cache.html * igt@api_intel_bb@render-ccs: - shard-dg2: NOTRUN -> [FAIL][5] ([i915#6122]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@api_intel_bb@render-ccs.html * igt@drm_fdinfo@busy-check-all@bcs0: - shard-dg1: NOTRUN -> [SKIP][6] ([i915#8414]) +4 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-17/igt@drm_fdinfo@busy-check-all@bcs0.html * igt@drm_fdinfo@busy-idle@bcs0: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#8414]) +30 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@drm_fdinfo@busy-idle@bcs0.html * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][8] -> [FAIL][9] ([i915#7742]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-7/igt@drm_fdinfo@most-busy-check-all@rcs0.html * igt@drm_fdinfo@virtual-busy-all: - shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8414]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-3/igt@drm_fdinfo@virtual-busy-all.html * igt@gem_busy@semaphore: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#3936]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@gem_busy@semaphore.html * igt@gem_ccs@block-copy-compressed: - shard-mtlp: NOTRUN -> [SKIP][12] ([i915#5325]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-8/igt@gem_ccs@block-copy-compressed.html * igt@gem_create@create-ext-cpu-access-big: - shard-dg2: NOTRUN -> [ABORT][13] ([i915#7461]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@gem_create@create-ext-cpu-access-big.html - shard-rkl: NOTRUN -> [SKIP][14] ([i915#6335]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@gem_create@create-ext-cpu-access-big.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-rkl: [PASS][15] -> [FAIL][16] ([i915#6268]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-7/igt@gem_ctx_exec@basic-nohangcheck.html - shard-tglu: [PASS][17] -> [FAIL][18] ([i915#6268]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-tglu-7/igt@gem_ctx_exec@basic-nohangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html * igt@gem_ctx_persistence@heartbeat-many: - shard-dg1: NOTRUN -> [SKIP][19] ([i915#8555]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@gem_ctx_persistence@heartbeat-many.html * igt@gem_ctx_persistence@legacy-engines-hang@bsd1: - shard-mtlp: [PASS][20] -> [FAIL][21] ([i915#2410]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-5/igt@gem_ctx_persistence@legacy-engines-hang@bsd1.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-3/igt@gem_ctx_persistence@legacy-engines-hang@bsd1.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#1099]) +2 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-snb6/igt@gem_ctx_persistence@legacy-engines-queued.html * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0: - shard-dg2: NOTRUN -> [SKIP][23] ([i915#5882]) +9 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html * igt@gem_ctx_persistence@smoketest: - shard-tglu: [PASS][24] -> [FAIL][25] ([i915#5099]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-tglu-9/igt@gem_ctx_persistence@smoketest.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-2/igt@gem_ctx_persistence@smoketest.html * igt@gem_exec_balancer@bonded-false-hang: - shard-dg2: NOTRUN -> [SKIP][26] ([i915#4812]) +2 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@gem_exec_balancer@bonded-false-hang.html * igt@gem_exec_balancer@bonded-sync: - shard-dg2: NOTRUN -> [SKIP][27] ([i915#4771]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@gem_exec_balancer@bonded-sync.html * igt@gem_exec_balancer@noheartbeat: - shard-dg2: NOTRUN -> [SKIP][28] ([i915#8555]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@gem_exec_balancer@noheartbeat.html - shard-mtlp: NOTRUN -> [SKIP][29] ([i915#8555]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-6/igt@gem_exec_balancer@noheartbeat.html * igt@gem_exec_capture@capture-invisible@lmem0: - shard-dg2: NOTRUN -> [SKIP][30] ([i915#6334]) +1 similar issue [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-11/igt@gem_exec_capture@capture-invisible@lmem0.html * igt@gem_exec_endless@dispatch@vecs0: - shard-tglu: [PASS][31] -> [TIMEOUT][32] ([i915#3778]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-tglu-3/igt@gem_exec_endless@dispatch@vecs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-8/igt@gem_exec_endless@dispatch@vecs0.html * igt@gem_exec_fair@basic-flow: - shard-dg1: NOTRUN -> [SKIP][33] ([i915#3539] / [i915#4852]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-18/igt@gem_exec_fair@basic-flow.html - shard-mtlp: NOTRUN -> [SKIP][34] ([i915#4473] / [i915#4771]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-6/igt@gem_exec_fair@basic-flow.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-rkl: [PASS][35] -> [FAIL][36] ([i915#2842]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-rkl-7/igt@gem_exec_fair@basic-none-share@rcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-2/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-rkl: NOTRUN -> [FAIL][37] ([i915#2842]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-7/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_fair@basic-throttle: - shard-dg2: NOTRUN -> [SKIP][38] ([i915#3539]) +4 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@gem_exec_fair@basic-throttle.html * igt@gem_exec_flush@basic-uc-rw-default: - shard-dg2: NOTRUN -> [SKIP][39] ([i915#3539] / [i915#4852]) +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-11/igt@gem_exec_flush@basic-uc-rw-default.html * igt@gem_exec_flush@basic-uc-set-default: - shard-dg1: NOTRUN -> [SKIP][40] ([i915#3539]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@gem_exec_flush@basic-uc-set-default.html * igt@gem_exec_reloc@basic-cpu-gtt: - shard-rkl: NOTRUN -> [SKIP][41] ([i915#3281]) +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-2/igt@gem_exec_reloc@basic-cpu-gtt.html - shard-dg1: NOTRUN -> [SKIP][42] ([i915#3281]) +4 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@gem_exec_reloc@basic-cpu-gtt.html * igt@gem_exec_reloc@basic-cpu-read-noreloc: - shard-mtlp: NOTRUN -> [SKIP][43] ([i915#3281]) +4 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-7/igt@gem_exec_reloc@basic-cpu-read-noreloc.html * igt@gem_exec_reloc@basic-gtt-read: - shard-dg2: NOTRUN -> [SKIP][44] ([i915#3281]) +11 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@gem_exec_reloc@basic-gtt-read.html * igt@gem_exec_schedule@preempt-queue: - shard-dg2: NOTRUN -> [SKIP][45] ([i915#4537] / [i915#4812]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@gem_exec_schedule@preempt-queue.html * igt@gem_exec_schedule@reorder-wide: - shard-dg1: NOTRUN -> [SKIP][46] ([i915#4812]) +2 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@gem_exec_schedule@reorder-wide.html - shard-mtlp: NOTRUN -> [SKIP][47] ([i915#4812]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-5/igt@gem_exec_schedule@reorder-wide.html * igt@gem_fence_thrash@bo-write-verify-y: - shard-dg2: NOTRUN -> [SKIP][48] ([i915#4860]) +3 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@gem_fence_thrash@bo-write-verify-y.html - shard-dg1: NOTRUN -> [SKIP][49] ([i915#4860]) +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@gem_fence_thrash@bo-write-verify-y.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-rkl: NOTRUN -> [SKIP][50] ([i915#4613]) +1 similar issue [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-1/igt@gem_lmem_swapping@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0: - shard-dg1: NOTRUN -> [SKIP][51] ([i915#4565]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html * igt@gem_lmem_swapping@smem-oom@lmem0: - shard-dg1: [PASS][52] -> [TIMEOUT][53] ([i915#5493]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-19/igt@gem_lmem_swapping@smem-oom@lmem0.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@gem_lmem_swapping@smem-oom@lmem0.html * igt@gem_mmap@basic-small-bo: - shard-mtlp: NOTRUN -> [SKIP][54] ([i915#4083]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-3/igt@gem_mmap@basic-small-bo.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-dg1: NOTRUN -> [SKIP][55] ([i915#4077]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html * igt@gem_mmap_gtt@cpuset-big-copy: - shard-dg2: NOTRUN -> [SKIP][56] ([i915#4077]) +9 similar issues [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@gem_mmap_gtt@cpuset-big-copy.html * igt@gem_mmap_wc@close: - shard-dg2: NOTRUN -> [SKIP][57] ([i915#4083]) +6 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@gem_mmap_wc@close.html - shard-dg1: NOTRUN -> [SKIP][58] ([i915#4083]) +1 similar issue [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@gem_mmap_wc@close.html * igt@gem_partial_pwrite_pread@reads: - shard-dg2: NOTRUN -> [SKIP][59] ([i915#3282]) +5 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@gem_partial_pwrite_pread@reads.html * igt@gem_partial_pwrite_pread@writes-after-reads-display: - shard-mtlp: NOTRUN -> [SKIP][60] ([i915#3282]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-5/igt@gem_partial_pwrite_pread@writes-after-reads-display.html * igt@gem_pxp@create-protected-buffer: - shard-mtlp: NOTRUN -> [SKIP][61] ([i915#4270]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-1/igt@gem_pxp@create-protected-buffer.html * igt@gem_pxp@fail-invalid-protected-context: - shard-rkl: NOTRUN -> [SKIP][62] ([i915#4270]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@gem_pxp@fail-invalid-protected-context.html - shard-dg1: NOTRUN -> [SKIP][63] ([i915#4270]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@gem_pxp@fail-invalid-protected-context.html * igt@gem_pxp@protected-encrypted-src-copy-not-readible: - shard-dg2: NOTRUN -> [SKIP][64] ([i915#4270]) +2 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html * igt@gem_render_copy@x-tiled-to-vebox-y-tiled: - shard-mtlp: NOTRUN -> [SKIP][65] ([i915#8428]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-3/igt@gem_render_copy@x-tiled-to-vebox-y-tiled.html * igt@gem_softpin@evict-snoop-interruptible: - shard-dg2: NOTRUN -> [SKIP][66] ([i915#4885]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@gem_softpin@evict-snoop-interruptible.html * igt@gem_tiled_blits@basic: - shard-mtlp: NOTRUN -> [SKIP][67] ([i915#4077]) +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-2/igt@gem_tiled_blits@basic.html * igt@gem_userptr_blits@coherency-unsync: - shard-mtlp: NOTRUN -> [SKIP][68] ([i915#3297]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-1/igt@gem_userptr_blits@coherency-unsync.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-dg2: NOTRUN -> [SKIP][69] ([i915#3297]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@forbidden-operations: - shard-dg1: NOTRUN -> [SKIP][70] ([i915#3282]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-18/igt@gem_userptr_blits@forbidden-operations.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-dg2: NOTRUN -> [SKIP][71] ([fdo#109289]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@gen7_exec_parse@cmd-crossing-page.html - shard-rkl: NOTRUN -> [SKIP][72] ([fdo#109289]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@gen7_exec_parse@cmd-crossing-page.html * igt@gen9_exec_parse@bb-large: - shard-dg1: NOTRUN -> [SKIP][73] ([i915#2527]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@gen9_exec_parse@bb-large.html - shard-rkl: NOTRUN -> [SKIP][74] ([i915#2527]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@gen9_exec_parse@bb-large.html * igt@gen9_exec_parse@secure-batches: - shard-dg2: NOTRUN -> [SKIP][75] ([i915#2856]) +2 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@gen9_exec_parse@secure-batches.html * igt@gen9_exec_parse@unaligned-access: - shard-mtlp: NOTRUN -> [SKIP][76] ([i915#2856]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-5/igt@gen9_exec_parse@unaligned-access.html * igt@i915_module_load@load: - shard-dg1: NOTRUN -> [SKIP][77] ([i915#6227]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-18/igt@i915_module_load@load.html - shard-dg2: NOTRUN -> [SKIP][78] ([i915#6227]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@i915_module_load@load.html - shard-rkl: NOTRUN -> [SKIP][79] ([i915#6227]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-1/igt@i915_module_load@load.html * igt@i915_pipe_stress@stress-xrgb8888-untiled: - shard-mtlp: [PASS][80] -> [FAIL][81] ([i915#8691]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-1/igt@i915_pipe_stress@stress-xrgb8888-untiled.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-4/igt@i915_pipe_stress@stress-xrgb8888-untiled.html * igt@i915_pm_backlight@fade-with-dpms: - shard-dg2: NOTRUN -> [SKIP][82] ([i915#5354] / [i915#7561]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@i915_pm_backlight@fade-with-dpms.html * igt@i915_pm_dc@dc5-dpms-negative: - shard-mtlp: NOTRUN -> [SKIP][83] ([i915#8018]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-5/igt@i915_pm_dc@dc5-dpms-negative.html * igt@i915_pm_dc@dc6-dpms: - shard-tglu: [PASS][84] -> [FAIL][85] ([i915#3989] / [i915#454]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-tglu-10/igt@i915_pm_dc@dc6-dpms.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-6/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_dc@dc9-dpms: - shard-apl: [PASS][86] -> [SKIP][87] ([fdo#109271]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-apl3/igt@i915_pm_dc@dc9-dpms.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-apl3/igt@i915_pm_dc@dc9-dpms.html * igt@i915_pm_rc6_residency@rc6-idle@vecs0: - shard-dg1: [PASS][88] -> [FAIL][89] ([i915#3591]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-rkl: [PASS][90] -> [SKIP][91] ([i915#1397]) +2 similar issues [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-rkl-4/igt@i915_pm_rpm@dpms-non-lpsp.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html - shard-dg1: [PASS][92] -> [SKIP][93] ([i915#1397]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-18/igt@i915_pm_rpm@dpms-non-lpsp.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@i915_pm_rpm@gem-mmap-type@gtt-smem0: - shard-mtlp: NOTRUN -> [SKIP][94] ([i915#8431]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-2/igt@i915_pm_rpm@gem-mmap-type@gtt-smem0.html * igt@i915_pm_rpm@i2c: - shard-dg2: [PASS][95] -> [FAIL][96] ([i915#8717]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-11/igt@i915_pm_rpm@i2c.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@i915_pm_rpm@i2c.html * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait: - shard-dg2: [PASS][97] -> [SKIP][98] ([i915#1397]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-mtlp: NOTRUN -> [SKIP][99] ([fdo#109293]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html * igt@i915_pm_rpm@pc8-residency: - shard-dg2: NOTRUN -> [SKIP][100] ([fdo#109506]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@i915_pm_rpm@pc8-residency.html * igt@i915_pm_sseu@full-enable: - shard-mtlp: NOTRUN -> [SKIP][101] ([i915#8437]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-5/igt@i915_pm_sseu@full-enable.html * igt@i915_suspend@basic-s3-without-i915: - shard-rkl: NOTRUN -> [INCOMPLETE][102] ([i915#4817]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-1/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - shard-dg2: NOTRUN -> [SKIP][103] ([i915#4212]) +1 similar issue [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - shard-dg2: NOTRUN -> [SKIP][104] ([i915#4215] / [i915#5190]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-4-mc_ccs: - shard-dg2: NOTRUN -> [SKIP][105] ([i915#8502] / [i915#8709]) +11 similar issues [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-4-mc_ccs.html * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs: - shard-dg1: NOTRUN -> [SKIP][106] ([i915#8502]) +7 similar issues [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs.html * igt@kms_async_flips@crc@pipe-a-hdmi-a-2: - shard-rkl: NOTRUN -> [FAIL][107] ([i915#8247]) +1 similar issue [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-2/igt@kms_async_flips@crc@pipe-a-hdmi-a-2.html * igt@kms_async_flips@crc@pipe-b-hdmi-a-1: - shard-snb: NOTRUN -> [FAIL][108] ([i915#8247]) +1 similar issue [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-snb1/igt@kms_async_flips@crc@pipe-b-hdmi-a-1.html * igt@kms_async_flips@crc@pipe-c-hdmi-a-1: - shard-dg1: NOTRUN -> [FAIL][109] ([i915#8247]) +3 similar issues [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@kms_async_flips@crc@pipe-c-hdmi-a-1.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels: - shard-dg2: NOTRUN -> [SKIP][110] ([i915#1769] / [i915#3555]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html * igt@kms_big_fb@4-tiled-32bpp-rotate-0: - shard-rkl: NOTRUN -> [SKIP][111] ([i915#5286]) +2 similar issues [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html - shard-dg1: NOTRUN -> [SKIP][112] ([i915#4538] / [i915#5286]) +2 similar issues [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-mtlp: NOTRUN -> [FAIL][113] ([i915#3743]) [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@x-tiled-32bpp-rotate-270: - shard-dg2: NOTRUN -> [SKIP][114] ([fdo#111614]) +3 similar issues [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html - shard-rkl: NOTRUN -> [SKIP][115] ([fdo#111614] / [i915#3638]) +2 similar issues [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html - shard-dg1: NOTRUN -> [SKIP][116] ([i915#3638]) +1 similar issue [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-mtlp: NOTRUN -> [SKIP][117] ([fdo#111615]) +2 similar issues [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: - shard-dg2: NOTRUN -> [SKIP][118] ([i915#5190]) +19 similar issues [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-90: - shard-dg2: NOTRUN -> [SKIP][119] ([i915#4538] / [i915#5190]) +3 similar issues [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-rkl: NOTRUN -> [SKIP][120] ([fdo#110723]) [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html - shard-dg1: NOTRUN -> [SKIP][121] ([i915#4538]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-17/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html * igt@kms_big_joiner@basic: - shard-mtlp: NOTRUN -> [SKIP][122] ([i915#2705]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-5/igt@kms_big_joiner@basic.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc: - shard-rkl: NOTRUN -> [SKIP][123] ([i915#5354] / [i915#6095]) [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html - shard-dg1: NOTRUN -> [SKIP][124] ([i915#3689] / [i915#5354] / [i915#6095]) +11 similar issues [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc: - shard-dg1: NOTRUN -> [SKIP][125] ([i915#5354] / [i915#6095]) +5 similar issues [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-17/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc.html * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs: - shard-rkl: NOTRUN -> [SKIP][126] ([i915#3734] / [i915#5354] / [i915#6095]) +4 similar issues [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs.html * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs_cc: - shard-mtlp: NOTRUN -> [SKIP][127] ([i915#6095]) +10 similar issues [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-4/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs_cc.html * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs: - shard-rkl: NOTRUN -> [SKIP][128] ([i915#3886] / [i915#5354] / [i915#6095]) [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-1/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html - shard-dg1: NOTRUN -> [SKIP][129] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095]) [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-18/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: - shard-mtlp: NOTRUN -> [SKIP][130] ([i915#3886] / [i915#6095]) +2 similar issues [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-3/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs: - shard-rkl: NOTRUN -> [SKIP][131] ([i915#5354]) +8 similar issues [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-dg2: NOTRUN -> [SKIP][132] ([i915#3689] / [i915#3886] / [i915#5354]) +6 similar issues [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs: - shard-dg2: NOTRUN -> [SKIP][133] ([i915#3689] / [i915#5354]) +27 similar issues [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html * igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_mtl_mc_ccs: - shard-tglu: NOTRUN -> [SKIP][134] ([i915#5354] / [i915#6095]) [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-10/igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_mtl_mc_ccs.html * igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1: - shard-dg2: NOTRUN -> [SKIP][135] ([i915#4087]) +3 similar issues [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html * igt@kms_chamelium_color@degamma: - shard-dg2: NOTRUN -> [SKIP][136] ([fdo#111827]) +1 similar issue [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@kms_chamelium_color@degamma.html - shard-rkl: NOTRUN -> [SKIP][137] ([fdo#111827]) [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@kms_chamelium_color@degamma.html - shard-dg1: NOTRUN -> [SKIP][138] ([fdo#111827]) [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@kms_chamelium_color@degamma.html * igt@kms_chamelium_frames@hdmi-cmp-planar-formats: - shard-dg2: NOTRUN -> [SKIP][139] ([i915#7828]) +10 similar issues [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats: - shard-rkl: NOTRUN -> [SKIP][140] ([i915#7828]) +1 similar issue [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html - shard-dg1: NOTRUN -> [SKIP][141] ([i915#7828]) +2 similar issues [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html * igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode: - shard-mtlp: NOTRUN -> [SKIP][142] ([i915#7828]) +2 similar issues [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-7/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html * igt@kms_content_protection@atomic@pipe-a-dp-2: - shard-dg2: NOTRUN -> [TIMEOUT][143] ([i915#7173]) [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_content_protection@atomic@pipe-a-dp-2.html * igt@kms_content_protection@dp-mst-lic-type-0: - shard-dg2: NOTRUN -> [SKIP][144] ([i915#3299]) [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@kms_content_protection@dp-mst-lic-type-0.html * igt@kms_content_protection@legacy: - shard-dg2: NOTRUN -> [SKIP][145] ([i915#7118]) [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@kms_content_protection@legacy.html * igt@kms_cursor_crc@cursor-offscreen-512x512: - shard-dg2: NOTRUN -> [SKIP][146] ([i915#3359]) +1 similar issue [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@kms_cursor_crc@cursor-offscreen-512x512.html * igt@kms_cursor_crc@cursor-random-512x170: - shard-mtlp: NOTRUN -> [SKIP][147] ([i915#3359]) [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-3/igt@kms_cursor_crc@cursor-random-512x170.html * igt@kms_cursor_crc@cursor-rapid-movement-32x32: - shard-dg2: NOTRUN -> [SKIP][148] ([i915#3555]) +7 similar issues [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html - shard-rkl: NOTRUN -> [SKIP][149] ([i915#3555]) +2 similar issues [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html - shard-dg1: NOTRUN -> [SKIP][150] ([i915#3555]) +6 similar issues [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-17/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - shard-dg2: NOTRUN -> [SKIP][151] ([i915#4103] / [i915#4213]) +1 similar issue [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic: - shard-rkl: NOTRUN -> [SKIP][152] ([fdo#111825]) +2 similar issues [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy: - shard-dg2: NOTRUN -> [SKIP][153] ([fdo#109274] / [i915#5354]) +4 similar issues [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-dg2: NOTRUN -> [SKIP][154] ([fdo#109274] / [fdo#111767] / [i915#5354]) +1 similar issue [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-apl: [PASS][155] -> [FAIL][156] ([i915#2346]) [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-glk: [PASS][157] -> [FAIL][158] ([i915#2346]) [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_display_modes@mst-extended-mode-negative: - shard-mtlp: NOTRUN -> [SKIP][159] ([i915#8588]) [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-8/igt@kms_display_modes@mst-extended-mode-negative.html * igt@kms_draw_crc@draw-method-mmap-wc: - shard-dg2: NOTRUN -> [SKIP][160] ([i915#8812]) [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_draw_crc@draw-method-mmap-wc.html * igt@kms_dsc@dsc-with-bpc: - shard-dg2: NOTRUN -> [SKIP][161] ([i915#3555] / [i915#3840]) [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@kms_dsc@dsc-with-bpc.html - shard-dg1: NOTRUN -> [SKIP][162] ([i915#3555] / [i915#3840]) [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@kms_dsc@dsc-with-bpc.html * igt@kms_fence_pin_leak: - shard-mtlp: NOTRUN -> [SKIP][163] ([i915#4881]) [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-7/igt@kms_fence_pin_leak.html * igt@kms_flip@2x-flip-vs-blocking-wf-vblank: - shard-snb: NOTRUN -> [SKIP][164] ([fdo#109271] / [fdo#111767]) [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-snb6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html * igt@kms_flip@2x-flip-vs-dpms: - shard-mtlp: NOTRUN -> [SKIP][165] ([i915#3637]) +2 similar issues [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-8/igt@kms_flip@2x-flip-vs-dpms.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-dg2: NOTRUN -> [SKIP][166] ([fdo#109274] / [fdo#111767]) [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-11/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@2x-flip-vs-panning-interruptible: - shard-tglu: NOTRUN -> [SKIP][167] ([fdo#109274] / [i915#3637]) [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-2/igt@kms_flip@2x-flip-vs-panning-interruptible.html * igt@kms_flip@2x-wf_vblank-ts-check: - shard-dg2: NOTRUN -> [SKIP][168] ([fdo#109274]) +4 similar issues [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_flip@2x-wf_vblank-ts-check.html * igt@kms_flip@flip-vs-fences-interruptible: - shard-dg2: NOTRUN -> [SKIP][169] ([i915#8381]) [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-11/igt@kms_flip@flip-vs-fences-interruptible.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][170] ([i915#2672]) +1 similar issue [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode: - shard-dg2: NOTRUN -> [SKIP][171] ([i915#2672]) +3 similar issues [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode: - shard-rkl: NOTRUN -> [SKIP][172] ([i915#2672]) [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html - shard-dg1: NOTRUN -> [SKIP][173] ([i915#2587] / [i915#2672]) +1 similar issue [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode: - shard-dg2: NOTRUN -> [SKIP][174] ([i915#2672] / [i915#3555]) [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html * igt@kms_force_connector_basic@force-load-detect: - shard-dg2: NOTRUN -> [SKIP][175] ([fdo#109285]) [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render: - shard-dg2: [PASS][176] -> [FAIL][177] ([i915#6880]) +2 similar issues [176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-mtlp: NOTRUN -> [SKIP][178] ([i915#8708]) +1 similar issue [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt: - shard-dg1: NOTRUN -> [SKIP][179] ([i915#8708]) +5 similar issues [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-dg2: NOTRUN -> [SKIP][180] ([i915#8708]) +19 similar issues [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt: - shard-dg2: NOTRUN -> [SKIP][181] ([i915#5354]) +52 similar issues [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite: - shard-dg1: NOTRUN -> [SKIP][182] ([fdo#111825]) +17 similar issues [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html - shard-mtlp: NOTRUN -> [SKIP][183] ([i915#1825]) +6 similar issues [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: - shard-rkl: NOTRUN -> [SKIP][184] ([i915#3023]) +5 similar issues [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html - shard-tglu: NOTRUN -> [SKIP][185] ([fdo#110189]) +1 similar issue [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt: - shard-rkl: NOTRUN -> [SKIP][186] ([fdo#111825] / [i915#1825]) +8 similar issues [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc: - shard-tglu: NOTRUN -> [SKIP][187] ([fdo#109280]) +1 similar issue [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu: - shard-dg2: NOTRUN -> [SKIP][188] ([i915#3458]) +13 similar issues [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-dg1: NOTRUN -> [SKIP][189] ([i915#3458]) +7 similar issues [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-suspend.html * igt@kms_hdmi_inject@inject-audio: - shard-tglu: [PASS][190] -> [SKIP][191] ([i915#433]) [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-tglu-3/igt@kms_hdmi_inject@inject-audio.html [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-8/igt@kms_hdmi_inject@inject-audio.html * igt@kms_hdr@invalid-metadata-sizes: - shard-dg2: NOTRUN -> [SKIP][192] ([i915#3555] / [i915#8228]) +1 similar issue [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@kms_hdr@invalid-metadata-sizes.html * igt@kms_panel_fitting@atomic-fastset: - shard-dg2: NOTRUN -> [SKIP][193] ([i915#6301]) +1 similar issue [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_panel_fitting@atomic-fastset.html * igt@kms_panel_fitting@legacy: - shard-rkl: NOTRUN -> [SKIP][194] ([i915#6301]) [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-1/igt@kms_panel_fitting@legacy.html - shard-dg1: NOTRUN -> [SKIP][195] ([i915#6301]) [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@kms_panel_fitting@legacy.html * igt@kms_plane_scaling@intel-max-src-size: - shard-dg2: NOTRUN -> [SKIP][196] ([i915#6953]) [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@kms_plane_scaling@intel-max-src-size.html * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][197] ([i915#5176]) +9 similar issues [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1.html * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-dp-4: - shard-dg2: NOTRUN -> [SKIP][198] ([i915#5176]) +3 similar issues [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-dp-4.html * igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1: - shard-dg1: NOTRUN -> [SKIP][199] ([i915#5176]) +15 similar issues [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4: - shard-dg1: NOTRUN -> [SKIP][200] ([i915#5235]) +7 similar issues [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4.html * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][201] ([i915#5235]) +11 similar issues [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2: - shard-rkl: NOTRUN -> [SKIP][202] ([i915#5235]) +3 similar issues [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html * igt@kms_prime@basic-crc-hybrid: - shard-rkl: NOTRUN -> [SKIP][203] ([i915#6524]) [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-2/igt@kms_prime@basic-crc-hybrid.html - shard-dg1: NOTRUN -> [SKIP][204] ([i915#6524]) [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@kms_prime@basic-crc-hybrid.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area: - shard-mtlp: NOTRUN -> [SKIP][205] ([i915#2920]) [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area: - shard-rkl: NOTRUN -> [SKIP][206] ([fdo#111068] / [i915#658]) [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html - shard-dg1: NOTRUN -> [SKIP][207] ([fdo#111068] / [i915#658]) [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-dg2: NOTRUN -> [SKIP][208] ([i915#658]) +2 similar issues [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-11/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr@dpms: - shard-dg2: NOTRUN -> [SKIP][209] ([i915#1072]) +7 similar issues [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@kms_psr@dpms.html * igt@kms_psr@no_drrs: - shard-rkl: NOTRUN -> [SKIP][210] ([i915#1072]) +1 similar issue [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-7/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_sprite_render: - shard-dg1: NOTRUN -> [SKIP][211] ([i915#1072]) +1 similar issue [211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@kms_psr@psr2_sprite_render.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90: - shard-dg2: NOTRUN -> [SKIP][212] ([i915#4235] / [i915#5190]) +1 similar issue [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html - shard-mtlp: NOTRUN -> [SKIP][213] ([i915#4235]) [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180: - shard-dg1: NOTRUN -> [SKIP][214] ([fdo#111615] / [i915#5289]) [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html - shard-mtlp: NOTRUN -> [SKIP][215] ([i915#5289]) [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html * igt@kms_selftest@drm_plane: - shard-dg2: NOTRUN -> [SKIP][216] ([i915#8661]) +1 similar issue [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@kms_selftest@drm_plane.html * igt@kms_selftest@framebuffer: - shard-snb: NOTRUN -> [SKIP][217] ([fdo#109271] / [i915#8661]) +1 similar issue [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-snb1/igt@kms_selftest@framebuffer.html * igt@kms_setmode@basic-clone-single-crtc: - shard-rkl: NOTRUN -> [SKIP][218] ([i915#3555] / [i915#4098]) +1 similar issue [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@kms_setmode@basic-clone-single-crtc.html * igt@kms_setmode@invalid-clone-exclusive-crtc: - shard-mtlp: NOTRUN -> [SKIP][219] ([i915#8823]) [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-8/igt@kms_setmode@invalid-clone-exclusive-crtc.html * igt@kms_sysfs_edid_timing: - shard-dg2: [PASS][220] -> [FAIL][221] ([IGT#2]) [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-11/igt@kms_sysfs_edid_timing.html [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@kms_sysfs_edid_timing.html * igt@kms_vblank@pipe-c-query-busy-hang: - shard-snb: NOTRUN -> [SKIP][222] ([fdo#109271]) +240 similar issues [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-snb4/igt@kms_vblank@pipe-c-query-busy-hang.html * igt@kms_vblank@pipe-c-query-forked-busy: - shard-rkl: NOTRUN -> [SKIP][223] ([i915#4070] / [i915#6768]) +1 similar issue [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@kms_vblank@pipe-c-query-forked-busy.html * igt@kms_vrr@flipline: - shard-mtlp: NOTRUN -> [SKIP][224] ([i915#8808]) [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-1/igt@kms_vrr@flipline.html * igt@kms_writeback@writeback-fb-id: - shard-rkl: NOTRUN -> [SKIP][225] ([i915#2437]) [225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@kms_writeback@writeback-fb-id.html - shard-dg1: NOTRUN -> [SKIP][226] ([i915#2437]) [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@kms_writeback@writeback-fb-id.html * igt@perf@global-sseu-config-invalid: - shard-dg2: NOTRUN -> [SKIP][227] ([i915#7387]) [227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@perf@global-sseu-config-invalid.html * igt@perf_pmu@busy-double-start@vcs1: - shard-dg1: [PASS][228] -> [FAIL][229] ([i915#4349]) +1 similar issue [228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-17/igt@perf_pmu@busy-double-start@vcs1.html [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@perf_pmu@busy-double-start@vcs1.html * igt@perf_pmu@busy-double-start@vecs1: - shard-dg2: [PASS][230] -> [FAIL][231] ([i915#4349]) +3 similar issues [230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@perf_pmu@busy-double-start@vecs1.html * igt@perf_pmu@cpu-hotplug: - shard-mtlp: NOTRUN -> [SKIP][232] ([i915#8850]) [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-6/igt@perf_pmu@cpu-hotplug.html * igt@perf_pmu@rc6-suspend: - shard-snb: NOTRUN -> [DMESG-WARN][233] ([i915#8841]) +1 similar issue [233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-snb4/igt@perf_pmu@rc6-suspend.html * igt@prime_vgem@basic-fence-read: - shard-dg2: NOTRUN -> [SKIP][234] ([i915#3291] / [i915#3708]) [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-1/igt@prime_vgem@basic-fence-read.html - shard-rkl: NOTRUN -> [SKIP][235] ([fdo#109295] / [i915#3291] / [i915#3708]) [235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@prime_vgem@basic-fence-read.html - shard-dg1: NOTRUN -> [SKIP][236] ([i915#3708]) [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@prime_vgem@basic-fence-read.html * igt@prime_vgem@coherency-gtt: - shard-dg2: NOTRUN -> [SKIP][237] ([i915#3708] / [i915#4077]) [237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-12/igt@prime_vgem@coherency-gtt.html * igt@v3d/v3d_perfmon@get-values-invalid-pad: - shard-rkl: NOTRUN -> [SKIP][238] ([fdo#109315]) [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-4/igt@v3d/v3d_perfmon@get-values-invalid-pad.html * igt@v3d/v3d_perfmon@get-values-invalid-perfmon: - shard-dg1: NOTRUN -> [SKIP][239] ([i915#2575]) +4 similar issues [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-16/igt@v3d/v3d_perfmon@get-values-invalid-perfmon.html * igt@v3d/v3d_perfmon@get-values-invalid-pointer: - shard-mtlp: NOTRUN -> [SKIP][240] ([i915#2575]) +5 similar issues [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-6/igt@v3d/v3d_perfmon@get-values-invalid-pointer.html * igt@v3d/v3d_submit_csd@bad-flag: - shard-dg2: NOTRUN -> [SKIP][241] ([i915#2575]) +15 similar issues [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@v3d/v3d_submit_csd@bad-flag.html * igt@vc4/vc4_create_bo@create-bo-0: - shard-rkl: NOTRUN -> [SKIP][242] ([i915#7711]) +1 similar issue [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-2/igt@vc4/vc4_create_bo@create-bo-0.html - shard-dg1: NOTRUN -> [SKIP][243] ([i915#7711]) +2 similar issues [243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@vc4/vc4_create_bo@create-bo-0.html * igt@vc4/vc4_mmap@mmap-bo: - shard-dg2: NOTRUN -> [SKIP][244] ([i915#7711]) +7 similar issues [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@vc4/vc4_mmap@mmap-bo.html * igt@vc4/vc4_perfmon@get-values-invalid-pointer: - shard-mtlp: NOTRUN -> [SKIP][245] ([i915#7711]) +1 similar issue [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-7/igt@vc4/vc4_perfmon@get-values-invalid-pointer.html #### Possible fixes #### * igt@gem_eio@hibernate: - shard-dg1: [ABORT][246] ([i915#7975] / [i915#8213]) -> [PASS][247] +1 similar issue [246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-14/igt@gem_eio@hibernate.html [247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-18/igt@gem_eio@hibernate.html * igt@gem_exec_capture@pi@ccs0: - shard-mtlp: [FAIL][248] ([i915#7765]) -> [PASS][249] [248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-8/igt@gem_exec_capture@pi@ccs0.html [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-4/igt@gem_exec_capture@pi@ccs0.html * igt@gem_exec_capture@pi@rcs0: - shard-dg1: [FAIL][250] ([i915#4475]) -> [PASS][251] [250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-18/igt@gem_exec_capture@pi@rcs0.html [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@gem_exec_capture@pi@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [FAIL][252] ([i915#2846]) -> [PASS][253] [252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-glk4/igt@gem_exec_fair@basic-deadline.html [253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-glk1/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [FAIL][254] ([i915#2842]) -> [PASS][255] [254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_schedule@preemptive-hang@vcs0: - shard-mtlp: [FAIL][256] ([i915#9051]) -> [PASS][257] [256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-6/igt@gem_exec_schedule@preemptive-hang@vcs0.html [257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-5/igt@gem_exec_schedule@preemptive-hang@vcs0.html * igt@gem_exec_suspend@basic-s0@smem: - shard-dg2: [INCOMPLETE][258] ([i915#8011]) -> [PASS][259] [258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-12/igt@gem_exec_suspend@basic-s0@smem.html [259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@gem_exec_suspend@basic-s0@smem.html * igt@i915_hangman@engine-engine-hang@vcs0: - shard-mtlp: [FAIL][260] ([i915#7069]) -> [PASS][261] +1 similar issue [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-8/igt@i915_hangman@engine-engine-hang@vcs0.html [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-8/igt@i915_hangman@engine-engine-hang@vcs0.html * igt@i915_pm_rc6_residency@rc6-idle@bcs0: - shard-dg1: [FAIL][262] ([i915#3591]) -> [PASS][263] [262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html [263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html * igt@i915_pm_rpm@dpms-lpsp: - shard-dg1: [SKIP][264] ([i915#1397]) -> [PASS][265] +2 similar issues [264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-16/igt@i915_pm_rpm@dpms-lpsp.html [265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-19/igt@i915_pm_rpm@dpms-lpsp.html * igt@i915_pm_rpm@modeset-non-lpsp: - shard-dg2: [SKIP][266] ([i915#1397]) -> [PASS][267] [266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp.html [267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@i915_pm_rpm@modeset-non-lpsp.html * igt@kms_big_fb@4-tiled-64bpp-rotate-180: - shard-mtlp: [FAIL][268] ([i915#5138]) -> [PASS][269] +1 similar issue [268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-4/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html [269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-5/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-mtlp: [FAIL][270] ([i915#3743]) -> [PASS][271] [270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html [271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [FAIL][272] ([i915#72]) -> [PASS][273] [272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * igt@kms_flip@dpms-vs-vblank-race@a-edp1: - shard-mtlp: [DMESG-WARN][274] ([i915#1982]) -> [PASS][275] +1 similar issue [274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-3/igt@kms_flip@dpms-vs-vblank-race@a-edp1.html [275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-2/igt@kms_flip@dpms-vs-vblank-race@a-edp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: - shard-dg2: [FAIL][276] ([i915#6880]) -> [PASS][277] +2 similar issues [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html [277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html * igt@perf_pmu@all-busy-idle-check-all: - shard-dg2: [FAIL][278] ([i915#5234]) -> [PASS][279] [278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-2/igt@perf_pmu@all-busy-idle-check-all.html [279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-6/igt@perf_pmu@all-busy-idle-check-all.html - shard-dg1: [FAIL][280] ([i915#5234]) -> [PASS][281] [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-14/igt@perf_pmu@all-busy-idle-check-all.html [281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@perf_pmu@all-busy-idle-check-all.html * igt@perf_pmu@rc6@runtime-pm-long-gt1: - shard-mtlp: [SKIP][282] ([i915#8537]) -> [PASS][283] +2 similar issues [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-8/igt@perf_pmu@rc6@runtime-pm-long-gt1.html [283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-3/igt@perf_pmu@rc6@runtime-pm-long-gt1.html * igt@sysfs_heartbeat_interval@nopreempt@ccs0: - shard-mtlp: [FAIL][284] ([i915#6015]) -> [PASS][285] +4 similar issues [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-5/igt@sysfs_heartbeat_interval@nopreempt@ccs0.html [285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-1/igt@sysfs_heartbeat_interval@nopreempt@ccs0.html * igt@sysfs_preempt_timeout@timeout@vecs0: - shard-mtlp: [ABORT][286] ([i915#8521] / [i915#8865]) -> [PASS][287] [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-1/igt@sysfs_preempt_timeout@timeout@vecs0.html [287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-8/igt@sysfs_preempt_timeout@timeout@vecs0.html * igt@sysfs_timeslice_duration@timeout@vecs0: - shard-mtlp: [TIMEOUT][288] ([i915#6950]) -> [PASS][289] [288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-mtlp-7/igt@sysfs_timeslice_duration@timeout@vecs0.html [289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-mtlp-7/igt@sysfs_timeslice_duration@timeout@vecs0.html #### Warnings #### * igt@gem_lmem_swapping@smem-oom@lmem0: - shard-dg2: [TIMEOUT][290] ([i915#5493]) -> [DMESG-WARN][291] ([i915#4936] / [i915#5493]) [290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-6/igt@gem_lmem_swapping@smem-oom@lmem0.html [291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-2/igt@gem_lmem_swapping@smem-oom@lmem0.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-tglu: [WARN][292] ([i915#2681]) -> [FAIL][293] ([i915#2681] / [i915#3591]) +1 similar issue [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-tglu-4/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@kms_content_protection@mei_interface: - shard-rkl: [SKIP][294] ([i915#7118]) -> [SKIP][295] ([fdo#109300]) [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-rkl-7/igt@kms_content_protection@mei_interface.html [295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-7/igt@kms_content_protection@mei_interface.html - shard-dg1: [SKIP][296] ([i915#7116]) -> [SKIP][297] ([fdo#109300]) [296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-17/igt@kms_content_protection@mei_interface.html [297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-18/igt@kms_content_protection@mei_interface.html - shard-tglu: [SKIP][298] ([i915#6944] / [i915#7116] / [i915#7118]) -> [SKIP][299] ([fdo#109300]) [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-tglu-7/igt@kms_content_protection@mei_interface.html [299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-tglu-9/igt@kms_content_protection@mei_interface.html * igt@kms_force_connector_basic@force-load-detect: - shard-rkl: [SKIP][300] ([fdo#109285] / [i915#4098]) -> [SKIP][301] ([fdo#109285]) [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-rkl-1/igt@kms_force_connector_basic@force-load-detect.html [301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_psr@primary_mmap_gtt: - shard-dg1: [SKIP][302] ([i915#1072] / [i915#4078]) -> [SKIP][303] ([i915#1072]) [302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-18/igt@kms_psr@primary_mmap_gtt.html [303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-14/igt@kms_psr@primary_mmap_gtt.html * igt@kms_psr@sprite_plane_onoff: - shard-dg1: [SKIP][304] ([i915#1072]) -> [SKIP][305] ([i915#1072] / [i915#4078]) [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-14/igt@kms_psr@sprite_plane_onoff.html [305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg1-18/igt@kms_psr@sprite_plane_onoff.html * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem: - shard-dg2: [CRASH][306] ([i915#7331]) -> [INCOMPLETE][307] ([i915#5493]) [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg2-1/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html [307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936 [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473 [i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475 [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936 [i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099 [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493 [i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882 [i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6122]: https://gitlab.freedesktop.org/drm/intel/issues/6122 [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768 [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880 [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944 [i915#6950]: https://gitlab.freedesktop.org/drm/intel/issues/6950 [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953 [i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331 [i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387 [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 [i915#7765]: https://gitlab.freedesktop.org/drm/intel/issues/7765 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975 [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011 [i915#8018]: https://gitlab.freedesktop.org/drm/intel/issues/8018 [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213 [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228 [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247 [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381 [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411 [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414 [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428 [i915#8431]: https://gitlab.freedesktop.org/drm/intel/issues/8431 [i915#8437]: https://gitlab.freedesktop.org/drm/intel/issues/8437 [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502 [i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521 [i915#8537]: https://gitlab.freedesktop.org/drm/intel/issues/8537 [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555 [i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588 [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661 [i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691 [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708 [i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709 [i915#8717]: https://gitlab.freedesktop.org/drm/intel/issues/8717 [i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808 [i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812 [i915#8823]: https://gitlab.freedesktop.org/drm/intel/issues/8823 [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841 [i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850 [i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865 [i915#9051]: https://gitlab.freedesktop.org/drm/intel/issues/9051 [i915#9053]: https://gitlab.freedesktop.org/drm/intel/issues/9053 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7444 -> IGTPW_9621 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_13536: 7a825a06c6ee60a6586ddf8b4adb03ea5262bda7 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_9621: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/index.html IGT_7444: 7444 piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9621/index.html [-- Attachment #2: Type: text/html, Size: 96974 bytes --] ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v3 0/3] lib/xe_spin: introduced fixed duration xe_spin 2023-08-18 10:21 [igt-dev] [PATCH i-g-t v2 0/2] lib/xe_spin: introduced fixed duration xe_spin Marcin Bernatowicz ` (5 preceding siblings ...) 2023-08-19 16:59 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork @ 2023-09-05 14:23 ` Marcin Bernatowicz 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 1/3] lib/xe_spin: xe_spin_opts for xe_spin initialization Marcin Bernatowicz ` (2 more replies) 6 siblings, 3 replies; 11+ messages in thread From: Marcin Bernatowicz @ 2023-09-05 14:23 UTC (permalink / raw) To: igt-dev Introduced struct xe_spin_opts for xe_spin initialization, adjusted tests to new xe_spin_init signature. Extended spinner with fixed duration capability. It allows to prepare fixed duration (ex. 10ms) workloads and take workloads/second measurements, a handy utility for scheduling tests. Basic test for xe_spin with fixed duration. v2: - added asserts in div64_u64_round_up, duration_to_ctx_ticks, simplified loop_addr (Zbyszek) - added xe_spin_init_opts macro (Zbyszek) - corrected patch title (Kamil) - Added assert for expected spinner duration. (Zbyszek) A median of 5x100ms spins duration is computed, which should satisfy CI runs, although better accuracy is achieved with disabled logging (echo 0 > /sys/module/drm/parameters/debug). v3: - extracted xe_spin_opts to separate patch (Kamil) - div64_u64_round_up assert on overflow (Kamil) - enum indentation cleanup in xe_spin.c (Kamil) Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> Marcin Bernatowicz (3): lib/xe_spin: xe_spin_opts for xe_spin initialization lib/xe_spin: fixed duration xe_spin capability tests/xe_spin_batch: spin-fixed-duration lib/xe/xe_spin.c | 123 ++++++++++++++++++++++++++++----- lib/xe/xe_spin.h | 27 +++++++- tests/intel/xe_dma_buf_sync.c | 6 +- tests/intel/xe_exec_balancer.c | 9 ++- tests/intel/xe_exec_reset.c | 24 ++++--- tests/intel/xe_exec_threads.c | 7 +- tests/intel/xe_spin_batch.c | 72 +++++++++++++++++++ tests/intel/xe_vm.c | 7 +- 8 files changed, 231 insertions(+), 44 deletions(-) -- 2.30.2 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v3 1/3] lib/xe_spin: xe_spin_opts for xe_spin initialization 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 0/3] " Marcin Bernatowicz @ 2023-09-05 14:23 ` Marcin Bernatowicz 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 2/3] lib/xe_spin: fixed duration xe_spin capability Marcin Bernatowicz 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 3/3] tests/xe_spin_batch: spin-fixed-duration Marcin Bernatowicz 2 siblings, 0 replies; 11+ messages in thread From: Marcin Bernatowicz @ 2023-09-05 14:23 UTC (permalink / raw) To: igt-dev Introduced struct xe_spin_opts for xe_spin initialization, adjusted tests to new xe_spin_init signature. Added xe_spin_init_opts macro (Zbyszek). Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> --- lib/xe/xe_spin.c | 28 ++++++++++------------------ lib/xe/xe_spin.h | 19 ++++++++++++++++++- tests/intel/xe_dma_buf_sync.c | 6 +++--- tests/intel/xe_exec_balancer.c | 9 ++++----- tests/intel/xe_exec_reset.c | 24 ++++++++++++++---------- tests/intel/xe_exec_threads.c | 7 ++++--- tests/intel/xe_vm.c | 7 ++++--- 7 files changed, 57 insertions(+), 43 deletions(-) diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c index 7113972ee..27f837ef9 100644 --- a/lib/xe/xe_spin.c +++ b/lib/xe/xe_spin.c @@ -19,17 +19,13 @@ /** * xe_spin_init: * @spin: pointer to mapped bo in which spinner code will be written - * @addr: offset of spinner within vm - * @preempt: allow spinner to be preempted or not + * @opts: pointer to spinner initialization options */ -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt) +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts) { - uint64_t batch_offset = (char *)&spin->batch - (char *)spin; - uint64_t batch_addr = addr + batch_offset; - uint64_t start_offset = (char *)&spin->start - (char *)spin; - uint64_t start_addr = addr + start_offset; - uint64_t end_offset = (char *)&spin->end - (char *)spin; - uint64_t end_addr = addr + end_offset; + uint64_t loop_addr = opts->addr + offsetof(struct xe_spin, batch); + uint64_t start_addr = opts->addr + offsetof(struct xe_spin, start); + uint64_t end_addr = opts->addr + offsetof(struct xe_spin, end); int b = 0; spin->start = 0; @@ -40,7 +36,7 @@ void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt) spin->batch[b++] = start_addr >> 32; spin->batch[b++] = 0xc0ffee; - if (preempt) + if (opts->preempt) spin->batch[b++] = (0x5 << 23); spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; @@ -49,8 +45,8 @@ void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt) spin->batch[b++] = end_addr >> 32; spin->batch[b++] = MI_BATCH_BUFFER_START | 1 << 8 | 1; - spin->batch[b++] = batch_addr; - spin->batch[b++] = batch_addr >> 32; + spin->batch[b++] = loop_addr; + spin->batch[b++] = loop_addr >> 32; igt_assert(b <= ARRAY_SIZE(spin->batch)); } @@ -133,11 +129,7 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt) addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size); - if (!(opt->flags & IGT_SPIN_NO_PREEMPTION)) - xe_spin_init(xe_spin, addr, true); - else - xe_spin_init(xe_spin, addr, false); - + xe_spin_init_opts(xe_spin, .addr = addr, .preempt = !(opt->flags & IGT_SPIN_NO_PREEMPTION)); exec.exec_queue_id = spin->engine; exec.address = addr; sync.handle = spin->syncobj; @@ -219,7 +211,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe, exec_queue = xe_exec_queue_create(fd, vm, hwe, 0); syncobj = syncobj_create(fd, 0); - xe_spin_init(spin, addr, true); + xe_spin_init_opts(spin, .addr = addr, .preempt = true); exec.exec_queue_id = exec_queue; exec.address = addr; sync.handle = syncobj; diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h index c84db175d..9f1d33294 100644 --- a/lib/xe/xe_spin.h +++ b/lib/xe/xe_spin.h @@ -15,6 +15,18 @@ #include "xe_query.h" #include "lib/igt_dummyload.h" +/** struct xe_spin_opts + * + * @addr: offset of spinner within vm + * @preempt: allow spinner to be preempted or not + * + * Used to initialize struct xe_spin spinner behavior. + */ +struct xe_spin_opts { + uint64_t addr; + bool preempt; +}; + /* Mapped GPU object */ struct xe_spin { uint32_t batch[16]; @@ -22,8 +34,13 @@ struct xe_spin { uint32_t start; uint32_t end; }; + igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt); -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt); +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts); + +#define xe_spin_init_opts(fd, ...) \ + xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__})) + bool xe_spin_started(struct xe_spin *spin); void xe_spin_sync_wait(int fd, struct igt_spin *spin); void xe_spin_wait_started(struct xe_spin *spin); diff --git a/tests/intel/xe_dma_buf_sync.c b/tests/intel/xe_dma_buf_sync.c index 29d675154..627f4c1e5 100644 --- a/tests/intel/xe_dma_buf_sync.c +++ b/tests/intel/xe_dma_buf_sync.c @@ -144,7 +144,6 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, uint64_t sdi_offset = (char *)&data[i]->data - (char *)data[i]; uint64_t sdi_addr = addr + sdi_offset; uint64_t spin_offset = (char *)&data[i]->spin - (char *)data[i]; - uint64_t spin_addr = addr + spin_offset; struct drm_xe_sync sync[2] = { { .flags = DRM_XE_SYNC_SYNCOBJ, }, { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }, @@ -153,14 +152,15 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, .num_batch_buffer = 1, .syncs = to_user_pointer(sync), }; + struct xe_spin_opts spin_opts = { .addr = addr + spin_offset, .preempt = true }; uint32_t syncobj; int b = 0; int sync_fd; /* Write spinner on FD[0] */ - xe_spin_init(&data[i]->spin, spin_addr, true); + xe_spin_init(&data[i]->spin, &spin_opts); exec.exec_queue_id = exec_queue[0]; - exec.address = spin_addr; + exec.address = spin_opts.addr; xe_exec(fd[0], &exec); /* Export prime BO as sync file and veify business */ diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c index f364a4b7a..d7d8dd8fb 100644 --- a/tests/intel/xe_exec_balancer.c +++ b/tests/intel/xe_exec_balancer.c @@ -52,6 +52,7 @@ static void test_all_active(int fd, int gt, int class) struct { struct xe_spin spin; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; struct drm_xe_engine_class_instance *hwe; struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; int i, num_placements = 0; @@ -90,16 +91,14 @@ static void test_all_active(int fd, int gt, int class) xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); for (i = 0; i < num_placements; i++) { - uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = addr + spin_offset; - - xe_spin_init(&data[i].spin, spin_addr, false); + spin_opts.addr = addr + (char *)&data[i].spin - (char *)data; + xe_spin_init(&data[i].spin, &spin_opts); sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; sync[1].flags |= DRM_XE_SYNC_SIGNAL; sync[1].handle = syncobjs[i]; exec.exec_queue_id = exec_queues[i]; - exec.address = spin_addr; + exec.address = spin_opts.addr; xe_exec(fd, &exec); xe_spin_wait_started(&data[i].spin); } diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c index a2d33baf1..be6bbada6 100644 --- a/tests/intel/xe_exec_reset.c +++ b/tests/intel/xe_exec_reset.c @@ -44,6 +44,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) size_t bo_size; uint32_t bo = 0; struct xe_spin *spin; + struct xe_spin_opts spin_opts = { .addr = addr, .preempt = false }; vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); bo_size = sizeof(*spin); @@ -60,7 +61,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) sync[0].handle = syncobj_create(fd, 0); xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); - xe_spin_init(spin, addr, false); + xe_spin_init(spin, &spin_opts); sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; sync[1].flags |= DRM_XE_SYNC_SIGNAL; @@ -165,6 +166,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; struct drm_xe_engine_class_instance *hwe; struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; int i, j, b, num_placements = 0, bad_batches = 1; @@ -236,7 +238,6 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = base_addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = base_addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = base_addr + sdi_offset; uint64_t exec_addr; @@ -247,8 +248,9 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, batches[j] = batch_addr; if (i < bad_batches) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = base_addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; @@ -368,6 +370,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; int i, b; igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); @@ -417,15 +420,15 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = base_addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = base_addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = base_addr + sdi_offset; uint64_t exec_addr; int e = i % n_exec_queues; if (!i) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = base_addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; @@ -539,6 +542,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t exec_sync; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; int i, b; igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); @@ -593,15 +597,15 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = base_addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = base_addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = base_addr + sdi_offset; uint64_t exec_addr; int e = i % n_exec_queues; if (!i) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = base_addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c index e64c1639a..ff4ebc280 100644 --- a/tests/intel/xe_exec_threads.c +++ b/tests/intel/xe_exec_threads.c @@ -486,6 +486,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; int i, j, b, hang_exec_queue = n_exec_queues / 2; bool owns_vm = false, owns_fd = false; @@ -562,15 +563,15 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = addr + sdi_offset; uint64_t exec_addr; int e = i % n_exec_queues; if (flags & HANG && e == hang_exec_queue && i == e) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c index e42c04e33..dc1850338 100644 --- a/tests/intel/xe_vm.c +++ b/tests/intel/xe_vm.c @@ -727,6 +727,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = true }; int i, b; vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); @@ -755,14 +756,14 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = addr + sdi_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = addr + spin_offset; int e = i; if (i == 0) { /* Cork 1st exec_queue with a spinner */ - xe_spin_init(&data[i].spin, spin_addr, true); + spin_opts.addr = addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); exec.exec_queue_id = exec_queues[e]; - exec.address = spin_addr; + exec.address = spin_opts.addr; sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; sync[1].flags |= DRM_XE_SYNC_SIGNAL; sync[1].handle = syncobjs[e]; -- 2.30.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v3 2/3] lib/xe_spin: fixed duration xe_spin capability 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 0/3] " Marcin Bernatowicz 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 1/3] lib/xe_spin: xe_spin_opts for xe_spin initialization Marcin Bernatowicz @ 2023-09-05 14:23 ` Marcin Bernatowicz 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 3/3] tests/xe_spin_batch: spin-fixed-duration Marcin Bernatowicz 2 siblings, 0 replies; 11+ messages in thread From: Marcin Bernatowicz @ 2023-09-05 14:23 UTC (permalink / raw) To: igt-dev Extended spinner with fixed duration capability. It allows to prepare fixed duration (ex. 10ms) workloads and take workloads/second measurements, a handy utility for scheduling tests. v2: - added asserts in div64_u64_round_up, duration_to_ctx_ticks, simplified loop_addr (Zbyszek) - corrected patch title (Kamil) v3: - div64_u64_round_up assert on overflow (Kamil) - enum indentation cleanup in xe_spin.c (Kamil) Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> --- lib/xe/xe_spin.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++- lib/xe/xe_spin.h | 8 +++- 2 files changed, 103 insertions(+), 2 deletions(-) diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c index 27f837ef9..54ae2d3ac 100644 --- a/lib/xe/xe_spin.c +++ b/lib/xe/xe_spin.c @@ -16,6 +16,50 @@ #include "xe_ioctl.h" #include "xe_spin.h" +static uint32_t read_timestamp_frequency(int fd, int gt_id) +{ + struct xe_device *dev = xe_device_get(fd); + + igt_assert(dev && dev->gts && dev->gts->num_gt); + igt_assert(gt_id >= 0 && gt_id <= dev->gts->num_gt); + + return dev->gts->gts[gt_id].clock_freq; +} + +static uint64_t div64_u64_round_up(const uint64_t x, const uint64_t y) +{ + igt_assert(y > 0); + igt_assert_lte_u64(x, UINT64_MAX - (y - 1)); + + return (x + y - 1) / y; +} + +/** + * duration_to_ctx_ticks: + * @fd: opened device + * @gt_id: tile id + * @duration_ns: duration in nanoseconds to be converted to context timestamp ticks + * @return: duration converted to context timestamp ticks. + */ +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t duration_ns) +{ + uint32_t f = read_timestamp_frequency(fd, gt_id); + uint64_t ctx_ticks = div64_u64_round_up(duration_ns * f, NSEC_PER_SEC); + + igt_assert_lt_u64(ctx_ticks, XE_SPIN_MAX_CTX_TICKS); + + return ctx_ticks; +} + +#define MI_SRM_CS_MMIO (1 << 19) +#define MI_LRI_CS_MMIO (1 << 19) +#define MI_LRR_DST_CS_MMIO (1 << 19) +#define MI_LRR_SRC_CS_MMIO (1 << 18) +#define CTX_TIMESTAMP 0x3a8; +#define CS_GPR(x) (0x600 + 8 * (x)) + +enum { START_TS, NOW_TS }; + /** * xe_spin_init: * @spin: pointer to mapped bo in which spinner code will be written @@ -23,13 +67,28 @@ */ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts) { - uint64_t loop_addr = opts->addr + offsetof(struct xe_spin, batch); + uint64_t loop_addr; uint64_t start_addr = opts->addr + offsetof(struct xe_spin, start); uint64_t end_addr = opts->addr + offsetof(struct xe_spin, end); + uint64_t ticks_delta_addr = opts->addr + offsetof(struct xe_spin, ticks_delta); + uint64_t pad_addr = opts->addr + offsetof(struct xe_spin, pad); int b = 0; spin->start = 0; spin->end = 0xffffffff; + spin->ticks_delta = 0; + + if (opts->ctx_ticks) { + /* store start timestamp */ + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; + spin->batch[b++] = CS_GPR(START_TS) + 4; + spin->batch[b++] = 0; + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; + spin->batch[b++] = CTX_TIMESTAMP; + spin->batch[b++] = CS_GPR(START_TS); + } + + loop_addr = opts->addr + b * sizeof(uint32_t); spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; spin->batch[b++] = start_addr; @@ -39,6 +98,42 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts) if (opts->preempt) spin->batch[b++] = (0x5 << 23); + if (opts->ctx_ticks) { + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; + spin->batch[b++] = CS_GPR(NOW_TS) + 4; + spin->batch[b++] = 0; + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; + spin->batch[b++] = CTX_TIMESTAMP; + spin->batch[b++] = CS_GPR(NOW_TS); + + /* delta = now - start; inverted to match COND_BBE */ + spin->batch[b++] = MI_MATH(4); + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + spin->batch[b++] = MI_MATH_SUB; + spin->batch[b++] = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + /* Save delta for reading by COND_BBE */ + spin->batch[b++] = MI_STORE_REGISTER_MEM | MI_SRM_CS_MMIO | 2; + spin->batch[b++] = CS_GPR(NOW_TS); + spin->batch[b++] = ticks_delta_addr; + spin->batch[b++] = ticks_delta_addr >> 32; + + /* Delay between SRM and COND_BBE to post the writes */ + for (int n = 0; n < 8; n++) { + spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; + spin->batch[b++] = pad_addr; + spin->batch[b++] = pad_addr >> 32; + spin->batch[b++] = 0xc0ffee; + } + + /* Break if delta [time elapsed] > ns */ + spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; + spin->batch[b++] = ~(opts->ctx_ticks); + spin->batch[b++] = ticks_delta_addr; + spin->batch[b++] = ticks_delta_addr >> 32; + } + spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; spin->batch[b++] = 0; spin->batch[b++] = end_addr; diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h index 9f1d33294..f1abc1102 100644 --- a/lib/xe/xe_spin.h +++ b/lib/xe/xe_spin.h @@ -15,27 +15,33 @@ #include "xe_query.h" #include "lib/igt_dummyload.h" +#define XE_SPIN_MAX_CTX_TICKS UINT32_MAX - 1000 + /** struct xe_spin_opts * * @addr: offset of spinner within vm * @preempt: allow spinner to be preempted or not + * @ctx_ticks: number of ticks after which spinner is stopped, applied if > 0 * * Used to initialize struct xe_spin spinner behavior. */ struct xe_spin_opts { uint64_t addr; bool preempt; + uint32_t ctx_ticks; }; /* Mapped GPU object */ struct xe_spin { - uint32_t batch[16]; + uint32_t batch[128]; uint64_t pad; uint32_t start; uint32_t end; + uint32_t ticks_delta; }; igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt); +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns); void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts); #define xe_spin_init_opts(fd, ...) \ -- 2.30.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v3 3/3] tests/xe_spin_batch: spin-fixed-duration 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 0/3] " Marcin Bernatowicz 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 1/3] lib/xe_spin: xe_spin_opts for xe_spin initialization Marcin Bernatowicz 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 2/3] lib/xe_spin: fixed duration xe_spin capability Marcin Bernatowicz @ 2023-09-05 14:23 ` Marcin Bernatowicz 2 siblings, 0 replies; 11+ messages in thread From: Marcin Bernatowicz @ 2023-09-05 14:23 UTC (permalink / raw) To: igt-dev Basic test for xe_spin with fixed duration. v2: Added assert for expected spinner duration. (Zbyszek) A median of 5x100ms spins duration is computed, which should satisfy CI runs, although better accuracy is achieved with disabled logging (echo 0 > /sys/module/drm/parameters/debug). Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> --- tests/intel/xe_spin_batch.c | 72 +++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c index 26f9daf36..6dcd89558 100644 --- a/tests/intel/xe_spin_batch.c +++ b/tests/intel/xe_spin_batch.c @@ -1,8 +1,10 @@ #include "igt.h" +#include "igt_syncobj.h" #include "lib/intel_reg.h" #include "xe_drm.h" #include "xe/xe_ioctl.h" #include "xe/xe_query.h" +#include "xe/xe_spin.h" /** * TEST: Tests for spin batch submissons. @@ -138,6 +140,73 @@ static void spin_all(int fd, int gt, int class) xe_vm_destroy(fd, vm); } +/** + * SUBTEST: spin-fixed-duration + * Description: Basic test which validates the functionality of xe_spin with fixed duration. + * Run type: FULL + */ +static void xe_spin_fixed_duration(int fd) +{ + uint64_t ahnd; + uint32_t vm; + unsigned int exec_queue; + uint32_t bo; + size_t bo_size; + struct xe_spin *spin; + uint64_t spin_addr; + struct drm_xe_sync sync = { + .handle = syncobj_create(fd, 0), + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, + }; + struct drm_xe_exec exec = { + .num_batch_buffer = 1, + .num_syncs = 1, + .syncs = to_user_pointer(&sync), + }; + struct timespec tv; + const uint64_t duration_ns = NSEC_PER_SEC / 10; /* 100ms */ + double elapsed_ms; + int i; + igt_stats_t stats; + + vm = xe_vm_create(fd, 0, 0); + exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC); + bo_size = ALIGN(sizeof(*spin) + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); + bo = xe_bo_create(fd, 0, vm, bo_size); + spin = xe_bo_map(fd, bo, bo_size); + spin_addr = intel_allocator_alloc_with_strategy(ahnd, bo, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); + xe_vm_bind_sync(fd, vm, bo, 0, spin_addr, bo_size); + xe_spin_init_opts(spin, .addr = spin_addr, + .preempt = true, + .ctx_ticks = duration_to_ctx_ticks(fd, 0, duration_ns)); + exec.address = spin_addr; + exec.exec_queue_id = exec_queue; + +#define NSAMPLES 5 + igt_stats_init_with_size(&stats, NSAMPLES); + for (i = 0; i < NSAMPLES; ++i) { + igt_gettime(&tv); + xe_exec(fd, &exec); + xe_spin_wait_started(spin); + igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL)); + igt_stats_push_float(&stats, igt_nsec_elapsed(&tv) * 1e-6); + syncobj_reset(fd, &sync.handle, 1); + igt_debug("i=%d %.2fms\n", i, stats.values_f[i]); + } + elapsed_ms = igt_stats_get_median(&stats); + igt_info("%.0fms spin took %.2fms (median)\n", duration_ns * 1e-6, elapsed_ms); + igt_assert(elapsed_ms < duration_ns * 1.5e-6 && elapsed_ms > duration_ns * 0.5e-6); + + xe_vm_unbind_sync(fd, vm, 0, spin_addr, bo_size); + syncobj_destroy(fd, sync.handle); + gem_munmap(spin, bo_size); + gem_close(fd, bo); + xe_exec_queue_destroy(fd, exec_queue); + xe_vm_destroy(fd, vm); + put_ahnd(ahnd); +} + igt_main { struct drm_xe_engine_class_instance *hwe; @@ -163,6 +232,9 @@ igt_main spin_all(fd, gt, class); } + igt_subtest("spin-fixed-duration") + xe_spin_fixed_duration(fd); + igt_fixture drm_close_driver(fd); } -- 2.30.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-09-05 14:58 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-08-18 10:21 [igt-dev] [PATCH i-g-t v2 0/2] lib/xe_spin: introduced fixed duration xe_spin Marcin Bernatowicz 2023-08-18 10:21 ` [igt-dev] [PATCH i-g-t v2 1/2] lib/xe_spin: fixed duration xe_spin capability Marcin Bernatowicz 2023-08-18 10:21 ` [igt-dev] [PATCH i-g-t v2 2/2] tests/xe_spin_batch: spin-fixed-duration Marcin Bernatowicz 2023-08-18 11:10 ` [igt-dev] ✗ GitLab.Pipeline: warning for lib/xe_spin: introduced fixed duration xe_spin Patchwork 2023-08-18 11:29 ` [igt-dev] ○ CI.xeBAT: info " Patchwork 2023-08-18 11:43 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork 2023-08-19 16:59 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 0/3] " Marcin Bernatowicz 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 1/3] lib/xe_spin: xe_spin_opts for xe_spin initialization Marcin Bernatowicz 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 2/3] lib/xe_spin: fixed duration xe_spin capability Marcin Bernatowicz 2023-09-05 14:23 ` [igt-dev] [PATCH i-g-t v3 3/3] tests/xe_spin_batch: spin-fixed-duration Marcin Bernatowicz
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