* [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support
@ 2023-08-18 17:20 Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 1/8] target/loongarch: Log I/O write accesses to CSR registers Philippe Mathieu-Daudé
` (7 more replies)
0 siblings, 8 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-18 17:20 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé,
Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen,
Song Gao
v2:
- Do no rename loongarch_cpu_get/set_pc (rth)
- Rebased Jiajie's patches for convenience
- Added rth's R-b
Jiajie, this series contains few notes I took while
reviewing your series adding loongarch32 support [*].
If your series isn't merged, consider rebasing it on
this one.
Regards,
Phil.
[*] https://lore.kernel.org/qemu-devel/20230817093121.1053890-1-gaosong@loongson.cn/
Jiajie Chen (3):
target/loongarch: Add function to check current arch
target/loongarch: Add new object class for loongarch32 cpus
target/loongarch: Add GDB support for loongarch32 mode
Philippe Mathieu-Daudé (4):
target/loongarch: Log I/O write accesses to CSR registers
target/loongarch: Remove duplicated disas_set_info assignment
target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU
target/loongarch: Extract 64-bit specifics to
loongarch64_cpu_class_init
Song Gao (1):
target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW
configs/targets/loongarch64-softmmu.mak | 2 +-
target/loongarch/cpu.h | 12 +++++
target/loongarch/cpu.c | 62 +++++++++++++++++++------
target/loongarch/gdbstub.c | 32 ++++++++++---
gdb-xml/loongarch-base32.xml | 45 ++++++++++++++++++
5 files changed, 132 insertions(+), 21 deletions(-)
create mode 100644 gdb-xml/loongarch-base32.xml
--
2.41.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/8] target/loongarch: Log I/O write accesses to CSR registers
2023-08-18 17:20 [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Philippe Mathieu-Daudé
@ 2023-08-18 17:20 ` Philippe Mathieu-Daudé
2023-08-19 7:33 ` gaosong
2023-08-18 17:20 ` [PATCH v2 2/8] target/loongarch: Remove duplicated disas_set_info assignment Philippe Mathieu-Daudé
` (6 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-18 17:20 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé,
Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen,
Song Gao
Various CSR registers have Read/Write fields. We might
want to see guest trying to change such registers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/loongarch/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ad93ecac92..7107968699 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -544,6 +544,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
static void loongarch_qemu_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
+ qemu_log_mask(LOG_UNIMP, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
}
static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/8] target/loongarch: Remove duplicated disas_set_info assignment
2023-08-18 17:20 [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 1/8] target/loongarch: Log I/O write accesses to CSR registers Philippe Mathieu-Daudé
@ 2023-08-18 17:20 ` Philippe Mathieu-Daudé
2023-08-19 7:34 ` gaosong
2023-08-18 17:20 ` [PATCH v2 3/8] target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW Philippe Mathieu-Daudé
` (5 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-18 17:20 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé,
Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen,
Song Gao, Richard Henderson
Commit 228021f05e ("target/loongarch: Add core definition") sets
disas_set_info to loongarch_cpu_disas_set_info. Probably due to
a failed git-rebase, commit ca61e75071 ("target/loongarch: Add gdb
support") also sets it to the same value. Remove the duplication.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 7107968699..dc617be36f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -723,7 +723,6 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = loongarch_cpu_disas_set_info;
cc->gdb_read_register = loongarch_cpu_gdb_read_register;
cc->gdb_write_register = loongarch_cpu_gdb_write_register;
- cc->disas_set_info = loongarch_cpu_disas_set_info;
cc->gdb_num_core_regs = 35;
cc->gdb_core_xml_file = "loongarch-base64.xml";
cc->gdb_stop_before_watchpoint = true;
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/8] target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW
2023-08-18 17:20 [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 1/8] target/loongarch: Log I/O write accesses to CSR registers Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 2/8] target/loongarch: Remove duplicated disas_set_info assignment Philippe Mathieu-Daudé
@ 2023-08-18 17:20 ` Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 4/8] target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU Philippe Mathieu-Daudé
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-18 17:20 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé,
Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen,
Song Gao, Richard Henderson
From: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230817093121.1053890-11-gaosong@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/loongarch/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index dc617be36f..a1ebc20330 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -391,6 +391,7 @@ static void loongarch_la464_initfn(Object *obj)
data = FIELD_DP32(data, CPUCFG2, LSX, 1),
data = FIELD_DP32(data, CPUCFG2, LLFTP, 1);
data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
+ data = FIELD_DP32(data, CPUCFG2, LSPW, 1);
data = FIELD_DP32(data, CPUCFG2, LAM, 1);
env->cpucfg[2] = data;
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 4/8] target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU
2023-08-18 17:20 [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2023-08-18 17:20 ` [PATCH v2 3/8] target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW Philippe Mathieu-Daudé
@ 2023-08-18 17:20 ` Philippe Mathieu-Daudé
2023-08-18 17:33 ` Richard Henderson
2023-08-18 17:20 ` [PATCH v2 5/8] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init Philippe Mathieu-Daudé
` (3 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-18 17:20 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé,
Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen,
Song Gao
In preparation of introducing TYPE_LOONGARCH32_CPU, introduce
an abstract TYPE_LOONGARCH64_CPU.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/loongarch/cpu.h | 1 +
target/loongarch/cpu.c | 12 +++++++++---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index fa371ca8ba..c50b3a5ef3 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -377,6 +377,7 @@ struct ArchCPU {
};
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
+#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
LOONGARCH_CPU)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index a1ebc20330..34d6c5a31d 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -734,9 +734,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
#endif
}
-#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
+#define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \
{ \
- .parent = TYPE_LOONGARCH_CPU, \
+ .parent = TYPE_LOONGARCH##size##_CPU, \
.instance_init = initfn, \
.name = LOONGARCH_CPU_TYPE_NAME(model), \
}
@@ -752,7 +752,13 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
.class_size = sizeof(LoongArchCPUClass),
.class_init = loongarch_cpu_class_init,
},
- DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn),
+ {
+ .name = TYPE_LOONGARCH64_CPU,
+ .parent = TYPE_LOONGARCH_CPU,
+
+ .abstract = true,
+ },
+ DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
};
DEFINE_TYPES(loongarch_cpu_type_infos)
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 5/8] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init
2023-08-18 17:20 [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2023-08-18 17:20 ` [PATCH v2 4/8] target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU Philippe Mathieu-Daudé
@ 2023-08-18 17:20 ` Philippe Mathieu-Daudé
2023-08-18 17:32 ` Richard Henderson
2023-08-18 17:20 ` [PATCH v2 6/8] target/loongarch: Add function to check current arch Philippe Mathieu-Daudé
` (2 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-18 17:20 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé,
Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen,
Song Gao
Extract loongarch64 specific code from loongarch_cpu_class_init()
to a new loongarch64_cpu_class_init().
In preparation of supporting loongarch32 cores, rename these
functions using the '64' suffix.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/loongarch/cpu.c | 27 +++++++++++++++++----------
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 34d6c5a31d..356d039560 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -356,7 +356,7 @@ static bool loongarch_cpu_has_work(CPUState *cs)
#endif
}
-static void loongarch_la464_initfn(Object *obj)
+static void loongarch64_la464_initfn(Object *obj)
{
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
CPULoongArchState *env = &cpu->env;
@@ -695,11 +695,6 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
};
#endif
-static gchar *loongarch_gdb_arch_name(CPUState *cs)
-{
- return g_strdup("loongarch64");
-}
-
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
{
LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
@@ -724,16 +719,27 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = loongarch_cpu_disas_set_info;
cc->gdb_read_register = loongarch_cpu_gdb_read_register;
cc->gdb_write_register = loongarch_cpu_gdb_write_register;
- cc->gdb_num_core_regs = 35;
- cc->gdb_core_xml_file = "loongarch-base64.xml";
cc->gdb_stop_before_watchpoint = true;
- cc->gdb_arch_name = loongarch_gdb_arch_name;
#ifdef CONFIG_TCG
cc->tcg_ops = &loongarch_tcg_ops;
#endif
}
+static gchar *loongarch64_gdb_arch_name(CPUState *cs)
+{
+ return g_strdup("loongarch64");
+}
+
+static void loongarch64_cpu_class_init(ObjectClass *c, void *data)
+{
+ CPUClass *cc = CPU_CLASS(c);
+
+ cc->gdb_num_core_regs = 35;
+ cc->gdb_core_xml_file = "loongarch-base64.xml";
+ cc->gdb_arch_name = loongarch64_gdb_arch_name;
+}
+
#define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \
{ \
.parent = TYPE_LOONGARCH##size##_CPU, \
@@ -757,8 +763,9 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
.parent = TYPE_LOONGARCH_CPU,
.abstract = true,
+ .class_init = loongarch64_cpu_class_init,
},
- DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
+ DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch64_la464_initfn),
};
DEFINE_TYPES(loongarch_cpu_type_infos)
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 6/8] target/loongarch: Add function to check current arch
2023-08-18 17:20 [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2023-08-18 17:20 ` [PATCH v2 5/8] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init Philippe Mathieu-Daudé
@ 2023-08-18 17:20 ` Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 7/8] target/loongarch: Add new object class for loongarch32 cpus Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 8/8] target/loongarch: Add GDB support for loongarch32 mode Philippe Mathieu-Daudé
7 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-18 17:20 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé,
Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen,
Song Gao, Richard Henderson
From: Jiajie Chen <c@jia.je>
Add is_la64 function to check if the current cpucfg[1].arch equals to
2(LA64).
Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230817093121.1053890-2-gaosong@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/loongarch/cpu.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index c50b3a5ef3..3235ad081f 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -132,6 +132,11 @@ FIELD(CPUCFG1, HP, 24, 1)
FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
FIELD(CPUCFG1, MSG_INT, 26, 1)
+/* cpucfg[1].arch */
+#define CPUCFG1_ARCH_LA32R 0
+#define CPUCFG1_ARCH_LA32 1
+#define CPUCFG1_ARCH_LA64 2
+
/* cpucfg[2] bits */
FIELD(CPUCFG2, FP, 0, 1)
FIELD(CPUCFG2, FP_SP, 1, 1)
@@ -421,6 +426,11 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
#endif
}
+static inline bool is_la64(CPULoongArchState *env)
+{
+ return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
+}
+
/*
* LoongArch CPUs hardware flags.
*/
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 7/8] target/loongarch: Add new object class for loongarch32 cpus
2023-08-18 17:20 [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2023-08-18 17:20 ` [PATCH v2 6/8] target/loongarch: Add function to check current arch Philippe Mathieu-Daudé
@ 2023-08-18 17:20 ` Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 8/8] target/loongarch: Add GDB support for loongarch32 mode Philippe Mathieu-Daudé
7 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-18 17:20 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé,
Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen,
Song Gao, Richard Henderson
From: Jiajie Chen <c@jia.je>
Add object class stub for future loongarch32 cpus.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230817093121.1053890-3-gaosong@loongson.cn>
[Rebased on TYPE_LOONGARCH64_CPU introduction]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/loongarch/cpu.h | 1 +
target/loongarch/cpu.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 3235ad081f..b8af491041 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -382,6 +382,7 @@ struct ArchCPU {
};
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
+#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 356d039560..5082506f10 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -726,6 +726,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
#endif
}
+static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
+{
+}
+
static gchar *loongarch64_gdb_arch_name(CPUState *cs)
{
return g_strdup("loongarch64");
@@ -758,6 +762,13 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
.class_size = sizeof(LoongArchCPUClass),
.class_init = loongarch_cpu_class_init,
},
+ {
+ .name = TYPE_LOONGARCH32_CPU,
+ .parent = TYPE_LOONGARCH_CPU,
+
+ .abstract = true,
+ .class_init = loongarch32_cpu_class_init,
+ },
{
.name = TYPE_LOONGARCH64_CPU,
.parent = TYPE_LOONGARCH_CPU,
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 8/8] target/loongarch: Add GDB support for loongarch32 mode
2023-08-18 17:20 [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2023-08-18 17:20 ` [PATCH v2 7/8] target/loongarch: Add new object class for loongarch32 cpus Philippe Mathieu-Daudé
@ 2023-08-18 17:20 ` Philippe Mathieu-Daudé
7 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-18 17:20 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé,
Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen,
Song Gao, Richard Henderson
From: Jiajie Chen <c@jia.je>
GPRs and PC are 32-bit wide in loongarch32 mode.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230817093121.1053890-4-gaosong@loongson.cn>
[PMD: Rebased, set gdb_num_core_regs]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
configs/targets/loongarch64-softmmu.mak | 2 +-
target/loongarch/cpu.c | 10 ++++++
target/loongarch/gdbstub.c | 32 ++++++++++++++----
gdb-xml/loongarch-base32.xml | 45 +++++++++++++++++++++++++
4 files changed, 81 insertions(+), 8 deletions(-)
create mode 100644 gdb-xml/loongarch-base32.xml
diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
index 9abc99056f..f23780fdd8 100644
--- a/configs/targets/loongarch64-softmmu.mak
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -1,5 +1,5 @@
TARGET_ARCH=loongarch64
TARGET_BASE_ARCH=loongarch
TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
+TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
TARGET_NEED_FDT=y
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 5082506f10..f42e8497d6 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -726,8 +726,18 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
#endif
}
+static gchar *loongarch32_gdb_arch_name(CPUState *cs)
+{
+ return g_strdup("loongarch32");
+}
+
static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
{
+ CPUClass *cc = CPU_CLASS(c);
+
+ cc->gdb_num_core_regs = 35;
+ cc->gdb_core_xml_file = "loongarch-base32.xml";
+ cc->gdb_arch_name = loongarch32_gdb_arch_name;
}
static gchar *loongarch64_gdb_arch_name(CPUState *cs)
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 0752fff924..a462e25737 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -34,16 +34,25 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
+ uint64_t val;
if (0 <= n && n < 32) {
- return gdb_get_regl(mem_buf, env->gpr[n]);
+ val = env->gpr[n];
} else if (n == 32) {
/* orig_a0 */
- return gdb_get_regl(mem_buf, 0);
+ val = 0;
} else if (n == 33) {
- return gdb_get_regl(mem_buf, env->pc);
+ val = env->pc;
} else if (n == 34) {
- return gdb_get_regl(mem_buf, env->CSR_BADV);
+ val = env->CSR_BADV;
+ }
+
+ if (0 <= n && n <= 34) {
+ if (is_la64(env)) {
+ return gdb_get_reg64(mem_buf, val);
+ } else {
+ return gdb_get_reg32(mem_buf, val);
+ }
}
return 0;
}
@@ -52,15 +61,24 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
- target_ulong tmp = ldtul_p(mem_buf);
+ target_ulong tmp;
+ int read_length;
int length = 0;
+ if (is_la64(env)) {
+ tmp = ldq_p(mem_buf);
+ read_length = 8;
+ } else {
+ tmp = ldl_p(mem_buf);
+ read_length = 4;
+ }
+
if (0 <= n && n < 32) {
env->gpr[n] = tmp;
- length = sizeof(target_ulong);
+ length = read_length;
} else if (n == 33) {
env->pc = tmp;
- length = sizeof(target_ulong);
+ length = read_length;
}
return length;
}
diff --git a/gdb-xml/loongarch-base32.xml b/gdb-xml/loongarch-base32.xml
new file mode 100644
index 0000000000..af47bbd3da
--- /dev/null
+++ b/gdb-xml/loongarch-base32.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2022 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.loongarch.base">
+ <reg name="r0" bitsize="32" type="uint32" group="general"/>
+ <reg name="r1" bitsize="32" type="code_ptr" group="general"/>
+ <reg name="r2" bitsize="32" type="data_ptr" group="general"/>
+ <reg name="r3" bitsize="32" type="data_ptr" group="general"/>
+ <reg name="r4" bitsize="32" type="uint32" group="general"/>
+ <reg name="r5" bitsize="32" type="uint32" group="general"/>
+ <reg name="r6" bitsize="32" type="uint32" group="general"/>
+ <reg name="r7" bitsize="32" type="uint32" group="general"/>
+ <reg name="r8" bitsize="32" type="uint32" group="general"/>
+ <reg name="r9" bitsize="32" type="uint32" group="general"/>
+ <reg name="r10" bitsize="32" type="uint32" group="general"/>
+ <reg name="r11" bitsize="32" type="uint32" group="general"/>
+ <reg name="r12" bitsize="32" type="uint32" group="general"/>
+ <reg name="r13" bitsize="32" type="uint32" group="general"/>
+ <reg name="r14" bitsize="32" type="uint32" group="general"/>
+ <reg name="r15" bitsize="32" type="uint32" group="general"/>
+ <reg name="r16" bitsize="32" type="uint32" group="general"/>
+ <reg name="r17" bitsize="32" type="uint32" group="general"/>
+ <reg name="r18" bitsize="32" type="uint32" group="general"/>
+ <reg name="r19" bitsize="32" type="uint32" group="general"/>
+ <reg name="r20" bitsize="32" type="uint32" group="general"/>
+ <reg name="r21" bitsize="32" type="uint32" group="general"/>
+ <reg name="r22" bitsize="32" type="data_ptr" group="general"/>
+ <reg name="r23" bitsize="32" type="uint32" group="general"/>
+ <reg name="r24" bitsize="32" type="uint32" group="general"/>
+ <reg name="r25" bitsize="32" type="uint32" group="general"/>
+ <reg name="r26" bitsize="32" type="uint32" group="general"/>
+ <reg name="r27" bitsize="32" type="uint32" group="general"/>
+ <reg name="r28" bitsize="32" type="uint32" group="general"/>
+ <reg name="r29" bitsize="32" type="uint32" group="general"/>
+ <reg name="r30" bitsize="32" type="uint32" group="general"/>
+ <reg name="r31" bitsize="32" type="uint32" group="general"/>
+ <reg name="orig_a0" bitsize="32" type="uint32" group="general"/>
+ <reg name="pc" bitsize="32" type="code_ptr" group="general"/>
+ <reg name="badv" bitsize="32" type="code_ptr" group="general"/>
+</feature>
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 5/8] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init
2023-08-18 17:20 ` [PATCH v2 5/8] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init Philippe Mathieu-Daudé
@ 2023-08-18 17:32 ` Richard Henderson
0 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2023-08-18 17:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen, Song Gao
On 8/18/23 10:20, Philippe Mathieu-Daudé wrote:
> Extract loongarch64 specific code from loongarch_cpu_class_init()
> to a new loongarch64_cpu_class_init().
>
> In preparation of supporting loongarch32 cores, rename these
> functions using the '64' suffix.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/loongarch/cpu.c | 27 +++++++++++++++++----------
> 1 file changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 34d6c5a31d..356d039560 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -356,7 +356,7 @@ static bool loongarch_cpu_has_work(CPUState *cs)
> #endif
> }
>
> -static void loongarch_la464_initfn(Object *obj)
> +static void loongarch64_la464_initfn(Object *obj)
This rename is not relevant to populating the abstract loongarch64 class.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 4/8] target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU
2023-08-18 17:20 ` [PATCH v2 4/8] target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU Philippe Mathieu-Daudé
@ 2023-08-18 17:33 ` Richard Henderson
0 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2023-08-18 17:33 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen, Song Gao
On 8/18/23 10:20, Philippe Mathieu-Daudé wrote:
> In preparation of introducing TYPE_LOONGARCH32_CPU, introduce
> an abstract TYPE_LOONGARCH64_CPU.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/loongarch/cpu.h | 1 +
> target/loongarch/cpu.c | 12 +++++++++---
> 2 files changed, 10 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/8] target/loongarch: Log I/O write accesses to CSR registers
2023-08-18 17:20 ` [PATCH v2 1/8] target/loongarch: Log I/O write accesses to CSR registers Philippe Mathieu-Daudé
@ 2023-08-19 7:33 ` gaosong
0 siblings, 0 replies; 13+ messages in thread
From: gaosong @ 2023-08-19 7:33 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen
在 2023/8/19 上午1:20, Philippe Mathieu-Daudé 写道:
> Various CSR registers have Read/Write fields. We might
> want to see guest trying to change such registers.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/loongarch/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index ad93ecac92..7107968699 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -544,6 +544,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
> static void loongarch_qemu_write(void *opaque, hwaddr addr,
> uint64_t val, unsigned size)
> {
> + qemu_log_mask(LOG_UNIMP, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx "\n",
> + __func__, addr);
> }
>
> static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Thanks.
Song Gao
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/8] target/loongarch: Remove duplicated disas_set_info assignment
2023-08-18 17:20 ` [PATCH v2 2/8] target/loongarch: Remove duplicated disas_set_info assignment Philippe Mathieu-Daudé
@ 2023-08-19 7:34 ` gaosong
0 siblings, 0 replies; 13+ messages in thread
From: gaosong @ 2023-08-19 7:34 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Xiaojuan Yang, Alex Bennée, Jiajie Chen,
Richard Henderson
在 2023/8/19 上午1:20, Philippe Mathieu-Daudé 写道:
> Commit 228021f05e ("target/loongarch: Add core definition") sets
> disas_set_info to loongarch_cpu_disas_set_info. Probably due to
> a failed git-rebase, commit ca61e75071 ("target/loongarch: Add gdb
> support") also sets it to the same value. Remove the duplication.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/loongarch/cpu.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 7107968699..dc617be36f 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -723,7 +723,6 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
> cc->disas_set_info = loongarch_cpu_disas_set_info;
> cc->gdb_read_register = loongarch_cpu_gdb_read_register;
> cc->gdb_write_register = loongarch_cpu_gdb_write_register;
> - cc->disas_set_info = loongarch_cpu_disas_set_info;
> cc->gdb_num_core_regs = 35;
> cc->gdb_core_xml_file = "loongarch-base64.xml";
> cc->gdb_stop_before_watchpoint = true;
>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Thanks.
Song Gao
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-08-19 7:34 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-18 17:20 [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 1/8] target/loongarch: Log I/O write accesses to CSR registers Philippe Mathieu-Daudé
2023-08-19 7:33 ` gaosong
2023-08-18 17:20 ` [PATCH v2 2/8] target/loongarch: Remove duplicated disas_set_info assignment Philippe Mathieu-Daudé
2023-08-19 7:34 ` gaosong
2023-08-18 17:20 ` [PATCH v2 3/8] target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 4/8] target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU Philippe Mathieu-Daudé
2023-08-18 17:33 ` Richard Henderson
2023-08-18 17:20 ` [PATCH v2 5/8] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init Philippe Mathieu-Daudé
2023-08-18 17:32 ` Richard Henderson
2023-08-18 17:20 ` [PATCH v2 6/8] target/loongarch: Add function to check current arch Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 7/8] target/loongarch: Add new object class for loongarch32 cpus Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 8/8] target/loongarch: Add GDB support for loongarch32 mode Philippe Mathieu-Daudé
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