[Intel-gfx] [PATCH 00/42] Enable Lunar Lake display

[Intel-gfx] [PATCH 00/42] Enable Lunar Lake display

[Lucas De Marchi]

Cross posting this to the i915 and xe mailing lists. The basic platform
enabling for Lunar Lake is already applied in xe[1]. This patch series
adds the display support, that will be driven by i915.

A few notes from the series:

	1. This is based on drm-xe-next branch since this is where it
	   can be tested. It should be good enough for reviewing and
	   getting early feedback, but not for applying. drm-xe-next
	   will soon be on a more recent drm-tip, that will make it
	   easier to get some of the patches landing. All the patches
	   prefixed with drm/i915 are expected to eventually be applied
	   through the drm-intel branch.
	2. The first 6 commits can be ignored: they are things already
	   applied in drm-intel. With the IP/platform separation, there
	   was a lot of prep work besides those patches, that already
	   landed there so we minimize the patches for new platforms.
	3. Patches 7 through 10 can also be ignored: they are not
	   applied yet, but being reviewed in other patch series by its
	   author[2].
	4. Patch 11 allows xe to build when the patches the follow are
	   applied. Depending on the timeline how things end up landing,
	   this patch may need to be squashed in the "Initial Xe display
	   support"
	5. Last patch finally enable the display support in xe once all
	   the patches on the i915 side are applied.

I also ask for the original authors of the patches to double check their
own patches as there were some adjustements needed in order to rebase,
cleanup and fix some of the patches.

Lastly as things get reviewed I may want to split up this series in
smaller pieces and do some re-ordering to expedite the i915
[1] https://patchwork.freedesktop.org/series/122353/
[2] https://patchwork.freedesktop.org/series/120980/

Balasubramani Vivekanandan (3):
  drm/xe/lnl: Add IS_LUNARLAKE
  drm/i915/lnl: Add display definitions
  drm/xe/lnl: Enable the display support

Clint Taylor (3):
  drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL
  drm/i915/xe2lpd: Register DE_RRMR has been removed
  drm/i915/display: Remove FBC capability from fused off pipes

Gustavo Sousa (9):
  drm/i915/display: Remove unused POWER_DOMAIN_MASK
  drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
  drm/i915: Simplify intel_cx0_program_phy_lane() with loop
  drm/i915/cx0: Enable/disable TX only for owned PHY lanes
  drm/i915/cx0: Program vswing only for owned lanes
  drm/i915/lnl: Add fake PCH
  drm/i915/xe2lpd: Add support for DP aux channels
  drm/i915/xe2lpd: Handle port AUX interrupts
  drm/i915/xe2lpd: Add support for HPD

Juha-Pekka Heikkilä (1):
  drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd

Luca Coelho (5):
  drm/i915/tc: rename mtl_tc_port_get_pin_assignment_mask()
  drm/i915/tc: make intel_tc_port_get_lane_mask() static
  drm/i915/tc: move legacy code out of the main _max_lane_count() func
  drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()
  drm/i915/xe2lpd: Read pin assignment from IOM

Lucas De Marchi (5):
  drm/i915: Re-order if/else ladder in intel_detect_pch()
  drm/i915/xe2lpd: Move D2D enable/disable
  drm/i915/xe2lpd: Move registers to PICA
  drm/i915/xe2lpd: Extend Wa_15010685871
  drm/i915/lnl: Add gmbus/ddc support

Matt Roper (3):
  drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
  drm/i915/xe2lpd: Add DC state support
  drm/i915/xe2lpd: FBC is now supported on all pipes

Ravi Kumar Vodapalli (4):
  drm/i915/xe2lpd: Add display power well
  drm/i915/lnl: Add support for CDCLK initialization sequence
  drm/i915/lnl: Add pll table for LNL platform
  drm/i915/lnl: Add support to check c10 phy link rate

Stanislav Lisovskiy (9):
  drm/i915: Start using plane scale factor for relative data rate
  drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB
    allocation
  drm/i915/lnl: Introduce MDCLK
  drm/i915/lnl: Add CDCLK table
  drm/i915/lnl: Start using CDCLK through PLL
  drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
  drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
  drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.
  drm/i915/xe2lpd: Update mbus on post plane updates

 .../gpu/drm/i915/display/intel_atomic_plane.c |  21 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 187 ++++-
 drivers/gpu/drm/i915/display/intel_cdclk.h    |   2 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 660 ++++++++++++++----
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |  71 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  96 ++-
 drivers/gpu/drm/i915/display/intel_display.c  |   5 +-
 .../drm/i915/display/intel_display_device.c   |  18 +
 .../gpu/drm/i915/display/intel_display_irq.c  |   4 +-
 .../drm/i915/display/intel_display_power.c    |   6 +-
 .../i915/display/intel_display_power_map.c    |  55 +-
 .../i915/display/intel_display_power_well.c   |  63 +-
 .../i915/display/intel_display_power_well.h   |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   6 +-
 drivers/gpu/drm/i915/display/intel_dp_aux.c   |  43 +-
 .../gpu/drm/i915/display/intel_dp_aux_regs.h  |  27 +
 drivers/gpu/drm/i915/display/intel_fbc.h      |   2 +
 drivers/gpu/drm/i915/display/intel_gmbus.c    |   5 +-
 .../gpu/drm/i915/display/intel_hotplug_irq.c  |  22 +-
 drivers/gpu/drm/i915/display/intel_tc.c       |  66 +-
 drivers/gpu/drm/i915/display/intel_tc.h       |   3 +-
 .../drm/i915/display/skl_universal_plane.c    |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |  58 +-
 drivers/gpu/drm/i915/display/skl_watermark.h  |   1 +
 .../gpu/drm/i915/display/skl_watermark_regs.h |   2 +
 drivers/gpu/drm/i915/i915_drv.h               |   1 +
 drivers/gpu/drm/i915/i915_gpu_error.c         |   2 +-
 drivers/gpu/drm/i915/i915_reg.h               |  11 +
 drivers/gpu/drm/i915/soc/intel_pch.c          |  12 +-
 drivers/gpu/drm/i915/soc/intel_pch.h          |   2 +
 .../gpu/drm/xe/compat-i915-headers/i915_drv.h |   1 +
 drivers/gpu/drm/xe/xe_pci.c                   |   1 +
 33 files changed, 1211 insertions(+), 247 deletions(-)

-- 
2.40.1

[Intel-xe] [PATCH 00/42] Enable Lunar Lake display

[Lucas De Marchi]

Cross posting this to the i915 and xe mailing lists. The basic platform
enabling for Lunar Lake is already applied in xe[1]. This patch series
adds the display support, that will be driven by i915.

A few notes from the series:

	1. This is based on drm-xe-next branch since this is where it
	   can be tested. It should be good enough for reviewing and
	   getting early feedback, but not for applying. drm-xe-next
	   will soon be on a more recent drm-tip, that will make it
	   easier to get some of the patches landing. All the patches
	   prefixed with drm/i915 are expected to eventually be applied
	   through the drm-intel branch.
	2. The first 6 commits can be ignored: they are things already
	   applied in drm-intel. With the IP/platform separation, there
	   was a lot of prep work besides those patches, that already
	   landed there so we minimize the patches for new platforms.
	3. Patches 7 through 10 can also be ignored: they are not
	   applied yet, but being reviewed in other patch series by its
	   author[2].
	4. Patch 11 allows xe to build when the patches the follow are
	   applied. Depending on the timeline how things end up landing,
	   this patch may need to be squashed in the "Initial Xe display
	   support"
	5. Last patch finally enable the display support in xe once all
	   the patches on the i915 side are applied.

I also ask for the original authors of the patches to double check their
own patches as there were some adjustements needed in order to rebase,
cleanup and fix some of the patches.

Lastly as things get reviewed I may want to split up this series in
smaller pieces and do some re-ordering to expedite the i915
[1] https://patchwork.freedesktop.org/series/122353/
[2] https://patchwork.freedesktop.org/series/120980/

Balasubramani Vivekanandan (3):
  drm/xe/lnl: Add IS_LUNARLAKE
  drm/i915/lnl: Add display definitions
  drm/xe/lnl: Enable the display support

Clint Taylor (3):
  drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL
  drm/i915/xe2lpd: Register DE_RRMR has been removed
  drm/i915/display: Remove FBC capability from fused off pipes

Gustavo Sousa (9):
  drm/i915/display: Remove unused POWER_DOMAIN_MASK
  drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
  drm/i915: Simplify intel_cx0_program_phy_lane() with loop
  drm/i915/cx0: Enable/disable TX only for owned PHY lanes
  drm/i915/cx0: Program vswing only for owned lanes
  drm/i915/lnl: Add fake PCH
  drm/i915/xe2lpd: Add support for DP aux channels
  drm/i915/xe2lpd: Handle port AUX interrupts
  drm/i915/xe2lpd: Add support for HPD

Juha-Pekka Heikkilä (1):
  drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd

Luca Coelho (5):
  drm/i915/tc: rename mtl_tc_port_get_pin_assignment_mask()
  drm/i915/tc: make intel_tc_port_get_lane_mask() static
  drm/i915/tc: move legacy code out of the main _max_lane_count() func
  drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()
  drm/i915/xe2lpd: Read pin assignment from IOM

Lucas De Marchi (5):
  drm/i915: Re-order if/else ladder in intel_detect_pch()
  drm/i915/xe2lpd: Move D2D enable/disable
  drm/i915/xe2lpd: Move registers to PICA
  drm/i915/xe2lpd: Extend Wa_15010685871
  drm/i915/lnl: Add gmbus/ddc support

Matt Roper (3):
  drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
  drm/i915/xe2lpd: Add DC state support
  drm/i915/xe2lpd: FBC is now supported on all pipes

Ravi Kumar Vodapalli (4):
  drm/i915/xe2lpd: Add display power well
  drm/i915/lnl: Add support for CDCLK initialization sequence
  drm/i915/lnl: Add pll table for LNL platform
  drm/i915/lnl: Add support to check c10 phy link rate

Stanislav Lisovskiy (9):
  drm/i915: Start using plane scale factor for relative data rate
  drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB
    allocation
  drm/i915/lnl: Introduce MDCLK
  drm/i915/lnl: Add CDCLK table
  drm/i915/lnl: Start using CDCLK through PLL
  drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
  drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
  drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.
  drm/i915/xe2lpd: Update mbus on post plane updates

 .../gpu/drm/i915/display/intel_atomic_plane.c |  21 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 187 ++++-
 drivers/gpu/drm/i915/display/intel_cdclk.h    |   2 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 660 ++++++++++++++----
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |  71 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  96 ++-
 drivers/gpu/drm/i915/display/intel_display.c  |   5 +-
 .../drm/i915/display/intel_display_device.c   |  18 +
 .../gpu/drm/i915/display/intel_display_irq.c  |   4 +-
 .../drm/i915/display/intel_display_power.c    |   6 +-
 .../i915/display/intel_display_power_map.c    |  55 +-
 .../i915/display/intel_display_power_well.c   |  63 +-
 .../i915/display/intel_display_power_well.h   |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   6 +-
 drivers/gpu/drm/i915/display/intel_dp_aux.c   |  43 +-
 .../gpu/drm/i915/display/intel_dp_aux_regs.h  |  27 +
 drivers/gpu/drm/i915/display/intel_fbc.h      |   2 +
 drivers/gpu/drm/i915/display/intel_gmbus.c    |   5 +-
 .../gpu/drm/i915/display/intel_hotplug_irq.c  |  22 +-
 drivers/gpu/drm/i915/display/intel_tc.c       |  66 +-
 drivers/gpu/drm/i915/display/intel_tc.h       |   3 +-
 .../drm/i915/display/skl_universal_plane.c    |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |  58 +-
 drivers/gpu/drm/i915/display/skl_watermark.h  |   1 +
 .../gpu/drm/i915/display/skl_watermark_regs.h |   2 +
 drivers/gpu/drm/i915/i915_drv.h               |   1 +
 drivers/gpu/drm/i915/i915_gpu_error.c         |   2 +-
 drivers/gpu/drm/i915/i915_reg.h               |  11 +
 drivers/gpu/drm/i915/soc/intel_pch.c          |  12 +-
 drivers/gpu/drm/i915/soc/intel_pch.h          |   2 +
 .../gpu/drm/xe/compat-i915-headers/i915_drv.h |   1 +
 drivers/gpu/drm/xe/xe_pci.c                   |   1 +
 33 files changed, 1211 insertions(+), 247 deletions(-)

-- 
2.40.1

[Intel-gfx] [PATCH 01/42] drm/i915: Start using plane scale factor for relative data rate

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

BSpec clearly instructs us to use plane scale factor when calculating
relative data rate to be used when allocating DDB blocks for each plane.
For some reason we use scale factor for data_rate calculation, which is
used for BW calculations, however we are not using it for DDB calculations.
So lets fix it as described in BSpec 68907.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Garg, Nemesa <nemesa.garg@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230719104833.25366-1-stanislav.lisovskiy@intel.com
(cherry picked from commit a86c75dcdd0374444514c1e40411177ff7afe9bd)
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index edee71664332..cb60165bc415 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -217,6 +217,7 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int width, height;
+	unsigned int rel_data_rate;
 
 	if (plane->id == PLANE_CURSOR)
 		return 0;
@@ -246,7 +247,11 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 		height /= 2;
 	}
 
-	return width * height * fb->format->cpp[color_plane];
+	rel_data_rate = width * height * fb->format->cpp[color_plane];
+
+	return intel_adjusted_rate(&plane_state->uapi.src,
+				   &plane_state->uapi.dst,
+				   rel_data_rate);
 }
 
 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
-- 
2.40.1

[Intel-xe] [PATCH 01/42] drm/i915: Start using plane scale factor for relative data rate

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

BSpec clearly instructs us to use plane scale factor when calculating
relative data rate to be used when allocating DDB blocks for each plane.
For some reason we use scale factor for data_rate calculation, which is
used for BW calculations, however we are not using it for DDB calculations.
So lets fix it as described in BSpec 68907.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Garg, Nemesa <nemesa.garg@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230719104833.25366-1-stanislav.lisovskiy@intel.com
(cherry picked from commit a86c75dcdd0374444514c1e40411177ff7afe9bd)
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index edee71664332..cb60165bc415 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -217,6 +217,7 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int width, height;
+	unsigned int rel_data_rate;
 
 	if (plane->id == PLANE_CURSOR)
 		return 0;
@@ -246,7 +247,11 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 		height /= 2;
 	}
 
-	return width * height * fb->format->cpp[color_plane];
+	rel_data_rate = width * height * fb->format->cpp[color_plane];
+
+	return intel_adjusted_rate(&plane_state->uapi.src,
+				   &plane_state->uapi.dst,
+				   rel_data_rate);
 }
 
 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
-- 
2.40.1

[Intel-gfx] [PATCH 02/42] drm/i915/display: Remove unused POWER_DOMAIN_MASK

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

That macro became unused with commit 323286c81245 ("drm/i915: Move the
power domain->well mappings to intel_display_power_map.c").

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230815201344.298573-1-gustavo.sousa@intel.com
(cherry picked from commit c0eeae21425ed8994f3ba5362c2f2faf5ed6d774)
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 41afb3d611b7..7e2059abae9a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -340,8 +340,6 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
 	mutex_unlock(&power_domains->lock);
 }
 
-#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
-
 static void __async_put_domains_mask(struct i915_power_domains *power_domains,
 				     struct intel_power_domain_mask *mask)
 {
-- 
2.40.1

[Intel-xe] [PATCH 02/42] drm/i915/display: Remove unused POWER_DOMAIN_MASK

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

That macro became unused with commit 323286c81245 ("drm/i915: Move the
power domain->well mappings to intel_display_power_map.c").

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230815201344.298573-1-gustavo.sousa@intel.com
(cherry picked from commit c0eeae21425ed8994f3ba5362c2f2faf5ed6d774)
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 41afb3d611b7..7e2059abae9a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -340,8 +340,6 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
 	mutex_unlock(&power_domains->lock);
 }
 
-#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
-
 static void __async_put_domains_mask(struct i915_power_domains *power_domains,
 				     struct intel_power_domain_mask *mask)
 {
-- 
2.40.1

[Intel-gfx] [PATCH 03/42] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

There are more parts of C10/C20 programming that need to take owned
lanes into account. Define the function intel_cx0_get_owned_lane_mask()
and use it. There will be new users of that function in upcoming
changes.

BSpec: 64539
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230814131331.69516-2-gustavo.sousa@intel.com
(cherry picked from commit 3a8ecd4c3ede7283619536917e61c1aa3b9db6b7)
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 44 ++++++++++++--------
 1 file changed, 27 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1b00ef2c6185..b903ceb0b56a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -46,6 +46,22 @@ static int lane_mask_to_lane(u8 lane_mask)
 	return ilog2(lane_mask);
 }
 
+static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
+					struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+	if (!intel_tc_port_in_dp_alt_mode(dig_port))
+		return INTEL_CX0_BOTH_LANES;
+
+	/*
+	 * In DP-alt with pin assignment D, only PHY lane 0 is owned
+	 * by display and lane 1 is owned by USB.
+	 */
+	return intel_tc_port_fia_max_lane_count(dig_port) > 2
+		? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
+}
+
 static void
 assert_dc_off(struct drm_i915_private *i915)
 {
@@ -2534,17 +2550,15 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
 {
 	enum port port = encoder->port;
 	enum phy phy = intel_port_to_phy(i915, port);
-	bool both_lanes =  intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2;
-	u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 :
-				  INTEL_CX0_LANE0;
-	u32 lane_pipe_reset = both_lanes ?
-			      XELPDP_LANE_PIPE_RESET(0) |
-			      XELPDP_LANE_PIPE_RESET(1) :
-			      XELPDP_LANE_PIPE_RESET(0);
-	u32 lane_phy_current_status = both_lanes ?
-				      XELPDP_LANE_PHY_CURRENT_STATUS(0) |
-				      XELPDP_LANE_PHY_CURRENT_STATUS(1) :
-				      XELPDP_LANE_PHY_CURRENT_STATUS(0);
+	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
+	u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;
+	u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES
+				? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1)
+				: XELPDP_LANE_PIPE_RESET(0);
+	u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES
+					? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
+					   XELPDP_LANE_PHY_CURRENT_STATUS(1))
+					: XELPDP_LANE_PHY_CURRENT_STATUS(0);
 
 	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
 					 XELPDP_PORT_BUF_SOC_PHY_READY,
@@ -2564,15 +2578,11 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
 			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
 
 	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
-		     intel_cx0_get_pclk_refclk_request(both_lanes ?
-						       INTEL_CX0_BOTH_LANES :
-						       INTEL_CX0_LANE0),
+		     intel_cx0_get_pclk_refclk_request(owned_lane_mask),
 		     intel_cx0_get_pclk_refclk_request(lane_mask));
 
 	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
-					 intel_cx0_get_pclk_refclk_ack(both_lanes ?
-								       INTEL_CX0_BOTH_LANES :
-								       INTEL_CX0_LANE0),
+					 intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
 					 intel_cx0_get_pclk_refclk_ack(lane_mask),
 					 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
 		drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
-- 
2.40.1

[Intel-xe] [PATCH 03/42] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

There are more parts of C10/C20 programming that need to take owned
lanes into account. Define the function intel_cx0_get_owned_lane_mask()
and use it. There will be new users of that function in upcoming
changes.

BSpec: 64539
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230814131331.69516-2-gustavo.sousa@intel.com
(cherry picked from commit 3a8ecd4c3ede7283619536917e61c1aa3b9db6b7)
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 44 ++++++++++++--------
 1 file changed, 27 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1b00ef2c6185..b903ceb0b56a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -46,6 +46,22 @@ static int lane_mask_to_lane(u8 lane_mask)
 	return ilog2(lane_mask);
 }
 
+static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
+					struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+	if (!intel_tc_port_in_dp_alt_mode(dig_port))
+		return INTEL_CX0_BOTH_LANES;
+
+	/*
+	 * In DP-alt with pin assignment D, only PHY lane 0 is owned
+	 * by display and lane 1 is owned by USB.
+	 */
+	return intel_tc_port_fia_max_lane_count(dig_port) > 2
+		? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
+}
+
 static void
 assert_dc_off(struct drm_i915_private *i915)
 {
@@ -2534,17 +2550,15 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
 {
 	enum port port = encoder->port;
 	enum phy phy = intel_port_to_phy(i915, port);
-	bool both_lanes =  intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2;
-	u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 :
-				  INTEL_CX0_LANE0;
-	u32 lane_pipe_reset = both_lanes ?
-			      XELPDP_LANE_PIPE_RESET(0) |
-			      XELPDP_LANE_PIPE_RESET(1) :
-			      XELPDP_LANE_PIPE_RESET(0);
-	u32 lane_phy_current_status = both_lanes ?
-				      XELPDP_LANE_PHY_CURRENT_STATUS(0) |
-				      XELPDP_LANE_PHY_CURRENT_STATUS(1) :
-				      XELPDP_LANE_PHY_CURRENT_STATUS(0);
+	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
+	u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;
+	u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES
+				? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1)
+				: XELPDP_LANE_PIPE_RESET(0);
+	u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES
+					? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
+					   XELPDP_LANE_PHY_CURRENT_STATUS(1))
+					: XELPDP_LANE_PHY_CURRENT_STATUS(0);
 
 	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
 					 XELPDP_PORT_BUF_SOC_PHY_READY,
@@ -2564,15 +2578,11 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
 			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
 
 	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
-		     intel_cx0_get_pclk_refclk_request(both_lanes ?
-						       INTEL_CX0_BOTH_LANES :
-						       INTEL_CX0_LANE0),
+		     intel_cx0_get_pclk_refclk_request(owned_lane_mask),
 		     intel_cx0_get_pclk_refclk_request(lane_mask));
 
 	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
-					 intel_cx0_get_pclk_refclk_ack(both_lanes ?
-								       INTEL_CX0_BOTH_LANES :
-								       INTEL_CX0_LANE0),
+					 intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
 					 intel_cx0_get_pclk_refclk_ack(lane_mask),
 					 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
 		drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
-- 
2.40.1

[Intel-gfx] [PATCH 04/42] drm/i915: Simplify intel_cx0_program_phy_lane() with loop

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

It is possible to generalize the "disable" value for the transmitters to
be a bit mask based on the port width and the port reversal boolean,
with a small exception for DP-alt mode with "x1" port width.

Simplify the code by using such a mask and a for-loop instead of using
switch-case statements.

v2:
  - Use (i < 2) instead of (i / 2 == 0) for PHY lane mask selection.
    (Jani)

BSpec: 64539
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230814131331.69516-3-gustavo.sousa@intel.com
(cherry picked from commit 0f5c2e5bd2fc8d2e09043b6bb3c81a889a483997)
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 79 +++++---------------
 1 file changed, 20 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b903ceb0b56a..2b112ed78943 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2604,7 +2604,8 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
 				       struct intel_encoder *encoder, int lane_count,
 				       bool lane_reversal)
 {
-	u8 l0t1, l0t2, l1t1, l1t2;
+	int i;
+	u8 disables;
 	bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
 	enum port port = encoder->port;
 
@@ -2614,66 +2615,26 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
 			      C10_VDR_CTRL_MSGBUS_ACCESS,
 			      MB_WRITE_COMMITTED);
 
-	/* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
-	l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
-	l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
-	l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
-	l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
-
-	l0t1 |= CONTROL2_DISABLE_SINGLE_TX;
-	l0t2 |= CONTROL2_DISABLE_SINGLE_TX;
-	l1t1 |= CONTROL2_DISABLE_SINGLE_TX;
-	l1t2 |= CONTROL2_DISABLE_SINGLE_TX;
-
-	if (lane_reversal) {
-		switch (lane_count) {
-		case 4:
-			l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			fallthrough;
-		case 3:
-			l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			fallthrough;
-		case 2:
-			l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			fallthrough;
-		case 1:
-			l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			break;
-		default:
-			MISSING_CASE(lane_count);
-		}
-	} else {
-		switch (lane_count) {
-		case 4:
-			l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			fallthrough;
-		case 3:
-			l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			fallthrough;
-		case 2:
-			l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			break;
-		case 1:
-			if (dp_alt_mode)
-				l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			else
-				l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			break;
-		default:
-			MISSING_CASE(lane_count);
-		}
+	if (lane_reversal)
+		disables = REG_GENMASK8(3, 0) >> lane_count;
+	else
+		disables = REG_GENMASK8(3, 0) << lane_count;
+
+	if (dp_alt_mode && lane_count == 1) {
+		disables &= ~REG_GENMASK8(1, 0);
+		disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
 	}
 
-	/* disable MLs */
-	intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
-			l0t1, MB_WRITE_COMMITTED);
-	intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
-			l0t2, MB_WRITE_COMMITTED);
-	intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
-			l1t1, MB_WRITE_COMMITTED);
-	intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
-			l1t2, MB_WRITE_COMMITTED);
+	/* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
+	for (i = 0; i < 4; i++) {
+		int tx = i % 2 + 1;
+		u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+
+		intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
+			      CONTROL2_DISABLE_SINGLE_TX,
+			      disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
+			      MB_WRITE_COMMITTED);
+	}
 
 	if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
 		intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
-- 
2.40.1

[Intel-xe] [PATCH 04/42] drm/i915: Simplify intel_cx0_program_phy_lane() with loop

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

It is possible to generalize the "disable" value for the transmitters to
be a bit mask based on the port width and the port reversal boolean,
with a small exception for DP-alt mode with "x1" port width.

Simplify the code by using such a mask and a for-loop instead of using
switch-case statements.

v2:
  - Use (i < 2) instead of (i / 2 == 0) for PHY lane mask selection.
    (Jani)

BSpec: 64539
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230814131331.69516-3-gustavo.sousa@intel.com
(cherry picked from commit 0f5c2e5bd2fc8d2e09043b6bb3c81a889a483997)
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 79 +++++---------------
 1 file changed, 20 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b903ceb0b56a..2b112ed78943 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2604,7 +2604,8 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
 				       struct intel_encoder *encoder, int lane_count,
 				       bool lane_reversal)
 {
-	u8 l0t1, l0t2, l1t1, l1t2;
+	int i;
+	u8 disables;
 	bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
 	enum port port = encoder->port;
 
@@ -2614,66 +2615,26 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
 			      C10_VDR_CTRL_MSGBUS_ACCESS,
 			      MB_WRITE_COMMITTED);
 
-	/* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
-	l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
-	l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
-	l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
-	l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
-
-	l0t1 |= CONTROL2_DISABLE_SINGLE_TX;
-	l0t2 |= CONTROL2_DISABLE_SINGLE_TX;
-	l1t1 |= CONTROL2_DISABLE_SINGLE_TX;
-	l1t2 |= CONTROL2_DISABLE_SINGLE_TX;
-
-	if (lane_reversal) {
-		switch (lane_count) {
-		case 4:
-			l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			fallthrough;
-		case 3:
-			l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			fallthrough;
-		case 2:
-			l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			fallthrough;
-		case 1:
-			l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			break;
-		default:
-			MISSING_CASE(lane_count);
-		}
-	} else {
-		switch (lane_count) {
-		case 4:
-			l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			fallthrough;
-		case 3:
-			l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			fallthrough;
-		case 2:
-			l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			break;
-		case 1:
-			if (dp_alt_mode)
-				l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			else
-				l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
-			break;
-		default:
-			MISSING_CASE(lane_count);
-		}
+	if (lane_reversal)
+		disables = REG_GENMASK8(3, 0) >> lane_count;
+	else
+		disables = REG_GENMASK8(3, 0) << lane_count;
+
+	if (dp_alt_mode && lane_count == 1) {
+		disables &= ~REG_GENMASK8(1, 0);
+		disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
 	}
 
-	/* disable MLs */
-	intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
-			l0t1, MB_WRITE_COMMITTED);
-	intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
-			l0t2, MB_WRITE_COMMITTED);
-	intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
-			l1t1, MB_WRITE_COMMITTED);
-	intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
-			l1t2, MB_WRITE_COMMITTED);
+	/* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
+	for (i = 0; i < 4; i++) {
+		int tx = i % 2 + 1;
+		u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+
+		intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
+			      CONTROL2_DISABLE_SINGLE_TX,
+			      disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
+			      MB_WRITE_COMMITTED);
+	}
 
 	if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
 		intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
-- 
2.40.1

[Intel-gfx] [PATCH 05/42] drm/i915/cx0: Enable/disable TX only for owned PHY lanes

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

Display must not enable or disable transmitters for not-owned PHY lanes.

BSpec: 64539
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230814131331.69516-4-gustavo.sousa@intel.com
(cherry picked from commit 6a62986bb52e3c96372d92486f9461190144a66b)
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 2b112ed78943..93d3a63fe89a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2607,10 +2607,11 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
 	int i;
 	u8 disables;
 	bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
+	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
 	enum port port = encoder->port;
 
 	if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
-		intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
+		intel_cx0_rmw(i915, port, owned_lane_mask,
 			      PHY_C10_VDR_CONTROL(1), 0,
 			      C10_VDR_CTRL_MSGBUS_ACCESS,
 			      MB_WRITE_COMMITTED);
@@ -2625,11 +2626,13 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
 		disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
 	}
 
-	/* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
 	for (i = 0; i < 4; i++) {
 		int tx = i % 2 + 1;
 		u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
 
+		if (!(owned_lane_mask & lane_mask))
+			continue;
+
 		intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
 			      CONTROL2_DISABLE_SINGLE_TX,
 			      disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
@@ -2637,7 +2640,7 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
 	}
 
 	if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
-		intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
+		intel_cx0_rmw(i915, port, owned_lane_mask,
 			      PHY_C10_VDR_CONTROL(1), 0,
 			      C10_VDR_CTRL_UPDATE_CFG,
 			      MB_WRITE_COMMITTED);
-- 
2.40.1

[Intel-xe] [PATCH 05/42] drm/i915/cx0: Enable/disable TX only for owned PHY lanes

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

Display must not enable or disable transmitters for not-owned PHY lanes.

BSpec: 64539
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230814131331.69516-4-gustavo.sousa@intel.com
(cherry picked from commit 6a62986bb52e3c96372d92486f9461190144a66b)
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 2b112ed78943..93d3a63fe89a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2607,10 +2607,11 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
 	int i;
 	u8 disables;
 	bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
+	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
 	enum port port = encoder->port;
 
 	if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
-		intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
+		intel_cx0_rmw(i915, port, owned_lane_mask,
 			      PHY_C10_VDR_CONTROL(1), 0,
 			      C10_VDR_CTRL_MSGBUS_ACCESS,
 			      MB_WRITE_COMMITTED);
@@ -2625,11 +2626,13 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
 		disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
 	}
 
-	/* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
 	for (i = 0; i < 4; i++) {
 		int tx = i % 2 + 1;
 		u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
 
+		if (!(owned_lane_mask & lane_mask))
+			continue;
+
 		intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
 			      CONTROL2_DISABLE_SINGLE_TX,
 			      disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
@@ -2637,7 +2640,7 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
 	}
 
 	if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
-		intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
+		intel_cx0_rmw(i915, port, owned_lane_mask,
 			      PHY_C10_VDR_CONTROL(1), 0,
 			      C10_VDR_CTRL_UPDATE_CFG,
 			      MB_WRITE_COMMITTED);
-- 
2.40.1

[Intel-gfx] [PATCH 06/42] drm/i915/cx0: Program vswing only for owned lanes

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

According to the BSpec, voltage swing programming should be done for
owned PHY lanes. Do not program a not-owned PHY lane.

BSpec: 74103, 74104
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230814131331.69516-5-gustavo.sousa@intel.com
(cherry picked from commit 226fa3ab8be57aecced64d004ee24437d18bbf5f)
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 +++++++++++---------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 93d3a63fe89a..26e256165b80 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -375,6 +375,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct intel_ddi_buf_trans *trans;
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
+	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
 	intel_wakeref_t wakeref;
 	int n_entries, ln;
 
@@ -387,13 +388,13 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 	}
 
 	if (intel_is_c10phy(i915, phy)) {
-		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
 			      0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
-		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3),
+		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CMN(3),
 			      C10_CMN3_TXVBOOST_MASK,
 			      C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
 			      MB_WRITE_UNCOMMITTED);
-		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1),
+		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_TX(1),
 			      C10_TX1_TERMCTL_MASK,
 			      C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
 			      MB_WRITE_COMMITTED);
@@ -401,32 +402,34 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 
 	for (ln = 0; ln < crtc_state->lane_count; ln++) {
 		int level = intel_ddi_level(encoder, crtc_state, ln);
-		int lane, tx;
+		int lane = ln / 2;
+		int tx = ln % 2;
+		u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
 
-		lane = ln / 2;
-		tx = ln % 2;
+		if (!(lane_mask & owned_lane_mask))
+			continue;
 
-		intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0),
+		intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0),
 			      C10_PHY_OVRD_LEVEL_MASK,
 			      C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
 			      MB_WRITE_COMMITTED);
-		intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 1),
+		intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1),
 			      C10_PHY_OVRD_LEVEL_MASK,
 			      C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
 			      MB_WRITE_COMMITTED);
-		intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 2),
+		intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2),
 			      C10_PHY_OVRD_LEVEL_MASK,
 			      C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),
 			      MB_WRITE_COMMITTED);
 	}
 
 	/* Write Override enables in 0xD71 */
-	intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD,
+	intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_OVRD,
 		      0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
 		      MB_WRITE_COMMITTED);
 
 	if (intel_is_c10phy(i915, phy))
-		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
 			      0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
-- 
2.40.1

[Intel-xe] [PATCH 06/42] drm/i915/cx0: Program vswing only for owned lanes

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

According to the BSpec, voltage swing programming should be done for
owned PHY lanes. Do not program a not-owned PHY lane.

BSpec: 74103, 74104
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230814131331.69516-5-gustavo.sousa@intel.com
(cherry picked from commit 226fa3ab8be57aecced64d004ee24437d18bbf5f)
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 +++++++++++---------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 93d3a63fe89a..26e256165b80 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -375,6 +375,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct intel_ddi_buf_trans *trans;
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
+	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
 	intel_wakeref_t wakeref;
 	int n_entries, ln;
 
@@ -387,13 +388,13 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 	}
 
 	if (intel_is_c10phy(i915, phy)) {
-		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
 			      0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
-		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3),
+		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CMN(3),
 			      C10_CMN3_TXVBOOST_MASK,
 			      C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
 			      MB_WRITE_UNCOMMITTED);
-		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1),
+		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_TX(1),
 			      C10_TX1_TERMCTL_MASK,
 			      C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
 			      MB_WRITE_COMMITTED);
@@ -401,32 +402,34 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 
 	for (ln = 0; ln < crtc_state->lane_count; ln++) {
 		int level = intel_ddi_level(encoder, crtc_state, ln);
-		int lane, tx;
+		int lane = ln / 2;
+		int tx = ln % 2;
+		u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
 
-		lane = ln / 2;
-		tx = ln % 2;
+		if (!(lane_mask & owned_lane_mask))
+			continue;
 
-		intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0),
+		intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0),
 			      C10_PHY_OVRD_LEVEL_MASK,
 			      C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
 			      MB_WRITE_COMMITTED);
-		intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 1),
+		intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1),
 			      C10_PHY_OVRD_LEVEL_MASK,
 			      C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
 			      MB_WRITE_COMMITTED);
-		intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 2),
+		intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2),
 			      C10_PHY_OVRD_LEVEL_MASK,
 			      C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),
 			      MB_WRITE_COMMITTED);
 	}
 
 	/* Write Override enables in 0xD71 */
-	intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD,
+	intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_OVRD,
 		      0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
 		      MB_WRITE_COMMITTED);
 
 	if (intel_is_c10phy(i915, phy))
-		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
 			      0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
-- 
2.40.1

[Intel-gfx] [PATCH 07/42] drm/i915/tc: rename mtl_tc_port_get_pin_assignment_mask()

[Lucas De Marchi]

From: Luca Coelho <luciano.coelho@intel.com>

This function doesn't really return the pin assignment mask, but the
max lane count derived from that.  So rename the function to
mtl_tc_port_get_max_lane_count() to better reflect what it really does.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230721111121.369227-2-luciano.coelho@intel.com
---
 drivers/gpu/drm/i915/display/intel_tc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 3ebf41859043..71bbc2b16a0e 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -290,7 +290,7 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
 	       DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
 }
 
-static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
+static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	intel_wakeref_t wakeref;
@@ -325,7 +325,7 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
 	assert_tc_cold_blocked(tc);
 
 	if (DISPLAY_VER(i915) >= 14)
-		return mtl_tc_port_get_pin_assignment_mask(dig_port);
+		return mtl_tc_port_get_max_lane_count(dig_port);
 
 	lane_mask = 0;
 	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
-- 
2.40.1

[Intel-xe] [PATCH 07/42] drm/i915/tc: rename mtl_tc_port_get_pin_assignment_mask()

[Lucas De Marchi]

From: Luca Coelho <luciano.coelho@intel.com>

This function doesn't really return the pin assignment mask, but the
max lane count derived from that.  So rename the function to
mtl_tc_port_get_max_lane_count() to better reflect what it really does.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230721111121.369227-2-luciano.coelho@intel.com
---
 drivers/gpu/drm/i915/display/intel_tc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 3ebf41859043..71bbc2b16a0e 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -290,7 +290,7 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
 	       DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
 }
 
-static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
+static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	intel_wakeref_t wakeref;
@@ -325,7 +325,7 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
 	assert_tc_cold_blocked(tc);
 
 	if (DISPLAY_VER(i915) >= 14)
-		return mtl_tc_port_get_pin_assignment_mask(dig_port);
+		return mtl_tc_port_get_max_lane_count(dig_port);
 
 	lane_mask = 0;
 	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
-- 
2.40.1

[Intel-gfx] [PATCH 08/42] drm/i915/tc: make intel_tc_port_get_lane_mask() static

[Lucas De Marchi]

From: Luca Coelho <luciano.coelho@intel.com>

This function is only used locally, so make it static and remove the
definition from the header file.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20230721111121.369227-3-luciano.coelho@intel.com
---
 drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
 drivers/gpu/drm/i915/display/intel_tc.h | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 71bbc2b16a0e..de848b329f4b 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -260,7 +260,7 @@ assert_tc_port_power_enabled(struct intel_tc_port *tc)
 		    !intel_display_power_is_enabled(i915, tc_port_power_domain(tc)));
 }
 
-u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
+static u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	struct intel_tc_port *tc = to_tc_port(dig_port);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index 3b16491925fa..ffc0e2a74e43 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -19,7 +19,6 @@ bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port);
 bool intel_tc_port_connected(struct intel_encoder *encoder);
 bool intel_tc_port_connected_locked(struct intel_encoder *encoder);
 
-u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
-- 
2.40.1

[Intel-xe] [PATCH 08/42] drm/i915/tc: make intel_tc_port_get_lane_mask() static

[Lucas De Marchi]

From: Luca Coelho <luciano.coelho@intel.com>

This function is only used locally, so make it static and remove the
definition from the header file.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20230721111121.369227-3-luciano.coelho@intel.com
---
 drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
 drivers/gpu/drm/i915/display/intel_tc.h | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 71bbc2b16a0e..de848b329f4b 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -260,7 +260,7 @@ assert_tc_port_power_enabled(struct intel_tc_port *tc)
 		    !intel_display_power_is_enabled(i915, tc_port_power_domain(tc)));
 }
 
-u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
+static u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	struct intel_tc_port *tc = to_tc_port(dig_port);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index 3b16491925fa..ffc0e2a74e43 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -19,7 +19,6 @@ bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port);
 bool intel_tc_port_connected(struct intel_encoder *encoder);
 bool intel_tc_port_connected_locked(struct intel_encoder *encoder);
 
-u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
-- 
2.40.1

[Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

[Lucas De Marchi]

From: Luca Coelho <luciano.coelho@intel.com>

This makes the code a bit more symmetric and readable, especially when
we start adding more display version-specific alternatives.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://lore.kernel.org/r/20230721111121.369227-4-luciano.coelho@intel.com
---
 drivers/gpu/drm/i915/display/intel_tc.c | 32 +++++++++++++++----------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index de848b329f4b..43b8eeba26f8 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -311,23 +311,12 @@ static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
 	}
 }
 
-int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
+static int intel_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
-	struct intel_tc_port *tc = to_tc_port(dig_port);
-	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 	intel_wakeref_t wakeref;
-	u32 lane_mask;
-
-	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
-		return 4;
+	u32 lane_mask = 0;
 
-	assert_tc_cold_blocked(tc);
-
-	if (DISPLAY_VER(i915) >= 14)
-		return mtl_tc_port_get_max_lane_count(dig_port);
-
-	lane_mask = 0;
 	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
 		lane_mask = intel_tc_port_get_lane_mask(dig_port);
 
@@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
 	}
 }
 
+int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	struct intel_tc_port *tc = to_tc_port(dig_port);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
+		return 4;
+
+	assert_tc_cold_blocked(tc);
+
+	if (DISPLAY_VER(i915) >= 14)
+		return mtl_tc_port_get_max_lane_count(dig_port);
+
+	return intel_tc_port_get_max_lane_count(dig_port);
+}
+
 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
 				      int required_lanes)
 {
-- 
2.40.1

[Intel-xe] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

[Lucas De Marchi]

From: Luca Coelho <luciano.coelho@intel.com>

This makes the code a bit more symmetric and readable, especially when
we start adding more display version-specific alternatives.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://lore.kernel.org/r/20230721111121.369227-4-luciano.coelho@intel.com
---
 drivers/gpu/drm/i915/display/intel_tc.c | 32 +++++++++++++++----------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index de848b329f4b..43b8eeba26f8 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -311,23 +311,12 @@ static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
 	}
 }
 
-int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
+static int intel_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
-	struct intel_tc_port *tc = to_tc_port(dig_port);
-	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 	intel_wakeref_t wakeref;
-	u32 lane_mask;
-
-	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
-		return 4;
+	u32 lane_mask = 0;
 
-	assert_tc_cold_blocked(tc);
-
-	if (DISPLAY_VER(i915) >= 14)
-		return mtl_tc_port_get_max_lane_count(dig_port);
-
-	lane_mask = 0;
 	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
 		lane_mask = intel_tc_port_get_lane_mask(dig_port);
 
@@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
 	}
 }
 
+int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	struct intel_tc_port *tc = to_tc_port(dig_port);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
+		return 4;
+
+	assert_tc_cold_blocked(tc);
+
+	if (DISPLAY_VER(i915) >= 14)
+		return mtl_tc_port_get_max_lane_count(dig_port);
+
+	return intel_tc_port_get_max_lane_count(dig_port);
+}
+
 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
 				      int required_lanes)
 {
-- 
2.40.1

[Intel-gfx] [PATCH 10/42] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()

[Lucas De Marchi]

From: Luca Coelho <luciano.coelho@intel.com>

It is irrelevant for the caller that the max lane count is being
derived from a FIA register, so having "fia" in the function name is
irrelevant.  Rename the function accordingly.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230721111121.369227-5-luciano.coelho@intel.com
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.c      | 4 ++--
 drivers/gpu/drm/i915/display/intel_tc.c      | 4 ++--
 drivers/gpu/drm/i915/display/intel_tc.h      | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 26e256165b80..a5918bf30c31 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -58,7 +58,7 @@ static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
 	 * In DP-alt with pin assignment D, only PHY lane 0 is owned
 	 * by display and lane 1 is owned by USB.
 	 */
-	return intel_tc_port_fia_max_lane_count(dig_port) > 2
+	return intel_tc_port_max_lane_count(dig_port) > 2
 		? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9f40da20e88d..84584864511b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -306,13 +306,13 @@ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	int source_max = intel_dp_max_source_lane_count(dig_port);
 	int sink_max = intel_dp->max_sink_lane_count;
-	int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
+	int port_max = intel_tc_port_max_lane_count(dig_port);
 	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 
 	if (lttpr_max)
 		sink_max = min(sink_max, lttpr_max);
 
-	return min3(source_max, sink_max, fia_max);
+	return min3(source_max, sink_max, port_max);
 }
 
 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 43b8eeba26f8..3c94bbcb5497 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -337,7 +337,7 @@ static int intel_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
 	}
 }
 
-int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
+int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	struct intel_tc_port *tc = to_tc_port(dig_port);
@@ -589,7 +589,7 @@ static bool tc_phy_verify_legacy_or_dp_alt_mode(struct intel_tc_port *tc,
 	struct intel_digital_port *dig_port = tc->dig_port;
 	int max_lanes;
 
-	max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
+	max_lanes = intel_tc_port_max_lane_count(dig_port);
 	if (tc->mode == TC_PORT_LEGACY) {
 		drm_WARN_ON(&i915->drm, max_lanes != 4);
 		return true;
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index ffc0e2a74e43..80a61e52850e 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -20,7 +20,7 @@ bool intel_tc_port_connected(struct intel_encoder *encoder);
 bool intel_tc_port_connected_locked(struct intel_encoder *encoder);
 
 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
-int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
+int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
 				      int required_lanes);
 
-- 
2.40.1

[Intel-xe] [PATCH 10/42] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()

[Lucas De Marchi]

From: Luca Coelho <luciano.coelho@intel.com>

It is irrelevant for the caller that the max lane count is being
derived from a FIA register, so having "fia" in the function name is
irrelevant.  Rename the function accordingly.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230721111121.369227-5-luciano.coelho@intel.com
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.c      | 4 ++--
 drivers/gpu/drm/i915/display/intel_tc.c      | 4 ++--
 drivers/gpu/drm/i915/display/intel_tc.h      | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 26e256165b80..a5918bf30c31 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -58,7 +58,7 @@ static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
 	 * In DP-alt with pin assignment D, only PHY lane 0 is owned
 	 * by display and lane 1 is owned by USB.
 	 */
-	return intel_tc_port_fia_max_lane_count(dig_port) > 2
+	return intel_tc_port_max_lane_count(dig_port) > 2
 		? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9f40da20e88d..84584864511b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -306,13 +306,13 @@ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	int source_max = intel_dp_max_source_lane_count(dig_port);
 	int sink_max = intel_dp->max_sink_lane_count;
-	int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
+	int port_max = intel_tc_port_max_lane_count(dig_port);
 	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 
 	if (lttpr_max)
 		sink_max = min(sink_max, lttpr_max);
 
-	return min3(source_max, sink_max, fia_max);
+	return min3(source_max, sink_max, port_max);
 }
 
 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 43b8eeba26f8..3c94bbcb5497 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -337,7 +337,7 @@ static int intel_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
 	}
 }
 
-int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
+int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	struct intel_tc_port *tc = to_tc_port(dig_port);
@@ -589,7 +589,7 @@ static bool tc_phy_verify_legacy_or_dp_alt_mode(struct intel_tc_port *tc,
 	struct intel_digital_port *dig_port = tc->dig_port;
 	int max_lanes;
 
-	max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
+	max_lanes = intel_tc_port_max_lane_count(dig_port);
 	if (tc->mode == TC_PORT_LEGACY) {
 		drm_WARN_ON(&i915->drm, max_lanes != 4);
 		return true;
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index ffc0e2a74e43..80a61e52850e 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -20,7 +20,7 @@ bool intel_tc_port_connected(struct intel_encoder *encoder);
 bool intel_tc_port_connected_locked(struct intel_encoder *encoder);
 
 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
-int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
+int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
 				      int required_lanes);
 
-- 
2.40.1

[Intel-gfx] [PATCH 11/42] drm/xe/lnl: Add IS_LUNARLAKE

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Add IS_LUNARLAKE in the compat-i915-headers. That macro, to be used by
the xe driver, checks for the platform, whereas the macro on the i915
side is always false.

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
 drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index d64d34181790..38b64ff6b9ea 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -79,6 +79,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 #define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, XE_DG2)
 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
+#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
 
 #define IS_HSW_ULT(dev_priv) (dev_priv && 0)
 #define IS_BDW_ULT(dev_priv) (dev_priv && 0)
-- 
2.40.1

[Intel-xe] [PATCH 11/42] drm/xe/lnl: Add IS_LUNARLAKE

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Add IS_LUNARLAKE in the compat-i915-headers. That macro, to be used by
the xe driver, checks for the platform, whereas the macro on the i915
side is always false.

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
 drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index d64d34181790..38b64ff6b9ea 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -79,6 +79,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 #define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, XE_DG2)
 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
+#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
 
 #define IS_HSW_ULT(dev_priv) (dev_priv && 0)
 #define IS_BDW_ULT(dev_priv) (dev_priv && 0)
-- 
2.40.1

[Intel-gfx] [PATCH 12/42] drm/i915/lnl: Add display definitions

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Add Lunar Lake platform definitions for i915 display. The support for
LNL will be added to the xe driver, with i915 only driving the display
side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
i915 module.

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../gpu/drm/i915/display/intel_display_device.c   | 15 +++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h                   |  1 +
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index f87470da25d0..b853cd0c704a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
 		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
 };
 
+static const struct intel_display_device_info xe2_lpd_display = {
+	XE_LPD_FEATURES,
+	.has_cdclk_crawl = 1,
+	.has_cdclk_squash = 1,
+
+	.__runtime_defaults.ip.ver = 20,
+	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
+	.__runtime_defaults.cpu_transcoder_mask =
+		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
+		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
+};
+
 __diag_pop();
 
 #undef INTEL_VGA_DEVICE
@@ -795,6 +809,7 @@ static const struct {
 	const struct intel_display_device_info *display;
 } gmdid_display_map[] = {
 	{ 14,  0, &xe_lpdp_display },
+	{ 20,  0, &xe2_lpd_display },
 };
 
 static const struct intel_display_device_info *
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 07f79b1028e1..96ac9a9cc155 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
 #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
+#define IS_LUNARLAKE(dev_priv)  0
 
 #define IS_METEORLAKE_M(i915) \
 	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
-- 
2.40.1

[Intel-xe] [PATCH 12/42] drm/i915/lnl: Add display definitions

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Add Lunar Lake platform definitions for i915 display. The support for
LNL will be added to the xe driver, with i915 only driving the display
side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
i915 module.

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../gpu/drm/i915/display/intel_display_device.c   | 15 +++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h                   |  1 +
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index f87470da25d0..b853cd0c704a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
 		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
 };
 
+static const struct intel_display_device_info xe2_lpd_display = {
+	XE_LPD_FEATURES,
+	.has_cdclk_crawl = 1,
+	.has_cdclk_squash = 1,
+
+	.__runtime_defaults.ip.ver = 20,
+	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
+	.__runtime_defaults.cpu_transcoder_mask =
+		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
+		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
+};
+
 __diag_pop();
 
 #undef INTEL_VGA_DEVICE
@@ -795,6 +809,7 @@ static const struct {
 	const struct intel_display_device_info *display;
 } gmdid_display_map[] = {
 	{ 14,  0, &xe_lpdp_display },
+	{ 20,  0, &xe2_lpd_display },
 };
 
 static const struct intel_display_device_info *
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 07f79b1028e1..96ac9a9cc155 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
 #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
+#define IS_LUNARLAKE(dev_priv)  0
 
 #define IS_METEORLAKE_M(i915) \
 	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
-- 
2.40.1

[Intel-gfx] [PATCH 13/42] drm/i915: Re-order if/else ladder in intel_detect_pch()

[Lucas De Marchi]

Follow the convention of checking the last platform first and reword the
comment to convey there are more platforms than just DG1.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/soc/intel_pch.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index ba9843cb1b13..cf795ecdcc26 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -216,13 +216,16 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
 	unsigned short id;
 	enum intel_pch pch_type;
 
-	/* DG1 has south engine display on the same PCI device */
-	if (IS_DG1(dev_priv)) {
-		dev_priv->pch_type = PCH_DG1;
-		return;
-	} else if (IS_DG2(dev_priv)) {
+	/*
+	 * South display engine on the same PCI device: just assign the fake
+	 * PCH.
+	 */
+	if (IS_DG2(dev_priv)) {
 		dev_priv->pch_type = PCH_DG2;
 		return;
+	} else if (IS_DG1(dev_priv)) {
+		dev_priv->pch_type = PCH_DG1;
+		return;
 	}
 
 	/*
-- 
2.40.1

[Intel-xe] [PATCH 13/42] drm/i915: Re-order if/else ladder in intel_detect_pch()

[Lucas De Marchi]

Follow the convention of checking the last platform first and reword the
comment to convey there are more platforms than just DG1.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/soc/intel_pch.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index ba9843cb1b13..cf795ecdcc26 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -216,13 +216,16 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
 	unsigned short id;
 	enum intel_pch pch_type;
 
-	/* DG1 has south engine display on the same PCI device */
-	if (IS_DG1(dev_priv)) {
-		dev_priv->pch_type = PCH_DG1;
-		return;
-	} else if (IS_DG2(dev_priv)) {
+	/*
+	 * South display engine on the same PCI device: just assign the fake
+	 * PCH.
+	 */
+	if (IS_DG2(dev_priv)) {
 		dev_priv->pch_type = PCH_DG2;
 		return;
+	} else if (IS_DG1(dev_priv)) {
+		dev_priv->pch_type = PCH_DG1;
+		return;
 	}
 
 	/*
-- 
2.40.1

[Intel-gfx] [PATCH 14/42] drm/i915/lnl: Add fake PCH

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

LNL has south display on the same SoC. As such, define a new fake PCH
entry for it.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
 drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index cf795ecdcc26..5b9a01d26cab 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -220,7 +220,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
 	 * South display engine on the same PCI device: just assign the fake
 	 * PCH.
 	 */
-	if (IS_DG2(dev_priv)) {
+	if (IS_LUNARLAKE(dev_priv)) {
+		dev_priv->pch_type = PCH_LNL;
+		return;
+	} else if (IS_DG2(dev_priv)) {
 		dev_priv->pch_type = PCH_DG2;
 		return;
 	} else if (IS_DG1(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
index 32aff5a70d04..1b03ea60a7a8 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.h
+++ b/drivers/gpu/drm/i915/soc/intel_pch.h
@@ -30,6 +30,7 @@ enum intel_pch {
 	/* Fake PCHs, functionality handled on the same PCI dev */
 	PCH_DG1 = 1024,
 	PCH_DG2,
+	PCH_LNL,
 };
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff80
@@ -66,6 +67,7 @@ enum intel_pch {
 
 #define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
 #define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
+#define HAS_PCH_LNL(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
 #define HAS_PCH_MTP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
 #define HAS_PCH_DG2(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
 #define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
-- 
2.40.1

[Intel-xe] [PATCH 14/42] drm/i915/lnl: Add fake PCH

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

LNL has south display on the same SoC. As such, define a new fake PCH
entry for it.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
 drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index cf795ecdcc26..5b9a01d26cab 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -220,7 +220,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
 	 * South display engine on the same PCI device: just assign the fake
 	 * PCH.
 	 */
-	if (IS_DG2(dev_priv)) {
+	if (IS_LUNARLAKE(dev_priv)) {
+		dev_priv->pch_type = PCH_LNL;
+		return;
+	} else if (IS_DG2(dev_priv)) {
 		dev_priv->pch_type = PCH_DG2;
 		return;
 	} else if (IS_DG1(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
index 32aff5a70d04..1b03ea60a7a8 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.h
+++ b/drivers/gpu/drm/i915/soc/intel_pch.h
@@ -30,6 +30,7 @@ enum intel_pch {
 	/* Fake PCHs, functionality handled on the same PCI dev */
 	PCH_DG1 = 1024,
 	PCH_DG2,
+	PCH_LNL,
 };
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff80
@@ -66,6 +67,7 @@ enum intel_pch {
 
 #define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
 #define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
+#define HAS_PCH_LNL(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
 #define HAS_PCH_MTP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
 #define HAS_PCH_DG2(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
 #define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
-- 
2.40.1

[Intel-gfx] [PATCH 15/42] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

We now start calculating relative plane data rate for sursor plane as
well, as instructed by BSpec and also treat cursor plane same way as
other planes, when doing allocation, i.e not using fixed allocation for
cursor anymore.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c    |  6 +++---
 drivers/gpu/drm/i915/display/skl_watermark.c     | 16 +++++++++-------
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index cb60165bc415..fb13f0bb8c52 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -219,9 +219,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 	int width, height;
 	unsigned int rel_data_rate;
 
-	if (plane->id == PLANE_CURSOR)
-		return 0;
-
 	if (!plane_state->uapi.visible)
 		return 0;
 
@@ -249,6 +246,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 
 	rel_data_rate = width * height * fb->format->cpp[color_plane];
 
+	if (plane->id == PLANE_CURSOR)
+		return rel_data_rate;
+
 	return intel_adjusted_rate(&plane_state->uapi.src,
 				   &plane_state->uapi.dst,
 				   rel_data_rate);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 063929a42a42..64a122d3c9c0 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
 	u64 data_rate = 0;
 
 	for_each_plane_id_on_crtc(crtc, plane_id) {
-		if (plane_id == PLANE_CURSOR)
+		if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
 			continue;
 
 		data_rate += crtc_state->rel_data_rate[plane_id];
@@ -1514,10 +1514,12 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 		return 0;
 
 	/* Allocate fixed number of blocks for cursor. */
-	cursor_size = skl_cursor_allocation(crtc_state, num_active);
-	iter.size -= cursor_size;
-	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
-			   alloc->end - cursor_size, alloc->end);
+	if (DISPLAY_VER(i915) < 20) {
+		cursor_size = skl_cursor_allocation(crtc_state, num_active);
+		iter.size -= cursor_size;
+		skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
+				   alloc->end - cursor_size, alloc->end);
+	}
 
 	iter.data_rate = skl_total_relative_data_rate(crtc_state);
 
@@ -1531,7 +1533,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 			const struct skl_plane_wm *wm =
 				&crtc_state->wm.skl.optimal.planes[plane_id];
 
-			if (plane_id == PLANE_CURSOR) {
+			if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20) {
 				const struct skl_ddb_entry *ddb =
 					&crtc_state->wm.skl.plane_ddb[plane_id];
 
@@ -1579,7 +1581,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 		const struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];
 
-		if (plane_id == PLANE_CURSOR)
+		if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
 			continue;
 
 		if (DISPLAY_VER(i915) < 11 &&
-- 
2.40.1

[Intel-xe] [PATCH 15/42] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

We now start calculating relative plane data rate for sursor plane as
well, as instructed by BSpec and also treat cursor plane same way as
other planes, when doing allocation, i.e not using fixed allocation for
cursor anymore.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c    |  6 +++---
 drivers/gpu/drm/i915/display/skl_watermark.c     | 16 +++++++++-------
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index cb60165bc415..fb13f0bb8c52 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -219,9 +219,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 	int width, height;
 	unsigned int rel_data_rate;
 
-	if (plane->id == PLANE_CURSOR)
-		return 0;
-
 	if (!plane_state->uapi.visible)
 		return 0;
 
@@ -249,6 +246,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 
 	rel_data_rate = width * height * fb->format->cpp[color_plane];
 
+	if (plane->id == PLANE_CURSOR)
+		return rel_data_rate;
+
 	return intel_adjusted_rate(&plane_state->uapi.src,
 				   &plane_state->uapi.dst,
 				   rel_data_rate);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 063929a42a42..64a122d3c9c0 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
 	u64 data_rate = 0;
 
 	for_each_plane_id_on_crtc(crtc, plane_id) {
-		if (plane_id == PLANE_CURSOR)
+		if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
 			continue;
 
 		data_rate += crtc_state->rel_data_rate[plane_id];
@@ -1514,10 +1514,12 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 		return 0;
 
 	/* Allocate fixed number of blocks for cursor. */
-	cursor_size = skl_cursor_allocation(crtc_state, num_active);
-	iter.size -= cursor_size;
-	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
-			   alloc->end - cursor_size, alloc->end);
+	if (DISPLAY_VER(i915) < 20) {
+		cursor_size = skl_cursor_allocation(crtc_state, num_active);
+		iter.size -= cursor_size;
+		skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
+				   alloc->end - cursor_size, alloc->end);
+	}
 
 	iter.data_rate = skl_total_relative_data_rate(crtc_state);
 
@@ -1531,7 +1533,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 			const struct skl_plane_wm *wm =
 				&crtc_state->wm.skl.optimal.planes[plane_id];
 
-			if (plane_id == PLANE_CURSOR) {
+			if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20) {
 				const struct skl_ddb_entry *ddb =
 					&crtc_state->wm.skl.plane_ddb[plane_id];
 
@@ -1579,7 +1581,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 		const struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];
 
-		if (plane_id == PLANE_CURSOR)
+		if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
 			continue;
 
 		if (DISPLAY_VER(i915) < 11 &&
-- 
2.40.1

[Intel-gfx] [PATCH 16/42] drm/i915/xe2lpd: Move D2D enable/disable

[Lucas De Marchi]

Bits to enable/disable and check state for D2D moved from
XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions
mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with
multiple reg location and bitfield layout.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 38 +++++++++++++++++-------
 drivers/gpu/drm/i915/i915_reg.h          |  2 ++
 2 files changed, 30 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 61722556bb47..a9440c0ecf61 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2356,13 +2356,22 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	i915_reg_t reg;
+	u32 set_bits, wait_bits;
 
-	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
-		     XELPDP_PORT_BUF_D2D_LINK_ENABLE);
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		reg = DDI_BUF_CTL(port);
+		set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+	} else {
+		reg = XELPDP_PORT_BUF_CTL1(port);
+		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+	}
 
-	if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
-			 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
-		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
+	intel_de_rmw(dev_priv, reg, 0, set_bits);
+	if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
+		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
 			port_name(port));
 	}
 }
@@ -2809,13 +2818,22 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	i915_reg_t reg;
+	u32 clr_bits, wait_bits;
 
-	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
-		     XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		reg = DDI_BUF_CTL(port);
+		clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+	} else {
+		reg = XELPDP_PORT_BUF_CTL1(port);
+		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+	}
 
-	if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
-			  XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
-		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
+	intel_de_rmw(dev_priv, reg, clr_bits, 0);
+	if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
+		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
 			port_name(port));
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dcf64e32cd54..84c5a76065a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5723,6 +5723,8 @@ enum skl_power_gate {
 /* Known as DDI_CTL_DE in MTL+ */
 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
 #define  DDI_BUF_CTL_ENABLE			(1 << 31)
+#define  XE2LPD_DDI_BUF_D2D_LINK_ENABLE		REG_BIT(29)
+#define  XE2LPD_DDI_BUF_D2D_LINK_STATE		REG_BIT(28)
 #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
 #define  DDI_BUF_EMP_MASK			(0xf << 24)
 #define  DDI_BUF_PHY_LINK_RATE(r)		((r) << 20)
-- 
2.40.1

[Intel-xe] [PATCH 16/42] drm/i915/xe2lpd: Move D2D enable/disable

[Lucas De Marchi]

Bits to enable/disable and check state for D2D moved from
XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions
mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with
multiple reg location and bitfield layout.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 38 +++++++++++++++++-------
 drivers/gpu/drm/i915/i915_reg.h          |  2 ++
 2 files changed, 30 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 61722556bb47..a9440c0ecf61 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2356,13 +2356,22 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	i915_reg_t reg;
+	u32 set_bits, wait_bits;
 
-	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
-		     XELPDP_PORT_BUF_D2D_LINK_ENABLE);
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		reg = DDI_BUF_CTL(port);
+		set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+	} else {
+		reg = XELPDP_PORT_BUF_CTL1(port);
+		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+	}
 
-	if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
-			 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
-		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
+	intel_de_rmw(dev_priv, reg, 0, set_bits);
+	if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
+		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
 			port_name(port));
 	}
 }
@@ -2809,13 +2818,22 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	i915_reg_t reg;
+	u32 clr_bits, wait_bits;
 
-	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
-		     XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		reg = DDI_BUF_CTL(port);
+		clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+	} else {
+		reg = XELPDP_PORT_BUF_CTL1(port);
+		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+	}
 
-	if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
-			  XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
-		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
+	intel_de_rmw(dev_priv, reg, clr_bits, 0);
+	if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
+		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
 			port_name(port));
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dcf64e32cd54..84c5a76065a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5723,6 +5723,8 @@ enum skl_power_gate {
 /* Known as DDI_CTL_DE in MTL+ */
 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
 #define  DDI_BUF_CTL_ENABLE			(1 << 31)
+#define  XE2LPD_DDI_BUF_D2D_LINK_ENABLE		REG_BIT(29)
+#define  XE2LPD_DDI_BUF_D2D_LINK_STATE		REG_BIT(28)
 #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
 #define  DDI_BUF_EMP_MASK			(0xf << 24)
 #define  DDI_BUF_PHY_LINK_RATE(r)		((r) << 20)
-- 
2.40.1

[Intel-gfx] [PATCH 17/42] drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL

[Lucas De Marchi]

From: Clint Taylor <clinton.a.taylor@intel.com>

Display Ver 20 moved the D2D Enable bit to DDI_BUF_CTL(DDI_CTL_DE)
register. We used multiple variables for HDMI and DisplayPort copies of
this register. Consolidate the various locations to use
intel_digital_port saved_port_bits.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 40 +++++++++++++-----------
 drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
 2 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a9440c0ecf61..3147ed174d83 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -324,26 +324,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 				      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
 	/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
-	intel_dp->DP = dig_port->saved_port_bits |
+	dig_port->saved_port_bits |=
 		DDI_PORT_WIDTH(crtc_state->lane_count) |
 		DDI_BUF_TRANS_SELECT(0);
 
 	if (DISPLAY_VER(i915) >= 14) {
 		if (intel_dp_is_uhbr(crtc_state))
-			intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
+			dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
 		else
-			intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
+			dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
 	}
 
 	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
-		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
+		dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
 		if (!intel_tc_port_in_tbt_alt_mode(dig_port))
-			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+			dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 	}
 }
 
@@ -1449,7 +1448,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	int level = intel_ddi_level(encoder, crtc_state, 0);
 	enum port port = encoder->port;
 	u32 signal_levels;
@@ -1466,10 +1465,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
 	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
 		    signal_levels);
 
-	intel_dp->DP &= ~DDI_BUF_EMP_MASK;
-	intel_dp->DP |= signal_levels;
+	dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
+	dig_port->saved_port_bits |= signal_levels;
 
-	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 }
 
@@ -2355,6 +2354,7 @@ static void
 mtl_ddi_enable_d2d(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	enum port port = encoder->port;
 	i915_reg_t reg;
 	u32 set_bits, wait_bits;
@@ -2362,6 +2362,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
 	if (DISPLAY_VER(dev_priv) >= 20) {
 		reg = DDI_BUF_CTL(port);
 		set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
 		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
 	} else {
 		reg = XELPDP_PORT_BUF_CTL1(port);
@@ -2817,6 +2818,7 @@ static void
 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	enum port port = encoder->port;
 	i915_reg_t reg;
 	u32 clr_bits, wait_bits;
@@ -2824,6 +2826,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
 	if (DISPLAY_VER(dev_priv) >= 20) {
 		reg = DDI_BUF_CTL(port);
 		clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
 		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
 	} else {
 		reg = XELPDP_PORT_BUF_CTL1(port);
@@ -3162,7 +3165,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 	struct drm_connector *connector = conn_state->connector;
 	enum port port = encoder->port;
 	enum phy phy = intel_port_to_phy(dev_priv, port);
-	u32 buf_ctl;
 
 	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
 					       crtc_state->hdmi_high_tmds_clock_ratio,
@@ -3228,7 +3230,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 	 * is filled with lane count, already set in the crtc_state.
 	 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
 	 */
-	buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
+	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
 	if (DISPLAY_VER(dev_priv) >= 14) {
 		u8  lane_count = mtl_get_port_width(crtc_state->lane_count);
 		u32 port_buf = 0;
@@ -3241,13 +3243,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
 			     XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
 
-		buf_ctl |= DDI_PORT_WIDTH(lane_count);
+		dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
 	} else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
 		drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
-		buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+		dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 	}
 
-	intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
+	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
 
 	intel_wait_ddi_buf_active(dev_priv, port);
 
@@ -3465,8 +3467,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 	mtl_port_buf_ctl_program(encoder, crtc_state);
 
 	/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
-	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
-	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
+	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 
 	/* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
@@ -3516,8 +3518,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 	    (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
 		adlp_tbt_to_dp_alt_switch_wa(encoder);
 
-	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
-	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
+	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 
 	intel_wait_ddi_buf_active(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 84584864511b..334789be0054 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5631,7 +5631,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 	intel_dp->pps.active_pipe = INVALID_PIPE;
 
 	/* Preserve the current hw state. */
-	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
+	dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
 	intel_dp->attached_connector = intel_connector;
 
 	if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
-- 
2.40.1

[Intel-xe] [PATCH 17/42] drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL

[Lucas De Marchi]

From: Clint Taylor <clinton.a.taylor@intel.com>

Display Ver 20 moved the D2D Enable bit to DDI_BUF_CTL(DDI_CTL_DE)
register. We used multiple variables for HDMI and DisplayPort copies of
this register. Consolidate the various locations to use
intel_digital_port saved_port_bits.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 40 +++++++++++++-----------
 drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
 2 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a9440c0ecf61..3147ed174d83 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -324,26 +324,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 				      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
 	/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
-	intel_dp->DP = dig_port->saved_port_bits |
+	dig_port->saved_port_bits |=
 		DDI_PORT_WIDTH(crtc_state->lane_count) |
 		DDI_BUF_TRANS_SELECT(0);
 
 	if (DISPLAY_VER(i915) >= 14) {
 		if (intel_dp_is_uhbr(crtc_state))
-			intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
+			dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
 		else
-			intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
+			dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
 	}
 
 	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
-		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
+		dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
 		if (!intel_tc_port_in_tbt_alt_mode(dig_port))
-			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+			dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 	}
 }
 
@@ -1449,7 +1448,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	int level = intel_ddi_level(encoder, crtc_state, 0);
 	enum port port = encoder->port;
 	u32 signal_levels;
@@ -1466,10 +1465,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
 	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
 		    signal_levels);
 
-	intel_dp->DP &= ~DDI_BUF_EMP_MASK;
-	intel_dp->DP |= signal_levels;
+	dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
+	dig_port->saved_port_bits |= signal_levels;
 
-	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 }
 
@@ -2355,6 +2354,7 @@ static void
 mtl_ddi_enable_d2d(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	enum port port = encoder->port;
 	i915_reg_t reg;
 	u32 set_bits, wait_bits;
@@ -2362,6 +2362,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
 	if (DISPLAY_VER(dev_priv) >= 20) {
 		reg = DDI_BUF_CTL(port);
 		set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
 		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
 	} else {
 		reg = XELPDP_PORT_BUF_CTL1(port);
@@ -2817,6 +2818,7 @@ static void
 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	enum port port = encoder->port;
 	i915_reg_t reg;
 	u32 clr_bits, wait_bits;
@@ -2824,6 +2826,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
 	if (DISPLAY_VER(dev_priv) >= 20) {
 		reg = DDI_BUF_CTL(port);
 		clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
 		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
 	} else {
 		reg = XELPDP_PORT_BUF_CTL1(port);
@@ -3162,7 +3165,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 	struct drm_connector *connector = conn_state->connector;
 	enum port port = encoder->port;
 	enum phy phy = intel_port_to_phy(dev_priv, port);
-	u32 buf_ctl;
 
 	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
 					       crtc_state->hdmi_high_tmds_clock_ratio,
@@ -3228,7 +3230,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 	 * is filled with lane count, already set in the crtc_state.
 	 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
 	 */
-	buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
+	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
 	if (DISPLAY_VER(dev_priv) >= 14) {
 		u8  lane_count = mtl_get_port_width(crtc_state->lane_count);
 		u32 port_buf = 0;
@@ -3241,13 +3243,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
 			     XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
 
-		buf_ctl |= DDI_PORT_WIDTH(lane_count);
+		dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
 	} else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
 		drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
-		buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+		dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 	}
 
-	intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
+	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
 
 	intel_wait_ddi_buf_active(dev_priv, port);
 
@@ -3465,8 +3467,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 	mtl_port_buf_ctl_program(encoder, crtc_state);
 
 	/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
-	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
-	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
+	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 
 	/* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
@@ -3516,8 +3518,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 	    (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
 		adlp_tbt_to_dp_alt_switch_wa(encoder);
 
-	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
-	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
+	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 
 	intel_wait_ddi_buf_active(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 84584864511b..334789be0054 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5631,7 +5631,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 	intel_dp->pps.active_pipe = INVALID_PIPE;
 
 	/* Preserve the current hw state. */
-	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
+	dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
 	intel_dp->attached_connector = intel_connector;
 
 	if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
-- 
2.40.1

[Intel-xe] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA

[Lucas De Marchi]

Some registers for DDI A/B moved to PICA and now follow the same format
as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:

	- Share the implementation between xe2lpd and previous
	  platforms: there are minor layout changes, it's mostly the
	  register location that changed
	- Handle offsets after TC ports

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 81 ++++++++++---------
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 71 ++++++++++++++--
 drivers/gpu/drm/i915/display/intel_ddi.c      | 18 +++--
 3 files changed, 117 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a5918bf30c31..6533ec417806 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -98,7 +98,7 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
 static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
 					    enum port port, int lane)
 {
-	intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+	intel_de_rmw(i915, xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
 		     0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
 }
 
@@ -106,10 +106,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, i
 {
 	enum phy phy = intel_port_to_phy(i915, port);
 
-	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_RESET);
 
-	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_RESET,
 				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
 		drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
@@ -125,7 +125,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port,
 	enum phy phy = intel_port_to_phy(i915, port);
 
 	if (__intel_de_wait_for_register(i915,
-					 XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+					 xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
 					 XELPDP_PORT_P2M_RESPONSE_READY,
 					 XELPDP_PORT_P2M_RESPONSE_READY,
 					 XELPDP_MSGBUS_TIMEOUT_FAST_US,
@@ -160,7 +160,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
 	int ack;
 	u32 val;
 
-	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
 				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
 		drm_dbg_kms(&i915->drm,
@@ -169,7 +169,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
 		return -ETIMEDOUT;
 	}
 
-	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
 		       XELPDP_PORT_M2P_COMMAND_READ |
 		       XELPDP_PORT_M2P_ADDRESS(addr));
@@ -220,7 +220,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
 	int ack;
 	u32 val;
 
-	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
 				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
 		drm_dbg_kms(&i915->drm,
@@ -229,14 +229,14 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
 		return -ETIMEDOUT;
 	}
 
-	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
 		       (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
 				    XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
 		       XELPDP_PORT_M2P_DATA(data) |
 		       XELPDP_PORT_M2P_ADDRESS(addr));
 
-	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
 				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
 		drm_dbg_kms(&i915->drm,
@@ -249,7 +249,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
 		ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
 		if (ack < 0)
 			return ack;
-	} else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) &
+	} else if ((intel_de_read(i915, xelpdp_port_p2m_msgbus_status_reg(i915, port, lane)) &
 		    XELPDP_PORT_P2M_ERROR_SET)) {
 		drm_dbg_kms(&i915->drm,
 			    "PHY %c Error occurred during write command.\n", phy_name(phy));
@@ -2431,7 +2431,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	u32 val = 0;
 
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
+	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
+		     XELPDP_PORT_REVERSAL,
 		     lane_reversal ? XELPDP_PORT_REVERSAL : 0);
 
 	if (lane_reversal)
@@ -2451,7 +2452,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 	else
 		val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
 
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
 		     XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
 		     XELPDP_SSC_ENABLE_PLLB, val);
@@ -2484,15 +2485,16 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
 						u8 lane_mask, u8 state)
 {
 	enum phy phy = intel_port_to_phy(i915, port);
+	i915_reg_t buf_ctl2_reg = xelpdp_port_buf_ctl2_reg(i915, port);
 	int lane;
 
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+	intel_de_rmw(i915, buf_ctl2_reg,
 		     intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
 		     intel_cx0_get_powerdown_state(lane_mask, state));
 
 	/* Wait for pending transactions.*/
 	for_each_cx0_lane_in_mask(lane_mask, lane)
-		if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+		if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 					    XELPDP_PORT_M2P_TRANSACTION_PENDING,
 					    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
 			drm_dbg_kms(&i915->drm,
@@ -2501,12 +2503,12 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
 			intel_cx0_bus_reset(i915, port, lane);
 		}
 
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+	intel_de_rmw(i915, buf_ctl2_reg,
 		     intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
 		     intel_cx0_get_powerdown_update(lane_mask));
 
 	/* Update Timeout Value */
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
+	if (__intel_de_wait_for_register(i915, buf_ctl2_reg,
 					 intel_cx0_get_powerdown_update(lane_mask), 0,
 					 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
 		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
@@ -2515,10 +2517,10 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
 
 static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
 {
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port),
 		     XELPDP_POWER_STATE_READY_MASK,
 		     XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
+	intel_de_rmw(i915, xelpdp_port_buf_ctl3_reg(i915, port),
 		     XELPDP_POWER_STATE_ACTIVE_MASK |
 		     XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
 		     XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
@@ -2563,28 +2565,28 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
 					   XELPDP_LANE_PHY_CURRENT_STATUS(1))
 					: XELPDP_LANE_PHY_CURRENT_STATUS(0);
 
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_buf_ctl1_reg(i915, port),
 					 XELPDP_PORT_BUF_SOC_PHY_READY,
 					 XELPDP_PORT_BUF_SOC_PHY_READY,
 					 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
 		drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
 			 phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
 
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port),
 		     XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
 		     lane_pipe_reset);
 
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_buf_ctl2_reg(i915, port),
 					 lane_phy_current_status, lane_phy_current_status,
 					 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
 		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
 			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
 
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, port),
 		     intel_cx0_get_pclk_refclk_request(owned_lane_mask),
 		     intel_cx0_get_pclk_refclk_request(lane_mask));
 
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, port),
 					 intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
 					 intel_cx0_get_pclk_refclk_ack(lane_mask),
 					 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
@@ -2595,9 +2597,10 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
 					    CX0_P2_STATE_RESET);
 	intel_cx0_setup_powerdown(i915, port);
 
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0);
+	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port), lane_pipe_reset, 0);
 
-	if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status,
+	if (intel_de_wait_for_clear(i915, xelpdp_port_buf_ctl2_reg(i915, port),
+				    lane_phy_current_status,
 				    XELPDP_PORT_RESET_END_TIMEOUT))
 		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
 			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
@@ -2726,12 +2729,12 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
 	 * LN<Lane for maxPCLK> to "1" to enable PLL.
 	 */
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
 		     intel_cx0_get_pclk_pll_request(maxpclk_lane));
 
 	/* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 					 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
 					 intel_cx0_get_pclk_pll_ack(maxpclk_lane),
 					 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
@@ -2751,7 +2754,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	u32 clock;
-	u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+	u32 val = intel_de_read(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port));
 
 	clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
 
@@ -2804,11 +2807,11 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
 	 */
 	val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
 	val |= XELPDP_FORWARD_CLOCK_UNGATE;
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
 
 	/* 2. Read back PORT_CLOCK_CTL REGISTER */
-	val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+	val = intel_de_read(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port));
 
 	/*
 	 * 3. Follow the Display Voltage Frequency Switching - Sequence
@@ -2819,10 +2822,10 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
 	 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
 	 */
 	val |= XELPDP_TBT_CLOCK_REQUEST;
-	intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
+	intel_de_write(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port), val);
 
 	/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 					 XELPDP_TBT_CLOCK_ACK,
 					 XELPDP_TBT_CLOCK_ACK,
 					 100, 0, NULL))
@@ -2874,7 +2877,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
 	 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
 	 * to "0" to disable PLL.
 	 */
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
 		     intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
 
@@ -2884,7 +2887,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
 	/*
 	 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
 	 */
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 					 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
 					 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
 					 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
@@ -2897,9 +2900,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
 	 */
 
 	/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_DDI_CLOCK_SELECT_MASK, 0);
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
@@ -2918,11 +2921,11 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
 	/*
 	 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
 	 */
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_TBT_CLOCK_REQUEST, 0);
 
 	/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 					 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
 		drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
 			 encoder->base.base.id, encoder->base.name, phy_name(phy));
@@ -2935,7 +2938,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
 	/*
 	 * 5. Program PORT CLOCK CTRL register to disable and gate clocks
 	 */
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_DDI_CLOCK_SELECT_MASK |
 		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index cb5d1be2ba19..4b5b9a97142d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -6,13 +6,15 @@
 #ifndef __INTEL_CX0_PHY_REGS_H__
 #define __INTEL_CX0_PHY_REGS_H__
 
+#include "i915_drv.h"
 #include "i915_reg_defs.h"
+#include "intel_display_limits.h"
 
 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A		0x64040
 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B		0x64140
 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1		0x16F240
 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2		0x16F440
-#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)		_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
@@ -27,7 +29,7 @@
 #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
 #define   XELPDP_PORT_M2P_ADDRESS_MASK			REG_GENMASK(11, 0)
 #define   XELPDP_PORT_M2P_ADDRESS(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
-#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)	_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
@@ -54,7 +56,7 @@
 #define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104
 #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1			0x16F200
 #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2			0x16F400
-#define XELPDP_PORT_BUF_CTL1(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_BUF_CTL1(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
@@ -75,7 +77,7 @@
 #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
 #define   XELPDP_PORT_WIDTH(val)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
 
-#define XELPDP_PORT_BUF_CTL2(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_BUF_CTL2(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
@@ -95,7 +97,7 @@
 #define   XELPDP_POWER_STATE_READY_MASK			REG_GENMASK(7, 4)
 #define   XELPDP_POWER_STATE_READY(val)			REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
 
-#define XELPDP_PORT_BUF_CTL3(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_BUF_CTL3(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
@@ -114,7 +116,7 @@
 #define _XELPDP_PORT_CLOCK_CTL_B			0x641E0
 #define _XELPDP_PORT_CLOCK_CTL_USBC1			0x16F260
 #define _XELPDP_PORT_CLOCK_CTL_USBC2			0x16F460
-#define XELPDP_PORT_CLOCK_CTL(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_CLOCK_CTL(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_CLOCK_CTL_A, \
 										 _XELPDP_PORT_CLOCK_CTL_B, \
 										 _XELPDP_PORT_CLOCK_CTL_USBC1, \
@@ -271,4 +273,61 @@
 #define HDMI_DIV_MASK		REG_GENMASK16(2, 0)
 #define HDMI_DIV(val)		REG_FIELD_PREP16(HDMI_DIV_MASK, val)
 
+/*
+ * All registers are in the same IP, with a single range.  However the registers
+ * for TC_PORT come first.
+ */
+static inline enum port xe2lpd_port_idx(enum port port)
+{
+	return port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A;
+}
+
+static inline i915_reg_t xelpdp_port_clock_ctl_reg(struct drm_i915_private *i915,
+						   enum port port)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_CLOCK_CTL(xe2lpd_port_idx(port)) :
+		XELPDP_PORT_CLOCK_CTL(port);
+}
+
+static inline i915_reg_t xelpdp_port_buf_ctl3_reg(struct drm_i915_private *i915,
+						  enum port port)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_BUF_CTL3(xe2lpd_port_idx(port)) :
+		XELPDP_PORT_BUF_CTL3(port);
+}
+
+static inline i915_reg_t xelpdp_port_buf_ctl2_reg(struct drm_i915_private *i915,
+						  enum port port)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_BUF_CTL2(xe2lpd_port_idx(port)) :
+		XELPDP_PORT_BUF_CTL2(port);
+}
+
+static inline i915_reg_t xelpdp_port_buf_ctl1_reg(struct drm_i915_private *i915,
+						  enum port port)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_BUF_CTL1(xe2lpd_port_idx(port)) :
+		XELPDP_PORT_BUF_CTL1(port);
+}
+
+static inline i915_reg_t xelpdp_port_m2p_msgbus_ctl_reg(struct drm_i915_private *i915,
+							enum port port, int lane)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_M2P_MSGBUS_CTL(xe2lpd_port_idx(port), lane) :
+		XELPDP_PORT_M2P_MSGBUS_CTL(port, lane);
+}
+
+static inline i915_reg_t xelpdp_port_p2m_msgbus_status_reg(struct drm_i915_private *i915,
+							   enum port port, int lane)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_P2M_MSGBUS_STATUS(xe2lpd_port_idx(port), lane) :
+		XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane);
+}
+
 #endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3147ed174d83..3587ddc6d8ed 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -176,7 +176,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
 	int ret;
 
 	/* FIXME: find out why Bspec's 100us timeout is too short */
-	ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
+	ret = wait_for_us((intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port)) &
 			   XELPDP_PORT_BUF_PHY_IDLE), 10000);
 	if (ret)
 		drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
@@ -224,7 +224,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 	}
 
 	if (DISPLAY_VER(dev_priv) >= 14)
-		ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
+		ret = _wait_for(!(intel_de_read(dev_priv,
+						xelpdp_port_buf_ctl1_reg(dev_priv, port)) &
+				  XELPDP_PORT_BUF_PHY_IDLE),
 				timeout_us, 10, 10);
 	else
 		ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
@@ -2365,7 +2367,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
 		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
 		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
 	} else {
-		reg = XELPDP_PORT_BUF_CTL1(port);
+		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
 		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
 		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
 	}
@@ -2385,7 +2387,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
 	enum port port = encoder->port;
 	u32 val;
 
-	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
+	val = intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port));
 	val &= ~XELPDP_PORT_WIDTH_MASK;
 	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
 
@@ -2398,7 +2400,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
 	if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
 		val |= XELPDP_PORT_REVERSAL;
 
-	intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
+	intel_de_write(i915, xelpdp_port_buf_ctl1_reg(i915, port), val);
 }
 
 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
@@ -2409,7 +2411,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
 
 	val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
 	      XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
 		     XELPDP_PORT_BUF_IO_SELECT_TBT, val);
 }
 
@@ -2829,7 +2831,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
 		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
 		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
 	} else {
-		reg = XELPDP_PORT_BUF_CTL1(port);
+		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
 		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
 		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
 	}
@@ -2967,7 +2969,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
 
 	/* De-select Thunderbolt */
 	if (DISPLAY_VER(dev_priv) >= 14)
-		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
+		intel_de_rmw(dev_priv, xelpdp_port_buf_ctl1_reg(dev_priv, encoder->port),
 			     XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
 }
 
-- 
2.40.1

[Intel-gfx] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA

[Lucas De Marchi]

Some registers for DDI A/B moved to PICA and now follow the same format
as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:

	- Share the implementation between xe2lpd and previous
	  platforms: there are minor layout changes, it's mostly the
	  register location that changed
	- Handle offsets after TC ports

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 81 ++++++++++---------
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 71 ++++++++++++++--
 drivers/gpu/drm/i915/display/intel_ddi.c      | 18 +++--
 3 files changed, 117 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a5918bf30c31..6533ec417806 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -98,7 +98,7 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
 static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
 					    enum port port, int lane)
 {
-	intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+	intel_de_rmw(i915, xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
 		     0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
 }
 
@@ -106,10 +106,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, i
 {
 	enum phy phy = intel_port_to_phy(i915, port);
 
-	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_RESET);
 
-	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_RESET,
 				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
 		drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
@@ -125,7 +125,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port,
 	enum phy phy = intel_port_to_phy(i915, port);
 
 	if (__intel_de_wait_for_register(i915,
-					 XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+					 xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
 					 XELPDP_PORT_P2M_RESPONSE_READY,
 					 XELPDP_PORT_P2M_RESPONSE_READY,
 					 XELPDP_MSGBUS_TIMEOUT_FAST_US,
@@ -160,7 +160,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
 	int ack;
 	u32 val;
 
-	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
 				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
 		drm_dbg_kms(&i915->drm,
@@ -169,7 +169,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
 		return -ETIMEDOUT;
 	}
 
-	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
 		       XELPDP_PORT_M2P_COMMAND_READ |
 		       XELPDP_PORT_M2P_ADDRESS(addr));
@@ -220,7 +220,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
 	int ack;
 	u32 val;
 
-	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
 				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
 		drm_dbg_kms(&i915->drm,
@@ -229,14 +229,14 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
 		return -ETIMEDOUT;
 	}
 
-	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
 		       (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
 				    XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
 		       XELPDP_PORT_M2P_DATA(data) |
 		       XELPDP_PORT_M2P_ADDRESS(addr));
 
-	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
 				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
 		drm_dbg_kms(&i915->drm,
@@ -249,7 +249,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
 		ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
 		if (ack < 0)
 			return ack;
-	} else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) &
+	} else if ((intel_de_read(i915, xelpdp_port_p2m_msgbus_status_reg(i915, port, lane)) &
 		    XELPDP_PORT_P2M_ERROR_SET)) {
 		drm_dbg_kms(&i915->drm,
 			    "PHY %c Error occurred during write command.\n", phy_name(phy));
@@ -2431,7 +2431,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	u32 val = 0;
 
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
+	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
+		     XELPDP_PORT_REVERSAL,
 		     lane_reversal ? XELPDP_PORT_REVERSAL : 0);
 
 	if (lane_reversal)
@@ -2451,7 +2452,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 	else
 		val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
 
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
 		     XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
 		     XELPDP_SSC_ENABLE_PLLB, val);
@@ -2484,15 +2485,16 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
 						u8 lane_mask, u8 state)
 {
 	enum phy phy = intel_port_to_phy(i915, port);
+	i915_reg_t buf_ctl2_reg = xelpdp_port_buf_ctl2_reg(i915, port);
 	int lane;
 
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+	intel_de_rmw(i915, buf_ctl2_reg,
 		     intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
 		     intel_cx0_get_powerdown_state(lane_mask, state));
 
 	/* Wait for pending transactions.*/
 	for_each_cx0_lane_in_mask(lane_mask, lane)
-		if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+		if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
 					    XELPDP_PORT_M2P_TRANSACTION_PENDING,
 					    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
 			drm_dbg_kms(&i915->drm,
@@ -2501,12 +2503,12 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
 			intel_cx0_bus_reset(i915, port, lane);
 		}
 
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+	intel_de_rmw(i915, buf_ctl2_reg,
 		     intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
 		     intel_cx0_get_powerdown_update(lane_mask));
 
 	/* Update Timeout Value */
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
+	if (__intel_de_wait_for_register(i915, buf_ctl2_reg,
 					 intel_cx0_get_powerdown_update(lane_mask), 0,
 					 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
 		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
@@ -2515,10 +2517,10 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
 
 static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
 {
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port),
 		     XELPDP_POWER_STATE_READY_MASK,
 		     XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
+	intel_de_rmw(i915, xelpdp_port_buf_ctl3_reg(i915, port),
 		     XELPDP_POWER_STATE_ACTIVE_MASK |
 		     XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
 		     XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
@@ -2563,28 +2565,28 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
 					   XELPDP_LANE_PHY_CURRENT_STATUS(1))
 					: XELPDP_LANE_PHY_CURRENT_STATUS(0);
 
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_buf_ctl1_reg(i915, port),
 					 XELPDP_PORT_BUF_SOC_PHY_READY,
 					 XELPDP_PORT_BUF_SOC_PHY_READY,
 					 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
 		drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
 			 phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
 
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port),
 		     XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
 		     lane_pipe_reset);
 
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_buf_ctl2_reg(i915, port),
 					 lane_phy_current_status, lane_phy_current_status,
 					 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
 		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
 			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
 
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, port),
 		     intel_cx0_get_pclk_refclk_request(owned_lane_mask),
 		     intel_cx0_get_pclk_refclk_request(lane_mask));
 
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, port),
 					 intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
 					 intel_cx0_get_pclk_refclk_ack(lane_mask),
 					 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
@@ -2595,9 +2597,10 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
 					    CX0_P2_STATE_RESET);
 	intel_cx0_setup_powerdown(i915, port);
 
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0);
+	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port), lane_pipe_reset, 0);
 
-	if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status,
+	if (intel_de_wait_for_clear(i915, xelpdp_port_buf_ctl2_reg(i915, port),
+				    lane_phy_current_status,
 				    XELPDP_PORT_RESET_END_TIMEOUT))
 		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
 			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
@@ -2726,12 +2729,12 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
 	 * LN<Lane for maxPCLK> to "1" to enable PLL.
 	 */
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
 		     intel_cx0_get_pclk_pll_request(maxpclk_lane));
 
 	/* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 					 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
 					 intel_cx0_get_pclk_pll_ack(maxpclk_lane),
 					 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
@@ -2751,7 +2754,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	u32 clock;
-	u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+	u32 val = intel_de_read(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port));
 
 	clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
 
@@ -2804,11 +2807,11 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
 	 */
 	val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
 	val |= XELPDP_FORWARD_CLOCK_UNGATE;
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
 
 	/* 2. Read back PORT_CLOCK_CTL REGISTER */
-	val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+	val = intel_de_read(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port));
 
 	/*
 	 * 3. Follow the Display Voltage Frequency Switching - Sequence
@@ -2819,10 +2822,10 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
 	 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
 	 */
 	val |= XELPDP_TBT_CLOCK_REQUEST;
-	intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
+	intel_de_write(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port), val);
 
 	/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 					 XELPDP_TBT_CLOCK_ACK,
 					 XELPDP_TBT_CLOCK_ACK,
 					 100, 0, NULL))
@@ -2874,7 +2877,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
 	 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
 	 * to "0" to disable PLL.
 	 */
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
 		     intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
 
@@ -2884,7 +2887,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
 	/*
 	 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
 	 */
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 					 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
 					 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
 					 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
@@ -2897,9 +2900,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
 	 */
 
 	/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_DDI_CLOCK_SELECT_MASK, 0);
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
@@ -2918,11 +2921,11 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
 	/*
 	 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
 	 */
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_TBT_CLOCK_REQUEST, 0);
 
 	/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
-	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 					 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
 		drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
 			 encoder->base.base.id, encoder->base.name, phy_name(phy));
@@ -2935,7 +2938,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
 	/*
 	 * 5. Program PORT CLOCK CTRL register to disable and gate clocks
 	 */
-	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
 		     XELPDP_DDI_CLOCK_SELECT_MASK |
 		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index cb5d1be2ba19..4b5b9a97142d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -6,13 +6,15 @@
 #ifndef __INTEL_CX0_PHY_REGS_H__
 #define __INTEL_CX0_PHY_REGS_H__
 
+#include "i915_drv.h"
 #include "i915_reg_defs.h"
+#include "intel_display_limits.h"
 
 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A		0x64040
 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B		0x64140
 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1		0x16F240
 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2		0x16F440
-#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)		_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
@@ -27,7 +29,7 @@
 #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
 #define   XELPDP_PORT_M2P_ADDRESS_MASK			REG_GENMASK(11, 0)
 #define   XELPDP_PORT_M2P_ADDRESS(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
-#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)	_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
@@ -54,7 +56,7 @@
 #define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104
 #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1			0x16F200
 #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2			0x16F400
-#define XELPDP_PORT_BUF_CTL1(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_BUF_CTL1(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
@@ -75,7 +77,7 @@
 #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
 #define   XELPDP_PORT_WIDTH(val)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
 
-#define XELPDP_PORT_BUF_CTL2(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_BUF_CTL2(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
@@ -95,7 +97,7 @@
 #define   XELPDP_POWER_STATE_READY_MASK			REG_GENMASK(7, 4)
 #define   XELPDP_POWER_STATE_READY(val)			REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
 
-#define XELPDP_PORT_BUF_CTL3(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_BUF_CTL3(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
@@ -114,7 +116,7 @@
 #define _XELPDP_PORT_CLOCK_CTL_B			0x641E0
 #define _XELPDP_PORT_CLOCK_CTL_USBC1			0x16F260
 #define _XELPDP_PORT_CLOCK_CTL_USBC2			0x16F460
-#define XELPDP_PORT_CLOCK_CTL(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define XELPDP_PORT_CLOCK_CTL(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 										 _XELPDP_PORT_CLOCK_CTL_A, \
 										 _XELPDP_PORT_CLOCK_CTL_B, \
 										 _XELPDP_PORT_CLOCK_CTL_USBC1, \
@@ -271,4 +273,61 @@
 #define HDMI_DIV_MASK		REG_GENMASK16(2, 0)
 #define HDMI_DIV(val)		REG_FIELD_PREP16(HDMI_DIV_MASK, val)
 
+/*
+ * All registers are in the same IP, with a single range.  However the registers
+ * for TC_PORT come first.
+ */
+static inline enum port xe2lpd_port_idx(enum port port)
+{
+	return port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A;
+}
+
+static inline i915_reg_t xelpdp_port_clock_ctl_reg(struct drm_i915_private *i915,
+						   enum port port)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_CLOCK_CTL(xe2lpd_port_idx(port)) :
+		XELPDP_PORT_CLOCK_CTL(port);
+}
+
+static inline i915_reg_t xelpdp_port_buf_ctl3_reg(struct drm_i915_private *i915,
+						  enum port port)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_BUF_CTL3(xe2lpd_port_idx(port)) :
+		XELPDP_PORT_BUF_CTL3(port);
+}
+
+static inline i915_reg_t xelpdp_port_buf_ctl2_reg(struct drm_i915_private *i915,
+						  enum port port)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_BUF_CTL2(xe2lpd_port_idx(port)) :
+		XELPDP_PORT_BUF_CTL2(port);
+}
+
+static inline i915_reg_t xelpdp_port_buf_ctl1_reg(struct drm_i915_private *i915,
+						  enum port port)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_BUF_CTL1(xe2lpd_port_idx(port)) :
+		XELPDP_PORT_BUF_CTL1(port);
+}
+
+static inline i915_reg_t xelpdp_port_m2p_msgbus_ctl_reg(struct drm_i915_private *i915,
+							enum port port, int lane)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_M2P_MSGBUS_CTL(xe2lpd_port_idx(port), lane) :
+		XELPDP_PORT_M2P_MSGBUS_CTL(port, lane);
+}
+
+static inline i915_reg_t xelpdp_port_p2m_msgbus_status_reg(struct drm_i915_private *i915,
+							   enum port port, int lane)
+{
+	return DISPLAY_VER(i915) >= 20 ?
+		XELPDP_PORT_P2M_MSGBUS_STATUS(xe2lpd_port_idx(port), lane) :
+		XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane);
+}
+
 #endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3147ed174d83..3587ddc6d8ed 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -176,7 +176,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
 	int ret;
 
 	/* FIXME: find out why Bspec's 100us timeout is too short */
-	ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
+	ret = wait_for_us((intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port)) &
 			   XELPDP_PORT_BUF_PHY_IDLE), 10000);
 	if (ret)
 		drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
@@ -224,7 +224,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 	}
 
 	if (DISPLAY_VER(dev_priv) >= 14)
-		ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
+		ret = _wait_for(!(intel_de_read(dev_priv,
+						xelpdp_port_buf_ctl1_reg(dev_priv, port)) &
+				  XELPDP_PORT_BUF_PHY_IDLE),
 				timeout_us, 10, 10);
 	else
 		ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
@@ -2365,7 +2367,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
 		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
 		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
 	} else {
-		reg = XELPDP_PORT_BUF_CTL1(port);
+		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
 		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
 		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
 	}
@@ -2385,7 +2387,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
 	enum port port = encoder->port;
 	u32 val;
 
-	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
+	val = intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port));
 	val &= ~XELPDP_PORT_WIDTH_MASK;
 	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
 
@@ -2398,7 +2400,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
 	if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
 		val |= XELPDP_PORT_REVERSAL;
 
-	intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
+	intel_de_write(i915, xelpdp_port_buf_ctl1_reg(i915, port), val);
 }
 
 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
@@ -2409,7 +2411,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
 
 	val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
 	      XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
-	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
+	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
 		     XELPDP_PORT_BUF_IO_SELECT_TBT, val);
 }
 
@@ -2829,7 +2831,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
 		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
 		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
 	} else {
-		reg = XELPDP_PORT_BUF_CTL1(port);
+		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
 		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
 		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
 	}
@@ -2967,7 +2969,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
 
 	/* De-select Thunderbolt */
 	if (DISPLAY_VER(dev_priv) >= 14)
-		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
+		intel_de_rmw(dev_priv, xelpdp_port_buf_ctl1_reg(dev_priv, encoder->port),
 			     XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
 }
 
-- 
2.40.1

[Intel-xe] [PATCH 19/42] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers
like PLANE_AUX_DIST.  However we currently have HAS_FLAT_CCS hardcoded
to 0 since compression isn't ready; we need to make sure this doesn't
cause the display code to go back to trying to write this register.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 3c212d8401c8..4dfd8b627147 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1254,7 +1254,7 @@ icl_plane_update_noarm(struct intel_plane *plane,
 	}
 
 	/* FLAT CCS doesn't need to program AUX_DIST */
-	if (!HAS_FLAT_CCS(dev_priv))
+	if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20)
 		intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
 				  skl_plane_aux_dist(plane_state, color_plane));
 
-- 
2.40.1

[Intel-gfx] [PATCH 19/42] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers
like PLANE_AUX_DIST.  However we currently have HAS_FLAT_CCS hardcoded
to 0 since compression isn't ready; we need to make sure this doesn't
cause the display code to go back to trying to write this register.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 3c212d8401c8..4dfd8b627147 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1254,7 +1254,7 @@ icl_plane_update_noarm(struct intel_plane *plane,
 	}
 
 	/* FLAT CCS doesn't need to program AUX_DIST */
-	if (!HAS_FLAT_CCS(dev_priv))
+	if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20)
 		intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
 				  skl_plane_aux_dist(plane_state, color_plane));
 
-- 
2.40.1

[Intel-gfx] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed

[Lucas De Marchi]

From: Clint Taylor <clinton.a.taylor@intel.com>

Do not read DE_RRMR register after display version 20. This register
contains display state information during GFX state dumps.

Bspec: 69456
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4749f99e6320..fe2fa6f966f2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1755,7 +1755,7 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
 	struct intel_uncore *uncore = gt->_gt->uncore;
 	struct drm_i915_private *i915 = uncore->i915;
 
-	if (GRAPHICS_VER(i915) >= 6)
+	if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)
 		gt->derrmr = intel_uncore_read(uncore, DERRMR);
 
 	if (GRAPHICS_VER(i915) >= 8)
-- 
2.40.1

[Intel-xe] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed

[Lucas De Marchi]

From: Clint Taylor <clinton.a.taylor@intel.com>

Do not read DE_RRMR register after display version 20. This register
contains display state information during GFX state dumps.

Bspec: 69456
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4749f99e6320..fe2fa6f966f2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1755,7 +1755,7 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
 	struct intel_uncore *uncore = gt->_gt->uncore;
 	struct drm_i915_private *i915 = uncore->i915;
 
-	if (GRAPHICS_VER(i915) >= 6)
+	if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)
 		gt->derrmr = intel_uncore_read(uncore, DERRMR);
 
 	if (GRAPHICS_VER(i915) >= 8)
-- 
2.40.1

[Intel-gfx] [PATCH 21/42] drm/i915/xe2lpd: Add display power well

[Lucas De Marchi]

From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>

Add Display Power Well for LNL platform, mostly it is same as MTL
platform so reused the code

Changes are:
1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
   logic xelpdp_aux_power_well_ops functions.
2. PGPICA1 contains type-C capable port slices which requires the well
   to power powered up, so added new power well definition for PGPICA1

BSpec: 68886
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../i915/display/intel_display_power_map.c    | 36 ++++++++++-
 .../i915/display/intel_display_power_well.c   | 63 ++++++++++++++++++-
 .../i915/display/intel_display_power_well.h   |  1 +
 .../gpu/drm/i915/display/intel_dp_aux_regs.h  | 27 ++++++++
 4 files changed, 123 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 5ad04cd42c15..cef3b313c9f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1545,6 +1545,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
 	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
 };
 
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
+		     POWER_DOMAIN_PORT_DDI_LANES_TC1,
+		     POWER_DOMAIN_PORT_DDI_LANES_TC2,
+		     POWER_DOMAIN_PORT_DDI_LANES_TC3,
+		     POWER_DOMAIN_PORT_DDI_LANES_TC4,
+		     POWER_DOMAIN_AUX_USBC1,
+		     POWER_DOMAIN_AUX_USBC2,
+		     POWER_DOMAIN_AUX_USBC3,
+		     POWER_DOMAIN_AUX_USBC4,
+		     POWER_DOMAIN_AUX_TBT1,
+		     POWER_DOMAIN_AUX_TBT2,
+		     POWER_DOMAIN_AUX_TBT3,
+		     POWER_DOMAIN_AUX_TBT4,
+		     POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
+	{
+		.instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
+							&xe2lpd_pwdoms_pica_tc,
+							.id = DISP_PW_ID_NONE),
+					       ),
+		.ops = &xe2lpd_pica_power_well_ops,
+	},
+};
+
+static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
+	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
+	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
+};
+
 static void init_power_well_domains(const struct i915_power_well_instance *inst,
 				    struct i915_power_well *power_well)
 {
@@ -1652,7 +1684,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
 		return 0;
 	}
 
-	if (DISPLAY_VER(i915) >= 14)
+	if (DISPLAY_VER(i915) >= 20)
+		return set_power_wells(power_domains, xe2lpd_power_wells);
+	else if (DISPLAY_VER(i915) >= 14)
 		return set_power_wells(power_domains, xelpdp_power_wells);
 	else if (IS_DG2(i915))
 		return set_power_wells(power_domains, xehpd_power_wells);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 916009894d89..e1fb0bd7b3bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1795,7 +1795,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
 {
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
 
-	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+				XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+	intel_de_rmw(dev_priv, aux_ch_ctl,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
 
@@ -1813,7 +1817,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
 {
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
 
-	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+				XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+	intel_de_rmw(dev_priv, aux_ch_ctl,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     0);
 	usleep_range(10, 30);
@@ -1823,11 +1831,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
 					  struct i915_power_well *power_well)
 {
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+	i915_reg_t aux_ch_ctl;
 
-	return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
+	aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+		     XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+		     XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+	return intel_de_read(dev_priv, aux_ch_ctl) &
 		XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
 }
 
+static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
+					  struct i915_power_well *power_well)
+{
+	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
+		     XE2LPD_PICA_CTL_POWER_REQUEST,
+		     XE2LPD_PICA_CTL_POWER_REQUEST);
+
+	if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
+				  XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+		drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
+
+		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
+	}
+}
+
+static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
+					   struct i915_power_well *power_well)
+{
+	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
+		     XE2LPD_PICA_CTL_POWER_REQUEST,
+		     0);
+
+	if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
+				    XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+		drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
+
+		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
+	}
+}
+
+static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
+					   struct i915_power_well *power_well)
+{
+	return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
+		XE2LPD_PICA_CTL_POWER_STATUS;
+}
+
 const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
 	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = i9xx_always_on_power_well_noop,
@@ -1947,3 +1997,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
 	.disable = xelpdp_aux_power_well_disable,
 	.is_enabled = xelpdp_aux_power_well_enabled,
 };
+
+const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
+	.sync_hw = i9xx_power_well_sync_hw_noop,
+	.enable = xe2lpd_pica_power_well_enable,
+	.disable = xe2lpd_pica_power_well_disable,
+	.is_enabled = xe2lpd_pica_power_well_enabled,
+};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index a8736588314d..9357a9a73c06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
 extern const struct i915_power_well_ops icl_ddi_power_well_ops;
 extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
 extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
+extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
index 5185345277c7..d855f3730381 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
@@ -83,4 +83,31 @@
 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK	REG_GENMASK(4, 0) /* skl+ */
 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)	REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
 
+#define _XE2LPD_DPA_AUX_CH_CTL		0x16FA10
+#define _XE2LPD_DPB_AUX_CH_CTL		0x16FC10
+#define _XE2LPD_DPA_AUX_CH_DATA1	0x16FA14
+#define _XE2LPD_DPB_AUX_CH_DATA1	0x16FC14
+#define XE2LPD_DP_AUX_CH_CTL(aux_ch)		_MMIO(_PICK(aux_ch, \
+						       _XE2LPD_DPA_AUX_CH_CTL, \
+						       _XE2LPD_DPB_AUX_CH_CTL, \
+						       0, /* port/aux_ch C is non-existent */ \
+						       _XELPDP_USBC1_AUX_CH_CTL, \
+						       _XELPDP_USBC2_AUX_CH_CTL, \
+						       _XELPDP_USBC3_AUX_CH_CTL, \
+						       _XELPDP_USBC4_AUX_CH_CTL))
+#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PICK(aux_ch, \
+						       _XE2LPD_DPA_AUX_CH_DATA1, \
+						       _XE2LPD_DPB_AUX_CH_DATA1, \
+						       0, /* port/aux_ch C is non-existent */ \
+						       _XELPDP_USBC1_AUX_CH_DATA1, \
+						       _XELPDP_USBC2_AUX_CH_DATA1, \
+						       _XELPDP_USBC3_AUX_CH_DATA1, \
+						       _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+
+/* PICA Power Well Control register for Xe2 platforms*/
+#define XE2LPD_PICA_PW_CTL	_MMIO(0x16FE04)
+
+#define   XE2LPD_PICA_CTL_POWER_REQUEST BIT(31)
+#define   XE2LPD_PICA_CTL_POWER_STATUS  BIT(30)
+
 #endif /* __INTEL_DP_AUX_REGS_H__ */
-- 
2.40.1

[Intel-xe] [PATCH 21/42] drm/i915/xe2lpd: Add display power well

[Lucas De Marchi]

From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>

Add Display Power Well for LNL platform, mostly it is same as MTL
platform so reused the code

Changes are:
1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
   logic xelpdp_aux_power_well_ops functions.
2. PGPICA1 contains type-C capable port slices which requires the well
   to power powered up, so added new power well definition for PGPICA1

BSpec: 68886
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../i915/display/intel_display_power_map.c    | 36 ++++++++++-
 .../i915/display/intel_display_power_well.c   | 63 ++++++++++++++++++-
 .../i915/display/intel_display_power_well.h   |  1 +
 .../gpu/drm/i915/display/intel_dp_aux_regs.h  | 27 ++++++++
 4 files changed, 123 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 5ad04cd42c15..cef3b313c9f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1545,6 +1545,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
 	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
 };
 
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
+		     POWER_DOMAIN_PORT_DDI_LANES_TC1,
+		     POWER_DOMAIN_PORT_DDI_LANES_TC2,
+		     POWER_DOMAIN_PORT_DDI_LANES_TC3,
+		     POWER_DOMAIN_PORT_DDI_LANES_TC4,
+		     POWER_DOMAIN_AUX_USBC1,
+		     POWER_DOMAIN_AUX_USBC2,
+		     POWER_DOMAIN_AUX_USBC3,
+		     POWER_DOMAIN_AUX_USBC4,
+		     POWER_DOMAIN_AUX_TBT1,
+		     POWER_DOMAIN_AUX_TBT2,
+		     POWER_DOMAIN_AUX_TBT3,
+		     POWER_DOMAIN_AUX_TBT4,
+		     POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
+	{
+		.instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
+							&xe2lpd_pwdoms_pica_tc,
+							.id = DISP_PW_ID_NONE),
+					       ),
+		.ops = &xe2lpd_pica_power_well_ops,
+	},
+};
+
+static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
+	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
+	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
+};
+
 static void init_power_well_domains(const struct i915_power_well_instance *inst,
 				    struct i915_power_well *power_well)
 {
@@ -1652,7 +1684,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
 		return 0;
 	}
 
-	if (DISPLAY_VER(i915) >= 14)
+	if (DISPLAY_VER(i915) >= 20)
+		return set_power_wells(power_domains, xe2lpd_power_wells);
+	else if (DISPLAY_VER(i915) >= 14)
 		return set_power_wells(power_domains, xelpdp_power_wells);
 	else if (IS_DG2(i915))
 		return set_power_wells(power_domains, xehpd_power_wells);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 916009894d89..e1fb0bd7b3bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1795,7 +1795,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
 {
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
 
-	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+				XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+	intel_de_rmw(dev_priv, aux_ch_ctl,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
 
@@ -1813,7 +1817,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
 {
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
 
-	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+				XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+	intel_de_rmw(dev_priv, aux_ch_ctl,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     0);
 	usleep_range(10, 30);
@@ -1823,11 +1831,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
 					  struct i915_power_well *power_well)
 {
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+	i915_reg_t aux_ch_ctl;
 
-	return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
+	aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+		     XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+		     XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+	return intel_de_read(dev_priv, aux_ch_ctl) &
 		XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
 }
 
+static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
+					  struct i915_power_well *power_well)
+{
+	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
+		     XE2LPD_PICA_CTL_POWER_REQUEST,
+		     XE2LPD_PICA_CTL_POWER_REQUEST);
+
+	if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
+				  XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+		drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
+
+		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
+	}
+}
+
+static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
+					   struct i915_power_well *power_well)
+{
+	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
+		     XE2LPD_PICA_CTL_POWER_REQUEST,
+		     0);
+
+	if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
+				    XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+		drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
+
+		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
+	}
+}
+
+static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
+					   struct i915_power_well *power_well)
+{
+	return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
+		XE2LPD_PICA_CTL_POWER_STATUS;
+}
+
 const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
 	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = i9xx_always_on_power_well_noop,
@@ -1947,3 +1997,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
 	.disable = xelpdp_aux_power_well_disable,
 	.is_enabled = xelpdp_aux_power_well_enabled,
 };
+
+const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
+	.sync_hw = i9xx_power_well_sync_hw_noop,
+	.enable = xe2lpd_pica_power_well_enable,
+	.disable = xe2lpd_pica_power_well_disable,
+	.is_enabled = xe2lpd_pica_power_well_enabled,
+};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index a8736588314d..9357a9a73c06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
 extern const struct i915_power_well_ops icl_ddi_power_well_ops;
 extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
 extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
+extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
index 5185345277c7..d855f3730381 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
@@ -83,4 +83,31 @@
 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK	REG_GENMASK(4, 0) /* skl+ */
 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)	REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
 
+#define _XE2LPD_DPA_AUX_CH_CTL		0x16FA10
+#define _XE2LPD_DPB_AUX_CH_CTL		0x16FC10
+#define _XE2LPD_DPA_AUX_CH_DATA1	0x16FA14
+#define _XE2LPD_DPB_AUX_CH_DATA1	0x16FC14
+#define XE2LPD_DP_AUX_CH_CTL(aux_ch)		_MMIO(_PICK(aux_ch, \
+						       _XE2LPD_DPA_AUX_CH_CTL, \
+						       _XE2LPD_DPB_AUX_CH_CTL, \
+						       0, /* port/aux_ch C is non-existent */ \
+						       _XELPDP_USBC1_AUX_CH_CTL, \
+						       _XELPDP_USBC2_AUX_CH_CTL, \
+						       _XELPDP_USBC3_AUX_CH_CTL, \
+						       _XELPDP_USBC4_AUX_CH_CTL))
+#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PICK(aux_ch, \
+						       _XE2LPD_DPA_AUX_CH_DATA1, \
+						       _XE2LPD_DPB_AUX_CH_DATA1, \
+						       0, /* port/aux_ch C is non-existent */ \
+						       _XELPDP_USBC1_AUX_CH_DATA1, \
+						       _XELPDP_USBC2_AUX_CH_DATA1, \
+						       _XELPDP_USBC3_AUX_CH_DATA1, \
+						       _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+
+/* PICA Power Well Control register for Xe2 platforms*/
+#define XE2LPD_PICA_PW_CTL	_MMIO(0x16FE04)
+
+#define   XE2LPD_PICA_CTL_POWER_REQUEST BIT(31)
+#define   XE2LPD_PICA_CTL_POWER_STATUS  BIT(30)
+
 #endif /* __INTEL_DP_AUX_REGS_H__ */
-- 
2.40.1

[Intel-gfx] [PATCH 22/42] drm/i915/xe2lpd: Add DC state support

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists).  The
overall programming and requirements to enter DC states are similar to
those of Xe_LPD+ although AUX transactions do not require DC5/DC6 exit
as they did previously.

Bspec: 68851, 68857, 68886, 69115
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../drm/i915/display/intel_display_power.c    |  4 +++-
 .../i915/display/intel_display_power_map.c    | 19 +++++++++++++++++++
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7e2059abae9a..508a3225d9f0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -944,7 +944,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	if (!HAS_DISPLAY(dev_priv))
 		return 0;
 
-	if (IS_DG2(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 20)
+		max_dc = 2;
+	else if (IS_DG2(dev_priv))
 		max_dc = 1;
 	else if (IS_DG1(dev_priv))
 		max_dc = 3;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index cef3b313c9f5..d74a742437c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1570,9 +1570,28 @@ static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
 	},
 };
 
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off,
+	POWER_DOMAIN_DC_OFF,
+	XELPD_PW_C_POWER_DOMAINS,
+	XELPD_PW_D_POWER_DOMAINS,
+	POWER_DOMAIN_AUDIO_MMIO,
+	POWER_DOMAIN_MODESET,
+	POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = {
+	{
+		.instances = &I915_PW_INSTANCES(
+			I915_PW("DC_off", &xe2lpd_pwdoms_dc_off,
+				.id = SKL_DISP_DC_OFF),
+		),
+		.ops = &gen9_dc_off_power_well_ops,
+	},
+};
+
 static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+	I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff),
 	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
 	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
 };
-- 
2.40.1

[Intel-xe] [PATCH 22/42] drm/i915/xe2lpd: Add DC state support

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists).  The
overall programming and requirements to enter DC states are similar to
those of Xe_LPD+ although AUX transactions do not require DC5/DC6 exit
as they did previously.

Bspec: 68851, 68857, 68886, 69115
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../drm/i915/display/intel_display_power.c    |  4 +++-
 .../i915/display/intel_display_power_map.c    | 19 +++++++++++++++++++
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7e2059abae9a..508a3225d9f0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -944,7 +944,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	if (!HAS_DISPLAY(dev_priv))
 		return 0;
 
-	if (IS_DG2(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 20)
+		max_dc = 2;
+	else if (IS_DG2(dev_priv))
 		max_dc = 1;
 	else if (IS_DG1(dev_priv))
 		max_dc = 3;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index cef3b313c9f5..d74a742437c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1570,9 +1570,28 @@ static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
 	},
 };
 
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off,
+	POWER_DOMAIN_DC_OFF,
+	XELPD_PW_C_POWER_DOMAINS,
+	XELPD_PW_D_POWER_DOMAINS,
+	POWER_DOMAIN_AUDIO_MMIO,
+	POWER_DOMAIN_MODESET,
+	POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = {
+	{
+		.instances = &I915_PW_INSTANCES(
+			I915_PW("DC_off", &xe2lpd_pwdoms_dc_off,
+				.id = SKL_DISP_DC_OFF),
+		),
+		.ops = &gen9_dc_off_power_well_ops,
+	},
+};
+
 static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+	I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff),
 	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
 	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
 };
-- 
2.40.1

[Intel-gfx] [PATCH 23/42] drm/i915/xe2lpd: FBC is now supported on all pipes

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

FBC is no longer limited by pipe.

Bspec: 68881, 68904
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 4adb98afe6ff..6720ec8ee8a2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -20,6 +20,8 @@ struct intel_plane_state;
 enum intel_fbc_id {
 	INTEL_FBC_A,
 	INTEL_FBC_B,
+	INTEL_FBC_C,
+	INTEL_FBC_D,
 
 	I915_MAX_FBCS,
 };
-- 
2.40.1

[Intel-xe] [PATCH 23/42] drm/i915/xe2lpd: FBC is now supported on all pipes

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

FBC is no longer limited by pipe.

Bspec: 68881, 68904
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 4adb98afe6ff..6720ec8ee8a2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -20,6 +20,8 @@ struct intel_plane_state;
 enum intel_fbc_id {
 	INTEL_FBC_A,
 	INTEL_FBC_B,
+	INTEL_FBC_C,
+	INTEL_FBC_D,
 
 	I915_MAX_FBCS,
 };
-- 
2.40.1

[Intel-gfx] [PATCH 24/42] drm/i915/display: Remove FBC capability from fused off pipes

[Lucas De Marchi]

From: Clint Taylor <clinton.a.taylor@intel.com>

If a particular pipe is disabled by fuse also remove the FBC for that
pipe.

Bspec: 69464
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index b853cd0c704a..c4ff5a08c269 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -962,16 +962,19 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
 		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
 			display_runtime->pipe_mask &= ~BIT(PIPE_B);
 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
+			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
 		}
 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
 			display_runtime->pipe_mask &= ~BIT(PIPE_C);
 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
 		}
 
 		if (DISPLAY_VER(i915) >= 12 &&
 		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
 			display_runtime->pipe_mask &= ~BIT(PIPE_D);
 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
+			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
 		}
 
 		if (!display_runtime->pipe_mask)
-- 
2.40.1

[Intel-xe] [PATCH 24/42] drm/i915/display: Remove FBC capability from fused off pipes

[Lucas De Marchi]

From: Clint Taylor <clinton.a.taylor@intel.com>

If a particular pipe is disabled by fuse also remove the FBC for that
pipe.

Bspec: 69464
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index b853cd0c704a..c4ff5a08c269 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -962,16 +962,19 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
 		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
 			display_runtime->pipe_mask &= ~BIT(PIPE_B);
 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
+			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
 		}
 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
 			display_runtime->pipe_mask &= ~BIT(PIPE_C);
 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
 		}
 
 		if (DISPLAY_VER(i915) >= 12 &&
 		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
 			display_runtime->pipe_mask &= ~BIT(PIPE_D);
 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
+			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
 		}
 
 		if (!display_runtime->pipe_mask)
-- 
2.40.1

[Intel-xe] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

The location of aux channels registers for Xe2 display changed w.r.t.
the previous version.

BSpec: 69010
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 ++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 3fcf609a1444..1ab6964ee1c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -714,6 +714,44 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
 	}
 }
 
+static i915_reg_t xe2lpd_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+		return XE2LPD_DP_AUX_CH_CTL(aux_ch);
+	default:
+		MISSING_CASE(aux_ch);
+		return XE2LPD_DP_AUX_CH_CTL(AUX_CH_A);
+	}
+}
+
+static i915_reg_t xe2lpd_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+		return XE2LPD_DP_AUX_CH_DATA(aux_ch, index);
+	default:
+		MISSING_CASE(aux_ch);
+		return XE2LPD_DP_AUX_CH_DATA(AUX_CH_A, index);
+	}
+}
+
 void intel_dp_aux_fini(struct intel_dp *intel_dp)
 {
 	if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
@@ -731,7 +769,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
 	struct intel_encoder *encoder = &dig_port->base;
 	enum aux_ch aux_ch = dig_port->aux_ch;
 
-	if (DISPLAY_VER(dev_priv) >= 14) {
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		intel_dp->aux_ch_ctl_reg = xe2lpd_aux_ctl_reg;
+		intel_dp->aux_ch_data_reg = xe2lpd_aux_data_reg;
+	} else if (DISPLAY_VER(dev_priv) >= 14) {
 		intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
 		intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
 	} else if (DISPLAY_VER(dev_priv) >= 12) {
-- 
2.40.1

[Intel-gfx] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

The location of aux channels registers for Xe2 display changed w.r.t.
the previous version.

BSpec: 69010
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 ++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 3fcf609a1444..1ab6964ee1c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -714,6 +714,44 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
 	}
 }
 
+static i915_reg_t xe2lpd_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+		return XE2LPD_DP_AUX_CH_CTL(aux_ch);
+	default:
+		MISSING_CASE(aux_ch);
+		return XE2LPD_DP_AUX_CH_CTL(AUX_CH_A);
+	}
+}
+
+static i915_reg_t xe2lpd_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+		return XE2LPD_DP_AUX_CH_DATA(aux_ch, index);
+	default:
+		MISSING_CASE(aux_ch);
+		return XE2LPD_DP_AUX_CH_DATA(AUX_CH_A, index);
+	}
+}
+
 void intel_dp_aux_fini(struct intel_dp *intel_dp)
 {
 	if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
@@ -731,7 +769,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
 	struct intel_encoder *encoder = &dig_port->base;
 	enum aux_ch aux_ch = dig_port->aux_ch;
 
-	if (DISPLAY_VER(dev_priv) >= 14) {
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		intel_dp->aux_ch_ctl_reg = xe2lpd_aux_ctl_reg;
+		intel_dp->aux_ch_data_reg = xe2lpd_aux_data_reg;
+	} else if (DISPLAY_VER(dev_priv) >= 14) {
 		intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
 		intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
 	} else if (DISPLAY_VER(dev_priv) >= 12) {
-- 
2.40.1

[Intel-gfx] [PATCH 26/42] drm/i915/xe2lpd: Handle port AUX interrupts

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

Differently from previous version, Xe2_LPD groups all port AUX interrupt
bits into PICA interrupt registers.

BSpec: 68958, 69697
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h                  | 3 +++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 62ce55475554..bff4a76310c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 {
 	u32 mask;
 
-	if (DISPLAY_VER(dev_priv) >= 14)
+	if (DISPLAY_VER(dev_priv) >= 20)
+		return 0;
+	else if (DISPLAY_VER(dev_priv) >= 14)
 		return TGL_DE_PORT_AUX_DDIA |
 			TGL_DE_PORT_AUX_DDIB;
 	else if (DISPLAY_VER(dev_priv) >= 13)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index f95fa793fabb..f76b9deb64b4 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -514,6 +514,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
 	u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
 	u32 pin_mask = 0, long_mask = 0;
 
+	if (DISPLAY_VER(i915) >= 20)
+		trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
+
 	for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
 		u32 val;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84c5a76065a0..e31a985b02d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4520,6 +4520,9 @@
 #define  XELPDP_AUX_TC(hpd_pin)			REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
 #define  XELPDP_AUX_TC_MASK			REG_GENMASK(11, 8)
 
+#define  XE2LPD_AUX_DDI(hpd_pin)		REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
+#define  XE2LPD_AUX_DDI_MASK			REG_GENMASK(7, 6)
+
 #define  XELPDP_TBT_HOTPLUG(hpd_pin)		REG_BIT(_HPD_PIN_TC(hpd_pin))
 #define  XELPDP_TBT_HOTPLUG_MASK		REG_GENMASK(3, 0)
 
-- 
2.40.1

[Intel-xe] [PATCH 26/42] drm/i915/xe2lpd: Handle port AUX interrupts

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

Differently from previous version, Xe2_LPD groups all port AUX interrupt
bits into PICA interrupt registers.

BSpec: 68958, 69697
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h                  | 3 +++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 62ce55475554..bff4a76310c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 {
 	u32 mask;
 
-	if (DISPLAY_VER(dev_priv) >= 14)
+	if (DISPLAY_VER(dev_priv) >= 20)
+		return 0;
+	else if (DISPLAY_VER(dev_priv) >= 14)
 		return TGL_DE_PORT_AUX_DDIA |
 			TGL_DE_PORT_AUX_DDIB;
 	else if (DISPLAY_VER(dev_priv) >= 13)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index f95fa793fabb..f76b9deb64b4 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -514,6 +514,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
 	u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
 	u32 pin_mask = 0, long_mask = 0;
 
+	if (DISPLAY_VER(i915) >= 20)
+		trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
+
 	for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
 		u32 val;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84c5a76065a0..e31a985b02d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4520,6 +4520,9 @@
 #define  XELPDP_AUX_TC(hpd_pin)			REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
 #define  XELPDP_AUX_TC_MASK			REG_GENMASK(11, 8)
 
+#define  XE2LPD_AUX_DDI(hpd_pin)		REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
+#define  XE2LPD_AUX_DDI_MASK			REG_GENMASK(7, 6)
+
 #define  XELPDP_TBT_HOTPLUG(hpd_pin)		REG_BIT(_HPD_PIN_TC(hpd_pin))
 #define  XELPDP_TBT_HOTPLUG_MASK		REG_GENMASK(3, 0)
 
-- 
2.40.1

[Intel-gfx] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

[Lucas De Marchi]

From: Luca Coelho <luciano.coelho@intel.com>

Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.

We use the pin assignment to decide the maximum lane count.  So, to
support this change, add a new lnl_tc_port_get_max_lane_count() function
that reads from the TCSS_DDI_STATUS register and decides the maximum
lane count based on that.

BSpec: 69594
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h         |  1 +
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 3c94bbcb5497..37b0f8529b4f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
 	       DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
 }
 
+static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+	intel_wakeref_t wakeref;
+	u32 val, pin_assignment;
+
+	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+		val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
+
+	pin_assignment =
+		REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
+
+	switch (pin_assignment) {
+	default:
+		MISSING_CASE(pin_assignment);
+		fallthrough;
+	case DP_PIN_ASSIGNMENT_D:
+		return 2;
+	case DP_PIN_ASSIGNMENT_C:
+	case DP_PIN_ASSIGNMENT_E:
+		return 4;
+	}
+}
+
 static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -348,6 +373,9 @@ int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
 
 	assert_tc_cold_blocked(tc);
 
+	if (DISPLAY_VER(i915) >= 20)
+		return lnl_tc_port_get_max_lane_count(dig_port);
+
 	if (DISPLAY_VER(i915) >= 14)
 		return mtl_tc_port_get_max_lane_count(dig_port);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e31a985b02d5..fa85530afac3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6628,6 +6628,7 @@ enum skl_power_gate {
 #define TCSS_DDI_STATUS(tc)			_MMIO(_PICK_EVEN(tc, \
 								 _TCSS_DDI_STATUS_1, \
 								 _TCSS_DDI_STATUS_2))
+#define  TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK	REG_GENMASK(28, 25)
 #define  TCSS_DDI_STATUS_READY			REG_BIT(2)
 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT	REG_BIT(1)
 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
-- 
2.40.1

[Intel-xe] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

[Lucas De Marchi]

From: Luca Coelho <luciano.coelho@intel.com>

Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.

We use the pin assignment to decide the maximum lane count.  So, to
support this change, add a new lnl_tc_port_get_max_lane_count() function
that reads from the TCSS_DDI_STATUS register and decides the maximum
lane count based on that.

BSpec: 69594
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h         |  1 +
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 3c94bbcb5497..37b0f8529b4f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
 	       DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
 }
 
+static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+	intel_wakeref_t wakeref;
+	u32 val, pin_assignment;
+
+	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+		val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
+
+	pin_assignment =
+		REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
+
+	switch (pin_assignment) {
+	default:
+		MISSING_CASE(pin_assignment);
+		fallthrough;
+	case DP_PIN_ASSIGNMENT_D:
+		return 2;
+	case DP_PIN_ASSIGNMENT_C:
+	case DP_PIN_ASSIGNMENT_E:
+		return 4;
+	}
+}
+
 static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -348,6 +373,9 @@ int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
 
 	assert_tc_cold_blocked(tc);
 
+	if (DISPLAY_VER(i915) >= 20)
+		return lnl_tc_port_get_max_lane_count(dig_port);
+
 	if (DISPLAY_VER(i915) >= 14)
 		return mtl_tc_port_get_max_lane_count(dig_port);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e31a985b02d5..fa85530afac3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6628,6 +6628,7 @@ enum skl_power_gate {
 #define TCSS_DDI_STATUS(tc)			_MMIO(_PICK_EVEN(tc, \
 								 _TCSS_DDI_STATUS_1, \
 								 _TCSS_DDI_STATUS_2))
+#define  TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK	REG_GENMASK(28, 25)
 #define  TCSS_DDI_STATUS_READY			REG_BIT(2)
 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT	REG_BIT(1)
 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
-- 
2.40.1

[Intel-xe] [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd

[Lucas De Marchi]

From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>

Enable odd size and panning for planar yuv formats.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index fb13f0bb8c52..da6ee7f0675a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -986,6 +986,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 	if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
 		hsub = 2;
 		vsub = 2;
+	} else if (DISPLAY_VER(i915) >= 20 &&
+		intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+		/*
+		 * This allow NV12 and P0xx formats to have odd size and/or odd
+		 * source coordinates on DISPLAY_VER(i915) >= 20
+		 */
+		hsub = 1;
+		vsub = 1;
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
-- 
2.40.1

[Intel-gfx] [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd

[Lucas De Marchi]

From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>

Enable odd size and panning for planar yuv formats.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index fb13f0bb8c52..da6ee7f0675a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -986,6 +986,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 	if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
 		hsub = 2;
 		vsub = 2;
+	} else if (DISPLAY_VER(i915) >= 20 &&
+		intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+		/*
+		 * This allow NV12 and P0xx formats to have odd size and/or odd
+		 * source coordinates on DISPLAY_VER(i915) >= 20
+		 */
+		hsub = 1;
+		vsub = 1;
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
-- 
2.40.1

[Intel-gfx] [PATCH 29/42] drm/i915/xe2lpd: Add support for HPD

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
extra programming for hotplug inversion and DDI HPD filter duration is
not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
prefer to fork it into a new function for Xe2_LPD instead of adding a
platform check.

BSpec: 68970
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../gpu/drm/i915/display/intel_hotplug_irq.c  | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index f76b9deb64b4..74aea0d8d9ae 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -163,7 +163,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 	    (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
 		return;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
+		hpd->pch_hpd = hpd_mtp;
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		hpd->pch_hpd = hpd_sde_dg1;
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
 		hpd->pch_hpd = hpd_mtp;
@@ -1061,6 +1063,19 @@ static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
 	mtp_tc_hpd_detection_setup(i915);
 }
 
+static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
+{
+	u32 hotplug_irqs, enabled_irqs;
+
+	enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
+	hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
+
+	ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
+
+	mtp_ddi_hpd_detection_setup(i915);
+	mtp_tc_hpd_detection_setup(i915);
+}
+
 static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
 {
 	return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
@@ -1120,6 +1135,8 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
 
 	xelpdp_pica_hpd_detection_setup(i915);
 
+	if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
+		xe2lpd_sde_hpd_irq_setup(i915);
 	if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
 		mtp_hpd_irq_setup(i915);
 }
-- 
2.40.1

[Intel-xe] [PATCH 29/42] drm/i915/xe2lpd: Add support for HPD

[Lucas De Marchi]

From: Gustavo Sousa <gustavo.sousa@intel.com>

Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
extra programming for hotplug inversion and DDI HPD filter duration is
not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
prefer to fork it into a new function for Xe2_LPD instead of adding a
platform check.

BSpec: 68970
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../gpu/drm/i915/display/intel_hotplug_irq.c  | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index f76b9deb64b4..74aea0d8d9ae 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -163,7 +163,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 	    (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
 		return;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
+		hpd->pch_hpd = hpd_mtp;
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		hpd->pch_hpd = hpd_sde_dg1;
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
 		hpd->pch_hpd = hpd_mtp;
@@ -1061,6 +1063,19 @@ static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
 	mtp_tc_hpd_detection_setup(i915);
 }
 
+static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
+{
+	u32 hotplug_irqs, enabled_irqs;
+
+	enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
+	hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
+
+	ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
+
+	mtp_ddi_hpd_detection_setup(i915);
+	mtp_tc_hpd_detection_setup(i915);
+}
+
 static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
 {
 	return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
@@ -1120,6 +1135,8 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
 
 	xelpdp_pica_hpd_detection_setup(i915);
 
+	if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
+		xe2lpd_sde_hpd_irq_setup(i915);
 	if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
 		mtp_hpd_irq_setup(i915);
 }
-- 
2.40.1

[Intel-gfx] [PATCH 30/42] drm/i915/xe2lpd: Extend Wa_15010685871

[Lucas De Marchi]

Xe2_LPD also needs workaround 15010685871.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..fdd8d04fe12c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1839,9 +1839,9 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
 
 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
 {
-	return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
-		dev_priv->display.cdclk.hw.vco > 0 &&
-		HAS_CDCLK_SQUASH(dev_priv));
+	return (IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv) ||
+		DISPLAY_VER(dev_priv) == 20) &&
+		dev_priv->display.cdclk.hw.vco > 0 && HAS_CDCLK_SQUASH(dev_priv);
 }
 
 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
-- 
2.40.1

[Intel-xe] [PATCH 30/42] drm/i915/xe2lpd: Extend Wa_15010685871

[Lucas De Marchi]

Xe2_LPD also needs workaround 15010685871.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..fdd8d04fe12c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1839,9 +1839,9 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
 
 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
 {
-	return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
-		dev_priv->display.cdclk.hw.vco > 0 &&
-		HAS_CDCLK_SQUASH(dev_priv));
+	return (IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv) ||
+		DISPLAY_VER(dev_priv) == 20) &&
+		dev_priv->display.cdclk.hw.vco > 0 && HAS_CDCLK_SQUASH(dev_priv);
 }
 
 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
-- 
2.40.1

[Intel-gfx] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

[Lucas De Marchi]

LNL's south display uses the same table as MTP. Check for LNL's fake PCH
to make it consistent with the other checks.

The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
other cases, uses the same as the previous platform.

Bspec: 68971, 20124
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 097c1f23d3ae..3772b91e155c 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
 	const u8 *ddc_pin_map;
 	int i, n_entries;
 
-	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
+	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {
 		ddc_pin_map = adlp_ddc_pin_map;
 		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
 	} else if (IS_ALDERLAKE_S(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index e95ddb580ef6..801fabbccf7e 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
 	const struct gmbus_pin *pins;
 	size_t size;
 
-	if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
+	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
+		pins = gmbus_pins_mtp;
+		size = ARRAY_SIZE(gmbus_pins_mtp);
+	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
 		pins = gmbus_pins_dg2;
 		size = ARRAY_SIZE(gmbus_pins_dg2);
 	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
-- 
2.40.1

[Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

[Lucas De Marchi]

LNL's south display uses the same table as MTP. Check for LNL's fake PCH
to make it consistent with the other checks.

The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
other cases, uses the same as the previous platform.

Bspec: 68971, 20124
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 097c1f23d3ae..3772b91e155c 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
 	const u8 *ddc_pin_map;
 	int i, n_entries;
 
-	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
+	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {
 		ddc_pin_map = adlp_ddc_pin_map;
 		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
 	} else if (IS_ALDERLAKE_S(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index e95ddb580ef6..801fabbccf7e 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
 	const struct gmbus_pin *pins;
 	size_t size;
 
-	if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
+	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
+		pins = gmbus_pins_mtp;
+		size = ARRAY_SIZE(gmbus_pins_mtp);
+	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
 		pins = gmbus_pins_dg2;
 		size = ARRAY_SIZE(gmbus_pins_dg2);
 	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
-- 
2.40.1

[Intel-gfx] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

In Lunar Lake we now separate MDCLK from CDLCK, which used to be before
always 2 times CDCLK.  Now we might afford lower CDCLK, while having
higher memory clock, so improving bandwidth and power consumption at the
same time.  This is prep work required to enable that.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 30 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h |  2 +-
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index fdd8d04fe12c..3e566f45996d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1223,6 +1223,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 
 struct intel_cdclk_vals {
 	u32 cdclk;
+	u32 mdclk;
 	u16 refclk;
 	u16 waveform;
 	u8 divider;	/* CD2X divider * 2 */
@@ -1524,6 +1525,8 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 			  struct intel_cdclk_config *cdclk_config)
 {
+	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
+	int i, ratio, tbl_waveform = 0;
 	u32 squash_ctl = 0;
 	u32 divider;
 	int div;
@@ -1574,10 +1577,36 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 
 		cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
 							cdclk_config->vco, size * div);
+		tbl_waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
 	} else {
 		cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
 	}
 
+	ratio = cdclk_config->vco / cdclk_config->ref;
+
+	for (i = 0; table[i].refclk; i++) {
+		if (table[i].refclk != cdclk_config->ref)
+			continue;
+
+		if (table[i].divider != div)
+			continue;
+
+		if (table[i].waveform != tbl_waveform)
+			continue;
+
+		if (table[i].ratio != ratio)
+			continue;
+
+		/*
+		 * Supported from LunarLake HW onwards, however considering that
+		 * besides this the whole procedure is the same, we keep this
+		 * for all the platforms.
+		 */
+		cdclk_config->mdclk = table[i].mdclk;
+
+		break;
+	}
+
  out:
 	/*
 	 * Can't read this out :( Let's assume it's
@@ -2191,6 +2220,7 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
 			       const struct intel_cdclk_config *b)
 {
 	return a->cdclk != b->cdclk ||
+		a->mdclk != b->mdclk ||
 		a->vco != b->vco ||
 		a->ref != b->ref;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 48fd7d39e0cd..3e7eabd4d7b6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -16,7 +16,7 @@ struct intel_atomic_state;
 struct intel_crtc_state;
 
 struct intel_cdclk_config {
-	unsigned int cdclk, vco, ref, bypass;
+	unsigned int cdclk, mdclk, vco, ref, bypass;
 	u8 voltage_level;
 };
 
-- 
2.40.1

[Intel-xe] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

In Lunar Lake we now separate MDCLK from CDLCK, which used to be before
always 2 times CDCLK.  Now we might afford lower CDCLK, while having
higher memory clock, so improving bandwidth and power consumption at the
same time.  This is prep work required to enable that.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 30 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h |  2 +-
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index fdd8d04fe12c..3e566f45996d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1223,6 +1223,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 
 struct intel_cdclk_vals {
 	u32 cdclk;
+	u32 mdclk;
 	u16 refclk;
 	u16 waveform;
 	u8 divider;	/* CD2X divider * 2 */
@@ -1524,6 +1525,8 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 			  struct intel_cdclk_config *cdclk_config)
 {
+	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
+	int i, ratio, tbl_waveform = 0;
 	u32 squash_ctl = 0;
 	u32 divider;
 	int div;
@@ -1574,10 +1577,36 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 
 		cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
 							cdclk_config->vco, size * div);
+		tbl_waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
 	} else {
 		cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
 	}
 
+	ratio = cdclk_config->vco / cdclk_config->ref;
+
+	for (i = 0; table[i].refclk; i++) {
+		if (table[i].refclk != cdclk_config->ref)
+			continue;
+
+		if (table[i].divider != div)
+			continue;
+
+		if (table[i].waveform != tbl_waveform)
+			continue;
+
+		if (table[i].ratio != ratio)
+			continue;
+
+		/*
+		 * Supported from LunarLake HW onwards, however considering that
+		 * besides this the whole procedure is the same, we keep this
+		 * for all the platforms.
+		 */
+		cdclk_config->mdclk = table[i].mdclk;
+
+		break;
+	}
+
  out:
 	/*
 	 * Can't read this out :( Let's assume it's
@@ -2191,6 +2220,7 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
 			       const struct intel_cdclk_config *b)
 {
 	return a->cdclk != b->cdclk ||
+		a->mdclk != b->mdclk ||
 		a->vco != b->vco ||
 		a->ref != b->ref;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 48fd7d39e0cd..3e7eabd4d7b6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -16,7 +16,7 @@ struct intel_atomic_state;
 struct intel_crtc_state;
 
 struct intel_cdclk_config {
-	unsigned int cdclk, vco, ref, bypass;
+	unsigned int cdclk, mdclk, vco, ref, bypass;
 	u8 voltage_level;
 };
 
-- 
2.40.1

[Intel-gfx] [PATCH 33/42] drm/i915/lnl: Add CDCLK table

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Add a new Lunar Lake CDCLK table from BSpec and also a helper function
in order to be able to find lowest possible CDCLK, which has required
MDCLK for the correspodent pixel rate.

Bspec: 68861
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 52 +++++++++++++++++++++-
 1 file changed, 50 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3e566f45996d..ed45a2cf5c9a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1381,6 +1381,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = {
 	{}
 };
 
+static const struct intel_cdclk_vals lnl_cdclk_table[] = {
+	{ .refclk = 38400, .cdclk = 153600, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
+	{ .refclk = 38400, .cdclk = 172800, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+	{ .refclk = 38400, .cdclk = 192000, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+	{ .refclk = 38400, .cdclk = 211200, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
+	{ .refclk = 38400, .cdclk = 230400, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
+	{ .refclk = 38400, .cdclk = 249600, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xf7de },
+	{ .refclk = 38400, .cdclk = 268800, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 288000, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 307200, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+	{ .refclk = 38400, .cdclk = 330000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
+	{ .refclk = 38400, .cdclk = 360000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
+	{ .refclk = 38400, .cdclk = 390000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
+	{ .refclk = 38400, .cdclk = 420000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 450000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 480000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+	{ .refclk = 38400, .cdclk = 487200, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 522000, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 556800, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+	{ .refclk = 38400, .cdclk = 571200, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 612000, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 652800, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+	{}
+};
+
 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 {
 	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -2531,12 +2556,32 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 	}
 }
 
+static int
+cdclk_match_by_refclk_mdclk(struct drm_i915_private *i915, int pixel_rate)
+{
+	const struct intel_cdclk_vals *table = i915->display.cdclk.table;
+	int i;
+
+	for (i = 0; table[i].refclk; i++)
+		if (table[i].refclk == i915->display.cdclk.hw.ref &&
+		    table[i].mdclk >= pixel_rate)
+			return table[i].cdclk;
+
+	drm_WARN(&i915->drm, 1,
+		 "Cannot satisfy pixel rate %d with refclk %u\n",
+		 pixel_rate, i915->display.cdclk.hw.ref);
+
+	return 0;
+}
+
 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int pixel_rate = crtc_state->pixel_rate;
 
-	if (DISPLAY_VER(dev_priv) >= 10)
+	if (DISPLAY_VER(dev_priv) >= 20)
+		return cdclk_match_by_refclk_mdclk(dev_priv, pixel_rate);
+	else if (DISPLAY_VER(dev_priv) >= 10)
 		return DIV_ROUND_UP(pixel_rate, 2);
 	else if (DISPLAY_VER(dev_priv) == 9 ||
 		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
@@ -3581,7 +3626,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_METEORLAKE(dev_priv)) {
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+		dev_priv->display.cdclk.table = lnl_cdclk_table;
+	} else if (IS_METEORLAKE(dev_priv)) {
 		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
 		dev_priv->display.cdclk.table = mtl_cdclk_table;
 	} else if (IS_DG2(dev_priv)) {
-- 
2.40.1

[Intel-xe] [PATCH 33/42] drm/i915/lnl: Add CDCLK table

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Add a new Lunar Lake CDCLK table from BSpec and also a helper function
in order to be able to find lowest possible CDCLK, which has required
MDCLK for the correspodent pixel rate.

Bspec: 68861
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 52 +++++++++++++++++++++-
 1 file changed, 50 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3e566f45996d..ed45a2cf5c9a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1381,6 +1381,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = {
 	{}
 };
 
+static const struct intel_cdclk_vals lnl_cdclk_table[] = {
+	{ .refclk = 38400, .cdclk = 153600, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
+	{ .refclk = 38400, .cdclk = 172800, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+	{ .refclk = 38400, .cdclk = 192000, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+	{ .refclk = 38400, .cdclk = 211200, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
+	{ .refclk = 38400, .cdclk = 230400, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
+	{ .refclk = 38400, .cdclk = 249600, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xf7de },
+	{ .refclk = 38400, .cdclk = 268800, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 288000, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 307200, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+	{ .refclk = 38400, .cdclk = 330000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
+	{ .refclk = 38400, .cdclk = 360000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
+	{ .refclk = 38400, .cdclk = 390000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
+	{ .refclk = 38400, .cdclk = 420000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 450000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 480000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+	{ .refclk = 38400, .cdclk = 487200, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 522000, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 556800, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+	{ .refclk = 38400, .cdclk = 571200, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 612000, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 652800, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+	{}
+};
+
 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 {
 	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -2531,12 +2556,32 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 	}
 }
 
+static int
+cdclk_match_by_refclk_mdclk(struct drm_i915_private *i915, int pixel_rate)
+{
+	const struct intel_cdclk_vals *table = i915->display.cdclk.table;
+	int i;
+
+	for (i = 0; table[i].refclk; i++)
+		if (table[i].refclk == i915->display.cdclk.hw.ref &&
+		    table[i].mdclk >= pixel_rate)
+			return table[i].cdclk;
+
+	drm_WARN(&i915->drm, 1,
+		 "Cannot satisfy pixel rate %d with refclk %u\n",
+		 pixel_rate, i915->display.cdclk.hw.ref);
+
+	return 0;
+}
+
 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int pixel_rate = crtc_state->pixel_rate;
 
-	if (DISPLAY_VER(dev_priv) >= 10)
+	if (DISPLAY_VER(dev_priv) >= 20)
+		return cdclk_match_by_refclk_mdclk(dev_priv, pixel_rate);
+	else if (DISPLAY_VER(dev_priv) >= 10)
 		return DIV_ROUND_UP(pixel_rate, 2);
 	else if (DISPLAY_VER(dev_priv) == 9 ||
 		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
@@ -3581,7 +3626,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_METEORLAKE(dev_priv)) {
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+		dev_priv->display.cdclk.table = lnl_cdclk_table;
+	} else if (IS_METEORLAKE(dev_priv)) {
 		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
 		dev_priv->display.cdclk.table = mtl_cdclk_table;
 	} else if (IS_DG2(dev_priv)) {
-- 
2.40.1

[Intel-xe] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Introduce correspondent definitions and for choosing between CD2X CDCLK
and PLL CDCLK as a source.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h            |  3 +++
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ed45a2cf5c9a..04937aaabcee 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1932,8 +1932,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		dg2_cdclk_squash_program(dev_priv, waveform);
 
 	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
-		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-		skl_cdclk_decimal(cdclk);
+		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
 
 	/*
 	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -1942,6 +1941,17 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
 	    cdclk >= 500000)
 		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+
+	if (DISPLAY_VER(dev_priv) >= 20)
+		/*
+		 * Using CDCLK through PLL seems to be always better option when
+		 * its supported, both in terms of performance and power
+		 * consumption.
+		 */
+		val |= CDCLK_SOURCE_SEL_CDCLK_PLL;
+	else
+		val |= skl_cdclk_decimal(cdclk);
+
 	intel_de_write(dev_priv, CDCLK_CTL, val);
 
 	if (pipe != INVALID_PIPE)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fa85530afac3..d5850761a75a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5933,6 +5933,9 @@ enum skl_power_gate {
 #define  CDCLK_FREQ_540		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
 #define  CDCLK_FREQ_337_308		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
 #define  CDCLK_FREQ_675_617		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
+#define  CDCLK_SOURCE_SEL_MASK		REG_BIT(25)
+#define  CDCLK_SOURCE_SEL_CD2X		REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 0)
+#define  CDCLK_SOURCE_SEL_CDCLK_PLL	REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 1)
 #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	REG_GENMASK(23, 22)
 #define  BXT_CDCLK_CD2X_DIV_SEL_1	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
 #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
-- 
2.40.1

[Intel-gfx] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Introduce correspondent definitions and for choosing between CD2X CDCLK
and PLL CDCLK as a source.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h            |  3 +++
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ed45a2cf5c9a..04937aaabcee 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1932,8 +1932,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		dg2_cdclk_squash_program(dev_priv, waveform);
 
 	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
-		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-		skl_cdclk_decimal(cdclk);
+		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
 
 	/*
 	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -1942,6 +1941,17 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
 	    cdclk >= 500000)
 		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+
+	if (DISPLAY_VER(dev_priv) >= 20)
+		/*
+		 * Using CDCLK through PLL seems to be always better option when
+		 * its supported, both in terms of performance and power
+		 * consumption.
+		 */
+		val |= CDCLK_SOURCE_SEL_CDCLK_PLL;
+	else
+		val |= skl_cdclk_decimal(cdclk);
+
 	intel_de_write(dev_priv, CDCLK_CTL, val);
 
 	if (pipe != INVALID_PIPE)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fa85530afac3..d5850761a75a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5933,6 +5933,9 @@ enum skl_power_gate {
 #define  CDCLK_FREQ_540		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
 #define  CDCLK_FREQ_337_308		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
 #define  CDCLK_FREQ_675_617		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
+#define  CDCLK_SOURCE_SEL_MASK		REG_BIT(25)
+#define  CDCLK_SOURCE_SEL_CD2X		REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 0)
+#define  CDCLK_SOURCE_SEL_CDCLK_PLL	REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 1)
 #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	REG_GENMASK(23, 22)
 #define  BXT_CDCLK_CD2X_DIV_SEL_1	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
 #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
-- 
2.40.1

[Intel-xe] [PATCH 35/42] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
change.

Previsouly DBuf state and CDCLK were not anyhow coupled together.  Now
at compute stage when we know which CDCLK/MDCLK we are going to use, we
need to update the DBuf state with that ratio, being properly encoded,
so that it gets written to those registers, once DBuf state is being
update. The criteria for updating DBuf state is also a CDCLK/MDCLK ratio
change now.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 16 +++++++++
 drivers/gpu/drm/i915/display/skl_watermark.c  | 35 ++++++++++++++++---
 drivers/gpu/drm/i915/display/skl_watermark.h  |  1 +
 .../gpu/drm/i915/display/skl_watermark_regs.h |  2 ++
 4 files changed, 50 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 04937aaabcee..aa1000db3cb9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -37,6 +37,7 @@
 #include "intel_pci_config.h"
 #include "intel_pcode.h"
 #include "intel_psr.h"
+#include "skl_watermark.h"
 #include "vlv_sideband.h"
 
 /**
@@ -1827,6 +1828,15 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
 	return vco == ~0;
 }
 
+static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+				 const struct intel_cdclk_config *cdclk_config)
+{
+	if (DISPLAY_VER(i915) >= 20)
+		return cdclk_config->mdclk / cdclk_config->cdclk - 1;
+	else
+		return 1;
+}
+
 static int cdclk_squash_divider(u16 waveform)
 {
 	return hweight16(waveform ?: 0xffff);
@@ -2727,6 +2737,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 	struct intel_crtc_state *crtc_state;
 	int min_cdclk, i;
 	enum pipe pipe;
+	struct intel_dbuf_state *dbuf_state;
 
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
 		int ret;
@@ -2760,6 +2771,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 		}
 	}
 
+	dbuf_state = intel_atomic_get_new_dbuf_state(state);
+	if (dbuf_state)
+		dbuf_state->mdclk_cdclk_ratio =
+			get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
+
 	min_cdclk = max(cdclk_state->force_min_cdclk,
 			cdclk_state->bw_min_cdclk);
 	for_each_pipe(dev_priv, pipe)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 64a122d3c9c0..79454b4d99e3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3472,6 +3472,23 @@ int intel_dbuf_init(struct drm_i915_private *i915)
 	return 0;
 }
 
+static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+				      int mdclk_cdclk_ratio,
+				      int mbus_joined)
+{
+	if (DISPLAY_VER(i915) >= 20) {
+		if (mbus_joined)
+			return (mdclk_cdclk_ratio << 1) + 1;
+		else
+			return mdclk_cdclk_ratio;
+	}
+
+	if (mbus_joined)
+		return 3;
+
+	return 1;
+}
+
 /*
  * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
  * update the request state of all DBUS slices.
@@ -3483,10 +3500,16 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
 	enum dbuf_slice slice;
 	const struct intel_dbuf_state *dbuf_state =
 		intel_atomic_get_new_dbuf_state(state);
+	int tracker_state_service;
 
 	if (!HAS_MBUS_JOINING(i915))
 		return;
 
+	tracker_state_service =
+		get_mbus_mdclk_cdclk_ratio(i915,
+					   dbuf_state->mdclk_cdclk_ratio,
+					   dbuf_state->joined_mbus);
+
 	/*
 	 * TODO: Implement vblank synchronized MBUS joining changes.
 	 * Must be properly coordinated with dbuf reprogramming.
@@ -3494,13 +3517,15 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
 	if (dbuf_state->joined_mbus) {
 		mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
 			MBUS_JOIN_PIPE_SELECT_NONE;
-		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
 	} else {
 		mbus_ctl = MBUS_HASHING_MODE_2x2 |
 			MBUS_JOIN_PIPE_SELECT_NONE;
-		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
 	}
 
+	dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(tracker_state_service);
+
+	mbus_ctl |= MBUS_TRANS_THROTTLE_MIN_SELECT(dbuf_state->mdclk_cdclk_ratio);
+
 	intel_de_rmw(i915, MBUS_CTL,
 		     MBUS_HASHING_MODE_MASK | MBUS_JOIN |
 		     MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
@@ -3521,7 +3546,8 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
 
 	if (!new_dbuf_state ||
 	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
-	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+	     new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
 		return;
 
 	WARN_ON(!new_dbuf_state->base.changed);
@@ -3542,7 +3568,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 
 	if (!new_dbuf_state ||
 	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
-	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+	     new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
 		return;
 
 	WARN_ON(!new_dbuf_state->base.changed);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index f91a3d4ddc07..54db5c7d517e 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -56,6 +56,7 @@ struct intel_dbuf_state {
 	u8 slices[I915_MAX_PIPES];
 	u8 enabled_slices;
 	u8 active_pipes;
+	u8 mdclk_cdclk_ratio;
 	bool joined_mbus;
 };
 
diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
index 628c5920ad49..4c820f1d351d 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
@@ -38,6 +38,8 @@
 #define MBUS_HASHING_MODE_2x2		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
 #define MBUS_HASHING_MODE_1x4		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
 #define MBUS_JOIN_PIPE_SELECT_MASK	REG_GENMASK(28, 26)
+#define MBUS_TRANS_THROTTLE_MIN_MASK	REG_GENMASK(15, 13)
+#define MBUS_TRANS_THROTTLE_MIN_SELECT(ratio)	REG_FIELD_PREP(MBUS_TRANS_THROTTLE_MIN_MASK, ratio)
 #define MBUS_JOIN_PIPE_SELECT(pipe)	REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
 #define MBUS_JOIN_PIPE_SELECT_NONE	MBUS_JOIN_PIPE_SELECT(7)
 
-- 
2.40.1

[Intel-gfx] [PATCH 35/42] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
change.

Previsouly DBuf state and CDCLK were not anyhow coupled together.  Now
at compute stage when we know which CDCLK/MDCLK we are going to use, we
need to update the DBuf state with that ratio, being properly encoded,
so that it gets written to those registers, once DBuf state is being
update. The criteria for updating DBuf state is also a CDCLK/MDCLK ratio
change now.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 16 +++++++++
 drivers/gpu/drm/i915/display/skl_watermark.c  | 35 ++++++++++++++++---
 drivers/gpu/drm/i915/display/skl_watermark.h  |  1 +
 .../gpu/drm/i915/display/skl_watermark_regs.h |  2 ++
 4 files changed, 50 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 04937aaabcee..aa1000db3cb9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -37,6 +37,7 @@
 #include "intel_pci_config.h"
 #include "intel_pcode.h"
 #include "intel_psr.h"
+#include "skl_watermark.h"
 #include "vlv_sideband.h"
 
 /**
@@ -1827,6 +1828,15 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
 	return vco == ~0;
 }
 
+static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+				 const struct intel_cdclk_config *cdclk_config)
+{
+	if (DISPLAY_VER(i915) >= 20)
+		return cdclk_config->mdclk / cdclk_config->cdclk - 1;
+	else
+		return 1;
+}
+
 static int cdclk_squash_divider(u16 waveform)
 {
 	return hweight16(waveform ?: 0xffff);
@@ -2727,6 +2737,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 	struct intel_crtc_state *crtc_state;
 	int min_cdclk, i;
 	enum pipe pipe;
+	struct intel_dbuf_state *dbuf_state;
 
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
 		int ret;
@@ -2760,6 +2771,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 		}
 	}
 
+	dbuf_state = intel_atomic_get_new_dbuf_state(state);
+	if (dbuf_state)
+		dbuf_state->mdclk_cdclk_ratio =
+			get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
+
 	min_cdclk = max(cdclk_state->force_min_cdclk,
 			cdclk_state->bw_min_cdclk);
 	for_each_pipe(dev_priv, pipe)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 64a122d3c9c0..79454b4d99e3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3472,6 +3472,23 @@ int intel_dbuf_init(struct drm_i915_private *i915)
 	return 0;
 }
 
+static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+				      int mdclk_cdclk_ratio,
+				      int mbus_joined)
+{
+	if (DISPLAY_VER(i915) >= 20) {
+		if (mbus_joined)
+			return (mdclk_cdclk_ratio << 1) + 1;
+		else
+			return mdclk_cdclk_ratio;
+	}
+
+	if (mbus_joined)
+		return 3;
+
+	return 1;
+}
+
 /*
  * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
  * update the request state of all DBUS slices.
@@ -3483,10 +3500,16 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
 	enum dbuf_slice slice;
 	const struct intel_dbuf_state *dbuf_state =
 		intel_atomic_get_new_dbuf_state(state);
+	int tracker_state_service;
 
 	if (!HAS_MBUS_JOINING(i915))
 		return;
 
+	tracker_state_service =
+		get_mbus_mdclk_cdclk_ratio(i915,
+					   dbuf_state->mdclk_cdclk_ratio,
+					   dbuf_state->joined_mbus);
+
 	/*
 	 * TODO: Implement vblank synchronized MBUS joining changes.
 	 * Must be properly coordinated with dbuf reprogramming.
@@ -3494,13 +3517,15 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
 	if (dbuf_state->joined_mbus) {
 		mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
 			MBUS_JOIN_PIPE_SELECT_NONE;
-		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
 	} else {
 		mbus_ctl = MBUS_HASHING_MODE_2x2 |
 			MBUS_JOIN_PIPE_SELECT_NONE;
-		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
 	}
 
+	dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(tracker_state_service);
+
+	mbus_ctl |= MBUS_TRANS_THROTTLE_MIN_SELECT(dbuf_state->mdclk_cdclk_ratio);
+
 	intel_de_rmw(i915, MBUS_CTL,
 		     MBUS_HASHING_MODE_MASK | MBUS_JOIN |
 		     MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
@@ -3521,7 +3546,8 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
 
 	if (!new_dbuf_state ||
 	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
-	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+	     new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
 		return;
 
 	WARN_ON(!new_dbuf_state->base.changed);
@@ -3542,7 +3568,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 
 	if (!new_dbuf_state ||
 	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
-	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+	     new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
 		return;
 
 	WARN_ON(!new_dbuf_state->base.changed);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index f91a3d4ddc07..54db5c7d517e 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -56,6 +56,7 @@ struct intel_dbuf_state {
 	u8 slices[I915_MAX_PIPES];
 	u8 enabled_slices;
 	u8 active_pipes;
+	u8 mdclk_cdclk_ratio;
 	bool joined_mbus;
 };
 
diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
index 628c5920ad49..4c820f1d351d 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
@@ -38,6 +38,8 @@
 #define MBUS_HASHING_MODE_2x2		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
 #define MBUS_HASHING_MODE_1x4		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
 #define MBUS_JOIN_PIPE_SELECT_MASK	REG_GENMASK(28, 26)
+#define MBUS_TRANS_THROTTLE_MIN_MASK	REG_GENMASK(15, 13)
+#define MBUS_TRANS_THROTTLE_MIN_SELECT(ratio)	REG_FIELD_PREP(MBUS_TRANS_THROTTLE_MIN_MASK, ratio)
 #define MBUS_JOIN_PIPE_SELECT(pipe)	REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
 #define MBUS_JOIN_PIPE_SELECT_NONE	MBUS_JOIN_PIPE_SELECT(7)
 
-- 
2.40.1

[Intel-gfx] [PATCH 36/42] drm/i915/lnl: Add support for CDCLK initialization sequence

[Lucas De Marchi]

From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>

Add CDCLK initialization sequence changes and CDCLK set frequency
sequence for LNL platform.

CDCLK frequency change sequence is different for LNL compared to MTL
when a change in mdclk/cdclk ratio is observed. Below are changes to be
made:

1. In MBUS_CTL register translation Throttle Min value.
2. In DBUF_CTL_S* register Min Tracker State Service value.

BSpec: 68846, 68864
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 58 ++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h            |  2 +
 2 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index aa1000db3cb9..4d8b960389ec 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -38,6 +38,7 @@
 #include "intel_pcode.h"
 #include "intel_psr.h"
 #include "skl_watermark.h"
+#include "skl_watermark_regs.h"
 #include "vlv_sideband.h"
 
 /**
@@ -1727,7 +1728,12 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
 
 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
-	if (DISPLAY_VER(dev_priv) >= 12) {
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		if (pipe == INVALID_PIPE)
+			return LNL_CDCLK_CD2X_PIPE_NONE;
+		else
+			return LNL_CDCLK_CD2X_PIPE(pipe);
+	} else if (DISPLAY_VER(dev_priv) >= 12) {
 		if (pipe == INVALID_PIPE)
 			return TGL_CDCLK_CD2X_PIPE_NONE;
 		else
@@ -1837,6 +1843,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
 		return 1;
 }
 
+static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
+				    const struct intel_cdclk_config *cdclk_config)
+{
+	int min_throttle_val;
+	int min_tracker_state;
+	enum dbuf_slice slice;
+	int mdclk_cdclk_div_ratio;
+	int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
+
+	mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
+
+	min_throttle_val = MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
+
+	intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK, min_throttle_val);
+
+	if (mbus_join)
+		mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
+
+	min_tracker_state = DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
+
+	for_each_dbuf_slice(i915, slice)
+		intel_de_rmw(i915, DBUF_CTL_S(slice),
+			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+			     min_tracker_state);
+}
+
+static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
+				     const struct intel_cdclk_config *cdclk_config,
+				     u16 waveform)
+{
+	if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
+		/* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
+		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+
+	dg2_cdclk_squash_program(i915, waveform);
+
+	if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
+		/* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
+		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+}
+
 static int cdclk_squash_divider(u16 waveform)
 {
 	return hweight16(waveform ?: 0xffff);
@@ -1938,8 +1985,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	else
 		clock = cdclk;
 
-	if (HAS_CDCLK_SQUASH(dev_priv))
-		dg2_cdclk_squash_program(dev_priv, waveform);
+	if (HAS_CDCLK_SQUASH(dev_priv)) {
+		if (DISPLAY_VER(dev_priv) >= 20)
+			lnl_cdclk_squash_program(dev_priv, cdclk_config,
+						 waveform);
+		else
+			dg2_cdclk_squash_program(dev_priv, waveform);
+	}
 
 	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
 		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d5850761a75a..c9639f0f4f49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5944,6 +5944,8 @@ enum skl_power_gate {
 #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
 #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
 #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
+#define  LNL_CDCLK_CD2X_PIPE(pipe)	((pipe) << 19)
+#define  LNL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
 #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
 #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
 #define  TGL_CDCLK_CD2X_PIPE(pipe)	BXT_CDCLK_CD2X_PIPE(pipe)
-- 
2.40.1

[Intel-xe] [PATCH 36/42] drm/i915/lnl: Add support for CDCLK initialization sequence

[Lucas De Marchi]

From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>

Add CDCLK initialization sequence changes and CDCLK set frequency
sequence for LNL platform.

CDCLK frequency change sequence is different for LNL compared to MTL
when a change in mdclk/cdclk ratio is observed. Below are changes to be
made:

1. In MBUS_CTL register translation Throttle Min value.
2. In DBUF_CTL_S* register Min Tracker State Service value.

BSpec: 68846, 68864
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 58 ++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h            |  2 +
 2 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index aa1000db3cb9..4d8b960389ec 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -38,6 +38,7 @@
 #include "intel_pcode.h"
 #include "intel_psr.h"
 #include "skl_watermark.h"
+#include "skl_watermark_regs.h"
 #include "vlv_sideband.h"
 
 /**
@@ -1727,7 +1728,12 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
 
 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
-	if (DISPLAY_VER(dev_priv) >= 12) {
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		if (pipe == INVALID_PIPE)
+			return LNL_CDCLK_CD2X_PIPE_NONE;
+		else
+			return LNL_CDCLK_CD2X_PIPE(pipe);
+	} else if (DISPLAY_VER(dev_priv) >= 12) {
 		if (pipe == INVALID_PIPE)
 			return TGL_CDCLK_CD2X_PIPE_NONE;
 		else
@@ -1837,6 +1843,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
 		return 1;
 }
 
+static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
+				    const struct intel_cdclk_config *cdclk_config)
+{
+	int min_throttle_val;
+	int min_tracker_state;
+	enum dbuf_slice slice;
+	int mdclk_cdclk_div_ratio;
+	int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
+
+	mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
+
+	min_throttle_val = MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
+
+	intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK, min_throttle_val);
+
+	if (mbus_join)
+		mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
+
+	min_tracker_state = DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
+
+	for_each_dbuf_slice(i915, slice)
+		intel_de_rmw(i915, DBUF_CTL_S(slice),
+			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+			     min_tracker_state);
+}
+
+static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
+				     const struct intel_cdclk_config *cdclk_config,
+				     u16 waveform)
+{
+	if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
+		/* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
+		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+
+	dg2_cdclk_squash_program(i915, waveform);
+
+	if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
+		/* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
+		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+}
+
 static int cdclk_squash_divider(u16 waveform)
 {
 	return hweight16(waveform ?: 0xffff);
@@ -1938,8 +1985,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	else
 		clock = cdclk;
 
-	if (HAS_CDCLK_SQUASH(dev_priv))
-		dg2_cdclk_squash_program(dev_priv, waveform);
+	if (HAS_CDCLK_SQUASH(dev_priv)) {
+		if (DISPLAY_VER(dev_priv) >= 20)
+			lnl_cdclk_squash_program(dev_priv, cdclk_config,
+						 waveform);
+		else
+			dg2_cdclk_squash_program(dev_priv, waveform);
+	}
 
 	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
 		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d5850761a75a..c9639f0f4f49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5944,6 +5944,8 @@ enum skl_power_gate {
 #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
 #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
 #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
+#define  LNL_CDCLK_CD2X_PIPE(pipe)	((pipe) << 19)
+#define  LNL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
 #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
 #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
 #define  TGL_CDCLK_CD2X_PIPE(pipe)	BXT_CDCLK_CD2X_PIPE(pipe)
-- 
2.40.1

[Intel-gfx] [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Previously we always updated DBuf MBUS CTL and DBUF CTL regs after
CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like
that anymore. According to BSpec, we have to first update DBuf regs and
then write CDCLK regs, when CDCLK is decreased, which we do in post
plane.

So now we do CDCLK post plane update only after DBuf regs are
written (CDCLK/MDCLK separation requires MDCLK/CDCLK ratio to be written
to DBuf regs).

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f9eda7ad892e..de813831a5cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7113,7 +7113,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	dev_priv->display.funcs.display->commit_modeset_enables(state);
 
-	if (state->modeset)
+	if (state->modeset && DISPLAY_VER(dev_priv) < 20)
 		intel_set_cdclk_post_plane_update(state);
 
 	intel_wait_for_vblank_workers(state);
@@ -7160,6 +7160,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	intel_dbuf_post_plane_update(state);
 	intel_psr_post_plane_update(state);
 
+	if (state->modeset && DISPLAY_VER(dev_priv) >= 20)
+		intel_set_cdclk_post_plane_update(state);
+
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 		intel_post_plane_update(state, crtc);
 
-- 
2.40.1

[Intel-xe] [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Previously we always updated DBuf MBUS CTL and DBUF CTL regs after
CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like
that anymore. According to BSpec, we have to first update DBuf regs and
then write CDCLK regs, when CDCLK is decreased, which we do in post
plane.

So now we do CDCLK post plane update only after DBuf regs are
written (CDCLK/MDCLK separation requires MDCLK/CDCLK ratio to be written
to DBuf regs).

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f9eda7ad892e..de813831a5cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7113,7 +7113,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	dev_priv->display.funcs.display->commit_modeset_enables(state);
 
-	if (state->modeset)
+	if (state->modeset && DISPLAY_VER(dev_priv) < 20)
 		intel_set_cdclk_post_plane_update(state);
 
 	intel_wait_for_vblank_workers(state);
@@ -7160,6 +7160,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	intel_dbuf_post_plane_update(state);
 	intel_psr_post_plane_update(state);
 
+	if (state->modeset && DISPLAY_VER(dev_priv) >= 20)
+		intel_set_cdclk_post_plane_update(state);
+
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 		intel_post_plane_update(state, crtc);
 
-- 
2.40.1

[Intel-gfx] [PATCH 38/42] drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

mdclk_cdclk_ratio is a part of dbuf_state and if it changes, it requires
hw to be poked, so we must serialize the global state in that case.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4d8b960389ec..38a9c47e4ae1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2789,7 +2789,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 	struct intel_crtc_state *crtc_state;
 	int min_cdclk, i;
 	enum pipe pipe;
-	struct intel_dbuf_state *dbuf_state;
+	struct intel_dbuf_state *new_dbuf_state;
+	struct intel_dbuf_state *old_dbuf_state;
 
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
 		int ret;
@@ -2823,11 +2824,21 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 		}
 	}
 
-	dbuf_state = intel_atomic_get_new_dbuf_state(state);
-	if (dbuf_state)
-		dbuf_state->mdclk_cdclk_ratio =
+	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+	if (new_dbuf_state && old_dbuf_state) {
+		new_dbuf_state->mdclk_cdclk_ratio =
 			get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
 
+		if (new_dbuf_state->mdclk_cdclk_ratio != old_dbuf_state->mdclk_cdclk_ratio) {
+			int ret;
+
+			ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
+			if (ret)
+				return ret;
+		}
+	}
+
 	min_cdclk = max(cdclk_state->force_min_cdclk,
 			cdclk_state->bw_min_cdclk);
 	for_each_pipe(dev_priv, pipe)
-- 
2.40.1

[Intel-xe] [PATCH 38/42] drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

mdclk_cdclk_ratio is a part of dbuf_state and if it changes, it requires
hw to be poked, so we must serialize the global state in that case.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4d8b960389ec..38a9c47e4ae1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2789,7 +2789,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 	struct intel_crtc_state *crtc_state;
 	int min_cdclk, i;
 	enum pipe pipe;
-	struct intel_dbuf_state *dbuf_state;
+	struct intel_dbuf_state *new_dbuf_state;
+	struct intel_dbuf_state *old_dbuf_state;
 
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
 		int ret;
@@ -2823,11 +2824,21 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 		}
 	}
 
-	dbuf_state = intel_atomic_get_new_dbuf_state(state);
-	if (dbuf_state)
-		dbuf_state->mdclk_cdclk_ratio =
+	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+	if (new_dbuf_state && old_dbuf_state) {
+		new_dbuf_state->mdclk_cdclk_ratio =
 			get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
 
+		if (new_dbuf_state->mdclk_cdclk_ratio != old_dbuf_state->mdclk_cdclk_ratio) {
+			int ret;
+
+			ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
+			if (ret)
+				return ret;
+		}
+	}
+
 	min_cdclk = max(cdclk_state->force_min_cdclk,
 			cdclk_state->bw_min_cdclk);
 	for_each_pipe(dev_priv, pipe)
-- 
2.40.1

[Intel-gfx] [PATCH 39/42] drm/i915/lnl: Add pll table for LNL platform

[Lucas De Marchi]

From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>

Add PLL Table for Lunar Lake platform.

BSpec: 68862
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 411 ++++++++++++++++++-
 1 file changed, 406 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6533ec417806..c8da6985c179 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -697,6 +697,261 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
 	NULL,
 };
 
+static const struct intel_c10pll_state lnl_c10_dp_rbr = {
+	.clock = 162000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0xB4,
+	.pll[1] = 0,
+	.pll[2] = 0x30,
+	.pll[3] = 0x1,
+	.pll[4] = 0x26,
+	.pll[5] = 0xC0,
+	.pll[6] = 0x98,
+	.pll[7] = 0x46,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xC0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x2,
+	.pll[16] = 0x84,
+	.pll[17] = 0x4F,
+	.pll[18] = 0xE5,
+	.pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_dp_hbr1 = {
+	.clock = 270000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0xF4,
+	.pll[1] = 0,
+	.pll[2] = 0xF8,
+	.pll[3] = 0x0,
+	.pll[4] = 0x20,
+	.pll[5] = 0xA0,
+	.pll[6] = 0x29,
+	.pll[7] = 0x10,
+	.pll[8] = 0x1,   /* Verify */
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xA0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x1,
+	.pll[16] = 0x84,
+	.pll[17] = 0x4F,
+	.pll[18] = 0xE5,
+	.pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_dp_hbr2 = {
+	.clock = 540000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0xF4,
+	.pll[1] = 0,
+	.pll[2] = 0xF8,
+	.pll[3] = 0,
+	.pll[4] = 0x20,
+	.pll[5] = 0xA0,
+	.pll[6] = 0x29,
+	.pll[7] = 0x10,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xA0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0,
+	.pll[16] = 0x84,
+	.pll[17] = 0x4F,
+	.pll[18] = 0xE5,
+	.pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_dp_hbr3 = {
+	.clock = 810000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0x34,
+	.pll[1] = 0,
+	.pll[2] = 0x84,
+	.pll[3] = 0x1,
+	.pll[4] = 0x30,
+	.pll[5] = 0xF0,
+	.pll[6] = 0x3D,
+	.pll[7] = 0x98,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xF0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0,
+	.pll[16] = 0x84,
+	.pll[17] = 0x0F,
+	.pll[18] = 0xE5,
+	.pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r216 = {
+	.clock = 216000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0x4,
+	.pll[1] = 0,
+	.pll[2] = 0xA2,
+	.pll[3] = 0x1,
+	.pll[4] = 0x33,
+	.pll[5] = 0x10,
+	.pll[6] = 0x75,
+	.pll[7] = 0xB3,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x2,
+	.pll[16] = 0x85,
+	.pll[17] = 0x20,
+	.pll[18] = 0xE6,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r243 = {
+	.clock = 243000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0x34,
+	.pll[1] = 0,
+	.pll[2] = 0xDA,
+	.pll[3] = 0x1,
+	.pll[4] = 0x39,
+	.pll[5] = 0x12,
+	.pll[6] = 0xE3,
+	.pll[7] = 0xE9,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0x20,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x2,
+	.pll[16] = 0x85,
+	.pll[17] = 0xA0,
+	.pll[18] = 0xE6,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r324 = {
+	.clock = 324000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0xB4,
+	.pll[1] = 0,
+	.pll[2] = 0x30,
+	.pll[3] = 0x1,
+	.pll[4] = 0x26,
+	.pll[5] = 0xC0,
+	.pll[6] = 0x98,
+	.pll[7] = 0x46,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xC0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x1,
+	.pll[16] = 0x85,
+	.pll[17] = 0x60,
+	.pll[18] = 0xE6,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r432 = {
+	.clock = 432000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0x4,
+	.pll[1] = 0,
+	.pll[2] = 0xA2,
+	.pll[3] = 0x1,
+	.pll[4] = 0x33,
+	.pll[5] = 0x10,
+	.pll[6] = 0x75,
+	.pll[7] = 0xB3,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x1,
+	.pll[16] = 0x85,
+	.pll[17] = 0x20,
+	.pll[18] = 0xE6,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r675 = {
+	.clock = 675000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0xB4,
+	.pll[1] = 0,
+	.pll[2] = 0x3E,
+	.pll[3] = 0x1,
+	.pll[4] = 0xA8,
+	.pll[5] = 0xC8,
+	.pll[6] = 0x33,
+	.pll[7] = 0x54,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xC8,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0,
+	.pll[16] = 0x85,
+	.pll[17] = 0xA0,
+	.pll[18] = 0xE6,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state * const lnl_c10_dp_tables[] = {
+	&lnl_c10_dp_rbr,
+	&lnl_c10_dp_hbr1,
+	&lnl_c10_dp_hbr2,
+	&lnl_c10_dp_hbr3,
+	NULL,
+};
+
+static const struct intel_c10pll_state * const lnl_c10_edp_tables[] = {
+	&lnl_c10_dp_rbr,
+	&lnl_c10_edp_r216,
+	&lnl_c10_edp_r243,
+	&lnl_c10_dp_hbr1,
+	&lnl_c10_edp_r324,
+	&lnl_c10_edp_r432,
+	&lnl_c10_dp_hbr2,
+	&lnl_c10_edp_r675,
+	&lnl_c10_dp_hbr3,
+	NULL,
+};
+
 /* C20 basic DP 1.4 tables */
 static const struct intel_c20pll_state mtl_c20_dp_rbr = {
 	.link_bit_rate = 162000,
@@ -1474,6 +1729,140 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
 	NULL,
 };
 
+/*
+ * HDMI link rates with 38.4 MHz reference clock.
+ */
+
+static const struct intel_c10pll_state lnl_c10_hdmi_252 = {
+	.clock = 25200,
+	.pll[0] = 0x4,
+	.pll[1] = 0,
+	.pll[2] = 0xB2,
+	.pll[3] = 0,
+	.pll[4] = 0,
+	.pll[5] = 0,
+	.pll[6] = 0,
+	.pll[7] = 0,
+	.pll[8] = 0x20,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0xD,
+	.pll[16] = 0x0A,
+	.pll[17] = 0xA0,
+	.pll[18] = 0x87,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_hdmi_27_0 = {
+	.clock = 27000,
+	.pll[0] = 0x34,
+	.pll[1] = 0,
+	.pll[2] = 0xC0,
+	.pll[3] = 0,
+	.pll[4] = 0,
+	.pll[5] = 0,
+	.pll[6] = 0,
+	.pll[7] = 0,
+	.pll[8] = 0x20,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0x80,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0xD,
+	.pll[16] = 0x6,
+	.pll[17] = 0xE0,
+	.pll[18] = 0x84,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_hdmi_74_2 = {
+	.clock = 74250,
+	.pll[0] = 0xF4,
+	.pll[1] = 0,
+	.pll[2] = 0x7A,
+	.pll[3] = 0,
+	.pll[4] = 0,
+	.pll[5] = 0,
+	.pll[6] = 0,
+	.pll[7] = 0,
+	.pll[8] = 0x20,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0x58,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0xB,
+	.pll[16] = 0x6,
+	.pll[17] = 0x20,
+	.pll[18] = 0x85,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_hdmi_148_5 = {
+	.clock = 148500,
+	.pll[0] = 0xF4,
+	.pll[1] = 0,
+	.pll[2] = 0x7A,
+	.pll[3] = 0,
+	.pll[4] = 0,
+	.pll[5] = 0,
+	.pll[6] = 0,
+	.pll[7] = 0,
+	.pll[8] = 0x20,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0x58,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0xA,
+	.pll[16] = 0x6,
+	.pll[17] = 0x20,
+	.pll[18] = 0x85,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_hdmi_594 = {
+	.clock = 594000,
+	.pll[0] = 0xF4,
+	.pll[1] = 0,
+	.pll[2] = 0x7A,
+	.pll[3] = 0,
+	.pll[4] = 0,
+	.pll[5] = 0,
+	.pll[6] = 0,
+	.pll[7] = 0,
+	.pll[8] = 0x20,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0x58,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x8,
+	.pll[16] = 0x6,
+	.pll[17] = 0x20,
+	.pll[18] = 0x85,
+	.pll[19] = 0x2F,
+};
+
+/* Consolidated Table */
+static const struct intel_c10pll_state * const lnl_c10_hdmi_tables[] = {
+	&lnl_c10_hdmi_252,
+	&lnl_c10_hdmi_27_0,
+	&lnl_c10_hdmi_74_2,
+	&lnl_c10_hdmi_148_5,
+	&lnl_c10_hdmi_594,
+	NULL,
+};
+
 static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
 	.link_bit_rate = 25175,
 	.clock = 25175,
@@ -1765,13 +2154,25 @@ static const struct intel_c10pll_state * const *
 intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
 			struct intel_encoder *encoder)
 {
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
-		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
-			return mtl_c10_edp_tables;
-		else
-			return mtl_c10_dp_tables;
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+			if (DISPLAY_VER(i915) >= 20)
+				return lnl_c10_edp_tables;
+			else
+				return mtl_c10_edp_tables;
+		} else {
+			if (DISPLAY_VER(i915) >= 20)
+				return lnl_c10_dp_tables;
+			else
+				return mtl_c10_dp_tables;
+		}
 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
-		return mtl_c10_hdmi_tables;
+		if (DISPLAY_VER(i915) >= 20)
+			return lnl_c10_hdmi_tables;
+		else
+			return mtl_c10_hdmi_tables;
 	}
 
 	MISSING_CASE(encoder->type);
-- 
2.40.1

[Intel-xe] [PATCH 39/42] drm/i915/lnl: Add pll table for LNL platform

[Lucas De Marchi]

From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>

Add PLL Table for Lunar Lake platform.

BSpec: 68862
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 411 ++++++++++++++++++-
 1 file changed, 406 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6533ec417806..c8da6985c179 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -697,6 +697,261 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
 	NULL,
 };
 
+static const struct intel_c10pll_state lnl_c10_dp_rbr = {
+	.clock = 162000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0xB4,
+	.pll[1] = 0,
+	.pll[2] = 0x30,
+	.pll[3] = 0x1,
+	.pll[4] = 0x26,
+	.pll[5] = 0xC0,
+	.pll[6] = 0x98,
+	.pll[7] = 0x46,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xC0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x2,
+	.pll[16] = 0x84,
+	.pll[17] = 0x4F,
+	.pll[18] = 0xE5,
+	.pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_dp_hbr1 = {
+	.clock = 270000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0xF4,
+	.pll[1] = 0,
+	.pll[2] = 0xF8,
+	.pll[3] = 0x0,
+	.pll[4] = 0x20,
+	.pll[5] = 0xA0,
+	.pll[6] = 0x29,
+	.pll[7] = 0x10,
+	.pll[8] = 0x1,   /* Verify */
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xA0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x1,
+	.pll[16] = 0x84,
+	.pll[17] = 0x4F,
+	.pll[18] = 0xE5,
+	.pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_dp_hbr2 = {
+	.clock = 540000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0xF4,
+	.pll[1] = 0,
+	.pll[2] = 0xF8,
+	.pll[3] = 0,
+	.pll[4] = 0x20,
+	.pll[5] = 0xA0,
+	.pll[6] = 0x29,
+	.pll[7] = 0x10,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xA0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0,
+	.pll[16] = 0x84,
+	.pll[17] = 0x4F,
+	.pll[18] = 0xE5,
+	.pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_dp_hbr3 = {
+	.clock = 810000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0x34,
+	.pll[1] = 0,
+	.pll[2] = 0x84,
+	.pll[3] = 0x1,
+	.pll[4] = 0x30,
+	.pll[5] = 0xF0,
+	.pll[6] = 0x3D,
+	.pll[7] = 0x98,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xF0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0,
+	.pll[16] = 0x84,
+	.pll[17] = 0x0F,
+	.pll[18] = 0xE5,
+	.pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r216 = {
+	.clock = 216000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0x4,
+	.pll[1] = 0,
+	.pll[2] = 0xA2,
+	.pll[3] = 0x1,
+	.pll[4] = 0x33,
+	.pll[5] = 0x10,
+	.pll[6] = 0x75,
+	.pll[7] = 0xB3,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x2,
+	.pll[16] = 0x85,
+	.pll[17] = 0x20,
+	.pll[18] = 0xE6,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r243 = {
+	.clock = 243000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0x34,
+	.pll[1] = 0,
+	.pll[2] = 0xDA,
+	.pll[3] = 0x1,
+	.pll[4] = 0x39,
+	.pll[5] = 0x12,
+	.pll[6] = 0xE3,
+	.pll[7] = 0xE9,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0x20,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x2,
+	.pll[16] = 0x85,
+	.pll[17] = 0xA0,
+	.pll[18] = 0xE6,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r324 = {
+	.clock = 324000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0xB4,
+	.pll[1] = 0,
+	.pll[2] = 0x30,
+	.pll[3] = 0x1,
+	.pll[4] = 0x26,
+	.pll[5] = 0xC0,
+	.pll[6] = 0x98,
+	.pll[7] = 0x46,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xC0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x1,
+	.pll[16] = 0x85,
+	.pll[17] = 0x60,
+	.pll[18] = 0xE6,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r432 = {
+	.clock = 432000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0x4,
+	.pll[1] = 0,
+	.pll[2] = 0xA2,
+	.pll[3] = 0x1,
+	.pll[4] = 0x33,
+	.pll[5] = 0x10,
+	.pll[6] = 0x75,
+	.pll[7] = 0xB3,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x1,
+	.pll[16] = 0x85,
+	.pll[17] = 0x20,
+	.pll[18] = 0xE6,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r675 = {
+	.clock = 675000,
+	.tx = 0x10,
+	.cmn = 0x21,
+	.pll[0] = 0xB4,
+	.pll[1] = 0,
+	.pll[2] = 0x3E,
+	.pll[3] = 0x1,
+	.pll[4] = 0xA8,
+	.pll[5] = 0xC8,
+	.pll[6] = 0x33,
+	.pll[7] = 0x54,
+	.pll[8] = 0x1,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0xC8,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0,
+	.pll[16] = 0x85,
+	.pll[17] = 0xA0,
+	.pll[18] = 0xE6,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state * const lnl_c10_dp_tables[] = {
+	&lnl_c10_dp_rbr,
+	&lnl_c10_dp_hbr1,
+	&lnl_c10_dp_hbr2,
+	&lnl_c10_dp_hbr3,
+	NULL,
+};
+
+static const struct intel_c10pll_state * const lnl_c10_edp_tables[] = {
+	&lnl_c10_dp_rbr,
+	&lnl_c10_edp_r216,
+	&lnl_c10_edp_r243,
+	&lnl_c10_dp_hbr1,
+	&lnl_c10_edp_r324,
+	&lnl_c10_edp_r432,
+	&lnl_c10_dp_hbr2,
+	&lnl_c10_edp_r675,
+	&lnl_c10_dp_hbr3,
+	NULL,
+};
+
 /* C20 basic DP 1.4 tables */
 static const struct intel_c20pll_state mtl_c20_dp_rbr = {
 	.link_bit_rate = 162000,
@@ -1474,6 +1729,140 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
 	NULL,
 };
 
+/*
+ * HDMI link rates with 38.4 MHz reference clock.
+ */
+
+static const struct intel_c10pll_state lnl_c10_hdmi_252 = {
+	.clock = 25200,
+	.pll[0] = 0x4,
+	.pll[1] = 0,
+	.pll[2] = 0xB2,
+	.pll[3] = 0,
+	.pll[4] = 0,
+	.pll[5] = 0,
+	.pll[6] = 0,
+	.pll[7] = 0,
+	.pll[8] = 0x20,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0xD,
+	.pll[16] = 0x0A,
+	.pll[17] = 0xA0,
+	.pll[18] = 0x87,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_hdmi_27_0 = {
+	.clock = 27000,
+	.pll[0] = 0x34,
+	.pll[1] = 0,
+	.pll[2] = 0xC0,
+	.pll[3] = 0,
+	.pll[4] = 0,
+	.pll[5] = 0,
+	.pll[6] = 0,
+	.pll[7] = 0,
+	.pll[8] = 0x20,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0x80,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0xD,
+	.pll[16] = 0x6,
+	.pll[17] = 0xE0,
+	.pll[18] = 0x84,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_hdmi_74_2 = {
+	.clock = 74250,
+	.pll[0] = 0xF4,
+	.pll[1] = 0,
+	.pll[2] = 0x7A,
+	.pll[3] = 0,
+	.pll[4] = 0,
+	.pll[5] = 0,
+	.pll[6] = 0,
+	.pll[7] = 0,
+	.pll[8] = 0x20,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0x58,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0xB,
+	.pll[16] = 0x6,
+	.pll[17] = 0x20,
+	.pll[18] = 0x85,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_hdmi_148_5 = {
+	.clock = 148500,
+	.pll[0] = 0xF4,
+	.pll[1] = 0,
+	.pll[2] = 0x7A,
+	.pll[3] = 0,
+	.pll[4] = 0,
+	.pll[5] = 0,
+	.pll[6] = 0,
+	.pll[7] = 0,
+	.pll[8] = 0x20,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0x58,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0xA,
+	.pll[16] = 0x6,
+	.pll[17] = 0x20,
+	.pll[18] = 0x85,
+	.pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_hdmi_594 = {
+	.clock = 594000,
+	.pll[0] = 0xF4,
+	.pll[1] = 0,
+	.pll[2] = 0x7A,
+	.pll[3] = 0,
+	.pll[4] = 0,
+	.pll[5] = 0,
+	.pll[6] = 0,
+	.pll[7] = 0,
+	.pll[8] = 0x20,
+	.pll[9] = 0x1,
+	.pll[10] = 0,
+	.pll[11] = 0,
+	.pll[12] = 0x58,
+	.pll[13] = 0,
+	.pll[14] = 0,
+	.pll[15] = 0x8,
+	.pll[16] = 0x6,
+	.pll[17] = 0x20,
+	.pll[18] = 0x85,
+	.pll[19] = 0x2F,
+};
+
+/* Consolidated Table */
+static const struct intel_c10pll_state * const lnl_c10_hdmi_tables[] = {
+	&lnl_c10_hdmi_252,
+	&lnl_c10_hdmi_27_0,
+	&lnl_c10_hdmi_74_2,
+	&lnl_c10_hdmi_148_5,
+	&lnl_c10_hdmi_594,
+	NULL,
+};
+
 static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
 	.link_bit_rate = 25175,
 	.clock = 25175,
@@ -1765,13 +2154,25 @@ static const struct intel_c10pll_state * const *
 intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
 			struct intel_encoder *encoder)
 {
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
-		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
-			return mtl_c10_edp_tables;
-		else
-			return mtl_c10_dp_tables;
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+			if (DISPLAY_VER(i915) >= 20)
+				return lnl_c10_edp_tables;
+			else
+				return mtl_c10_edp_tables;
+		} else {
+			if (DISPLAY_VER(i915) >= 20)
+				return lnl_c10_dp_tables;
+			else
+				return mtl_c10_dp_tables;
+		}
 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
-		return mtl_c10_hdmi_tables;
+		if (DISPLAY_VER(i915) >= 20)
+			return lnl_c10_hdmi_tables;
+		else
+			return mtl_c10_hdmi_tables;
 	}
 
 	MISSING_CASE(encoder->type);
-- 
2.40.1

[Intel-gfx] [PATCH 40/42] drm/i915/lnl: Add support to check c10 phy link rate

[Lucas De Marchi]

From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>

Add support to check c10 phy link rate for LNL in
intel_c10_phy_check_hdmi_link_rate() function.

BSpec: 68862
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index c8da6985c179..d9c43f3b4f34 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2137,11 +2137,16 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
 	NULL,
 };
 
-static int intel_c10_phy_check_hdmi_link_rate(int clock)
+static int intel_c10_phy_check_hdmi_link_rate(struct drm_i915_private *i915, int clock)
 {
-	const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
+	const struct intel_c10pll_state * const *tables;
 	int i;
 
+	if (DISPLAY_VER(i915) >= 20)
+		tables = lnl_c10_hdmi_tables;
+	else
+		tables = mtl_c10_hdmi_tables;
+
 	for (i = 0; tables[i]; i++) {
 		if (clock == tables[i]->clock)
 			return MODE_OK;
@@ -2414,7 +2419,7 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
 	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
 	if (intel_is_c10phy(i915, phy))
-		return intel_c10_phy_check_hdmi_link_rate(clock);
+		return intel_c10_phy_check_hdmi_link_rate(i915, clock);
 	return intel_c20_phy_check_hdmi_link_rate(clock);
 }
 
-- 
2.40.1

[Intel-xe] [PATCH 40/42] drm/i915/lnl: Add support to check c10 phy link rate

[Lucas De Marchi]

From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>

Add support to check c10 phy link rate for LNL in
intel_c10_phy_check_hdmi_link_rate() function.

BSpec: 68862
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index c8da6985c179..d9c43f3b4f34 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2137,11 +2137,16 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
 	NULL,
 };
 
-static int intel_c10_phy_check_hdmi_link_rate(int clock)
+static int intel_c10_phy_check_hdmi_link_rate(struct drm_i915_private *i915, int clock)
 {
-	const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
+	const struct intel_c10pll_state * const *tables;
 	int i;
 
+	if (DISPLAY_VER(i915) >= 20)
+		tables = lnl_c10_hdmi_tables;
+	else
+		tables = mtl_c10_hdmi_tables;
+
 	for (i = 0; tables[i]; i++) {
 		if (clock == tables[i]->clock)
 			return MODE_OK;
@@ -2414,7 +2419,7 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
 	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
 	if (intel_is_c10phy(i915, phy))
-		return intel_c10_phy_check_hdmi_link_rate(clock);
+		return intel_c10_phy_check_hdmi_link_rate(i915, clock);
 	return intel_c20_phy_check_hdmi_link_rate(clock);
 }
 
-- 
2.40.1

[Intel-xe] [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

According to BSpec we need to write the MBUS CTL and DBUF CTL both for
increasing CDCLK case (pre plane) and for decreasing CDCLK case (post
plane). Make sure those updates are in place for Xe2-LPD.

Since the mbus update is not only on pre-enable anymore, also rename the
function accordingly.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 79454b4d99e3..77a4c85538c2 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3493,7 +3493,7 @@ static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
  * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
  * update the request state of all DBUS slices.
  */
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+static void update_mbus(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	u32 mbus_ctl, dbuf_min_tracker_val;
@@ -3552,7 +3552,7 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
 
 	WARN_ON(!new_dbuf_state->base.changed);
 
-	update_mbus_pre_enable(state);
+	update_mbus(state);
 	gen9_dbuf_slices_update(i915,
 				old_dbuf_state->enabled_slices |
 				new_dbuf_state->enabled_slices);
@@ -3574,6 +3574,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 
 	WARN_ON(!new_dbuf_state->base.changed);
 
+	if (DISPLAY_VER(i915) >= 20)
+		update_mbus(state);
+
 	gen9_dbuf_slices_update(i915,
 				new_dbuf_state->enabled_slices);
 }
-- 
2.40.1

[Intel-gfx] [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

According to BSpec we need to write the MBUS CTL and DBUF CTL both for
increasing CDCLK case (pre plane) and for decreasing CDCLK case (post
plane). Make sure those updates are in place for Xe2-LPD.

Since the mbus update is not only on pre-enable anymore, also rename the
function accordingly.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 79454b4d99e3..77a4c85538c2 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3493,7 +3493,7 @@ static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
  * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
  * update the request state of all DBUS slices.
  */
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+static void update_mbus(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	u32 mbus_ctl, dbuf_min_tracker_val;
@@ -3552,7 +3552,7 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
 
 	WARN_ON(!new_dbuf_state->base.changed);
 
-	update_mbus_pre_enable(state);
+	update_mbus(state);
 	gen9_dbuf_slices_update(i915,
 				old_dbuf_state->enabled_slices |
 				new_dbuf_state->enabled_slices);
@@ -3574,6 +3574,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 
 	WARN_ON(!new_dbuf_state->base.changed);
 
+	if (DISPLAY_VER(i915) >= 20)
+		update_mbus(state);
+
 	gen9_dbuf_slices_update(i915,
 				new_dbuf_state->enabled_slices);
 }
-- 
2.40.1

[Intel-xe] [PATCH 42/42] drm/xe/lnl: Enable the display support

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Enable the display support for LUNARLAKE

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 7fb00ea410a6..f723e19e8ca5 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -337,6 +337,7 @@ static const struct xe_device_desc mtl_desc = {
 
 static const struct xe_device_desc lnl_desc = {
 	PLATFORM(XE_LUNARLAKE),
+	.has_display = true,
 	.require_force_probe = true,
 };
 
-- 
2.40.1

[Intel-gfx] [PATCH 42/42] drm/xe/lnl: Enable the display support

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Enable the display support for LUNARLAKE

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 7fb00ea410a6..f723e19e8ca5 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -337,6 +337,7 @@ static const struct xe_device_desc mtl_desc = {
 
 static const struct xe_device_desc lnl_desc = {
 	PLATFORM(XE_LUNARLAKE),
+	.has_display = true,
 	.require_force_probe = true,
 };
 
-- 
2.40.1

[Intel-xe] ✓ CI.Patch_applied: success for Enable Lunar Lake display

[Patchwork]

== Series Details ==

Series: Enable Lunar Lake display
URL   : https://patchwork.freedesktop.org/series/122798/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: 8ca78f69c drm/xe: Drop xe_mmio_write64()
=== git am output follows ===
Applying: drm/i915: Start using plane scale factor for relative data rate
Applying: drm/i915/display: Remove unused POWER_DOMAIN_MASK
Applying: drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
Applying: drm/i915: Simplify intel_cx0_program_phy_lane() with loop
Applying: drm/i915/cx0: Enable/disable TX only for owned PHY lanes
Applying: drm/i915/cx0: Program vswing only for owned lanes
Applying: drm/i915/tc: rename mtl_tc_port_get_pin_assignment_mask()
Applying: drm/i915/tc: make intel_tc_port_get_lane_mask() static
Applying: drm/i915/tc: move legacy code out of the main _max_lane_count() func
Applying: drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()
Applying: drm/xe/lnl: Add IS_LUNARLAKE
Applying: drm/i915/lnl: Add display definitions
Applying: drm/i915: Re-order if/else ladder in intel_detect_pch()
Applying: drm/i915/lnl: Add fake PCH
Applying: drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
Applying: drm/i915/xe2lpd: Move D2D enable/disable
Applying: drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL
Applying: drm/i915/xe2lpd: Move registers to PICA
Applying: drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
Applying: drm/i915/xe2lpd: Register DE_RRMR has been removed
Applying: drm/i915/xe2lpd: Add display power well
Applying: drm/i915/xe2lpd: Add DC state support
Applying: drm/i915/xe2lpd: FBC is now supported on all pipes
Applying: drm/i915/display: Remove FBC capability from fused off pipes
Applying: drm/i915/xe2lpd: Add support for DP aux channels
Applying: drm/i915/xe2lpd: Handle port AUX interrupts
Applying: drm/i915/xe2lpd: Read pin assignment from IOM
Applying: drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd
Applying: drm/i915/xe2lpd: Add support for HPD
Applying: drm/i915/xe2lpd: Extend Wa_15010685871
Applying: drm/i915/lnl: Add gmbus/ddc support
Applying: drm/i915/lnl: Introduce MDCLK
Applying: drm/i915/lnl: Add CDCLK table
Applying: drm/i915/lnl: Start using CDCLK through PLL
Applying: drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
Applying: drm/i915/lnl: Add support for CDCLK initialization sequence
Applying: drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
Applying: drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.
Applying: drm/i915/lnl: Add pll table for LNL platform
Applying: drm/i915/lnl: Add support to check c10 phy link rate
Applying: drm/i915/xe2lpd: Update mbus on post plane updates
Applying: drm/xe/lnl: Enable the display support

[Intel-xe] ✗ CI.checkpatch: warning for Enable Lunar Lake display

[Patchwork]

== Series Details ==

Series: Enable Lunar Lake display
URL   : https://patchwork.freedesktop.org/series/122798/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
e700ea2f248a75138759bcb443affeef4a2d1991
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 7a7fb548ba0cb08b1ac786ba86008a9e3356153c
Author: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Date:   Wed Aug 23 10:07:40 2023 -0700

    drm/xe/lnl: Enable the display support
    
    Enable the display support for LUNARLAKE
    
    Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
+ /mt/dim checkpatch 8ca78f69c23d5f68a24bdacc014f82eff9719980 drm-intel
/mt/dim: line 50: /root/.dimrc: No such file or directory

[Intel-xe] ✓ CI.KUnit: success for Enable Lunar Lake display

[Patchwork]

== Series Details ==

Series: Enable Lunar Lake display
URL   : https://patchwork.freedesktop.org/series/122798/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
stty: 'standard input': Inappropriate ioctl for device
[17:12:46] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:12:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[17:13:09] Starting KUnit Kernel (1/1)...
[17:13:09] ============================================================
[17:13:09] ==================== xe_bo (2 subtests) ====================
[17:13:09] [SKIPPED] xe_ccs_migrate_kunit
[17:13:09] [SKIPPED] xe_bo_evict_kunit
[17:13:09] ===================== [SKIPPED] xe_bo ======================
[17:13:09] ================== xe_dma_buf (1 subtest) ==================
[17:13:09] [SKIPPED] xe_dma_buf_kunit
[17:13:09] =================== [SKIPPED] xe_dma_buf ===================
[17:13:09] ================== xe_migrate (1 subtest) ==================
[17:13:09] [SKIPPED] xe_migrate_sanity_kunit
[17:13:09] =================== [SKIPPED] xe_migrate ===================
[17:13:09] =================== xe_pci (2 subtests) ====================
[17:13:09] [PASSED] xe_gmdid_graphics_ip
[17:13:09] [PASSED] xe_gmdid_media_ip
[17:13:09] ===================== [PASSED] xe_pci ======================
[17:13:09] ==================== xe_rtp (1 subtest) ====================
[17:13:09] ================== xe_rtp_process_tests  ===================
[17:13:09] [PASSED] coalesce-same-reg
[17:13:09] [PASSED] no-match-no-add
[17:13:09] [PASSED] no-match-no-add-multiple-rules
[17:13:09] [PASSED] two-regs-two-entries
[17:13:09] [PASSED] clr-one-set-other
[17:13:09] [PASSED] set-field
[17:13:09] [PASSED] conflict-duplicate
[17:13:09] [PASSED] conflict-not-disjoint
[17:13:09] [PASSED] conflict-reg-type
[17:13:09] ============== [PASSED] xe_rtp_process_tests ===============
[17:13:09] ===================== [PASSED] xe_rtp ======================
[17:13:09] ==================== xe_wa (1 subtest) =====================
[17:13:09] ======================== xe_wa_gt  =========================
[17:13:09] [PASSED] TIGERLAKE (B0)
[17:13:09] [PASSED] DG1 (A0)
[17:13:09] [PASSED] DG1 (B0)
[17:13:09] [PASSED] ALDERLAKE_S (A0)
[17:13:09] [PASSED] ALDERLAKE_S (B0)
[17:13:09] [PASSED] ALDERLAKE_S (C0)
[17:13:09] [PASSED] ALDERLAKE_S (D0)
[17:13:09] [PASSED] ALDERLAKE_P (A0)
[17:13:09] [PASSED] ALDERLAKE_P (B0)
[17:13:09] [PASSED] ALDERLAKE_P (C0)
[17:13:09] [PASSED] DG2_G10 (A0)
[17:13:09] [PASSED] DG2_G10 (A1)
[17:13:09] [PASSED] DG2_G10 (B0)
[17:13:09] [PASSED] DG2_G10 (C0)
[17:13:09] [PASSED] DG2_G11 (A0)
[17:13:09] [PASSED] DG2_G11 (B0)
[17:13:09] [PASSED] DG2_G11 (B1)
[17:13:09] [PASSED] DG2_G12 (A0)
[17:13:09] [PASSED] DG2_G12 (A1)
[17:13:09] [PASSED] PVC (B0)
[17:13:09] [PASSED] PVC (B1)
[17:13:09] [PASSED] PVC (C0)
[17:13:09] ==================== [PASSED] xe_wa_gt =====================
[17:13:09] ====================== [PASSED] xe_wa ======================
[17:13:09] ============================================================
[17:13:09] Testing complete. Ran 37 tests: passed: 33, skipped: 4
[17:13:09] Elapsed time: 23.745s total, 4.263s configuring, 19.312s building, 0.144s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:13:10] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:13:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[17:13:30] Starting KUnit Kernel (1/1)...
[17:13:30] ============================================================
[17:13:30] ============ drm_test_pick_cmdline (2 subtests) ============
[17:13:30] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:13:30] =============== drm_test_pick_cmdline_named  ===============
[17:13:30] [PASSED] NTSC
[17:13:30] [PASSED] NTSC-J
[17:13:30] [PASSED] PAL
[17:13:30] [PASSED] PAL-M
[17:13:30] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:13:30] ============== [PASSED] drm_test_pick_cmdline ==============
[17:13:30] ================== drm_buddy (6 subtests) ==================
[17:13:30] [PASSED] drm_test_buddy_alloc_limit
[17:13:30] [PASSED] drm_test_buddy_alloc_range
[17:13:30] [PASSED] drm_test_buddy_alloc_optimistic
[17:13:30] [PASSED] drm_test_buddy_alloc_pessimistic
[17:13:30] [PASSED] drm_test_buddy_alloc_smoke
[17:13:30] [PASSED] drm_test_buddy_alloc_pathological
[17:13:30] ==================== [PASSED] drm_buddy ====================
[17:13:30] ============= drm_cmdline_parser (40 subtests) =============
[17:13:30] [PASSED] drm_test_cmdline_force_d_only
[17:13:30] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:13:30] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:13:30] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:13:30] [PASSED] drm_test_cmdline_force_e_only
[17:13:30] [PASSED] drm_test_cmdline_res
[17:13:30] [PASSED] drm_test_cmdline_res_vesa
[17:13:30] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:13:30] [PASSED] drm_test_cmdline_res_rblank
[17:13:30] [PASSED] drm_test_cmdline_res_bpp
[17:13:30] [PASSED] drm_test_cmdline_res_refresh
[17:13:30] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:13:30] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:13:30] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:13:30] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:13:30] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:13:30] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:13:30] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:13:30] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:13:30] [PASSED] drm_test_cmdline_res_margins_force_on
[17:13:30] [PASSED] drm_test_cmdline_res_vesa_margins
[17:13:30] [PASSED] drm_test_cmdline_name
[17:13:30] [PASSED] drm_test_cmdline_name_bpp
[17:13:30] [PASSED] drm_test_cmdline_name_option
[17:13:30] [PASSED] drm_test_cmdline_name_bpp_option
[17:13:30] [PASSED] drm_test_cmdline_rotate_0
[17:13:30] [PASSED] drm_test_cmdline_rotate_90
[17:13:30] [PASSED] drm_test_cmdline_rotate_180
[17:13:30] [PASSED] drm_test_cmdline_rotate_270
[17:13:30] [PASSED] drm_test_cmdline_hmirror
[17:13:30] [PASSED] drm_test_cmdline_vmirror
[17:13:30] [PASSED] drm_test_cmdline_margin_options
[17:13:30] [PASSED] drm_test_cmdline_multiple_options
[17:13:30] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:13:30] [PASSED] drm_test_cmdline_extra_and_option
[17:13:30] [PASSED] drm_test_cmdline_freestanding_options
[17:13:30] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:13:30] [PASSED] drm_test_cmdline_panel_orientation
[17:13:30] ================ drm_test_cmdline_invalid  =================
[17:13:30] [PASSED] margin_only
[17:13:30] [PASSED] interlace_only
[17:13:30] [PASSED] res_missing_x
[17:13:30] [PASSED] res_missing_y
[17:13:30] [PASSED] res_bad_y
[17:13:30] [PASSED] res_missing_y_bpp
[17:13:30] [PASSED] res_bad_bpp
[17:13:30] [PASSED] res_bad_refresh
[17:13:30] [PASSED] res_bpp_refresh_force_on_off
[17:13:30] [PASSED] res_invalid_mode
[17:13:30] [PASSED] res_bpp_wrong_place_mode
[17:13:30] [PASSED] name_bpp_refresh
[17:13:30] [PASSED] name_refresh
[17:13:30] [PASSED] name_refresh_wrong_mode
[17:13:30] [PASSED] name_refresh_invalid_mode
[17:13:30] [PASSED] rotate_multiple
[17:13:30] [PASSED] rotate_invalid_val
[17:13:30] [PASSED] rotate_truncated
[17:13:30] [PASSED] invalid_option
[17:13:30] [PASSED] invalid_tv_option
[17:13:30] [PASSED] truncated_tv_option
[17:13:30] ============ [PASSED] drm_test_cmdline_invalid =============
[17:13:30] =============== drm_test_cmdline_tv_options  ===============
[17:13:30] [PASSED] NTSC
[17:13:30] [PASSED] NTSC_443
[17:13:30] [PASSED] NTSC_J
[17:13:30] [PASSED] PAL
[17:13:30] [PASSED] PAL_M
[17:13:30] [PASSED] PAL_N
[17:13:30] [PASSED] SECAM
[17:13:30] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:13:30] =============== [PASSED] drm_cmdline_parser ================
[17:13:30] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:13:30] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:13:30] [PASSED] NTSC
[17:13:30] [PASSED] NTSC-443
[17:13:30] [PASSED] NTSC-J
[17:13:30] [PASSED] PAL
[17:13:30] [PASSED] PAL-M
[17:13:30] [PASSED] PAL-N
[17:13:30] [PASSED] SECAM
[17:13:30] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:13:30] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:13:30] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:13:30] ============= drm_damage_helper (21 subtests) ==============
[17:13:30] [PASSED] drm_test_damage_iter_no_damage
[17:13:30] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:13:30] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:13:30] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:13:30] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:13:30] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:13:30] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:13:30] [PASSED] drm_test_damage_iter_simple_damage
[17:13:30] [PASSED] drm_test_damage_iter_single_damage
[17:13:30] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:13:30] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:13:30] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:13:30] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:13:30] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:13:30] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:13:30] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:13:30] [PASSED] drm_test_damage_iter_damage
[17:13:30] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:13:30] [PASSED] drm_test_damage_iter_damage_one_outside
[17:13:30] [PASSED] drm_test_damage_iter_damage_src_moved
[17:13:30] [PASSED] drm_test_damage_iter_damage_not_visible
[17:13:30] ================ [PASSED] drm_damage_helper ================
[17:13:30] ============== drm_dp_mst_helper (2 subtests) ==============
[17:13:30] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:13:30] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:13:30] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:13:30] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:13:30] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:13:30] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:13:30] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:13:30] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:13:30] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:13:30] [PASSED] DP_POWER_UP_PHY with port number
[17:13:30] [PASSED] DP_POWER_DOWN_PHY with port number
[17:13:30] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:13:30] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:13:30] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:13:30] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:13:30] [PASSED] DP_QUERY_PAYLOAD with port number
[17:13:30] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:13:30] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:13:30] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:13:30] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:13:30] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:13:30] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:13:30] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:13:30] [PASSED] DP_REMOTE_I2C_READ with port number
[17:13:30] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:13:30] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:13:30] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:13:30] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:13:30] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:13:30] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:13:30] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:13:30] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:13:30] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:13:30] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:13:30] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:13:30] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:13:30] ================ [PASSED] drm_dp_mst_helper ================
[17:13:30] =========== drm_format_helper_test (11 subtests) ===========
[17:13:30] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:13:30] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:13:30] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:13:30] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:13:30] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:13:30] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:13:30] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:13:30] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:13:30] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:13:30] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:13:30] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:13:30] [PASSED] single_pixel_source_buffer
[17:13:30] [PASSED] single_pixel_clip_rectangle
[17:13:30] [PASSED] well_known_colors
[17:13:30] [PASSED] destination_pitch
[17:13:30] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:13:30] ============= [PASSED] drm_format_helper_test ==============
[17:13:30] ================= drm_format (18 subtests) =================
[17:13:30] [PASSED] drm_test_format_block_width_invalid
[17:13:30] [PASSED] drm_test_format_block_width_one_plane
[17:13:30] [PASSED] drm_test_format_block_width_two_plane
[17:13:30] [PASSED] drm_test_format_block_width_three_plane
[17:13:30] [PASSED] drm_test_format_block_width_tiled
[17:13:30] [PASSED] drm_test_format_block_height_invalid
[17:13:30] [PASSED] drm_test_format_block_height_one_plane
[17:13:30] [PASSED] drm_test_format_block_height_two_plane
[17:13:30] [PASSED] drm_test_format_block_height_three_plane
[17:13:30] [PASSED] drm_test_format_block_height_tiled
[17:13:30] [PASSED] drm_test_format_min_pitch_invalid
[17:13:30] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:13:30] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:13:30] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:13:30] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:13:30] [PASSED] drm_test_format_min_pitch_two_plane
[17:13:30] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:13:30] [PASSED] drm_test_format_min_pitch_tiled
[17:13:30] =================== [PASSED] drm_format ====================
[17:13:30] =============== drm_framebuffer (1 subtest) ================
[17:13:30] =============== drm_test_framebuffer_create  ===============
[17:13:30] [PASSED] ABGR8888 normal sizes
[17:13:30] [PASSED] ABGR8888 max sizes
[17:13:30] [PASSED] ABGR8888 pitch greater than min required
[17:13:30] [PASSED] ABGR8888 pitch less than min required
[17:13:30] [PASSED] ABGR8888 Invalid width
[17:13:30] [PASSED] ABGR8888 Invalid buffer handle
[17:13:30] [PASSED] No pixel format
[17:13:30] [PASSED] ABGR8888 Width 0
[17:13:30] [PASSED] ABGR8888 Height 0
[17:13:30] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:13:30] [PASSED] ABGR8888 Large buffer offset
[17:13:30] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:13:30] [PASSED] ABGR8888 Valid buffer modifier
[17:13:30] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:13:30] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:13:30] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:13:30] [PASSED] NV12 Normal sizes
[17:13:30] [PASSED] NV12 Max sizes
[17:13:30] [PASSED] NV12 Invalid pitch
[17:13:30] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:13:30] [PASSED] NV12 different  modifier per-plane
[17:13:30] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:13:30] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:13:30] [PASSED] NV12 Modifier for inexistent plane
[17:13:30] [PASSED] NV12 Handle for inexistent plane
[17:13:30] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:13:30] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:13:30] [PASSED] YVU420 Normal sizes
[17:13:30] [PASSED] YVU420 Max sizes
[17:13:30] [PASSED] YVU420 Invalid pitch
[17:13:30] [PASSED] YVU420 Different pitches
[17:13:30] [PASSED] YVU420 Different buffer offsets/pitches
[17:13:30] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:13:30] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:13:30] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:13:30] [PASSED] YVU420 Valid modifier
[17:13:30] [PASSED] YVU420 Different modifiers per plane
[17:13:30] [PASSED] YVU420 Modifier for inexistent plane
[17:13:30] [PASSED] X0L2 Normal sizes
[17:13:30] [PASSED] X0L2 Max sizes
[17:13:30] [PASSED] X0L2 Invalid pitch
[17:13:30] [PASSED] X0L2 Pitch greater than minimum required
stty: 'standard input': Inappropriate ioctl for device
[17:13:30] [PASSED] X0L2 Handle for inexistent plane
[17:13:30] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:13:30] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:13:30] [PASSED] X0L2 Valid modifier
[17:13:30] [PASSED] X0L2 Modifier for inexistent plane
[17:13:30] =========== [PASSED] drm_test_framebuffer_create ===========
[17:13:30] ================= [PASSED] drm_framebuffer =================
[17:13:30] =============== drm-test-managed (1 subtest) ===============
[17:13:30] [PASSED] drm_test_managed_run_action
[17:13:30] ================ [PASSED] drm-test-managed =================
[17:13:30] =================== drm_mm (19 subtests) ===================
[17:13:30] [PASSED] drm_test_mm_init
[17:13:30] [PASSED] drm_test_mm_debug
[17:13:40] [PASSED] drm_test_mm_reserve
[17:13:50] [PASSED] drm_test_mm_insert
[17:13:50] [PASSED] drm_test_mm_replace
[17:13:50] [PASSED] drm_test_mm_insert_range
[17:13:51] [PASSED] drm_test_mm_frag
[17:13:51] [PASSED] drm_test_mm_align
[17:13:51] [PASSED] drm_test_mm_align32
[17:13:51] [PASSED] drm_test_mm_align64
[17:13:51] [PASSED] drm_test_mm_evict
[17:13:51] [PASSED] drm_test_mm_evict_range
[17:13:51] [PASSED] drm_test_mm_topdown
[17:13:51] [PASSED] drm_test_mm_bottomup
[17:13:51] [PASSED] drm_test_mm_lowest
[17:13:51] [PASSED] drm_test_mm_highest
[17:13:52] [PASSED] drm_test_mm_color
[17:13:53] [PASSED] drm_test_mm_color_evict
[17:13:53] [PASSED] drm_test_mm_color_evict_range
[17:13:53] ===================== [PASSED] drm_mm ======================
[17:13:53] ============= drm_modes_analog_tv (4 subtests) =============
[17:13:53] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:13:53] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:13:53] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:13:53] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:13:53] =============== [PASSED] drm_modes_analog_tv ===============
[17:13:53] ============== drm_plane_helper (2 subtests) ===============
[17:13:53] =============== drm_test_check_plane_state  ================
[17:13:53] [PASSED] clipping_simple
[17:13:53] [PASSED] clipping_rotate_reflect
[17:13:53] [PASSED] positioning_simple
[17:13:53] [PASSED] upscaling
[17:13:53] [PASSED] downscaling
[17:13:53] [PASSED] rounding1
[17:13:53] [PASSED] rounding2
[17:13:53] [PASSED] rounding3
[17:13:53] [PASSED] rounding4
[17:13:53] =========== [PASSED] drm_test_check_plane_state ============
[17:13:53] =========== drm_test_check_invalid_plane_state  ============
[17:13:53] [PASSED] positioning_invalid
[17:13:53] [PASSED] upscaling_invalid
[17:13:53] [PASSED] downscaling_invalid
[17:13:53] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:13:53] ================ [PASSED] drm_plane_helper =================
[17:13:53] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:13:53] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:13:53] [PASSED] None
[17:13:53] [PASSED] PAL
[17:13:53] [PASSED] NTSC
[17:13:53] [PASSED] Both, NTSC Default
[17:13:53] [PASSED] Both, PAL Default
[17:13:53] [PASSED] Both, NTSC Default, with PAL on command-line
[17:13:53] [PASSED] Both, PAL Default, with NTSC on command-line
[17:13:53] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:13:53] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:13:53] ================== drm_rect (9 subtests) ===================
[17:13:53] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:13:53] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:13:53] [PASSED] drm_test_rect_clip_scaled_clipped
[17:13:53] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:13:53] ================= drm_test_rect_intersect  =================
[17:13:53] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:13:53] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:13:53] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:13:53] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:13:53] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:13:53] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:13:53] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:13:53] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:13:53] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:13:53] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:13:53] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:13:53] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:13:53] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:13:53] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:13:53] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:13:53] ============= [PASSED] drm_test_rect_intersect =============
[17:13:53] ================ drm_test_rect_calc_hscale  ================
[17:13:53] [PASSED] normal use
[17:13:53] [PASSED] out of max range
[17:13:53] [PASSED] out of min range
[17:13:53] [PASSED] zero dst
[17:13:53] [PASSED] negative src
[17:13:53] [PASSED] negative dst
[17:13:53] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:13:53] ================ drm_test_rect_calc_vscale  ================
[17:13:53] [PASSED] normal use
[17:13:53] [PASSED] out of max range
[17:13:53] [PASSED] out of min range
[17:13:53] [PASSED] zero dst
[17:13:53] [PASSED] negative src
[17:13:53] [PASSED] negative dst
[17:13:53] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:13:53] ================== drm_test_rect_rotate  ===================
[17:13:53] [PASSED] reflect-x
[17:13:53] [PASSED] reflect-y
[17:13:53] [PASSED] rotate-0
[17:13:53] [PASSED] rotate-90
[17:13:53] [PASSED] rotate-180
[17:13:53] [PASSED] rotate-270
[17:13:53] ============== [PASSED] drm_test_rect_rotate ===============
[17:13:53] ================ drm_test_rect_rotate_inv  =================
[17:13:53] [PASSED] reflect-x
[17:13:53] [PASSED] reflect-y
[17:13:53] [PASSED] rotate-0
[17:13:53] [PASSED] rotate-90
[17:13:53] [PASSED] rotate-180
[17:13:53] [PASSED] rotate-270
[17:13:53] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:13:53] ==================== [PASSED] drm_rect =====================
[17:13:53] ============================================================
[17:13:53] Testing complete. Ran 333 tests: passed: 333
[17:13:53] Elapsed time: 43.041s total, 1.713s configuring, 18.394s building, 22.930s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

[Intel-xe] ✓ CI.Build: success for Enable Lunar Lake display

[Patchwork]

== Series Details ==

Series: Enable Lunar Lake display
URL   : https://patchwork.freedesktop.org/series/122798/
State : success

== Summary ==

+ trap cleanup EXIT
+ cd /kernel
+ git clone https://gitlab.freedesktop.org/drm/xe/ci.git .ci
Cloning into '.ci'...
++ date +%s
^[[0Ksection_start:1692810845:build_x86_64[collapsed=true]
^[[0KBuild x86-64
+ echo -e '\e[0Ksection_start:1692810845:build_x86_64[collapsed=true]\r\e[0KBuild x86-64'
+ mkdir -p build64
+ cat .ci/kernel/kconfig
+ make O=build64 olddefconfig
make[1]: Entering directory '/kernel/build64'
  GEN     Makefile
  HOSTCC  scripts/basic/fixdep
  HOSTCC  scripts/kconfig/conf.o
  HOSTCC  scripts/kconfig/confdata.o
  HOSTCC  scripts/kconfig/expr.o
  LEX     scripts/kconfig/lexer.lex.c
  YACC    scripts/kconfig/parser.tab.[ch]
  HOSTCC  scripts/kconfig/lexer.lex.o
  HOSTCC  scripts/kconfig/menu.o
  HOSTCC  scripts/kconfig/parser.tab.o
  HOSTCC  scripts/kconfig/preprocess.o
  HOSTCC  scripts/kconfig/symbol.o
  HOSTCC  scripts/kconfig/util.o
  HOSTLD  scripts/kconfig/conf
#
# configuration written to .config
#
make[1]: Leaving directory '/kernel/build64'
++ nproc
+ make O=build64 -j48
make[1]: Entering directory '/kernel/build64'
  GEN     Makefile
  WRAP    arch/x86/include/generated/uapi/asm/bpf_perf_event.h
  WRAP    arch/x86/include/generated/uapi/asm/errno.h
  SYSHDR  arch/x86/include/generated/uapi/asm/unistd_32.h
  WRAP    arch/x86/include/generated/uapi/asm/fcntl.h
  GEN     arch/x86/include/generated/asm/orc_hash.h
  WRAP    arch/x86/include/generated/uapi/asm/ioctl.h
  SYSHDR  arch/x86/include/generated/uapi/asm/unistd_64.h
  WRAP    arch/x86/include/generated/uapi/asm/ioctls.h
  SYSHDR  arch/x86/include/generated/uapi/asm/unistd_x32.h
  WRAP    arch/x86/include/generated/uapi/asm/param.h
  WRAP    arch/x86/include/generated/uapi/asm/ipcbuf.h
  SYSTBL  arch/x86/include/generated/asm/syscalls_32.h
  SYSHDR  arch/x86/include/generated/asm/unistd_32_ia32.h
  WRAP    arch/x86/include/generated/uapi/asm/poll.h
  SYSHDR  arch/x86/include/generated/asm/unistd_64_x32.h
  SYSTBL  arch/x86/include/generated/asm/syscalls_64.h
  WRAP    arch/x86/include/generated/uapi/asm/resource.h
  WRAP    arch/x86/include/generated/uapi/asm/socket.h
  WRAP    arch/x86/include/generated/uapi/asm/sockios.h
  WRAP    arch/x86/include/generated/uapi/asm/termbits.h
  WRAP    arch/x86/include/generated/uapi/asm/termios.h
  WRAP    arch/x86/include/generated/uapi/asm/types.h
  WRAP    arch/x86/include/generated/asm/early_ioremap.h
  HOSTCC  arch/x86/tools/relocs_32.o
  WRAP    arch/x86/include/generated/asm/export.h
  HOSTCC  arch/x86/tools/relocs_64.o
  WRAP    arch/x86/include/generated/asm/irq_regs.h
  HOSTCC  arch/x86/tools/relocs_common.o
  WRAP    arch/x86/include/generated/asm/kmap_size.h
  WRAP    arch/x86/include/generated/asm/local64.h
  WRAP    arch/x86/include/generated/asm/mcs_spinlock.h
  WRAP    arch/x86/include/generated/asm/mmiowb.h
  WRAP    arch/x86/include/generated/asm/module.lds.h
  WRAP    arch/x86/include/generated/asm/rwonce.h
  WRAP    arch/x86/include/generated/asm/unaligned.h
  UPD     include/generated/uapi/linux/version.h
  UPD     include/config/kernel.release
  UPD     include/generated/compile.h
  HOSTCC  scripts/kallsyms
  HOSTCC  scripts/sorttable
  HOSTCC  scripts/unifdef
  UPD     include/generated/utsrelease.h
  HOSTCC  scripts/asn1_compiler
  DESCEND objtool
  HOSTCC  /kernel/build64/tools/objtool/fixdep.o
  HOSTLD  /kernel/build64/tools/objtool/fixdep-in.o
  LINK    /kernel/build64/tools/objtool/fixdep
  INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/exec-cmd.h
  HOSTLD  arch/x86/tools/relocs
  INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/pager.h
  INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/help.h
  INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/parse-options.h
  INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/run-command.h
  CC      /kernel/build64/tools/objtool/libsubcmd/exec-cmd.o
  CC      /kernel/build64/tools/objtool/libsubcmd/help.o
  CC      /kernel/build64/tools/objtool/libsubcmd/pager.o
  INSTALL libsubcmd_headers
  CC      /kernel/build64/tools/objtool/libsubcmd/parse-options.o
  CC      /kernel/build64/tools/objtool/libsubcmd/run-command.o
  CC      /kernel/build64/tools/objtool/libsubcmd/sigchain.o
  CC      /kernel/build64/tools/objtool/libsubcmd/subcmd-config.o
  CC      scripts/mod/empty.o
  HOSTCC  scripts/mod/mk_elfconfig
  CC      scripts/mod/devicetable-offsets.s
  HDRINST usr/include/video/edid.h
  HDRINST usr/include/video/sisfb.h
  HDRINST usr/include/video/uvesafb.h
  HDRINST usr/include/drm/amdgpu_drm.h
  HDRINST usr/include/drm/i915_drm.h
  HDRINST usr/include/drm/qaic_accel.h
  HDRINST usr/include/drm/vgem_drm.h
  HDRINST usr/include/drm/virtgpu_drm.h
  HDRINST usr/include/drm/xe_drm.h
  HDRINST usr/include/drm/omap_drm.h
  HDRINST usr/include/drm/radeon_drm.h
  HDRINST usr/include/drm/tegra_drm.h
  HDRINST usr/include/drm/drm_mode.h
  HDRINST usr/include/drm/ivpu_accel.h
  HDRINST usr/include/drm/drm_sarea.h
  HDRINST usr/include/drm/exynos_drm.h
  HDRINST usr/include/drm/v3d_drm.h
  HDRINST usr/include/drm/qxl_drm.h
  HDRINST usr/include/drm/drm_fourcc.h
  HDRINST usr/include/drm/nouveau_drm.h
  HDRINST usr/include/drm/habanalabs_accel.h
  HDRINST usr/include/drm/vmwgfx_drm.h
  HDRINST usr/include/drm/msm_drm.h
  HDRINST usr/include/drm/etnaviv_drm.h
  HDRINST usr/include/drm/vc4_drm.h
  HDRINST usr/include/drm/panfrost_drm.h
  HDRINST usr/include/drm/lima_drm.h
  HDRINST usr/include/drm/drm.h
  HDRINST usr/include/drm/armada_drm.h
  HDRINST usr/include/mtd/inftl-user.h
  HDRINST usr/include/mtd/nftl-user.h
  HDRINST usr/include/mtd/mtd-user.h
  HDRINST usr/include/mtd/ubi-user.h
  HDRINST usr/include/mtd/mtd-abi.h
  HDRINST usr/include/xen/gntdev.h
  HDRINST usr/include/xen/gntalloc.h
  HDRINST usr/include/xen/evtchn.h
  HDRINST usr/include/asm-generic/auxvec.h
  HDRINST usr/include/xen/privcmd.h
  HDRINST usr/include/asm-generic/bitsperlong.h
  HDRINST usr/include/asm-generic/posix_types.h
  HDRINST usr/include/asm-generic/ioctls.h
  HDRINST usr/include/asm-generic/mman.h
  HDRINST usr/include/asm-generic/shmbuf.h
  HDRINST usr/include/asm-generic/bpf_perf_event.h
  HDRINST usr/include/asm-generic/types.h
  HDRINST usr/include/asm-generic/poll.h
  HDRINST usr/include/asm-generic/msgbuf.h
  HDRINST usr/include/asm-generic/swab.h
  HDRINST usr/include/asm-generic/statfs.h
  HDRINST usr/include/asm-generic/unistd.h
  HDRINST usr/include/asm-generic/hugetlb_encode.h
  HDRINST usr/include/asm-generic/resource.h
  HDRINST usr/include/asm-generic/param.h
  HDRINST usr/include/asm-generic/termbits-common.h
  HDRINST usr/include/asm-generic/sockios.h
  HDRINST usr/include/asm-generic/kvm_para.h
  HDRINST usr/include/asm-generic/errno.h
  HDRINST usr/include/asm-generic/termios.h
  HDRINST usr/include/asm-generic/mman-common.h
  HDRINST usr/include/asm-generic/ioctl.h
  HDRINST usr/include/asm-generic/socket.h
  HDRINST usr/include/asm-generic/signal-defs.h
  HDRINST usr/include/asm-generic/termbits.h
  HDRINST usr/include/asm-generic/int-ll64.h
  HDRINST usr/include/asm-generic/signal.h
  HDRINST usr/include/asm-generic/siginfo.h
  HDRINST usr/include/asm-generic/stat.h
  HDRINST usr/include/asm-generic/int-l64.h
  HDRINST usr/include/asm-generic/errno-base.h
  HDRINST usr/include/asm-generic/fcntl.h
  HDRINST usr/include/asm-generic/setup.h
  HDRINST usr/include/asm-generic/ipcbuf.h
  HDRINST usr/include/asm-generic/sembuf.h
  HDRINST usr/include/asm-generic/ucontext.h
  HDRINST usr/include/rdma/mlx5_user_ioctl_cmds.h
  HDRINST usr/include/rdma/irdma-abi.h
  HDRINST usr/include/rdma/mana-abi.h
  HDRINST usr/include/rdma/hfi/hfi1_user.h
  HDRINST usr/include/rdma/hfi/hfi1_ioctl.h
  HDRINST usr/include/rdma/rdma_user_rxe.h
  HDRINST usr/include/rdma/rdma_user_ioctl.h
  HDRINST usr/include/rdma/mlx5_user_ioctl_verbs.h
  HDRINST usr/include/rdma/bnxt_re-abi.h
  HDRINST usr/include/rdma/hns-abi.h
  HDRINST usr/include/rdma/qedr-abi.h
  HDRINST usr/include/rdma/ib_user_ioctl_cmds.h
  HDRINST usr/include/rdma/vmw_pvrdma-abi.h
  UPD     scripts/mod/devicetable-offsets.h
  HDRINST usr/include/rdma/ib_user_sa.h
  HDRINST usr/include/rdma/ib_user_ioctl_verbs.h
  HDRINST usr/include/rdma/rvt-abi.h
  HDRINST usr/include/rdma/mlx5-abi.h
  HDRINST usr/include/rdma/rdma_netlink.h
  HDRINST usr/include/rdma/erdma-abi.h
  HDRINST usr/include/rdma/rdma_user_ioctl_cmds.h
  HDRINST usr/include/rdma/rdma_user_cm.h
  HDRINST usr/include/rdma/ib_user_verbs.h
  HDRINST usr/include/rdma/efa-abi.h
  HDRINST usr/include/rdma/siw-abi.h
  HDRINST usr/include/rdma/mlx4-abi.h
  HDRINST usr/include/rdma/mthca-abi.h
  HDRINST usr/include/rdma/ib_user_mad.h
  HDRINST usr/include/rdma/ocrdma-abi.h
  HDRINST usr/include/rdma/cxgb4-abi.h
  HDRINST usr/include/misc/xilinx_sdfec.h
  HDRINST usr/include/misc/uacce/hisi_qm.h
  HDRINST usr/include/misc/uacce/uacce.h
  HDRINST usr/include/misc/cxl.h
  HDRINST usr/include/misc/ocxl.h
  HDRINST usr/include/misc/fastrpc.h
  HDRINST usr/include/misc/pvpanic.h
  HDRINST usr/include/linux/i8k.h
  HDRINST usr/include/linux/acct.h
  HDRINST usr/include/linux/atmmpc.h
  HDRINST usr/include/linux/fs.h
  HDRINST usr/include/linux/cifs/cifs_mount.h
  HDRINST usr/include/linux/cifs/cifs_netlink.h
  HDRINST usr/include/linux/if_packet.h
  HDRINST usr/include/linux/route.h
  HDRINST usr/include/linux/patchkey.h
  HDRINST usr/include/linux/tc_ematch/tc_em_cmp.h
  HDRINST usr/include/linux/tc_ematch/tc_em_ipt.h
  HDRINST usr/include/linux/tc_ematch/tc_em_meta.h
  HDRINST usr/include/linux/tc_ematch/tc_em_nbyte.h
  HDRINST usr/include/linux/tc_ematch/tc_em_text.h
  HDRINST usr/include/linux/virtio_pmem.h
  HDRINST usr/include/linux/rkisp1-config.h
  HDRINST usr/include/linux/vhost.h
  HDRINST usr/include/linux/cec-funcs.h
  HDRINST usr/include/linux/ppdev.h
  HDRINST usr/include/linux/isdn/capicmd.h
  HDRINST usr/include/linux/virtio_fs.h
  HDRINST usr/include/linux/netfilter_ipv6.h
  HDRINST usr/include/linux/lirc.h
  HDRINST usr/include/linux/mroute6.h
  HDRINST usr/include/linux/nl80211-vnd-intel.h
  HDRINST usr/include/linux/ivtvfb.h
  HDRINST usr/include/linux/auxvec.h
  HDRINST usr/include/linux/dm-log-userspace.h
  HDRINST usr/include/linux/dccp.h
  HDRINST usr/include/linux/virtio_scmi.h
  HDRINST usr/include/linux/atmarp.h
  HDRINST usr/include/linux/arcfb.h
  HDRINST usr/include/linux/nbd-netlink.h
  HDRINST usr/include/linux/sched/types.h
  HDRINST usr/include/linux/tcp.h
  HDRINST usr/include/linux/neighbour.h
  HDRINST usr/include/linux/dlm_device.h
  HDRINST usr/include/linux/wmi.h
  HDRINST usr/include/linux/btrfs_tree.h
  HDRINST usr/include/linux/virtio_crypto.h
  HDRINST usr/include/linux/vbox_err.h
  HDRINST usr/include/linux/edd.h
  HDRINST usr/include/linux/loop.h
  HDRINST usr/include/linux/nvme_ioctl.h
  HDRINST usr/include/linux/mmtimer.h
  HDRINST usr/include/linux/if_pppol2tp.h
  HDRINST usr/include/linux/mtio.h
  HDRINST usr/include/linux/if_arcnet.h
  HDRINST usr/include/linux/romfs_fs.h
  MKELF   scripts/mod/elfconfig.h
  HDRINST usr/include/linux/posix_types.h
  HDRINST usr/include/linux/rtc.h
  HDRINST usr/include/linux/landlock.h
  HDRINST usr/include/linux/gpio.h
  HDRINST usr/include/linux/selinux_netlink.h
  HOSTCC  scripts/mod/modpost.o
  HOSTCC  scripts/mod/file2alias.o
  HOSTCC  scripts/mod/sumversion.o
  HDRINST usr/include/linux/pps.h
  HDRINST usr/include/linux/ndctl.h
  HDRINST usr/include/linux/virtio_gpu.h
  HDRINST usr/include/linux/android/binderfs.h
  HDRINST usr/include/linux/android/binder.h
  HDRINST usr/include/linux/virtio_vsock.h
  HDRINST usr/include/linux/sound.h
  HDRINST usr/include/linux/vtpm_proxy.h
  HDRINST usr/include/linux/nfs_fs.h
  HDRINST usr/include/linux/elf-fdpic.h
  HDRINST usr/include/linux/adfs_fs.h
  HDRINST usr/include/linux/target_core_user.h
  HDRINST usr/include/linux/netlink_diag.h
  HDRINST usr/include/linux/const.h
  HDRINST usr/include/linux/firewire-cdev.h
  HDRINST usr/include/linux/vdpa.h
  HDRINST usr/include/linux/if_infiniband.h
  HDRINST usr/include/linux/serial.h
  HDRINST usr/include/linux/iio/types.h
  HDRINST usr/include/linux/iio/buffer.h
  HDRINST usr/include/linux/iio/events.h
  HDRINST usr/include/linux/baycom.h
  HDRINST usr/include/linux/major.h
  HDRINST usr/include/linux/atmppp.h
  HDRINST usr/include/linux/ipv6_route.h
  HDRINST usr/include/linux/spi/spidev.h
  HDRINST usr/include/linux/spi/spi.h
  HDRINST usr/include/linux/virtio_ring.h
  HDRINST usr/include/linux/hdlc/ioctl.h
  HDRINST usr/include/linux/remoteproc_cdev.h
  HDRINST usr/include/linux/hyperv.h
  HDRINST usr/include/linux/rpl_iptunnel.h
  HDRINST usr/include/linux/sync_file.h
  HDRINST usr/include/linux/igmp.h
  HDRINST usr/include/linux/v4l2-dv-timings.h
  HDRINST usr/include/linux/virtio_i2c.h
  HDRINST usr/include/linux/xfrm.h
  HDRINST usr/include/linux/capability.h
  HDRINST usr/include/linux/gtp.h
  HDRINST usr/include/linux/xdp_diag.h
  HDRINST usr/include/linux/pkt_cls.h
  HDRINST usr/include/linux/suspend_ioctls.h
  HDRINST usr/include/linux/vt.h
  HDRINST usr/include/linux/loadpin.h
  HDRINST usr/include/linux/dlm_plock.h
  HDRINST usr/include/linux/fb.h
  HDRINST usr/include/linux/max2175.h
  HDRINST usr/include/linux/sunrpc/debug.h
  HDRINST usr/include/linux/gsmmux.h
  HDRINST usr/include/linux/watchdog.h
  HDRINST usr/include/linux/vhost_types.h
  HDRINST usr/include/linux/vduse.h
  HDRINST usr/include/linux/ila.h
  HDRINST usr/include/linux/tdx-guest.h
  HDRINST usr/include/linux/close_range.h
  HDRINST usr/include/linux/ivtv.h
  HDRINST usr/include/linux/cryptouser.h
  HDRINST usr/include/linux/netfilter/xt_string.h
  HDRINST usr/include/linux/netfilter/nfnetlink_compat.h
  HDRINST usr/include/linux/netfilter/nf_nat.h
  HDRINST usr/include/linux/netfilter/xt_recent.h
  HDRINST usr/include/linux/netfilter/xt_addrtype.h
  HDRINST usr/include/linux/netfilter/nf_conntrack_tcp.h
  HDRINST usr/include/linux/netfilter/xt_MARK.h
  HDRINST usr/include/linux/netfilter/xt_SYNPROXY.h
  HDRINST usr/include/linux/netfilter/xt_multiport.h
  HDRINST usr/include/linux/netfilter/nfnetlink.h
  HDRINST usr/include/linux/netfilter/xt_cgroup.h
  HDRINST usr/include/linux/netfilter/nf_synproxy.h
  HDRINST usr/include/linux/netfilter/xt_TCPOPTSTRIP.h
  HDRINST usr/include/linux/netfilter/nfnetlink_log.h
  HDRINST usr/include/linux/netfilter/xt_TPROXY.h
  HDRINST usr/include/linux/netfilter/xt_u32.h
  HDRINST usr/include/linux/netfilter/nfnetlink_osf.h
  HDRINST usr/include/linux/netfilter/xt_ecn.h
  HDRINST usr/include/linux/netfilter/xt_esp.h
  HDRINST usr/include/linux/netfilter/nfnetlink_hook.h
  HDRINST usr/include/linux/netfilter/xt_mac.h
  HDRINST usr/include/linux/netfilter/xt_comment.h
  HDRINST usr/include/linux/netfilter/xt_NFQUEUE.h
  HDRINST usr/include/linux/netfilter/xt_osf.h
  HDRINST usr/include/linux/netfilter/xt_hashlimit.h
  HDRINST usr/include/linux/netfilter/nf_conntrack_sctp.h
  HDRINST usr/include/linux/netfilter/xt_socket.h
  HDRINST usr/include/linux/netfilter/xt_connmark.h
  HDRINST usr/include/linux/netfilter/xt_sctp.h
  HDRINST usr/include/linux/netfilter/xt_tcpudp.h
  HDRINST usr/include/linux/netfilter/xt_DSCP.h
  HDRINST usr/include/linux/netfilter/xt_time.h
  HDRINST usr/include/linux/netfilter/xt_IDLETIMER.h
  HDRINST usr/include/linux/netfilter/xt_policy.h
  HDRINST usr/include/linux/netfilter/xt_rpfilter.h
  HDRINST usr/include/linux/netfilter/xt_nfacct.h
  HDRINST usr/include/linux/netfilter/xt_SECMARK.h
  HDRINST usr/include/linux/netfilter/xt_length.h
  HDRINST usr/include/linux/netfilter/nfnetlink_cthelper.h
  HDRINST usr/include/linux/netfilter/xt_quota.h
  HDRINST usr/include/linux/netfilter/xt_CLASSIFY.h
  HDRINST usr/include/linux/netfilter/xt_ipcomp.h
  HDRINST usr/include/linux/netfilter/xt_iprange.h
  HDRINST usr/include/linux/netfilter/xt_bpf.h
  HDRINST usr/include/linux/netfilter/xt_LOG.h
  HDRINST usr/include/linux/netfilter/xt_rateest.h
  HDRINST usr/include/linux/netfilter/xt_CONNSECMARK.h
  HDRINST usr/include/linux/netfilter/xt_HMARK.h
  HDRINST usr/include/linux/netfilter/xt_CONNMARK.h
  HDRINST usr/include/linux/netfilter/xt_pkttype.h
  HDRINST usr/include/linux/netfilter/xt_ipvs.h
  HDRINST usr/include/linux/netfilter/xt_devgroup.h
  HDRINST usr/include/linux/netfilter/xt_AUDIT.h
  HDRINST usr/include/linux/netfilter/xt_realm.h
  HDRINST usr/include/linux/netfilter/nf_conntrack_common.h
  HDRINST usr/include/linux/netfilter/xt_set.h
  HDRINST usr/include/linux/netfilter/xt_LED.h
  HDRINST usr/include/linux/netfilter/xt_connlabel.h
  HDRINST usr/include/linux/netfilter/xt_owner.h
  HDRINST usr/include/linux/netfilter/xt_dccp.h
  HDRINST usr/include/linux/netfilter/xt_limit.h
  HDRINST usr/include/linux/netfilter/xt_conntrack.h
  HDRINST usr/include/linux/netfilter/xt_TEE.h
  HDRINST usr/include/linux/netfilter/xt_RATEEST.h
  HDRINST usr/include/linux/netfilter/xt_connlimit.h
  HDRINST usr/include/linux/netfilter/ipset/ip_set.h
  HDRINST usr/include/linux/netfilter/ipset/ip_set_list.h
  HDRINST usr/include/linux/netfilter/ipset/ip_set_hash.h
  HDRINST usr/include/linux/netfilter/ipset/ip_set_bitmap.h
  HDRINST usr/include/linux/netfilter/x_tables.h
  HDRINST usr/include/linux/netfilter/xt_dscp.h
  HDRINST usr/include/linux/netfilter/nf_conntrack_ftp.h
  HDRINST usr/include/linux/netfilter/xt_cluster.h
  HDRINST usr/include/linux/netfilter/nf_conntrack_tuple_common.h
  HDRINST usr/include/linux/netfilter/nf_log.h
  HDRINST usr/include/linux/netfilter/xt_tcpmss.h
  HDRINST usr/include/linux/netfilter/xt_NFLOG.h
  HDRINST usr/include/linux/netfilter/xt_l2tp.h
  HDRINST usr/include/linux/netfilter/xt_helper.h
  HDRINST usr/include/linux/netfilter/xt_statistic.h
  HDRINST usr/include/linux/netfilter/nfnetlink_queue.h
  HDRINST usr/include/linux/netfilter/nfnetlink_cttimeout.h
  HDRINST usr/include/linux/netfilter/xt_CT.h
  HDRINST usr/include/linux/netfilter/xt_CHECKSUM.h
  HDRINST usr/include/linux/netfilter/xt_connbytes.h
  HDRINST usr/include/linux/netfilter/xt_state.h
  HDRINST usr/include/linux/netfilter/nf_tables.h
  HDRINST usr/include/linux/netfilter/xt_mark.h
  HDRINST usr/include/linux/netfilter/xt_cpu.h
  HDRINST usr/include/linux/netfilter/nf_tables_compat.h
  HDRINST usr/include/linux/netfilter/xt_physdev.h
  HDRINST usr/include/linux/netfilter/nfnetlink_conntrack.h
  HDRINST usr/include/linux/netfilter/nfnetlink_acct.h
  HDRINST usr/include/linux/netfilter/xt_TCPMSS.h
  HDRINST usr/include/linux/tty_flags.h
  HDRINST usr/include/linux/if_phonet.h
  HDRINST usr/include/linux/vm_sockets.h
  HDRINST usr/include/linux/elf-em.h
  HDRINST usr/include/linux/dlmconstants.h
  HDRINST usr/include/linux/bsg.h
  HDRINST usr/include/linux/matroxfb.h
  HDRINST usr/include/linux/sysctl.h
  HDRINST usr/include/linux/unix_diag.h
  HDRINST usr/include/linux/pcitest.h
  HDRINST usr/include/linux/mman.h
  HDRINST usr/include/linux/if_plip.h
  HDRINST usr/include/linux/virtio_balloon.h
  HDRINST usr/include/linux/pidfd.h
  HDRINST usr/include/linux/f2fs.h
  HDRINST usr/include/linux/x25.h
  HDRINST usr/include/linux/if_cablemodem.h
  HDRINST usr/include/linux/utsname.h
  HDRINST usr/include/linux/counter.h
  HDRINST usr/include/linux/atm_tcp.h
  HDRINST usr/include/linux/atalk.h
  HDRINST usr/include/linux/virtio_rng.h
  HDRINST usr/include/linux/vboxguest.h
  HDRINST usr/include/linux/bpf_perf_event.h
  HDRINST usr/include/linux/ipmi_ssif_bmc.h
  HDRINST usr/include/linux/nfs_mount.h
  HDRINST usr/include/linux/sonet.h
  HDRINST usr/include/linux/netfilter.h
  HDRINST usr/include/linux/keyctl.h
  HDRINST usr/include/linux/nl80211.h
  HDRINST usr/include/linux/misc/bcm_vk.h
  HDRINST usr/include/linux/audit.h
  HDRINST usr/include/linux/tipc_config.h
  HDRINST usr/include/linux/tipc_sockets_diag.h
  HDRINST usr/include/linux/futex.h
  HDRINST usr/include/linux/sev-guest.h
  HDRINST usr/include/linux/ublk_cmd.h
  HDRINST usr/include/linux/types.h
  HDRINST usr/include/linux/virtio_input.h
  HDRINST usr/include/linux/if_slip.h
  HDRINST usr/include/linux/personality.h
  HDRINST usr/include/linux/openat2.h
  HDRINST usr/include/linux/poll.h
  HDRINST usr/include/linux/posix_acl.h
  HDRINST usr/include/linux/smc_diag.h
  HDRINST usr/include/linux/snmp.h
  HDRINST usr/include/linux/errqueue.h
  HDRINST usr/include/linux/if_tunnel.h
  HDRINST usr/include/linux/fanotify.h
  HDRINST usr/include/linux/kernel.h
  HDRINST usr/include/linux/rtnetlink.h
  HDRINST usr/include/linux/rpl.h
  HDRINST usr/include/linux/memfd.h
  HDRINST usr/include/linux/serial_core.h
  HDRINST usr/include/linux/dns_resolver.h
  HDRINST usr/include/linux/pr.h
  HDRINST usr/include/linux/atm_eni.h
  HDRINST usr/include/linux/lp.h
  HDRINST usr/include/linux/virtio_mem.h
  HDRINST usr/include/linux/ultrasound.h
  HDRINST usr/include/linux/sctp.h
  HDRINST usr/include/linux/uio.h
  HDRINST usr/include/linux/tcp_metrics.h
  HDRINST usr/include/linux/wwan.h
  HDRINST usr/include/linux/atmbr2684.h
  HDRINST usr/include/linux/in_route.h
  HDRINST usr/include/linux/qemu_fw_cfg.h
  HDRINST usr/include/linux/if_macsec.h
  HDRINST usr/include/linux/usb/charger.h
  HDRINST usr/include/linux/usb/g_uvc.h
  HDRINST usr/include/linux/usb/gadgetfs.h
  HDRINST usr/include/linux/usb/raw_gadget.h
  HDRINST usr/include/linux/usb/cdc-wdm.h
  HDRINST usr/include/linux/usb/g_printer.h
  HDRINST usr/include/linux/usb/midi.h
  HDRINST usr/include/linux/usb/tmc.h
  HDRINST usr/include/linux/usb/video.h
  HDRINST usr/include/linux/usb/functionfs.h
  HDRINST usr/include/linux/usb/audio.h
  HDRINST usr/include/linux/usb/ch11.h
  HDRINST usr/include/linux/usb/ch9.h
  HDRINST usr/include/linux/usb/cdc.h
  HDRINST usr/include/linux/jffs2.h
  HDRINST usr/include/linux/ax25.h
  HDRINST usr/include/linux/auto_fs.h
  HDRINST usr/include/linux/tiocl.h
  HDRINST usr/include/linux/scc.h
  HDRINST usr/include/linux/psci.h
  HDRINST usr/include/linux/swab.h
  HDRINST usr/include/linux/cec.h
  HDRINST usr/include/linux/kfd_ioctl.h
  HDRINST usr/include/linux/smc.h
  HDRINST usr/include/linux/qrtr.h
  HDRINST usr/include/linux/screen_info.h
  HDRINST usr/include/linux/nfsacl.h
  HDRINST usr/include/linux/seg6_hmac.h
  HDRINST usr/include/linux/gameport.h
  HDRINST usr/include/linux/wireless.h
  HDRINST usr/include/linux/fdreg.h
  HDRINST usr/include/linux/cciss_defs.h
  HDRINST usr/include/linux/serial_reg.h
  HDRINST usr/include/linux/perf_event.h
  HDRINST usr/include/linux/in6.h
  HDRINST usr/include/linux/hid.h
  HDRINST usr/include/linux/netlink.h
  HDRINST usr/include/linux/fuse.h
  HDRINST usr/include/linux/magic.h
  HDRINST usr/include/linux/ioam6_iptunnel.h
  HDRINST usr/include/linux/stm.h
  HDRINST usr/include/linux/vsockmon.h
  HDRINST usr/include/linux/seg6.h
  HDRINST usr/include/linux/idxd.h
  HDRINST usr/include/linux/nitro_enclaves.h
  HDRINST usr/include/linux/ptrace.h
  HDRINST usr/include/linux/ioam6_genl.h
  HDRINST usr/include/linux/qnx4_fs.h
  HDRINST usr/include/linux/fsl_mc.h
  HDRINST usr/include/linux/net_tstamp.h
  HDRINST usr/include/linux/msg.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_TTL.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_ttl.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_ah.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_ECN.h
  HDRINST usr/include/linux/netfilter_ipv4/ip_tables.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_ecn.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_REJECT.h
  HDRINST usr/include/linux/netfilter_ipv4/ipt_LOG.h
  HDRINST usr/include/linux/sem.h
  HDRINST usr/include/linux/net_namespace.h
  HDRINST usr/include/linux/radeonfb.h
  HDRINST usr/include/linux/tee.h
  HDRINST usr/include/linux/udp.h
  HDRINST usr/include/linux/virtio_bt.h
  HDRINST usr/include/linux/v4l2-subdev.h
  HDRINST usr/include/linux/posix_acl_xattr.h
  HDRINST usr/include/linux/v4l2-mediabus.h
  HDRINST usr/include/linux/atmapi.h
  HDRINST usr/include/linux/raid/md_p.h
  HDRINST usr/include/linux/raid/md_u.h
  HDRINST usr/include/linux/zorro_ids.h
  HDRINST usr/include/linux/nbd.h
  HDRINST usr/include/linux/isst_if.h
  HDRINST usr/include/linux/rxrpc.h
  HDRINST usr/include/linux/unistd.h
  HDRINST usr/include/linux/if_arp.h
  HDRINST usr/include/linux/atm_zatm.h
  HDRINST usr/include/linux/io_uring.h
  HDRINST usr/include/linux/if_fddi.h
  HDRINST usr/include/linux/bpqether.h
  HDRINST usr/include/linux/sysinfo.h
  HDRINST usr/include/linux/auto_dev-ioctl.h
  HDRINST usr/include/linux/nfs4_mount.h
  HDRINST usr/include/linux/keyboard.h
  HDRINST usr/include/linux/virtio_mmio.h
  HDRINST usr/include/linux/input.h
  HDRINST usr/include/linux/qnxtypes.h
  HDRINST usr/include/linux/mdio.h
  HDRINST usr/include/linux/lwtunnel.h
  HDRINST usr/include/linux/gfs2_ondisk.h
  HDRINST usr/include/linux/nfs4.h
  HDRINST usr/include/linux/ptp_clock.h
  HDRINST usr/include/linux/nubus.h
  HDRINST usr/include/linux/if_bonding.h
  HDRINST usr/include/linux/kcov.h
  HDRINST usr/include/linux/fadvise.h
  HDRINST usr/include/linux/taskstats.h
  HDRINST usr/include/linux/veth.h
  HDRINST usr/include/linux/atm.h
  HDRINST usr/include/linux/ipmi.h
  HDRINST usr/include/linux/kdev_t.h
  HDRINST usr/include/linux/mount.h
  HDRINST usr/include/linux/shm.h
  HDRINST usr/include/linux/resource.h
  HDRINST usr/include/linux/prctl.h
  HDRINST usr/include/linux/watch_queue.h
  HDRINST usr/include/linux/sched.h
  HDRINST usr/include/linux/phonet.h
  HDRINST usr/include/linux/random.h
  HDRINST usr/include/linux/tty.h
  HDRINST usr/include/linux/apm_bios.h
  HDRINST usr/include/linux/fd.h
  HDRINST usr/include/linux/um_timetravel.h
  HDRINST usr/include/linux/tls.h
  HDRINST usr/include/linux/rpmsg_types.h
  HDRINST usr/include/linux/pfrut.h
  HDRINST usr/include/linux/mei.h
  HDRINST usr/include/linux/fsi.h
  HDRINST usr/include/linux/rds.h
  HDRINST usr/include/linux/if_x25.h
  HDRINST usr/include/linux/param.h
  HDRINST usr/include/linux/netdevice.h
  HDRINST usr/include/linux/binfmts.h
  HDRINST usr/include/linux/if_pppox.h
  HDRINST usr/include/linux/sockios.h
  HDRINST usr/include/linux/kcm.h
  HDRINST usr/include/linux/virtio_9p.h
  HDRINST usr/include/linux/genwqe/genwqe_card.h
  HDRINST usr/include/linux/if_tun.h
  HDRINST usr/include/linux/ext4.h
  HDRINST usr/include/linux/if_ether.h
  HDRINST usr/include/linux/kvm_para.h
  HDRINST usr/include/linux/kernel-page-flags.h
  HDRINST usr/include/linux/cdrom.h
  HDRINST usr/include/linux/un.h
  HDRINST usr/include/linux/module.h
  HDRINST usr/include/linux/mqueue.h
  HDRINST usr/include/linux/a.out.h
  HDRINST usr/include/linux/input-event-codes.h
  HDRINST usr/include/linux/coda.h
  HDRINST usr/include/linux/rio_mport_cdev.h
  HDRINST usr/include/linux/ipsec.h
  HDRINST usr/include/linux/blkpg.h
  HDRINST usr/include/linux/blkzoned.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_arpreply.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_redirect.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_nflog.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_802_3.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_nat.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_mark_m.h
  HDRINST usr/include/linux/netfilter_bridge/ebtables.h
  LD      /kernel/build64/tools/objtool/libsubcmd/libsubcmd-in.o
  HDRINST usr/include/linux/netfilter_bridge/ebt_vlan.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_limit.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_log.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_stp.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_pkttype.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_ip.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_ip6.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_arp.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_mark_t.h
  HDRINST usr/include/linux/netfilter_bridge/ebt_among.h
  HDRINST usr/include/linux/reiserfs_fs.h
  HDRINST usr/include/linux/cciss_ioctl.h
  HDRINST usr/include/linux/fsmap.h
  HDRINST usr/include/linux/smiapp.h
  HDRINST usr/include/linux/switchtec_ioctl.h
  HDRINST usr/include/linux/atmdev.h
  HDRINST usr/include/linux/hpet.h
  HDRINST usr/include/linux/virtio_config.h
  HDRINST usr/include/linux/string.h
  HDRINST usr/include/linux/kfd_sysfs.h
  HDRINST usr/include/linux/inet_diag.h
  HDRINST usr/include/linux/netdev.h
  HDRINST usr/include/linux/xattr.h
  HDRINST usr/include/linux/iommufd.h
  HDRINST usr/include/linux/user_events.h
  HDRINST usr/include/linux/errno.h
  HDRINST usr/include/linux/icmp.h
  HDRINST usr/include/linux/i2o-dev.h
  HDRINST usr/include/linux/pg.h
  HDRINST usr/include/linux/if_bridge.h
  HDRINST usr/include/linux/thermal.h
  HDRINST usr/include/linux/uinput.h
  HDRINST usr/include/linux/handshake.h
  HDRINST usr/include/linux/dqblk_xfs.h
  AR      /kernel/build64/tools/objtool/libsubcmd/libsubcmd.a
  HDRINST usr/include/linux/v4l2-common.h
  HDRINST usr/include/linux/nvram.h
  HDRINST usr/include/linux/if_vlan.h
  HDRINST usr/include/linux/uhid.h
  HDRINST usr/include/linux/omap3isp.h
  HDRINST usr/include/linux/rose.h
  HDRINST usr/include/linux/phantom.h
  HDRINST usr/include/linux/ipmi_msgdefs.h
  HDRINST usr/include/linux/bcm933xx_hcs.h
  HDRINST usr/include/linux/bpf.h
  HDRINST usr/include/linux/mempolicy.h
  HDRINST usr/include/linux/efs_fs_sb.h
  HDRINST usr/include/linux/nexthop.h
  HDRINST usr/include/linux/net_dropmon.h
  HDRINST usr/include/linux/surface_aggregator/cdev.h
  HDRINST usr/include/linux/surface_aggregator/dtx.h
  HDRINST usr/include/linux/net.h
  HDRINST usr/include/linux/mii.h
  HDRINST usr/include/linux/virtio_pcidev.h
  HDRINST usr/include/linux/termios.h
  HDRINST usr/include/linux/cgroupstats.h
  HDRINST usr/include/linux/mpls.h
  HDRINST usr/include/linux/iommu.h
  HDRINST usr/include/linux/toshiba.h
  HDRINST usr/include/linux/virtio_scsi.h
  HDRINST usr/include/linux/zorro.h
  HDRINST usr/include/linux/chio.h
  HDRINST usr/include/linux/pkt_sched.h
  HDRINST usr/include/linux/cramfs_fs.h
  HDRINST usr/include/linux/nfs3.h
  HDRINST usr/include/linux/vfio_ccw.h
  HDRINST usr/include/linux/atm_nicstar.h
  HDRINST usr/include/linux/ncsi.h
  HDRINST usr/include/linux/virtio_net.h
  HDRINST usr/include/linux/ioctl.h
  HDRINST usr/include/linux/stddef.h
  HDRINST usr/include/linux/limits.h
  HDRINST usr/include/linux/ipmi_bmc.h
  HDRINST usr/include/linux/netfilter_arp.h
  HDRINST usr/include/linux/if_addr.h
  HDRINST usr/include/linux/rpmsg.h
  HDRINST usr/include/linux/media-bus-format.h
  HDRINST usr/include/linux/kernelcapi.h
  HDRINST usr/include/linux/ppp_defs.h
  HDRINST usr/include/linux/ethtool.h
  HDRINST usr/include/linux/aspeed-video.h
  HDRINST usr/include/linux/hdlc.h
  HDRINST usr/include/linux/fscrypt.h
  HDRINST usr/include/linux/batadv_packet.h
  HDRINST usr/include/linux/uuid.h
  HDRINST usr/include/linux/capi.h
  HDRINST usr/include/linux/mptcp.h
  HDRINST usr/include/linux/virtio_console.h
  HDRINST usr/include/linux/hidraw.h
  HDRINST usr/include/linux/irqnr.h
  HDRINST usr/include/linux/coresight-stm.h
  HDRINST usr/include/linux/cxl_mem.h
  HDRINST usr/include/linux/iso_fs.h
  HDRINST usr/include/linux/virtio_blk.h
  HDRINST usr/include/linux/udf_fs_i.h
  HDRINST usr/include/linux/coff.h
  HDRINST usr/include/linux/dma-buf.h
  HDRINST usr/include/linux/ife.h
  HDRINST usr/include/linux/agpgart.h
  HDRINST usr/include/linux/socket.h
  HDRINST usr/include/linux/nilfs2_ondisk.h
  HDRINST usr/include/linux/connector.h
  CC      /kernel/build64/tools/objtool/weak.o
  HDRINST usr/include/linux/auto_fs4.h
  CC      /kernel/build64/tools/objtool/check.o
  HDRINST usr/include/linux/bt-bmc.h
  HDRINST usr/include/linux/map_to_7segment.h
  CC      /kernel/build64/tools/objtool/special.o
  HDRINST usr/include/linux/tc_act/tc_skbedit.h
  HDRINST usr/include/linux/tc_act/tc_ctinfo.h
  HDRINST usr/include/linux/tc_act/tc_defact.h
  MKDIR   /kernel/build64/tools/objtool/arch/x86/
  CC      /kernel/build64/tools/objtool/builtin-check.o
  HDRINST usr/include/linux/tc_act/tc_gact.h
  HDRINST usr/include/linux/tc_act/tc_vlan.h
  HDRINST usr/include/linux/tc_act/tc_skbmod.h
  HDRINST usr/include/linux/tc_act/tc_sample.h
  HDRINST usr/include/linux/tc_act/tc_tunnel_key.h
  MKDIR   /kernel/build64/tools/objtool/arch/x86/lib/
  HDRINST usr/include/linux/tc_act/tc_gate.h
  CC      /kernel/build64/tools/objtool/elf.o
  HDRINST usr/include/linux/tc_act/tc_mirred.h
  CC      /kernel/build64/tools/objtool/arch/x86/special.o
  CC      /kernel/build64/tools/objtool/objtool.o
  HDRINST usr/include/linux/tc_act/tc_nat.h
  HDRINST usr/include/linux/tc_act/tc_csum.h
  HDRINST usr/include/linux/tc_act/tc_connmark.h
  GEN     /kernel/build64/tools/objtool/arch/x86/lib/inat-tables.c
  CC      /kernel/build64/tools/objtool/orc_gen.o
  HDRINST usr/include/linux/tc_act/tc_ife.h
  CC      /kernel/build64/tools/objtool/orc_dump.o
  HDRINST usr/include/linux/tc_act/tc_mpls.h
  HDRINST usr/include/linux/tc_act/tc_ct.h
  HDRINST usr/include/linux/tc_act/tc_pedit.h
  HDRINST usr/include/linux/tc_act/tc_bpf.h
  HDRINST usr/include/linux/tc_act/tc_ipt.h
  CC      /kernel/build64/tools/objtool/libstring.o
  HDRINST usr/include/linux/netrom.h
  HDRINST usr/include/linux/joystick.h
  CC      /kernel/build64/tools/objtool/libctype.o
  HDRINST usr/include/linux/falloc.h
  HDRINST usr/include/linux/cycx_cfm.h
  HDRINST usr/include/linux/omapfb.h
  HDRINST usr/include/linux/msdos_fs.h
  HDRINST usr/include/linux/virtio_types.h
  CC      /kernel/build64/tools/objtool/str_error_r.o
  CC      /kernel/build64/tools/objtool/librbtree.o
  HDRINST usr/include/linux/mroute.h
  HDRINST usr/include/linux/psample.h
  HDRINST usr/include/linux/ipv6.h
  HDRINST usr/include/linux/dw100.h
  HDRINST usr/include/linux/psp-sev.h
  HDRINST usr/include/linux/vfio.h
  HDRINST usr/include/linux/if_ppp.h
  HDRINST usr/include/linux/byteorder/big_endian.h
  HDRINST usr/include/linux/byteorder/little_endian.h
  HDRINST usr/include/linux/comedi.h
  HDRINST usr/include/linux/scif_ioctl.h
  HDRINST usr/include/linux/timerfd.h
  HDRINST usr/include/linux/time_types.h
  HDRINST usr/include/linux/firewire-constants.h
  HDRINST usr/include/linux/virtio_snd.h
  HDRINST usr/include/linux/ppp-ioctl.h
  HDRINST usr/include/linux/fib_rules.h
  HDRINST usr/include/linux/gen_stats.h
  HDRINST usr/include/linux/virtio_iommu.h
  HDRINST usr/include/linux/genetlink.h
  HDRINST usr/include/linux/uvcvideo.h
  HDRINST usr/include/linux/pfkeyv2.h
  HDRINST usr/include/linux/soundcard.h
  HDRINST usr/include/linux/times.h
  HDRINST usr/include/linux/nfc.h
  HDRINST usr/include/linux/affs_hardblocks.h
  HDRINST usr/include/linux/nilfs2_api.h
  HDRINST usr/include/linux/rseq.h
  HDRINST usr/include/linux/caif/caif_socket.h
  HDRINST usr/include/linux/caif/if_caif.h
  HDRINST usr/include/linux/i2c-dev.h
  HDRINST usr/include/linux/cuda.h
  HDRINST usr/include/linux/mei_uuid.h
  HDRINST usr/include/linux/cn_proc.h
  HDRINST usr/include/linux/parport.h
  HDRINST usr/include/linux/v4l2-controls.h
  HDRINST usr/include/linux/hsi/cs-protocol.h
  HDRINST usr/include/linux/hsi/hsi_char.h
  HDRINST usr/include/linux/seg6_genl.h
  HDRINST usr/include/linux/am437x-vpfe.h
  HDRINST usr/include/linux/amt.h
  HDRINST usr/include/linux/netconf.h
  HDRINST usr/include/linux/erspan.h
  HDRINST usr/include/linux/nsfs.h
  HDRINST usr/include/linux/xilinx-v4l2-controls.h
  HDRINST usr/include/linux/aspeed-p2a-ctrl.h
  HDRINST usr/include/linux/vfio_zdev.h
  HDRINST usr/include/linux/serio.h
  HDRINST usr/include/linux/acrn.h
  HDRINST usr/include/linux/nfs2.h
  HDRINST usr/include/linux/virtio_pci.h
  HDRINST usr/include/linux/ipc.h
  HDRINST usr/include/linux/ethtool_netlink.h
  HDRINST usr/include/linux/kd.h
  HDRINST usr/include/linux/elf.h
  HDRINST usr/include/linux/videodev2.h
  HDRINST usr/include/linux/if_alg.h
  HDRINST usr/include/linux/sonypi.h
  HDRINST usr/include/linux/fsverity.h
  HDRINST usr/include/linux/if.h
  HDRINST usr/include/linux/btrfs.h
  HDRINST usr/include/linux/vm_sockets_diag.h
  HDRINST usr/include/linux/netfilter_bridge.h
  HDRINST usr/include/linux/packet_diag.h
  HDRINST usr/include/linux/netfilter_ipv4.h
  HDRINST usr/include/linux/kvm.h
  HDRINST usr/include/linux/pci.h
  CC      /kernel/build64/tools/objtool/arch/x86/decode.o
  HDRINST usr/include/linux/if_addrlabel.h
  HDRINST usr/include/linux/hdlcdrv.h
  HDRINST usr/include/linux/cfm_bridge.h
  HDRINST usr/include/linux/fiemap.h
  HDRINST usr/include/linux/dm-ioctl.h
  HDRINST usr/include/linux/aspeed-lpc-ctrl.h
  HDRINST usr/include/linux/atmioc.h
  HDRINST usr/include/linux/dlm.h
  HDRINST usr/include/linux/pci_regs.h
  HDRINST usr/include/linux/cachefiles.h
  HDRINST usr/include/linux/membarrier.h
  HDRINST usr/include/linux/nfs_idmap.h
  HDRINST usr/include/linux/ip.h
  HDRINST usr/include/linux/atm_he.h
  HDRINST usr/include/linux/nfsd/export.h
  HDRINST usr/include/linux/nfsd/stats.h
  HDRINST usr/include/linux/nfsd/debug.h
  HDRINST usr/include/linux/nfsd/cld.h
  HDRINST usr/include/linux/ip_vs.h
  HDRINST usr/include/linux/vmcore.h
  HDRINST usr/include/linux/vbox_vmmdev_types.h
  HDRINST usr/include/linux/dvb/osd.h
  HDRINST usr/include/linux/dvb/dmx.h
  HDRINST usr/include/linux/dvb/net.h
  HDRINST usr/include/linux/dvb/frontend.h
  HDRINST usr/include/linux/dvb/ca.h
  HDRINST usr/include/linux/dvb/version.h
  HDRINST usr/include/linux/dvb/video.h
  HDRINST usr/include/linux/dvb/audio.h
  HDRINST usr/include/linux/nfs.h
  HDRINST usr/include/linux/if_link.h
  HDRINST usr/include/linux/wait.h
  HDRINST usr/include/linux/icmpv6.h
  HDRINST usr/include/linux/media.h
  HDRINST usr/include/linux/seg6_local.h
  HDRINST usr/include/linux/openvswitch.h
  HDRINST usr/include/linux/atmsap.h
  HDRINST usr/include/linux/bpfilter.h
  HDRINST usr/include/linux/fpga-dfl.h
  HDRINST usr/include/linux/userio.h
  HDRINST usr/include/linux/signal.h
  HDRINST usr/include/linux/map_to_14segment.h
  HDRINST usr/include/linux/hdreg.h
  HDRINST usr/include/linux/utime.h
  HDRINST usr/include/linux/usbdevice_fs.h
  HDRINST usr/include/linux/timex.h
  HDRINST usr/include/linux/if_fc.h
  HDRINST usr/include/linux/reiserfs_xattr.h
  HDRINST usr/include/linux/hw_breakpoint.h
  HDRINST usr/include/linux/quota.h
  HDRINST usr/include/linux/ioprio.h
  HDRINST usr/include/linux/eventpoll.h
  HDRINST usr/include/linux/atmclip.h
  HDRINST usr/include/linux/can.h
  HDRINST usr/include/linux/if_team.h
  HDRINST usr/include/linux/usbip.h
  HDRINST usr/include/linux/stat.h
  HDRINST usr/include/linux/fou.h
  HDRINST usr/include/linux/hash_info.h
  HDRINST usr/include/linux/ppp-comp.h
  HDRINST usr/include/linux/ip6_tunnel.h
  HDRINST usr/include/linux/tipc_netlink.h
  HDRINST usr/include/linux/in.h
  HDRINST usr/include/linux/wireguard.h
  HDRINST usr/include/linux/btf.h
  HDRINST usr/include/linux/batman_adv.h
  HDRINST usr/include/linux/fcntl.h
  HDRINST usr/include/linux/if_ltalk.h
  HDRINST usr/include/linux/i2c.h
  HDRINST usr/include/linux/atm_idt77105.h
  HDRINST usr/include/linux/kexec.h
  HDRINST usr/include/linux/arm_sdei.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6_tables.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_ah.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_NPT.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_rt.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_REJECT.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_opts.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_srh.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_LOG.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_mh.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_HL.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_hl.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_frag.h
  HDRINST usr/include/linux/netfilter_ipv6/ip6t_ipv6header.h
  HDRINST usr/include/linux/minix_fs.h
  HDRINST usr/include/linux/aio_abi.h
  HDRINST usr/include/linux/pktcdvd.h
  HDRINST usr/include/linux/libc-compat.h
  HDRINST usr/include/linux/atmlec.h
  HDRINST usr/include/linux/signalfd.h
  HDRINST usr/include/linux/bpf_common.h
  HDRINST usr/include/linux/seg6_iptunnel.h
  HDRINST usr/include/linux/synclink.h
  HDRINST usr/include/linux/mpls_iptunnel.h
  HDRINST usr/include/linux/mctp.h
  HDRINST usr/include/linux/if_xdp.h
  HDRINST usr/include/linux/llc.h
  HDRINST usr/include/linux/atmsvc.h
  HDRINST usr/include/linux/sed-opal.h
  HDRINST usr/include/linux/sock_diag.h
  HDRINST usr/include/linux/time.h
  HDRINST usr/include/linux/securebits.h
  HDRINST usr/include/linux/fsl_hypervisor.h
  HDRINST usr/include/linux/if_hippi.h
  HDRINST usr/include/linux/seccomp.h
  HDRINST usr/include/linux/oom.h
  HDRINST usr/include/linux/filter.h
  HDRINST usr/include/linux/inotify.h
  HDRINST usr/include/linux/rfkill.h
  HDRINST usr/include/linux/reboot.h
  HDRINST usr/include/linux/can/vxcan.h
  HDRINST usr/include/linux/can/j1939.h
  HDRINST usr/include/linux/can/netlink.h
  HDRINST usr/include/linux/can/bcm.h
  HDRINST usr/include/linux/can/raw.h
  HDRINST usr/include/linux/can/gw.h
  HDRINST usr/include/linux/can/error.h
  HDRINST usr/include/linux/can/isotp.h
  HDRINST usr/include/linux/if_eql.h
  HDRINST usr/include/linux/hiddev.h
  HDRINST usr/include/linux/blktrace_api.h
  HDRINST usr/include/linux/ccs.h
  HDRINST usr/include/linux/ioam6.h
  HDRINST usr/include/linux/hsr_netlink.h
  HDRINST usr/include/linux/mmc/ioctl.h
  HDRINST usr/include/linux/bfs_fs.h
  HDRINST usr/include/linux/rio_cm_cdev.h
  HDRINST usr/include/linux/uleds.h
  HDRINST usr/include/linux/mrp_bridge.h
  HDRINST usr/include/linux/adb.h
  HDRINST usr/include/linux/pmu.h
  HDRINST usr/include/linux/udmabuf.h
  HDRINST usr/include/linux/kcmp.h
  HDRINST usr/include/linux/dma-heap.h
  HDRINST usr/include/linux/userfaultfd.h
  HDRINST usr/include/linux/netfilter_arp/arpt_mangle.h
  HDRINST usr/include/linux/netfilter_arp/arp_tables.h
  HDRINST usr/include/linux/tipc.h
  HDRINST usr/include/linux/virtio_ids.h
  HDRINST usr/include/linux/l2tp.h
  HDRINST usr/include/linux/devlink.h
  HDRINST usr/include/linux/virtio_gpio.h
  HDRINST usr/include/linux/dcbnl.h
  HDRINST usr/include/linux/cyclades.h
  HDRINST usr/include/sound/intel/avs/tokens.h
  HDRINST usr/include/sound/sof/fw.h
  HDRINST usr/include/sound/sof/abi.h
  HDRINST usr/include/sound/sof/tokens.h
  HDRINST usr/include/sound/sof/header.h
  HDRINST usr/include/sound/usb_stream.h
  HDRINST usr/include/sound/sfnt_info.h
  HDRINST usr/include/sound/asequencer.h
  HDRINST usr/include/sound/tlv.h
  HDRINST usr/include/sound/asound.h
  HDRINST usr/include/sound/asoc.h
  HDRINST usr/include/sound/sb16_csp.h
  HDRINST usr/include/sound/compress_offload.h
  HDRINST usr/include/sound/hdsp.h
  HDRINST usr/include/sound/emu10k1.h
  HDRINST usr/include/sound/snd_ar_tokens.h
  HDRINST usr/include/sound/snd_sst_tokens.h
  HDRINST usr/include/sound/asound_fm.h
  HDRINST usr/include/sound/hdspm.h
  HDRINST usr/include/sound/compress_params.h
  HDRINST usr/include/sound/firewire.h
  HDRINST usr/include/sound/skl-tplg-interface.h
  HDRINST usr/include/scsi/scsi_bsg_ufs.h
  HDRINST usr/include/scsi/scsi_netlink_fc.h
  HDRINST usr/include/scsi/scsi_bsg_mpi3mr.h
  HDRINST usr/include/scsi/fc/fc_ns.h
  HDRINST usr/include/scsi/fc/fc_fs.h
  HDRINST usr/include/scsi/fc/fc_els.h
  HDRINST usr/include/scsi/fc/fc_gs.h
  HDRINST usr/include/scsi/scsi_bsg_fc.h
  HDRINST usr/include/scsi/cxlflash_ioctl.h
  HDRINST usr/include/scsi/scsi_netlink.h
  HDRINST usr/include/linux/version.h
  HDRINST usr/include/asm/processor-flags.h
  HDRINST usr/include/asm/auxvec.h
  HDRINST usr/include/asm/svm.h
  HDRINST usr/include/asm/bitsperlong.h
  HDRINST usr/include/asm/kvm_perf.h
  HDRINST usr/include/asm/mce.h
  HDRINST usr/include/asm/posix_types.h
  HDRINST usr/include/asm/msr.h
  HDRINST usr/include/asm/sigcontext32.h
  HDRINST usr/include/asm/mman.h
  HDRINST usr/include/asm/shmbuf.h
  HDRINST usr/include/asm/e820.h
  HDRINST usr/include/asm/posix_types_64.h
  HDRINST usr/include/asm/vsyscall.h
  HDRINST usr/include/asm/msgbuf.h
  HDRINST usr/include/asm/swab.h
  HDRINST usr/include/asm/statfs.h
  HDRINST usr/include/asm/posix_types_x32.h
  HDRINST usr/include/asm/ptrace.h
  HDRINST usr/include/asm/unistd.h
  HDRINST usr/include/asm/ist.h
  HDRINST usr/include/asm/prctl.h
  HDRINST usr/include/asm/boot.h
  HDRINST usr/include/asm/sigcontext.h
  HDRINST usr/include/asm/posix_types_32.h
  HDRINST usr/include/asm/kvm_para.h
  HDRINST usr/include/asm/a.out.h
  HDRINST usr/include/asm/mtrr.h
  HDRINST usr/include/asm/amd_hsmp.h
  HDRINST usr/include/asm/hwcap2.h
  HDRINST usr/include/asm/ptrace-abi.h
  HDRINST usr/include/asm/vm86.h
  HDRINST usr/include/asm/vmx.h
  HDRINST usr/include/asm/ldt.h
  HDRINST usr/include/asm/perf_regs.h
  HDRINST usr/include/asm/kvm.h
  HDRINST usr/include/asm/debugreg.h
  HDRINST usr/include/asm/signal.h
  HDRINST usr/include/asm/bootparam.h
  HDRINST usr/include/asm/siginfo.h
  HDRINST usr/include/asm/hw_breakpoint.h
  HDRINST usr/include/asm/stat.h
  HDRINST usr/include/asm/setup.h
  HDRINST usr/include/asm/sembuf.h
  HDRINST usr/include/asm/sgx.h
  HDRINST usr/include/asm/ucontext.h
  HDRINST usr/include/asm/byteorder.h
  HDRINST usr/include/asm/unistd_64.h
  HDRINST usr/include/asm/ioctls.h
  HDRINST usr/include/asm/bpf_perf_event.h
  HDRINST usr/include/asm/types.h
  HDRINST usr/include/asm/poll.h
  HDRINST usr/include/asm/resource.h
  HDRINST usr/include/asm/param.h
  HDRINST usr/include/asm/sockios.h
  HDRINST usr/include/asm/errno.h
  HDRINST usr/include/asm/unistd_x32.h
  HDRINST usr/include/asm/termios.h
  HDRINST usr/include/asm/ioctl.h
  HDRINST usr/include/asm/socket.h
  HDRINST usr/include/asm/unistd_32.h
  HDRINST usr/include/asm/termbits.h
  HDRINST usr/include/asm/fcntl.h
  HDRINST usr/include/asm/ipcbuf.h
  HOSTLD  scripts/mod/modpost
  CC      kernel/bounds.s
  CHKSHA1 ../include/linux/atomic/atomic-arch-fallback.h
  CHKSHA1 ../include/linux/atomic/atomic-instrumented.h
  CHKSHA1 ../include/linux/atomic/atomic-long.h
  UPD     include/generated/timeconst.h
  LD      /kernel/build64/tools/objtool/arch/x86/objtool-in.o
  UPD     include/generated/bounds.h
  CC      arch/x86/kernel/asm-offsets.s
  UPD     include/generated/asm-offsets.h
  CALL    ../scripts/checksyscalls.sh
  LD      /kernel/build64/tools/objtool/objtool-in.o
  LINK    /kernel/build64/tools/objtool/objtool
  LDS     scripts/module.lds
  HOSTCC  usr/gen_init_cpio
  CC      ipc/compat.o
  CC      ipc/util.o
  CC      ipc/msgutil.o
  CC      ipc/msg.o
  AR      certs/built-in.a
  CC      ipc/sem.o
  CC      ipc/shm.o
  CC      ipc/syscall.o
  CC      ipc/ipc_sysctl.o
  CC      ipc/mqueue.o
  CC      io_uring/io_uring.o
  CC      init/main.o
  AS      arch/x86/lib/clear_page_64.o
  CC      init/do_mounts.o
  CC      security/commoncap.o
  CC      ipc/namespace.o
  CC      io_uring/xattr.o
  CC      arch/x86/lib/cmdline.o
  CC      mm/filemap.o
  CC      arch/x86/realmode/init.o
  CC      ipc/mq_sysctl.o
  AR      arch/x86/video/built-in.a
  CC      arch/x86/power/cpu.o
  CC      arch/x86/pci/i386.o
  AS      arch/x86/crypto/aesni-intel_asm.o
  CC      security/min_addr.o
  UPD     init/utsversion-tmp.h
  CC      security/keys/gc.o
  AR      arch/x86/ia32/built-in.a
  AR      arch/x86/net/built-in.a
  CC      block/partitions/core.o
  AR      virt/lib/built-in.a
  CC [M]  arch/x86/video/fbdev.o
  CC      net/core/sock.o
  CC      arch/x86/mm/init.o
  CC      net/llc/llc_core.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/kvm_main.o
  CC      arch/x86/entry/vsyscall/vsyscall_64.o
  CC      arch/x86/mm/pat/set_memory.o
  CC      arch/x86/events/amd/core.o
  CC      arch/x86/kernel/fpu/init.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/eventfd.o
  AR      drivers/irqchip/built-in.a
  CC      fs/notify/dnotify/dnotify.o
  CC      sound/core/seq/seq.o
  CC [M]  virt/lib/irqbypass.o
  CC      fs/notify/inotify/inotify_fsnotify.o
  AR      arch/x86/platform/atom/built-in.a
  AR      arch/x86/platform/ce4100/built-in.a
  CC      arch/x86/entry/vdso/vma.o
  CC      lib/kunit/test.o
  AR      drivers/phy/allwinner/built-in.a
  AR      drivers/bus/mhi/built-in.a
  CC      mm/kasan/common.o
  CC      arch/x86/platform/efi/memmap.o
  AR      drivers/bus/built-in.a
  AR      drivers/phy/amlogic/built-in.a
  CC      kernel/sched/core.o
  CC      arch/x86/crypto/aesni-intel_glue.o
  AR      drivers/phy/broadcom/built-in.a
  AS      arch/x86/crypto/aesni-intel_avx-x86_64.o
  AR      drivers/phy/cadence/built-in.a
  CC      crypto/api.o
  AR      drivers/phy/freescale/built-in.a
  AR      drivers/phy/hisilicon/built-in.a
  AR      drivers/phy/ingenic/built-in.a
  AS      arch/x86/lib/cmpxchg16b_emu.o
  AR      drivers/phy/intel/built-in.a
  AR      drivers/phy/lantiq/built-in.a
  CC      arch/x86/lib/copy_mc.o
  AR      drivers/phy/marvell/built-in.a
  AR      drivers/phy/mediatek/built-in.a
  AR      drivers/phy/microchip/built-in.a
  AR      drivers/phy/motorola/built-in.a
  AR      drivers/phy/mscc/built-in.a
  AR      drivers/phy/qualcomm/built-in.a
  AR      drivers/phy/ralink/built-in.a
  AR      drivers/phy/renesas/built-in.a
  AR      drivers/phy/rockchip/built-in.a
  AR      drivers/phy/samsung/built-in.a
  AR      drivers/phy/socionext/built-in.a
  AR      drivers/phy/st/built-in.a
  AR      drivers/phy/sunplus/built-in.a
  AR      drivers/phy/tegra/built-in.a
  GEN     usr/initramfs_data.cpio
  AR      drivers/phy/ti/built-in.a
  COPY    usr/initramfs_inc_data
  AS      usr/initramfs_data.o
  AR      drivers/phy/xilinx/built-in.a
  CC      drivers/phy/phy-core.o
  AR      usr/built-in.a
  CC      security/keys/key.o
  AS      arch/x86/realmode/rm/header.o
  CC      arch/x86/kernel/fpu/bugs.o
  CC      arch/x86/kernel/fpu/core.o
  AS      arch/x86/realmode/rm/trampoline_64.o
  AS      arch/x86/realmode/rm/stack.o
  AS      arch/x86/lib/copy_mc_64.o
  AS      arch/x86/realmode/rm/reboot.o
  AR      virt/built-in.a
  CC      init/do_mounts_initrd.o
  AS      arch/x86/lib/copy_page_64.o
  AS      arch/x86/realmode/rm/wakeup_asm.o
  AR      drivers/pinctrl/actions/built-in.a
  AR      drivers/pinctrl/bcm/built-in.a
  AS      arch/x86/lib/copy_user_64.o
  CC      arch/x86/realmode/rm/wakemain.o
  AR      drivers/pinctrl/cirrus/built-in.a
  CC      fs/notify/inotify/inotify_user.o
  CC      sound/core/seq/seq_lock.o
  AR      drivers/pinctrl/freescale/built-in.a
  CC      init/initramfs.o
  CC      security/inode.o
  AS      arch/x86/crypto/aes_ctrby8_avx-x86_64.o
  AS      arch/x86/lib/copy_user_uncached_64.o
  CC      drivers/gpio/gpiolib.o
  CC      drivers/pinctrl/intel/pinctrl-baytrail.o
  CC      drivers/gpio/gpiolib-devres.o
  CC      arch/x86/lib/cpu.o
  CC      arch/x86/realmode/rm/video-mode.o
  AR      drivers/pinctrl/mediatek/built-in.a
  CC      drivers/pinctrl/intel/pinctrl-intel.o
  CC [M]  drivers/pinctrl/intel/pinctrl-cherryview.o
  CC [M]  drivers/pinctrl/intel/pinctrl-broxton.o
  CC      arch/x86/kernel/cpu/mce/core.o
  AR      fs/notify/dnotify/built-in.a
  CC [M]  drivers/pinctrl/intel/pinctrl-geminilake.o
  CC      arch/x86/pci/init.o
  AS      arch/x86/realmode/rm/copy.o
  CC      lib/kunit/resource.o
  AS      arch/x86/realmode/rm/bioscall.o
  CC      arch/x86/mm/init_64.o
  CC      arch/x86/platform/efi/quirks.o
  CC      arch/x86/realmode/rm/regs.o
  CC      arch/x86/events/amd/lbr.o
  AS      arch/x86/entry/vsyscall/vsyscall_emu_64.o
  AR      arch/x86/entry/vsyscall/built-in.a
  CC      arch/x86/entry/vdso/extable.o
  CC      crypto/cipher.o
  CC      arch/x86/realmode/rm/video-vga.o
  CC      net/llc/llc_input.o
  CC      net/llc/llc_output.o
  CC      mm/kasan/report.o
  CC      arch/x86/power/hibernate_64.o
  CC      block/partitions/ldm.o
  CC      sound/core/seq/seq_clientmgr.o
  CC      arch/x86/realmode/rm/video-vesa.o
  CC      arch/x86/kernel/acpi/boot.o
  CC      arch/x86/lib/delay.o
  CC      arch/x86/realmode/rm/video-bios.o
  AS [M]  arch/x86/crypto/ghash-clmulni-intel_asm.o
  CC [M]  arch/x86/crypto/ghash-clmulni-intel_glue.o
  CC      arch/x86/kernel/fpu/regset.o
  PASYMS  arch/x86/realmode/rm/pasyms.h
  LDS     arch/x86/realmode/rm/realmode.lds
  CC      security/keys/keyring.o
  CC      init/calibrate.o
  LD      arch/x86/realmode/rm/realmode.elf
  RELOCS  arch/x86/realmode/rm/realmode.relocs
  OBJCOPY arch/x86/realmode/rm/realmode.bin
  CC      arch/x86/kernel/cpu/mtrr/mtrr.o
  CC      arch/x86/pci/mmconfig_64.o
  AS      arch/x86/realmode/rmpiggy.o
  CC      arch/x86/kernel/cpu/mtrr/if.o
  CC      arch/x86/pci/direct.o
  CC      net/ethernet/eth.o
  CC      arch/x86/kernel/cpu/mtrr/generic.o
  CC      arch/x86/pci/mmconfig-shared.o
  AR      arch/x86/realmode/built-in.a
  CC      lib/kunit/static_stub.o
  CC      sound/core/seq/seq_memory.o
  CC      arch/x86/kernel/cpu/mtrr/cleanup.o
  AS      arch/x86/lib/getuser.o
  CC      crypto/compress.o
  CC      arch/x86/platform/efi/efi.o
  CC      arch/x86/platform/efi/efi_64.o
  GEN     arch/x86/lib/inat-tables.c
  AR      drivers/phy/built-in.a
  CC      arch/x86/events/amd/ibs.o
  CC      arch/x86/lib/insn-eval.o
  CC      net/core/request_sock.o
  AR      drivers/pinctrl/mvebu/built-in.a
  CC      drivers/gpio/gpiolib-legacy.o
  CC      arch/x86/entry/vdso/vdso32-setup.o
  CC      drivers/gpio/gpiolib-cdev.o
  CC      init/init_task.o
  AR      fs/notify/inotify/built-in.a
  CC      fs/notify/fanotify/fanotify.o
  AS      arch/x86/power/hibernate_asm_64.o
  CC      drivers/gpio/gpiolib-sysfs.o
  CC      arch/x86/power/hibernate.o
  AS [M]  arch/x86/crypto/crc32-pclmul_asm.o
  CC      arch/x86/mm/pat/memtype.o
  CC      drivers/gpio/gpiolib-acpi.o
  CC [M]  arch/x86/crypto/crc32-pclmul_glue.o
  CC      mm/kasan/init.o
  LDS     arch/x86/entry/vdso/vdso.lds
  CC [M]  drivers/pinctrl/intel/pinctrl-sunrisepoint.o
  CC      mm/mempool.o
  AR      net/llc/built-in.a
  CC      io_uring/nop.o
  CC      lib/math/div64.o
  AS      arch/x86/entry/vdso/vdso-note.o
  CC      lib/kunit/string-stream.o
  CC      arch/x86/entry/vdso/vclock_gettime.o
  CC      crypto/algapi.o
  CC      lib/math/gcd.o
  CC      net/802/p8022.o
  CC      arch/x86/kernel/fpu/signal.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/binary_stats.o
  CC      lib/crypto/memneq.o
  CC      lib/math/lcm.o
  CC      security/device_cgroup.o
  CC      lib/crypto/utils.o
  CC      sound/core/sound.o
  CC      lib/math/int_pow.o
  CC      lib/math/int_sqrt.o
  CC      lib/math/reciprocal_div.o
  CC      sound/core/init.o
  CC      lib/kunit/assert.o
  CC      block/partitions/msdos.o
  AR      sound/i2c/other/built-in.a
  AR      sound/i2c/built-in.a
  CC      arch/x86/kernel/acpi/sleep.o
  CC      lib/math/rational.o
  AR      sound/drivers/opl3/built-in.a
  AR      sound/drivers/opl4/built-in.a
  AS [M]  arch/x86/crypto/crct10dif-pcl-asm_64.o
  AR      sound/drivers/mpu401/built-in.a
  AR      sound/drivers/vx/built-in.a
  CC      fs/notify/fanotify/fanotify_user.o
  CC [M]  arch/x86/crypto/crct10dif-pclmul_glue.o
  AR      sound/drivers/pcsp/built-in.a
  AR      sound/drivers/built-in.a
  CC      arch/x86/pci/fixup.o
  CC      mm/oom_kill.o
  AR      drivers/pinctrl/intel/built-in.a
  CC      mm/fadvise.o
  AR      drivers/pinctrl/nomadik/built-in.a
  AR      arch/x86/platform/geode/built-in.a
  CC      mm/maccess.o
  AR      drivers/pinctrl/nuvoton/built-in.a
  CC      init/version.o
  AR      ipc/built-in.a
  AR      arch/x86/platform/iris/built-in.a
  CC      arch/x86/mm/fault.o
  AR      drivers/pinctrl/nxp/built-in.a
  CC      arch/x86/mm/ioremap.o
  AS      arch/x86/platform/efi/efi_stub_64.o
  AR      arch/x86/kernel/cpu/mtrr/built-in.a
  CC      lib/kunit/try-catch.o
  AR      drivers/pinctrl/sprd/built-in.a
  CC      lib/kunit/executor.o
  CC      lib/crypto/chacha.o
  CC      arch/x86/entry/vdso/vgetcpu.o
  AR      drivers/pinctrl/sunplus/built-in.a
  AR      arch/x86/platform/efi/built-in.a
  AR      arch/x86/power/built-in.a
  AR      drivers/pinctrl/ti/built-in.a
  CC      drivers/pinctrl/core.o
  CC      arch/x86/platform/intel/iosf_mbi.o
  AR      arch/x86/platform/intel-mid/built-in.a
  CC      drivers/pinctrl/pinctrl-utils.o
  CC      lib/kunit/hooks.o
  CC      sound/core/seq/seq_queue.o
  CC      security/keys/keyctl.o
  HOSTCC  arch/x86/entry/vdso/vdso2c
  CC      block/partitions/efi.o
  CC      arch/x86/kernel/cpu/mce/severity.o
  CC      arch/x86/lib/insn.o
  CC      lib/crypto/aes.o
  CC      arch/x86/mm/extable.o
  AR      net/ethernet/built-in.a
  CC      net/core/skbuff.o
  CC [M]  lib/math/prime_numbers.o
  CC      mm/kasan/generic.o
  CC      arch/x86/events/amd/uncore.o
  AR      init/built-in.a
  CC      net/core/datagram.o
  CC      arch/x86/mm/pat/memtype_interval.o
  CC      net/sched/sch_generic.o
  CC      net/netlink/af_netlink.o
  AS      arch/x86/entry/entry.o
  CC      net/netlink/genetlink.o
  CC      net/netlink/policy.o
  CC      net/802/psnap.o
  LD [M]  arch/x86/crypto/ghash-clmulni-intel.o
  CC      kernel/locking/mutex.o
  LD [M]  arch/x86/crypto/crc32-pclmul.o
  CC      kernel/locking/semaphore.o
  LD [M]  arch/x86/crypto/crct10dif-pclmul.o
  AR      arch/x86/crypto/built-in.a
  AR      net/bpf/built-in.a
  CC      sound/core/memory.o
  CC      net/sched/sch_mq.o
  CC      arch/x86/kernel/fpu/xstate.o
  CC      net/sched/sch_frag.o
  LDS     arch/x86/entry/vdso/vdso32/vdso32.lds
  AS      arch/x86/entry/vdso/vdso32/note.o
  AS      arch/x86/lib/memcpy_64.o
  AS      arch/x86/kernel/acpi/wakeup_64.o
  AS      arch/x86/entry/vdso/vdso32/system_call.o
  AS      arch/x86/lib/memmove_64.o
  CC      arch/x86/kernel/acpi/apei.o
  AR      lib/kunit/built-in.a
  AS      arch/x86/entry/vdso/vdso32/sigreturn.o
  CC      mm/page-writeback.o
  CC      lib/crypto/gf128mul.o
  AS      arch/x86/lib/memset_64.o
  CC      arch/x86/entry/vdso/vdso32/vclock_gettime.o
  CC      lib/crypto/blake2s.o
  CC      arch/x86/lib/misc.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/vfio.o
  CC      arch/x86/lib/pc-conf-reg.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/coalesced_mmio.o
  CC      mm/folio-compat.o
  CC      arch/x86/pci/acpi.o
  CC      crypto/scatterwalk.o
  AR      arch/x86/platform/intel/built-in.a
  AR      arch/x86/platform/intel-quark/built-in.a
  AR      arch/x86/platform/olpc/built-in.a
  AR      arch/x86/platform/scx200/built-in.a
  AR      arch/x86/platform/ts5500/built-in.a
  AR      lib/math/built-in.a
  AR      arch/x86/platform/uv/built-in.a
  AR      arch/x86/platform/built-in.a
  CC      sound/core/control.o
  CC      lib/zlib_inflate/inffast.o
  CC      sound/core/misc.o
  AS      arch/x86/lib/putuser.o
  CC      mm/readahead.o
  CC      sound/core/seq/seq_fifo.o
  CC      arch/x86/kernel/cpu/mce/genpool.o
  CC      lib/zlib_inflate/inflate.o
  AS      arch/x86/lib/retpoline.o
  CC      mm/swap.o
  CC      lib/zlib_inflate/infutil.o
  AR      arch/x86/mm/pat/built-in.a
  CC      arch/x86/lib/usercopy.o
  CC      lib/zlib_deflate/deflate.o
  CC      arch/x86/lib/usercopy_64.o
  CC      lib/zlib_deflate/deftree.o
  CC      lib/zlib_deflate/deflate_syms.o
  AR      block/partitions/built-in.a
  CC      arch/x86/lib/msr-smp.o
  CC      block/bdev.o
  CC      drivers/gpio/gpiolib-swnode.o
  CC      arch/x86/kernel/acpi/cppc.o
  CC      arch/x86/kernel/acpi/cstate.o
  CC      mm/kasan/report_generic.o
  CC      net/802/stp.o
  AR      arch/x86/events/amd/built-in.a
  CC      arch/x86/events/intel/core.o
  CC      arch/x86/entry/vdso/vdso32/vgetcpu.o
  CC      arch/x86/events/zhaoxin/core.o
  CC      lib/crypto/blake2s-generic.o
  CC      lib/zlib_inflate/inftrees.o
  CC      lib/crypto/blake2s-selftest.o
  VDSO    arch/x86/entry/vdso/vdso64.so.dbg
  CC      arch/x86/events/intel/bts.o
  AR      fs/notify/fanotify/built-in.a
  CC      fs/notify/fsnotify.o
  VDSO    arch/x86/entry/vdso/vdso32.so.dbg
  CC      arch/x86/events/intel/ds.o
  CC      arch/x86/mm/mmap.o
  OBJCOPY arch/x86/entry/vdso/vdso64.so
  OBJCOPY arch/x86/entry/vdso/vdso32.so
  CC      security/keys/permission.o
  VDSO2C  arch/x86/entry/vdso/vdso-image-64.c
  CC      drivers/pinctrl/pinmux.o
  VDSO2C  arch/x86/entry/vdso/vdso-image-32.c
  CC      crypto/proc.o
  CC      arch/x86/entry/vdso/vdso-image-64.o
  CC      fs/notify/notification.o
  CC      crypto/aead.o
  CC      kernel/locking/rwsem.o
  CC      arch/x86/kernel/cpu/mce/intel.o
  CC      arch/x86/events/intel/knc.o
  CC      fs/notify/group.o
  AS      arch/x86/entry/entry_64.o
  CC      arch/x86/pci/legacy.o
  CC      sound/core/seq/seq_prioq.o
  CC      arch/x86/pci/irq.o
  CC      arch/x86/lib/cache-smp.o
  CC      arch/x86/pci/common.o
  AR      drivers/gpio/built-in.a
  AR      sound/isa/ad1816a/built-in.a
  CC      arch/x86/kernel/cpu/mce/threshold.o
  AR      sound/isa/ad1848/built-in.a
  AR      sound/isa/cs423x/built-in.a
  AR      sound/isa/es1688/built-in.a
  CC      arch/x86/entry/vdso/vdso-image-32.o
  CC      lib/zlib_inflate/inflate_syms.o
  AR      sound/isa/galaxy/built-in.a
  AR      sound/ppc/built-in.a
  AR      sound/pci/ac97/built-in.a
  CC      net/sched/sch_api.o
  AR      sound/isa/gus/built-in.a
  AR      sound/pci/ali5451/built-in.a
  AR      sound/isa/msnd/built-in.a
  AR      sound/pci/asihpi/built-in.a
  AR      sound/isa/opti9xx/built-in.a
  CC      lib/crypto/des.o
  AR      sound/isa/sb/built-in.a
  AR      sound/pci/au88x0/built-in.a
  AR      sound/pci/aw2/built-in.a
  CC      net/sched/sch_blackhole.o
  AR      sound/isa/wavefront/built-in.a
  CC      lib/crypto/sha1.o
  AR      sound/pci/ctxfi/built-in.a
  CC      arch/x86/lib/msr.o
  AR      sound/isa/wss/built-in.a
  AR      arch/x86/kernel/fpu/built-in.a
  AR      sound/pci/ca0106/built-in.a
  AR      sound/isa/built-in.a
  AR      arch/x86/kernel/acpi/built-in.a
  CC      net/sched/sch_fifo.o
  AR      sound/pci/cs46xx/built-in.a
  AR      sound/arm/built-in.a
  CC      arch/x86/kernel/apic/apic.o
  AR      sound/pci/cs5535audio/built-in.a
  CC      arch/x86/kernel/kprobes/core.o
  AR      sound/pci/lola/built-in.a
  CC      fs/notify/mark.o
  AR      sound/pci/lx6464es/built-in.a
  AR      sound/pci/echoaudio/built-in.a
  AR      sound/pci/emu10k1/built-in.a
  AR      sound/pci/hda/built-in.a
  CC [M]  sound/pci/hda/hda_bind.o
  CC      mm/kasan/shadow.o
  AR      arch/x86/entry/vdso/built-in.a
  CC      arch/x86/entry/syscall_64.o
  CC [M]  sound/pci/hda/hda_codec.o
  AR      lib/zlib_deflate/built-in.a
  CC      arch/x86/pci/early.o
  CC      security/keys/process_keys.o
  AR      sound/pci/ice1712/built-in.a
  CC      security/keys/request_key.o
  AR      net/802/built-in.a
  CC [M]  sound/pci/hda/hda_jack.o
  CC      security/keys/request_key_auth.o
  AR      lib/zlib_inflate/built-in.a
  CC      arch/x86/mm/pgtable.o
  CC      security/keys/user_defined.o
  CC      lib/lzo/lzo1x_compress.o
  AR      arch/x86/events/zhaoxin/built-in.a
  CC      mm/truncate.o
  CC      lib/lzo/lzo1x_decompress_safe.o
  CC      fs/notify/fdinfo.o
  CC      block/fops.o
  AR      sound/sh/built-in.a
  CC      lib/crypto/sha256.o
  CC      sound/core/seq/seq_timer.o
  CC      drivers/pinctrl/pinconf.o
  AR      sound/pci/korg1212/built-in.a
  CC      net/netlink/diag.o
  CC      crypto/geniv.o
  AR      sound/pci/mixart/built-in.a
  CC      mm/vmscan.o
  CC      arch/x86/kernel/kprobes/opt.o
  CC      arch/x86/kernel/apic/apic_common.o
  CC      arch/x86/kernel/cpu/cacheinfo.o
  CC      arch/x86/kernel/cpu/scattered.o
  CC      arch/x86/kernel/cpu/mce/apei.o
  CC      arch/x86/kernel/cpu/topology.o
  CC      io_uring/fs.o
  CC      kernel/locking/percpu-rwsem.o
  CC      mm/kasan/quarantine.o
  CC      arch/x86/entry/common.o
  AS      arch/x86/lib/msr-reg.o
  AR      sound/pci/nm256/built-in.a
  CC      mm/shmem.o
  CC      io_uring/splice.o
  CC      arch/x86/kernel/kprobes/ftrace.o
  CC      arch/x86/lib/msr-reg-export.o
  CC      mm/util.o
  AR      lib/lzo/built-in.a
  CC [M]  arch/x86/kvm/../../../virt/kvm/async_pf.o
  CC      lib/lz4/lz4_compress.o
  CC      sound/core/device.o
  CC      arch/x86/events/intel/lbr.o
  AS      arch/x86/entry/thunk_64.o
  AS      arch/x86/lib/hweight.o
  AS      arch/x86/entry/entry_64_compat.o
  CC      arch/x86/lib/iomem.o
  CC      arch/x86/entry/syscall_32.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/irqchip.o
  CC      arch/x86/pci/bus_numa.o
  AR      sound/pci/oxygen/built-in.a
  CC      arch/x86/pci/amd_bus.o
  CC      mm/mmzone.o
  CC      io_uring/sync.o
  CC      security/keys/compat.o
  CC [M]  lib/crypto/arc4.o
  AR      fs/notify/built-in.a
  CC      fs/nfs_common/grace.o
  CC      arch/x86/kernel/cpu/common.o
  CC      drivers/pinctrl/pinconf-generic.o
  CC      block/bio.o
  LDS     arch/x86/kernel/vmlinux.lds
  CC      security/keys/proc.o
  CC      security/keys/sysctl.o
  AS      arch/x86/lib/iomap_copy_64.o
  CC      mm/vmstat.o
  CC      sound/core/seq/seq_system.o
  CC      arch/x86/mm/physaddr.o
  CC      arch/x86/mm/tlb.o
  CC      crypto/skcipher.o
  AR      arch/x86/kernel/cpu/mce/built-in.a
  CC      lib/zstd/zstd_compress_module.o
  CC      arch/x86/kernel/cpu/rdrand.o
  CC      crypto/seqiv.o
  CC      lib/zstd/compress/fse_compress.o
  CC      arch/x86/lib/inat.o
  CC      lib/xz/xz_dec_syms.o
  AR      lib/crypto/built-in.a
  LD [M]  lib/crypto/libarc4.o
  CC      mm/backing-dev.o
  AR      arch/x86/kernel/kprobes/built-in.a
  AR      arch/x86/lib/built-in.a
  CC      kernel/locking/irqflag-debug.o
  CC      block/elevator.o
  CC      lib/raid6/algos.o
  CC      sound/core/info.o
  AR      sound/pci/pcxhr/built-in.a
  AR      net/netlink/built-in.a
  CC      block/blk-core.o
  CC      lib/fonts/fonts.o
  CC      mm/mm_init.o
  CC      crypto/echainiv.o
  AR      arch/x86/lib/lib.a
  CC      lib/fonts/font_8x8.o
  CC      kernel/locking/mutex-debug.o
  AR      mm/kasan/built-in.a
  CC      lib/fonts/font_8x16.o
  CC      sound/core/isadma.o
  CC      lib/argv_split.o
  CC      block/blk-sysfs.o
  CC      block/blk-flush.o
  AR      arch/x86/entry/built-in.a
  CC      lib/xz/xz_dec_stream.o
  CC      crypto/ahash.o
  AR      drivers/pinctrl/built-in.a
  AR      drivers/pwm/built-in.a
  CC      arch/x86/kernel/cpu/match.o
  CC      arch/x86/kernel/cpu/bugs.o
  CC      mm/percpu.o
  CC      drivers/pci/msi/pcidev_msi.o
  AR      arch/x86/pci/built-in.a
  CC      arch/x86/kernel/cpu/aperfmperf.o
  CC      sound/core/seq/seq_ports.o
  CC      drivers/pci/msi/api.o
  CC      net/core/stream.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/dirty_ring.o
  AR      fs/nfs_common/built-in.a
  CC      io_uring/advise.o
  CC      lib/zstd/compress/hist.o
  CC      arch/x86/kernel/cpu/cpuid-deps.o
  CC      fs/iomap/trace.o
  AR      security/keys/built-in.a
  AR      security/built-in.a
  CC      lib/zstd/compress/huf_compress.o
  CC      arch/x86/kernel/apic/apic_noop.o
  CC      io_uring/filetable.o
  CC [M]  arch/x86/kvm/../../../virt/kvm/pfncache.o
  CC      drivers/pci/msi/msi.o
  CC      drivers/pci/msi/irqdomain.o
  AR      lib/fonts/built-in.a
  CC      arch/x86/mm/cpu_entry_area.o
  CC      sound/core/vmaster.o
  CC      lib/xz/xz_dec_lzma2.o
  CC      drivers/video/console/dummycon.o
  CC      lib/raid6/recov.o
  CC      arch/x86/kernel/apic/ipi.o
  CC      arch/x86/kernel/apic/vector.o
  CC      kernel/locking/lockdep.o
  CC      drivers/video/logo/logo.o
  HOSTCC  drivers/video/logo/pnmtologo
  CC      drivers/video/backlight/backlight.o
  CC      drivers/video/console/vgacon.o
  AR      net/sched/built-in.a
  CC      net/ethtool/ioctl.o
  CC      arch/x86/events/intel/p4.o
  CC      arch/x86/mm/maccess.o
  CC [M]  net/netfilter/ipvs/ip_vs_conn.o
  CC [M]  net/netfilter/ipvs/ip_vs_core.o
  CC      arch/x86/mm/pgprot.o
  CC [M]  arch/x86/kvm/x86.o
  CC      net/ethtool/common.o
  CC      kernel/sched/fair.o
  CC [M]  sound/pci/hda/hda_auto_parser.o
  CC      sound/core/ctljack.o
  CC      lib/lz4/lz4hc_compress.o
  LOGO    drivers/video/logo/logo_linux_clut224.c
  CC      arch/x86/kernel/apic/hw_nmi.o
  CC      net/netfilter/core.o
  CC      drivers/video/logo/logo_linux_clut224.o
  CC      net/netfilter/nf_log.o
  CC      io_uring/openclose.o
  CC      sound/core/seq/seq_info.o
  AR      drivers/video/logo/built-in.a
  AR      sound/synth/emux/built-in.a
  AR      sound/synth/built-in.a
  CC      drivers/video/aperture.o
  CC      drivers/video/fbdev/core/fb_notify.o
  CC      arch/x86/mm/hugetlbpage.o
  CC      drivers/video/cmdline.o
  CC      drivers/video/nomodeset.o
  CC      arch/x86/events/intel/p6.o
  CC      block/blk-settings.o
  CC      crypto/shash.o
  HOSTCC  lib/raid6/mktables
  CC [M]  net/netfilter/ipvs/ip_vs_ctl.o
  CC      drivers/video/hdmi.o
  CC      lib/xz/xz_dec_bcj.o
  CC      block/blk-ioc.o
  CC      block/blk-map.o
  UNROLL  lib/raid6/int1.c
  CC      mm/slab_common.o
  AR      sound/usb/misc/built-in.a
  UNROLL  lib/raid6/int2.c
  AR      sound/usb/usx2y/built-in.a
  UNROLL  lib/raid6/int4.c
  AR      sound/firewire/built-in.a
  UNROLL  lib/raid6/int8.c
  AR      sound/usb/caiaq/built-in.a
  UNROLL  lib/raid6/int16.c
  UNROLL  lib/raid6/int32.c
  CC [M]  net/netfilter/ipvs/ip_vs_sched.o
  AR      sound/usb/6fire/built-in.a
  CC      lib/raid6/recov_ssse3.o
  AR      sound/usb/hiface/built-in.a
  CC      mm/compaction.o
  AR      drivers/pci/msi/built-in.a
  AR      sound/usb/bcd2000/built-in.a
  CC [M]  net/netfilter/ipvs/ip_vs_xmit.o
  CC      fs/iomap/iter.o
  AR      sound/usb/built-in.a
  CC      drivers/pci/pcie/portdrv.o
  CC      fs/iomap/buffered-io.o
  CC      io_uring/uring_cmd.o
  CC      drivers/pci/pcie/rcec.o
  CC      arch/x86/mm/kasan_init_64.o
  AR      sound/core/seq/built-in.a
  CC      sound/core/jack.o
  CC      fs/iomap/direct-io.o
  CC      arch/x86/kernel/cpu/umwait.o
  AR      drivers/video/backlight/built-in.a
  CC      lib/bug.o
  CC      arch/x86/events/intel/pt.o
  AR      lib/xz/built-in.a
  CC [M]  net/netfilter/ipvs/ip_vs_app.o
  AR      drivers/video/console/built-in.a
  CC      lib/zstd/compress/zstd_compress.o
  CC [M]  drivers/video/fbdev/core/fb_backlight.o
  CC      lib/zstd/compress/zstd_compress_literals.o
  CC      arch/x86/events/intel/uncore.o
  CC      drivers/pci/pcie/aspm.o
  CC      lib/zstd/compress/zstd_compress_sequences.o
  AR      net/ipv4/netfilter/built-in.a
  CC      net/ethtool/netlink.o
  CC [M]  net/ipv4/netfilter/nf_defrag_ipv4.o
  CC [M]  net/netfilter/ipvs/ip_vs_sync.o
  CC      drivers/pci/pcie/aer.o
  CC      lib/raid6/recov_avx2.o
  CC [M]  sound/pci/hda/hda_sysfs.o
  CC      sound/core/timer.o
  CC      net/ethtool/bitset.o
  CC      net/core/scm.o
  CC      fs/iomap/fiemap.o
  CC      io_uring/epoll.o
  AR      drivers/video/fbdev/omap/built-in.a
  CC      net/ipv4/route.o
  CC      fs/iomap/seek.o
  CC      crypto/akcipher.o
  CC      arch/x86/kernel/apic/io_apic.o
  CC      lib/lz4/lz4_decompress.o
  CC      arch/x86/mm/pkeys.o
  CC      net/core/gen_stats.o
  CC      net/ethtool/strset.o
  CC      io_uring/statx.o
  CC [M]  net/netfilter/ipvs/ip_vs_est.o
  CC      block/blk-merge.o
  CC      net/netfilter/nf_queue.o
  CC      arch/x86/kernel/cpu/proc.o
  MKCAP   arch/x86/kernel/cpu/capflags.c
  AR      sound/pci/riptide/built-in.a
  CC      net/netfilter/nf_sockopt.o
  CC      net/ethtool/linkinfo.o
  CC      net/ethtool/linkmodes.o
  CC [M]  drivers/video/fbdev/core/fb_info.o
  CC      net/netfilter/utils.o
  CC      lib/raid6/mmx.o
  CC      mm/interval_tree.o
  CC      lib/raid6/sse1.o
  CC      mm/list_lru.o
  CC [M]  sound/pci/hda/hda_controller.o
  CC      lib/raid6/sse2.o
  CC      mm/workingset.o
  CC      arch/x86/kernel/cpu/powerflags.o
  CC      arch/x86/mm/pti.o
  CC      crypto/kpp.o
  CC      io_uring/net.o
  CC [M]  net/ipv4/netfilter/nf_reject_ipv4.o
  CC      drivers/pci/pcie/err.o
  CC      drivers/pci/pcie/aer_inject.o
  CC [M]  drivers/video/fbdev/core/fbmem.o
  CC [M]  net/netfilter/ipvs/ip_vs_proto.o
  CC      block/blk-timeout.o
  CC      kernel/locking/lockdep_proc.o
  CC      net/ipv4/inetpeer.o
  CC [M]  net/netfilter/ipvs/ip_vs_pe.o
  CC      lib/zstd/compress/zstd_compress_superblock.o
  AS      arch/x86/kernel/head_64.o
  CC [M]  net/ipv4/netfilter/ip_tables.o
  CC [M]  arch/x86/kvm/emulate.o
  CC      net/ethtool/rss.o
  CC      arch/x86/events/intel/uncore_nhmex.o
  CC      kernel/locking/spinlock.o
  CC      arch/x86/events/intel/uncore_snb.o
  CC      net/core/gen_estimator.o
  AR      lib/lz4/built-in.a
  CC      kernel/locking/osq_lock.o
  CC      io_uring/msg_ring.o
  CC [M]  net/netfilter/nfnetlink.o
  CC [M]  drivers/video/fbdev/core/fbmon.o
  AR      sound/pci/rme9652/built-in.a
  AR      sound/pci/trident/built-in.a
  CC      kernel/locking/qspinlock.o
  CC      lib/zstd/compress/zstd_double_fast.o
  CC      fs/iomap/swapfile.o
  CC      lib/raid6/avx2.o
  CC      net/core/net_namespace.o
  CC      kernel/locking/rtmutex_api.o
  CC      crypto/acompress.o
  CC      crypto/scompress.o
  CC      crypto/algboss.o
  AR      arch/x86/mm/built-in.a
  CC      net/ipv4/protocol.o
  CC [M]  drivers/video/fbdev/core/fbcmap.o
  CC      lib/zstd/compress/zstd_fast.o
  CC [M]  net/netfilter/ipvs/ip_vs_proto_tcp.o
  CC      lib/zstd/compress/zstd_lazy.o
  CC      sound/core/hrtimer.o
  CC      arch/x86/kernel/cpu/feat_ctl.o
  CC      mm/debug.o
  CC      arch/x86/kernel/cpu/intel.o
  CC      drivers/pci/pcie/pme.o
  CC      mm/gup.o
  CC      crypto/testmgr.o
  AR      sound/sparc/built-in.a
  CC      net/core/secure_seq.o
  CC      block/blk-lib.o
  CC      block/blk-mq.o
  CC      arch/x86/kernel/apic/msi.o
  CC [M]  net/netfilter/ipvs/ip_vs_proto_udp.o
  AR      fs/iomap/built-in.a
  CC [M]  net/netfilter/ipvs/ip_vs_nfct.o
  CC [M]  sound/pci/hda/hda_proc.o
  AR      fs/quota/built-in.a
  CC      kernel/locking/spinlock_debug.o
  CC      net/ethtool/linkstate.o
  CC      lib/raid6/avx512.o
  CC      net/ethtool/debug.o
  CC      arch/x86/events/intel/uncore_snbep.o
  CC      sound/core/seq_device.o
  CC      arch/x86/events/intel/uncore_discovery.o
  CC      fs/proc/task_mmu.o
  CC      drivers/idle/intel_idle.o
  AR      drivers/char/ipmi/built-in.a
  CC      arch/x86/events/core.o
  CC [M]  sound/pci/hda/hda_hwdep.o
  CC      drivers/acpi/apei/apei-base.o
  CC      drivers/acpi/acpica/dsargs.o
  AR      drivers/acpi/pmic/built-in.a
  CC      drivers/acpi/dptf/int340x_thermal.o
  CC      net/core/flow_dissector.o
  CC      drivers/acpi/acpica/dscontrol.o
  CC      drivers/acpi/acpica/dsdebug.o
  CC      drivers/acpi/acpica/dsfield.o
  CC      drivers/acpi/acpica/dsinit.o
  CC      drivers/pci/pcie/dpc.o
  CC      crypto/cmac.o
  CC      mm/mmap_lock.o
  CC [M]  drivers/video/fbdev/core/modedb.o
  CC      kernel/locking/qrwlock.o
  CC      block/blk-mq-tag.o
  CC      io_uring/timeout.o
  CC      arch/x86/events/intel/cstate.o
  CC      block/blk-stat.o
  CC [M]  net/ipv4/netfilter/iptable_filter.o
  CC [M]  sound/core/control_led.o
  AR      sound/pci/ymfpci/built-in.a
  CC [M]  net/ipv4/netfilter/iptable_mangle.o
  CC      arch/x86/kernel/apic/x2apic_phys.o
  CC [M]  net/ipv4/netfilter/iptable_nat.o
  AR      drivers/acpi/dptf/built-in.a
  CC      lib/raid6/recov_avx512.o
  CC [M]  drivers/video/fbdev/core/fbcvt.o
  CC      net/xfrm/xfrm_policy.o
  CC      drivers/pci/hotplug/pci_hotplug_core.o
  CC      net/unix/af_unix.o
  CC      lib/zstd/compress/zstd_ldm.o
  CC      lib/zstd/compress/zstd_opt.o
  CC      kernel/power/qos.o
  CC      drivers/acpi/acpica/dsmethod.o
  CC      fs/kernfs/mount.o
  CC      net/xfrm/xfrm_state.o
  CC [M]  net/netfilter/ipvs/ip_vs_rr.o
  CC      net/xfrm/xfrm_hash.o
  CC      net/ethtool/wol.o
  AR      kernel/locking/built-in.a
  CC      net/xfrm/xfrm_input.o
  CC      crypto/hmac.o
  CC [M]  sound/pci/hda/hda_generic.o
  CC      drivers/acpi/apei/hest.o
  AR      drivers/pci/pcie/built-in.a
  CC      drivers/pnp/pnpacpi/core.o
  CC      drivers/pnp/pnpacpi/rsparser.o
  CC      fs/proc/inode.o
  AR      drivers/idle/built-in.a
  CC      arch/x86/kernel/apic/x2apic_cluster.o
  CC      drivers/pnp/core.o
  AR      sound/pci/vx222/built-in.a
  CC      net/xfrm/xfrm_output.o
  CC      kernel/sched/build_policy.o
  CC      net/xfrm/xfrm_sysctl.o
  TABLE   lib/raid6/tables.c
  CC      lib/raid6/int1.o
  CC      lib/raid6/int2.o
  CC      drivers/acpi/acpica/dsmthdat.o
  CC      drivers/acpi/acpica/dsobject.o
  CC      fs/proc/root.o
  CC [M]  sound/core/hwdep.o
  CC      arch/x86/kernel/cpu/intel_pconfig.o
  CC      arch/x86/kernel/head64.o
  CC      block/blk-mq-sysfs.o
  CC [M]  drivers/video/fbdev/core/fb_cmdline.o
  CC      net/ethtool/features.o
  CC      drivers/pci/hotplug/acpi_pcihp.o
  CC      io_uring/sqpoll.o
  CC      fs/kernfs/inode.o
  CC      arch/x86/kernel/cpu/tsx.o
  CC [M]  net/ipv4/netfilter/ipt_REJECT.o
  CC      drivers/acpi/apei/erst.o
  AR      drivers/pci/controller/dwc/built-in.a
  AR      drivers/pci/controller/mobiveil/built-in.a
  CC      drivers/pci/controller/vmd.o
  AR      drivers/pci/switch/built-in.a
  CC      arch/x86/kernel/ebda.o
  CC      arch/x86/kernel/cpu/intel_epb.o
  CC      kernel/power/main.o
  CC      mm/highmem.o
  CC      mm/memory.o
  CC      drivers/pci/hotplug/pciehp_core.o
  CC      drivers/acpi/acpica/dsopcode.o
  CC      arch/x86/kernel/apic/apic_flat_64.o
  CC      drivers/pci/access.o
  CC [M]  drivers/video/fbdev/core/fb_io_fops.o
  LD [M]  net/netfilter/ipvs/ip_vs.o
  CC      lib/raid6/int4.o
  CC      kernel/sched/build_utility.o
  CC      crypto/vmac.o
  CC [M]  net/netfilter/nf_conntrack_core.o
  CC      mm/mincore.o
  CC      fs/proc/base.o
  CC [M]  net/netfilter/nf_conntrack_standalone.o
  AR      drivers/pnp/pnpacpi/built-in.a
  CC      drivers/pnp/card.o
  CC [M]  sound/core/pcm.o
  CC [M]  arch/x86/kvm/i8259.o
  CC      drivers/pnp/driver.o
  CC      mm/mlock.o
  CC      mm/mmap.o
  AR      arch/x86/events/intel/built-in.a
  CC      arch/x86/events/probe.o
  CC      net/core/sysctl_net_core.o
  CC      arch/x86/kernel/cpu/amd.o
  CC      net/core/dev.o
  CC      fs/sysfs/file.o
  CC      net/xfrm/xfrm_replay.o
  CC      kernel/printk/printk.o
  CC      fs/kernfs/dir.o
  CC      drivers/acpi/acpica/dspkginit.o
  CC      kernel/printk/printk_safe.o
  CC      arch/x86/kernel/apic/probe_64.o
  CC      net/ethtool/privflags.o
  CC      net/xfrm/xfrm_device.o
  CC      arch/x86/events/utils.o
  CC      io_uring/fdinfo.o
  CC      net/ipv4/ip_input.o
  CC      drivers/pci/hotplug/pciehp_ctrl.o
  CC      lib/raid6/int8.o
  CC [M]  drivers/video/fbdev/core/fb_defio.o
  AR      arch/x86/kernel/apic/built-in.a
  CC      drivers/acpi/apei/bert.o
  CC      drivers/pnp/resource.o
  CC      fs/sysfs/dir.o
  AR      drivers/pci/controller/built-in.a
  CC      net/ethtool/rings.o
  CC      kernel/power/console.o
  CC      net/ethtool/channels.o
  CC      mm/mmu_gather.o
  CC      crypto/xcbc.o
  CC      crypto/crypto_null.o
  CC      drivers/acpi/acpica/dsutils.o
  CC      crypto/md5.o
  CC      fs/sysfs/symlink.o
  CC      fs/sysfs/mount.o
  CC [M]  sound/core/pcm_native.o
  CC      drivers/acpi/acpica/dswexec.o
  CC      net/xfrm/xfrm_algo.o
  CC      arch/x86/kernel/cpu/hygon.o
  CC      fs/sysfs/group.o
  CC      arch/x86/events/rapl.o
  CC      net/unix/garbage.o
  CC      crypto/sha1_generic.o
  CC      drivers/acpi/apei/ghes.o
  CC      net/unix/sysctl_net_unix.o
  CC      lib/zstd/zstd_decompress_module.o
  CC      lib/raid6/int16.o
  CC      crypto/sha256_generic.o
  CC      drivers/pci/hotplug/pciehp_pci.o
  CC      lib/zstd/decompress/huf_decompress.o
  CC [M]  drivers/video/fbdev/core/fb_chrdev.o
  CC      kernel/power/process.o
  CC      crypto/sha512_generic.o
  CC [M]  net/netfilter/nf_conntrack_expect.o
  CC      block/blk-mq-cpumap.o
  CC      arch/x86/kernel/platform-quirks.o
  CC      block/blk-mq-sched.o
  CC      fs/kernfs/file.o
  CC      net/ethtool/coalesce.o
  CC      drivers/acpi/acpica/dswload.o
  CC      drivers/pci/hotplug/pciehp_hpc.o
  CC      kernel/printk/printk_ringbuffer.o
  CC      arch/x86/kernel/cpu/centaur.o
  CC [M]  net/netfilter/nf_conntrack_helper.o
  CC      fs/configfs/inode.o
  CC      arch/x86/kernel/process_64.o
  CC      drivers/pnp/manager.o
  CC      fs/configfs/file.o
  CC      block/ioctl.o
  CC [M]  net/netfilter/nf_conntrack_proto.o
  CC      io_uring/tctx.o
  CC      net/ipv4/ip_fragment.o
  CC      net/ipv4/ip_forward.o
  AR      fs/sysfs/built-in.a
  CC      mm/mprotect.o
  CC      lib/raid6/int32.o
  CC      crypto/blake2b_generic.o
  CC [M]  arch/x86/kvm/irq.o
  CC      drivers/acpi/acpica/dswload2.o
  CC      kernel/printk/sysctl.o
  CC      arch/x86/events/msr.o
  CC      drivers/acpi/tables.o
  CC      mm/mremap.o
  CC      net/ipv4/ip_options.o
  CC      crypto/ecb.o
  CC      crypto/cbc.o
  CC      arch/x86/kernel/cpu/zhaoxin.o
  CC      net/unix/diag.o
  CC      drivers/pnp/support.o
  CC      net/xfrm/xfrm_user.o
  CC      fs/devpts/inode.o
  CC [M]  drivers/video/fbdev/core/fb_procfs.o
  CC      fs/proc/generic.o
  CC      fs/proc/array.o
  AR      kernel/printk/built-in.a
  CC [M]  sound/pci/hda/patch_realtek.o
  CC      arch/x86/kernel/cpu/perfctr-watchdog.o
  CC      kernel/power/suspend.o
  CC      fs/configfs/dir.o
  CC      fs/kernfs/symlink.o
  CC      block/genhd.o
  AR      drivers/acpi/apei/built-in.a
  CC      drivers/pnp/interface.o
  CC      lib/raid6/tables.o
  CC      drivers/acpi/acpica/dswscope.o
  AR      sound/spi/built-in.a
  CC      io_uring/poll.o
  AR      sound/parisc/built-in.a
  CC      net/ethtool/pause.o
  CC      drivers/acpi/blacklist.o
  AR      sound/pcmcia/vx/built-in.a
  AR      sound/pcmcia/pdaudiocf/built-in.a
  AR      sound/pcmcia/built-in.a
  CC      crypto/pcbc.o
  AR      net/ipv6/netfilter/built-in.a
  CC      drivers/pci/hotplug/acpiphp_core.o
  CC      net/ipv6/af_inet6.o
  CC [M]  net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
  CC      net/packet/af_packet.o
  CC [M]  net/ipv6/netfilter/nf_conntrack_reasm.o
  AR      arch/x86/events/built-in.a
  CC      arch/x86/kernel/signal.o
  CC      drivers/acpi/acpica/dswstate.o
  CC      net/ethtool/eee.o
  CC      block/ioprio.o
  CC      net/key/af_key.o
  AR      net/bridge/netfilter/built-in.a
  CC      net/bridge/br.o
  CC [M]  net/netfilter/nf_conntrack_proto_generic.o
  CC      net/unix/scm.o
  CC      lib/zstd/decompress/zstd_ddict.o
  CC      arch/x86/kernel/cpu/vmware.o
  AR      fs/kernfs/built-in.a
  CC [M]  drivers/video/fbdev/core/fbsysfs.o
  CC      arch/x86/kernel/cpu/hypervisor.o
  CC      fs/ext4/balloc.o
  AR      fs/devpts/built-in.a
  CC      arch/x86/kernel/signal_64.o
  CC      drivers/acpi/acpica/evevent.o
  CC      drivers/acpi/acpica/evgpe.o
  AR      net/dsa/built-in.a
  CC      fs/ext4/bitmap.o
  CC      drivers/pnp/quirks.o
  CC      crypto/cts.o
  CC      net/ethtool/tsinfo.o
  CC      drivers/acpi/acpica/evgpeblk.o
  CC      drivers/acpi/osi.o
  AR      lib/raid6/built-in.a
  CC [M]  sound/pci/hda/patch_analog.o
  CC [M]  net/netfilter/nf_conntrack_proto_tcp.o
  CC      kernel/power/hibernate.o
  CC      arch/x86/kernel/traps.o
  CC      mm/msync.o
  CC      arch/x86/kernel/cpu/mshyperv.o
  CC      drivers/pci/hotplug/acpiphp_glue.o
  CC [M]  sound/pci/hda/patch_hdmi.o
  CC      net/ipv4/ip_output.o
  CC      fs/proc/fd.o
  CC      kernel/power/snapshot.o
  CC      drivers/acpi/acpica/evgpeinit.o
  CC      fs/proc/cmdline.o
  CC      fs/proc/proc_tty.o
  CC      crypto/lrw.o
  CC      fs/configfs/symlink.o
  CC [M]  sound/core/pcm_lib.o
  CC      kernel/power/swap.o
  CC      drivers/acpi/acpica/evgpeutil.o
  CC      drivers/acpi/osl.o
  CC      block/badblocks.o
  CC      io_uring/cancel.o
  CC      io_uring/kbuf.o
  CC      fs/configfs/mount.o
  CC [M]  arch/x86/kvm/lapic.o
  CC      crypto/xts.o
  CC      fs/ext4/block_validity.o
  AR      net/unix/built-in.a
  CC      drivers/pnp/system.o
  CC [M]  net/sunrpc/auth_gss/auth_gss.o
  CC [M]  drivers/video/fbdev/core/fbcon.o
  CC [M]  net/sunrpc/auth_gss/gss_generic_token.o
  CC      net/sunrpc/clnt.o
  CC [M]  net/sunrpc/auth_gss/gss_mech_switch.o
  CC      net/bridge/br_device.o
  CC [M]  sound/core/pcm_misc.o
  CC      fs/ext4/dir.o
  CC      mm/page_vma_mapped.o
  CC [M]  net/sunrpc/auth_gss/svcauth_gss.o
  CC      net/ethtool/cabletest.o
  CC      arch/x86/kernel/cpu/capflags.o
  CC      fs/proc/consoles.o
  CC      drivers/acpi/acpica/evglock.o
  LD [M]  net/ipv6/netfilter/nf_defrag_ipv6.o
  AR      arch/x86/kernel/cpu/built-in.a
  CC      net/sunrpc/xprt.o
  CC      net/bridge/br_fdb.o
  CC [M]  sound/core/pcm_memory.o
  CC [M]  sound/core/memalloc.o
  CC      net/ipv6/anycast.o
  AR      drivers/pnp/built-in.a
  CC      arch/x86/kernel/idt.o
  CC [M]  sound/core/pcm_timer.o
  AR      drivers/amba/built-in.a
  CC      fs/configfs/item.o
  CC      net/bridge/br_forward.o
  CC      block/blk-rq-qos.o
  AR      drivers/pci/hotplug/built-in.a
  CC      drivers/pci/bus.o
  CC      drivers/pci/probe.o
  CC      mm/pagewalk.o
  CC      crypto/ctr.o
  CC      drivers/pci/host-bridge.o
  CC      drivers/pci/remove.o
  CC      drivers/acpi/acpica/evhandler.o
  CC      io_uring/rsrc.o
  CC      block/disk-events.o
  CC      lib/zstd/decompress/zstd_decompress.o
  CC      fs/proc/cpuinfo.o
  CC      net/8021q/vlan_core.o
  AR      net/xfrm/built-in.a
  CC      net/bridge/br_if.o
  AR      fs/configfs/built-in.a
  CC      net/ipv4/ip_sockglue.o
  CC      block/blk-ia-ranges.o
  CC      kernel/irq/irqdesc.o
  CC      kernel/rcu/update.o
  CC [M]  net/netfilter/nf_conntrack_proto_udp.o
  CC      kernel/irq/handle.o
  CC      kernel/power/user.o
  CC [M]  net/netfilter/nf_conntrack_proto_icmp.o
  CC      kernel/power/poweroff.o
  CC      arch/x86/kernel/irq.o
  CC      fs/ext4/ext4_jbd2.o
  CC      block/bsg.o
  CC      drivers/acpi/acpica/evmisc.o
  AR      kernel/sched/built-in.a
  CC      drivers/pci/pci.o
  CC      drivers/acpi/acpica/evregion.o
  CC      crypto/gcm.o
  CC [M]  net/netfilter/nf_conntrack_extend.o
  CC [M]  net/sunrpc/auth_gss/gss_rpc_upcall.o
  CC      net/ethtool/tunnels.o
  CC [M]  arch/x86/kvm/i8254.o
  CC      drivers/acpi/utils.o
  CC      fs/proc/devices.o
  CC      drivers/acpi/reboot.o
  CC      drivers/acpi/acpica/evrgnini.o
  CC [M]  arch/x86/kvm/ioapic.o
  LD [M]  sound/core/snd-ctl-led.o
  LD [M]  sound/core/snd-hwdep.o
  LD [M]  sound/core/snd-pcm.o
  AR      sound/core/built-in.a
  CC      block/bsg-lib.o
  AR      sound/mips/built-in.a
  CC      drivers/acpi/acpica/evsci.o
  AR      net/key/built-in.a
  CC      net/ethtool/fec.o
  CC      mm/pgtable-generic.o
  CC [M]  sound/pci/hda/hda_eld.o
  CC      drivers/acpi/acpica/evxface.o
  CC      drivers/acpi/acpica/evxfevnt.o
  AR      drivers/clk/actions/built-in.a
  AR      drivers/clk/analogbits/built-in.a
  CC      net/ipv6/ip6_output.o
  AR      drivers/clk/bcm/built-in.a
  AR      drivers/clk/imgtec/built-in.a
  CC      net/ipv6/ip6_input.o
  CC      net/ipv6/addrconf.o
  AR      drivers/clk/imx/built-in.a
  AR      drivers/clk/ingenic/built-in.a
  AR      drivers/clk/mediatek/built-in.a
  AR      drivers/clk/microchip/built-in.a
  AR      drivers/clk/mstar/built-in.a
  AR      drivers/clk/mvebu/built-in.a
  AR      drivers/clk/ralink/built-in.a
  CC      kernel/irq/manage.o
  CC      net/ipv4/inet_hashtables.o
  AR      drivers/clk/renesas/built-in.a
  AR      kernel/power/built-in.a
  AR      drivers/clk/socfpga/built-in.a
  CC      net/ipv4/inet_timewait_sock.o
  AR      drivers/clk/sprd/built-in.a
  AR      drivers/clk/starfive/built-in.a
  AR      drivers/clk/sunxi-ng/built-in.a
  AR      drivers/clk/ti/built-in.a
  AR      drivers/clk/versatile/built-in.a
  CC      block/blk-cgroup.o
  CC      block/blk-cgroup-rwstat.o
  CC      drivers/clk/x86/clk-lpss-atom.o
  CC [M]  drivers/video/fbdev/core/bitblit.o
  CC      kernel/rcu/sync.o
  CC      fs/proc/interrupts.o
  CC      net/bridge/br_input.o
  AR      drivers/clk/xilinx/built-in.a
  CC      drivers/clk/clk-devres.o
  CC      io_uring/rw.o
  CC [M]  net/8021q/vlan.o
  CC [M]  net/8021q/vlan_dev.o
  AR      sound/soc/built-in.a
  CC [M]  net/8021q/vlan_netlink.o
  AR      sound/atmel/built-in.a
  AR      sound/hda/built-in.a
  AR      sound/x86/built-in.a
  CC [M]  sound/hda/hda_bus_type.o
  CC [M]  net/8021q/vlanproc.o
  CC      drivers/acpi/acpica/evxfgpe.o
  CC      io_uring/opdef.o
  CC [M]  sound/hda/hdac_bus.o
  CC      kernel/rcu/srcutree.o
  CC      drivers/clk/x86/clk-pmc-atom.o
  CC [M]  net/netfilter/nf_conntrack_acct.o
  CC      net/packet/diag.o
  CC [M]  net/netfilter/nf_conntrack_seqadj.o
  CC      kernel/irq/spurious.o
  CC      mm/rmap.o
  CC [M]  net/sunrpc/auth_gss/gss_rpc_xdr.o
  AR      kernel/livepatch/built-in.a
  CC      crypto/pcrypt.o
  CC      mm/vmalloc.o
  CC      crypto/cryptd.o
  CC      fs/ext4/extents.o
  CC      fs/proc/loadavg.o
  CC      fs/proc/meminfo.o
  CC      fs/proc/stat.o
  CC      fs/proc/uptime.o
  AR      sound/xen/built-in.a
  CC [M]  net/sunrpc/auth_gss/trace.o
  CC [M]  sound/pci/hda/hda_intel.o
  CC      drivers/acpi/nvs.o
  CC      net/ethtool/eeprom.o
  CC      kernel/dma/mapping.o
  CC      kernel/entry/common.o
  CC [M]  arch/x86/kvm/irq_comm.o
  CC      drivers/acpi/acpica/evxfregn.o
  CC      kernel/entry/syscall_user_dispatch.o
  CC      io_uring/notif.o
  CC [M]  drivers/video/fbdev/core/softcursor.o
  CC      arch/x86/kernel/irq_64.o
  CC      io_uring/io-wq.o
  AR      drivers/clk/x86/built-in.a
  CC      drivers/clk/clk-bulk.o
  CC      drivers/acpi/wakeup.o
  CC      kernel/module/main.o
  CC      kernel/time/time.o
  CC      kernel/futex/core.o
  CC      net/ipv4/inet_connection_sock.o
  CC [M]  sound/hda/hdac_device.o
  CC      kernel/module/strict_rwx.o
  CC      kernel/futex/syscalls.o
  CC      net/bridge/br_ioctl.o
  CC [M]  arch/x86/kvm/cpuid.o
  CC      fs/proc/util.o
  CC      drivers/acpi/acpica/exconcat.o
  CC      crypto/des_generic.o
  CC      kernel/irq/resend.o
  CC      drivers/clk/clkdev.o
  CC      arch/x86/kernel/dumpstack_64.o
  CC      kernel/dma/direct.o
  CC      net/ipv6/addrlabel.o
  CC [M]  drivers/video/fbdev/core/tileblit.o
  AR      net/8021q/built-in.a
  LD [M]  net/8021q/8021q.o
  CC      kernel/rcu/tree.o
  AR      net/packet/built-in.a
  CC      drivers/clk/clk.o
  CC      net/dcb/dcbnl.o
  CC      drivers/clk/clk-divider.o
  CC      lib/zstd/decompress/zstd_decompress_block.o
  CC      net/dcb/dcbevent.o
  CC [M]  arch/x86/kvm/pmu.o
  CC      net/l3mdev/l3mdev.o
  CC      net/ethtool/stats.o
  CC      fs/ext4/extents_status.o
  CC [M]  net/netfilter/nf_conntrack_proto_icmpv6.o
  CC      kernel/entry/kvm.o
  CC [M]  net/netfilter/nf_conntrack_proto_dccp.o
  CC      drivers/clk/clk-fixed-factor.o
  CC      drivers/acpi/acpica/exconfig.o
  CC      net/core/dev_addr_lists.o
  CC      crypto/aes_generic.o
  CC      fs/proc/version.o
  CC      net/handshake/genl.o
  CC      drivers/clk/clk-fixed-rate.o
  CC      drivers/clk/clk-gate.o
  CC      kernel/irq/chip.o
  CC      block/blk-throttle.o
  CC      net/handshake/netlink.o
  CC      drivers/clk/clk-multiplier.o
  CC      arch/x86/kernel/time.o
  CC      net/ipv4/tcp.o
  CC [M]  sound/hda/hdac_sysfs.o
  CC      kernel/futex/pi.o
  CC      net/handshake/request.o
  CC      kernel/time/timer.o
  AR      sound/virtio/built-in.a
  CC      net/bridge/br_stp.o
  CC      drivers/pci/pci-driver.o
  CC      drivers/acpi/acpica/exconvrt.o
  LD [M]  sound/pci/hda/snd-hda-codec.o
  CC [M]  drivers/video/fbdev/core/cfbfillrect.o
  CC      drivers/clk/clk-mux.o
  CC      fs/proc/softirqs.o
  CC      kernel/dma/ops_helpers.o
  CC      drivers/pci/search.o
  CC [M]  net/bluetooth/af_bluetooth.o
  LD [M]  sound/pci/hda/snd-hda-codec-generic.o
  LD [M]  sound/pci/hda/snd-hda-codec-realtek.o
  CC      kernel/futex/requeue.o
  CC      mm/page_alloc.o
  LD [M]  sound/pci/hda/snd-hda-codec-analog.o
  LD [M]  sound/pci/hda/snd-hda-codec-hdmi.o
  CC      net/ethtool/phc_vclocks.o
  LD [M]  sound/pci/hda/snd-hda-intel.o
  CC      arch/x86/kernel/ioport.o
  AR      sound/pci/built-in.a
  AR      net/l3mdev/built-in.a
  CC      net/bridge/br_stp_bpdu.o
  CC      net/bridge/br_stp_if.o
  CC      net/bridge/br_stp_timer.o
  AR      kernel/entry/built-in.a
  CC      net/ethtool/mm.o
  AR      io_uring/built-in.a
  CC      mm/init-mm.o
  CC      net/ethtool/module.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_mech.o
  CC      drivers/acpi/acpica/excreate.o
  CC      net/ethtool/pse-pd.o
  CC      drivers/clk/clk-composite.o
  CC [M]  arch/x86/kvm/mtrr.o
  CC      kernel/cgroup/cgroup.o
  CC      fs/proc/namespaces.o
  CC [M]  arch/x86/kvm/hyperv.o
  CC [M]  net/netfilter/nf_conntrack_proto_sctp.o
  CC [M]  sound/hda/hdac_regmap.o
  CC      net/core/dst.o
  CC      drivers/clk/clk-fractional-divider.o
  CC      kernel/dma/dummy.o
  CC      crypto/deflate.o
  CC      kernel/futex/waitwake.o
  CC      kernel/irq/dummychip.o
  CC      net/bridge/br_netlink.o
  CC      arch/x86/kernel/dumpstack.o
  CC      net/ipv4/tcp_input.o
  CC [M]  drivers/video/fbdev/core/cfbcopyarea.o
  CC      arch/x86/kernel/nmi.o
  CC [M]  arch/x86/kvm/debugfs.o
  CC      drivers/acpi/acpica/exdebug.o
  CC      kernel/trace/trace_clock.o
  CC [M]  arch/x86/kvm/mmu/mmu.o
  CC      kernel/module/kmod.o
  CC      kernel/module/tree_lookup.o
  CC      block/mq-deadline.o
  CC [M]  drivers/video/fbdev/core/cfbimgblt.o
  AR      net/dcb/built-in.a
  CC [M]  net/netfilter/nf_conntrack_netlink.o
  CC      kernel/dma/contiguous.o
  CC      kernel/irq/devres.o
  CC      fs/proc/self.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_seal.o
  CC      net/bridge/br_netlink_tunnel.o
  CC      fs/ext4/file.o
  CC      fs/ext4/fsmap.o
  CC      fs/ext4/fsync.o
  CC      net/handshake/tlshd.o
  AR      kernel/futex/built-in.a
  CC      drivers/pci/pci-sysfs.o
  CC      net/handshake/trace.o
  CC      crypto/crc32c_generic.o
  CC [M]  net/dns_resolver/dns_key.o
  CC      drivers/dma/dw/core.o
  CC [M]  sound/hda/hdac_controller.o
  CC      drivers/dma/dw/dw.o
  CC      net/core/netevent.o
  CC [M]  net/bluetooth/hci_core.o
  CC      kernel/trace/ftrace.o
  CC      drivers/acpi/acpica/exdump.o
  CC      net/ethtool/plca.o
  CC      drivers/dma/dw/idma32.o
  CC      sound/sound_core.o
  CC      kernel/trace/ring_buffer.o
  CC      fs/jbd2/transaction.o
  CC      kernel/irq/autoprobe.o
  CC      fs/jbd2/commit.o
  CC      kernel/irq/irqdomain.o
  CC      fs/proc/thread_self.o
  CC      crypto/crct10dif_common.o
  CC      arch/x86/kernel/ldt.o
  CC      kernel/dma/swiotlb.o
  CC      drivers/acpi/acpica/exfield.o
  CC      fs/jbd2/recovery.o
  CC      kernel/module/debug_kmemleak.o
  CC      kernel/module/kallsyms.o
  CC      block/kyber-iosched.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_unseal.o
  CC      kernel/time/hrtimer.o
  CC [M]  net/dns_resolver/dns_query.o
  CC      fs/proc/proc_sysctl.o
  CC [M]  drivers/video/fbdev/core/sysfillrect.o
  CC      net/core/neighbour.o
  CC [M]  drivers/video/fbdev/core/syscopyarea.o
  CC      crypto/crct10dif_generic.o
  CC      net/ipv6/route.o
  CC      fs/ext4/hash.o
  CC [M]  sound/hda/hdac_stream.o
  CC      net/core/rtnetlink.o
  CC      kernel/trace/trace.o
  CC      kernel/trace/trace_output.o
  CC      drivers/acpi/acpica/exfldio.o
  CC      fs/ext4/ialloc.o
  CC      block/bfq-iosched.o
  CC      kernel/trace/trace_seq.o
  AR      net/ethtool/built-in.a
  CC      drivers/pci/rom.o
  CC      fs/ext4/indirect.o
  CC      net/sunrpc/socklib.o
  AR      net/handshake/built-in.a
  CC      drivers/acpi/acpica/exmisc.o
  CC      kernel/bpf/core.o
  CC      drivers/clk/clk-gpio.o
  CC      drivers/dma/dw/acpi.o
  CC [M]  net/bluetooth/hci_conn.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_seqnum.o
  LD [M]  net/dns_resolver/dns_resolver.o
  CC      crypto/authenc.o
  CC      lib/zstd/zstd_common_module.o
  CC      net/bridge/br_arp_nd_proxy.o
  CC      kernel/module/procfs.o
  CC      fs/ext4/inline.o
  CC      arch/x86/kernel/setup.o
  CC [M]  net/netfilter/nf_nat_core.o
  CC      lib/zstd/common/debug.o
  CC      fs/jbd2/checkpoint.o
  CC      net/devres.o
  CC      drivers/acpi/acpica/exmutex.o
  CC      drivers/acpi/acpica/exnames.o
  CC      kernel/irq/proc.o
  CC      net/socket.o
  CC      fs/ext4/inode.o
  CC [M]  drivers/video/fbdev/core/sysimgblt.o
  CC      kernel/dma/remap.o
  CC      lib/zstd/common/entropy_common.o
  AR      drivers/clk/built-in.a
  CC      kernel/irq/migration.o
  CC      drivers/pci/setup-res.o
  CC      kernel/irq/cpuhotplug.o
  CC [M]  sound/hda/array.o
  CC      drivers/dma/dw/pci.o
  CC      fs/jbd2/revoke.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_wrap.o
  CC      lib/zstd/common/error_private.o
  CC      kernel/module/sysfs.o
  CC      lib/zstd/common/fse_decompress.o
  CC      kernel/time/timekeeping.o
  CC      fs/jbd2/journal.o
  CC      block/bfq-wf2q.o
  CC      drivers/pci/irq.o
  CC      drivers/acpi/acpica/exoparg1.o
  CC      net/bridge/br_sysfs_if.o
  CC      kernel/events/core.o
  CC      crypto/authencesn.o
  CC      net/ipv4/tcp_output.o
  AR      kernel/dma/built-in.a
  CC      kernel/events/ring_buffer.o
  CC [M]  arch/x86/kvm/mmu/page_track.o
  CC      fs/proc/proc_net.o
  CC      kernel/time/ntp.o
  CC      kernel/trace/trace_stat.o
  CC      arch/x86/kernel/x86_init.o
  CC      kernel/irq/pm.o
  CC [M]  sound/hda/hdmi_chmap.o
  AR      drivers/dma/dw/built-in.a
  CC      kernel/time/clocksource.o
  CC      net/bridge/br_sysfs_br.o
  CC      drivers/dma/hsu/hsu.o
  CC      drivers/pci/vpd.o
  CC [M]  drivers/video/fbdev/core/fb_sys_fops.o
  AR      drivers/dma/idxd/built-in.a
  CC      crypto/lzo.o
  CC      kernel/rcu/rcu_segcblist.o
  CC      drivers/acpi/acpica/exoparg2.o
  CC      net/sunrpc/xprtsock.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_crypto.o
  AR      kernel/module/built-in.a
  CC      arch/x86/kernel/i8259.o
  CC      kernel/time/jiffies.o
  CC      fs/proc/kcore.o
  CC      kernel/irq/msi.o
  CC      lib/zstd/common/zstd_common.o
  AR      lib/zstd/built-in.a
  CC      lib/buildid.o
  CC      arch/x86/kernel/irqinit.o
  CC      kernel/trace/trace_printk.o
  CC      net/ipv6/ip6_fib.o
  CC [M]  net/netfilter/nf_nat_proto.o
  CC      kernel/irq/affinity.o
  CC      net/ipv6/ipv6_sockglue.o
  CC      drivers/pci/setup-bus.o
  CC      kernel/trace/pid_list.o
  CC      kernel/events/callchain.o
  CC      arch/x86/kernel/jump_label.o
  CC      drivers/acpi/acpica/exoparg3.o
  CC      drivers/acpi/acpica/exoparg6.o
  CC [M]  sound/hda/trace.o
  CC      crypto/lzo-rle.o
  CC      mm/memblock.o
  CC      net/compat.o
  AR      kernel/rcu/built-in.a
  CC      kernel/irq/matrix.o
  CC      kernel/fork.o
  LD [M]  drivers/video/fbdev/core/fb.o
  CC      kernel/cgroup/rstat.o
  CC      fs/ext4/ioctl.o
  CC      kernel/events/hw_breakpoint.o
  AR      drivers/dma/hsu/built-in.a
  AR      drivers/dma/mediatek/built-in.a
  CC      crypto/lz4.o
  AR      drivers/dma/qcom/built-in.a
  AR      drivers/video/fbdev/core/built-in.a
  AR      drivers/dma/ti/built-in.a
  AR      drivers/dma/xilinx/built-in.a
  AR      drivers/video/fbdev/omap2/omapfb/dss/built-in.a
  AR      drivers/video/fbdev/omap2/omapfb/displays/built-in.a
  CC [M]  drivers/dma/ioat/init.o
  AR      drivers/video/fbdev/omap2/omapfb/built-in.a
  CC [M]  drivers/dma/ioat/dma.o
  AR      drivers/video/fbdev/omap2/built-in.a
  CC [M]  drivers/video/fbdev/uvesafb.o
  CC      kernel/time/timer_list.o
  CC      lib/cmdline.o
  CC [M]  drivers/dma/ioat/prep.o
  CC [M]  drivers/dma/ioat/dca.o
  CC      drivers/acpi/acpica/exprep.o
  CC      fs/proc/kmsg.o
  CC      mm/memory_hotplug.o
  AR      kernel/bpf/built-in.a
  CC      drivers/pci/vc.o
  CC      drivers/pci/mmap.o
  CC      lib/cpumask.o
  CC      crypto/lz4hc.o
  CC      net/bridge/br_nf_core.o
  CC [M]  net/sunrpc/auth_gss/gss_krb5_keys.o
  CC      arch/x86/kernel/irq_work.o
  CC      kernel/trace/trace_sched_switch.o
  CC      net/bridge/br_multicast.o
  CC      kernel/exec_domain.o
  CC [M]  net/bluetooth/hci_event.o
  CC      kernel/trace/trace_functions.o
  CC      drivers/dma/dmaengine.o
  CC [M]  sound/hda/hdac_component.o
  CC      drivers/acpi/acpica/exregion.o
  CC      fs/proc/page.o
  CC      block/bfq-cgroup.o
  CC      kernel/time/timeconv.o
  CC      kernel/cgroup/namespace.o
  CC      kernel/events/uprobes.o
  CC      crypto/xxhash_generic.o
  CC      arch/x86/kernel/probe_roms.o
  CC      mm/madvise.o
  CC      lib/ctype.o
  CC      lib/dec_and_lock.o
  CC      lib/decompress.o
  CC      drivers/pci/setup-irq.o
  LD [M]  net/sunrpc/auth_gss/auth_rpcgss.o
  CC      lib/decompress_bunzip2.o
  CC      kernel/time/timecounter.o
  CC [M]  sound/hda/hdac_i915.o
  CC      kernel/panic.o
  CC      net/sysctl_net.o
  CC      drivers/acpi/acpica/exresnte.o
  AR      kernel/irq/built-in.a
  CC      kernel/time/alarmtimer.o
  CC      drivers/acpi/acpica/exresolv.o
  CC      mm/page_io.o
  CC      mm/swap_state.o
  CC      arch/x86/kernel/sys_ia32.o
  CC      kernel/time/posix-timers.o
  CC      kernel/time/posix-cpu-timers.o
  CC      kernel/time/posix-clock.o
  CC [M]  net/netfilter/nf_nat_helper.o
  LD [M]  net/sunrpc/auth_gss/rpcsec_gss_krb5.o
  CC      crypto/rng.o
  CC [M]  net/netfilter/nf_nat_redirect.o
  CC      kernel/trace/trace_preemptirq.o
  CC [M]  net/netfilter/nf_nat_masquerade.o
  CC [M]  drivers/dma/ioat/sysfs.o
  CC      kernel/trace/trace_nop.o
  AR      fs/jbd2/built-in.a
  CC      net/core/utils.o
  CC      net/core/link_watch.o
  CC      kernel/cgroup/cgroup-v1.o
  CC      sound/last.o
  CC      kernel/trace/trace_functions_graph.o
  CC      net/ipv6/ndisc.o
  CC      drivers/acpi/sleep.o
  CC [M]  net/netfilter/x_tables.o
  CC      net/bridge/br_mdb.o
  CC      drivers/pci/proc.o
  CC      drivers/acpi/acpica/exresop.o
  AR      fs/proc/built-in.a
  CC [M]  net/bluetooth/mgmt.o
  CC [M]  drivers/video/fbdev/simplefb.o
  CC      block/blk-mq-pci.o
  AR      drivers/video/fbdev/built-in.a
  CC      net/ipv6/udp.o
  CC      net/bridge/br_multicast_eht.o
  CC [M]  sound/hda/intel-dsp-config.o
  CC      drivers/pci/slot.o
  CC      fs/ramfs/inode.o
  CC      lib/decompress_inflate.o
  CC      net/ipv6/udplite.o
  CC      fs/ramfs/file-mmu.o
  CC      mm/swapfile.o
  CC      drivers/pci/pci-acpi.o
  CC      crypto/drbg.o
  LD [M]  drivers/dma/ioat/ioatdma.o
  CC      block/blk-mq-virtio.o
  CC      drivers/dma/virt-dma.o
  CC      arch/x86/kernel/signal_32.o
  CC      net/sunrpc/sched.o
  CC [M]  net/netfilter/xt_tcpudp.o
  CC      net/sunrpc/auth.o
  CC      drivers/acpi/acpica/exserial.o
  CC      mm/swap_slots.o
  CC      drivers/acpi/acpica/exstore.o
  CC      drivers/pci/quirks.o
  CC      mm/dmapool.o
  CC      net/ipv4/tcp_timer.o
  CC      arch/x86/kernel/sys_x86_64.o
  CC      lib/decompress_unlz4.o
  CC      block/blk-mq-debugfs.o
  CC [M]  net/netfilter/xt_mark.o
  CC      net/core/filter.o
  CC [M]  sound/hda/intel-nhlt.o
  CC      net/ipv4/tcp_ipv4.o
  CC      mm/hugetlb.o
  CC      mm/hugetlb_vmemmap.o
  CC      net/core/sock_diag.o
  AR      drivers/video/built-in.a
  AR      fs/ramfs/built-in.a
  CC      kernel/trace/fgraph.o
  CC      net/bridge/br_vlan.o
  CC      kernel/trace/blktrace.o
  CC      net/ipv4/tcp_minisocks.o
  CC [M]  sound/hda/intel-sdw-acpi.o
  CC      drivers/acpi/device_sysfs.o
  CC      drivers/pci/ats.o
  CC      block/blk-pm.o
  CC      kernel/time/itimer.o
  CC      kernel/cgroup/freezer.o
  CC      drivers/dma/acpi-dma.o
  CC      fs/hugetlbfs/inode.o
  CC      drivers/acpi/acpica/exstoren.o
  CC      kernel/time/clockevents.o
  CC      fs/ext4/mballoc.o
  CC      block/holder.o
  CC [M]  arch/x86/kvm/mmu/spte.o
  CC      net/sunrpc/auth_null.o
  CC      lib/decompress_unlzma.o
  CC      mm/sparse.o
  CC      mm/sparse-vmemmap.o
  CC      drivers/pci/iov.o
  CC      kernel/cgroup/legacy_freezer.o
  CC      kernel/cgroup/pids.o
  CC      drivers/pci/pci-label.o
  CC      arch/x86/kernel/espfix_64.o
  LD [M]  sound/hda/snd-hda-core.o
  CC      drivers/acpi/acpica/exstorob.o
  LD [M]  sound/hda/snd-intel-dspcfg.o
  LD [M]  sound/hda/snd-intel-sdw-acpi.o
  CC [M]  net/netfilter/xt_nat.o
  AR      sound/built-in.a
  CC      fs/ext4/migrate.o
  CC      crypto/jitterentropy.o
  CC      kernel/cgroup/cpuset.o
  CC [M]  net/netfilter/xt_REDIRECT.o
  CC      drivers/acpi/device_pm.o
  CC      drivers/acpi/proc.o
  CC      net/ipv6/raw.o
  CC      net/sunrpc/auth_unix.o
  CC      crypto/jitterentropy-kcapi.o
  CC      net/sunrpc/svc.o
  AR      drivers/soc/apple/built-in.a
  AR      drivers/soc/aspeed/built-in.a
  AR      drivers/soc/bcm/bcm63xx/built-in.a
  AR      drivers/soc/bcm/built-in.a
  AR      drivers/soc/fsl/built-in.a
  AR      drivers/dma/built-in.a
  AR      drivers/soc/fujitsu/built-in.a
  AR      block/built-in.a
  AR      drivers/soc/imx/built-in.a
  CC      drivers/virtio/virtio.o
  CC      drivers/virtio/virtio_ring.o
  AR      drivers/soc/ixp4xx/built-in.a
  CC      crypto/ghash-generic.o
  AR      drivers/soc/loongson/built-in.a
  CC      kernel/trace/trace_events.o
  AR      drivers/soc/mediatek/built-in.a
  AR      drivers/soc/microchip/built-in.a
  CC      drivers/tty/vt/vt_ioctl.o
  AR      drivers/soc/nuvoton/built-in.a
  AR      drivers/soc/pxa/built-in.a
  AR      drivers/soc/amlogic/built-in.a
  AR      drivers/soc/qcom/built-in.a
  AR      drivers/soc/renesas/built-in.a
  CC      drivers/acpi/acpica/exsystem.o
  AR      drivers/soc/rockchip/built-in.a
  CC      drivers/char/hw_random/core.o
  CC      kernel/time/tick-common.o
  CC      drivers/char/agp/backend.o
  AR      drivers/soc/sifive/built-in.a
  AR      drivers/soc/sunxi/built-in.a
  AR      drivers/soc/ti/built-in.a
  AR      drivers/soc/xilinx/built-in.a
  CC      lib/decompress_unlzo.o
  AR      drivers/soc/built-in.a
  CC      drivers/char/hw_random/intel-rng.o
  CC      drivers/char/agp/generic.o
  CC      crypto/af_alg.o
  CC [M]  arch/x86/kvm/mmu/tdp_iter.o
  CC      fs/ext4/mmp.o
  CC      fs/ext4/move_extent.o
  CC      fs/fat/cache.o
  CC      arch/x86/kernel/ksysfs.o
  CC      fs/nfs/client.o
  CC      fs/exportfs/expfs.o
  CC      mm/mmu_notifier.o
  CC      fs/lockd/clntlock.o
  CC      fs/lockd/clntproc.o
  CC      fs/lockd/clntxdr.o
  CC      drivers/acpi/acpica/extrace.o
  CC      net/ipv4/tcp_cong.o
  CC      fs/fat/dir.o
  AR      fs/hugetlbfs/built-in.a
  CC      net/sunrpc/svcsock.o
  CC      fs/ext4/namei.o
  CC      drivers/pci/pci-stub.o
  CC      lib/decompress_unxz.o
  CC      kernel/cpu.o
  CC      net/ipv4/tcp_metrics.o
  CC      net/ipv4/tcp_fastopen.o
  CC      fs/nls/nls_base.o
  CC      drivers/char/agp/isoch.o
  CC      net/ipv4/tcp_rate.o
  AR      drivers/char/hw_random/built-in.a
  CC      drivers/char/agp/intel-agp.o
  CC      drivers/acpi/acpica/exutils.o
  CC      drivers/char/tpm/tpm-chip.o
  CC      arch/x86/kernel/bootflag.o
  CC      drivers/char/agp/intel-gtt.o
  AR      fs/exportfs/built-in.a
  CC      drivers/char/mem.o
  CC [M]  net/netfilter/xt_MASQUERADE.o
  AR      fs/unicode/built-in.a
  CC      net/ipv4/tcp_recovery.o
  CC      net/bridge/br_vlan_tunnel.o
  CC      kernel/time/tick-broadcast.o
  CC      drivers/tty/vt/vc_screen.o
  CC [M]  arch/x86/kvm/mmu/tdp_mmu.o
  CC      drivers/virtio/virtio_anchor.o
  CC      lib/decompress_unzstd.o
  CC      fs/ext4/page-io.o
  CC      drivers/pci/vgaarb.o
  CC      fs/fat/fatent.o
  CC      fs/nls/nls_cp437.o
  CC      net/bridge/br_vlan_options.o
  CC      net/bridge/br_mst.o
  CC      drivers/acpi/acpica/hwacpi.o
  CC      fs/lockd/host.o
  CC      drivers/char/tpm/tpm-dev-common.o
  CC      arch/x86/kernel/e820.o
  CC      kernel/time/tick-broadcast-hrtimer.o
  CC [M]  arch/x86/kvm/smm.o
  CC      drivers/acpi/acpica/hwesleep.o
  CC      fs/nls/nls_ascii.o
  AR      drivers/iommu/amd/built-in.a
  CC      drivers/iommu/intel/dmar.o
  CC      lib/dump_stack.o
  CC      drivers/virtio/virtio_pci_modern_dev.o
  CC      drivers/iommu/intel/iommu.o
  CC      kernel/trace/trace_export.o
  CC      lib/earlycpio.o
  AR      drivers/iommu/arm/arm-smmu/built-in.a
  CC      net/ipv6/icmp.o
  CC      drivers/char/tpm/tpm-dev.o
  AR      drivers/iommu/arm/arm-smmu-v3/built-in.a
  AR      drivers/iommu/arm/built-in.a
  CC      crypto/algif_hash.o
  CC      net/ipv6/mcast.o
  CC      arch/x86/kernel/pci-dma.o
  CC      drivers/tty/vt/selection.o
  CC      kernel/trace/trace_event_perf.o
  CC [M]  net/netfilter/xt_addrtype.o
  CC      kernel/time/tick-oneshot.o
  CC      fs/nfs/dir.o
  CC      kernel/trace/trace_events_filter.o
  AR      drivers/gpu/host1x/built-in.a
  AR      drivers/char/agp/built-in.a
  AR      drivers/gpu/drm/tests/built-in.a
  CC [M]  drivers/gpu/drm/tests/drm_kunit_helpers.o
  CC      fs/nls/nls_iso8859-1.o
  CC [M]  net/netfilter/xt_conntrack.o
  CC      fs/lockd/svc.o
  CC [M]  net/bluetooth/hci_sock.o
  CC      kernel/trace/trace_events_trigger.o
  CC      drivers/acpi/acpica/hwgpe.o
  CC      fs/nls/nls_utf8.o
  CC      crypto/algif_skcipher.o
  AR      drivers/gpu/drm/arm/built-in.a
  AR      drivers/gpu/drm/display/built-in.a
  CC [M]  drivers/gpu/drm/display/drm_display_helper_mod.o
  CC      kernel/trace/trace_eprobe.o
  CC      lib/extable.o
  CC      net/ipv4/tcp_ulp.o
  AR      drivers/gpu/vga/built-in.a
  CC      net/ipv4/tcp_offload.o
  AR      kernel/events/built-in.a
  CC      fs/fat/file.o
  AR      drivers/iommu/iommufd/built-in.a
  CC      crypto/xor.o
  CC      kernel/exit.o
  AR      drivers/pci/built-in.a
  CC      kernel/time/tick-sched.o
  CC      fs/fat/inode.o
  CC      net/ipv4/tcp_plb.o
  CC      drivers/char/tpm/tpm-interface.o
  CC      drivers/iommu/iommu.o
  CC [M]  net/bridge/br_netfilter_hooks.o
  AR      kernel/cgroup/built-in.a
  CC      drivers/virtio/virtio_pci_legacy_dev.o
  CC      drivers/char/tpm/tpm1-cmd.o
  CC [M]  drivers/gpu/drm/tests/drm_buddy_test.o
  AR      fs/nls/built-in.a
  CC      fs/ntfs/aops.o
  CC      fs/ntfs/attrib.o
  CC [M]  drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
  CC      mm/ksm.o
  CC      drivers/acpi/acpica/hwregs.o
  CC      arch/x86/kernel/quirks.o
  CC      drivers/tty/vt/keyboard.o
  CC      drivers/char/tpm/tpm2-cmd.o
  CC      drivers/char/tpm/tpmrm-dev.o
  CC      lib/flex_proportions.o
  CC      kernel/time/vsyscall.o
  CC      fs/autofs/init.o
  CC      net/sunrpc/svcauth.o
  CC      kernel/time/timekeeping_debug.o
  CC      net/sunrpc/svcauth_unix.o
  CC      kernel/softirq.o
  CC      drivers/virtio/virtio_mmio.o
  CC [M]  net/netfilter/xt_ipvs.o
  CC      lib/idr.o
  CC      drivers/acpi/acpica/hwsleep.o
  CC [M]  net/bridge/br_netfilter_ipv6.o
  CC      crypto/hash_info.o
  CC      fs/lockd/svclock.o
  CC      drivers/char/tpm/tpm2-space.o
  CC      crypto/simd.o
  CC [M]  crypto/md4.o
  CC [M]  arch/x86/kvm/vmx/vmx.o
  CC      fs/autofs/inode.o
  CC      drivers/tty/vt/consolemap.o
  CC      drivers/connector/cn_queue.o
  CC      drivers/connector/connector.o
  CC      arch/x86/kernel/topology.o
  CC      fs/fat/misc.o
  HOSTCC  drivers/tty/vt/conmakehash
  CC [M]  drivers/gpu/drm/display/drm_dp_helper.o
  CC      mm/slub.o
  CC      kernel/time/namespace.o
  CC      fs/fat/nfs.o
  CC      mm/migrate.o
  CC      drivers/connector/cn_proc.o
  CC [M]  drivers/gpu/drm/tests/drm_cmdline_parser_test.o
  CC      drivers/virtio/virtio_pci_modern.o
  CC      drivers/iommu/intel/pasid.o
  CC      drivers/acpi/acpica/hwvalid.o
  CC      kernel/trace/trace_kprobe.o
  CC      fs/ntfs/collate.o
  CC      fs/fat/namei_vfat.o
  CC      fs/ntfs/compress.o
  CC      net/ipv4/datagram.o
  CC      kernel/resource.o
  CC      lib/irq_regs.o
  CC      kernel/sysctl.o
  CC      fs/ext4/readpage.o
  CC      fs/ext4/resize.o
  CC [M]  crypto/ccm.o
  CC      arch/x86/kernel/kdebugfs.o
  CC      fs/ext4/super.o
  CC      lib/is_single_threaded.o
  CC      fs/autofs/root.o
  CC      drivers/acpi/acpica/hwxface.o
  CC [M]  net/bluetooth/hci_sysfs.o
  CC      drivers/char/tpm/tpm-sysfs.o
  CC      fs/autofs/symlink.o
  CC      fs/fat/namei_msdos.o
  CC      arch/x86/kernel/alternative.o
  AR      kernel/time/built-in.a
  CC [M]  net/bluetooth/l2cap_core.o
  CC [M]  net/bluetooth/l2cap_sock.o
  CC      drivers/tty/vt/vt.o
  COPY    drivers/tty/vt/defkeymap.c
  CC [M]  net/bluetooth/smp.o
  LD [M]  net/netfilter/nf_conntrack.o
  CC      drivers/acpi/acpica/hwxfsleep.o
  CC      drivers/virtio/virtio_pci_common.o
  CC      arch/x86/kernel/i8253.o
  CC      lib/klist.o
  LD [M]  net/netfilter/nf_nat.o
  CC      drivers/virtio/virtio_pci_legacy.o
  CC      fs/autofs/waitq.o
  CC      kernel/capability.o
  AR      net/netfilter/built-in.a
  CC      arch/x86/kernel/hw_breakpoint.o
  CC      lib/kobject.o
  AR      net/bridge/built-in.a
  CC      lib/kobject_uevent.o
  CC [M]  net/bluetooth/lib.o
  CC [M]  drivers/virtio/virtio_mem.o
  CC      fs/lockd/svcshare.o
  CC      drivers/char/tpm/eventlog/common.o
  CC      drivers/char/tpm/eventlog/tpm1.o
  AR      drivers/connector/built-in.a
  CC      fs/lockd/svcproc.o
  LD [M]  net/bridge/br_netfilter.o
  CC      drivers/iommu/intel/trace.o
  CC      drivers/iommu/intel/cap_audit.o
  CC      drivers/acpi/acpica/hwpci.o
  CC      drivers/acpi/acpica/nsaccess.o
  CC      mm/migrate_device.o
  CC      lib/logic_pio.o
  CC [M]  arch/x86/kvm/kvm-asm-offsets.s
  CC      drivers/char/tpm/eventlog/tpm2.o
  CC      fs/ntfs/debug.o
  CC      net/ipv4/raw.o
  CC [M]  crypto/arc4.o
  CC      fs/ext4/symlink.o
  CC      drivers/acpi/acpica/nsalloc.o
  CC      net/sunrpc/addr.o
  AR      fs/fat/built-in.a
  CC      arch/x86/kernel/tsc.o
  CC      net/sunrpc/rpcb_clnt.o
  AR      fs/hostfs/built-in.a
  CC      net/sunrpc/timer.o
  CC      fs/autofs/expire.o
  CC      net/sunrpc/xdr.o
  CC      fs/nfs/file.o
  CC      drivers/tty/hvc/hvc_console.o
  CC      lib/maple_tree.o
  CC      lib/memcat_p.o
  CC      lib/nmi_backtrace.o
  CC      lib/plist.o
  CC      lib/radix-tree.o
  CC [M]  drivers/gpu/drm/tests/drm_connector_test.o
  CC      fs/ext4/sysfs.o
  CC [M]  drivers/gpu/drm/display/drm_dp_mst_topology.o
  CC [M]  crypto/ecc.o
  CC      net/ipv6/reassembly.o
  CC      drivers/char/tpm/tpm_ppi.o
  CC      drivers/acpi/bus.o
  CC      fs/ntfs/dir.o
  CC      fs/ntfs/file.o
  CC      drivers/acpi/acpica/nsarguments.o
  CC      net/ipv6/tcp_ipv6.o
  CC      fs/ext4/xattr.o
  CC      drivers/base/power/sysfs.o
  CC      drivers/block/loop.o
  CC      mm/huge_memory.o
  CC      fs/ext4/xattr_hurd.o
  CC      lib/ratelimit.o
  CC      fs/ext4/xattr_trusted.o
  CC      kernel/trace/error_report-traces.o
  CC      arch/x86/kernel/tsc_msr.o
  CC      mm/khugepaged.o
  CC      drivers/char/tpm/eventlog/acpi.o
  CC      kernel/trace/power-traces.o
  CC      drivers/iommu/intel/irq_remapping.o
  CC      fs/lockd/svcsubs.o
  CC      fs/ext4/xattr_user.o
  CC      fs/autofs/dev-ioctl.o
  CC [M]  drivers/gpu/drm/display/drm_dsc_helper.o
  CC      drivers/acpi/acpica/nsconvert.o
  CC [M]  arch/x86/kvm/vmx/pmu_intel.o
  CC [M]  drivers/gpu/drm/tests/drm_damage_helper_test.o
  CC      drivers/char/random.o
  CC      net/sunrpc/sunrpc_syms.o
  CC      drivers/char/misc.o
  CC      drivers/block/virtio_blk.o
  CC      kernel/trace/rpm-traces.o
  CC      drivers/iommu/intel/perfmon.o
  CC      arch/x86/kernel/io_delay.o
  CC      fs/lockd/mon.o
  CC      drivers/base/power/generic_ops.o
  AR      drivers/tty/hvc/built-in.a
  CC      fs/ext4/fast_commit.o
  CC      drivers/tty/serial/8250/8250_core.o
  AR      drivers/tty/ipwireless/built-in.a
  CC      drivers/tty/serial/8250/8250_pnp.o
  CC      drivers/tty/serial/8250/8250_port.o
  CC      drivers/char/tpm/eventlog/efi.o
  AR      drivers/virtio/built-in.a
  CC      drivers/tty/serial/8250/8250_dma.o
  CC      arch/x86/kernel/rtc.o
  CC      fs/ext4/orphan.o
  CC      drivers/acpi/acpica/nsdump.o
  CC      drivers/acpi/glue.o
  CC      drivers/acpi/acpica/nseval.o
  CC      lib/rbtree.o
  CC      fs/ntfs/index.o
  CC      net/core/dev_ioctl.o
  AR      fs/autofs/built-in.a
  CC      fs/debugfs/inode.o
  CC      drivers/base/power/common.o
  CC      net/ipv4/udp.o
  CC [M]  drivers/gpu/drm/tests/drm_dp_mst_helper_test.o
  CC      drivers/acpi/acpica/nsinit.o
  CC      kernel/ptrace.o
  CC      kernel/user.o
  CC      drivers/char/tpm/tpm_crb.o
  CC      net/core/tso.o
  CONMK   drivers/tty/vt/consolemap_deftbl.c
  CC      drivers/tty/serial/8250/8250_dwlib.o
  CC      drivers/tty/vt/defkeymap.o
  CC      drivers/base/power/qos.o
  CC      drivers/acpi/acpica/nsload.o
  CC [M]  net/bluetooth/ecdh_helper.o
  CC      drivers/tty/serial/8250/8250_pcilib.o
  CC [M]  drivers/gpu/drm/tests/drm_format_helper_test.o
  CC      net/sunrpc/cache.o
  CC      drivers/base/power/runtime.o
  CC      arch/x86/kernel/resource.o
  CC      fs/nfs/getroot.o
  CC      drivers/tty/vt/consolemap_deftbl.o
  CC      drivers/iommu/iommu-traces.o
  AR      drivers/tty/vt/built-in.a
  CC      fs/debugfs/file.o
  CC      fs/lockd/trace.o
  CC      drivers/tty/serial/8250/8250_pci.o
  CC [M]  crypto/essiv.o
  AS      arch/x86/kernel/irqflags.o
  CC      drivers/tty/serial/8250/8250_exar.o
  CC      arch/x86/kernel/static_call.o
  CC      drivers/acpi/acpica/nsnames.o
  CC [M]  drivers/block/nbd.o
  CC [M]  arch/x86/kvm/vmx/vmcs12.o
  CC      kernel/trace/trace_dynevent.o
  CC      drivers/base/power/wakeirq.o
  CC      drivers/tty/serial/8250/8250_early.o
  CC      fs/ntfs/inode.o
  CC      drivers/acpi/scan.o
  CC      mm/page_counter.o
  CC      drivers/tty/serial/8250/8250_dw.o
  AR      drivers/iommu/intel/built-in.a
  CC      drivers/tty/tty_io.o
  CC      fs/nfs/inode.o
  AR      drivers/gpu/drm/renesas/rcar-du/built-in.a
  AR      drivers/gpu/drm/renesas/built-in.a
  CC      drivers/char/virtio_console.o
  CC      drivers/char/hpet.o
  CC      drivers/acpi/acpica/nsobject.o
  CC [M]  drivers/gpu/drm/tests/drm_format_test.o
  CC [M]  drivers/gpu/drm/display/drm_hdcp_helper.o
  CC      drivers/tty/n_tty.o
  CC      fs/tracefs/inode.o
  CC      drivers/tty/tty_ioctl.o
  CC      arch/x86/kernel/process.o
  CC      drivers/tty/tty_ldisc.o
  CC      net/sunrpc/rpc_pipe.o
  AR      drivers/char/tpm/built-in.a
  CC      drivers/char/nvram.o
  AR      drivers/gpu/drm/omapdrm/built-in.a
  CC      fs/btrfs/super.o
  CC      kernel/signal.o
  CC      fs/lockd/xdr.o
  CC      drivers/base/power/main.o
  CC      net/core/sock_reuseport.o
  CC      drivers/acpi/acpica/nsparse.o
  CC      drivers/base/power/wakeup.o
  CC [M]  drivers/gpu/drm/tests/drm_framebuffer_test.o
  CC      drivers/iommu/iommu-sysfs.o
  CC      fs/pstore/inode.o
  CC [M]  crypto/ecdh.o
  CC      net/ipv6/ping.o
  CC      fs/efivarfs/inode.o
  CC [M]  fs/netfs/buffered_read.o
  CC      kernel/trace/trace_probe.o
  CC      fs/efivarfs/file.o
  AR      fs/debugfs/built-in.a
  CC [M]  arch/x86/kvm/vmx/hyperv.o
  CC [M]  arch/x86/kvm/vmx/nested.o
  CC      net/ipv6/exthdrs.o
  CC [M]  drivers/gpu/drm/display/drm_hdmi_helper.o
  CC      drivers/tty/serial/8250/8250_lpss.o
  CC [M]  fs/fscache/cache.o
  AR      fs/tracefs/built-in.a
  CC      drivers/acpi/acpica/nspredef.o
  CC [M]  fs/fscache/cookie.o
  CC      net/ipv6/datagram.o
  CC      drivers/tty/serial/8250/8250_mid.o
  CC [M]  fs/smb/common/cifs_arc4.o
  CC [M]  fs/smb/client/trace.o
  CC [M]  drivers/gpu/drm/tests/drm_managed_test.o
  CC [M]  fs/fuse/dev.o
  CC [M]  fs/overlayfs/super.o
  CC [M]  fs/fuse/dir.o
  CC [M]  fs/smb/client/cifsfs.o
  CC [M]  crypto/ecdh_helper.o
  CC      drivers/base/power/wakeup_stats.o
  CC      fs/efivarfs/super.o
  CC      drivers/iommu/dma-iommu.o
  CC      fs/ntfs/mft.o
  CC      fs/pstore/platform.o
  CC      drivers/acpi/acpica/nsprepkg.o
  AR      drivers/char/built-in.a
  CC [M]  fs/smb/common/cifs_md4.o
  CC      mm/memcontrol.o
  AR      drivers/misc/eeprom/built-in.a
  CC [M]  drivers/gpu/drm/display/drm_scdc_helper.o
  CC      drivers/mfd/mfd-core.o
  AR      drivers/misc/cb710/built-in.a
  AR      drivers/misc/ti-st/built-in.a
  AR      drivers/misc/lis3lv02d/built-in.a
  AR      drivers/misc/cardreader/built-in.a
  CC [M]  drivers/misc/mei/hdcp/mei_hdcp.o
  CC      fs/lockd/clnt4xdr.o
  CC      drivers/mfd/intel-lpss.o
  CC      drivers/acpi/acpica/nsrepair.o
  CC [M]  drivers/gpu/drm/tests/drm_mm_test.o
  LD [M]  crypto/ecdh_generic.o
  AR      crypto/built-in.a
  CC      arch/x86/kernel/ptrace.o
  CC [M]  fs/netfs/io.o
  CC [M]  fs/netfs/iterator.o
  CC      fs/efivarfs/vars.o
  CC      lib/seq_buf.o
  CC      kernel/sys.o
  CC      kernel/umh.o
  CC      drivers/tty/serial/8250/8250_pericom.o
  CC      drivers/base/power/domain.o
  CC      drivers/base/power/domain_governor.o
  CC [M]  fs/netfs/main.o
  CC [M]  arch/x86/kvm/vmx/posted_intr.o
  CC      net/core/fib_notifier.o
  CC      net/core/xdp.o
  CC      fs/lockd/xdr4.o
  CC      kernel/workqueue.o
  CC      drivers/tty/tty_buffer.o
  CC      fs/pstore/pmsg.o
  CC      net/sunrpc/sysfs.o
  CC [M]  net/bluetooth/hci_request.o
  CC      kernel/trace/trace_uprobe.o
  CC      drivers/acpi/acpica/nsrepair2.o
  CC      fs/ntfs/mst.o
  CC [M]  drivers/gpu/drm/display/drm_dp_aux_dev.o
  CC      drivers/mfd/intel-lpss-pci.o
  CC      lib/show_mem.o
  CC      drivers/mfd/intel-lpss-acpi.o
  CC [M]  fs/netfs/objects.o
  CC      lib/siphash.o
  AR      drivers/block/built-in.a
  CC      fs/nfs/super.o
  CC [M]  fs/fscache/io.o
  AR      drivers/tty/serial/8250/built-in.a
  CC      drivers/tty/serial/serial_core.o
  CC [M]  drivers/misc/mei/pxp/mei_pxp.o
  AR      fs/efivarfs/built-in.a
  CC [M]  fs/overlayfs/namei.o
  CC      drivers/tty/serial/earlycon.o
  CC [M]  fs/overlayfs/util.o
  CC      drivers/mfd/intel_soc_pmic_crc.o
  AR      fs/pstore/built-in.a
  CC      kernel/pid.o
  CC      drivers/acpi/acpica/nssearch.o
  CC      drivers/iommu/iova.o
  CC      kernel/task_work.o
  CC      drivers/acpi/acpica/nsutils.o
  CC      kernel/trace/rethook.o
  CC      net/ipv4/udplite.o
  CC [M]  fs/fscache/main.o
  CC      arch/x86/kernel/tls.o
  CC      fs/ntfs/namei.o
  AR      drivers/nfc/built-in.a
  AR      drivers/dax/hmem/built-in.a
  CC      drivers/dma-buf/dma-buf.o
  CC      drivers/dax/super.o
  CC      drivers/dax/bus.o
  CC      drivers/dma-buf/dma-fence.o
  CC      drivers/dma-buf/dma-fence-array.o
  CC      lib/string.o
  CC      net/ipv6/ip6_flowlabel.o
  CC      fs/ntfs/runlist.o
  CC      drivers/tty/tty_port.o
  CC [M]  fs/fuse/file.o
  LD [M]  arch/x86/kvm/kvm.o
  CC      fs/lockd/svc4proc.o
  UPD     arch/x86/kvm/kvm-asm-offsets.h
  CC      drivers/acpi/acpica/nswalk.o
  CC      drivers/acpi/acpica/nsxfeval.o
  CC [M]  drivers/misc/mei/init.o
  LD [M]  fs/netfs/netfs.o
  LD [M]  drivers/gpu/drm/display/drm_display_helper.o
  CC      kernel/extable.o
  CC      lib/timerqueue.o
  CC      net/sunrpc/svc_xprt.o
  CC      lib/vsprintf.o
  CC      net/core/flow_offload.o
  CC [M]  drivers/mfd/lpc_sch.o
  CC      fs/ntfs/super.o
  CC      fs/ntfs/sysctl.o
  CC      drivers/acpi/resource.o
  CC      lib/win_minmax.o
  CC      fs/ntfs/unistr.o
  CC      net/core/gro.o
  CC [M]  net/bluetooth/mgmt_util.o
  CC      net/core/netdev-genl.o
  CC      fs/open.o
  CC      drivers/base/power/clock_ops.o
  CC      net/core/netdev-genl-gen.o
  CC      drivers/dma-buf/dma-fence-chain.o
  CC      arch/x86/kernel/step.o
  CC      drivers/iommu/irq_remapping.o
  CC [M]  drivers/gpu/drm/tests/drm_modes_test.o
  AS [M]  arch/x86/kvm/vmx/vmenter.o
  CC [M]  fs/overlayfs/inode.o
  CC      drivers/acpi/acpica/nsxfname.o
  AR      drivers/cxl/core/built-in.a
  AR      drivers/cxl/built-in.a
  CC      lib/xarray.o
  AR      drivers/macintosh/built-in.a
  CC      lib/lockref.o
  CC      drivers/dma-buf/dma-fence-unwrap.o
  CC      arch/x86/kernel/i8237.o
  CC      net/ipv4/udp_offload.o
  CC      kernel/params.o
  CC      fs/ntfs/upcase.o
  CC      lib/bcd.o
  CC      lib/sort.o
  CC [M]  drivers/misc/mei/hbm.o
  CC [M]  fs/overlayfs/file.o
  CC [M]  fs/smb/client/cifs_debug.o
  CC [M]  fs/fscache/volume.o
  CC [M]  fs/fscache/proc.o
  CC      fs/nfs/io.o
  CC      drivers/dma-buf/dma-resv.o
  CC [M]  drivers/mfd/lpc_ich.o
  CC      drivers/dma-buf/sync_file.o
  CC [M]  fs/overlayfs/dir.o
  AR      kernel/trace/built-in.a
  CC      arch/x86/kernel/stacktrace.o
  AR      drivers/dax/built-in.a
  CC      net/sunrpc/xprtmultipath.o
  CC      mm/vmpressure.o
  CC      drivers/dma-buf/sw_sync.o
  CC      drivers/acpi/acpica/nsxfobj.o
  CC      net/core/net-sysfs.o
  CC      kernel/kthread.o
  CC      drivers/dma-buf/sync_debug.o
  CC      drivers/scsi/scsi.o
  CC [M]  drivers/gpu/drm/tests/drm_plane_helper_test.o
  AR      drivers/base/power/built-in.a
  CC [M]  drivers/gpu/drm/tests/drm_probe_helper_test.o
  CC      drivers/scsi/hosts.o
  AR      drivers/iommu/built-in.a
  CC [M]  drivers/dma-buf/selftest.o
  CC      drivers/base/firmware_loader/builtin/main.o
  CC      fs/lockd/procfs.o
  CC [M]  drivers/gpu/drm/tests/drm_rect_test.o
  CC      arch/x86/kernel/reboot.o
  CC      drivers/tty/tty_mutex.o
  CC      net/ipv6/inet6_connection_sock.o
  CC      drivers/tty/tty_ldsem.o
  CC [M]  net/bluetooth/mgmt_config.o
  CC      drivers/acpi/acpica/psargs.o
  AR      drivers/base/firmware_loader/builtin/built-in.a
  CC [M]  net/bluetooth/hci_codec.o
  CC      drivers/base/firmware_loader/main.o
  CC [M]  net/bluetooth/eir.o
  CC      drivers/tty/serial/serial_mctrl_gpio.o
  CC      arch/x86/kernel/msr.o
  CC      fs/btrfs/ctree.o
  CC [M]  fs/overlayfs/readdir.o
  CC      kernel/sys_ni.o
  AR      fs/ntfs/built-in.a
  CC      fs/read_write.o
  CC      fs/btrfs/extent-tree.o
  CC [M]  drivers/dma-buf/st-dma-fence.o
  AR      drivers/mfd/built-in.a
  CC      drivers/acpi/acpica/psloop.o
  CC      drivers/acpi/acpica/psobject.o
  CC      arch/x86/kernel/cpuid.o
  CC      fs/nfs/direct.o
  CC      net/ipv6/udp_offload.o
  LD [M]  fs/fscache/fscache.o
  CC [M]  drivers/dma-buf/st-dma-fence-chain.o
  CC      fs/file_table.o
  AR      fs/lockd/built-in.a
  CC [M]  drivers/dma-buf/st-dma-fence-unwrap.o
  CC      net/ipv6/seg6.o
  CC      fs/nfs/pagelist.o
  CC      fs/nfs/read.o
  CC [M]  drivers/misc/mei/interrupt.o
  AR      drivers/gpu/drm/tilcdc/built-in.a
  AR      drivers/gpu/drm/imx/built-in.a
  CC      mm/swap_cgroup.o
  AR      drivers/gpu/drm/i2c/built-in.a
  AR      drivers/gpu/drm/panel/built-in.a
  CC      mm/hugetlb_cgroup.o
  AR      drivers/gpu/drm/bridge/analogix/built-in.a
  CC      drivers/scsi/scsi_ioctl.o
  AR      drivers/gpu/drm/bridge/cadence/built-in.a
  CC      fs/super.o
  AR      drivers/gpu/drm/bridge/imx/built-in.a
  CC      mm/kmemleak.o
  AR      drivers/gpu/drm/bridge/synopsys/built-in.a
  AR      drivers/gpu/drm/bridge/built-in.a
  AR      drivers/gpu/drm/hisilicon/built-in.a
  AR      drivers/gpu/drm/mxsfb/built-in.a
  AR      drivers/gpu/drm/tiny/built-in.a
  CC      net/ipv4/arp.o
  AR      drivers/gpu/drm/xlnx/built-in.a
  AR      drivers/gpu/drm/gud/built-in.a
  CC [M]  fs/overlayfs/copy_up.o
  AR      drivers/gpu/drm/solomon/built-in.a
  CC      mm/page_isolation.o
  CC [M]  drivers/gpu/drm/ttm/ttm_tt.o
  CC [M]  drivers/gpu/drm/ttm/ttm_bo.o
  CC      mm/early_ioremap.o
  CC [M]  fs/fuse/inode.o
  CC [M]  fs/fuse/control.o
  CC [M]  drivers/dma-buf/st-dma-resv.o
  AR      drivers/tty/serial/built-in.a
  CC      drivers/tty/tty_baudrate.o
  CC      drivers/acpi/acpica/psopcode.o
  CC      drivers/tty/tty_jobctrl.o
  CC      arch/x86/kernel/early-quirks.o
  CC [M]  drivers/gpu/drm/scheduler/sched_main.o
  AR      fs/ext4/built-in.a
  CC      drivers/scsi/scsicam.o
  CC [M]  fs/smb/client/connect.o
  CC [M]  fs/smb/client/dir.o
  CC [M]  fs/smb/client/file.o
  CC      kernel/nsproxy.o
  AR      drivers/dma-buf/built-in.a
  CC [M]  fs/smb/client/inode.o
  CC      net/sunrpc/stats.o
  AR      drivers/base/firmware_loader/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.o
  CC      drivers/base/regmap/regmap.o
  CC      fs/char_dev.o
  CC      fs/stat.o
  CC [M]  net/bluetooth/hci_sync.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_device.o
  CC      drivers/base/regmap/regcache.o
  CC      drivers/acpi/acpica/psopinfo.o
  CC [M]  fs/smb/client/link.o
  CC      lib/parser.o
  CC [M]  fs/overlayfs/export.o
  CC [M]  drivers/misc/mei/client.o
  CC [M]  fs/smb/client/misc.o
  LD [M]  drivers/dma-buf/dmabuf_selftests.o
  LD [M]  arch/x86/kvm/kvm-intel.o
  CC      net/core/page_pool.o
  CC [M]  drivers/misc/mei/main.o
  CC      drivers/tty/n_null.o
  CC      net/ipv6/fib6_notifier.o
  CC      drivers/tty/pty.o
  CC [M]  net/bluetooth/coredump.o
  CC [M]  drivers/gpu/drm/scheduler/sched_fence.o
  CC      net/sunrpc/sysctl.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.o
  CC      drivers/scsi/scsi_error.o
  CC      fs/exec.o
  CC      drivers/tty/sysrq.o
  CC      lib/debug_locks.o
  CC      arch/x86/kernel/smp.o
  CC      drivers/acpi/acpica/psparse.o
  CC      drivers/base/regmap/regcache-rbtree.o
  CC      kernel/notifier.o
  CC      kernel/ksysfs.o
  CC [M]  drivers/gpu/drm/ttm/ttm_bo_util.o
  CC      fs/pipe.o
  CC      lib/random32.o
  CC      fs/namei.o
  CC      mm/cma.o
  CC [M]  drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.o
  CC      fs/fcntl.o
  CC      mm/secretmem.o
  CC      mm/userfaultfd.o
  CC [M]  drivers/gpu/drm/ttm/ttm_bo_vm.o
  LD [M]  fs/overlayfs/overlay.o
  CC      fs/nfs/symlink.o
  CC      drivers/base/regmap/regcache-flat.o
  CC      fs/btrfs/print-tree.o
  CC [M]  fs/fuse/xattr.o
  CC      arch/x86/kernel/smpboot.o
  CC      drivers/acpi/acpica/psscope.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.o
  CC      drivers/acpi/acpica/pstree.o
  CC [M]  drivers/gpu/drm/scheduler/sched_entity.o
  CC      lib/bust_spinlocks.o
  CC      kernel/cred.o
  CC [M]  net/bluetooth/sco.o
  LD [M]  drivers/gpu/drm/amd/amdxcp/amdxcp.o
  CC      net/ipv6/rpl.o
  CC [M]  drivers/gpu/drm/i915/i915_driver.o
  CC      net/ipv6/ioam6.o
  CC      net/ipv4/icmp.o
  CC      net/ipv4/devinet.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_bo_test.o
  CC [M]  drivers/misc/mei/dma-ring.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_dma_buf_test.o
  AR      net/sunrpc/built-in.a
  AR      drivers/tty/built-in.a
  CC      net/ipv6/sysctl_net_ipv6.o
  CC      drivers/nvme/host/core.o
  CC [M]  drivers/gpu/drm/xe/xe_bb.o
  CC      drivers/acpi/acpica/psutils.o
  CC [M]  drivers/gpu/drm/xe/xe_bo.o
  CC      drivers/nvme/host/ioctl.o
  CC      drivers/base/regmap/regcache-maple.o
  CC [M]  drivers/gpu/drm/xe/xe_bo_evict.o
  CC      net/core/net-procfs.o
  CC      kernel/reboot.o
  CC [M]  drivers/gpu/drm/i915/i915_drm_client.o
  CC [M]  drivers/gpu/drm/ttm/ttm_module.o
  CC      lib/kasprintf.o
  CC [M]  fs/fuse/acl.o
  CC [M]  drivers/misc/mei/bus.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_migrate_test.o
  CC      drivers/base/regmap/regmap-debugfs.o
  AR      drivers/nvme/target/built-in.a
  CC [M]  drivers/gpu/drm/xe/tests/xe_pci_test.o
  CC      drivers/acpi/acpica/pswalk.o
  CC      drivers/scsi/scsi_lib.o
  CC      fs/nfs/unlink.o
  CC      fs/nfs/write.o
  CC      fs/ioctl.o
  CC [M]  drivers/misc/mei/bus-fixup.o
  CC      net/ipv4/af_inet.o
  LD [M]  drivers/gpu/drm/scheduler/gpu-sched.o
  CC      lib/bitmap.o
  CC [M]  drivers/gpu/drm/ttm/ttm_execbuf_util.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_rtp_test.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/atombios_crtc.o
  CC      lib/scatterlist.o
  CC [M]  drivers/gpu/drm/xe/xe_debugfs.o
  CC      mm/memremap.o
  CC      drivers/nvme/host/trace.o
  CC [M]  fs/smb/client/netmisc.o
  CC      kernel/async.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_wa_test.o
  CC      mm/hmm.o
  CC      drivers/nvme/host/fault_inject.o
  CC      drivers/acpi/acpica/psxface.o
  CC [M]  fs/fuse/readdir.o
  CC      arch/x86/kernel/tsc_sync.o
  CC      fs/btrfs/root-tree.o
  CC      kernel/range.o
  CC      net/ipv6/xfrm6_policy.o
  CC      net/core/netpoll.o
  CC [M]  drivers/gpu/drm/xe/xe_devcoredump.o
  CC      net/core/fib_rules.o
  CC      fs/readdir.o
  CC      net/ipv6/xfrm6_state.o
  CC      drivers/base/regmap/regmap-i2c.o
  CC      drivers/nvme/host/pci.o
  CC [M]  drivers/gpu/drm/xe/xe_device.o
  CC [M]  drivers/gpu/drm/ttm/ttm_range_manager.o
  CC      kernel/smpboot.o
  CC      arch/x86/kernel/setup_percpu.o
  CC [M]  drivers/misc/mei/debugfs.o
  CC      drivers/acpi/acpica/rsaddr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.o
  CC      net/ipv4/igmp.o
  CC [M]  drivers/gpu/drm/vgem/vgem_drv.o
  CC [M]  drivers/gpu/drm/i915/i915_config.o
  CC [M]  drivers/gpu/drm/i915/i915_getparam.o
  CC [M]  drivers/misc/mei/mei-trace.o
  AR      drivers/misc/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_device_sysfs.o
  CC      kernel/ucount.o
  CC [M]  drivers/gpu/drm/xe/xe_dma_buf.o
  CC      fs/select.o
  CC      drivers/base/regmap/regmap-irq.o
  CC      lib/list_sort.o
  CC [M]  drivers/gpu/drm/i915/i915_ioctl.o
  CC      net/ipv6/xfrm6_input.o
  CC      mm/memfd.o
  CC      net/core/net-traces.o
  CC      lib/uuid.o
  CC      drivers/acpi/acpica/rscalc.o
  CC      lib/iov_iter.o
  CC [M]  drivers/gpu/drm/i915/i915_irq.o
  CC [M]  fs/fuse/ioctl.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/atom.o
  CC      drivers/acpi/acpica/rscreate.o
  CC      drivers/acpi/acpica/rsdumpinfo.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/object.o
  CC      arch/x86/kernel/ftrace.o
  CC [M]  drivers/gpu/drm/ttm/ttm_resource.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/client.o
  CC      drivers/acpi/acpica/rsinfo.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.o
  CC      net/ipv4/fib_frontend.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/conn.o
  CC      net/ipv6/xfrm6_output.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/device.o
  CC      kernel/regset.o
  CC [M]  drivers/gpu/drm/vgem/vgem_fence.o
  CC      fs/btrfs/dir-item.o
  CC [M]  net/bluetooth/iso.o
  AS      arch/x86/kernel/ftrace_64.o
  CC      fs/dcache.o
  CC      drivers/acpi/acpi_processor.o
  CC      fs/inode.o
  CC      fs/attr.o
  CC [M]  net/bluetooth/a2mp.o
  CC      fs/nfs/namespace.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.o
  CC      drivers/acpi/acpica/rsio.o
  CC      arch/x86/kernel/trace_clock.o
  CC [M]  drivers/misc/mei/pci-me.o
  CC      fs/bad_inode.o
  CC [M]  drivers/gpu/drm/xe/xe_exec.o
  CC      drivers/scsi/scsi_lib_dma.o
  CC [M]  drivers/gpu/drm/i915/i915_mitigations.o
  CC [M]  drivers/gpu/drm/i915/i915_module.o
  CC [M]  drivers/gpu/drm/xe/xe_execlist.o
  CC      kernel/groups.o
  CC [M]  fs/smb/client/smbencrypt.o
  CC [M]  drivers/gpu/drm/i915/i915_params.o
  CC      mm/bootmem_info.o
  CC      net/ipv4/fib_semantics.o
  LD [M]  fs/fuse/fuse.o
  CC      drivers/acpi/acpica/rsirq.o
  CC      arch/x86/kernel/trace.o
  CC      drivers/acpi/acpica/rslist.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/disp.o
  CC [M]  drivers/gpu/drm/i915/i915_pci.o
  CC [M]  fs/smb/client/transport.o
  LD [M]  drivers/gpu/drm/vgem/vgem.o
  CC      net/core/selftests.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_object.o
  CC [M]  net/bluetooth/amp.o
  AR      drivers/base/regmap/built-in.a
  AR      drivers/base/test/built-in.a
  CC      drivers/base/component.o
  CC [M]  net/bluetooth/hci_debugfs.o
  CC [M]  drivers/gpu/drm/ttm/ttm_pool.o
  CC      net/ipv4/fib_trie.o
  CC [M]  drivers/gpu/drm/ast/ast_drv.o
  CC      lib/clz_ctz.o
  CC      drivers/scsi/scsi_scan.o
  CC [M]  drivers/misc/mei/hw-me.o
  GEN     drivers/scsi/scsi_devinfo_tbl.c
  CC      drivers/scsi/scsi_devinfo.o
  CC      net/ipv4/fib_notifier.o
  CC      drivers/gpu/drm/drm_mipi_dsi.o
  CC [M]  drivers/gpu/drm/ast/ast_i2c.o
  CC [M]  drivers/gpu/drm/i915/i915_scatterlist.o
  CC      drivers/acpi/acpica/rsmemory.o
  AR      mm/built-in.a
  CC      arch/x86/kernel/rethook.o
  CC      drivers/acpi/acpica/rsmisc.o
  CC [M]  drivers/gpu/drm/xe/xe_exec_queue.o
  CC [M]  drivers/gpu/drm/xe/xe_force_wake.o
  CC      kernel/vhost_task.o
  CC      net/ipv6/xfrm6_protocol.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.o
  CC      fs/btrfs/file-item.o
  CC      fs/nfs/mount_clnt.o
  CC [M]  drivers/gpu/drm/i915/i915_suspend.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_display.o
  CC      drivers/scsi/scsi_sysctl.o
  CC      drivers/ata/libata-core.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/driver.o
  CC      drivers/ata/libata-scsi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.o
  CC      arch/x86/kernel/crash_core_64.o
  CC      drivers/base/core.o
  AR      drivers/nvme/host/built-in.a
  AR      drivers/nvme/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_ggtt.o
  CC      fs/file.o
  CC      drivers/scsi/scsi_debugfs.o
  CC      fs/nfs/nfstrace.o
  CC      kernel/kcmp.o
  CC      drivers/ata/libata-eh.o
  CC [M]  drivers/gpu/drm/ttm/ttm_device.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.o
  CC      drivers/acpi/acpica/rsserial.o
  CC [M]  drivers/gpu/drm/i915/i915_switcheroo.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.o
  CC      arch/x86/kernel/module.o
  CC [M]  drivers/gpu/drm/ast/ast_main.o
  CC [M]  drivers/gpu/drm/ast/ast_mm.o
  CC [M]  fs/smb/client/cached_dir.o
  CC      drivers/acpi/acpica/rsutils.o
  CC      drivers/scsi/scsi_trace.o
  CC      fs/nfs/export.o
  CC [M]  drivers/gpu/drm/i915/i915_sysfs.o
  CC      drivers/scsi/scsi_logging.o
  CC [M]  drivers/gpu/drm/drm_aperture.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.o
  CC      arch/x86/kernel/early_printk.o
  CC      arch/x86/kernel/hpet.o
  CC      drivers/scsi/scsi_pm.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/event.o
  CC [M]  drivers/gpu/drm/ast/ast_mode.o
  CC      net/ipv4/inet_fragment.o
  CC [M]  drivers/gpu/drm/ast/ast_post.o
  CC      drivers/acpi/acpica/rsxface.o
  CC      drivers/acpi/acpica/tbdata.o
  CC      lib/bsearch.o
  CC      lib/find_bit.o
  CC      fs/nfs/sysfs.o
  CC      kernel/freezer.o
  LD [M]  net/bluetooth/bluetooth.o
  CC      kernel/stacktrace.o
  CC [M]  drivers/gpu/drm/drm_atomic.o
  CC      net/ipv6/netfilter.o
  CC      net/ipv6/fib6_rules.o
  CC      kernel/dma.o
  CC [M]  drivers/gpu/drm/ttm/ttm_sys_manager.o
  CC      kernel/smp.o
  CC [M]  drivers/gpu/drm/xe/xe_gt.o
  CC [M]  drivers/gpu/drm/drm_atomic_uapi.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/fifo.o
  CC      fs/filesystems.o
  CC [M]  drivers/gpu/drm/ttm/ttm_agp_backend.o
  CC [M]  drivers/misc/mei/gsc-me.o
  CC [M]  fs/smb/client/cifs_unicode.o
  CC      drivers/spi/spi.o
  CC      drivers/net/phy/mdio-boardinfo.o
  CC      drivers/net/phy/mdio_devres.o
  AR      drivers/net/pse-pd/built-in.a
  CC      drivers/scsi/scsi_bsg.o
  CC      drivers/net/mdio/acpi_mdio.o
  AR      drivers/net/pcs/built-in.a
  CC      drivers/scsi/scsi_common.o
  CC      net/ipv4/ping.o
  CC      drivers/acpi/acpica/tbfadt.o
  CC      lib/llist.o
  CC      lib/memweight.o
  AR      drivers/firewire/built-in.a
  CC      net/ipv6/proc.o
  CC      lib/kfifo.o
  CC      drivers/net/mdio/fwnode_mdio.o
  CC [M]  drivers/gpu/drm/i915/i915_utils.o
  LD [M]  drivers/misc/mei/mei.o
  CC      drivers/scsi/sd.o
  CC      fs/btrfs/inode-item.o
  CC [M]  fs/smb/client/nterr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_bios.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/head.o
  LD [M]  drivers/misc/mei/mei-me.o
  CC      fs/btrfs/disk-io.o
  CC [M]  drivers/gpu/drm/i915/intel_clock_gating.o
  CC [M]  drivers/gpu/drm/i915/intel_device_info.o
  CC      net/ipv6/syncookies.o
  CC      drivers/ata/libata-transport.o
  CC      arch/x86/kernel/amd_nb.o
  LD [M]  drivers/gpu/drm/ttm/ttm.o
  CC [M]  drivers/gpu/drm/drm_auth.o
  CC      fs/btrfs/transaction.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.o
  CC [M]  fs/smb/client/cifsencrypt.o
  CC      kernel/uid16.o
  CC [M]  drivers/gpu/drm/drm_blend.o
  LD [M]  drivers/misc/mei/mei-gsc.o
  CC      drivers/scsi/sg.o
  CC      drivers/acpi/acpica/tbfind.o
  CC      fs/nfs/fs_context.o
  AR      drivers/net/ethernet/adi/built-in.a
  AR      drivers/net/ethernet/alacritech/built-in.a
  CC      drivers/net/phy/phy.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/mem.o
  AR      drivers/net/ethernet/amazon/built-in.a
  AR      drivers/net/ethernet/aquantia/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_gt_clock.o
  AR      drivers/net/ethernet/asix/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_gt_debugfs.o
  CC [M]  fs/smb/client/readdir.o
  AR      drivers/net/ethernet/cadence/built-in.a
  CC      drivers/acpi/acpica/tbinstal.o
  AR      drivers/net/ethernet/broadcom/built-in.a
  CC [M]  drivers/net/ethernet/broadcom/b44.o
  CC      drivers/net/phy/phy-c45.o
  CC [M]  drivers/gpu/drm/i915/intel_memory_region.o
  AR      drivers/net/ethernet/cavium/common/built-in.a
  AR      drivers/net/ethernet/cavium/thunder/built-in.a
  AR      drivers/net/ethernet/cavium/liquidio/built-in.a
  AR      drivers/net/ethernet/cavium/octeon/built-in.a
  AR      drivers/net/ethernet/cortina/built-in.a
  AR      drivers/net/ethernet/cavium/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/atombios_dp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.o
  AR      drivers/net/mdio/built-in.a
  CC      fs/btrfs/inode.o
  CC      lib/percpu-refcount.o
  CC      fs/btrfs/file.o
  CC      net/ipv6/mip6.o
  CC      net/ipv4/ip_tunnel_core.o
  CC [M]  drivers/gpu/drm/ast/ast_dp501.o
  CC [M]  drivers/gpu/drm/i915/intel_pcode.o
  CC      kernel/kallsyms.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/mmu.o
  CC      net/ipv4/gre_offload.o
  CC      net/core/ptp_classifier.o
  CC      drivers/ata/libata-trace.o
  CC [M]  drivers/gpu/drm/i915/intel_region_ttm.o
  CC      drivers/acpi/acpica/tbprint.o
  CC      arch/x86/kernel/kvm.o
  CC [M]  drivers/gpu/drm/drm_bridge.o
  CC      kernel/acct.o
  CC      kernel/crash_core.o
  CC [M]  drivers/gpu/drm/drm_cache.o
  CC      drivers/scsi/scsi_sysfs.o
  CC [M]  drivers/gpu/drm/ast/ast_dp.o
  CC      kernel/compat.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_idle_sysfs.o
  CC      fs/btrfs/defrag.o
  CC [M]  drivers/net/ethernet/broadcom/bnx2.o
  CC      drivers/base/bus.o
  CC [M]  drivers/gpu/drm/i915/intel_runtime_pm.o
  CC      net/ipv6/addrconf_core.o
  CC      drivers/acpi/acpica/tbutils.o
  CC      lib/rhashtable.o
  CC      lib/base64.o
  CC      drivers/ata/libata-sata.o
  CC [M]  drivers/net/ethernet/broadcom/cnic.o
  CC      lib/once.o
  CC      kernel/utsname.o
  CC      net/core/netprio_cgroup.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/outp.o
  CC      fs/namespace.o
  CC      kernel/user_namespace.o
  CC [M]  drivers/gpu/drm/drm_client.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_mcr.o
  CC      drivers/acpi/acpica/tbxface.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_pagefault.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/atombios_encoders.o
  CC [M]  drivers/net/ethernet/broadcom/tg3.o
  CC [M]  drivers/gpu/drm/i915/intel_sbi.o
  CC      drivers/net/phy/phy-core.o
  CC      net/core/dst_cache.o
  CC      lib/refcount.o
  CC      drivers/acpi/processor_core.o
  CC      net/ipv6/exthdrs_core.o
  CC      drivers/net/phy/phy_device.o
  AR      drivers/cdrom/built-in.a
  CC      drivers/acpi/acpica/tbxfload.o
  LD [M]  drivers/gpu/drm/ast/ast.o
  CC      kernel/pid_namespace.o
  AR      drivers/auxdisplay/built-in.a
  CC      net/ipv6/ip6_checksum.o
  UPD     kernel/config_data
  CC      drivers/acpi/acpica/tbxfroot.o
  CC      net/ipv6/ip6_icmp.o
  CC      fs/seq_file.o
  CC      drivers/base/dd.o
  CC      kernel/stop_machine.o
  CC      lib/rcuref.o
  CC [M]  drivers/gpu/drm/i915/intel_step.o
  CC      net/ipv4/metrics.o
  CC [M]  fs/smb/client/ioctl.o
  CC [M]  fs/smb/client/sess.o
  CC [M]  drivers/gpu/drm/i915/intel_uncore.o
  CC      net/ipv6/output_core.o
  CC      arch/x86/kernel/kvmclock.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_topology.o
  CC      drivers/acpi/acpica/utaddress.o
  CC      net/core/gro_cells.o
  AR      drivers/scsi/built-in.a
  CC [M]  drivers/gpu/drm/nouveau/nvif/timer.o
  CC      drivers/acpi/processor_pdc.o
  AR      drivers/spi/built-in.a
  CC      drivers/usb/common/common.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/vmm.o
  CC      drivers/acpi/ec.o
  CC      drivers/usb/core/usb.o
  AR      drivers/usb/phy/built-in.a
  CC [M]  drivers/gpu/drm/i915/intel_wakeref.o
  CC      drivers/usb/core/hub.o
  CC      drivers/usb/core/hcd.o
  CC      fs/xattr.o
  CC      fs/nfs/sysctl.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/user.o
  CC      net/core/failover.o
  CC      drivers/ata/libata-sff.o
  CC      lib/usercopy.o
  CC      kernel/kprobes.o
  HOSTCC  drivers/gpu/drm/xe/xe_gen_wa_oob
  CC [M]  drivers/gpu/drm/i915/vlv_sideband.o
  CC      drivers/acpi/acpica/utalloc.o
  CC [M]  drivers/gpu/drm/nouveau/nvif/userc361.o
  CC      drivers/net/phy/linkmode.o
  CC      drivers/acpi/dock.o
  CC      fs/nfs/nfs2super.o
  CC      drivers/net/phy/mdio_bus.o
  CC      drivers/acpi/acpica/utascii.o
  CC      arch/x86/kernel/paravirt.o
  CC      drivers/base/syscore.o
  CC      fs/btrfs/extent_map.o
  CC      drivers/base/driver.o
  CC      fs/nfs/proc.o
  CC      lib/errseq.o
  CC      arch/x86/kernel/pvclock.o
  CC      arch/x86/kernel/pcspeaker.o
  CC      drivers/usb/common/debug.o
  CC      lib/bucket_locks.o
  CC      lib/generic-radix-tree.o
  CC      fs/libfs.o
  CC      fs/fs-writeback.o
  CC      net/ipv4/netlink.o
  AR      drivers/usb/common/built-in.a
  CC      net/ipv6/protocol.o
  CC [M]  drivers/gpu/drm/i915/vlv_suspend.o
  AR      drivers/net/ethernet/engleder/built-in.a
  CC      drivers/acpi/acpica/utbuffer.o
  CC      arch/x86/kernel/check.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_ads.o
  CC      drivers/acpi/acpica/utcksum.o
  AR      drivers/net/usb/built-in.a
  CC [M]  drivers/net/usb/pegasus.o
  CC      net/ipv6/ip6_offload.o
  CC      drivers/base/class.o
  CC      fs/btrfs/sysfs.o
  CC      fs/btrfs/accessors.o
  CC [M]  drivers/net/usb/rtl8150.o
  CC      fs/nfs/nfs2xdr.o
  CC      arch/x86/kernel/uprobes.o
  CC      lib/string_helpers.o
  CC      arch/x86/kernel/perf_regs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/client.o
  CC [M]  drivers/gpu/drm/drm_client_modeset.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_sa.o
  CC      fs/btrfs/xattr.o
  CC      drivers/acpi/pci_root.o
  AR      net/core/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_guc_ct.o
  CC [M]  drivers/net/usb/r8152.o
  CC [M]  drivers/net/ipvlan/ipvlan_core.o
  CC [M]  drivers/net/ipvlan/ipvlan_main.o
  CC      lib/hexdump.o
  CC      drivers/ata/libata-pmp.o
  CC      drivers/acpi/acpica/utcopy.o
  CC      drivers/acpi/pci_link.o
  CC      fs/pnode.o
  CC [M]  drivers/net/ipvlan/ipvlan_l3s.o
  CC [M]  drivers/gpu/drm/drm_color_mgmt.o
  CC      net/ipv4/nexthop.o
  CC      net/ipv6/tcpv6_offload.o
  CC [M]  drivers/net/vxlan/vxlan_core.o
  CC      arch/x86/kernel/tracepoint.o
  CC      net/ipv4/udp_tunnel_stub.o
  CC      drivers/net/phy/mdio_device.o
  CC      fs/splice.o
  CC      arch/x86/kernel/itmt.o
  CC      drivers/base/platform.o
  CC [M]  fs/smb/client/export.o
  CC      drivers/usb/core/urb.o
  CC      lib/kstrtox.o
  CC      drivers/usb/core/message.o
  CC      drivers/acpi/acpica/utexcep.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/engine.o
  CC [M]  drivers/gpu/drm/i915/soc/intel_dram.o
  CC      fs/btrfs/ordered-data.o
  CC      kernel/hung_task.o
  CC      lib/debug_info.o
  CC      lib/iomap.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/atombios_i2c.o
  CC      fs/nfs/nfs3super.o
  CC      drivers/acpi/pci_irq.o
  CC      fs/sync.o
  CC      net/ipv4/sysctl_net_ipv4.o
  CC      lib/pci_iomap.o
  CC      fs/btrfs/extent_io.o
  CC [M]  drivers/net/usb/asix_devices.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_hwconfig.o
  CC      drivers/net/phy/swphy.o
  CC      drivers/acpi/acpica/utdebug.o
  CC      drivers/base/cpu.o
  CC [M]  drivers/gpu/drm/i915/soc/intel_gmch.o
  CC      fs/btrfs/volumes.o
  CC      arch/x86/kernel/umip.o
  CC      drivers/ata/libata-acpi.o
  CC      drivers/acpi/acpica/utdecode.o
  CC      drivers/acpi/acpi_lpss.o
  CC      drivers/net/phy/fixed_phy.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.o
  CC      net/ipv6/exthdrs_offload.o
  CC [M]  drivers/net/vxlan/vxlan_multicast.o
  CC      arch/x86/kernel/unwind_orc.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_log.o
  CC [M]  fs/smb/client/unc.o
  CC      drivers/usb/host/pci-quirks.o
  CC      drivers/usb/storage/scsiglue.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/enum.o
  CC      drivers/usb/storage/protocol.o
  LD [M]  drivers/net/ipvlan/ipvlan.o
  CC      drivers/base/firmware.o
  CC [M]  fs/smb/client/winucase.o
  CC      drivers/net/loopback.o
  CC      drivers/usb/serial/usb-serial.o
  CC      drivers/acpi/acpica/utdelete.o
  CC      drivers/acpi/acpica/uterror.o
  CC      drivers/usb/serial/generic.o
  CC      drivers/acpi/acpi_apd.o
  CC      kernel/watchdog.o
  CC      kernel/watchdog_hld.o
  CC      drivers/base/init.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_pc.o
  CC      fs/nfs/nfs3client.o
  CC      drivers/acpi/acpi_platform.o
  CC [M]  drivers/net/phy/phylink.o
  CC      drivers/acpi/acpica/uteval.o
  AR      drivers/usb/misc/built-in.a
  CC      drivers/acpi/acpi_pnp.o
  CC      drivers/base/map.o
  CC [M]  fs/smb/client/smb2ops.o
  CC      fs/utimes.o
  CC      lib/iomap_copy.o
  CC [M]  drivers/net/vxlan/vxlan_vnifilter.o
  CC      drivers/net/netconsole.o
  CC [M]  drivers/gpu/drm/i915/soc/intel_pch.o
  CC [M]  drivers/gpu/drm/i915/i915_memcpy.o
  CC      drivers/acpi/acpica/utglobal.o
  CC      drivers/acpi/acpica/uthex.o
  CC      drivers/usb/core/driver.o
  CC      lib/devres.o
  CC [M]  fs/smb/client/smb2maperror.o
  CC      lib/check_signature.o
  CC [M]  drivers/net/vxlan/vxlan_mdb.o
  CC      arch/x86/kernel/callthunks.o
  CC      drivers/ata/libata-pata-timings.o
  CC [M]  drivers/gpu/drm/i915/i915_mm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/event.o
  CC      net/ipv6/inet6_hashtables.o
  CC [M]  fs/smb/client/smb2transport.o
  CC      drivers/base/devres.o
  CC      drivers/usb/core/config.o
  CC      drivers/net/virtio_net.o
  CC      drivers/net/net_failover.o
  CC [M]  drivers/net/usb/asix_common.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o
  CC      drivers/usb/storage/transport.o
  CC [M]  drivers/gpu/drm/i915/i915_sw_fence.o
  CC      net/ipv4/proc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/firmware.o
  CC      drivers/usb/host/ehci-hcd.o
  CC      net/ipv4/syncookies.o
  CC      kernel/seccomp.o
  CC      drivers/usb/storage/usb.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.o
  CC [M]  drivers/net/dummy.o
  CC      drivers/acpi/acpica/utids.o
  CC      drivers/usb/serial/bus.o
  CC      kernel/relay.o
  CC      drivers/usb/storage/initializers.o
  CC      lib/interval_tree.o
  CC      fs/nfs/nfs3proc.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_submit.o
  CC      fs/nfs/nfs3xdr.o
  CC      fs/d_path.o
  CC      lib/assoc_array.o
  CC [M]  drivers/gpu/drm/i915/i915_sw_fence_work.o
  CC [M]  drivers/net/usb/ax88172a.o
  CC      drivers/ata/ahci.o
  CC      arch/x86/kernel/mmconf-fam10h_64.o
  CC      drivers/acpi/acpica/utinit.o
  CC      fs/stack.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/gpuobj.o
  CC [M]  fs/smb/client/smb2misc.o
  CC      drivers/usb/serial/console.o
  CC      drivers/base/attribute_container.o
  CC [M]  drivers/gpu/drm/i915/i915_syncmap.o
  CC      net/ipv4/esp4.o
  CC      arch/x86/kernel/vsmp_64.o
  CC      fs/btrfs/async-thread.o
  CC [M]  drivers/gpu/drm/i915/i915_user_extensions.o
  AR      drivers/net/ethernet/ezchip/built-in.a
  CC      drivers/usb/host/ehci-pci.o
  CC [M]  drivers/gpu/drm/i915/i915_ioc32.o
  CC      kernel/utsname_sysctl.o
  CC [M]  drivers/gpu/drm/i915/i915_debugfs.o
  CC      drivers/usb/storage/sierra_ms.o
  CC [M]  drivers/gpu/drm/i915/i915_debugfs_params.o
  CC      drivers/acpi/acpica/utlock.o
  CC      drivers/usb/core/file.o
  AR      drivers/net/ethernet/fungible/built-in.a
  AR      drivers/net/ethernet/huawei/built-in.a
  CC [M]  drivers/gpu/drm/i915/display/intel_display_debugfs.o
  AR      drivers/net/ethernet/i825xx/built-in.a
  CC [M]  drivers/net/ethernet/intel/e1000/e1000_main.o
  AR      drivers/net/ethernet/microsoft/built-in.a
  AR      drivers/net/ethernet/litex/built-in.a
  CC [M]  drivers/net/macvlan.o
  CC [M]  drivers/net/mii.o
  CC      net/ipv6/mcast_snoop.o
  CC [M]  drivers/net/mdio.o
  CC [M]  net/ipv6/ip6_udp_tunnel.o
  CC      drivers/acpi/acpica/utmath.o
  AR      arch/x86/kernel/built-in.a
  CC      drivers/ata/libahci.o
  AR      arch/x86/built-in.a
  CC [M]  drivers/net/ethernet/intel/e1000e/82571.o
  CC [M]  drivers/net/ethernet/intel/e1000e/ich8lan.o
  CC      drivers/base/transport_class.o
  CC [M]  drivers/net/ethernet/intel/e1000e/80003es2lan.o
  CC      drivers/base/topology.o
  CC      lib/list_debug.o
  CC [M]  fs/smb/client/smb2pdu.o
  CC [M]  fs/smb/client/smb2inode.o
  CC      drivers/usb/serial/ftdi_sio.o
  CC      drivers/base/container.o
  CC      drivers/ata/ata_piix.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/intr.o
  CC      lib/debugobjects.o
  CC [M]  drivers/net/phy/aquantia_main.o
  CC      drivers/acpi/acpica/utmisc.o
  CC      lib/bitrev.o
  AR      drivers/net/ethernet/microchip/built-in.a
  CC [M]  drivers/usb/class/usbtmc.o
  CC      drivers/usb/gadget/udc/core.o
  AR      drivers/usb/gadget/function/built-in.a
  CC      drivers/usb/gadget/udc/trace.o
  CC      kernel/delayacct.o
  CC      drivers/usb/storage/option_ms.o
  CC      drivers/usb/core/buffer.o
  CC      drivers/base/property.o
  CC      drivers/usb/host/ohci-hcd.o
  CC [M]  drivers/net/tun.o
  CC [M]  drivers/net/ethernet/intel/igb/igb_main.o
  CC [M]  drivers/gpu/drm/i915/display/intel_pipe_crc.o
  CC [M]  drivers/net/phy/aquantia_hwmon.o
  AR      drivers/net/ethernet/mscc/built-in.a
  AR      drivers/net/ethernet/neterion/built-in.a
  CC [M]  drivers/net/veth.o
  AR      drivers/net/ethernet/netronome/built-in.a
  CC [M]  fs/smb/client/smb2file.o
  CC      fs/btrfs/ioctl.o
  CC      lib/crc16.o
  CC      drivers/acpi/acpica/utmutex.o
  LD [M]  drivers/net/vxlan/vxlan.o
  CC [M]  drivers/net/ethernet/intel/igb/igb_ethtool.o
  CC      kernel/taskstats.o
  AR      drivers/usb/gadget/legacy/built-in.a
  CC [M]  drivers/net/phy/ax88796b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.o
  CC [M]  drivers/gpu/drm/i915/i915_pmu.o
  AR      net/ipv6/built-in.a
  AR      fs/nfs/built-in.a
  CC      fs/fs_struct.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_main.o
  CC      drivers/usb/storage/usual-tables.o
  CC [M]  drivers/net/ethernet/intel/igbvf/vf.o
  CC      drivers/usb/core/sysfs.o
  CC [M]  drivers/net/ethernet/intel/igbvf/mbx.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_main.o
  CC [M]  drivers/net/ethernet/intel/ixgbevf/vf.o
  CC      net/ipv4/esp4_offload.o
  CC      drivers/acpi/acpica/utnonansi.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_engine.o
  CC [M]  drivers/net/ethernet/intel/igbvf/ethtool.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_pll.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/ioctl.o
  CC [M]  drivers/net/usb/ax88179_178a.o
  CC [M]  drivers/net/ethernet/intel/ixgbevf/mbx.o
  CC      lib/crc-t10dif.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_common.o
  CC [M]  drivers/net/phy/bcm7xxx.o
  CC      drivers/usb/serial/pl2303.o
  CC      fs/statfs.o
  AR      drivers/usb/storage/built-in.a
  CC      fs/fs_pin.o
  CC      drivers/acpi/acpica/utobject.o
  CC      drivers/base/cacheinfo.o
  CC [M]  drivers/net/usb/cdc_ether.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.o
  AR      drivers/net/ethernet/intel/built-in.a
  CC [M]  drivers/net/ethernet/intel/e100.o
  AR      drivers/usb/gadget/udc/built-in.a
  CC      drivers/usb/gadget/usbstring.o
  AR      drivers/ata/built-in.a
  CC      kernel/tsacct.o
  CC [M]  drivers/net/usb/cdc_eem.o
  HOSTCC  lib/gen_crc32table
  CC [M]  drivers/net/ethernet/intel/igbvf/netdev.o
  CC [M]  fs/smb/client/cifsacl.o
  CC      lib/libcrc32c.o
  CC      fs/btrfs/locking.o
  CC      lib/xxhash.o
  CC [M]  drivers/net/ethernet/intel/e1000/e1000_hw.o
  CC [M]  drivers/net/usb/smsc75xx.o
  CC      drivers/acpi/acpica/utosi.o
  CC      drivers/usb/core/endpoint.o
  CC      drivers/acpi/acpica/utownerid.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.o
  CC [M]  drivers/gpu/drm/i915/gt/gen2_engine_cs.o
  CC      drivers/acpi/acpica/utpredef.o
  CC      fs/nsfs.o
  CC [M]  fs/smb/client/fs_context.o
  CC [M]  drivers/net/ethernet/intel/ixgbevf/ethtool.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/memory.o
  CC      drivers/base/swnode.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o
  CC [M]  drivers/net/phy/bcm87xx.o
  CC      kernel/tracepoint.o
  CC      drivers/usb/core/devio.o
  CC      net/ipv4/netfilter.o
  CC      drivers/usb/gadget/config.o
  CC [M]  drivers/gpu/drm/i915/gt/gen6_engine_cs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/mm.o
  CC [M]  drivers/gpu/drm/i915/gt/gen6_ppgtt.o
  AR      drivers/usb/serial/built-in.a
  CC      drivers/usb/core/notify.o
  CC      drivers/usb/core/generic.o
  CC      lib/genalloc.o
  CC      drivers/acpi/acpica/utresdecode.o
  CC [M]  drivers/net/phy/bcm-phy-lib.o
  CC [M]  drivers/net/usb/smsc95xx.o
  CC      fs/fs_types.o
  CC [M]  drivers/net/ethernet/intel/e1000e/mac.o
  CC      drivers/base/auxiliary.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_82599.o
  CC [M]  drivers/net/usb/mcs7830.o
  CC [M]  drivers/gpu/drm/i915/gt/gen7_renderclear.o
  CC      fs/fs_context.o
  CC      drivers/usb/host/ohci-pci.o
  CC [M]  fs/smb/client/dns_resolve.o
  CC      drivers/acpi/acpica/utresrc.o
  CC      drivers/usb/core/quirks.o
  CC      net/ipv4/inet_diag.o
  CC [M]  drivers/net/phy/broadcom.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.o
  CC      net/ipv4/tcp_diag.o
  CC      kernel/latencytop.o
  CC      net/ipv4/udp_diag.o
  CC      drivers/usb/core/devices.o
  CC      drivers/usb/gadget/epautoconf.o
  CC      drivers/usb/host/uhci-hcd.o
  CC      drivers/usb/host/xhci.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/object.o
  CC      drivers/base/devtmpfs.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_fence.o
  CC      fs/btrfs/orphan.o
  CC      lib/percpu_counter.o
  CC [M]  drivers/gpu/drm/i915/gt/gen8_engine_cs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/oproxy.o
  CC      drivers/acpi/acpica/utstate.o
  CC      drivers/usb/gadget/composite.o
  CC [M]  drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.o
  CC      drivers/usb/host/xhci-mem.o
  CC      drivers/usb/core/phy.o
  CC [M]  drivers/gpu/drm/i915/gt/gen8_ppgtt.o
  CC [M]  drivers/net/phy/lxt.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
  CC      kernel/irq_work.o
  CC      lib/fault-inject.o
  CC      drivers/input/serio/serio.o
  CC      drivers/input/serio/i8042.o
  CC      drivers/acpi/acpica/utstring.o
  CC [M]  drivers/net/usb/usbnet.o
  CC [M]  drivers/net/usb/cdc_ncm.o
  CC      drivers/acpi/acpica/utstrsuppt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.o
  ASN.1   fs/smb/client/cifs_spnego_negtokeninit.asn1.[ch]
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.o
  CC [M]  drivers/gpu/drm/xe/xe_huc.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_82598.o
  CC      net/ipv4/tcp_cubic.o
  CC      drivers/usb/host/xhci-ext-caps.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_context.o
  LD [M]  drivers/net/ethernet/intel/igbvf/igbvf.o
  CC      kernel/static_call.o
  CC      drivers/base/memory.o
  CC [M]  drivers/net/ethernet/intel/e1000e/manage.o
  CC      kernel/static_call_inline.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_phy.o
  CC [M]  drivers/gpu/drm/xe/xe_huc_debugfs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/option.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/ramht.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_context_sseu.o
  CC      lib/syscall.o
  CC      lib/dynamic_debug.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.o
  CC      kernel/user-return-notifier.o
  CC      drivers/acpi/acpica/utstrtoul64.o
  CC      fs/btrfs/export.o
  CC [M]  drivers/net/usb/r8153_ecm.o
  CC      fs/fs_parser.o
  CC      kernel/padata.o
  CC [M]  fs/smb/client/smb1ops.o
  CC      drivers/usb/core/port.o
  CC      drivers/input/serio/libps2.o
  CC [M]  drivers/net/phy/realtek.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/subdev.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o
  CC      net/ipv4/xfrm4_policy.o
  CC      net/ipv4/xfrm4_state.o
  CC      drivers/usb/core/hcd-pci.o
  CC [M]  drivers/net/ethernet/intel/e1000/e1000_ethtool.o
  CC      drivers/acpi/acpica/utxface.o
  CC      kernel/jump_label.o
  CC      drivers/usb/host/xhci-ring.o
  CC      net/ipv4/xfrm4_input.o
  CC      drivers/base/module.o
  CC [M]  drivers/gpu/drm/xe/xe_irq.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_engine_cs.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
  CC      drivers/usb/core/usb-acpi.o
  CC      lib/errname.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.o
  CC      drivers/acpi/power.o
  CC      net/ipv4/xfrm4_output.o
  CC [M]  drivers/gpu/drm/xe/xe_lrc.o
  CC [M]  drivers/net/ethernet/intel/e1000e/nvm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/core/uevent.o
  CC      drivers/usb/host/xhci-hub.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_mac.o
  CC      fs/fsopen.o
  CC [M]  drivers/gpu/drm/drm_connector.o
  CC      drivers/acpi/acpica/utxfinit.o
  CC [M]  drivers/net/ethernet/intel/e1000/e1000_param.o
  AR      drivers/input/serio/built-in.a
  CC      drivers/input/keyboard/atkbd.o
  CC      drivers/base/pinctrl.o
  AR      drivers/input/mouse/built-in.a
  CC      drivers/input/input.o
  CC      drivers/base/devcoredump.o
  CC      drivers/input/input-compat.o
  CC      drivers/usb/host/xhci-dbg.o
  CC      drivers/usb/host/xhci-trace.o
  CC      drivers/usb/gadget/functions.o
  CC      fs/btrfs/tree-log.o
  CC      kernel/context_tracking.o
  CC [M]  drivers/net/phy/smsc.o
  CC      drivers/base/platform-msi.o
  CC      drivers/rtc/lib.o
  AR      drivers/i2c/algos/built-in.a
  CC [M]  drivers/i2c/algos/i2c-algo-bit.o
  CC      drivers/usb/host/xhci-debugfs.o
  CC      net/ipv4/xfrm4_protocol.o
  CC      drivers/acpi/acpica/utxferror.o
  CC      fs/btrfs/free-space-cache.o
  CC      drivers/i2c/busses/i2c-designware-common.o
  LD [M]  drivers/net/usb/asix.o
  AR      drivers/usb/core/built-in.a
  CC      drivers/base/physical_location.o
  AR      drivers/i2c/muxes/built-in.a
  CC [M]  drivers/i2c/muxes/i2c-mux-gpio.o
  CC      drivers/base/trace.o
  CC      fs/btrfs/zlib.o
  CC      drivers/rtc/class.o
  CC      lib/nlattr.o
  CC [M]  net/ipv4/ip_tunnel.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_sched.o
  CC      fs/btrfs/lzo.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/nvfw/fw.o
  CC      drivers/usb/host/xhci-pci.o
  CC      drivers/input/input-mt.o
  CC      lib/checksum.o
  CC      lib/cpu_rmap.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.o
  CC      drivers/rtc/interface.o
  CC      drivers/acpi/acpica/utxfmutex.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_82575.o
  CC      drivers/usb/gadget/configfs.o
  CC      drivers/usb/gadget/u_f.o
  CC      fs/btrfs/zstd.o
  CC [M]  drivers/gpu/drm/xe/xe_migrate.o
  CC [M]  fs/smb/client/cifssmb.o
  CC [M]  fs/smb/client/cifs_spnego_negtokeninit.asn1.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_i225.o
  CC      kernel/iomem.o
  CC [M]  net/ipv4/udp_tunnel_core.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ids.o
  CC [M]  drivers/net/ethernet/intel/e1000e/phy.o
  CC      lib/dynamic_queue_limits.o
  CC      drivers/acpi/event.o
  CC      drivers/acpi/evged.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_mac.o
  LD [M]  drivers/net/phy/aquantia.o
  AR      drivers/net/phy/built-in.a
  AR      drivers/input/keyboard/built-in.a
  CC [M]  drivers/net/ethernet/intel/igb/e1000_nvm.o
  AR      drivers/acpi/acpica/built-in.a
  CC      lib/glob.o
  AR      drivers/base/built-in.a
  CC [M]  drivers/gpu/drm/nouveau/nvkm/nvfw/hs.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_phy.o
  CC      drivers/input/input-poller.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_engine_pm.o
  CC [M]  drivers/net/ethernet/intel/e1000e/param.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_mbx.o
  LD [M]  drivers/net/ethernet/intel/e1000/e1000.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_i210.o
  CC      fs/init.o
  CC      drivers/i2c/i2c-boardinfo.o
  CC      kernel/rseq.o
  CC [M]  drivers/net/ethernet/intel/e1000e/ethtool.o
  CC      drivers/i2c/busses/i2c-designware-master.o
  CC      drivers/rtc/nvmem.o
  CC [M]  drivers/net/ethernet/intel/e1000e/netdev.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_base.o
  CC      lib/strncpy_from_user.o
  CC      drivers/input/ff-core.o
  CC [M]  fs/smb/client/asn1.o
  CC [M]  drivers/net/ethernet/intel/ixgbevf/ipsec.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_engine_user.o
  CC      lib/strnlen_user.o
  CC      drivers/acpi/sysfs.o
  CC [M]  drivers/net/ethernet/intel/igb/igb_ptp.o
  CC [M]  drivers/gpu/drm/drm_crtc.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_nvm.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_phy.o
  CC      drivers/rtc/dev.o
  AR      drivers/net/ethernet/ni/built-in.a
  CC      drivers/acpi/property.o
  CC [M]  drivers/net/ethernet/intel/igb/igb_hwmon.o
  CC      drivers/rtc/proc.o
  CC      fs/kernel_read_file.o
  CC      lib/net_utils.o
  CC      drivers/i2c/i2c-core-base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/nvfw/ls.o
  CC      drivers/i2c/i2c-core-smbus.o
  CC      drivers/input/touchscreen.o
  CC      drivers/input/ff-memless.o
  CC      lib/sg_pool.o
  AR      drivers/usb/gadget/built-in.a
  CC      fs/btrfs/compression.o
  CC      fs/mnt_idmapping.o
  CC      fs/btrfs/delayed-ref.o
  CC      drivers/acpi/acpi_cmos_rtc.o
  CC      drivers/acpi/x86/apple.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.o
  AR      drivers/net/ethernet/packetengines/built-in.a
  GZIP    kernel/config_data.gz
  CC      drivers/rtc/sysfs.o
  CC      kernel/configs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.o
  CC      fs/remap_range.o
  CC      drivers/i2c/busses/i2c-designware-platdrv.o
  CC      drivers/acpi/x86/utils.o
  CC [M]  drivers/net/ethernet/intel/e1000e/ptp.o
  CC      drivers/rtc/rtc-mc146818-lib.o
  CC      drivers/acpi/x86/s2idle.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.o
  AR      drivers/i3c/built-in.a
  CC      fs/buffer.o
  CC      fs/btrfs/relocation.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_diag.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_csa.o
  CC      drivers/i2c/busses/i2c-designware-baytrail.o
  CC      fs/mpage.o
  CC      drivers/i2c/i2c-core-acpi.o
  CC      lib/stackdepot.o
  CC      drivers/acpi/debugfs.o
  CC      drivers/acpi/acpi_lpat.o
  AR      drivers/usb/host/built-in.a
  CC [M]  drivers/gpu/drm/drm_displayid.o
  AR      drivers/usb/built-in.a
  LD [M]  drivers/net/ethernet/intel/ixgbevf/ixgbevf.o
  CC [M]  drivers/gpu/drm/drm_drv.o
  CC [M]  drivers/gpu/drm/drm_dumb_buffers.o
  CC [M]  net/ipv4/udp_tunnel_nic.o
  CC [M]  drivers/gpu/drm/drm_edid.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_ethtool.o
  CC      drivers/i2c/i2c-core-slave.o
  CC      lib/ucs2_string.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_execlists_submission.o
  AR      kernel/built-in.a
  AR      drivers/media/i2c/built-in.a
  AR      drivers/media/tuners/built-in.a
  AR      drivers/ptp/built-in.a
  AR      drivers/media/rc/keymaps/built-in.a
  AR      drivers/media/rc/built-in.a
  CC [M]  drivers/ptp/ptp_clock.o
  AR      drivers/media/common/b2c2/built-in.a
  AR      drivers/media/common/saa7146/built-in.a
  AR      drivers/media/platform/allegro-dvt/built-in.a
  AR      drivers/media/common/siano/built-in.a
  AR      drivers/media/platform/amlogic/meson-ge2d/built-in.a
  AR      drivers/media/common/v4l2-tpg/built-in.a
  AR      drivers/media/platform/amlogic/built-in.a
  AR      drivers/power/reset/built-in.a
  AR      drivers/media/common/videobuf2/built-in.a
  AR      drivers/media/platform/amphion/built-in.a
  AR      drivers/media/common/built-in.a
  CC      drivers/power/supply/power_supply_core.o
  CC      drivers/input/vivaldi-fmap.o
  AR      drivers/media/platform/aspeed/built-in.a
  CC [M]  drivers/gpu/drm/i915/gt/intel_ggtt.o
  AR      drivers/media/platform/atmel/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
  CC      drivers/hwmon/hwmon.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/nvfw/acr.o
  AR      drivers/media/platform/cadence/built-in.a
  AR      drivers/media/platform/chips-media/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_mmio.o
  AR      drivers/media/platform/intel/built-in.a
  AR      drivers/media/platform/marvell/built-in.a
  AR      drivers/media/platform/mediatek/jpeg/built-in.a
  AR      drivers/media/platform/mediatek/mdp/built-in.a
  AR      drivers/media/platform/mediatek/vcodec/built-in.a
  AR      drivers/media/platform/mediatek/vpu/built-in.a
  AR      drivers/media/platform/mediatek/mdp3/built-in.a
  AR      drivers/media/platform/mediatek/built-in.a
  AR      drivers/net/ethernet/realtek/built-in.a
  CC [M]  drivers/net/ethernet/realtek/8139cp.o
  AR      drivers/media/platform/microchip/built-in.a
  CC      drivers/rtc/rtc-cmos.o
  AR      drivers/media/platform/nvidia/tegra-vde/built-in.a
  AR      drivers/media/platform/nvidia/built-in.a
  AR      drivers/media/platform/nxp/dw100/built-in.a
  AR      drivers/media/platform/nxp/imx-jpeg/built-in.a
  AR      drivers/media/platform/nxp/imx8-isi/built-in.a
  AR      drivers/media/platform/nxp/built-in.a
  AR      drivers/media/platform/qcom/camss/built-in.a
  CC [M]  drivers/net/ethernet/realtek/8139too.o
  AR      drivers/media/platform/qcom/venus/built-in.a
  AR      drivers/media/platform/qcom/built-in.a
  CC      drivers/input/input-leds.o
  LD [M]  drivers/net/ethernet/intel/igb/igb.o
  AR      drivers/media/platform/renesas/rcar-vin/built-in.a
  AR      drivers/media/platform/renesas/rzg2l-cru/built-in.a
  AR      drivers/media/platform/rockchip/rga/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.o
  AR      drivers/media/platform/rockchip/rkisp1/built-in.a
  CC      lib/sbitmap.o
  AR      drivers/media/platform/renesas/vsp1/built-in.a
  AR      drivers/media/platform/rockchip/built-in.a
  AR      drivers/media/platform/renesas/built-in.a
  CC      lib/group_cpus.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.o
  CC [M]  drivers/gpu/drm/drm_encoder.o
  AR      drivers/media/platform/samsung/exynos-gsc/built-in.a
  CC [M]  drivers/i2c/busses/i2c-scmi.o
  CC [M]  drivers/i2c/busses/i2c-ccgx-ucsi.o
  AR      drivers/media/platform/samsung/exynos4-is/built-in.a
  AR      drivers/media/platform/samsung/s3c-camif/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.o
  AR      drivers/media/platform/samsung/s5p-g2d/built-in.a
  AR      drivers/media/platform/st/sti/bdisp/built-in.a
  AR      drivers/media/platform/st/sti/c8sectpfe/built-in.a
  AR      drivers/media/platform/samsung/s5p-jpeg/built-in.a
  CC [M]  drivers/hwmon/acpi_power_meter.o
  AR      drivers/media/platform/st/sti/delta/built-in.a
  AR      drivers/media/platform/samsung/s5p-mfc/built-in.a
  AR      drivers/media/platform/st/sti/hva/built-in.a
  AR      drivers/media/platform/samsung/built-in.a
  AR      drivers/media/platform/st/stm32/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_mocs.o
  AR      drivers/media/platform/st/built-in.a
  CC [M]  drivers/gpu/drm/drm_file.o
  CC      fs/btrfs/delayed-inode.o
  CC      drivers/i2c/i2c-dev.o
  CC      drivers/acpi/acpi_lpit.o
  AR      drivers/media/platform/sunxi/sun4i-csi/built-in.a
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/base.o
  AR      drivers/media/platform/sunxi/sun6i-csi/built-in.a
  AR      drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
  AR      drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
  AR      drivers/media/platform/sunxi/sun8i-di/built-in.a
  AR      drivers/media/platform/sunxi/sun8i-rotate/built-in.a
  CC      drivers/acpi/prmt.o
  AR      drivers/media/platform/sunxi/built-in.a
  CC [M]  drivers/gpu/drm/drm_fourcc.o
  AR      drivers/media/platform/ti/am437x/built-in.a
  AR      drivers/media/platform/ti/cal/built-in.a
  AR      drivers/media/platform/ti/vpe/built-in.a
  AR      drivers/media/platform/ti/davinci/built-in.a
  AR      drivers/media/platform/ti/omap/built-in.a
  AR      drivers/media/pci/ttpci/built-in.a
  AR      drivers/media/platform/ti/omap3isp/built-in.a
  AR      drivers/media/pci/b2c2/built-in.a
  AR      drivers/media/platform/ti/built-in.a
  AR      drivers/media/pci/pluto2/built-in.a
  AR      drivers/media/platform/verisilicon/built-in.a
  AR      drivers/media/pci/dm1105/built-in.a
  AR      drivers/media/platform/via/built-in.a
  AR      drivers/media/pci/pt1/built-in.a
  AR      drivers/media/platform/xilinx/built-in.a
  AR      drivers/media/pci/pt3/built-in.a
  AR      drivers/media/platform/built-in.a
  AR      drivers/media/pci/mantis/built-in.a
  AR      drivers/media/pci/ngene/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_module.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_ptp.o
  AR      drivers/media/pci/ddbridge/built-in.a
  AR      drivers/media/pci/saa7146/built-in.a
  AR      drivers/media/pci/smipcie/built-in.a
  AR      drivers/media/pci/netup_unidvb/built-in.a
  AR      drivers/net/ethernet/renesas/built-in.a
  AR      drivers/media/pci/intel/ipu3/built-in.a
  AR      drivers/thermal/broadcom/built-in.a
  CC      drivers/watchdog/watchdog_core.o
  AR      drivers/media/pci/intel/built-in.a
  AR      drivers/thermal/samsung/built-in.a
  AR      drivers/media/pci/built-in.a
  CC      drivers/thermal/intel/intel_tcc.o
  CC [M]  drivers/gpu/drm/drm_framebuffer.o
  CC [M]  drivers/gpu/drm/drm_gem.o
  AR      drivers/media/usb/b2c2/built-in.a
  AR      drivers/media/usb/dvb-usb/built-in.a
  CC [M]  drivers/ptp/ptp_chardev.o
  AR      drivers/media/usb/dvb-usb-v2/built-in.a
  CC      fs/btrfs/scrub.o
  AR      drivers/media/usb/s2255/built-in.a
  CC      drivers/input/mousedev.o
  CC [M]  drivers/i2c/i2c-smbus.o
  AR      drivers/media/usb/siano/built-in.a
  AR      drivers/media/usb/ttusb-budget/built-in.a
  CC      drivers/input/evdev.o
  AR      drivers/media/usb/ttusb-dec/built-in.a
  CC      drivers/power/supply/power_supply_sysfs.o
  AR      drivers/media/usb/built-in.a
  AR      drivers/media/mmc/siano/built-in.a
  AR      drivers/media/mmc/built-in.a
  AR      drivers/media/firewire/built-in.a
  AR      drivers/media/spi/built-in.a
  CC      drivers/power/supply/power_supply_leds.o
  CC      drivers/thermal/intel/therm_throt.o
  CC      drivers/power/supply/power_supply_hwmon.o
  AR      drivers/media/test-drivers/built-in.a
  CC [M]  drivers/thermal/intel/x86_pkg_temp_thermal.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
  AR      drivers/media/built-in.a
  CC      drivers/acpi/acpi_pcc.o
  CC [M]  drivers/gpu/drm/xe/xe_pat.o
  CC [M]  drivers/gpu/drm/drm_ioctl.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.o
  CC [M]  drivers/i2c/i2c-mux.o
  AR      drivers/rtc/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.o
  CC [M]  drivers/i2c/busses/i2c-i801.o
  CC [M]  drivers/i2c/busses/i2c-isch.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.o
  CC [M]  drivers/i2c/busses/i2c-ismt.o
  CC [M]  drivers/hwmon/coretemp.o
  CC [M]  lib/asn1_decoder.o
  AR      drivers/net/ethernet/sfc/built-in.a
  GEN     lib/oid_registry_data.c
  CC [M]  drivers/gpu/drm/xe/xe_pci.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.o
  CC [M]  drivers/gpu/drm/xe/xe_pcode.o
  LD [M]  net/ipv4/udp_tunnel.o
  AR      net/ipv4/built-in.a
  AR      net/built-in.a
  CC      drivers/acpi/ac.o
  CC      drivers/acpi/button.o
  CC      drivers/opp/core.o
  CC      drivers/cpufreq/cpufreq.o
  CC [M]  drivers/md/persistent-data/dm-array.o
  CC      drivers/opp/cpu.o
  CC      drivers/cpufreq/freq_table.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt.o
  AR      drivers/power/supply/built-in.a
  CC      drivers/cpufreq/cpufreq_performance.o
  AR      drivers/power/built-in.a
  CC      drivers/cpufreq/cpufreq_ondemand.o
  CC [M]  drivers/md/persistent-data/dm-bitset.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_x540.o
  CC [M]  drivers/ptp/ptp_sysfs.o
  CC [M]  drivers/gpu/drm/drm_lease.o
  CC      drivers/watchdog/watchdog_dev.o
  CC [M]  drivers/gpu/drm/drm_managed.o
  LD [M]  fs/smb/client/cifs.o
  CC [M]  drivers/gpu/drm/xe/xe_pm.o
  CC [M]  lib/oid_registry.o
  CC [M]  drivers/net/ethernet/realtek/r8169_main.o
  CC      drivers/md/md.o
  CC [M]  drivers/net/ethernet/realtek/r8169_firmware.o
  CC [M]  drivers/gpu/drm/drm_mm.o
  CC [M]  drivers/net/ethernet/realtek/r8169_phy_config.o
  CC      drivers/cpufreq/cpufreq_governor.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_dump.o
  AR      drivers/thermal/intel/built-in.a
  AR      drivers/thermal/st/built-in.a
  AR      drivers/thermal/qcom/built-in.a
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_x550.o
  AR      drivers/input/built-in.a
  CC      drivers/cpufreq/cpufreq_governor_attr_set.o
  AR      drivers/thermal/tegra/built-in.a
  CC      drivers/opp/debugfs.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_lib.o
  AR      drivers/thermal/mediatek/built-in.a
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
  CC      drivers/thermal/thermal_core.o
  CC [M]  drivers/gpu/drm/xe/xe_preempt_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_pt.o
  AR      drivers/hwmon/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_pt_walk.o
  CC      drivers/md/md-bitmap.o
  CC      fs/proc_namespace.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/fw.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/msgq.o
  CC      drivers/acpi/fan_core.o
  CC      drivers/acpi/fan_attr.o
  CC      fs/direct-io.o
  CC      drivers/md/md-autodetect.o
  AR      lib/lib.a
  CC      fs/btrfs/backref.o
  GEN     lib/crc32table.h
  CC      lib/crc32.o
  CC [M]  drivers/md/persistent-data/dm-block-manager.o
  CC [M]  drivers/md/persistent-data/dm-space-map-common.o
  CC      drivers/cpufreq/acpi-cpufreq.o
  CC      drivers/cpufreq/intel_pstate.o
  AR      drivers/net/ethernet/smsc/built-in.a
  CC [M]  drivers/i2c/busses/i2c-piix4.o
  CC [M]  drivers/net/ethernet/smsc/smsc9420.o
  AR      drivers/net/ethernet/socionext/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_umc.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.o
  CC [M]  drivers/ptp/ptp_vclock.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_tsn.o
  CC [M]  drivers/net/ethernet/intel/igc/igc_xdp.o
  CC [M]  drivers/md/persistent-data/dm-space-map-disk.o
  CC [M]  drivers/gpu/drm/drm_mode_config.o
  CC [M]  drivers/gpu/drm/drm_mode_object.o
  CC      drivers/watchdog/softdog.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.o
  CC      fs/btrfs/ulist.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.o
  CC      drivers/thermal/thermal_sysfs.o
  AR      lib/built-in.a
  CC      drivers/acpi/processor_driver.o
  CC [M]  drivers/md/persistent-data/dm-space-map-metadata.o
  CC [M]  drivers/gpu/drm/drm_modes.o
  CC [M]  drivers/gpu/drm/drm_modeset_lock.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/v1.o
  CC      drivers/md/dm-uevent.o
  CC      drivers/cpuidle/governors/menu.o
  CC      drivers/mmc/core/core.o
  LD [M]  drivers/net/ethernet/intel/e1000e/e1000e.o
  CC      drivers/cpuidle/governors/haltpoll.o
  CC      drivers/md/dm.o
  AR      drivers/opp/built-in.a
  CC      fs/btrfs/qgroup.o
  CC      drivers/cpuidle/cpuidle.o
  CC      drivers/md/dm-table.o
  AR      drivers/watchdog/built-in.a
  CC      drivers/md/dm-target.o
  CC      drivers/mmc/host/sdhci.o
  CC      fs/eventpoll.o
  CC [M]  drivers/ptp/ptp_kvm_x86.o
  CC      drivers/thermal/thermal_trip.o
  CC [M]  drivers/ptp/ptp_kvm_common.o
  CC [M]  drivers/md/persistent-data/dm-transaction-manager.o
  LD [M]  drivers/ptp/ptp.o
  CC [M]  drivers/gpu/drm/drm_plane.o
  CC      drivers/acpi/processor_thermal.o
  CC [M]  drivers/md/persistent-data/dm-btree.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
  CC      drivers/acpi/processor_idle.o
  CC      fs/btrfs/send.o
  AR      drivers/net/ethernet/vertexcom/built-in.a
  AR      drivers/ufs/built-in.a
  CC      fs/btrfs/dev-replace.o
  AR      drivers/leds/trigger/built-in.a
  CC [M]  drivers/leds/trigger/ledtrig-audio.o
  CC      fs/btrfs/uuid-tree.o
  CC      fs/btrfs/raid56.o
  AR      drivers/firmware/arm_ffa/built-in.a
  AR      drivers/crypto/stm32/built-in.a
  CC      fs/btrfs/props.o
  CC      fs/btrfs/free-space-tree.o
  AR      drivers/firmware/arm_scmi/built-in.a
  AR      drivers/crypto/xilinx/built-in.a
  AR      drivers/firmware/broadcom/built-in.a
  LD [M]  drivers/net/ethernet/intel/igc/igc.o
  AR      drivers/firmware/cirrus/built-in.a
  AR      drivers/crypto/hisilicon/trng/built-in.a
  AR      drivers/crypto/hisilicon/built-in.a
  AR      drivers/firmware/meson/built-in.a
  CC [M]  drivers/i2c/busses/i2c-designware-pcidrv.o
  CC      drivers/clocksource/acpi_pm.o
  AR      drivers/firmware/imx/built-in.a
  AR      drivers/crypto/intel/keembay/built-in.a
  CC      fs/btrfs/tree-checker.o
  CC      drivers/clocksource/i8253.o
  AR      drivers/crypto/intel/ixp4xx/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_rap.o
  AR      drivers/crypto/intel/built-in.a
  AR      drivers/crypto/built-in.a
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/gm200.o
  CC      drivers/firmware/efi/libstub/efi-stub-helper.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/gp102.o
  CC      drivers/hid/usbhid/hid-core.o
  AR      drivers/cpuidle/governors/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_query.o
  CC      drivers/hid/usbhid/hiddev.o
  CC      drivers/thermal/thermal_helpers.o
  CC      fs/anon_inodes.o
  CC      drivers/thermal/thermal_hwmon.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.o
  CC      drivers/md/dm-linear.o
  CC      drivers/mmc/host/sdhci-pci-core.o
  AR      drivers/leds/blink/built-in.a
  AR      drivers/leds/simple/built-in.a
  CC      drivers/leds/led-core.o
  CC      drivers/hid/hid-core.o
  LD [M]  drivers/ptp/ptp_kvm.o
  CC      drivers/firmware/efi/efi-bgrt.o
  CC      drivers/acpi/processor_throttling.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/ga100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.o
  CC      drivers/cpuidle/driver.o
  CC      drivers/md/dm-stripe.o
  AR      drivers/clocksource/built-in.a
  CC      drivers/hid/hid-input.o
  CC      fs/signalfd.o
  CC      drivers/hid/hid-quirks.o
  CC      drivers/thermal/gov_fair_share.o
  CC      fs/timerfd.o
  CC      drivers/firmware/efi/libstub/gop.o
  LD [M]  drivers/i2c/busses/i2c-designware-pci.o
  CC [M]  drivers/gpu/drm/xe/xe_range_fence.o
  AR      drivers/cpufreq/built-in.a
  CC      drivers/firmware/efi/libstub/secureboot.o
  AR      drivers/i2c/busses/built-in.a
  CC [M]  drivers/gpu/drm/drm_prime.o
  AR      drivers/i2c/built-in.a
  CC [M]  drivers/gpu/drm/nouveau/nvkm/falcon/ga102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.o
  CC      drivers/md/dm-ioctl.o
  CC      drivers/leds/led-class.o
  CC [M]  drivers/md/persistent-data/dm-btree-remove.o
  CC [M]  drivers/md/persistent-data/dm-btree-spine.o
  CC      drivers/firmware/efi/libstub/tpm.o
  CC      fs/btrfs/space-info.o
  CC      fs/eventfd.o
  LD [M]  drivers/net/ethernet/realtek/r8169.o
  CC      drivers/cpuidle/governor.o
  CC      drivers/hid/hid-debug.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
  CC      drivers/thermal/gov_step_wise.o
  CC      drivers/firmware/efi/libstub/file.o
  CC      drivers/firmware/efi/efi.o
  CC      drivers/mmc/core/bus.o
  CC      drivers/thermal/gov_user_space.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.o
  CC      fs/userfaultfd.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.o
  CC      drivers/firmware/efi/libstub/mem.o
  CC      drivers/acpi/processor_perflib.o
  CC [M]  drivers/gpu/drm/xe/xe_reg_sr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_mca.o
  CC      drivers/md/dm-io.o
  CC      drivers/md/dm-kcopyd.o
  CC      fs/aio.o
  CC      drivers/cpuidle/sysfs.o
  CC      fs/btrfs/block-rsv.o
  CC      drivers/hid/hidraw.o
  CC      drivers/hid/hid-generic.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_irq.o
  CC      drivers/md/dm-sysfs.o
  CC      drivers/leds/led-triggers.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.o
  AR      drivers/hid/usbhid/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_reg_whitelist.o
  CC      drivers/acpi/container.o
  AR      drivers/thermal/built-in.a
  CC      fs/locks.o
  AR      drivers/staging/media/built-in.a
  AR      drivers/staging/built-in.a
  CC      drivers/firmware/efi/libstub/random.o
  AR      drivers/platform/surface/built-in.a
  AR      drivers/platform/x86/amd/built-in.a
  CC      drivers/mailbox/mailbox.o
  CC      drivers/platform/x86/intel/pmc/core.o
  CC      drivers/mailbox/pcc.o
  CC      drivers/platform/x86/intel/pmc/spt.o
  CC [M]  drivers/platform/x86/intel/pmt/class.o
  CC      drivers/platform/x86/intel/turbo_max_3.o
  CC      drivers/platform/x86/p2sb.o
  LD [M]  drivers/md/persistent-data/dm-persistent-data.o
  CC      fs/binfmt_script.o
  CC      drivers/acpi/thermal.o
  CC      drivers/mmc/core/host.o
  CC      fs/btrfs/delalloc-space.o
  CC      drivers/platform/x86/intel/pmc/cnp.o
  CC      drivers/hid/hid-a4tech.o
  CC      drivers/acpi/acpi_memhotplug.o
  CC      drivers/md/dm-stats.o
  CC      drivers/mmc/core/mmc.o
  CC      drivers/cpuidle/poll_state.o
  CC      drivers/platform/x86/intel/pmc/icl.o
  CC      drivers/acpi/ioapic.o
  CC      drivers/firmware/efi/vars.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.o
  CC      drivers/mmc/core/mmc_ops.o
  CC      drivers/md/dm-rq.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_mcr.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.o
  CC [M]  drivers/gpu/drm/xe/xe_rtp.o
  CC      drivers/mmc/host/sdhci-pci-o2micro.o
  CC      drivers/platform/x86/intel/pmc/tgl.o
  CC [M]  drivers/platform/x86/intel/pmt/telemetry.o
  AR      drivers/leds/built-in.a
  CC [M]  drivers/gpu/drm/drm_print.o
  GEN     xe_wa_oob.c xe_wa_oob.h
  CC      drivers/firmware/efi/libstub/randomalloc.o
  CC      drivers/cpuidle/cpuidle-haltpoll.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.o
  CC [M]  drivers/platform/x86/intel/vsec.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.o
  AR      drivers/mailbox/built-in.a
  CC [M]  drivers/gpu/drm/drm_property.o
  CC [M]  drivers/platform/x86/intel/rst.o
  CC      drivers/devfreq/devfreq.o
  CC [M]  drivers/gpu/drm/drm_syncobj.o
  CC      drivers/powercap/powercap_sys.o
  GEN     xe_wa_oob.c xe_wa_oob.h
  AR      drivers/perf/built-in.a
  CC      drivers/powercap/intel_rapl_common.o
  CC [M]  drivers/devfreq/governor_simpleondemand.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.o
  CC [M]  drivers/devfreq/governor_performance.o
  CC      drivers/platform/x86/pmc_atom.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.o
  CC      drivers/platform/x86/intel/pmc/adl.o
  CC      drivers/powercap/intel_rapl_msr.o
  CC      drivers/mmc/host/sdhci-pci-arasan.o
  AR      drivers/cpuidle/built-in.a
  CC      drivers/platform/x86/intel/pmc/mtl.o
  AR      drivers/firmware/psci/built-in.a
  CC      drivers/hid/hid-apple.o
  CC      drivers/mmc/core/sd.o
  CC      drivers/acpi/battery.o
  CC      drivers/ras/ras.o
  CC      drivers/firmware/efi/reboot.o
  CC      drivers/mmc/host/sdhci-pci-dwc-mshc.o
  CC      fs/binfmt_elf.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.o
  CC      drivers/mmc/core/sd_ops.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.o
  CC [M]  drivers/platform/x86/intel/pmt/crashlog.o
  CC      drivers/firmware/efi/memattr.o
  CC      drivers/platform/x86/intel/pmc/pltdrv.o
  CC      drivers/firmware/efi/tpm.o
  CC      drivers/firmware/efi/libstub/pci.o
  CC      drivers/firmware/efi/memmap.o
  CC      drivers/mmc/host/sdhci-pci-gli.o
  CC [M]  drivers/gpu/drm/xe/xe_sa.o
  LD [M]  drivers/platform/x86/intel/intel-rst.o
  CC      fs/mbcache.o
  CC      fs/compat_binfmt_elf.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.o
  CC      drivers/firmware/efi/libstub/skip_spaces.o
  CC      drivers/mmc/host/sdhci-acpi.o
  CC      drivers/firmware/efi/esrt.o
  CC      drivers/firmware/efi/efi-pstore.o
  CC      drivers/firmware/efi/cper.o
  CC      drivers/mmc/host/cqhci-core.o
  CC [M]  drivers/mmc/host/sdhci-pltfm.o
  AR      drivers/hwtracing/intel_th/built-in.a
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gv100.o
  CC      drivers/android/binderfs.o
  CC [M]  drivers/platform/x86/wmi.o
  AR      drivers/nvmem/layouts/built-in.a
  CC      drivers/nvmem/core.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_pm.o
  CC [M]  drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.o
  CC [M]  drivers/gpu/drm/drm_sysfs.o
  CC      drivers/hid/hid-belkin.o
  CC      drivers/mmc/core/sdio.o
  AR      drivers/platform/x86/intel/pmc/built-in.a
  CC [M]  drivers/platform/x86/wmi-bmof.o
  CC      drivers/firmware/efi/libstub/lib-cmdline.o
  CC      drivers/android/binder.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.o
  LD [M]  drivers/platform/x86/intel/pmt/pmt_class.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/cik.o
  LD [M]  drivers/platform/x86/intel/pmt/pmt_telemetry.o
  LD [M]  drivers/platform/x86/intel/pmt/pmt_crashlog.o
  CC [M]  drivers/platform/x86/mxm-wmi.o
  CC      drivers/firmware/efi/libstub/lib-ctype.o
  LD [M]  drivers/platform/x86/intel/intel_vsec.o
  AR      drivers/powercap/built-in.a
  CC      drivers/firmware/efi/cper_cxl.o
  CC      drivers/hid/hid-cherry.o
  AR      drivers/platform/x86/intel/built-in.a
  CC [M]  drivers/gpu/drm/xe/xe_sched_job.o
  CC      drivers/md/dm-io-rewind.o
  CC      drivers/firmware/efi/libstub/alignedmem.o
  CC [M]  drivers/platform/x86/intel_ips.o
  CC      fs/btrfs/block-group.o
  CC      fs/btrfs/discard.o
  CC      fs/btrfs/reflink.o
  CC [M]  drivers/mtd/chips/chipreg.o
  CC      drivers/ras/debugfs.o
  CC      drivers/firmware/efi/runtime-wrappers.o
  CC [M]  drivers/gpu/drm/xe/xe_step.o
  CC      drivers/acpi/hed.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
  AR      drivers/firmware/smccc/built-in.a
  AR      drivers/net/ethernet/wangxun/built-in.a
  CC      fs/posix_acl.o
  CC      fs/coredump.o
  AR      drivers/devfreq/built-in.a
  AR      drivers/net/ethernet/xilinx/built-in.a
  CC [M]  drivers/gpu/drm/amd/amdgpu/cik_ih.o
  CC      fs/drop_caches.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/dce_v8_0.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.o
  CC [M]  drivers/uio/uio.o
  CC [M]  drivers/vfio/pci/vfio_pci_core.o
  CC [M]  drivers/vfio/vfio_main.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.o
  CC [M]  drivers/vfio/group.o
  CC [M]  drivers/vfio/iova_bitmap.o
  CC      drivers/mmc/core/sdio_ops.o
  CC      drivers/firmware/efi/dev-path-parser.o
  CC [M]  drivers/vfio/container.o
  CC [M]  drivers/gpu/drm/drm_trace_points.o
  CC [M]  drivers/gpu/drm/drm_vblank.o
  CC [M]  drivers/bluetooth/btusb.o
  CC [M]  drivers/pps/pps.o
  CC [M]  drivers/dca/dca-core.o
  AR      drivers/ras/built-in.a
  CC [M]  drivers/pps/kapi.o
  CC      drivers/firmware/efi/libstub/relocate.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_requests.o
  CC      drivers/hid/hid-chicony.o
  CC      drivers/hid/hid-cypress.o
  CC      drivers/acpi/bgrt.o
  CC      fs/sysctls.o
  CC [M]  drivers/mtd/mtdcore.o
  CC      fs/fhandle.o
  AR      drivers/nvmem/built-in.a
  CC [M]  drivers/bluetooth/btintel.o
  AR      drivers/mmc/host/built-in.a
  CC [M]  drivers/bluetooth/btbcm.o
  CC      drivers/mmc/core/sdio_bus.o
  CC [M]  drivers/dca/dca-sysfs.o
  CC      drivers/firmware/efi/apple-properties.o
  CC      fs/btrfs/subpage.o
  CC [M]  drivers/gpu/drm/xe/xe_sync.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/cik_sdma.o
  CC [M]  drivers/vfio/virqfd.o
  CC      drivers/firmware/efi/earlycon.o
  AR      drivers/platform/x86/built-in.a
  AR      drivers/platform/built-in.a
  CC [M]  drivers/ssb/main.o
  CC      drivers/firmware/efi/cper-x86.o
  CC [M]  drivers/ssb/scan.o
  CC      drivers/mmc/core/sdio_cis.o
  CC      drivers/md/dm-builtin.o
  CC [M]  drivers/vfio/vfio_iommu_type1.o
  CC      drivers/acpi/cppc_acpi.o
  CC [M]  drivers/vhost/net.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga100.o
  CC [M]  drivers/pps/sysfs.o
  CC [M]  drivers/vhost/vhost.o
  LD [M]  drivers/net/ethernet/intel/ixgbe/ixgbe.o
  CC      drivers/firmware/efi/libstub/printk.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/uvd_v4_2.o
  CC [M]  drivers/vhost/iotlb.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
  CC [M]  drivers/mtd/mtdsuper.o
  CC [M]  drivers/vfio/pci/vfio_pci_intrs.o
  CC      drivers/mmc/core/sdio_io.o
  CC [M]  drivers/gpu/drm/drm_vblank_work.o
  CC [M]  drivers/bluetooth/btrtl.o
  CC [M]  drivers/gpu/drm/drm_vma_manager.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.o
  AR      drivers/net/ethernet/synopsys/built-in.a
  AR      drivers/net/ethernet/pensando/built-in.a
  AR      drivers/net/ethernet/built-in.a
  AR      drivers/net/built-in.a
  LD [M]  drivers/dca/dca.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gtt.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_llc.o
  CC      drivers/hid/hid-ezkey.o
  AR      drivers/firmware/tegra/built-in.a
  CC      drivers/hid/hid-kensington.o
  CC      drivers/hid/hid-lg.o
  AR      drivers/firmware/xilinx/built-in.a
  CC      drivers/firmware/dmi_scan.o
  LD [M]  drivers/pps/pps_core.o
  CC [M]  drivers/mtd/mtdconcat.o
  LD [M]  drivers/vfio/vfio.o
  CC [M]  drivers/gpu/drm/drm_gpuva_mgr.o
  CC      drivers/mmc/core/sdio_irq.o
  CC      drivers/mmc/core/slot-gpio.o
  CC [M]  drivers/md/dm-bufio.o
  CC      drivers/firmware/dmi-sysfs.o
  CC [M]  drivers/vfio/pci/vfio_pci_rdwr.o
  CC [M]  drivers/ssb/sprom.o
  CC [M]  drivers/gpu/drm/drm_writeback.o
  CC [M]  drivers/gpu/drm/xe/xe_tile.o
  CC      drivers/firmware/efi/libstub/vsprintf.o
  CC      drivers/firmware/efi/libstub/x86-stub.o
  AR      drivers/firmware/efi/built-in.a
  CC      drivers/firmware/dmi-id.o
  CC [M]  drivers/ssb/pci.o
  CC [M]  drivers/vfio/pci/vfio_pci_config.o
  CC [M]  drivers/gpu/drm/lib/drm_random.o
  STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
  CC      drivers/mmc/core/regulator.o
  STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.o
  CC [M]  drivers/gpu/drm/drm_ioc32.o
  STUBCPY drivers/firmware/efi/libstub/file.stub.o
  CC [M]  drivers/mtd/mtdpart.o
  CC [M]  drivers/gpu/drm/xe/xe_tile_sysfs.o
  CC [M]  drivers/ssb/pcihost_wrapper.o
  CC [M]  drivers/md/dm-bio-prison-v1.o
  CC [M]  drivers/vfio/pci/vfio_pci.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vce_v2_0.o
  CC      drivers/android/binder_alloc.o
  CC      drivers/firmware/memmap.o
  CC      drivers/hid/hid-lg-g15.o
  STUBCPY drivers/firmware/efi/libstub/gop.stub.o
  CC [M]  drivers/mtd/mtdchar.o
  CC [M]  drivers/gpu/drm/drm_panel.o
  CC      drivers/mmc/core/debugfs.o
  CC      drivers/acpi/spcr.o
  CC      drivers/mmc/core/block.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_lrc.o
  CC [M]  drivers/gpu/drm/xe/xe_trace.o
  CC [M]  drivers/ssb/driver_chipcommon.o
  CC      drivers/mmc/core/queue.o
  CC [M]  drivers/md/dm-bio-prison-v2.o
  STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
  CC      fs/btrfs/tree-mod-log.o
  CC [M]  drivers/ssb/driver_chipcommon_pmu.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
  STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
  STUBCPY drivers/firmware/efi/libstub/mem.stub.o
  STUBCPY drivers/firmware/efi/libstub/pci.stub.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/si.o
  CC [M]  drivers/ssb/driver_pcicore.o
  CC      drivers/hid/hid-microsoft.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.o
  CC      fs/btrfs/extent-io-tree.o
  STUBCPY drivers/firmware/efi/libstub/printk.stub.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_migrate.o
  CC      drivers/hid/hid-monterey.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_mocs.o
  CC [M]  drivers/md/dm-crypt.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.o
  STUBCPY drivers/firmware/efi/libstub/random.stub.o
  STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ppgtt.o
  STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
  CC [M]  drivers/gpu/drm/xe/xe_tuning.o
  CC [M]  drivers/md/dm-thin.o
  STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
  STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
  STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
  STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
  CC      drivers/acpi/acpi_pad.o
  STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
  AR      drivers/firmware/efi/libstub/lib.a
  CC [M]  drivers/gpu/drm/i915/gt/intel_rc6.o
  CC [M]  drivers/gpu/drm/xe/xe_uc.o
  CC [M]  drivers/gpu/drm/xe/xe_uc_debugfs.o
  LD [M]  drivers/vhost/vhost_iotlb.o
  LD [M]  drivers/vhost/vhost_net.o
  AR      drivers/firmware/built-in.a
  CC      fs/btrfs/fs.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_region_lmem.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_renderstate.o
  CC [M]  drivers/md/dm-thin-metadata.o
  AR      drivers/md/built-in.a
  CC [M]  drivers/acpi/acpi_video.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_reset.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ring.o
  CC      fs/btrfs/messages.o
  CC      fs/btrfs/bio.o
  LD [M]  drivers/md/dm-bio-prison.o
  CC      fs/btrfs/lru_cache.o
  CC      fs/btrfs/acl.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.o
  CC [M]  drivers/acpi/video_detect.o
  LD [M]  drivers/vfio/pci/vfio-pci.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.o
  LD [M]  drivers/vfio/pci/vfio-pci-core.o
  CC [M]  drivers/gpu/drm/drm_pci.o
  CC [M]  drivers/gpu/drm/drm_debugfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.o
  CC [M]  drivers/gpu/drm/xe/xe_uc_fw.o
  CC [M]  drivers/gpu/drm/xe/xe_vm.o
  CC [M]  drivers/gpu/drm/xe/xe_vm_madvise.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/si_ih.o
  CC [M]  drivers/gpu/drm/xe/xe_wait_user_fence.o
  LD [M]  drivers/ssb/ssb.o
  LD [M]  drivers/mtd/mtd.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/si_dma.o
  CC [M]  drivers/gpu/drm/xe/xe_wa.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.o
  CC [M]  drivers/gpu/drm/xe/xe_wopcm.o
  CC [M]  drivers/gpu/drm/xe/xe_display.o
  AR      drivers/hid/built-in.a
  CC [M]  drivers/gpu/drm/xe/display/xe_fb_pin.o
  CC [M]  drivers/gpu/drm/xe/display/xe_hdcp_gsc.o
  CC [M]  drivers/gpu/drm/xe/display/xe_plane_initial.o
  CC [M]  drivers/gpu/drm/xe/display/xe_display_rps.o
  CC [M]  drivers/gpu/drm/xe/display/ext/i915_irq.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ring_submission.o
  CC [M]  drivers/gpu/drm/drm_debugfs_crc.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_rps.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_sa_media.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.o
  AR      drivers/acpi/built-in.a
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.o
  CC [M]  drivers/gpu/drm/drm_edid_load.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_sseu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/dce_v6_0.o
  CC [M]  drivers/gpu/drm/xe/display/ext/i915_utils.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.o
  CC [M]  drivers/gpu/drm/drm_panel_orientation_quirks.o
  CC [M]  drivers/gpu/drm/drm_buddy.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_timeline.o
  CC [M]  drivers/gpu/drm/xe/display/ext/intel_clock_gating.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_wopcm.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_workarounds.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.o
  AR      drivers/mmc/core/built-in.a
  AR      drivers/mmc/built-in.a
  CC [M]  drivers/gpu/drm/xe/i915-soc/intel_dram.o
  CC [M]  drivers/gpu/drm/i915/gt/shmem_utils.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.o
  CC [M]  drivers/gpu/drm/xe/i915-soc/intel_pch.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/uvd_v3_1.o
  CC [M]  drivers/gpu/drm/i915/gt/sysfs_engines.o
  CC [M]  drivers/gpu/drm/xe/i915-display/icl_dsi.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.o
  CC [M]  drivers/gpu/drm/i915/gt/gen6_renderstate.o
  AR      drivers/android/built-in.a
  CC [M]  drivers/gpu/drm/i915/gt/gen7_renderstate.o
  LD [M]  drivers/acpi/video.o
  CC [M]  drivers/gpu/drm/i915/gt/gen8_renderstate.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_atomic.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_audio.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_backlight.o
  AR      fs/btrfs/built-in.a
  AR      fs/built-in.a
  CC [M]  drivers/gpu/drm/drm_gem_shmem_helper.o
  CC [M]  drivers/gpu/drm/drm_suballoc.o
  CC [M]  drivers/gpu/drm/drm_gem_ttm_helper.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.o
  CC [M]  drivers/gpu/drm/drm_atomic_helper.o
  CC [M]  drivers/gpu/drm/i915/gt/gen9_renderstate.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_bios.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_busy.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_bw.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_clflush.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_context.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_create.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_cdclk.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_domain.o
  CC [M]  drivers/gpu/drm/drm_atomic_state_helper.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_color.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_internal.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_combo_phy.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_object.o
  CC [M]  drivers/gpu/drm/drm_bridge_connector.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_lmem.o
  LD [M]  drivers/md/dm-thin-pool.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_mman.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_pages.o
  CC [M]  drivers/gpu/drm/drm_crtc_helper.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_phys.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_pm.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_connector.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_crtc.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_region.o
  CC [M]  drivers/gpu/drm/drm_damage_helper.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.o
  CC [M]  drivers/gpu/drm/drm_encoder_slave.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/soc15.o
  CC [M]  drivers/gpu/drm/drm_flip_work.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_shmem.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/emu_soc.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
  CC [M]  drivers/gpu/drm/drm_format_helper.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_stolen.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.o
  CC [M]  drivers/gpu/drm/drm_gem_atomic_helper.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_cursor.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_throttle.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_tiling.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.o
  CC [M]  drivers/gpu/drm/drm_gem_framebuffer_helper.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_ttm.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o
  CC [M]  drivers/gpu/drm/drm_kms_helper_common.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vega10_reg_init.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_userptr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vega20_reg_init.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gem_wait.o
  CC [M]  drivers/gpu/drm/drm_modeset_helper.o
  CC [M]  drivers/gpu/drm/i915/gem/i915_gemfs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.o
  CC [M]  drivers/gpu/drm/i915/i915_active.o
  CC [M]  drivers/gpu/drm/i915/i915_cmd_parser.o
  CC [M]  drivers/gpu/drm/i915/i915_deps.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.o
  CC [M]  drivers/gpu/drm/i915/i915_gem_evict.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_ddi.o
  CC [M]  drivers/gpu/drm/i915/i915_gem_gtt.o
  CC [M]  drivers/gpu/drm/i915/i915_gem_ww.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v7_4.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display.o
  CC [M]  drivers/gpu/drm/drm_plane_helper.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v2_3.o
  CC [M]  drivers/gpu/drm/drm_probe_helper.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.o
  CC [M]  drivers/gpu/drm/i915/i915_gem.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nv.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_device.o
  CC [M]  drivers/gpu/drm/i915/i915_query.o
  CC [M]  drivers/gpu/drm/drm_rect.o
  CC [M]  drivers/gpu/drm/i915/i915_request.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/arct_reg_init.o
  CC [M]  drivers/gpu/drm/i915/i915_scheduler.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_driver.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mxgpu_nv.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.o
  CC [M]  drivers/gpu/drm/i915/i915_trace_points.o
  CC [M]  drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
  CC [M]  drivers/gpu/drm/i915/i915_vma.o
  CC [M]  drivers/gpu/drm/i915/i915_vma_resource.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v7_2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/hdp_v4_0.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
  CC [M]  drivers/gpu/drm/drm_self_refresh_helper.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/hdp_v5_0.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
  CC [M]  drivers/gpu/drm/drm_simple_kms_helper.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_irq.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.o
  CC [M]  drivers/gpu/drm/bridge/panel.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_power.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_power_map.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_power_well.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/aldebaran.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/vpstate.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
  CC [M]  drivers/gpu/drm/drm_fbdev_generic.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_display_trace.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/soc21.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sienna_cichlid.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_huc.o
  CC [M]  drivers/gpu/drm/drm_fb_helper.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_uc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o
  CC [M]  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
  LD [M]  drivers/gpu/drm/drm.o
  CC [M]  drivers/gpu/drm/i915/gt/intel_gsc.o
  CC [M]  drivers/gpu/drm/i915/i915_hwmon.o
  CC [M]  drivers/gpu/drm/i915/display/hsw_ips.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.o
  CC [M]  drivers/gpu/drm/i915/display/intel_atomic.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v4_3.o
  LD [M]  drivers/gpu/drm/drm_shmem_helper.o
  LD [M]  drivers/gpu/drm/drm_suballoc_helper.o
  LD [M]  drivers/gpu/drm/drm_ttm_helper.o
  AR      drivers/gpu/drm/built-in.a
  CC [M]  drivers/gpu/drm/i915/display/intel_atomic_plane.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.o
  CC [M]  drivers/gpu/drm/i915/display/intel_audio.o
  CC [M]  drivers/gpu/drm/i915/display/intel_bios.o
  CC [M]  drivers/gpu/drm/i915/display/intel_bw.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dmc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_cdclk.o
  CC [M]  drivers/gpu/drm/i915/display/intel_color.o
  CC [M]  drivers/gpu/drm/i915/display/intel_combo_phy.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/hdp_v6_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v7_7.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/hdp_v5_2.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.o
  CC [M]  drivers/gpu/drm/i915/display/intel_connector.o
  CC [M]  drivers/gpu/drm/i915/display/intel_crtc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp_aux.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o
  CC [M]  drivers/gpu/drm/i915/display/intel_cursor.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/nbio_v7_9.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_driver.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_irq.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_power.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_power_map.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_power_well.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_reset.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_rps.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dp_mst.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dmc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dpio_phy.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dpll.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dpll_mgr.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dpt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/df_v1_7.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/df_v3_6.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/df_v4_3.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dpll.o
  CC [M]  drivers/gpu/drm/i915/display/intel_drrs.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dsb.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dpt.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fb.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_drrs.o
  LD [M]  drivers/gpu/drm/drm_kms_helper.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dsb.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fb_pin.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fbc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fdi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fifo_underrun.o
  CC [M]  drivers/gpu/drm/i915/display/intel_frontbuffer.o
  CC [M]  drivers/gpu/drm/i915/display/intel_global_state.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hdcp.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dsi.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hotplug.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hotplug_irq.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hti.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.o
  CC [M]  drivers/gpu/drm/i915/display/intel_load_detect.o
  CC [M]  drivers/gpu/drm/i915/display/intel_lpe_audio.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.o
  CC [M]  drivers/gpu/drm/i915/display/intel_modeset_lock.o
  CC [M]  drivers/gpu/drm/i915/display/intel_modeset_verify.o
  CC [M]  drivers/gpu/drm/i915/display/intel_modeset_setup.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_fb.o
  CC [M]  drivers/gpu/drm/i915/display/intel_overlay.o
  CC [M]  drivers/gpu/drm/i915/display/intel_pch_display.o
  CC [M]  drivers/gpu/drm/i915/display/intel_pch_refclk.o
  CC [M]  drivers/gpu/drm/i915/display/intel_plane_initial.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_fbc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_pmdemand.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_fdi.o
  CC [M]  drivers/gpu/drm/i915/display/intel_psr.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.o
  CC [M]  drivers/gpu/drm/i915/display/intel_quirks.o
  CC [M]  drivers/gpu/drm/i915/display/intel_sprite.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.o
  CC [M]  drivers/gpu/drm/i915/display/intel_sprite_uapi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.o
  CC [M]  drivers/gpu/drm/i915/display/intel_tc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.o
  CC [M]  drivers/gpu/drm/i915/display/intel_vblank.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.o
  CC [M]  drivers/gpu/drm/i915/display/intel_vga.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.o
  CC [M]  drivers/gpu/drm/i915/display/intel_wm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.o
  CC [M]  drivers/gpu/drm/i915/display/i9xx_plane.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_global_state.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_gmbus.o
  CC [M]  drivers/gpu/drm/i915/display/i9xx_wm.o
  CC [M]  drivers/gpu/drm/i915/display/skl_scaler.o
  CC [M]  drivers/gpu/drm/i915/display/skl_universal_plane.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_hdcp.o
  CC [M]  drivers/gpu/drm/i915/display/skl_watermark.o
  CC [M]  drivers/gpu/drm/i915/display/intel_acpi.o
  CC [M]  drivers/gpu/drm/i915/display/intel_opregion.o
  CC [M]  drivers/gpu/drm/i915/display/intel_fbdev.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_hdmi.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_hotplug.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_ch7017.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_ch7xxx.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_hti.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_ivch.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_ns2501.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_lspcon.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_sil164.o
  CC [M]  drivers/gpu/drm/i915/display/dvo_tfp410.o
  CC [M]  drivers/gpu/drm/i915/display/g4x_dp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.o
  CC [M]  drivers/gpu/drm/i915/display/g4x_hdmi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.o
  CC [M]  drivers/gpu/drm/i915/display/icl_dsi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.o
  CC [M]  drivers/gpu/drm/i915/display/intel_backlight.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_modeset_lock.o
  CC [M]  drivers/gpu/drm/i915/display/intel_crt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gmc_v11_0.o
  CC [M]  drivers/gpu/drm/i915/display/intel_cx0_phy.o
  CC [M]  drivers/gpu/drm/i915/display/intel_ddi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.o
  CC [M]  drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_panel.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_device.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.o
  CC [M]  drivers/gpu/drm/i915/display/intel_display_trace.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dkl_phy.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp_aux.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp_hdcp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp_link_training.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_pmdemand.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_pps.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dp_mst.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dsi.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dsi_vbt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/umc_v6_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/umc_v6_1.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/umc_v6_7.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/umc_v8_7.o
  CC [M]  drivers/gpu/drm/i915/display/intel_dvo.o
  CC [M]  drivers/gpu/drm/i915/display/intel_gmbus.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/umc_v8_10.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_psr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.o
  CC [M]  drivers/gpu/drm/i915/display/intel_hdmi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ih.o
  CC [M]  drivers/gpu/drm/i915/display/intel_lspcon.o
  CC [M]  drivers/gpu/drm/i915/display/intel_lvds.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_qp_tables.o
  CC [M]  drivers/gpu/drm/i915/display/intel_panel.o
  CC [M]  drivers/gpu/drm/i915/display/intel_pps.o
  CC [M]  drivers/gpu/drm/i915/display/intel_qp_tables.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/iceland_ih.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_quirks.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_snps_phy.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_tc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_sdvo.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_vblank.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/tonga_ih.o
  CC [M]  drivers/gpu/drm/i915/display/intel_snps_phy.o
  CC [M]  drivers/gpu/drm/i915/display/intel_tv.o
  CC [M]  drivers/gpu/drm/i915/display/intel_vdsc.o
  CC [M]  drivers/gpu/drm/i915/display/intel_vrr.o
  CC [M]  drivers/gpu/drm/i915/display/vlv_dsi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/cz_ih.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vega10_ih.o
  CC [M]  drivers/gpu/drm/i915/display/vlv_dsi_pll.o
  CC [M]  drivers/gpu/drm/i915/i915_perf.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vega20_ih.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/navi10_ih.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_vdsc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_cmd.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/ih_v6_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_vga.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_irq.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_pm.o
  CC [M]  drivers/gpu/drm/i915/pxp/intel_pxp_session.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v3_1.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v10_0.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_vrr.o
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_wm.o
  CC [M]  drivers/gpu/drm/i915/i915_gpu_error.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.o
  CC [M]  drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.o
  CC [M]  drivers/gpu/drm/xe/i915-display/skl_scaler.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.o
  CC [M]  drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.o
  CC [M]  drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v11_0.o
  CC [M]  drivers/gpu/drm/i915/selftests/i915_random.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.o
  CC [M]  drivers/gpu/drm/i915/selftests/i915_selftest.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.o
  CC [M]  drivers/gpu/drm/xe/i915-display/skl_universal_plane.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_atomic.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v12_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v13_0.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_flush_test.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_live_test.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_mmap.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_reset.o
  CC [M]  drivers/gpu/drm/i915/selftests/igt_spinner.o
  CC [M]  drivers/gpu/drm/i915/selftests/librapl.o
  CC [M]  drivers/gpu/drm/i915/i915_vgpu.o
  CC [M]  drivers/gpu/drm/xe/i915-display/skl_watermark.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
  HDRTEST drivers/gpu/drm/i915/display/hsw_ips.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.o
  HDRTEST drivers/gpu/drm/i915/display/g4x_hdmi.h
  HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/dce_v10_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_overlay.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display.h
  HDRTEST drivers/gpu/drm/i915/display/skl_watermark_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dmc.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/dce_v11_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_vga.h
  HDRTEST drivers/gpu/drm/i915/display/intel_audio.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.o
  HDRTEST drivers/gpu/drm/i915/display/intel_lvds.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_acpi.o
  HDRTEST drivers/gpu/drm/i915/display/intel_modeset_setup.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.o
  HDRTEST drivers/gpu/drm/i915/display/intel_cdclk.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_limits.h
  HDRTEST drivers/gpu/drm/i915/display/intel_hotplug.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_opregion.o
  HDRTEST drivers/gpu/drm/i915/display/intel_atomic.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_driver.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dpll.h
  HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h
  CC [M]  drivers/gpu/drm/xe/i915-display/intel_fbdev.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_mst.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.o
  HDRTEST drivers/gpu/drm/i915/display/intel_fdi_regs.h
  HDRTEST drivers/gpu/drm/i915/display/g4x_dp.h
  HDRTEST drivers/gpu/drm/i915/display/intel_tc.h
  HDRTEST drivers/gpu/drm/i915/display/intel_frontbuffer.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dsi_vbt.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.o
  HDRTEST drivers/gpu/drm/i915/display/intel_psr.h
  HDRTEST drivers/gpu/drm/i915/display/intel_crt.h
  HDRTEST drivers/gpu/drm/i915/display/intel_opregion.h
  HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.o
  HDRTEST drivers/gpu/drm/i915/display/i9xx_wm.h
  HDRTEST drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_global_state.h
  CC [M]  drivers/gpu/drm/xe/xe_guc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v9_4.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.o
  CC [M]  drivers/gpu/drm/xe/xe_ring_ops.o
  HDRTEST drivers/gpu/drm/i915/display/intel_lpe_audio.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.o
  HDRTEST drivers/gpu/drm/i915/display/intel_drrs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.o
  HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_rps.h
  HDRTEST drivers/gpu/drm/i915/display/intel_fbdev.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h
  HDRTEST drivers/gpu/drm/i915/display/intel_pps_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.o
  HDRTEST drivers/gpu/drm/i915/display/intel_hdmi.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/imu_v11_0.o
  HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h
  HDRTEST drivers/gpu/drm/i915/display/intel_fdi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h
  HDRTEST drivers/gpu/drm/i915/display/intel_fb.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_irq.h
  HDRTEST drivers/gpu/drm/i915/display/intel_qp_tables.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dsb_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_vdsc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/imu_v11_0_3.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.o
  HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_core.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
  HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dvo_dev.h
  HDRTEST drivers/gpu/drm/i915/display/intel_hdcp.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v2_4.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_sdvo_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_pch_refclk.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h
  HDRTEST drivers/gpu/drm/i915/display/intel_modeset_lock.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_trace.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_power.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.o
  HDRTEST drivers/gpu/drm/i915/display/i9xx_plane.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_backlight.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_config.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dpll_mgr.h
  HDRTEST drivers/gpu/drm/i915/display/vlv_dsi.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_plane_initial.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v4_4.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_device.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.o
  HDRTEST drivers/gpu/drm/i915/display/intel_fifo_underrun.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h
  HDRTEST drivers/gpu/drm/i915/display/intel_cursor.h
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h
  HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.o
  HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h
  HDRTEST drivers/gpu/drm/i915/display/intel_cx0_phy.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v5_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h
  HDRTEST drivers/gpu/drm/i915/display/skl_scaler.h
  HDRTEST drivers/gpu/drm/i915/display/intel_hti.h
  HDRTEST drivers/gpu/drm/i915/display/icl_dsi_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_atomic_plane.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h
  HDRTEST drivers/gpu/drm/i915/display/skl_watermark.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.o
  HDRTEST drivers/gpu/drm/i915/display/intel_fbc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/sdma_v6_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_reg_defs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mes_v10_1.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/mes_v11_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.o
  HDRTEST drivers/gpu/drm/i915/display/intel_acpi.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/uvd_v5_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.o
  HDRTEST drivers/gpu/drm/xe/tests/xe_test.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_connector.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dpt.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.o
  HDRTEST drivers/gpu/drm/i915/display/intel_quirks.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_link_training.h
  HDRTEST drivers/gpu/drm/i915/display/intel_color.h
  HDRTEST drivers/gpu/drm/i915/display/intel_crtc.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_debugfs.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h
  HDRTEST drivers/gpu/drm/i915/display/intel_modeset_verify.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.o
  HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vce_v3_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vce_v4_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_power_well.h
  HDRTEST drivers/gpu/drm/i915/display/intel_psr_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.o
  HDRTEST drivers/gpu/drm/i915/display/intel_wm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.o
  HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.o
  HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_pipe_crc.h
  HDRTEST drivers/gpu/drm/i915/display/intel_audio_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.o
  HDRTEST drivers/gpu/drm/i915/display/intel_panel.h
  HDRTEST drivers/gpu/drm/i915/display/intel_sprite.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.o
  HDRTEST drivers/gpu/drm/i915/display/intel_wm_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.o
  HDRTEST drivers/gpu/drm/i915/display/intel_tv.h
  HDRTEST drivers/gpu/drm/i915/display/intel_hti_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v2_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_vrr.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.o
  HDRTEST drivers/gpu/drm/i915/display/intel_load_detect.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.o
  HDRTEST drivers/gpu/drm/xe/xe_bb.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v2_5.o
  HDRTEST drivers/gpu/drm/i915/display/skl_universal_plane.h
  HDRTEST drivers/gpu/drm/xe/xe_bb_types.h
  HDRTEST drivers/gpu/drm/xe/xe_bo.h
  HDRTEST drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.o
  HDRTEST drivers/gpu/drm/i915/display/intel_bw.h
  HDRTEST drivers/gpu/drm/i915/display/intel_display_irq.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v3_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_de.h
  HDRTEST drivers/gpu/drm/i915/display/intel_lvds_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_gmbus_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dvo.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.o
  HDRTEST drivers/gpu/drm/i915/display/intel_sdvo.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v4_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_vdsc_regs.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.o
  HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dvo_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.o
  HDRTEST drivers/gpu/drm/i915/display/intel_gmbus.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.o
  HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dsi.h
  HDRTEST drivers/gpu/drm/xe/xe_debugfs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dmc_regs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.o
  HDRTEST drivers/gpu/drm/xe/xe_devcoredump.h
  HDRTEST drivers/gpu/drm/i915/display/intel_ddi.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.o
  HDRTEST drivers/gpu/drm/xe/xe_devcoredump_types.h
  HDRTEST drivers/gpu/drm/i915/display/intel_hotplug_irq.h
  HDRTEST drivers/gpu/drm/i915/display/intel_tv_regs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.o
  HDRTEST drivers/gpu/drm/i915/display/intel_dsb.h
  HDRTEST drivers/gpu/drm/i915/display/intel_bios.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_pch_display.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_types.h
  HDRTEST drivers/gpu/drm/i915/display/intel_backlight.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.o
  HDRTEST drivers/gpu/drm/i915/display/intel_vblank.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dp.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.o
  HDRTEST drivers/gpu/drm/i915/display/intel_pmdemand.h
  HDRTEST drivers/gpu/drm/i915/display/intel_backlight_regs.h
  HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
  HDRTEST drivers/gpu/drm/xe/xe_device.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.o
  HDRTEST drivers/gpu/drm/xe/xe_device_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_device_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/athub_v1_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_reset.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/athub_v2_0.o
  HDRTEST drivers/gpu/drm/i915/display/intel_display_power_map.h
  HDRTEST drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/athub_v2_1.o
  HDRTEST drivers/gpu/drm/i915/display/icl_dsi.h
  HDRTEST drivers/gpu/drm/i915/display/intel_lspcon.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dpio_phy.h
  HDRTEST drivers/gpu/drm/i915/display/intel_fb_pin.h
  HDRTEST drivers/gpu/drm/i915/display/intel_dp_hdcp.h
  HDRTEST drivers/gpu/drm/xe/xe_display.h
  HDRTEST drivers/gpu/drm/i915/display/intel_pps.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.o
  HDRTEST drivers/gpu/drm/i915/display/intel_sprite_uapi.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_region.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/athub_v3_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v9_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v11_0.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_lmem.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.o
  HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_mman.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.o
  HDRTEST drivers/gpu/drm/xe/xe_drv.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.o
  HDRTEST drivers/gpu/drm/xe/xe_exec.h
  HDRTEST drivers/gpu/drm/xe/xe_exec_queue.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_clflush.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_tiling.h
  HDRTEST drivers/gpu/drm/xe/xe_exec_queue_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v13_0.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_stolen.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v13_0_3.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
  HDRTEST drivers/gpu/drm/xe/xe_execlist.h
  HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h
  HDRTEST drivers/gpu/drm/xe/xe_force_wake.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_create.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_move.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_domain.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/mca_v3_0.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_internal.h
  HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h
  HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_context.h
  HDRTEST drivers/gpu/drm/i915/gem/selftests/huge_gem_object.h
  HDRTEST drivers/gpu/drm/xe/xe_ggtt.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.o
  HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_gem_object.h
  HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.o
  HDRTEST drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h
  HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_userptr.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_module.o
  HDRTEST drivers/gpu/drm/xe/xe_gt.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_pm.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.o
  HDRTEST drivers/gpu/drm/i915/gem/i915_gemfs.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h
  HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_timeline_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h
  HDRTEST drivers/gpu/drm/i915/gt/selftest_engine.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_pasid.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_printk.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_context_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_execlists_submission.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm.h
  HDRTEST drivers/gpu/drm/i915/gt/selftest_rc6.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_llc_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_region_lmem.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_flat_memory.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_requests.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_print.h
  HDRTEST drivers/gpu/drm/i915/gt/gen8_ppgtt.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_mcr.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_timeline.h
  HDRTEST drivers/gpu/drm/i915/gt/gen6_engine_cs.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.o
  HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_cik.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v9.o
  HDRTEST drivers/gpu/drm/i915/gt/selftest_rps.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_sa_media.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v11.o
  HDRTEST drivers/gpu/drm/xe/xe_guc.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_rps_types.h
  HDRTEST drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h
  HDRTEST drivers/gpu/drm/i915/gt/sysfs_engines.h
  HDRTEST drivers/gpu/drm/i915/gt/gen7_renderclear.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_context.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_wopcm.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_mocs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv4e.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_vi.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_pm.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv50.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_rc6.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_ring_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_v9.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_regs.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
  HDRTEST drivers/gpu/drm/i915/gt/shmem_utils.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process_queue_manager.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgf119.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_log.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_reset_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_regs.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_reset.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_cik.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_vi.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_submit_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.o
  HDRTEST drivers/gpu/drm/xe/xe_guc_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.o
  HDRTEST drivers/gpu/drm/xe/xe_huc.h
  HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_huc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v9.o
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgf119.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v11.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
  HDRTEST drivers/gpu/drm/xe/xe_irq.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/cik_event_interrupt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.o
  HDRTEST drivers/gpu/drm/xe/xe_lrc.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
  HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_macros.h
  HDRTEST drivers/gpu/drm/xe/xe_map.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
  HDRTEST drivers/gpu/drm/xe/xe_migrate.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.o
  HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
  HDRTEST drivers/gpu/drm/xe/xe_mmio.h
  HDRTEST drivers/gpu/drm/xe/xe_mocs.h
  HDRTEST drivers/gpu/drm/xe/xe_module.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h
  HDRTEST drivers/gpu/drm/xe/xe_pat.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc.h
  HDRTEST drivers/gpu/drm/xe/xe_pci.h
  HDRTEST drivers/gpu/drm/xe/xe_pci_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pcode.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.o
  HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.o
  HDRTEST drivers/gpu/drm/xe/xe_platform_types.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_print.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debug.o
  HDRTEST drivers/gpu/drm/xe/xe_pm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
  HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debugfs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.o
  HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pt.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.o
  HDRTEST drivers/gpu/drm/xe/xe_pt_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pt_walk.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.o
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h
  HDRTEST drivers/gpu/drm/xe/xe_query.h
  HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_hwconfig.h
  HDRTEST drivers/gpu/drm/xe/xe_range_fence.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_llc.h
  HDRTEST drivers/gpu/drm/i915/gt/gen8_engine_cs.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_sseu_debugfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ga102.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_rc6_types.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_context_param.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gpu_commands.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_user.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_irq.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gsc.h
  HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h
  HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_rps.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.o
  HDRTEST drivers/gpu/drm/i915/gt/selftest_llc.h
  HDRTEST drivers/gpu/drm/i915/gt/gen6_ppgtt.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_migrate_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.o
  HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h
  HDRTEST drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
  HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.o
  HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_lrc.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_lrc_reg.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_migrate.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.o
  HDRTEST drivers/gpu/drm/i915/gt/mock_engine.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_stats.h
  HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h
  HDRTEST drivers/gpu/drm/xe/xe_rtp.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gtt.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.o
  HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.o
  HDRTEST drivers/gpu/drm/xe/xe_sa.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h
  HDRTEST drivers/gpu/drm/xe/xe_sa_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_ring.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.o
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_types.h
  HDRTEST drivers/gpu/drm/xe/xe_sched_job.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.o
  HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_renderstate.h
  HDRTEST drivers/gpu/drm/xe/xe_step.h
  HDRTEST drivers/gpu/drm/xe/xe_step_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_job.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_acp.o
  HDRTEST drivers/gpu/drm/xe/xe_sync.h
  HDRTEST drivers/gpu/drm/xe/xe_sync_types.h
  HDRTEST drivers/gpu/drm/xe/xe_tile.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_sseu.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.o
  HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.o
  HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs_types.h
  HDRTEST drivers/gpu/drm/xe/xe_trace.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_engine_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.o
  HDRTEST drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h
  HDRTEST drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_sys_mgr.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../acp/acp_hw.o
  HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
  HDRTEST drivers/gpu/drm/xe/xe_tuning.h
  HDRTEST drivers/gpu/drm/xe/xe_uc.h
  HDRTEST drivers/gpu/drm/i915/gt/gen2_engine_cs.h
  HDRTEST drivers/gpu/drm/i915/gvt/gvt.h
  HDRTEST drivers/gpu/drm/i915/gvt/trace.h
  HDRTEST drivers/gpu/drm/i915/gvt/debug.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.o
  HDRTEST drivers/gpu/drm/i915/gvt/edid.h
  HDRTEST drivers/gpu/drm/i915/gvt/page_track.h
  HDRTEST drivers/gpu/drm/i915/gvt/mmio.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.o
  HDRTEST drivers/gpu/drm/i915/gvt/sched_policy.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.o
  HDRTEST drivers/gpu/drm/xe/xe_uc_debugfs.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.o
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw.h
  HDRTEST drivers/gpu/drm/i915/gvt/fb_decoder.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.o
  HDRTEST drivers/gpu/drm/i915/gvt/cmd_parser.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/arcturus_ppt.o
  HDRTEST drivers/gpu/drm/i915/gvt/dmabuf.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw_abi.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.o
  HDRTEST drivers/gpu/drm/i915/gvt/mmio_context.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw_types.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.o
  HDRTEST drivers/gpu/drm/xe/xe_uc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_vm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.o
  HDRTEST drivers/gpu/drm/i915/gvt/display.h
  HDRTEST drivers/gpu/drm/xe/xe_vm_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_vm_madvise.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/cyan_skillfish_ppt.o
  HDRTEST drivers/gpu/drm/xe/xe_vm_types.h
  HDRTEST drivers/gpu/drm/xe/xe_wa.h
  HDRTEST drivers/gpu/drm/i915/gvt/gtt.h
  HDRTEST drivers/gpu/drm/xe/xe_wait_user_fence.h
  HDRTEST drivers/gpu/drm/xe/xe_wopcm.h
  HDRTEST drivers/gpu/drm/xe/xe_wopcm_types.h
  HDRTEST drivers/gpu/drm/i915/gvt/scheduler.h
  LD [M]  drivers/gpu/drm/xe/xe.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/smu_v11_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/renoir_ppt.o
  HDRTEST drivers/gpu/drm/i915/gvt/reg.h
  HDRTEST drivers/gpu/drm/i915/gvt/execlist.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.o
  HDRTEST drivers/gpu/drm/i915/gvt/interrupt.h
  HDRTEST drivers/gpu/drm/i915/i915_active.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/smu_v12_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.o
  HDRTEST drivers/gpu/drm/i915/i915_active_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.o
  HDRTEST drivers/gpu/drm/i915/i915_cmd_parser.h
  HDRTEST drivers/gpu/drm/i915/i915_config.h
  HDRTEST drivers/gpu/drm/i915/i915_debugfs.h
  HDRTEST drivers/gpu/drm/i915/i915_debugfs_params.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_0_ppt.o
  HDRTEST drivers/gpu/drm/i915/i915_deps.h
  HDRTEST drivers/gpu/drm/i915/i915_driver.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_4_ppt.o
  HDRTEST drivers/gpu/drm/i915/i915_drm_client.h
  HDRTEST drivers/gpu/drm/i915/i915_drv.h
  HDRTEST drivers/gpu/drm/i915/i915_file_private.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_5_ppt.o
  HDRTEST drivers/gpu/drm/i915/i915_fixed.h
  HDRTEST drivers/gpu/drm/i915/i915_gem.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_7_ppt.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.o
  HDRTEST drivers/gpu/drm/i915/i915_gem_evict.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.o
  HDRTEST drivers/gpu/drm/i915/i915_gem_gtt.h
  HDRTEST drivers/gpu/drm/i915/i915_gem_ww.h
  HDRTEST drivers/gpu/drm/i915/i915_getparam.h
  HDRTEST drivers/gpu/drm/i915/i915_gpu_error.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smumgr.o
  HDRTEST drivers/gpu/drm/i915/i915_hwmon.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu8_smumgr.o
  HDRTEST drivers/gpu/drm/i915/i915_ioc32.h
  HDRTEST drivers/gpu/drm/i915/i915_ioctl.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.o
  HDRTEST drivers/gpu/drm/i915/i915_iosf_mbi.h
  HDRTEST drivers/gpu/drm/i915/i915_irq.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/tonga_smumgr.o
  HDRTEST drivers/gpu/drm/i915/i915_memcpy.h
  HDRTEST drivers/gpu/drm/i915/i915_mitigations.h
  HDRTEST drivers/gpu/drm/i915/i915_mm.h
  HDRTEST drivers/gpu/drm/i915/i915_params.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.o
  HDRTEST drivers/gpu/drm/i915/i915_pci.h
  HDRTEST drivers/gpu/drm/i915/i915_perf.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.o
  HDRTEST drivers/gpu/drm/i915/i915_perf_oa_regs.h
  HDRTEST drivers/gpu/drm/i915/i915_perf_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/fiji_smumgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/polaris10_smumgr.o
  HDRTEST drivers/gpu/drm/i915/i915_pmu.h
  HDRTEST drivers/gpu/drm/i915/i915_priolist_types.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.o
  HDRTEST drivers/gpu/drm/i915/i915_pvinfo.h
  HDRTEST drivers/gpu/drm/i915/i915_query.h
  HDRTEST drivers/gpu/drm/i915/i915_reg.h
  HDRTEST drivers/gpu/drm/i915/i915_reg_defs.h
  HDRTEST drivers/gpu/drm/i915/i915_request.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv04.o
  HDRTEST drivers/gpu/drm/i915/i915_scatterlist.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/iceland_smumgr.o
  HDRTEST drivers/gpu/drm/i915/i915_scheduler.h
  HDRTEST drivers/gpu/drm/i915/i915_scheduler_types.h
  HDRTEST drivers/gpu/drm/i915/i915_selftest.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu7_smumgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega10_smumgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.o
  HDRTEST drivers/gpu/drm/i915/i915_suspend.h
  HDRTEST drivers/gpu/drm/i915/i915_sw_fence.h
  HDRTEST drivers/gpu/drm/i915/i915_sw_fence_work.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu10_smumgr.o
  HDRTEST drivers/gpu/drm/i915/i915_switcheroo.h
  HDRTEST drivers/gpu/drm/i915/i915_syncmap.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.o
  HDRTEST drivers/gpu/drm/i915/i915_sysfs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/ci_smumgr.o
  HDRTEST drivers/gpu/drm/i915/i915_tasklet.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega12_smumgr.o
  HDRTEST drivers/gpu/drm/i915/i915_trace.h
  HDRTEST drivers/gpu/drm/i915/i915_ttm_buddy_manager.h
  HDRTEST drivers/gpu/drm/i915/i915_user_extensions.h
  HDRTEST drivers/gpu/drm/i915/i915_utils.h
  HDRTEST drivers/gpu/drm/i915/i915_vgpu.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vegam_smumgr.o
  HDRTEST drivers/gpu/drm/i915/i915_vma.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.o
  HDRTEST drivers/gpu/drm/i915/i915_vma_resource.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu9_smumgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega20_smumgr.o
  HDRTEST drivers/gpu/drm/i915/i915_vma_types.h
  HDRTEST drivers/gpu/drm/i915/intel_clock_gating.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hwmgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.o
  HDRTEST drivers/gpu/drm/i915/intel_device_info.h
  HDRTEST drivers/gpu/drm/i915/intel_gvt.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/processpptables.o
  HDRTEST drivers/gpu/drm/i915/intel_mchbar_regs.h
  HDRTEST drivers/gpu/drm/i915/intel_memory_region.h
  HDRTEST drivers/gpu/drm/i915/intel_pci_config.h
  HDRTEST drivers/gpu/drm/i915/intel_pcode.h
  HDRTEST drivers/gpu/drm/i915/intel_region_ttm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmmcp77.o
  HDRTEST drivers/gpu/drm/i915/intel_runtime_pm.h
  HDRTEST drivers/gpu/drm/i915/intel_sbi.h
  HDRTEST drivers/gpu/drm/i915/intel_step.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu8_hwmgr.o
  HDRTEST drivers/gpu/drm/i915/intel_uncore.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.o
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
  HDRTEST drivers/gpu/drm/i915/intel_wakeref.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pppcielanes.o
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_session.h
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/process_pptables_v1_0.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.o
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomfwctrl.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.o
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp.h
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_types.h
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.o
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
  HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_regs.h
  HDRTEST drivers/gpu/drm/i915/selftests/igt_live_test.h
  HDRTEST drivers/gpu/drm/i915/selftests/igt_atomic.h
  HDRTEST drivers/gpu/drm/i915/selftests/mock_gem_device.h
  HDRTEST drivers/gpu/drm/i915/selftests/mock_drm.h
  HDRTEST drivers/gpu/drm/i915/selftests/igt_reset.h
  HDRTEST drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.o
  HDRTEST drivers/gpu/drm/i915/selftests/lib_sw_fence.h
  HDRTEST drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
  HDRTEST drivers/gpu/drm/i915/selftests/mock_uncore.h
  HDRTEST drivers/gpu/drm/i915/selftests/mock_gtt.h
  HDRTEST drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_powertune.o
  HDRTEST drivers/gpu/drm/i915/selftests/mock_request.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_thermal.o
  HDRTEST drivers/gpu/drm/i915/selftests/i915_random.h
  HDRTEST drivers/gpu/drm/i915/selftests/igt_spinner.h
  HDRTEST drivers/gpu/drm/i915/selftests/librapl.h
  HDRTEST drivers/gpu/drm/i915/selftests/mock_region.h
  HDRTEST drivers/gpu/drm/i915/selftests/i915_live_selftests.h
  HDRTEST drivers/gpu/drm/i915/selftests/igt_mmap.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_clockpowergating.o
  HDRTEST drivers/gpu/drm/i915/selftests/igt_flush_test.h
  HDRTEST drivers/gpu/drm/i915/soc/intel_pch.h
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_processpptables.o
  HDRTEST drivers/gpu/drm/i915/soc/intel_dram.h
  HDRTEST drivers/gpu/drm/i915/soc/intel_gmch.h
  HDRTEST drivers/gpu/drm/i915/vlv_sideband.h
  HDRTEST drivers/gpu/drm/i915/vlv_sideband_reg.h
  HDRTEST drivers/gpu/drm/i915/vlv_suspend.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.o
  LD [M]  drivers/gpu/drm/i915/i915.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_powertune.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_thermal.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu10_hwmgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_psm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_processpptables.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_hwmgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_thermal.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_overdriver.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu_helper.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_processpptables.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_hwmgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_powertune.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_thermal.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/common_baco.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_baco.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_baco.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_baco.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu9_baco.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/tonga_baco.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/polaris_baco.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/fiji_baco.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ci_baco.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_baco.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/powerplay/amd_powerplay.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/legacy_dpm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_dpm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_smc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_dpm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_smc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_pm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crtc.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_color.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_services.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/basics/conversion.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/basics/fixpt31_32.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/basics/vector.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_interface.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_helper.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/top/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_common.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/vfn/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/vfn/uvfn.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/vfn/gv100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce60/command_table_helper_dce60.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/vfn/tu102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/vfn/ga100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper_dce112.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper2_dce112.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dce_calcs.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/custom_float.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/bw_fixed.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_rq_dlg_helpers.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dml1_display_rq_dlg_calc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn10/dcn10_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_vba.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/falcon.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/xtensa.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_rq_dlg_calc_21.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_rq_dlg_calc_30.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_rq_dlg_calc_31.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_mode_vba_314.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/ce/ga102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn321/dcn321_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn302/dcn302_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dsc/rc_calc_fpu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calcs.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/pci.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_math.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_auto.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/device/user.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce60/dce60_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/head.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce100/dce_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce110/dce110_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce112/dce112_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce120/dce120_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv2_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/dcn301_smu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_smu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_smu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_smu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_smu.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_audio.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_link_encoder.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/user.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_scl_filters.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/chid.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_dmcu.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/runq.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_abm.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_ipp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/g98.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_hw.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_sw.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_psr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_panel_cntl.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_hw_lock_mgr.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_outbox.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_base.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/base.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_factory.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_gpio.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_hpd.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_ddc.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_generic.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_translate.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce60/hw_translate_dce60.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce60/hw_factory_dce60.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_translate_dce80.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_factory_dce80.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_translate_dce110.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_factory_dce110.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_translate_dce120.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_factory_dce120.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_translate_dcn10.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_factory_dcn10.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_translate_dcn20.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_factory_dcn20.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_translate_dcn21.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_factory_dcn21.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn30/hw_translate_dcn30.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn30/hw_factory_dcn30.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn315/hw_translate_dcn315.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn315/hw_factory_dcn315.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn32/hw_translate_dcn32.o
  CC [M]  dri

[Intel-xe] ✓ CI.Hooks: success for Enable Lunar Lake display

[Patchwork]

== Series Details ==

Series: Enable Lunar Lake display
URL   : https://patchwork.freedesktop.org/series/122798/
State : success

== Summary ==

run-parts: executing /workspace/ci/hooks/00-showenv
+ pwd
+ ls -la
/workspace
total 636
drwxrwxr-x 10 1003 1003   4096 Aug 23 17:17 .
drwxr-xr-x  1 root root   4096 Aug 23 17:17 ..
-rw-rw-r--  1 1003 1003 389633 Aug 23 17:17 build.log
-rw-rw-r--  1 1003 1003    819 Aug 23 17:12 checkpatch.log
drwxrwxr-x  5 1003 1003   4096 Aug 23 17:11 ci
drwxrwxr-x  9 1003 1003   4096 Aug 23 17:10 docker
drwxrwxr-x  8 1003 1003   4096 Aug 23 17:10 .git
-rw-rw-r--  1 1003 1003   2653 Aug 23 17:12 git_apply.log
drwxrwxr-x  4 1003 1003   4096 Aug 23 17:10 .github
-rw-rw-r--  1 1003 1003    233 Aug 23 17:10 .groovylintrc.json
-rw-rw-r--  1 1003 1003     78 Aug 23 17:17 hooks.log
drwxrwxr-x 31 1003 1003   4096 Aug 23 17:17 kernel
-rw-rw-r--  1 1003 1003 162525 Aug 23 17:12 kernel.mbox
-rw-rw-r--  1 1003 1003  26091 Aug 23 17:13 kunit.log
-rw-rw-r--  1 1003 1003     48 Aug 23 17:12 parent.tag
drwxrwxr-x 45 1003 1003   4096 Aug 23 17:10 pipelines
-rw-rw-r--  1 1003 1003    793 Aug 23 17:10 README.adoc
drwxrwxr-x  3 1003 1003   4096 Aug 23 17:10 scripts
drwxrwxr-x  2 1003 1003   4096 Aug 23 17:10 .vscode
+ uname -a
Linux f27040101db7 5.4.0-149-generic #166-Ubuntu SMP Tue Apr 18 16:51:45 UTC 2023 x86_64 x86_64 x86_64 GNU/Linux
+ export
+ grep -Ei '(^|\W)CI_'
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64"
declare -x CI_KERNEL_IMAGES_DIR="/workspace/kernel/archive/boot"
declare -x CI_KERNEL_MODULES_DIR="/workspace/kernel/archive"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
+ '[' -n /workspace ']'
+ git_args='-C /workspace/kernel'
+ git_log_args=
+ git --no-pager -C /workspace/kernel log --format=oneline --abbrev-commit
7a7fb548b drm/xe/lnl: Enable the display support
864377c6f drm/i915/xe2lpd: Update mbus on post plane updates
e808d0dea drm/i915/lnl: Add support to check c10 phy link rate
b1c80f064 drm/i915/lnl: Add pll table for LNL platform
c64abf87f drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.
1f972b26c drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
543c95a76 drm/i915/lnl: Add support for CDCLK initialization sequence
4f9e931f7 drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
d99d99fbe drm/i915/lnl: Start using CDCLK through PLL
a0a66463a drm/i915/lnl: Add CDCLK table
865b8202a drm/i915/lnl: Introduce MDCLK
be76a2fdd drm/i915/lnl: Add gmbus/ddc support
ede7c2f44 drm/i915/xe2lpd: Extend Wa_15010685871
8a8ef87d0 drm/i915/xe2lpd: Add support for HPD
7e21cb54f drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd
5a1f92f74 drm/i915/xe2lpd: Read pin assignment from IOM
433d3d183 drm/i915/xe2lpd: Handle port AUX interrupts
4356f16bb drm/i915/xe2lpd: Add support for DP aux channels
9891129c0 drm/i915/display: Remove FBC capability from fused off pipes
20495b494 drm/i915/xe2lpd: FBC is now supported on all pipes
1fe4dde9e drm/i915/xe2lpd: Add DC state support
d03a63d37 drm/i915/xe2lpd: Add display power well
fd46b6348 drm/i915/xe2lpd: Register DE_RRMR has been removed
e5acb29e1 drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
c886d5588 drm/i915/xe2lpd: Move registers to PICA
d075f1a0b drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL
4c5bd89d1 drm/i915/xe2lpd: Move D2D enable/disable
ae9221874 drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
39aca337c drm/i915/lnl: Add fake PCH
f618bbc11 drm/i915: Re-order if/else ladder in intel_detect_pch()
e17c6b692 drm/i915/lnl: Add display definitions
689a5b110 drm/xe/lnl: Add IS_LUNARLAKE
a0f67eb6f drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()
f3d99060f drm/i915/tc: move legacy code out of the main _max_lane_count() func
20c1ccb68 drm/i915/tc: make intel_tc_port_get_lane_mask() static
51b4a907d drm/i915/tc: rename mtl_tc_port_get_pin_assignment_mask()
1e59f5b4a drm/i915/cx0: Program vswing only for owned lanes
60a4bf7d8 drm/i915/cx0: Enable/disable TX only for owned PHY lanes
6bb63deeb drm/i915: Simplify intel_cx0_program_phy_lane() with loop
554a10101 drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
1fa4315d8 drm/i915/display: Remove unused POWER_DOMAIN_MASK
db1ba75c3 drm/i915: Start using plane scale factor for relative data rate
8ca78f69c drm/xe: Drop xe_mmio_write64()
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64 ']'
+ BUILD_DIR=/workspace/kernel/build64
+ cd /workspace/kernel
+ grep -q -e '^CONFIG_DRM_XE_DISPLAY=[yY]' /workspace/kernel/build64/.config
+ RESTORE_DISPLAY_CONFIG=1
+ trap cleanup EXIT
+ ./scripts/config --file /workspace/kernel/build64/.config --disable CONFIG_DRM_XE_DISPLAY
++ nproc
+ make -j48 O=/workspace/kernel/build64 modules_prepare
make[1]: Entering directory '/workspace/kernel/build64'
  SYNC    include/config/auto.conf.cmd
  GEN     Makefile
  GEN     Makefile
  UPD     include/generated/compile.h
  UPD     include/config/kernel.release
  UPD     include/generated/utsrelease.h
  DESCEND objtool
  CALL    ../scripts/checksyscalls.sh
  HOSTCC  /workspace/kernel/build64/tools/objtool/fixdep.o
  HOSTLD  /workspace/kernel/build64/tools/objtool/fixdep-in.o
  LINK    /workspace/kernel/build64/tools/objtool/fixdep
  INSTALL libsubcmd_headers
  CC      /workspace/kernel/build64/tools/objtool/libsubcmd/exec-cmd.o
  CC      /workspace/kernel/build64/tools/objtool/libsubcmd/help.o
  CC      /workspace/kernel/build64/tools/objtool/libsubcmd/pager.o
  CC      /workspace/kernel/build64/tools/objtool/libsubcmd/parse-options.o
  CC      /workspace/kernel/build64/tools/objtool/libsubcmd/run-command.o
  CC      /workspace/kernel/build64/tools/objtool/libsubcmd/sigchain.o
  CC      /workspace/kernel/build64/tools/objtool/libsubcmd/subcmd-config.o
  LD      /workspace/kernel/build64/tools/objtool/libsubcmd/libsubcmd-in.o
  AR      /workspace/kernel/build64/tools/objtool/libsubcmd/libsubcmd.a
  CC      /workspace/kernel/build64/tools/objtool/weak.o
  CC      /workspace/kernel/build64/tools/objtool/check.o
  CC      /workspace/kernel/build64/tools/objtool/special.o
  CC      /workspace/kernel/build64/tools/objtool/builtin-check.o
  CC      /workspace/kernel/build64/tools/objtool/elf.o
  CC      /workspace/kernel/build64/tools/objtool/objtool.o
  CC      /workspace/kernel/build64/tools/objtool/orc_gen.o
  CC      /workspace/kernel/build64/tools/objtool/orc_dump.o
  CC      /workspace/kernel/build64/tools/objtool/libstring.o
  CC      /workspace/kernel/build64/tools/objtool/libctype.o
  CC      /workspace/kernel/build64/tools/objtool/str_error_r.o
  CC      /workspace/kernel/build64/tools/objtool/librbtree.o
  CC      /workspace/kernel/build64/tools/objtool/arch/x86/special.o
  CC      /workspace/kernel/build64/tools/objtool/arch/x86/decode.o
  LD      /workspace/kernel/build64/tools/objtool/arch/x86/objtool-in.o
  LD      /workspace/kernel/build64/tools/objtool/objtool-in.o
  LINK    /workspace/kernel/build64/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64'
++ nproc
+ make -j48 O=/workspace/kernel/build64 M=drivers/gpu/drm/xe W=1
make[1]: Entering directory '/workspace/kernel/build64'
  CC [M]  drivers/gpu/drm/xe/xe_bb.o
  CC [M]  drivers/gpu/drm/xe/xe_bo.o
  CC [M]  drivers/gpu/drm/xe/xe_bo_evict.o
  CC [M]  drivers/gpu/drm/xe/xe_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_devcoredump.o
  CC [M]  drivers/gpu/drm/xe/xe_device.o
  CC [M]  drivers/gpu/drm/xe/xe_device_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_dma_buf.o
  CC [M]  drivers/gpu/drm/xe/xe_exec.o
  CC [M]  drivers/gpu/drm/xe/xe_execlist.o
  CC [M]  drivers/gpu/drm/xe/xe_exec_queue.o
  CC [M]  drivers/gpu/drm/xe/xe_force_wake.o
  CC [M]  drivers/gpu/drm/xe/xe_ggtt.o
  CC [M]  drivers/gpu/drm/xe/xe_gt.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_clock.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_idle_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_mcr.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_pagefault.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
  CC [M]  drivers/gpu/drm/xe/xe_gt_topology.o
  HOSTCC  drivers/gpu/drm/xe/xe_gen_wa_oob
  CC [M]  drivers/gpu/drm/xe/xe_guc_ads.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_ct.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_hwconfig.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_log.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_pc.o
  CC [M]  drivers/gpu/drm/xe/xe_guc_submit.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_engine.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_hw_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_huc.o
  CC [M]  drivers/gpu/drm/xe/xe_huc_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_irq.o
  CC [M]  drivers/gpu/drm/xe/xe_lrc.o
  CC [M]  drivers/gpu/drm/xe/xe_migrate.o
  CC [M]  drivers/gpu/drm/xe/xe_mmio.o
  CC [M]  drivers/gpu/drm/xe/xe_mocs.o
  CC [M]  drivers/gpu/drm/xe/xe_module.o
  CC [M]  drivers/gpu/drm/xe/xe_pat.o
  CC [M]  drivers/gpu/drm/xe/xe_pci.o
  CC [M]  drivers/gpu/drm/xe/xe_pcode.o
  CC [M]  drivers/gpu/drm/xe/xe_pm.o
  CC [M]  drivers/gpu/drm/xe/xe_preempt_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_pt.o
  CC [M]  drivers/gpu/drm/xe/xe_pt_walk.o
  CC [M]  drivers/gpu/drm/xe/xe_query.o
  CC [M]  drivers/gpu/drm/xe/xe_range_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_reg_sr.o
  CC [M]  drivers/gpu/drm/xe/xe_reg_whitelist.o
  CC [M]  drivers/gpu/drm/xe/xe_rtp.o
  CC [M]  drivers/gpu/drm/xe/xe_sa.o
  CC [M]  drivers/gpu/drm/xe/xe_sched_job.o
  CC [M]  drivers/gpu/drm/xe/xe_step.o
  CC [M]  drivers/gpu/drm/xe/xe_sync.o
  CC [M]  drivers/gpu/drm/xe/xe_tile.o
  CC [M]  drivers/gpu/drm/xe/xe_tile_sysfs.o
  CC [M]  drivers/gpu/drm/xe/xe_trace.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
  CC [M]  drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
  CC [M]  drivers/gpu/drm/xe/xe_tuning.o
  CC [M]  drivers/gpu/drm/xe/xe_uc.o
  CC [M]  drivers/gpu/drm/xe/xe_uc_debugfs.o
  CC [M]  drivers/gpu/drm/xe/xe_uc_fw.o
  CC [M]  drivers/gpu/drm/xe/xe_vm_madvise.o
  CC [M]  drivers/gpu/drm/xe/xe_wait_user_fence.o
  CC [M]  drivers/gpu/drm/xe/xe_wopcm.o
  HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
  CC [M]  drivers/gpu/drm/xe/tests/xe_bo_test.o
  HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h
  HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h
  CC [M]  drivers/gpu/drm/xe/tests/xe_dma_buf_test.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h
  CC [M]  drivers/gpu/drm/xe/tests/xe_migrate_test.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h
  CC [M]  drivers/gpu/drm/xe/tests/xe_pci_test.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_rtp_test.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_wa_test.o
  HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h
  HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_test.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h
  HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h
  HDRTEST drivers/gpu/drm/xe/xe_bb.h
  HDRTEST drivers/gpu/drm/xe/xe_bb_types.h
  HDRTEST drivers/gpu/drm/xe/xe_bo.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h
  HDRTEST drivers/gpu/drm/xe/xe_bo_types.h
  HDRTEST drivers/gpu/drm/xe/xe_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_devcoredump.h
  HDRTEST drivers/gpu/drm/xe/xe_devcoredump_types.h
  HDRTEST drivers/gpu/drm/xe/xe_device.h
  HDRTEST drivers/gpu/drm/xe/xe_device_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_device_types.h
  HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h
  HDRTEST drivers/gpu/drm/xe/xe_drv.h
  HDRTEST drivers/gpu/drm/xe/xe_exec.h
  HDRTEST drivers/gpu/drm/xe/xe_exec_queue.h
  HDRTEST drivers/gpu/drm/xe/xe_exec_queue_types.h
  HDRTEST drivers/gpu/drm/xe/xe_execlist.h
  HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h
  HDRTEST drivers/gpu/drm/xe/xe_force_wake.h
  HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h
  HDRTEST drivers/gpu/drm/xe/xe_ggtt.h
  HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_printk.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h
  HDRTEST drivers/gpu/drm/xe/xe_gt_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_log.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_submit_types.h
  HDRTEST drivers/gpu/drm/xe/xe_guc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_huc.h
  HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_huc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h
  HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h
  HDRTEST drivers/gpu/drm/xe/xe_irq.h
  HDRTEST drivers/gpu/drm/xe/xe_lrc.h
  HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_macros.h
  HDRTEST drivers/gpu/drm/xe/xe_map.h
  HDRTEST drivers/gpu/drm/xe/xe_migrate.h
  HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_mmio.h
  HDRTEST drivers/gpu/drm/xe/xe_mocs.h
  HDRTEST drivers/gpu/drm/xe/xe_module.h
  HDRTEST drivers/gpu/drm/xe/xe_pat.h
  HDRTEST drivers/gpu/drm/xe/xe_pci.h
  HDRTEST drivers/gpu/drm/xe/xe_pci_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pcode.h
  HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h
  HDRTEST drivers/gpu/drm/xe/xe_platform_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pm.h
  HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h
  HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pt.h
  HDRTEST drivers/gpu/drm/xe/xe_pt_types.h
  HDRTEST drivers/gpu/drm/xe/xe_pt_walk.h
  HDRTEST drivers/gpu/drm/xe/xe_query.h
  HDRTEST drivers/gpu/drm/xe/xe_range_fence.h
  HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h
  HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h
  HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h
  HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h
  HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h
  HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h
  HDRTEST drivers/gpu/drm/xe/xe_rtp.h
  HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h
  HDRTEST drivers/gpu/drm/xe/xe_sa.h
  HDRTEST drivers/gpu/drm/xe/xe_sched_job.h
  HDRTEST drivers/gpu/drm/xe/xe_sa_types.h
  HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h
  HDRTEST drivers/gpu/drm/xe/xe_step.h
  HDRTEST drivers/gpu/drm/xe/xe_step_types.h
  HDRTEST drivers/gpu/drm/xe/xe_sync.h
  HDRTEST drivers/gpu/drm/xe/xe_sync_types.h
  HDRTEST drivers/gpu/drm/xe/xe_tile.h
  HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs.h
  HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs_types.h
  HDRTEST drivers/gpu/drm/xe/xe_trace.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_sys_mgr.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
  HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
  HDRTEST drivers/gpu/drm/xe/xe_tuning.h
  HDRTEST drivers/gpu/drm/xe/xe_uc.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_debugfs.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw_abi.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_fw_types.h
  HDRTEST drivers/gpu/drm/xe/xe_uc_types.h
  HDRTEST drivers/gpu/drm/xe/xe_vm.h
  HDRTEST drivers/gpu/drm/xe/xe_vm_doc.h
  HDRTEST drivers/gpu/drm/xe/xe_vm_madvise.h
  HDRTEST drivers/gpu/drm/xe/xe_vm_types.h
  HDRTEST drivers/gpu/drm/xe/xe_wa.h
  HDRTEST drivers/gpu/drm/xe/xe_wait_user_fence.h
  HDRTEST drivers/gpu/drm/xe/xe_wopcm.h
  HDRTEST drivers/gpu/drm/xe/xe_wopcm_types.h
  GEN     xe_wa_oob.c xe_wa_oob.h
  GEN     xe_wa_oob.c xe_wa_oob.h
  CC [M]  drivers/gpu/drm/xe/xe_guc.o
  CC [M]  drivers/gpu/drm/xe/xe_ring_ops.o
  CC [M]  drivers/gpu/drm/xe/xe_vm.o
  CC [M]  drivers/gpu/drm/xe/xe_wa.o
  LD [M]  drivers/gpu/drm/xe/xe.o
  MODPOST drivers/gpu/drm/xe/Module.symvers
  CC [M]  drivers/gpu/drm/xe/xe.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_bo_test.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_dma_buf_test.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_migrate_test.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_pci_test.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_rtp_test.mod.o
  CC [M]  drivers/gpu/drm/xe/tests/xe_wa_test.mod.o
  LD [M]  drivers/gpu/drm/xe/tests/xe_bo_test.ko
  LD [M]  drivers/gpu/drm/xe/tests/xe_rtp_test.ko
  LD [M]  drivers/gpu/drm/xe/tests/xe_dma_buf_test.ko
  LD [M]  drivers/gpu/drm/xe/tests/xe_wa_test.ko
  LD [M]  drivers/gpu/drm/xe/tests/xe_pci_test.ko
  LD [M]  drivers/gpu/drm/xe/xe.ko
  LD [M]  drivers/gpu/drm/xe/tests/xe_migrate_test.ko
make[1]: Leaving directory '/workspace/kernel/build64'
+ cleanup
+ '[' 1 -eq 1 ']'
+ ./scripts/config --file /workspace/kernel/build64/.config --enable CONFIG_DRM_XE_DISPLAY
run-parts: executing /workspace/ci/hooks/20-kernel-doc
+ SRC_DIR=/workspace/kernel
+ cd /workspace/kernel
+ find drivers/gpu/drm/xe/ -name '*.[ch]' -not -path 'drivers/gpu/drm/xe/display/*'
+ xargs ./scripts/kernel-doc -Werror -none include/uapi/drm/xe_drm.h
All hooks done

[Intel-xe] ✗ CI.checksparse: warning for Enable Lunar Lake display

[Patchwork]

== Series Details ==

Series: Enable Lunar Lake display
URL   : https://patchwork.freedesktop.org/series/122798/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 8ca78f69c23d5f68a24bdacc014f82eff9719980
/root/linux/maintainer-tools/dim: line 50: /root/.dimrc: No such file or directory
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable Lunar Lake display

[Patchwork]

== Series Details ==

Series: Enable Lunar Lake display
URL   : https://patchwork.freedesktop.org/series/122799/
State : failure

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/122799/revisions/1/mbox/ not applied
Applying: drm/i915: Start using plane scale factor for relative data rate
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_atomic_plane.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915: Start using plane scale factor for relative data rate
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

[Intel-xe] ✓ CI.BAT: success for Enable Lunar Lake display

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1913 bytes --]

== Series Details ==

Series: Enable Lunar Lake display
URL   : https://patchwork.freedesktop.org/series/122798/
State : success

== Summary ==

CI Bug Log - changes from xe-331-8ca78f69c23d5f68a24bdacc014f82eff9719980_BAT -> xe-pw-122798v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-122798v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
    - bat-adlp-7:         [PASS][1] -> [FAIL][2] ([Intel XE#480]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-331-8ca78f69c23d5f68a24bdacc014f82eff9719980/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-122798v1/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html

  * igt@xe_exec_threads@threads-mixed-fd-basic:
    - bat-atsm-2:         [PASS][3] -> [TIMEOUT][4] ([Intel XE#280])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-331-8ca78f69c23d5f68a24bdacc014f82eff9719980/bat-atsm-2/igt@xe_exec_threads@threads-mixed-fd-basic.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-122798v1/bat-atsm-2/igt@xe_exec_threads@threads-mixed-fd-basic.html

  
  [Intel XE#280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/280
  [Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480


Build changes
-------------

  * Linux: xe-331-8ca78f69c23d5f68a24bdacc014f82eff9719980 -> xe-pw-122798v1

  IGT_7451: 5d48d1fb231f449fe2f80cda14ea7a1ecfda59fa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-331-8ca78f69c23d5f68a24bdacc014f82eff9719980: 8ca78f69c23d5f68a24bdacc014f82eff9719980
  xe-pw-122798v1: 122798v1



[-- Attachment #2: Type: text/html, Size: 2418 bytes --]

Re: [Intel-gfx] [Intel-xe] [PATCH 11/42] drm/xe/lnl: Add IS_LUNARLAKE

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:09AM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> Add IS_LUNARLAKE in the compat-i915-headers. That macro, to be used by
> the xe driver, checks for the platform, whereas the macro on the i915
> side is always false.

Stepping back, do we really need this macro?  Most display code should
be matching on the display IP rather than the platform going forward.
Looking at this series, I only see this used for fake PCH and GMBUS,
both of which I think could probably be checking the display IP rather
than the platform.


Matt

> 
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> ---
>  drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> index d64d34181790..38b64ff6b9ea 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> @@ -79,6 +79,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
>  #define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, XE_DG2)
>  #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
>  #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
> +#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
>  
>  #define IS_HSW_ULT(dev_priv) (dev_priv && 0)
>  #define IS_BDW_ULT(dev_priv) (dev_priv && 0)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 11/42] drm/xe/lnl: Add IS_LUNARLAKE

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:09AM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> Add IS_LUNARLAKE in the compat-i915-headers. That macro, to be used by
> the xe driver, checks for the platform, whereas the macro on the i915
> side is always false.

Stepping back, do we really need this macro?  Most display code should
be matching on the display IP rather than the platform going forward.
Looking at this series, I only see this used for fake PCH and GMBUS,
both of which I think could probably be checking the display IP rather
than the platform.


Matt

> 
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> ---
>  drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> index d64d34181790..38b64ff6b9ea 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> @@ -79,6 +79,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
>  #define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, XE_DG2)
>  #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
>  #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
> +#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
>  
>  #define IS_HSW_ULT(dev_priv) (dev_priv && 0)
>  #define IS_BDW_ULT(dev_priv) (dev_priv && 0)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 12/42] drm/i915/lnl: Add display definitions

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> Add Lunar Lake platform definitions for i915 display. The support for
> LNL will be added to the xe driver, with i915 only driving the display
> side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
> i915 module.
> 
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_device.c   | 15 +++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h                   |  1 +
>  2 files changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index f87470da25d0..b853cd0c704a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
>  		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
>  };
>  
> +static const struct intel_display_device_info xe2_lpd_display = {
> +	XE_LPD_FEATURES,
> +	.has_cdclk_crawl = 1,
> +	.has_cdclk_squash = 1,

XE_LPD_FEATURES, crawl, squash, transcoder mask, and port mask are all
common between Xe_LPD+ and Xe2_LPD.  Maybe we should add an
XE_LPDP_FEATURES macro first, and then re-use it here so that the deltas
are smaller and it's more obvious what the key changes are with this new
IP?

> +
> +	.__runtime_defaults.ip.ver = 20,
> +	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),

With Xe2, FBC is supported on all pipes now (bspec 68881, 68904).

> +	.__runtime_defaults.cpu_transcoder_mask =
> +		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> +	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
> +		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> +};
> +
>  __diag_pop();
>  
>  #undef INTEL_VGA_DEVICE
> @@ -795,6 +809,7 @@ static const struct {
>  	const struct intel_display_device_info *display;
>  } gmdid_display_map[] = {
>  	{ 14,  0, &xe_lpdp_display },
> +	{ 20,  0, &xe2_lpd_display },
>  };
>  
>  static const struct intel_display_device_info *
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 07f79b1028e1..96ac9a9cc155 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
>  #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
>  #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
> +#define IS_LUNARLAKE(dev_priv)  0

As noted on the previous patch, we might be able to drop this completely
if we update the fake PCH and gmbus code to match on display IP.  Given
that PCH isn't even involved in south display handling anymore, that
seems like it might be reasonable?  If anything, we're more likely to
need to match on PICA ID (which has its own GMD_ID register) than base
platform at some point in the future.


Matt

>  
>  #define IS_METEORLAKE_M(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 12/42] drm/i915/lnl: Add display definitions

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> Add Lunar Lake platform definitions for i915 display. The support for
> LNL will be added to the xe driver, with i915 only driving the display
> side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
> i915 module.
> 
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_device.c   | 15 +++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h                   |  1 +
>  2 files changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index f87470da25d0..b853cd0c704a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
>  		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
>  };
>  
> +static const struct intel_display_device_info xe2_lpd_display = {
> +	XE_LPD_FEATURES,
> +	.has_cdclk_crawl = 1,
> +	.has_cdclk_squash = 1,

XE_LPD_FEATURES, crawl, squash, transcoder mask, and port mask are all
common between Xe_LPD+ and Xe2_LPD.  Maybe we should add an
XE_LPDP_FEATURES macro first, and then re-use it here so that the deltas
are smaller and it's more obvious what the key changes are with this new
IP?

> +
> +	.__runtime_defaults.ip.ver = 20,
> +	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),

With Xe2, FBC is supported on all pipes now (bspec 68881, 68904).

> +	.__runtime_defaults.cpu_transcoder_mask =
> +		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> +	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
> +		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> +};
> +
>  __diag_pop();
>  
>  #undef INTEL_VGA_DEVICE
> @@ -795,6 +809,7 @@ static const struct {
>  	const struct intel_display_device_info *display;
>  } gmdid_display_map[] = {
>  	{ 14,  0, &xe_lpdp_display },
> +	{ 20,  0, &xe2_lpd_display },
>  };
>  
>  static const struct intel_display_device_info *
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 07f79b1028e1..96ac9a9cc155 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
>  #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
>  #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
> +#define IS_LUNARLAKE(dev_priv)  0

As noted on the previous patch, we might be able to drop this completely
if we update the fake PCH and gmbus code to match on display IP.  Given
that PCH isn't even involved in south display handling anymore, that
seems like it might be reasonable?  If anything, we're more likely to
need to match on PICA ID (which has its own GMD_ID register) than base
platform at some point in the future.


Matt

>  
>  #define IS_METEORLAKE_M(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 13/42] drm/i915: Re-order if/else ladder in intel_detect_pch()

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:11AM -0700, Lucas De Marchi wrote:
> Follow the convention of checking the last platform first and reword the
> comment to convey there are more platforms than just DG1.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/soc/intel_pch.c | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
> index ba9843cb1b13..cf795ecdcc26 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.c
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
> @@ -216,13 +216,16 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
>  	unsigned short id;
>  	enum intel_pch pch_type;
>  
> -	/* DG1 has south engine display on the same PCI device */
> -	if (IS_DG1(dev_priv)) {
> -		dev_priv->pch_type = PCH_DG1;
> -		return;
> -	} else if (IS_DG2(dev_priv)) {
> +	/*
> +	 * South display engine on the same PCI device: just assign the fake
> +	 * PCH.
> +	 */
> +	if (IS_DG2(dev_priv)) {
>  		dev_priv->pch_type = PCH_DG2;
>  		return;
> +	} else if (IS_DG1(dev_priv)) {
> +		dev_priv->pch_type = PCH_DG1;
> +		return;
>  	}
>  
>  	/*
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 13/42] drm/i915: Re-order if/else ladder in intel_detect_pch()

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:11AM -0700, Lucas De Marchi wrote:
> Follow the convention of checking the last platform first and reword the
> comment to convey there are more platforms than just DG1.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/soc/intel_pch.c | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
> index ba9843cb1b13..cf795ecdcc26 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.c
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
> @@ -216,13 +216,16 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
>  	unsigned short id;
>  	enum intel_pch pch_type;
>  
> -	/* DG1 has south engine display on the same PCI device */
> -	if (IS_DG1(dev_priv)) {
> -		dev_priv->pch_type = PCH_DG1;
> -		return;
> -	} else if (IS_DG2(dev_priv)) {
> +	/*
> +	 * South display engine on the same PCI device: just assign the fake
> +	 * PCH.
> +	 */
> +	if (IS_DG2(dev_priv)) {
>  		dev_priv->pch_type = PCH_DG2;
>  		return;
> +	} else if (IS_DG1(dev_priv)) {
> +		dev_priv->pch_type = PCH_DG1;
> +		return;
>  	}
>  
>  	/*
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 14/42] drm/i915/lnl: Add fake PCH

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:12AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> LNL has south display on the same SoC. As such, define a new fake PCH
> entry for it.

As mentioned on the earlier patches, either matching on display IP or
PICA ID might be more appropriate than matching on LNL base platform?


Matt

> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
>  drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
> index cf795ecdcc26..5b9a01d26cab 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.c
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
> @@ -220,7 +220,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
>  	 * South display engine on the same PCI device: just assign the fake
>  	 * PCH.
>  	 */
> -	if (IS_DG2(dev_priv)) {
> +	if (IS_LUNARLAKE(dev_priv)) {
> +		dev_priv->pch_type = PCH_LNL;
> +		return;
> +	} else if (IS_DG2(dev_priv)) {
>  		dev_priv->pch_type = PCH_DG2;
>  		return;
>  	} else if (IS_DG1(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
> index 32aff5a70d04..1b03ea60a7a8 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.h
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.h
> @@ -30,6 +30,7 @@ enum intel_pch {
>  	/* Fake PCHs, functionality handled on the same PCI dev */
>  	PCH_DG1 = 1024,
>  	PCH_DG2,
> +	PCH_LNL,
>  };
>  
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff80
> @@ -66,6 +67,7 @@ enum intel_pch {
>  
>  #define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
>  #define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
> +#define HAS_PCH_LNL(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
>  #define HAS_PCH_MTP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
>  #define HAS_PCH_DG2(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
>  #define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 14/42] drm/i915/lnl: Add fake PCH

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:12AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> LNL has south display on the same SoC. As such, define a new fake PCH
> entry for it.

As mentioned on the earlier patches, either matching on display IP or
PICA ID might be more appropriate than matching on LNL base platform?


Matt

> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
>  drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
> index cf795ecdcc26..5b9a01d26cab 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.c
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
> @@ -220,7 +220,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
>  	 * South display engine on the same PCI device: just assign the fake
>  	 * PCH.
>  	 */
> -	if (IS_DG2(dev_priv)) {
> +	if (IS_LUNARLAKE(dev_priv)) {
> +		dev_priv->pch_type = PCH_LNL;
> +		return;
> +	} else if (IS_DG2(dev_priv)) {
>  		dev_priv->pch_type = PCH_DG2;
>  		return;
>  	} else if (IS_DG1(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
> index 32aff5a70d04..1b03ea60a7a8 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.h
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.h
> @@ -30,6 +30,7 @@ enum intel_pch {
>  	/* Fake PCHs, functionality handled on the same PCI dev */
>  	PCH_DG1 = 1024,
>  	PCH_DG2,
> +	PCH_LNL,
>  };
>  
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff80
> @@ -66,6 +67,7 @@ enum intel_pch {
>  
>  #define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
>  #define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
> +#define HAS_PCH_LNL(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
>  #define HAS_PCH_MTP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
>  #define HAS_PCH_DG2(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
>  #define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 15/42] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:13AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> We now start calculating relative plane data rate for sursor plane as

s/sursor/cursor/

> well, as instructed by BSpec and also treat cursor plane same way as
> other planes, when doing allocation, i.e not using fixed allocation for
> cursor anymore.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Bspec: 68907
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c    |  6 +++---
>  drivers/gpu/drm/i915/display/skl_watermark.c     | 16 +++++++++-------
>  2 files changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index cb60165bc415..fb13f0bb8c52 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -219,9 +219,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
>  	int width, height;
>  	unsigned int rel_data_rate;
>  
> -	if (plane->id == PLANE_CURSOR)
> -		return 0;
> -
>  	if (!plane_state->uapi.visible)
>  		return 0;
>  
> @@ -249,6 +246,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
>  
>  	rel_data_rate = width * height * fb->format->cpp[color_plane];
>  
> +	if (plane->id == PLANE_CURSOR)
> +		return rel_data_rate;
> +
>  	return intel_adjusted_rate(&plane_state->uapi.src,
>  				   &plane_state->uapi.dst,
>  				   rel_data_rate);
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 063929a42a42..64a122d3c9c0 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
>  	u64 data_rate = 0;
>  
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
> -		if (plane_id == PLANE_CURSOR)
> +		if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
>  			continue;
>  
>  		data_rate += crtc_state->rel_data_rate[plane_id];
> @@ -1514,10 +1514,12 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  		return 0;
>  
>  	/* Allocate fixed number of blocks for cursor. */
> -	cursor_size = skl_cursor_allocation(crtc_state, num_active);
> -	iter.size -= cursor_size;
> -	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
> -			   alloc->end - cursor_size, alloc->end);
> +	if (DISPLAY_VER(i915) < 20) {
> +		cursor_size = skl_cursor_allocation(crtc_state, num_active);
> +		iter.size -= cursor_size;
> +		skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
> +				   alloc->end - cursor_size, alloc->end);
> +	}
>  
>  	iter.data_rate = skl_total_relative_data_rate(crtc_state);
>  
> @@ -1531,7 +1533,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  			const struct skl_plane_wm *wm =
>  				&crtc_state->wm.skl.optimal.planes[plane_id];
>  
> -			if (plane_id == PLANE_CURSOR) {
> +			if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20) {
>  				const struct skl_ddb_entry *ddb =
>  					&crtc_state->wm.skl.plane_ddb[plane_id];
>  
> @@ -1579,7 +1581,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  		const struct skl_plane_wm *wm =
>  			&crtc_state->wm.skl.optimal.planes[plane_id];
>  
> -		if (plane_id == PLANE_CURSOR)
> +		if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
>  			continue;
>  
>  		if (DISPLAY_VER(i915) < 11 &&
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 15/42] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:13AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> We now start calculating relative plane data rate for sursor plane as

s/sursor/cursor/

> well, as instructed by BSpec and also treat cursor plane same way as
> other planes, when doing allocation, i.e not using fixed allocation for
> cursor anymore.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Bspec: 68907
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c    |  6 +++---
>  drivers/gpu/drm/i915/display/skl_watermark.c     | 16 +++++++++-------
>  2 files changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index cb60165bc415..fb13f0bb8c52 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -219,9 +219,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
>  	int width, height;
>  	unsigned int rel_data_rate;
>  
> -	if (plane->id == PLANE_CURSOR)
> -		return 0;
> -
>  	if (!plane_state->uapi.visible)
>  		return 0;
>  
> @@ -249,6 +246,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
>  
>  	rel_data_rate = width * height * fb->format->cpp[color_plane];
>  
> +	if (plane->id == PLANE_CURSOR)
> +		return rel_data_rate;
> +
>  	return intel_adjusted_rate(&plane_state->uapi.src,
>  				   &plane_state->uapi.dst,
>  				   rel_data_rate);
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 063929a42a42..64a122d3c9c0 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
>  	u64 data_rate = 0;
>  
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
> -		if (plane_id == PLANE_CURSOR)
> +		if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
>  			continue;
>  
>  		data_rate += crtc_state->rel_data_rate[plane_id];
> @@ -1514,10 +1514,12 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  		return 0;
>  
>  	/* Allocate fixed number of blocks for cursor. */
> -	cursor_size = skl_cursor_allocation(crtc_state, num_active);
> -	iter.size -= cursor_size;
> -	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
> -			   alloc->end - cursor_size, alloc->end);
> +	if (DISPLAY_VER(i915) < 20) {
> +		cursor_size = skl_cursor_allocation(crtc_state, num_active);
> +		iter.size -= cursor_size;
> +		skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
> +				   alloc->end - cursor_size, alloc->end);
> +	}
>  
>  	iter.data_rate = skl_total_relative_data_rate(crtc_state);
>  
> @@ -1531,7 +1533,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  			const struct skl_plane_wm *wm =
>  				&crtc_state->wm.skl.optimal.planes[plane_id];
>  
> -			if (plane_id == PLANE_CURSOR) {
> +			if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20) {
>  				const struct skl_ddb_entry *ddb =
>  					&crtc_state->wm.skl.plane_ddb[plane_id];
>  
> @@ -1579,7 +1581,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  		const struct skl_plane_wm *wm =
>  			&crtc_state->wm.skl.optimal.planes[plane_id];
>  
> -		if (plane_id == PLANE_CURSOR)
> +		if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
>  			continue;
>  
>  		if (DISPLAY_VER(i915) < 11 &&
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 16/42] drm/i915/xe2lpd: Move D2D enable/disable

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:14AM -0700, Lucas De Marchi wrote:
> Bits to enable/disable and check state for D2D moved from
> XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions

As of Xe2, DDI_BUF_CTL is now renamed to "DDI_CTL_DE" in the spec, so
you might want to toss a mention of the new register name in the commit
message here to make it easier to lookup in the spec.  E.g.,
"... (now named DDI_CTL_DE in the spec) ..."  Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with
> multiple reg location and bitfield layout.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 38 +++++++++++++++++-------
>  drivers/gpu/drm/i915/i915_reg.h          |  2 ++
>  2 files changed, 30 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 61722556bb47..a9440c0ecf61 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2356,13 +2356,22 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
> +	i915_reg_t reg;
> +	u32 set_bits, wait_bits;
>  
> -	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
> -		     XELPDP_PORT_BUF_D2D_LINK_ENABLE);
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		reg = DDI_BUF_CTL(port);
> +		set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> +	} else {
> +		reg = XELPDP_PORT_BUF_CTL1(port);
> +		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> +	}
>  
> -	if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
> -			 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
> -		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
> +	intel_de_rmw(dev_priv, reg, 0, set_bits);
> +	if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
> +		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
>  			port_name(port));
>  	}
>  }
> @@ -2809,13 +2818,22 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
> +	i915_reg_t reg;
> +	u32 clr_bits, wait_bits;
>  
> -	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> -		     XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		reg = DDI_BUF_CTL(port);
> +		clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> +	} else {
> +		reg = XELPDP_PORT_BUF_CTL1(port);
> +		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> +	}
>  
> -	if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
> -			  XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
> -		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
> +	intel_de_rmw(dev_priv, reg, clr_bits, 0);
> +	if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
> +		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
>  			port_name(port));
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dcf64e32cd54..84c5a76065a0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5723,6 +5723,8 @@ enum skl_power_gate {
>  /* Known as DDI_CTL_DE in MTL+ */
>  #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
>  #define  DDI_BUF_CTL_ENABLE			(1 << 31)
> +#define  XE2LPD_DDI_BUF_D2D_LINK_ENABLE		REG_BIT(29)
> +#define  XE2LPD_DDI_BUF_D2D_LINK_STATE		REG_BIT(28)
>  #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
>  #define  DDI_BUF_EMP_MASK			(0xf << 24)
>  #define  DDI_BUF_PHY_LINK_RATE(r)		((r) << 20)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 16/42] drm/i915/xe2lpd: Move D2D enable/disable

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:14AM -0700, Lucas De Marchi wrote:
> Bits to enable/disable and check state for D2D moved from
> XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions

As of Xe2, DDI_BUF_CTL is now renamed to "DDI_CTL_DE" in the spec, so
you might want to toss a mention of the new register name in the commit
message here to make it easier to lookup in the spec.  E.g.,
"... (now named DDI_CTL_DE in the spec) ..."  Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with
> multiple reg location and bitfield layout.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 38 +++++++++++++++++-------
>  drivers/gpu/drm/i915/i915_reg.h          |  2 ++
>  2 files changed, 30 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 61722556bb47..a9440c0ecf61 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2356,13 +2356,22 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
> +	i915_reg_t reg;
> +	u32 set_bits, wait_bits;
>  
> -	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
> -		     XELPDP_PORT_BUF_D2D_LINK_ENABLE);
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		reg = DDI_BUF_CTL(port);
> +		set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> +	} else {
> +		reg = XELPDP_PORT_BUF_CTL1(port);
> +		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> +	}
>  
> -	if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
> -			 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
> -		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
> +	intel_de_rmw(dev_priv, reg, 0, set_bits);
> +	if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
> +		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
>  			port_name(port));
>  	}
>  }
> @@ -2809,13 +2818,22 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
> +	i915_reg_t reg;
> +	u32 clr_bits, wait_bits;
>  
> -	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> -		     XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		reg = DDI_BUF_CTL(port);
> +		clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> +	} else {
> +		reg = XELPDP_PORT_BUF_CTL1(port);
> +		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> +	}
>  
> -	if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
> -			  XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
> -		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
> +	intel_de_rmw(dev_priv, reg, clr_bits, 0);
> +	if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
> +		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
>  			port_name(port));
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dcf64e32cd54..84c5a76065a0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5723,6 +5723,8 @@ enum skl_power_gate {
>  /* Known as DDI_CTL_DE in MTL+ */
>  #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
>  #define  DDI_BUF_CTL_ENABLE			(1 << 31)
> +#define  XE2LPD_DDI_BUF_D2D_LINK_ENABLE		REG_BIT(29)
> +#define  XE2LPD_DDI_BUF_D2D_LINK_STATE		REG_BIT(28)
>  #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
>  #define  DDI_BUF_EMP_MASK			(0xf << 24)
>  #define  DDI_BUF_PHY_LINK_RATE(r)		((r) << 20)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:16AM -0700, Lucas De Marchi wrote:
> Some registers for DDI A/B moved to PICA and now follow the same format
> as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
> 
> 	- Share the implementation between xe2lpd and previous
> 	  platforms: there are minor layout changes, it's mostly the
> 	  register location that changed
> 	- Handle offsets after TC ports
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 81 ++++++++++---------
>  .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 71 ++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 18 +++--
>  3 files changed, 117 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a5918bf30c31..6533ec417806 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -98,7 +98,7 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
>  static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
>  					    enum port port, int lane)
>  {
> -	intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
> +	intel_de_rmw(i915, xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
>  		     0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
>  }
>  
> @@ -106,10 +106,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, i
>  {
>  	enum phy phy = intel_port_to_phy(i915, port);
>  
> -	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  		       XELPDP_PORT_M2P_TRANSACTION_RESET);
>  
> -	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_RESET,
>  				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
>  		drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
> @@ -125,7 +125,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port,
>  	enum phy phy = intel_port_to_phy(i915, port);
>  
>  	if (__intel_de_wait_for_register(i915,
> -					 XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
> +					 xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
>  					 XELPDP_PORT_P2M_RESPONSE_READY,
>  					 XELPDP_PORT_P2M_RESPONSE_READY,
>  					 XELPDP_MSGBUS_TIMEOUT_FAST_US,
> @@ -160,7 +160,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
>  	int ack;
>  	u32 val;
>  
> -	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
>  				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
>  		drm_dbg_kms(&i915->drm,
> @@ -169,7 +169,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
>  		return -ETIMEDOUT;
>  	}
>  
> -	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
>  		       XELPDP_PORT_M2P_COMMAND_READ |
>  		       XELPDP_PORT_M2P_ADDRESS(addr));
> @@ -220,7 +220,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
>  	int ack;
>  	u32 val;
>  
> -	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
>  				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
>  		drm_dbg_kms(&i915->drm,
> @@ -229,14 +229,14 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
>  		return -ETIMEDOUT;
>  	}
>  
> -	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
>  		       (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
>  				    XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
>  		       XELPDP_PORT_M2P_DATA(data) |
>  		       XELPDP_PORT_M2P_ADDRESS(addr));
>  
> -	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
>  				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
>  		drm_dbg_kms(&i915->drm,
> @@ -249,7 +249,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
>  		ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
>  		if (ack < 0)
>  			return ack;
> -	} else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) &
> +	} else if ((intel_de_read(i915, xelpdp_port_p2m_msgbus_status_reg(i915, port, lane)) &
>  		    XELPDP_PORT_P2M_ERROR_SET)) {
>  		drm_dbg_kms(&i915->drm,
>  			    "PHY %c Error occurred during write command.\n", phy_name(phy));
> @@ -2431,7 +2431,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	u32 val = 0;
>  
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
> +		     XELPDP_PORT_REVERSAL,
>  		     lane_reversal ? XELPDP_PORT_REVERSAL : 0);
>  
>  	if (lane_reversal)
> @@ -2451,7 +2452,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>  	else
>  		val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
>  
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
>  		     XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
>  		     XELPDP_SSC_ENABLE_PLLB, val);
> @@ -2484,15 +2485,16 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
>  						u8 lane_mask, u8 state)
>  {
>  	enum phy phy = intel_port_to_phy(i915, port);
> +	i915_reg_t buf_ctl2_reg = xelpdp_port_buf_ctl2_reg(i915, port);
>  	int lane;
>  
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> +	intel_de_rmw(i915, buf_ctl2_reg,
>  		     intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
>  		     intel_cx0_get_powerdown_state(lane_mask, state));
>  
>  	/* Wait for pending transactions.*/
>  	for_each_cx0_lane_in_mask(lane_mask, lane)
> -		if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +		if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  					    XELPDP_PORT_M2P_TRANSACTION_PENDING,
>  					    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
>  			drm_dbg_kms(&i915->drm,
> @@ -2501,12 +2503,12 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
>  			intel_cx0_bus_reset(i915, port, lane);
>  		}
>  
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> +	intel_de_rmw(i915, buf_ctl2_reg,
>  		     intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
>  		     intel_cx0_get_powerdown_update(lane_mask));
>  
>  	/* Update Timeout Value */
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> +	if (__intel_de_wait_for_register(i915, buf_ctl2_reg,
>  					 intel_cx0_get_powerdown_update(lane_mask), 0,
>  					 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
>  		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> @@ -2515,10 +2517,10 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
>  
>  static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
>  {
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port),
>  		     XELPDP_POWER_STATE_READY_MASK,
>  		     XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl3_reg(i915, port),
>  		     XELPDP_POWER_STATE_ACTIVE_MASK |
>  		     XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
>  		     XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
> @@ -2563,28 +2565,28 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
>  					   XELPDP_LANE_PHY_CURRENT_STATUS(1))
>  					: XELPDP_LANE_PHY_CURRENT_STATUS(0);
>  
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_buf_ctl1_reg(i915, port),
>  					 XELPDP_PORT_BUF_SOC_PHY_READY,
>  					 XELPDP_PORT_BUF_SOC_PHY_READY,
>  					 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
>  		drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
>  			 phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
>  
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port),
>  		     XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
>  		     lane_pipe_reset);
>  
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_buf_ctl2_reg(i915, port),
>  					 lane_phy_current_status, lane_phy_current_status,
>  					 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
>  		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
>  			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
>  
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, port),
>  		     intel_cx0_get_pclk_refclk_request(owned_lane_mask),
>  		     intel_cx0_get_pclk_refclk_request(lane_mask));
>  
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, port),
>  					 intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
>  					 intel_cx0_get_pclk_refclk_ack(lane_mask),
>  					 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
> @@ -2595,9 +2597,10 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
>  					    CX0_P2_STATE_RESET);
>  	intel_cx0_setup_powerdown(i915, port);
>  
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0);
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port), lane_pipe_reset, 0);
>  
> -	if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status,
> +	if (intel_de_wait_for_clear(i915, xelpdp_port_buf_ctl2_reg(i915, port),
> +				    lane_phy_current_status,
>  				    XELPDP_PORT_RESET_END_TIMEOUT))
>  		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
>  			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
> @@ -2726,12 +2729,12 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>  	 * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
>  	 * LN<Lane for maxPCLK> to "1" to enable PLL.
>  	 */
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
>  		     intel_cx0_get_pclk_pll_request(maxpclk_lane));
>  
>  	/* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  					 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
>  					 intel_cx0_get_pclk_pll_ack(maxpclk_lane),
>  					 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
> @@ -2751,7 +2754,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	u32 clock;
> -	u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> +	u32 val = intel_de_read(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port));
>  
>  	clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
>  
> @@ -2804,11 +2807,11 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
>  	 */
>  	val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
>  	val |= XELPDP_FORWARD_CLOCK_UNGATE;
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
>  
>  	/* 2. Read back PORT_CLOCK_CTL REGISTER */
> -	val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> +	val = intel_de_read(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port));
>  
>  	/*
>  	 * 3. Follow the Display Voltage Frequency Switching - Sequence
> @@ -2819,10 +2822,10 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
>  	 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
>  	 */
>  	val |= XELPDP_TBT_CLOCK_REQUEST;
> -	intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
> +	intel_de_write(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port), val);
>  
>  	/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  					 XELPDP_TBT_CLOCK_ACK,
>  					 XELPDP_TBT_CLOCK_ACK,
>  					 100, 0, NULL))
> @@ -2874,7 +2877,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
>  	 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
>  	 * to "0" to disable PLL.
>  	 */
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
>  		     intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
>  
> @@ -2884,7 +2887,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
>  	/*
>  	 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
>  	 */
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  					 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
>  					 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
>  					 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
> @@ -2897,9 +2900,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
>  	 */
>  
>  	/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_DDI_CLOCK_SELECT_MASK, 0);
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
>  
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
> @@ -2918,11 +2921,11 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
>  	/*
>  	 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
>  	 */
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_TBT_CLOCK_REQUEST, 0);
>  
>  	/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  					 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
>  		drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
>  			 encoder->base.base.id, encoder->base.name, phy_name(phy));
> @@ -2935,7 +2938,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
>  	/*
>  	 * 5. Program PORT CLOCK CTRL register to disable and gate clocks
>  	 */
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_DDI_CLOCK_SELECT_MASK |
>  		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index cb5d1be2ba19..4b5b9a97142d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -6,13 +6,15 @@
>  #ifndef __INTEL_CX0_PHY_REGS_H__
>  #define __INTEL_CX0_PHY_REGS_H__
>  
> +#include "i915_drv.h"
>  #include "i915_reg_defs.h"
> +#include "intel_display_limits.h"
>  
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A		0x64040
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B		0x64140
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1		0x16F240
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2		0x16F440
> -#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)		_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> @@ -27,7 +29,7 @@
>  #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
>  #define   XELPDP_PORT_M2P_ADDRESS_MASK			REG_GENMASK(11, 0)
>  #define   XELPDP_PORT_M2P_ADDRESS(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
> -#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)	_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> @@ -54,7 +56,7 @@
>  #define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104
>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1			0x16F200
>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2			0x16F400
> -#define XELPDP_PORT_BUF_CTL1(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL1(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -75,7 +77,7 @@
>  #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
>  #define   XELPDP_PORT_WIDTH(val)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
>  
> -#define XELPDP_PORT_BUF_CTL2(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL2(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -95,7 +97,7 @@
>  #define   XELPDP_POWER_STATE_READY_MASK			REG_GENMASK(7, 4)
>  #define   XELPDP_POWER_STATE_READY(val)			REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
>  
> -#define XELPDP_PORT_BUF_CTL3(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL3(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -114,7 +116,7 @@
>  #define _XELPDP_PORT_CLOCK_CTL_B			0x641E0
>  #define _XELPDP_PORT_CLOCK_CTL_USBC1			0x16F260
>  #define _XELPDP_PORT_CLOCK_CTL_USBC2			0x16F460
> -#define XELPDP_PORT_CLOCK_CTL(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_CLOCK_CTL(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_CLOCK_CTL_A, \
>  										 _XELPDP_PORT_CLOCK_CTL_B, \
>  										 _XELPDP_PORT_CLOCK_CTL_USBC1, \
> @@ -271,4 +273,61 @@
>  #define HDMI_DIV_MASK		REG_GENMASK16(2, 0)
>  #define HDMI_DIV(val)		REG_FIELD_PREP16(HDMI_DIV_MASK, val)
>  
> +/*
> + * All registers are in the same IP, with a single range.  However the registers
> + * for TC_PORT come first.
> + */
> +static inline enum port xe2lpd_port_idx(enum port port)
> +{
> +	return port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A;
> +}

Somewhat confusing, but this is still the cleanest way to implement it
that I can think of.  I guess the most unintuitive part here is that the
index handling above ensures (correctly) that for Xe2 the result always
falls in the upper range of the _PICK_EVEN_2RANGES() macro.  Maybe we
should mention that to help make the logic more understandable?  Up to
you.

> +
> +static inline i915_reg_t xelpdp_port_clock_ctl_reg(struct drm_i915_private *i915,
> +						   enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_CLOCK_CTL(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_CLOCK_CTL(port);
> +}

I think there's one instance of XELPDP_PORT_CLOCK_CTL that didn't get
converted to this function in intel_mtl_port_pll_type().

> +
> +static inline i915_reg_t xelpdp_port_buf_ctl3_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL3(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL3(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_buf_ctl2_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL2(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL2(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_buf_ctl1_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL1(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL1(port);
> +}

There are several uses of XELPDP_PORT_BUF_CTL1 that didn't get converted
in intel_tc.c and one in intel_ddi.c.


Matt

> +
> +static inline i915_reg_t xelpdp_port_m2p_msgbus_ctl_reg(struct drm_i915_private *i915,
> +							enum port port, int lane)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_M2P_MSGBUS_CTL(xe2lpd_port_idx(port), lane) :
> +		XELPDP_PORT_M2P_MSGBUS_CTL(port, lane);
> +}
> +
> +static inline i915_reg_t xelpdp_port_p2m_msgbus_status_reg(struct drm_i915_private *i915,
> +							   enum port port, int lane)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_P2M_MSGBUS_STATUS(xe2lpd_port_idx(port), lane) :
> +		XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane);
> +}
> +
>  #endif /* __INTEL_CX0_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3147ed174d83..3587ddc6d8ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -176,7 +176,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
>  	int ret;
>  
>  	/* FIXME: find out why Bspec's 100us timeout is too short */
> -	ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
> +	ret = wait_for_us((intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port)) &
>  			   XELPDP_PORT_BUF_PHY_IDLE), 10000);
>  	if (ret)
>  		drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
> @@ -224,7 +224,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
>  	}
>  
>  	if (DISPLAY_VER(dev_priv) >= 14)
> -		ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
> +		ret = _wait_for(!(intel_de_read(dev_priv,
> +						xelpdp_port_buf_ctl1_reg(dev_priv, port)) &
> +				  XELPDP_PORT_BUF_PHY_IDLE),
>  				timeout_us, 10, 10);
>  	else
>  		ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
> @@ -2365,7 +2367,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
> -		reg = XELPDP_PORT_BUF_CTL1(port);
> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>  		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>  	}
> @@ -2385,7 +2387,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>  	enum port port = encoder->port;
>  	u32 val;
>  
> -	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
> +	val = intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port));
>  	val &= ~XELPDP_PORT_WIDTH_MASK;
>  	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
>  
> @@ -2398,7 +2400,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>  	if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
>  		val |= XELPDP_PORT_REVERSAL;
>  
> -	intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
> +	intel_de_write(i915, xelpdp_port_buf_ctl1_reg(i915, port), val);
>  }
>  
>  static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
> @@ -2409,7 +2411,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>  
>  	val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
>  	      XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
>  		     XELPDP_PORT_BUF_IO_SELECT_TBT, val);
>  }
>  
> @@ -2829,7 +2831,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
> -		reg = XELPDP_PORT_BUF_CTL1(port);
> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>  		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>  	}
> @@ -2967,7 +2969,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>  
>  	/* De-select Thunderbolt */
>  	if (DISPLAY_VER(dev_priv) >= 14)
> -		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
> +		intel_de_rmw(dev_priv, xelpdp_port_buf_ctl1_reg(dev_priv, encoder->port),
>  			     XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
>  }
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:16AM -0700, Lucas De Marchi wrote:
> Some registers for DDI A/B moved to PICA and now follow the same format
> as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
> 
> 	- Share the implementation between xe2lpd and previous
> 	  platforms: there are minor layout changes, it's mostly the
> 	  register location that changed
> 	- Handle offsets after TC ports
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 81 ++++++++++---------
>  .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 71 ++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 18 +++--
>  3 files changed, 117 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a5918bf30c31..6533ec417806 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -98,7 +98,7 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
>  static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
>  					    enum port port, int lane)
>  {
> -	intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
> +	intel_de_rmw(i915, xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
>  		     0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
>  }
>  
> @@ -106,10 +106,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, i
>  {
>  	enum phy phy = intel_port_to_phy(i915, port);
>  
> -	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  		       XELPDP_PORT_M2P_TRANSACTION_RESET);
>  
> -	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_RESET,
>  				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
>  		drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
> @@ -125,7 +125,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port,
>  	enum phy phy = intel_port_to_phy(i915, port);
>  
>  	if (__intel_de_wait_for_register(i915,
> -					 XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
> +					 xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
>  					 XELPDP_PORT_P2M_RESPONSE_READY,
>  					 XELPDP_PORT_P2M_RESPONSE_READY,
>  					 XELPDP_MSGBUS_TIMEOUT_FAST_US,
> @@ -160,7 +160,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
>  	int ack;
>  	u32 val;
>  
> -	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
>  				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
>  		drm_dbg_kms(&i915->drm,
> @@ -169,7 +169,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
>  		return -ETIMEDOUT;
>  	}
>  
> -	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
>  		       XELPDP_PORT_M2P_COMMAND_READ |
>  		       XELPDP_PORT_M2P_ADDRESS(addr));
> @@ -220,7 +220,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
>  	int ack;
>  	u32 val;
>  
> -	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
>  				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
>  		drm_dbg_kms(&i915->drm,
> @@ -229,14 +229,14 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
>  		return -ETIMEDOUT;
>  	}
>  
> -	intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
>  		       (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
>  				    XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
>  		       XELPDP_PORT_M2P_DATA(data) |
>  		       XELPDP_PORT_M2P_ADDRESS(addr));
>  
> -	if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +	if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
>  				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
>  		drm_dbg_kms(&i915->drm,
> @@ -249,7 +249,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
>  		ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
>  		if (ack < 0)
>  			return ack;
> -	} else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) &
> +	} else if ((intel_de_read(i915, xelpdp_port_p2m_msgbus_status_reg(i915, port, lane)) &
>  		    XELPDP_PORT_P2M_ERROR_SET)) {
>  		drm_dbg_kms(&i915->drm,
>  			    "PHY %c Error occurred during write command.\n", phy_name(phy));
> @@ -2431,7 +2431,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	u32 val = 0;
>  
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
> +		     XELPDP_PORT_REVERSAL,
>  		     lane_reversal ? XELPDP_PORT_REVERSAL : 0);
>  
>  	if (lane_reversal)
> @@ -2451,7 +2452,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>  	else
>  		val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
>  
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
>  		     XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
>  		     XELPDP_SSC_ENABLE_PLLB, val);
> @@ -2484,15 +2485,16 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
>  						u8 lane_mask, u8 state)
>  {
>  	enum phy phy = intel_port_to_phy(i915, port);
> +	i915_reg_t buf_ctl2_reg = xelpdp_port_buf_ctl2_reg(i915, port);
>  	int lane;
>  
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> +	intel_de_rmw(i915, buf_ctl2_reg,
>  		     intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
>  		     intel_cx0_get_powerdown_state(lane_mask, state));
>  
>  	/* Wait for pending transactions.*/
>  	for_each_cx0_lane_in_mask(lane_mask, lane)
> -		if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> +		if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
>  					    XELPDP_PORT_M2P_TRANSACTION_PENDING,
>  					    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
>  			drm_dbg_kms(&i915->drm,
> @@ -2501,12 +2503,12 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
>  			intel_cx0_bus_reset(i915, port, lane);
>  		}
>  
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> +	intel_de_rmw(i915, buf_ctl2_reg,
>  		     intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
>  		     intel_cx0_get_powerdown_update(lane_mask));
>  
>  	/* Update Timeout Value */
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> +	if (__intel_de_wait_for_register(i915, buf_ctl2_reg,
>  					 intel_cx0_get_powerdown_update(lane_mask), 0,
>  					 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
>  		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> @@ -2515,10 +2517,10 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
>  
>  static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
>  {
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port),
>  		     XELPDP_POWER_STATE_READY_MASK,
>  		     XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl3_reg(i915, port),
>  		     XELPDP_POWER_STATE_ACTIVE_MASK |
>  		     XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
>  		     XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
> @@ -2563,28 +2565,28 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
>  					   XELPDP_LANE_PHY_CURRENT_STATUS(1))
>  					: XELPDP_LANE_PHY_CURRENT_STATUS(0);
>  
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_buf_ctl1_reg(i915, port),
>  					 XELPDP_PORT_BUF_SOC_PHY_READY,
>  					 XELPDP_PORT_BUF_SOC_PHY_READY,
>  					 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
>  		drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
>  			 phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
>  
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port),
>  		     XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
>  		     lane_pipe_reset);
>  
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_buf_ctl2_reg(i915, port),
>  					 lane_phy_current_status, lane_phy_current_status,
>  					 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
>  		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
>  			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
>  
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, port),
>  		     intel_cx0_get_pclk_refclk_request(owned_lane_mask),
>  		     intel_cx0_get_pclk_refclk_request(lane_mask));
>  
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, port),
>  					 intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
>  					 intel_cx0_get_pclk_refclk_ack(lane_mask),
>  					 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
> @@ -2595,9 +2597,10 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
>  					    CX0_P2_STATE_RESET);
>  	intel_cx0_setup_powerdown(i915, port);
>  
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0);
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl2_reg(i915, port), lane_pipe_reset, 0);
>  
> -	if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status,
> +	if (intel_de_wait_for_clear(i915, xelpdp_port_buf_ctl2_reg(i915, port),
> +				    lane_phy_current_status,
>  				    XELPDP_PORT_RESET_END_TIMEOUT))
>  		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
>  			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
> @@ -2726,12 +2729,12 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>  	 * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
>  	 * LN<Lane for maxPCLK> to "1" to enable PLL.
>  	 */
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
>  		     intel_cx0_get_pclk_pll_request(maxpclk_lane));
>  
>  	/* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  					 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
>  					 intel_cx0_get_pclk_pll_ack(maxpclk_lane),
>  					 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
> @@ -2751,7 +2754,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	u32 clock;
> -	u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> +	u32 val = intel_de_read(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port));
>  
>  	clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
>  
> @@ -2804,11 +2807,11 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
>  	 */
>  	val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
>  	val |= XELPDP_FORWARD_CLOCK_UNGATE;
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
>  
>  	/* 2. Read back PORT_CLOCK_CTL REGISTER */
> -	val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> +	val = intel_de_read(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port));
>  
>  	/*
>  	 * 3. Follow the Display Voltage Frequency Switching - Sequence
> @@ -2819,10 +2822,10 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
>  	 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
>  	 */
>  	val |= XELPDP_TBT_CLOCK_REQUEST;
> -	intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
> +	intel_de_write(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port), val);
>  
>  	/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  					 XELPDP_TBT_CLOCK_ACK,
>  					 XELPDP_TBT_CLOCK_ACK,
>  					 100, 0, NULL))
> @@ -2874,7 +2877,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
>  	 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
>  	 * to "0" to disable PLL.
>  	 */
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
>  		     intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
>  
> @@ -2884,7 +2887,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
>  	/*
>  	 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
>  	 */
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  					 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
>  					 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
>  					 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
> @@ -2897,9 +2900,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
>  	 */
>  
>  	/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_DDI_CLOCK_SELECT_MASK, 0);
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
>  
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
> @@ -2918,11 +2921,11 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
>  	/*
>  	 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
>  	 */
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_TBT_CLOCK_REQUEST, 0);
>  
>  	/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
> -	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	if (__intel_de_wait_for_register(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  					 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
>  		drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
>  			 encoder->base.base.id, encoder->base.name, phy_name(phy));
> @@ -2935,7 +2938,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
>  	/*
>  	 * 5. Program PORT CLOCK CTRL register to disable and gate clocks
>  	 */
> -	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_clock_ctl_reg(i915, encoder->port),
>  		     XELPDP_DDI_CLOCK_SELECT_MASK |
>  		     XELPDP_FORWARD_CLOCK_UNGATE, 0);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index cb5d1be2ba19..4b5b9a97142d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -6,13 +6,15 @@
>  #ifndef __INTEL_CX0_PHY_REGS_H__
>  #define __INTEL_CX0_PHY_REGS_H__
>  
> +#include "i915_drv.h"
>  #include "i915_reg_defs.h"
> +#include "intel_display_limits.h"
>  
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A		0x64040
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B		0x64140
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1		0x16F240
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2		0x16F440
> -#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)		_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> @@ -27,7 +29,7 @@
>  #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
>  #define   XELPDP_PORT_M2P_ADDRESS_MASK			REG_GENMASK(11, 0)
>  #define   XELPDP_PORT_M2P_ADDRESS(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
> -#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)	_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> @@ -54,7 +56,7 @@
>  #define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104
>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1			0x16F200
>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2			0x16F400
> -#define XELPDP_PORT_BUF_CTL1(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL1(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -75,7 +77,7 @@
>  #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
>  #define   XELPDP_PORT_WIDTH(val)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
>  
> -#define XELPDP_PORT_BUF_CTL2(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL2(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -95,7 +97,7 @@
>  #define   XELPDP_POWER_STATE_READY_MASK			REG_GENMASK(7, 4)
>  #define   XELPDP_POWER_STATE_READY(val)			REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
>  
> -#define XELPDP_PORT_BUF_CTL3(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL3(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -114,7 +116,7 @@
>  #define _XELPDP_PORT_CLOCK_CTL_B			0x641E0
>  #define _XELPDP_PORT_CLOCK_CTL_USBC1			0x16F260
>  #define _XELPDP_PORT_CLOCK_CTL_USBC2			0x16F460
> -#define XELPDP_PORT_CLOCK_CTL(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_CLOCK_CTL(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_CLOCK_CTL_A, \
>  										 _XELPDP_PORT_CLOCK_CTL_B, \
>  										 _XELPDP_PORT_CLOCK_CTL_USBC1, \
> @@ -271,4 +273,61 @@
>  #define HDMI_DIV_MASK		REG_GENMASK16(2, 0)
>  #define HDMI_DIV(val)		REG_FIELD_PREP16(HDMI_DIV_MASK, val)
>  
> +/*
> + * All registers are in the same IP, with a single range.  However the registers
> + * for TC_PORT come first.
> + */
> +static inline enum port xe2lpd_port_idx(enum port port)
> +{
> +	return port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A;
> +}

Somewhat confusing, but this is still the cleanest way to implement it
that I can think of.  I guess the most unintuitive part here is that the
index handling above ensures (correctly) that for Xe2 the result always
falls in the upper range of the _PICK_EVEN_2RANGES() macro.  Maybe we
should mention that to help make the logic more understandable?  Up to
you.

> +
> +static inline i915_reg_t xelpdp_port_clock_ctl_reg(struct drm_i915_private *i915,
> +						   enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_CLOCK_CTL(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_CLOCK_CTL(port);
> +}

I think there's one instance of XELPDP_PORT_CLOCK_CTL that didn't get
converted to this function in intel_mtl_port_pll_type().

> +
> +static inline i915_reg_t xelpdp_port_buf_ctl3_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL3(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL3(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_buf_ctl2_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL2(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL2(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_buf_ctl1_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL1(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL1(port);
> +}

There are several uses of XELPDP_PORT_BUF_CTL1 that didn't get converted
in intel_tc.c and one in intel_ddi.c.


Matt

> +
> +static inline i915_reg_t xelpdp_port_m2p_msgbus_ctl_reg(struct drm_i915_private *i915,
> +							enum port port, int lane)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_M2P_MSGBUS_CTL(xe2lpd_port_idx(port), lane) :
> +		XELPDP_PORT_M2P_MSGBUS_CTL(port, lane);
> +}
> +
> +static inline i915_reg_t xelpdp_port_p2m_msgbus_status_reg(struct drm_i915_private *i915,
> +							   enum port port, int lane)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_P2M_MSGBUS_STATUS(xe2lpd_port_idx(port), lane) :
> +		XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane);
> +}
> +
>  #endif /* __INTEL_CX0_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3147ed174d83..3587ddc6d8ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -176,7 +176,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
>  	int ret;
>  
>  	/* FIXME: find out why Bspec's 100us timeout is too short */
> -	ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
> +	ret = wait_for_us((intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port)) &
>  			   XELPDP_PORT_BUF_PHY_IDLE), 10000);
>  	if (ret)
>  		drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
> @@ -224,7 +224,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
>  	}
>  
>  	if (DISPLAY_VER(dev_priv) >= 14)
> -		ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
> +		ret = _wait_for(!(intel_de_read(dev_priv,
> +						xelpdp_port_buf_ctl1_reg(dev_priv, port)) &
> +				  XELPDP_PORT_BUF_PHY_IDLE),
>  				timeout_us, 10, 10);
>  	else
>  		ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
> @@ -2365,7 +2367,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
> -		reg = XELPDP_PORT_BUF_CTL1(port);
> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>  		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>  	}
> @@ -2385,7 +2387,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>  	enum port port = encoder->port;
>  	u32 val;
>  
> -	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
> +	val = intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port));
>  	val &= ~XELPDP_PORT_WIDTH_MASK;
>  	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
>  
> @@ -2398,7 +2400,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>  	if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
>  		val |= XELPDP_PORT_REVERSAL;
>  
> -	intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
> +	intel_de_write(i915, xelpdp_port_buf_ctl1_reg(i915, port), val);
>  }
>  
>  static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
> @@ -2409,7 +2411,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>  
>  	val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
>  	      XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
>  		     XELPDP_PORT_BUF_IO_SELECT_TBT, val);
>  }
>  
> @@ -2829,7 +2831,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
> -		reg = XELPDP_PORT_BUF_CTL1(port);
> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>  		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>  	}
> @@ -2967,7 +2969,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>  
>  	/* De-select Thunderbolt */
>  	if (DISPLAY_VER(dev_priv) >= 14)
> -		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
> +		intel_de_rmw(dev_priv, xelpdp_port_buf_ctl1_reg(dev_priv, encoder->port),
>  			     XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
>  }
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:18AM -0700, Lucas De Marchi wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
> 
> Do not read DE_RRMR register after display version 20. This register
> contains display state information during GFX state dumps.
> 
> Bspec: 69456
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 4749f99e6320..fe2fa6f966f2 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1755,7 +1755,7 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
>  	struct intel_uncore *uncore = gt->_gt->uncore;
>  	struct drm_i915_private *i915 = uncore->i915;
>  
> -	if (GRAPHICS_VER(i915) >= 6)
> +	if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)

We have IS_DISPLAY_VER() that's slightly simpler for ranges like this.

Aside from that,

        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


Matt

>  		gt->derrmr = intel_uncore_read(uncore, DERRMR);
>  
>  	if (GRAPHICS_VER(i915) >= 8)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:18AM -0700, Lucas De Marchi wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
> 
> Do not read DE_RRMR register after display version 20. This register
> contains display state information during GFX state dumps.
> 
> Bspec: 69456
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 4749f99e6320..fe2fa6f966f2 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1755,7 +1755,7 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
>  	struct intel_uncore *uncore = gt->_gt->uncore;
>  	struct drm_i915_private *i915 = uncore->i915;
>  
> -	if (GRAPHICS_VER(i915) >= 6)
> +	if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)

We have IS_DISPLAY_VER() that's slightly simpler for ranges like this.

Aside from that,

        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


Matt

>  		gt->derrmr = intel_uncore_read(uncore, DERRMR);
>  
>  	if (GRAPHICS_VER(i915) >= 8)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 21/42] drm/i915/xe2lpd: Add display power well

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:19AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> 
> Add Display Power Well for LNL platform, mostly it is same as MTL
> platform so reused the code
> 
> Changes are:
> 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
>    logic xelpdp_aux_power_well_ops functions.
> 2. PGPICA1 contains type-C capable port slices which requires the well
>    to power powered up, so added new power well definition for PGPICA1
> 
> BSpec: 68886
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../i915/display/intel_display_power_map.c    | 36 ++++++++++-
>  .../i915/display/intel_display_power_well.c   | 63 ++++++++++++++++++-
>  .../i915/display/intel_display_power_well.h   |  1 +
>  .../gpu/drm/i915/display/intel_dp_aux_regs.h  | 27 ++++++++
>  4 files changed, 123 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 5ad04cd42c15..cef3b313c9f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1545,6 +1545,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
>  	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
>  };
>  
> +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
> +		     POWER_DOMAIN_PORT_DDI_LANES_TC1,
> +		     POWER_DOMAIN_PORT_DDI_LANES_TC2,
> +		     POWER_DOMAIN_PORT_DDI_LANES_TC3,
> +		     POWER_DOMAIN_PORT_DDI_LANES_TC4,
> +		     POWER_DOMAIN_AUX_USBC1,
> +		     POWER_DOMAIN_AUX_USBC2,
> +		     POWER_DOMAIN_AUX_USBC3,
> +		     POWER_DOMAIN_AUX_USBC4,
> +		     POWER_DOMAIN_AUX_TBT1,
> +		     POWER_DOMAIN_AUX_TBT2,
> +		     POWER_DOMAIN_AUX_TBT3,
> +		     POWER_DOMAIN_AUX_TBT4,
> +		     POWER_DOMAIN_INIT);
> +
> +static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
> +	{
> +		.instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
> +							&xe2lpd_pwdoms_pica_tc,
> +							.id = DISP_PW_ID_NONE),
> +					       ),
> +		.ops = &xe2lpd_pica_power_well_ops,
> +	},
> +};
> +
> +static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
> +	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> +	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> +	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> +	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
> +};

Are we missing a "dc_off" power well here?  This patch might have
originally been written before we separated dc_off out from main.

Assuming the DC state requirements are the same for Xe2_LPD as they were
for Xe_LPD and Xe_LPD+ (I haven't checked), then adding

        I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off),

immediately before xelpdp_power_wells_main should be sufficient.

> +
>  static void init_power_well_domains(const struct i915_power_well_instance *inst,
>  				    struct i915_power_well *power_well)
>  {
> @@ -1652,7 +1684,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
>  		return 0;
>  	}
>  
> -	if (DISPLAY_VER(i915) >= 14)
> +	if (DISPLAY_VER(i915) >= 20)
> +		return set_power_wells(power_domains, xe2lpd_power_wells);
> +	else if (DISPLAY_VER(i915) >= 14)
>  		return set_power_wells(power_domains, xelpdp_power_wells);
>  	else if (IS_DG2(i915))
>  		return set_power_wells(power_domains, xehpd_power_wells);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 916009894d89..e1fb0bd7b3bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1795,7 +1795,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  {
>  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
>  
> -	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> +	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> +				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> +				XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> +	intel_de_rmw(dev_priv, aux_ch_ctl,
>  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
>  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
>  
> @@ -1813,7 +1817,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
>  {
>  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
>  
> -	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> +	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> +				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> +				XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> +	intel_de_rmw(dev_priv, aux_ch_ctl,
>  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
>  		     0);
>  	usleep_range(10, 30);
> @@ -1823,11 +1831,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
>  					  struct i915_power_well *power_well)
>  {
>  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> +	i915_reg_t aux_ch_ctl;
>  
> -	return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
> +	aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> +		     XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> +		     XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> +	return intel_de_read(dev_priv, aux_ch_ctl) &
>  		XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
>  }
>  
> +static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
> +					  struct i915_power_well *power_well)
> +{
> +	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> +		     XE2LPD_PICA_CTL_POWER_REQUEST,
> +		     XE2LPD_PICA_CTL_POWER_REQUEST);
> +
> +	if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
> +				  XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> +		drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
> +
> +		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
> +	}
> +}
> +
> +static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
> +					   struct i915_power_well *power_well)
> +{
> +	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> +		     XE2LPD_PICA_CTL_POWER_REQUEST,
> +		     0);
> +
> +	if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
> +				    XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> +		drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
> +
> +		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
> +	}
> +}
> +
> +static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
> +					   struct i915_power_well *power_well)
> +{
> +	return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
> +		XE2LPD_PICA_CTL_POWER_STATUS;
> +}
> +
>  const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>  	.sync_hw = i9xx_power_well_sync_hw_noop,
>  	.enable = i9xx_always_on_power_well_noop,
> @@ -1947,3 +1997,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
>  	.disable = xelpdp_aux_power_well_disable,
>  	.is_enabled = xelpdp_aux_power_well_enabled,
>  };
> +
> +const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
> +	.sync_hw = i9xx_power_well_sync_hw_noop,
> +	.enable = xe2lpd_pica_power_well_enable,
> +	.disable = xe2lpd_pica_power_well_disable,
> +	.is_enabled = xe2lpd_pica_power_well_enabled,
> +};
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index a8736588314d..9357a9a73c06 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
>  extern const struct i915_power_well_ops icl_ddi_power_well_ops;
>  extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
>  extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
> +extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
>  
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> index 5185345277c7..d855f3730381 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> @@ -83,4 +83,31 @@
>  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK	REG_GENMASK(4, 0) /* skl+ */
>  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)	REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
>  
> +#define _XE2LPD_DPA_AUX_CH_CTL		0x16FA10
> +#define _XE2LPD_DPB_AUX_CH_CTL		0x16FC10
> +#define _XE2LPD_DPA_AUX_CH_DATA1	0x16FA14
> +#define _XE2LPD_DPB_AUX_CH_DATA1	0x16FC14

We're generally trying to standardize on lowercase hex for register
offsets these days.

> +#define XE2LPD_DP_AUX_CH_CTL(aux_ch)		_MMIO(_PICK(aux_ch, \
> +						       _XE2LPD_DPA_AUX_CH_CTL, \
> +						       _XE2LPD_DPB_AUX_CH_CTL, \
> +						       0, /* port/aux_ch C is non-existent */ \
> +						       _XELPDP_USBC1_AUX_CH_CTL, \
> +						       _XELPDP_USBC2_AUX_CH_CTL, \
> +						       _XELPDP_USBC3_AUX_CH_CTL, \
> +						       _XELPDP_USBC4_AUX_CH_CTL))
> +#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PICK(aux_ch, \
> +						       _XE2LPD_DPA_AUX_CH_DATA1, \
> +						       _XE2LPD_DPB_AUX_CH_DATA1, \
> +						       0, /* port/aux_ch C is non-existent */ \
> +						       _XELPDP_USBC1_AUX_CH_DATA1, \
> +						       _XELPDP_USBC2_AUX_CH_DATA1, \
> +						       _XELPDP_USBC3_AUX_CH_DATA1, \
> +						       _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)

It looks like these PICA registers are following the same general layout
change as the ones we modified a couple patches ago ("drm/i915/xe2lpd:
Move registers to PICA").  We should probably handle these the same way
for consistency (or maybe even squash the register movement here into
that previous patch?).

> +
> +/* PICA Power Well Control register for Xe2 platforms*/
> +#define XE2LPD_PICA_PW_CTL	_MMIO(0x16FE04)
> +

Unwanted blank line?


Matt

> +#define   XE2LPD_PICA_CTL_POWER_REQUEST BIT(31)
> +#define   XE2LPD_PICA_CTL_POWER_STATUS  BIT(30)
> +
>  #endif /* __INTEL_DP_AUX_REGS_H__ */
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 21/42] drm/i915/xe2lpd: Add display power well

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:19AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> 
> Add Display Power Well for LNL platform, mostly it is same as MTL
> platform so reused the code
> 
> Changes are:
> 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
>    logic xelpdp_aux_power_well_ops functions.
> 2. PGPICA1 contains type-C capable port slices which requires the well
>    to power powered up, so added new power well definition for PGPICA1
> 
> BSpec: 68886
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../i915/display/intel_display_power_map.c    | 36 ++++++++++-
>  .../i915/display/intel_display_power_well.c   | 63 ++++++++++++++++++-
>  .../i915/display/intel_display_power_well.h   |  1 +
>  .../gpu/drm/i915/display/intel_dp_aux_regs.h  | 27 ++++++++
>  4 files changed, 123 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 5ad04cd42c15..cef3b313c9f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1545,6 +1545,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
>  	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
>  };
>  
> +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
> +		     POWER_DOMAIN_PORT_DDI_LANES_TC1,
> +		     POWER_DOMAIN_PORT_DDI_LANES_TC2,
> +		     POWER_DOMAIN_PORT_DDI_LANES_TC3,
> +		     POWER_DOMAIN_PORT_DDI_LANES_TC4,
> +		     POWER_DOMAIN_AUX_USBC1,
> +		     POWER_DOMAIN_AUX_USBC2,
> +		     POWER_DOMAIN_AUX_USBC3,
> +		     POWER_DOMAIN_AUX_USBC4,
> +		     POWER_DOMAIN_AUX_TBT1,
> +		     POWER_DOMAIN_AUX_TBT2,
> +		     POWER_DOMAIN_AUX_TBT3,
> +		     POWER_DOMAIN_AUX_TBT4,
> +		     POWER_DOMAIN_INIT);
> +
> +static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
> +	{
> +		.instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
> +							&xe2lpd_pwdoms_pica_tc,
> +							.id = DISP_PW_ID_NONE),
> +					       ),
> +		.ops = &xe2lpd_pica_power_well_ops,
> +	},
> +};
> +
> +static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
> +	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> +	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> +	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> +	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
> +};

Are we missing a "dc_off" power well here?  This patch might have
originally been written before we separated dc_off out from main.

Assuming the DC state requirements are the same for Xe2_LPD as they were
for Xe_LPD and Xe_LPD+ (I haven't checked), then adding

        I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off),

immediately before xelpdp_power_wells_main should be sufficient.

> +
>  static void init_power_well_domains(const struct i915_power_well_instance *inst,
>  				    struct i915_power_well *power_well)
>  {
> @@ -1652,7 +1684,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
>  		return 0;
>  	}
>  
> -	if (DISPLAY_VER(i915) >= 14)
> +	if (DISPLAY_VER(i915) >= 20)
> +		return set_power_wells(power_domains, xe2lpd_power_wells);
> +	else if (DISPLAY_VER(i915) >= 14)
>  		return set_power_wells(power_domains, xelpdp_power_wells);
>  	else if (IS_DG2(i915))
>  		return set_power_wells(power_domains, xehpd_power_wells);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 916009894d89..e1fb0bd7b3bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1795,7 +1795,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  {
>  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
>  
> -	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> +	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> +				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> +				XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> +	intel_de_rmw(dev_priv, aux_ch_ctl,
>  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
>  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
>  
> @@ -1813,7 +1817,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
>  {
>  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
>  
> -	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> +	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> +				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> +				XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> +	intel_de_rmw(dev_priv, aux_ch_ctl,
>  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
>  		     0);
>  	usleep_range(10, 30);
> @@ -1823,11 +1831,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
>  					  struct i915_power_well *power_well)
>  {
>  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> +	i915_reg_t aux_ch_ctl;
>  
> -	return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
> +	aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> +		     XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> +		     XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> +	return intel_de_read(dev_priv, aux_ch_ctl) &
>  		XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
>  }
>  
> +static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
> +					  struct i915_power_well *power_well)
> +{
> +	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> +		     XE2LPD_PICA_CTL_POWER_REQUEST,
> +		     XE2LPD_PICA_CTL_POWER_REQUEST);
> +
> +	if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
> +				  XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> +		drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
> +
> +		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
> +	}
> +}
> +
> +static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
> +					   struct i915_power_well *power_well)
> +{
> +	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> +		     XE2LPD_PICA_CTL_POWER_REQUEST,
> +		     0);
> +
> +	if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
> +				    XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> +		drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
> +
> +		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
> +	}
> +}
> +
> +static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
> +					   struct i915_power_well *power_well)
> +{
> +	return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
> +		XE2LPD_PICA_CTL_POWER_STATUS;
> +}
> +
>  const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>  	.sync_hw = i9xx_power_well_sync_hw_noop,
>  	.enable = i9xx_always_on_power_well_noop,
> @@ -1947,3 +1997,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
>  	.disable = xelpdp_aux_power_well_disable,
>  	.is_enabled = xelpdp_aux_power_well_enabled,
>  };
> +
> +const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
> +	.sync_hw = i9xx_power_well_sync_hw_noop,
> +	.enable = xe2lpd_pica_power_well_enable,
> +	.disable = xe2lpd_pica_power_well_disable,
> +	.is_enabled = xe2lpd_pica_power_well_enabled,
> +};
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index a8736588314d..9357a9a73c06 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
>  extern const struct i915_power_well_ops icl_ddi_power_well_ops;
>  extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
>  extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
> +extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
>  
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> index 5185345277c7..d855f3730381 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> @@ -83,4 +83,31 @@
>  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK	REG_GENMASK(4, 0) /* skl+ */
>  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)	REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
>  
> +#define _XE2LPD_DPA_AUX_CH_CTL		0x16FA10
> +#define _XE2LPD_DPB_AUX_CH_CTL		0x16FC10
> +#define _XE2LPD_DPA_AUX_CH_DATA1	0x16FA14
> +#define _XE2LPD_DPB_AUX_CH_DATA1	0x16FC14

We're generally trying to standardize on lowercase hex for register
offsets these days.

> +#define XE2LPD_DP_AUX_CH_CTL(aux_ch)		_MMIO(_PICK(aux_ch, \
> +						       _XE2LPD_DPA_AUX_CH_CTL, \
> +						       _XE2LPD_DPB_AUX_CH_CTL, \
> +						       0, /* port/aux_ch C is non-existent */ \
> +						       _XELPDP_USBC1_AUX_CH_CTL, \
> +						       _XELPDP_USBC2_AUX_CH_CTL, \
> +						       _XELPDP_USBC3_AUX_CH_CTL, \
> +						       _XELPDP_USBC4_AUX_CH_CTL))
> +#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PICK(aux_ch, \
> +						       _XE2LPD_DPA_AUX_CH_DATA1, \
> +						       _XE2LPD_DPB_AUX_CH_DATA1, \
> +						       0, /* port/aux_ch C is non-existent */ \
> +						       _XELPDP_USBC1_AUX_CH_DATA1, \
> +						       _XELPDP_USBC2_AUX_CH_DATA1, \
> +						       _XELPDP_USBC3_AUX_CH_DATA1, \
> +						       _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)

It looks like these PICA registers are following the same general layout
change as the ones we modified a couple patches ago ("drm/i915/xe2lpd:
Move registers to PICA").  We should probably handle these the same way
for consistency (or maybe even squash the register movement here into
that previous patch?).

> +
> +/* PICA Power Well Control register for Xe2 platforms*/
> +#define XE2LPD_PICA_PW_CTL	_MMIO(0x16FE04)
> +

Unwanted blank line?


Matt

> +#define   XE2LPD_PICA_CTL_POWER_REQUEST BIT(31)
> +#define   XE2LPD_PICA_CTL_POWER_STATUS  BIT(30)
> +
>  #endif /* __INTEL_DP_AUX_REGS_H__ */
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 21/42] drm/i915/xe2lpd: Add display power well

[Matt Roper]

On Wed, Aug 23, 2023 at 12:44:56PM -0700, Matt Roper wrote:
> On Wed, Aug 23, 2023 at 10:07:19AM -0700, Lucas De Marchi wrote:
> > From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> > 
> > Add Display Power Well for LNL platform, mostly it is same as MTL
> > platform so reused the code
> > 
> > Changes are:
> > 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
> >    logic xelpdp_aux_power_well_ops functions.
> > 2. PGPICA1 contains type-C capable port slices which requires the well
> >    to power powered up, so added new power well definition for PGPICA1
> > 
> > BSpec: 68886
> > Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  .../i915/display/intel_display_power_map.c    | 36 ++++++++++-
> >  .../i915/display/intel_display_power_well.c   | 63 ++++++++++++++++++-
> >  .../i915/display/intel_display_power_well.h   |  1 +
> >  .../gpu/drm/i915/display/intel_dp_aux_regs.h  | 27 ++++++++
> >  4 files changed, 123 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 5ad04cd42c15..cef3b313c9f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -1545,6 +1545,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
> >  	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> >  };
> >  
> > +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
> > +		     POWER_DOMAIN_PORT_DDI_LANES_TC1,
> > +		     POWER_DOMAIN_PORT_DDI_LANES_TC2,
> > +		     POWER_DOMAIN_PORT_DDI_LANES_TC3,
> > +		     POWER_DOMAIN_PORT_DDI_LANES_TC4,
> > +		     POWER_DOMAIN_AUX_USBC1,
> > +		     POWER_DOMAIN_AUX_USBC2,
> > +		     POWER_DOMAIN_AUX_USBC3,
> > +		     POWER_DOMAIN_AUX_USBC4,
> > +		     POWER_DOMAIN_AUX_TBT1,
> > +		     POWER_DOMAIN_AUX_TBT2,
> > +		     POWER_DOMAIN_AUX_TBT3,
> > +		     POWER_DOMAIN_AUX_TBT4,
> > +		     POWER_DOMAIN_INIT);
> > +
> > +static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
> > +	{
> > +		.instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
> > +							&xe2lpd_pwdoms_pica_tc,
> > +							.id = DISP_PW_ID_NONE),
> > +					       ),
> > +		.ops = &xe2lpd_pica_power_well_ops,
> > +	},
> > +};
> > +
> > +static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
> > +	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> > +	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> > +	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> > +	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
> > +};
> 
> Are we missing a "dc_off" power well here?  This patch might have
> originally been written before we separated dc_off out from main.
> 
> Assuming the DC state requirements are the same for Xe2_LPD as they were
> for Xe_LPD and Xe_LPD+ (I haven't checked), then adding
> 
>         I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off),
> 
> immediately before xelpdp_power_wells_main should be sufficient.

Okay, this is actually taken care of by the next patch in the series.
Disregard this comment.


Matt

> 
> > +
> >  static void init_power_well_domains(const struct i915_power_well_instance *inst,
> >  				    struct i915_power_well *power_well)
> >  {
> > @@ -1652,7 +1684,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
> >  		return 0;
> >  	}
> >  
> > -	if (DISPLAY_VER(i915) >= 14)
> > +	if (DISPLAY_VER(i915) >= 20)
> > +		return set_power_wells(power_domains, xe2lpd_power_wells);
> > +	else if (DISPLAY_VER(i915) >= 14)
> >  		return set_power_wells(power_domains, xelpdp_power_wells);
> >  	else if (IS_DG2(i915))
> >  		return set_power_wells(power_domains, xehpd_power_wells);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 916009894d89..e1fb0bd7b3bf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -1795,7 +1795,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
> >  {
> >  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> >  
> > -	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> > +	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> > +				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> > +				XELPDP_DP_AUX_CH_CTL(aux_ch);
> > +
> > +	intel_de_rmw(dev_priv, aux_ch_ctl,
> >  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> >  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
> >  
> > @@ -1813,7 +1817,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
> >  {
> >  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> >  
> > -	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> > +	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> > +				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> > +				XELPDP_DP_AUX_CH_CTL(aux_ch);
> > +
> > +	intel_de_rmw(dev_priv, aux_ch_ctl,
> >  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> >  		     0);
> >  	usleep_range(10, 30);
> > @@ -1823,11 +1831,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
> >  					  struct i915_power_well *power_well)
> >  {
> >  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> > +	i915_reg_t aux_ch_ctl;
> >  
> > -	return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
> > +	aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> > +		     XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> > +		     XELPDP_DP_AUX_CH_CTL(aux_ch);
> > +
> > +	return intel_de_read(dev_priv, aux_ch_ctl) &
> >  		XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
> >  }
> >  
> > +static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
> > +					  struct i915_power_well *power_well)
> > +{
> > +	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> > +		     XE2LPD_PICA_CTL_POWER_REQUEST,
> > +		     XE2LPD_PICA_CTL_POWER_REQUEST);
> > +
> > +	if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
> > +				  XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> > +		drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
> > +
> > +		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
> > +	}
> > +}
> > +
> > +static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
> > +					   struct i915_power_well *power_well)
> > +{
> > +	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> > +		     XE2LPD_PICA_CTL_POWER_REQUEST,
> > +		     0);
> > +
> > +	if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
> > +				    XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> > +		drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
> > +
> > +		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
> > +	}
> > +}
> > +
> > +static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
> > +					   struct i915_power_well *power_well)
> > +{
> > +	return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
> > +		XE2LPD_PICA_CTL_POWER_STATUS;
> > +}
> > +
> >  const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> >  	.sync_hw = i9xx_power_well_sync_hw_noop,
> >  	.enable = i9xx_always_on_power_well_noop,
> > @@ -1947,3 +1997,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
> >  	.disable = xelpdp_aux_power_well_disable,
> >  	.is_enabled = xelpdp_aux_power_well_enabled,
> >  };
> > +
> > +const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
> > +	.sync_hw = i9xx_power_well_sync_hw_noop,
> > +	.enable = xe2lpd_pica_power_well_enable,
> > +	.disable = xe2lpd_pica_power_well_disable,
> > +	.is_enabled = xe2lpd_pica_power_well_enabled,
> > +};
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> > index a8736588314d..9357a9a73c06 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> > @@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
> >  extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> >  extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
> >  extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
> > +extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
> >  
> >  #endif
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> > index 5185345277c7..d855f3730381 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> > @@ -83,4 +83,31 @@
> >  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK	REG_GENMASK(4, 0) /* skl+ */
> >  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)	REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
> >  
> > +#define _XE2LPD_DPA_AUX_CH_CTL		0x16FA10
> > +#define _XE2LPD_DPB_AUX_CH_CTL		0x16FC10
> > +#define _XE2LPD_DPA_AUX_CH_DATA1	0x16FA14
> > +#define _XE2LPD_DPB_AUX_CH_DATA1	0x16FC14
> 
> We're generally trying to standardize on lowercase hex for register
> offsets these days.
> 
> > +#define XE2LPD_DP_AUX_CH_CTL(aux_ch)		_MMIO(_PICK(aux_ch, \
> > +						       _XE2LPD_DPA_AUX_CH_CTL, \
> > +						       _XE2LPD_DPB_AUX_CH_CTL, \
> > +						       0, /* port/aux_ch C is non-existent */ \
> > +						       _XELPDP_USBC1_AUX_CH_CTL, \
> > +						       _XELPDP_USBC2_AUX_CH_CTL, \
> > +						       _XELPDP_USBC3_AUX_CH_CTL, \
> > +						       _XELPDP_USBC4_AUX_CH_CTL))
> > +#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PICK(aux_ch, \
> > +						       _XE2LPD_DPA_AUX_CH_DATA1, \
> > +						       _XE2LPD_DPB_AUX_CH_DATA1, \
> > +						       0, /* port/aux_ch C is non-existent */ \
> > +						       _XELPDP_USBC1_AUX_CH_DATA1, \
> > +						       _XELPDP_USBC2_AUX_CH_DATA1, \
> > +						       _XELPDP_USBC3_AUX_CH_DATA1, \
> > +						       _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
> 
> It looks like these PICA registers are following the same general layout
> change as the ones we modified a couple patches ago ("drm/i915/xe2lpd:
> Move registers to PICA").  We should probably handle these the same way
> for consistency (or maybe even squash the register movement here into
> that previous patch?).
> 
> > +
> > +/* PICA Power Well Control register for Xe2 platforms*/
> > +#define XE2LPD_PICA_PW_CTL	_MMIO(0x16FE04)
> > +
> 
> Unwanted blank line?
> 
> 
> Matt
> 
> > +#define   XE2LPD_PICA_CTL_POWER_REQUEST BIT(31)
> > +#define   XE2LPD_PICA_CTL_POWER_STATUS  BIT(30)
> > +
> >  #endif /* __INTEL_DP_AUX_REGS_H__ */
> > -- 
> > 2.40.1
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 21/42] drm/i915/xe2lpd: Add display power well

[Matt Roper]

On Wed, Aug 23, 2023 at 12:44:56PM -0700, Matt Roper wrote:
> On Wed, Aug 23, 2023 at 10:07:19AM -0700, Lucas De Marchi wrote:
> > From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> > 
> > Add Display Power Well for LNL platform, mostly it is same as MTL
> > platform so reused the code
> > 
> > Changes are:
> > 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
> >    logic xelpdp_aux_power_well_ops functions.
> > 2. PGPICA1 contains type-C capable port slices which requires the well
> >    to power powered up, so added new power well definition for PGPICA1
> > 
> > BSpec: 68886
> > Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  .../i915/display/intel_display_power_map.c    | 36 ++++++++++-
> >  .../i915/display/intel_display_power_well.c   | 63 ++++++++++++++++++-
> >  .../i915/display/intel_display_power_well.h   |  1 +
> >  .../gpu/drm/i915/display/intel_dp_aux_regs.h  | 27 ++++++++
> >  4 files changed, 123 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 5ad04cd42c15..cef3b313c9f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -1545,6 +1545,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
> >  	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> >  };
> >  
> > +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
> > +		     POWER_DOMAIN_PORT_DDI_LANES_TC1,
> > +		     POWER_DOMAIN_PORT_DDI_LANES_TC2,
> > +		     POWER_DOMAIN_PORT_DDI_LANES_TC3,
> > +		     POWER_DOMAIN_PORT_DDI_LANES_TC4,
> > +		     POWER_DOMAIN_AUX_USBC1,
> > +		     POWER_DOMAIN_AUX_USBC2,
> > +		     POWER_DOMAIN_AUX_USBC3,
> > +		     POWER_DOMAIN_AUX_USBC4,
> > +		     POWER_DOMAIN_AUX_TBT1,
> > +		     POWER_DOMAIN_AUX_TBT2,
> > +		     POWER_DOMAIN_AUX_TBT3,
> > +		     POWER_DOMAIN_AUX_TBT4,
> > +		     POWER_DOMAIN_INIT);
> > +
> > +static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
> > +	{
> > +		.instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
> > +							&xe2lpd_pwdoms_pica_tc,
> > +							.id = DISP_PW_ID_NONE),
> > +					       ),
> > +		.ops = &xe2lpd_pica_power_well_ops,
> > +	},
> > +};
> > +
> > +static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
> > +	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> > +	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> > +	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> > +	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
> > +};
> 
> Are we missing a "dc_off" power well here?  This patch might have
> originally been written before we separated dc_off out from main.
> 
> Assuming the DC state requirements are the same for Xe2_LPD as they were
> for Xe_LPD and Xe_LPD+ (I haven't checked), then adding
> 
>         I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off),
> 
> immediately before xelpdp_power_wells_main should be sufficient.

Okay, this is actually taken care of by the next patch in the series.
Disregard this comment.


Matt

> 
> > +
> >  static void init_power_well_domains(const struct i915_power_well_instance *inst,
> >  				    struct i915_power_well *power_well)
> >  {
> > @@ -1652,7 +1684,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
> >  		return 0;
> >  	}
> >  
> > -	if (DISPLAY_VER(i915) >= 14)
> > +	if (DISPLAY_VER(i915) >= 20)
> > +		return set_power_wells(power_domains, xe2lpd_power_wells);
> > +	else if (DISPLAY_VER(i915) >= 14)
> >  		return set_power_wells(power_domains, xelpdp_power_wells);
> >  	else if (IS_DG2(i915))
> >  		return set_power_wells(power_domains, xehpd_power_wells);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 916009894d89..e1fb0bd7b3bf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -1795,7 +1795,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
> >  {
> >  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> >  
> > -	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> > +	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> > +				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> > +				XELPDP_DP_AUX_CH_CTL(aux_ch);
> > +
> > +	intel_de_rmw(dev_priv, aux_ch_ctl,
> >  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> >  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
> >  
> > @@ -1813,7 +1817,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
> >  {
> >  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> >  
> > -	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> > +	i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> > +				XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> > +				XELPDP_DP_AUX_CH_CTL(aux_ch);
> > +
> > +	intel_de_rmw(dev_priv, aux_ch_ctl,
> >  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> >  		     0);
> >  	usleep_range(10, 30);
> > @@ -1823,11 +1831,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
> >  					  struct i915_power_well *power_well)
> >  {
> >  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> > +	i915_reg_t aux_ch_ctl;
> >  
> > -	return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
> > +	aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> > +		     XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> > +		     XELPDP_DP_AUX_CH_CTL(aux_ch);
> > +
> > +	return intel_de_read(dev_priv, aux_ch_ctl) &
> >  		XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
> >  }
> >  
> > +static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
> > +					  struct i915_power_well *power_well)
> > +{
> > +	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> > +		     XE2LPD_PICA_CTL_POWER_REQUEST,
> > +		     XE2LPD_PICA_CTL_POWER_REQUEST);
> > +
> > +	if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
> > +				  XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> > +		drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
> > +
> > +		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
> > +	}
> > +}
> > +
> > +static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
> > +					   struct i915_power_well *power_well)
> > +{
> > +	intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> > +		     XE2LPD_PICA_CTL_POWER_REQUEST,
> > +		     0);
> > +
> > +	if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
> > +				    XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> > +		drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
> > +
> > +		drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
> > +	}
> > +}
> > +
> > +static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
> > +					   struct i915_power_well *power_well)
> > +{
> > +	return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
> > +		XE2LPD_PICA_CTL_POWER_STATUS;
> > +}
> > +
> >  const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> >  	.sync_hw = i9xx_power_well_sync_hw_noop,
> >  	.enable = i9xx_always_on_power_well_noop,
> > @@ -1947,3 +1997,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
> >  	.disable = xelpdp_aux_power_well_disable,
> >  	.is_enabled = xelpdp_aux_power_well_enabled,
> >  };
> > +
> > +const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
> > +	.sync_hw = i9xx_power_well_sync_hw_noop,
> > +	.enable = xe2lpd_pica_power_well_enable,
> > +	.disable = xe2lpd_pica_power_well_disable,
> > +	.is_enabled = xe2lpd_pica_power_well_enabled,
> > +};
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> > index a8736588314d..9357a9a73c06 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> > @@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
> >  extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> >  extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
> >  extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
> > +extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
> >  
> >  #endif
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> > index 5185345277c7..d855f3730381 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> > @@ -83,4 +83,31 @@
> >  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK	REG_GENMASK(4, 0) /* skl+ */
> >  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)	REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
> >  
> > +#define _XE2LPD_DPA_AUX_CH_CTL		0x16FA10
> > +#define _XE2LPD_DPB_AUX_CH_CTL		0x16FC10
> > +#define _XE2LPD_DPA_AUX_CH_DATA1	0x16FA14
> > +#define _XE2LPD_DPB_AUX_CH_DATA1	0x16FC14
> 
> We're generally trying to standardize on lowercase hex for register
> offsets these days.
> 
> > +#define XE2LPD_DP_AUX_CH_CTL(aux_ch)		_MMIO(_PICK(aux_ch, \
> > +						       _XE2LPD_DPA_AUX_CH_CTL, \
> > +						       _XE2LPD_DPB_AUX_CH_CTL, \
> > +						       0, /* port/aux_ch C is non-existent */ \
> > +						       _XELPDP_USBC1_AUX_CH_CTL, \
> > +						       _XELPDP_USBC2_AUX_CH_CTL, \
> > +						       _XELPDP_USBC3_AUX_CH_CTL, \
> > +						       _XELPDP_USBC4_AUX_CH_CTL))
> > +#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PICK(aux_ch, \
> > +						       _XE2LPD_DPA_AUX_CH_DATA1, \
> > +						       _XE2LPD_DPB_AUX_CH_DATA1, \
> > +						       0, /* port/aux_ch C is non-existent */ \
> > +						       _XELPDP_USBC1_AUX_CH_DATA1, \
> > +						       _XELPDP_USBC2_AUX_CH_DATA1, \
> > +						       _XELPDP_USBC3_AUX_CH_DATA1, \
> > +						       _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
> 
> It looks like these PICA registers are following the same general layout
> change as the ones we modified a couple patches ago ("drm/i915/xe2lpd:
> Move registers to PICA").  We should probably handle these the same way
> for consistency (or maybe even squash the register movement here into
> that previous patch?).
> 
> > +
> > +/* PICA Power Well Control register for Xe2 platforms*/
> > +#define XE2LPD_PICA_PW_CTL	_MMIO(0x16FE04)
> > +
> 
> Unwanted blank line?
> 
> 
> Matt
> 
> > +#define   XE2LPD_PICA_CTL_POWER_REQUEST BIT(31)
> > +#define   XE2LPD_PICA_CTL_POWER_STATUS  BIT(30)
> > +
> >  #endif /* __INTEL_DP_AUX_REGS_H__ */
> > -- 
> > 2.40.1
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 23/42] drm/i915/xe2lpd: FBC is now supported on all pipes

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:21AM -0700, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> FBC is no longer limited by pipe.

It looks like we lost the part of this patch that adds this to the
xe2_lpd_display device info structure.


Matt

> 
> Bspec: 68881, 68904
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 4adb98afe6ff..6720ec8ee8a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -20,6 +20,8 @@ struct intel_plane_state;
>  enum intel_fbc_id {
>  	INTEL_FBC_A,
>  	INTEL_FBC_B,
> +	INTEL_FBC_C,
> +	INTEL_FBC_D,
>  
>  	I915_MAX_FBCS,
>  };
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 23/42] drm/i915/xe2lpd: FBC is now supported on all pipes

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:21AM -0700, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> FBC is no longer limited by pipe.

It looks like we lost the part of this patch that adds this to the
xe2_lpd_display device info structure.


Matt

> 
> Bspec: 68881, 68904
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 4adb98afe6ff..6720ec8ee8a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -20,6 +20,8 @@ struct intel_plane_state;
>  enum intel_fbc_id {
>  	INTEL_FBC_A,
>  	INTEL_FBC_B,
> +	INTEL_FBC_C,
> +	INTEL_FBC_D,
>  
>  	I915_MAX_FBCS,
>  };
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 24/42] drm/i915/display: Remove FBC capability from fused off pipes

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:22AM -0700, Lucas De Marchi wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
> 
> If a particular pipe is disabled by fuse also remove the FBC for that
> pipe.
> 
> Bspec: 69464
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index b853cd0c704a..c4ff5a08c269 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -962,16 +962,19 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
>  		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
>  			display_runtime->pipe_mask &= ~BIT(PIPE_B);
>  			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
> +			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
>  		}
>  		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
>  			display_runtime->pipe_mask &= ~BIT(PIPE_C);
>  			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> +			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
>  		}
>  
>  		if (DISPLAY_VER(i915) >= 12 &&
>  		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
>  			display_runtime->pipe_mask &= ~BIT(PIPE_D);
>  			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
> +			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
>  		}
>  
>  		if (!display_runtime->pipe_mask)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 24/42] drm/i915/display: Remove FBC capability from fused off pipes

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:22AM -0700, Lucas De Marchi wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
> 
> If a particular pipe is disabled by fuse also remove the FBC for that
> pipe.
> 
> Bspec: 69464
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index b853cd0c704a..c4ff5a08c269 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -962,16 +962,19 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
>  		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
>  			display_runtime->pipe_mask &= ~BIT(PIPE_B);
>  			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
> +			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
>  		}
>  		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
>  			display_runtime->pipe_mask &= ~BIT(PIPE_C);
>  			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> +			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
>  		}
>  
>  		if (DISPLAY_VER(i915) >= 12 &&
>  		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
>  			display_runtime->pipe_mask &= ~BIT(PIPE_D);
>  			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
> +			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
>  		}
>  
>  		if (!display_runtime->pipe_mask)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:23AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> The location of aux channels registers for Xe2 display changed w.r.t.
> the previous version.

This is another case of "PICA register ordering where 'A' comes after
'TC4.'"  We should probably consolidate on the same design used in
"drm/i915/xe2lpd: Move registers to PICA."


Matt

> 
> BSpec: 69010
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 ++++++++++++++++++++-
>  1 file changed, 42 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 3fcf609a1444..1ab6964ee1c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -714,6 +714,44 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
>  	}
>  }
>  
> +static i915_reg_t xe2lpd_aux_ctl_reg(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum aux_ch aux_ch = dig_port->aux_ch;
> +
> +	switch (aux_ch) {
> +	case AUX_CH_A:
> +	case AUX_CH_B:
> +	case AUX_CH_USBC1:
> +	case AUX_CH_USBC2:
> +	case AUX_CH_USBC3:
> +	case AUX_CH_USBC4:
> +		return XE2LPD_DP_AUX_CH_CTL(aux_ch);
> +	default:
> +		MISSING_CASE(aux_ch);
> +		return XE2LPD_DP_AUX_CH_CTL(AUX_CH_A);
> +	}
> +}
> +
> +static i915_reg_t xe2lpd_aux_data_reg(struct intel_dp *intel_dp, int index)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum aux_ch aux_ch = dig_port->aux_ch;
> +
> +	switch (aux_ch) {
> +	case AUX_CH_A:
> +	case AUX_CH_B:
> +	case AUX_CH_USBC1:
> +	case AUX_CH_USBC2:
> +	case AUX_CH_USBC3:
> +	case AUX_CH_USBC4:
> +		return XE2LPD_DP_AUX_CH_DATA(aux_ch, index);
> +	default:
> +		MISSING_CASE(aux_ch);
> +		return XE2LPD_DP_AUX_CH_DATA(AUX_CH_A, index);
> +	}
> +}
> +
>  void intel_dp_aux_fini(struct intel_dp *intel_dp)
>  {
>  	if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
> @@ -731,7 +769,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
>  	struct intel_encoder *encoder = &dig_port->base;
>  	enum aux_ch aux_ch = dig_port->aux_ch;
>  
> -	if (DISPLAY_VER(dev_priv) >= 14) {
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		intel_dp->aux_ch_ctl_reg = xe2lpd_aux_ctl_reg;
> +		intel_dp->aux_ch_data_reg = xe2lpd_aux_data_reg;
> +	} else if (DISPLAY_VER(dev_priv) >= 14) {
>  		intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
>  		intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
>  	} else if (DISPLAY_VER(dev_priv) >= 12) {
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:23AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> The location of aux channels registers for Xe2 display changed w.r.t.
> the previous version.

This is another case of "PICA register ordering where 'A' comes after
'TC4.'"  We should probably consolidate on the same design used in
"drm/i915/xe2lpd: Move registers to PICA."


Matt

> 
> BSpec: 69010
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 ++++++++++++++++++++-
>  1 file changed, 42 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 3fcf609a1444..1ab6964ee1c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -714,6 +714,44 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
>  	}
>  }
>  
> +static i915_reg_t xe2lpd_aux_ctl_reg(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum aux_ch aux_ch = dig_port->aux_ch;
> +
> +	switch (aux_ch) {
> +	case AUX_CH_A:
> +	case AUX_CH_B:
> +	case AUX_CH_USBC1:
> +	case AUX_CH_USBC2:
> +	case AUX_CH_USBC3:
> +	case AUX_CH_USBC4:
> +		return XE2LPD_DP_AUX_CH_CTL(aux_ch);
> +	default:
> +		MISSING_CASE(aux_ch);
> +		return XE2LPD_DP_AUX_CH_CTL(AUX_CH_A);
> +	}
> +}
> +
> +static i915_reg_t xe2lpd_aux_data_reg(struct intel_dp *intel_dp, int index)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum aux_ch aux_ch = dig_port->aux_ch;
> +
> +	switch (aux_ch) {
> +	case AUX_CH_A:
> +	case AUX_CH_B:
> +	case AUX_CH_USBC1:
> +	case AUX_CH_USBC2:
> +	case AUX_CH_USBC3:
> +	case AUX_CH_USBC4:
> +		return XE2LPD_DP_AUX_CH_DATA(aux_ch, index);
> +	default:
> +		MISSING_CASE(aux_ch);
> +		return XE2LPD_DP_AUX_CH_DATA(AUX_CH_A, index);
> +	}
> +}
> +
>  void intel_dp_aux_fini(struct intel_dp *intel_dp)
>  {
>  	if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
> @@ -731,7 +769,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
>  	struct intel_encoder *encoder = &dig_port->base;
>  	enum aux_ch aux_ch = dig_port->aux_ch;
>  
> -	if (DISPLAY_VER(dev_priv) >= 14) {
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		intel_dp->aux_ch_ctl_reg = xe2lpd_aux_ctl_reg;
> +		intel_dp->aux_ch_data_reg = xe2lpd_aux_data_reg;
> +	} else if (DISPLAY_VER(dev_priv) >= 14) {
>  		intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
>  		intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
>  	} else if (DISPLAY_VER(dev_priv) >= 12) {
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 26/42] drm/i915/xe2lpd: Handle port AUX interrupts

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:24AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> Differently from previous version, Xe2_LPD groups all port AUX interrupt
> bits into PICA interrupt registers.
> 
> BSpec: 68958, 69697
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
>  drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h                  | 3 +++
>  3 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 62ce55475554..bff4a76310c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
>  {
>  	u32 mask;
>  
> -	if (DISPLAY_VER(dev_priv) >= 14)
> +	if (DISPLAY_VER(dev_priv) >= 20)
> +		return 0;
> +	else if (DISPLAY_VER(dev_priv) >= 14)
>  		return TGL_DE_PORT_AUX_DDIA |
>  			TGL_DE_PORT_AUX_DDIB;
>  	else if (DISPLAY_VER(dev_priv) >= 13)
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index f95fa793fabb..f76b9deb64b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -514,6 +514,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
>  	u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
>  	u32 pin_mask = 0, long_mask = 0;
>  
> +	if (DISPLAY_VER(i915) >= 20)
> +		trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
> +
>  	for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
>  		u32 val;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84c5a76065a0..e31a985b02d5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4520,6 +4520,9 @@
>  #define  XELPDP_AUX_TC(hpd_pin)			REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
>  #define  XELPDP_AUX_TC_MASK			REG_GENMASK(11, 8)
>  
> +#define  XE2LPD_AUX_DDI(hpd_pin)		REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
> +#define  XE2LPD_AUX_DDI_MASK			REG_GENMASK(7, 6)
> +

It seems like we have extra, atypical whitespace around the fields of
this register.  I'd drop the blank line here, as well as the one above
the new definitions so that things are a bit more compact.  Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  #define  XELPDP_TBT_HOTPLUG(hpd_pin)		REG_BIT(_HPD_PIN_TC(hpd_pin))
>  #define  XELPDP_TBT_HOTPLUG_MASK		REG_GENMASK(3, 0)
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 26/42] drm/i915/xe2lpd: Handle port AUX interrupts

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:24AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> Differently from previous version, Xe2_LPD groups all port AUX interrupt
> bits into PICA interrupt registers.
> 
> BSpec: 68958, 69697
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
>  drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h                  | 3 +++
>  3 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 62ce55475554..bff4a76310c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
>  {
>  	u32 mask;
>  
> -	if (DISPLAY_VER(dev_priv) >= 14)
> +	if (DISPLAY_VER(dev_priv) >= 20)
> +		return 0;
> +	else if (DISPLAY_VER(dev_priv) >= 14)
>  		return TGL_DE_PORT_AUX_DDIA |
>  			TGL_DE_PORT_AUX_DDIB;
>  	else if (DISPLAY_VER(dev_priv) >= 13)
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index f95fa793fabb..f76b9deb64b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -514,6 +514,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
>  	u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
>  	u32 pin_mask = 0, long_mask = 0;
>  
> +	if (DISPLAY_VER(i915) >= 20)
> +		trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
> +
>  	for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
>  		u32 val;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84c5a76065a0..e31a985b02d5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4520,6 +4520,9 @@
>  #define  XELPDP_AUX_TC(hpd_pin)			REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
>  #define  XELPDP_AUX_TC_MASK			REG_GENMASK(11, 8)
>  
> +#define  XE2LPD_AUX_DDI(hpd_pin)		REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
> +#define  XE2LPD_AUX_DDI_MASK			REG_GENMASK(7, 6)
> +

It seems like we have extra, atypical whitespace around the fields of
this register.  I'd drop the blank line here, as well as the one above
the new definitions so that things are a bit more compact.  Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  #define  XELPDP_TBT_HOTPLUG(hpd_pin)		REG_BIT(_HPD_PIN_TC(hpd_pin))
>  #define  XELPDP_TBT_HOTPLUG_MASK		REG_GENMASK(3, 0)
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 01:01:44PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:23AM -0700, Lucas De Marchi wrote:
>> From: Gustavo Sousa <gustavo.sousa@intel.com>
>>
>> The location of aux channels registers for Xe2 display changed w.r.t.
>> the previous version.
>
>This is another case of "PICA register ordering where 'A' comes after
>'TC4.'"  We should probably consolidate on the same design used in
>"drm/i915/xe2lpd: Move registers to PICA."


yeah... I'm actually not very happy with that implementation and
thinking if we can have something different. Maybe a regs struct per
port or phy? Then during init we just set the right offset on each of
them rather than calculating the offset every time.  Maybe it'd still be
a challenge to support multiple platforms moving the register offsets
left and right, dunno. Also, maybe we should consider such a refactor
only after these patches settle so we can have everything applied
to refactor at once. Thoughts?


Lucas De Marchi

>
>
>Matt
>
>>
>> BSpec: 69010
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 ++++++++++++++++++++-
>>  1 file changed, 42 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> index 3fcf609a1444..1ab6964ee1c2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> @@ -714,6 +714,44 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
>>  	}
>>  }
>>
>> +static i915_reg_t xe2lpd_aux_ctl_reg(struct intel_dp *intel_dp)
>> +{
>> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> +	enum aux_ch aux_ch = dig_port->aux_ch;
>> +
>> +	switch (aux_ch) {
>> +	case AUX_CH_A:
>> +	case AUX_CH_B:
>> +	case AUX_CH_USBC1:
>> +	case AUX_CH_USBC2:
>> +	case AUX_CH_USBC3:
>> +	case AUX_CH_USBC4:
>> +		return XE2LPD_DP_AUX_CH_CTL(aux_ch);
>> +	default:
>> +		MISSING_CASE(aux_ch);
>> +		return XE2LPD_DP_AUX_CH_CTL(AUX_CH_A);
>> +	}
>> +}
>> +
>> +static i915_reg_t xe2lpd_aux_data_reg(struct intel_dp *intel_dp, int index)
>> +{
>> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> +	enum aux_ch aux_ch = dig_port->aux_ch;
>> +
>> +	switch (aux_ch) {
>> +	case AUX_CH_A:
>> +	case AUX_CH_B:
>> +	case AUX_CH_USBC1:
>> +	case AUX_CH_USBC2:
>> +	case AUX_CH_USBC3:
>> +	case AUX_CH_USBC4:
>> +		return XE2LPD_DP_AUX_CH_DATA(aux_ch, index);
>> +	default:
>> +		MISSING_CASE(aux_ch);
>> +		return XE2LPD_DP_AUX_CH_DATA(AUX_CH_A, index);
>> +	}
>> +}
>> +
>>  void intel_dp_aux_fini(struct intel_dp *intel_dp)
>>  {
>>  	if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
>> @@ -731,7 +769,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
>>  	struct intel_encoder *encoder = &dig_port->base;
>>  	enum aux_ch aux_ch = dig_port->aux_ch;
>>
>> -	if (DISPLAY_VER(dev_priv) >= 14) {
>> +	if (DISPLAY_VER(dev_priv) >= 20) {
>> +		intel_dp->aux_ch_ctl_reg = xe2lpd_aux_ctl_reg;
>> +		intel_dp->aux_ch_data_reg = xe2lpd_aux_data_reg;
>> +	} else if (DISPLAY_VER(dev_priv) >= 14) {
>>  		intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
>>  		intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
>>  	} else if (DISPLAY_VER(dev_priv) >= 12) {
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-xe] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 01:01:44PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:23AM -0700, Lucas De Marchi wrote:
>> From: Gustavo Sousa <gustavo.sousa@intel.com>
>>
>> The location of aux channels registers for Xe2 display changed w.r.t.
>> the previous version.
>
>This is another case of "PICA register ordering where 'A' comes after
>'TC4.'"  We should probably consolidate on the same design used in
>"drm/i915/xe2lpd: Move registers to PICA."


yeah... I'm actually not very happy with that implementation and
thinking if we can have something different. Maybe a regs struct per
port or phy? Then during init we just set the right offset on each of
them rather than calculating the offset every time.  Maybe it'd still be
a challenge to support multiple platforms moving the register offsets
left and right, dunno. Also, maybe we should consider such a refactor
only after these patches settle so we can have everything applied
to refactor at once. Thoughts?


Lucas De Marchi

>
>
>Matt
>
>>
>> BSpec: 69010
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 ++++++++++++++++++++-
>>  1 file changed, 42 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> index 3fcf609a1444..1ab6964ee1c2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> @@ -714,6 +714,44 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
>>  	}
>>  }
>>
>> +static i915_reg_t xe2lpd_aux_ctl_reg(struct intel_dp *intel_dp)
>> +{
>> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> +	enum aux_ch aux_ch = dig_port->aux_ch;
>> +
>> +	switch (aux_ch) {
>> +	case AUX_CH_A:
>> +	case AUX_CH_B:
>> +	case AUX_CH_USBC1:
>> +	case AUX_CH_USBC2:
>> +	case AUX_CH_USBC3:
>> +	case AUX_CH_USBC4:
>> +		return XE2LPD_DP_AUX_CH_CTL(aux_ch);
>> +	default:
>> +		MISSING_CASE(aux_ch);
>> +		return XE2LPD_DP_AUX_CH_CTL(AUX_CH_A);
>> +	}
>> +}
>> +
>> +static i915_reg_t xe2lpd_aux_data_reg(struct intel_dp *intel_dp, int index)
>> +{
>> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> +	enum aux_ch aux_ch = dig_port->aux_ch;
>> +
>> +	switch (aux_ch) {
>> +	case AUX_CH_A:
>> +	case AUX_CH_B:
>> +	case AUX_CH_USBC1:
>> +	case AUX_CH_USBC2:
>> +	case AUX_CH_USBC3:
>> +	case AUX_CH_USBC4:
>> +		return XE2LPD_DP_AUX_CH_DATA(aux_ch, index);
>> +	default:
>> +		MISSING_CASE(aux_ch);
>> +		return XE2LPD_DP_AUX_CH_DATA(AUX_CH_A, index);
>> +	}
>> +}
>> +
>>  void intel_dp_aux_fini(struct intel_dp *intel_dp)
>>  {
>>  	if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
>> @@ -731,7 +769,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
>>  	struct intel_encoder *encoder = &dig_port->base;
>>  	enum aux_ch aux_ch = dig_port->aux_ch;
>>
>> -	if (DISPLAY_VER(dev_priv) >= 14) {
>> +	if (DISPLAY_VER(dev_priv) >= 20) {
>> +		intel_dp->aux_ch_ctl_reg = xe2lpd_aux_ctl_reg;
>> +		intel_dp->aux_ch_data_reg = xe2lpd_aux_data_reg;
>> +	} else if (DISPLAY_VER(dev_priv) >= 14) {
>>  		intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
>>  		intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
>>  	} else if (DISPLAY_VER(dev_priv) >= 12) {
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:25AM -0700, Lucas De Marchi wrote:
> From: Luca Coelho <luciano.coelho@intel.com>
> 
> Starting from display version 20, we need to read the pin assignment
> from the IOM TCSS_DDI_STATUS register instead of reading it from the
> FIA.
> 
> We use the pin assignment to decide the maximum lane count.  So, to
> support this change, add a new lnl_tc_port_get_max_lane_count() function
> that reads from the TCSS_DDI_STATUS register and decides the maximum
> lane count based on that.
> 
> BSpec: 69594
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h         |  1 +
>  2 files changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 3c94bbcb5497..37b0f8529b4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
>  	       DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
>  }
>  
> +static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> +	intel_wakeref_t wakeref;
> +	u32 val, pin_assignment;
> +
> +	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)

Do we need this?  I don't think POWER_DOMAIN_DISPLAY_CORE has been tied
to any power wells since VLV/CHV.

Hmm, it looks like we actually grab it (and even assert it) in a bunch of
places on modern platforms that don't make sense to me since it isn't
tied to anything.

I guess leaving this here doesn't hurt anything, although we might want
to go back and take another look at this in the future.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> +		val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
> +
> +	pin_assignment =
> +		REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
> +
> +	switch (pin_assignment) {
> +	default:
> +		MISSING_CASE(pin_assignment);
> +		fallthrough;
> +	case DP_PIN_ASSIGNMENT_D:
> +		return 2;
> +	case DP_PIN_ASSIGNMENT_C:
> +	case DP_PIN_ASSIGNMENT_E:
> +		return 4;
> +	}
> +}
> +
>  static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -348,6 +373,9 @@ int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
>  
>  	assert_tc_cold_blocked(tc);
>  
> +	if (DISPLAY_VER(i915) >= 20)
> +		return lnl_tc_port_get_max_lane_count(dig_port);
> +
>  	if (DISPLAY_VER(i915) >= 14)
>  		return mtl_tc_port_get_max_lane_count(dig_port);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e31a985b02d5..fa85530afac3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6628,6 +6628,7 @@ enum skl_power_gate {
>  #define TCSS_DDI_STATUS(tc)			_MMIO(_PICK_EVEN(tc, \
>  								 _TCSS_DDI_STATUS_1, \
>  								 _TCSS_DDI_STATUS_2))
> +#define  TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK	REG_GENMASK(28, 25)
>  #define  TCSS_DDI_STATUS_READY			REG_BIT(2)
>  #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT	REG_BIT(1)
>  #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:25AM -0700, Lucas De Marchi wrote:
> From: Luca Coelho <luciano.coelho@intel.com>
> 
> Starting from display version 20, we need to read the pin assignment
> from the IOM TCSS_DDI_STATUS register instead of reading it from the
> FIA.
> 
> We use the pin assignment to decide the maximum lane count.  So, to
> support this change, add a new lnl_tc_port_get_max_lane_count() function
> that reads from the TCSS_DDI_STATUS register and decides the maximum
> lane count based on that.
> 
> BSpec: 69594
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h         |  1 +
>  2 files changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 3c94bbcb5497..37b0f8529b4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
>  	       DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
>  }
>  
> +static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> +	intel_wakeref_t wakeref;
> +	u32 val, pin_assignment;
> +
> +	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)

Do we need this?  I don't think POWER_DOMAIN_DISPLAY_CORE has been tied
to any power wells since VLV/CHV.

Hmm, it looks like we actually grab it (and even assert it) in a bunch of
places on modern platforms that don't make sense to me since it isn't
tied to anything.

I guess leaving this here doesn't hurt anything, although we might want
to go back and take another look at this in the future.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> +		val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
> +
> +	pin_assignment =
> +		REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
> +
> +	switch (pin_assignment) {
> +	default:
> +		MISSING_CASE(pin_assignment);
> +		fallthrough;
> +	case DP_PIN_ASSIGNMENT_D:
> +		return 2;
> +	case DP_PIN_ASSIGNMENT_C:
> +	case DP_PIN_ASSIGNMENT_E:
> +		return 4;
> +	}
> +}
> +
>  static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -348,6 +373,9 @@ int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
>  
>  	assert_tc_cold_blocked(tc);
>  
> +	if (DISPLAY_VER(i915) >= 20)
> +		return lnl_tc_port_get_max_lane_count(dig_port);
> +
>  	if (DISPLAY_VER(i915) >= 14)
>  		return mtl_tc_port_get_max_lane_count(dig_port);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e31a985b02d5..fa85530afac3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6628,6 +6628,7 @@ enum skl_power_gate {
>  #define TCSS_DDI_STATUS(tc)			_MMIO(_PICK_EVEN(tc, \
>  								 _TCSS_DDI_STATUS_1, \
>  								 _TCSS_DDI_STATUS_2))
> +#define  TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK	REG_GENMASK(28, 25)
>  #define  TCSS_DDI_STATUS_READY			REG_BIT(2)
>  #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT	REG_BIT(1)
>  #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 29/42] drm/i915/xe2lpd: Add support for HPD

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:27AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
> extra programming for hotplug inversion and DDI HPD filter duration is
> not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
> prefer to fork it into a new function for Xe2_LPD instead of adding a
> platform check.
> 
> BSpec: 68970

It might be worth adding 69940 to the list here, since that's useful for
confirming the hpd pin => bit mapping.

> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_hotplug_irq.c  | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index f76b9deb64b4..74aea0d8d9ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -163,7 +163,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>  	    (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
>  		return;
>  
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
> +		hpd->pch_hpd = hpd_mtp;
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		hpd->pch_hpd = hpd_sde_dg1;
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
>  		hpd->pch_hpd = hpd_mtp;
> @@ -1061,6 +1063,19 @@ static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
>  	mtp_tc_hpd_detection_setup(i915);
>  }
>  
> +static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
> +{
> +	u32 hotplug_irqs, enabled_irqs;
> +
> +	enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
> +	hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
> +
> +	ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
> +
> +	mtp_ddi_hpd_detection_setup(i915);
> +	mtp_tc_hpd_detection_setup(i915);
> +}
> +
>  static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
>  {
>  	return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
> @@ -1120,6 +1135,8 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
>  
>  	xelpdp_pica_hpd_detection_setup(i915);
>  
> +	if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
> +		xe2lpd_sde_hpd_irq_setup(i915);
>  	if (INTEL_PCH_TYPE(i915) >= PCH_MTP)

I think we want an 'else if' here.


Matt

>  		mtp_hpd_irq_setup(i915);
>  }
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 29/42] drm/i915/xe2lpd: Add support for HPD

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:27AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
> extra programming for hotplug inversion and DDI HPD filter duration is
> not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
> prefer to fork it into a new function for Xe2_LPD instead of adding a
> platform check.
> 
> BSpec: 68970

It might be worth adding 69940 to the list here, since that's useful for
confirming the hpd pin => bit mapping.

> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_hotplug_irq.c  | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index f76b9deb64b4..74aea0d8d9ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -163,7 +163,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>  	    (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
>  		return;
>  
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
> +		hpd->pch_hpd = hpd_mtp;
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		hpd->pch_hpd = hpd_sde_dg1;
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
>  		hpd->pch_hpd = hpd_mtp;
> @@ -1061,6 +1063,19 @@ static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
>  	mtp_tc_hpd_detection_setup(i915);
>  }
>  
> +static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
> +{
> +	u32 hotplug_irqs, enabled_irqs;
> +
> +	enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
> +	hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
> +
> +	ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
> +
> +	mtp_ddi_hpd_detection_setup(i915);
> +	mtp_tc_hpd_detection_setup(i915);
> +}
> +
>  static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
>  {
>  	return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
> @@ -1120,6 +1135,8 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
>  
>  	xelpdp_pica_hpd_detection_setup(i915);
>  
> +	if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
> +		xe2lpd_sde_hpd_irq_setup(i915);
>  	if (INTEL_PCH_TYPE(i915) >= PCH_MTP)

I think we want an 'else if' here.


Matt

>  		mtp_hpd_irq_setup(i915);
>  }
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 30/42] drm/i915/xe2lpd: Extend Wa_15010685871

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:28AM -0700, Lucas De Marchi wrote:
> Xe2_LPD also needs workaround 15010685871.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4207863b7b2a..fdd8d04fe12c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1839,9 +1839,9 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
>  
>  static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
>  {
> -	return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
> -		dev_priv->display.cdclk.hw.vco > 0 &&
> -		HAS_CDCLK_SQUASH(dev_priv));
> +	return (IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv) ||
> +		DISPLAY_VER(dev_priv) == 20) &&

We may have future 20.xx platforms for which this doesn't hold true.
This should probably be a "DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0)"
to exactly match Xe2_LPD and nothing else.

Note that the drm-intel version of the code has already replaced the MTL
check with an Xe_LPD+ version check, but that hasn't propagated to
drm-xe-next yet.

While we're here, we can probably re-order this too (newest platform
first).


Matt

> +		dev_priv->display.cdclk.hw.vco > 0 && HAS_CDCLK_SQUASH(dev_priv);
>  }
>  
>  static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 30/42] drm/i915/xe2lpd: Extend Wa_15010685871

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:28AM -0700, Lucas De Marchi wrote:
> Xe2_LPD also needs workaround 15010685871.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4207863b7b2a..fdd8d04fe12c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1839,9 +1839,9 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
>  
>  static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
>  {
> -	return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
> -		dev_priv->display.cdclk.hw.vco > 0 &&
> -		HAS_CDCLK_SQUASH(dev_priv));
> +	return (IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv) ||
> +		DISPLAY_VER(dev_priv) == 20) &&

We may have future 20.xx platforms for which this doesn't hold true.
This should probably be a "DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0)"
to exactly match Xe2_LPD and nothing else.

Note that the drm-intel version of the code has already replaced the MTL
check with an Xe_LPD+ version check, but that hasn't propagated to
drm-xe-next yet.

While we're here, we can probably re-order this too (newest platform
first).


Matt

> +		dev_priv->display.cdclk.hw.vco > 0 && HAS_CDCLK_SQUASH(dev_priv);
>  }
>  
>  static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote:
> LNL's south display uses the same table as MTP. Check for LNL's fake PCH
> to make it consistent with the other checks.
> 
> The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
> other cases, uses the same as the previous platform.
> 
> Bspec: 68971, 20124
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c  | 2 +-
>  drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 097c1f23d3ae..3772b91e155c 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
>  	const u8 *ddc_pin_map;
>  	int i, n_entries;
>  
> -	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
> +	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {

The LUNARLAKE here vs PCH_LNL below seems inconsistent.  Either way, we
should probably put the newer platform first in the condition.

Aside from those

        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  		ddc_pin_map = adlp_ddc_pin_map;
>  		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
>  	} else if (IS_ALDERLAKE_S(i915)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index e95ddb580ef6..801fabbccf7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
>  	const struct gmbus_pin *pins;
>  	size_t size;
>  
> -	if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
> +	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
> +		pins = gmbus_pins_mtp;
> +		size = ARRAY_SIZE(gmbus_pins_mtp);
> +	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
>  		pins = gmbus_pins_dg2;
>  		size = ARRAY_SIZE(gmbus_pins_dg2);
>  	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote:
> LNL's south display uses the same table as MTP. Check for LNL's fake PCH
> to make it consistent with the other checks.
> 
> The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
> other cases, uses the same as the previous platform.
> 
> Bspec: 68971, 20124
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c  | 2 +-
>  drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 097c1f23d3ae..3772b91e155c 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
>  	const u8 *ddc_pin_map;
>  	int i, n_entries;
>  
> -	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
> +	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {

The LUNARLAKE here vs PCH_LNL below seems inconsistent.  Either way, we
should probably put the newer platform first in the condition.

Aside from those

        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  		ddc_pin_map = adlp_ddc_pin_map;
>  		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
>  	} else if (IS_ALDERLAKE_S(i915)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index e95ddb580ef6..801fabbccf7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
>  	const struct gmbus_pin *pins;
>  	size_t size;
>  
> -	if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
> +	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
> +		pins = gmbus_pins_mtp;
> +		size = ARRAY_SIZE(gmbus_pins_mtp);
> +	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
>  		pins = gmbus_pins_dg2;
>  		size = ARRAY_SIZE(gmbus_pins_dg2);
>  	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:30AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> In Lunar Lake we now separate MDCLK from CDLCK, which used to be before
> always 2 times CDCLK.  Now we might afford lower CDCLK, while having
> higher memory clock, so improving bandwidth and power consumption at the
> same time.  This is prep work required to enable that.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 30 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cdclk.h |  2 +-
>  2 files changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index fdd8d04fe12c..3e566f45996d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1223,6 +1223,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>  
>  struct intel_cdclk_vals {
>  	u32 cdclk;
> +	u32 mdclk;
>  	u16 refclk;
>  	u16 waveform;
>  	u8 divider;	/* CD2X divider * 2 */
> @@ -1524,6 +1525,8 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
>  static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  			  struct intel_cdclk_config *cdclk_config)
>  {
> +	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> +	int i, ratio, tbl_waveform = 0;
>  	u32 squash_ctl = 0;
>  	u32 divider;
>  	int div;
> @@ -1574,10 +1577,36 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  
>  		cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
>  							cdclk_config->vco, size * div);
> +		tbl_waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
>  	} else {
>  		cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
>  	}
>  
> +	ratio = cdclk_config->vco / cdclk_config->ref;
> +
> +	for (i = 0; table[i].refclk; i++) {
> +		if (table[i].refclk != cdclk_config->ref)
> +			continue;
> +
> +		if (table[i].divider != div)
> +			continue;
> +
> +		if (table[i].waveform != tbl_waveform)
> +			continue;
> +
> +		if (table[i].ratio != ratio)
> +			continue;
> +
> +		/*
> +		 * Supported from LunarLake HW onwards, however considering that
> +		 * besides this the whole procedure is the same, we keep this
> +		 * for all the platforms.
> +		 */
> +		cdclk_config->mdclk = table[i].mdclk;
> +
> +		break;
> +	}

I might be misunderstanding something, but from bspec 68861, is looks
like the mdclk frequency is always just "ratio * refclk."  Which is the
value we already have stored in cdclk_config->vco.  Do we need to do
this extra lookup or track this value separately?


Matt

> +
>   out:
>  	/*
>  	 * Can't read this out :( Let's assume it's
> @@ -2191,6 +2220,7 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
>  			       const struct intel_cdclk_config *b)
>  {
>  	return a->cdclk != b->cdclk ||
> +		a->mdclk != b->mdclk ||
>  		a->vco != b->vco ||
>  		a->ref != b->ref;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 48fd7d39e0cd..3e7eabd4d7b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -16,7 +16,7 @@ struct intel_atomic_state;
>  struct intel_crtc_state;
>  
>  struct intel_cdclk_config {
> -	unsigned int cdclk, vco, ref, bypass;
> +	unsigned int cdclk, mdclk, vco, ref, bypass;
>  	u8 voltage_level;
>  };
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:30AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> In Lunar Lake we now separate MDCLK from CDLCK, which used to be before
> always 2 times CDCLK.  Now we might afford lower CDCLK, while having
> higher memory clock, so improving bandwidth and power consumption at the
> same time.  This is prep work required to enable that.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 30 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cdclk.h |  2 +-
>  2 files changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index fdd8d04fe12c..3e566f45996d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1223,6 +1223,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>  
>  struct intel_cdclk_vals {
>  	u32 cdclk;
> +	u32 mdclk;
>  	u16 refclk;
>  	u16 waveform;
>  	u8 divider;	/* CD2X divider * 2 */
> @@ -1524,6 +1525,8 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
>  static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  			  struct intel_cdclk_config *cdclk_config)
>  {
> +	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> +	int i, ratio, tbl_waveform = 0;
>  	u32 squash_ctl = 0;
>  	u32 divider;
>  	int div;
> @@ -1574,10 +1577,36 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  
>  		cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
>  							cdclk_config->vco, size * div);
> +		tbl_waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
>  	} else {
>  		cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
>  	}
>  
> +	ratio = cdclk_config->vco / cdclk_config->ref;
> +
> +	for (i = 0; table[i].refclk; i++) {
> +		if (table[i].refclk != cdclk_config->ref)
> +			continue;
> +
> +		if (table[i].divider != div)
> +			continue;
> +
> +		if (table[i].waveform != tbl_waveform)
> +			continue;
> +
> +		if (table[i].ratio != ratio)
> +			continue;
> +
> +		/*
> +		 * Supported from LunarLake HW onwards, however considering that
> +		 * besides this the whole procedure is the same, we keep this
> +		 * for all the platforms.
> +		 */
> +		cdclk_config->mdclk = table[i].mdclk;
> +
> +		break;
> +	}

I might be misunderstanding something, but from bspec 68861, is looks
like the mdclk frequency is always just "ratio * refclk."  Which is the
value we already have stored in cdclk_config->vco.  Do we need to do
this extra lookup or track this value separately?


Matt

> +
>   out:
>  	/*
>  	 * Can't read this out :( Let's assume it's
> @@ -2191,6 +2220,7 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
>  			       const struct intel_cdclk_config *b)
>  {
>  	return a->cdclk != b->cdclk ||
> +		a->mdclk != b->mdclk ||
>  		a->vco != b->vco ||
>  		a->ref != b->ref;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 48fd7d39e0cd..3e7eabd4d7b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -16,7 +16,7 @@ struct intel_atomic_state;
>  struct intel_crtc_state;
>  
>  struct intel_cdclk_config {
> -	unsigned int cdclk, vco, ref, bypass;
> +	unsigned int cdclk, mdclk, vco, ref, bypass;
>  	u8 voltage_level;
>  };
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 33/42] drm/i915/lnl: Add CDCLK table

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:31AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> Add a new Lunar Lake CDCLK table from BSpec and also a helper function
> in order to be able to find lowest possible CDCLK, which has required
> MDCLK for the correspodent pixel rate.
> 
> Bspec: 68861
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 52 +++++++++++++++++++++-
>  1 file changed, 50 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3e566f45996d..ed45a2cf5c9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1381,6 +1381,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = {
>  	{}
>  };
>  
> +static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> +	{ .refclk = 38400, .cdclk = 153600, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> +	{ .refclk = 38400, .cdclk = 172800, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> +	{ .refclk = 38400, .cdclk = 192000, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> +	{ .refclk = 38400, .cdclk = 211200, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> +	{ .refclk = 38400, .cdclk = 230400, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> +	{ .refclk = 38400, .cdclk = 249600, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> +	{ .refclk = 38400, .cdclk = 268800, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> +	{ .refclk = 38400, .cdclk = 288000, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> +	{ .refclk = 38400, .cdclk = 307200, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0x0000 },

Shouldn't waveform be 0xffff for this one?

> +	{ .refclk = 38400, .cdclk = 330000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> +	{ .refclk = 38400, .cdclk = 360000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> +	{ .refclk = 38400, .cdclk = 390000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> +	{ .refclk = 38400, .cdclk = 420000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> +	{ .refclk = 38400, .cdclk = 450000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> +	{ .refclk = 38400, .cdclk = 480000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0x0000 },

Ditto.

> +	{ .refclk = 38400, .cdclk = 487200, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> +	{ .refclk = 38400, .cdclk = 522000, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> +	{ .refclk = 38400, .cdclk = 556800, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0x0000 },

Ditto.

> +	{ .refclk = 38400, .cdclk = 571200, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> +	{ .refclk = 38400, .cdclk = 612000, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> +	{ .refclk = 38400, .cdclk = 652800, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0x0000 },

Ditto.

> +	{}
> +};

As noted on the previous patch, I don't see a need for the .mdclk field
since that's equivalent to the vco value that we're already tracking.


Matt

> +
>  static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
>  {
>  	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> @@ -2531,12 +2556,32 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>  	}
>  }
>  
> +static int
> +cdclk_match_by_refclk_mdclk(struct drm_i915_private *i915, int pixel_rate)
> +{
> +	const struct intel_cdclk_vals *table = i915->display.cdclk.table;
> +	int i;
> +
> +	for (i = 0; table[i].refclk; i++)
> +		if (table[i].refclk == i915->display.cdclk.hw.ref &&
> +		    table[i].mdclk >= pixel_rate)
> +			return table[i].cdclk;
> +
> +	drm_WARN(&i915->drm, 1,
> +		 "Cannot satisfy pixel rate %d with refclk %u\n",
> +		 pixel_rate, i915->display.cdclk.hw.ref);
> +
> +	return 0;
> +}
> +
>  static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	int pixel_rate = crtc_state->pixel_rate;
>  
> -	if (DISPLAY_VER(dev_priv) >= 10)
> +	if (DISPLAY_VER(dev_priv) >= 20)
> +		return cdclk_match_by_refclk_mdclk(dev_priv, pixel_rate);
> +	else if (DISPLAY_VER(dev_priv) >= 10)
>  		return DIV_ROUND_UP(pixel_rate, 2);
>  	else if (DISPLAY_VER(dev_priv) == 9 ||
>  		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> @@ -3581,7 +3626,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
>   */
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_METEORLAKE(dev_priv)) {
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> +		dev_priv->display.cdclk.table = lnl_cdclk_table;
> +	} else if (IS_METEORLAKE(dev_priv)) {
>  		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
>  		dev_priv->display.cdclk.table = mtl_cdclk_table;
>  	} else if (IS_DG2(dev_priv)) {
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 33/42] drm/i915/lnl: Add CDCLK table

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:31AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> Add a new Lunar Lake CDCLK table from BSpec and also a helper function
> in order to be able to find lowest possible CDCLK, which has required
> MDCLK for the correspodent pixel rate.
> 
> Bspec: 68861
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 52 +++++++++++++++++++++-
>  1 file changed, 50 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3e566f45996d..ed45a2cf5c9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1381,6 +1381,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = {
>  	{}
>  };
>  
> +static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> +	{ .refclk = 38400, .cdclk = 153600, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> +	{ .refclk = 38400, .cdclk = 172800, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> +	{ .refclk = 38400, .cdclk = 192000, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> +	{ .refclk = 38400, .cdclk = 211200, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> +	{ .refclk = 38400, .cdclk = 230400, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> +	{ .refclk = 38400, .cdclk = 249600, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> +	{ .refclk = 38400, .cdclk = 268800, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> +	{ .refclk = 38400, .cdclk = 288000, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> +	{ .refclk = 38400, .cdclk = 307200, .mdclk = 614400, .divider = 2, .ratio = 16, .waveform = 0x0000 },

Shouldn't waveform be 0xffff for this one?

> +	{ .refclk = 38400, .cdclk = 330000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> +	{ .refclk = 38400, .cdclk = 360000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> +	{ .refclk = 38400, .cdclk = 390000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> +	{ .refclk = 38400, .cdclk = 420000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> +	{ .refclk = 38400, .cdclk = 450000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> +	{ .refclk = 38400, .cdclk = 480000, .mdclk = 960000, .divider = 2, .ratio = 25, .waveform = 0x0000 },

Ditto.

> +	{ .refclk = 38400, .cdclk = 487200, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> +	{ .refclk = 38400, .cdclk = 522000, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> +	{ .refclk = 38400, .cdclk = 556800, .mdclk = 1113600, .divider = 2, .ratio = 29, .waveform = 0x0000 },

Ditto.

> +	{ .refclk = 38400, .cdclk = 571200, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> +	{ .refclk = 38400, .cdclk = 612000, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> +	{ .refclk = 38400, .cdclk = 652800, .mdclk = 1305600, .divider = 2, .ratio = 34, .waveform = 0x0000 },

Ditto.

> +	{}
> +};

As noted on the previous patch, I don't see a need for the .mdclk field
since that's equivalent to the vco value that we're already tracking.


Matt

> +
>  static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
>  {
>  	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> @@ -2531,12 +2556,32 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>  	}
>  }
>  
> +static int
> +cdclk_match_by_refclk_mdclk(struct drm_i915_private *i915, int pixel_rate)
> +{
> +	const struct intel_cdclk_vals *table = i915->display.cdclk.table;
> +	int i;
> +
> +	for (i = 0; table[i].refclk; i++)
> +		if (table[i].refclk == i915->display.cdclk.hw.ref &&
> +		    table[i].mdclk >= pixel_rate)
> +			return table[i].cdclk;
> +
> +	drm_WARN(&i915->drm, 1,
> +		 "Cannot satisfy pixel rate %d with refclk %u\n",
> +		 pixel_rate, i915->display.cdclk.hw.ref);
> +
> +	return 0;
> +}
> +
>  static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	int pixel_rate = crtc_state->pixel_rate;
>  
> -	if (DISPLAY_VER(dev_priv) >= 10)
> +	if (DISPLAY_VER(dev_priv) >= 20)
> +		return cdclk_match_by_refclk_mdclk(dev_priv, pixel_rate);
> +	else if (DISPLAY_VER(dev_priv) >= 10)
>  		return DIV_ROUND_UP(pixel_rate, 2);
>  	else if (DISPLAY_VER(dev_priv) == 9 ||
>  		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> @@ -3581,7 +3626,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
>   */
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_METEORLAKE(dev_priv)) {
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> +		dev_priv->display.cdclk.table = lnl_cdclk_table;
> +	} else if (IS_METEORLAKE(dev_priv)) {
>  		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
>  		dev_priv->display.cdclk.table = mtl_cdclk_table;
>  	} else if (IS_DG2(dev_priv)) {
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:32AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> Introduce correspondent definitions and for choosing between CD2X CDCLK
> and PLL CDCLK as a source.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h            |  3 +++
>  2 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ed45a2cf5c9a..04937aaabcee 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1932,8 +1932,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  		dg2_cdclk_squash_program(dev_priv, waveform);
>  
>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
> -		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> -		skl_cdclk_decimal(cdclk);
> +		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
>  
>  	/*
>  	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
> @@ -1942,6 +1941,17 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
>  	    cdclk >= 500000)
>  		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> +
> +	if (DISPLAY_VER(dev_priv) >= 20)
> +		/*
> +		 * Using CDCLK through PLL seems to be always better option when
> +		 * its supported, both in terms of performance and power
> +		 * consumption.
> +		 */

I'm not sure what this comment is based on.  But the table on bspec
68861 specifically tells us to set this bit for the cdclk table we
implemented in the last patch, so the logic is correct regardless.

> +		val |= CDCLK_SOURCE_SEL_CDCLK_PLL;
> +	else
> +		val |= skl_cdclk_decimal(cdclk);
> +
>  	intel_de_write(dev_priv, CDCLK_CTL, val);
>  
>  	if (pipe != INVALID_PIPE)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa85530afac3..d5850761a75a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5933,6 +5933,9 @@ enum skl_power_gate {
>  #define  CDCLK_FREQ_540		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
>  #define  CDCLK_FREQ_337_308		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
>  #define  CDCLK_FREQ_675_617		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
> +#define  CDCLK_SOURCE_SEL_MASK		REG_BIT(25)
> +#define  CDCLK_SOURCE_SEL_CD2X		REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 0)

No need to make a single-bit "mask" or define the unused
CDCLK_SOURCE_SEL_CD2X here.  We can just define
CDCLK_SOURCE_SEL_CDCLK_PLL as REG_BIT(25) directly.


Matt

> +#define  CDCLK_SOURCE_SEL_CDCLK_PLL	REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 1)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	REG_GENMASK(23, 22)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_1	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:32AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> Introduce correspondent definitions and for choosing between CD2X CDCLK
> and PLL CDCLK as a source.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h            |  3 +++
>  2 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ed45a2cf5c9a..04937aaabcee 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1932,8 +1932,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  		dg2_cdclk_squash_program(dev_priv, waveform);
>  
>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
> -		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> -		skl_cdclk_decimal(cdclk);
> +		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
>  
>  	/*
>  	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
> @@ -1942,6 +1941,17 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
>  	    cdclk >= 500000)
>  		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> +
> +	if (DISPLAY_VER(dev_priv) >= 20)
> +		/*
> +		 * Using CDCLK through PLL seems to be always better option when
> +		 * its supported, both in terms of performance and power
> +		 * consumption.
> +		 */

I'm not sure what this comment is based on.  But the table on bspec
68861 specifically tells us to set this bit for the cdclk table we
implemented in the last patch, so the logic is correct regardless.

> +		val |= CDCLK_SOURCE_SEL_CDCLK_PLL;
> +	else
> +		val |= skl_cdclk_decimal(cdclk);
> +
>  	intel_de_write(dev_priv, CDCLK_CTL, val);
>  
>  	if (pipe != INVALID_PIPE)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa85530afac3..d5850761a75a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5933,6 +5933,9 @@ enum skl_power_gate {
>  #define  CDCLK_FREQ_540		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
>  #define  CDCLK_FREQ_337_308		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
>  #define  CDCLK_FREQ_675_617		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
> +#define  CDCLK_SOURCE_SEL_MASK		REG_BIT(25)
> +#define  CDCLK_SOURCE_SEL_CD2X		REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 0)

No need to make a single-bit "mask" or define the unused
CDCLK_SOURCE_SEL_CD2X here.  We can just define
CDCLK_SOURCE_SEL_CDCLK_PLL as REG_BIT(25) directly.


Matt

> +#define  CDCLK_SOURCE_SEL_CDCLK_PLL	REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 1)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	REG_GENMASK(23, 22)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_1	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd

[Kandpal, Suraj]

> Subject: [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for
> planar yuv on xe2lpd
> 
> From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> 
> Enable odd size and panning for planar yuv formats.
> 
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Maybe add the Bspec/ HSD reference in here otherwise
LGTM

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index fb13f0bb8c52..da6ee7f0675a 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -986,6 +986,14 @@ int intel_plane_check_src_coordinates(struct
> intel_plane_state *plane_state)
>  	if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
>  		hsub = 2;
>  		vsub = 2;
> +	} else if (DISPLAY_VER(i915) >= 20 &&
> +		intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier)) {
> +		/*
> +		 * This allow NV12 and P0xx formats to have odd size and/or
> odd
> +		 * source coordinates on DISPLAY_VER(i915) >= 20
> +		 */
> +		hsub = 1;
> +		vsub = 1;
>  	} else {
>  		hsub = fb->format->hsub;
>  		vsub = fb->format->vsub;
> --
> 2.40.1

Re: [Intel-xe] [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd

[Kandpal, Suraj]

> Subject: [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for
> planar yuv on xe2lpd
> 
> From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> 
> Enable odd size and panning for planar yuv formats.
> 
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Maybe add the Bspec/ HSD reference in here otherwise
LGTM

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index fb13f0bb8c52..da6ee7f0675a 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -986,6 +986,14 @@ int intel_plane_check_src_coordinates(struct
> intel_plane_state *plane_state)
>  	if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
>  		hsub = 2;
>  		vsub = 2;
> +	} else if (DISPLAY_VER(i915) >= 20 &&
> +		intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier)) {
> +		/*
> +		 * This allow NV12 and P0xx formats to have odd size and/or
> odd
> +		 * source coordinates on DISPLAY_VER(i915) >= 20
> +		 */
> +		hsub = 1;
> +		vsub = 1;
>  	} else {
>  		hsub = fb->format->hsub;
>  		vsub = fb->format->vsub;
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Wednesday, August 23, 2023 10:37 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Coelho, Luciano <luciano.coelho@intel.com>
> Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the
> main _max_lane_count() func
> 
> From: Luca Coelho <luciano.coelho@intel.com>
> 
> This makes the code a bit more symmetric and readable, especially when we
> start adding more display version-specific alternatives.
> 
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> Link: https://lore.kernel.org/r/20230721111121.369227-4-
> luciano.coelho@intel.com
> ---
>  drivers/gpu/drm/i915/display/intel_tc.c | 32 +++++++++++++++----------
>  1 file changed, 19 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index de848b329f4b..43b8eeba26f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -311,23 +311,12 @@ static int mtl_tc_port_get_max_lane_count(struct
> intel_digital_port *dig_port)
>  	}
>  }
> 
> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> +static int intel_tc_port_get_max_lane_count(struct intel_digital_port
> +*dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> -	struct intel_tc_port *tc = to_tc_port(dig_port);
> -	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>  	intel_wakeref_t wakeref;
> -	u32 lane_mask;
> -
> -	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> -		return 4;
> +	u32 lane_mask = 0;
> 
> -	assert_tc_cold_blocked(tc);
> -
> -	if (DISPLAY_VER(i915) >= 14)
> -		return mtl_tc_port_get_max_lane_count(dig_port);
> -
> -	lane_mask = 0;
>  	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE,
> wakeref)
>  		lane_mask = intel_tc_port_get_lane_mask(dig_port);
> 
> @@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct
> intel_digital_port *dig_port)
>  	}
>  }

Rather than having two functions:
mtl_tc_port_get_max_lane_count()
& intel_tc_port_get_max_lane_count() that both call:
with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
                lane_mask = intel_tc_port_get_lane_mask(dig_port);
to get the lane mask the us directly pass the lane_mask to the above two functions
and make the call for getting the lane_mask common i.e lets call it in 
intel_tc_port_fia_max_lane_count().

Regards,
Suraj Kandpal
> 
> +int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> +*dig_port) {
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	struct intel_tc_port *tc = to_tc_port(dig_port);
> +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> +
> +	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> +		return 4;
> +
> +	assert_tc_cold_blocked(tc);
> +
> +	if (DISPLAY_VER(i915) >= 14)
> +		return mtl_tc_port_get_max_lane_count(dig_port);
> +
> +	return intel_tc_port_get_max_lane_count(dig_port);
> +}
> +
>  void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>  				      int required_lanes)
>  {
> --
> 2.40.1

Re: [Intel-xe] [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Wednesday, August 23, 2023 10:37 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Coelho, Luciano <luciano.coelho@intel.com>
> Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the
> main _max_lane_count() func
> 
> From: Luca Coelho <luciano.coelho@intel.com>
> 
> This makes the code a bit more symmetric and readable, especially when we
> start adding more display version-specific alternatives.
> 
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> Link: https://lore.kernel.org/r/20230721111121.369227-4-
> luciano.coelho@intel.com
> ---
>  drivers/gpu/drm/i915/display/intel_tc.c | 32 +++++++++++++++----------
>  1 file changed, 19 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index de848b329f4b..43b8eeba26f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -311,23 +311,12 @@ static int mtl_tc_port_get_max_lane_count(struct
> intel_digital_port *dig_port)
>  	}
>  }
> 
> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> +static int intel_tc_port_get_max_lane_count(struct intel_digital_port
> +*dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> -	struct intel_tc_port *tc = to_tc_port(dig_port);
> -	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>  	intel_wakeref_t wakeref;
> -	u32 lane_mask;
> -
> -	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> -		return 4;
> +	u32 lane_mask = 0;
> 
> -	assert_tc_cold_blocked(tc);
> -
> -	if (DISPLAY_VER(i915) >= 14)
> -		return mtl_tc_port_get_max_lane_count(dig_port);
> -
> -	lane_mask = 0;
>  	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE,
> wakeref)
>  		lane_mask = intel_tc_port_get_lane_mask(dig_port);
> 
> @@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct
> intel_digital_port *dig_port)
>  	}
>  }

Rather than having two functions:
mtl_tc_port_get_max_lane_count()
& intel_tc_port_get_max_lane_count() that both call:
with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
                lane_mask = intel_tc_port_get_lane_mask(dig_port);
to get the lane mask the us directly pass the lane_mask to the above two functions
and make the call for getting the lane_mask common i.e lets call it in 
intel_tc_port_fia_max_lane_count().

Regards,
Suraj Kandpal
> 
> +int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> +*dig_port) {
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	struct intel_tc_port *tc = to_tc_port(dig_port);
> +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> +
> +	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> +		return 4;
> +
> +	assert_tc_cold_blocked(tc);
> +
> +	if (DISPLAY_VER(i915) >= 14)
> +		return mtl_tc_port_get_max_lane_count(dig_port);
> +
> +	return intel_tc_port_get_max_lane_count(dig_port);
> +}
> +
>  void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>  				      int required_lanes)
>  {
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 10/42] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()

[Kandpal, Suraj]

> From: Luca Coelho <luciano.coelho@intel.com>
> 
> It is irrelevant for the caller that the max lane count is being derived from a FIA
> register, so having "fia" in the function name is irrelevant.  Rename the
> function accordingly.
> 
LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Link: https://lore.kernel.org/r/20230721111121.369227-5-
> luciano.coelho@intel.com
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c      | 4 ++--
>  drivers/gpu/drm/i915/display/intel_tc.c      | 4 ++--
>  drivers/gpu/drm/i915/display/intel_tc.h      | 2 +-
>  4 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 26e256165b80..a5918bf30c31 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -58,7 +58,7 @@ static u8 intel_cx0_get_owned_lane_mask(struct
> drm_i915_private *i915,
>  	 * In DP-alt with pin assignment D, only PHY lane 0 is owned
>  	 * by display and lane 1 is owned by USB.
>  	 */
> -	return intel_tc_port_fia_max_lane_count(dig_port) > 2
> +	return intel_tc_port_max_lane_count(dig_port) > 2
>  		? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9f40da20e88d..84584864511b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -306,13 +306,13 @@ static int
> intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	int source_max = intel_dp_max_source_lane_count(dig_port);
>  	int sink_max = intel_dp->max_sink_lane_count;
> -	int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
> +	int port_max = intel_tc_port_max_lane_count(dig_port);
>  	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp-
> >lttpr_common_caps);
> 
>  	if (lttpr_max)
>  		sink_max = min(sink_max, lttpr_max);
> 
> -	return min3(source_max, sink_max, fia_max);
> +	return min3(source_max, sink_max, port_max);
>  }
> 
>  int intel_dp_max_lane_count(struct intel_dp *intel_dp) diff --git
> a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index 43b8eeba26f8..3c94bbcb5497 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -337,7 +337,7 @@ static int intel_tc_port_get_max_lane_count(struct
> intel_digital_port *dig_port)
>  	}
>  }
> 
> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> +int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  	struct intel_tc_port *tc = to_tc_port(dig_port); @@ -589,7 +589,7
> @@ static bool tc_phy_verify_legacy_or_dp_alt_mode(struct intel_tc_port
> *tc,
>  	struct intel_digital_port *dig_port = tc->dig_port;
>  	int max_lanes;
> 
> -	max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
> +	max_lanes = intel_tc_port_max_lane_count(dig_port);
>  	if (tc->mode == TC_PORT_LEGACY) {
>  		drm_WARN_ON(&i915->drm, max_lanes != 4);
>  		return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
> b/drivers/gpu/drm/i915/display/intel_tc.h
> index ffc0e2a74e43..80a61e52850e 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> @@ -20,7 +20,7 @@ bool intel_tc_port_connected(struct intel_encoder
> *encoder);  bool intel_tc_port_connected_locked(struct intel_encoder
> *encoder);
> 
>  u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port
> *dig_port); -int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> *dig_port);
> +int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
>  void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>  				      int required_lanes);
> 
> --
> 2.40.1

Re: [Intel-xe] [Intel-gfx] [PATCH 10/42] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()

[Kandpal, Suraj]

> From: Luca Coelho <luciano.coelho@intel.com>
> 
> It is irrelevant for the caller that the max lane count is being derived from a FIA
> register, so having "fia" in the function name is irrelevant.  Rename the
> function accordingly.
> 
LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Link: https://lore.kernel.org/r/20230721111121.369227-5-
> luciano.coelho@intel.com
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c      | 4 ++--
>  drivers/gpu/drm/i915/display/intel_tc.c      | 4 ++--
>  drivers/gpu/drm/i915/display/intel_tc.h      | 2 +-
>  4 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 26e256165b80..a5918bf30c31 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -58,7 +58,7 @@ static u8 intel_cx0_get_owned_lane_mask(struct
> drm_i915_private *i915,
>  	 * In DP-alt with pin assignment D, only PHY lane 0 is owned
>  	 * by display and lane 1 is owned by USB.
>  	 */
> -	return intel_tc_port_fia_max_lane_count(dig_port) > 2
> +	return intel_tc_port_max_lane_count(dig_port) > 2
>  		? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9f40da20e88d..84584864511b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -306,13 +306,13 @@ static int
> intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	int source_max = intel_dp_max_source_lane_count(dig_port);
>  	int sink_max = intel_dp->max_sink_lane_count;
> -	int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
> +	int port_max = intel_tc_port_max_lane_count(dig_port);
>  	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp-
> >lttpr_common_caps);
> 
>  	if (lttpr_max)
>  		sink_max = min(sink_max, lttpr_max);
> 
> -	return min3(source_max, sink_max, fia_max);
> +	return min3(source_max, sink_max, port_max);
>  }
> 
>  int intel_dp_max_lane_count(struct intel_dp *intel_dp) diff --git
> a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index 43b8eeba26f8..3c94bbcb5497 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -337,7 +337,7 @@ static int intel_tc_port_get_max_lane_count(struct
> intel_digital_port *dig_port)
>  	}
>  }
> 
> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> +int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  	struct intel_tc_port *tc = to_tc_port(dig_port); @@ -589,7 +589,7
> @@ static bool tc_phy_verify_legacy_or_dp_alt_mode(struct intel_tc_port
> *tc,
>  	struct intel_digital_port *dig_port = tc->dig_port;
>  	int max_lanes;
> 
> -	max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
> +	max_lanes = intel_tc_port_max_lane_count(dig_port);
>  	if (tc->mode == TC_PORT_LEGACY) {
>  		drm_WARN_ON(&i915->drm, max_lanes != 4);
>  		return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
> b/drivers/gpu/drm/i915/display/intel_tc.h
> index ffc0e2a74e43..80a61e52850e 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> @@ -20,7 +20,7 @@ bool intel_tc_port_connected(struct intel_encoder
> *encoder);  bool intel_tc_port_connected_locked(struct intel_encoder
> *encoder);
> 
>  u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port
> *dig_port); -int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> *dig_port);
> +int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
>  void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>  				      int required_lanes);
> 
> --
> 2.40.1

Re: [Intel-gfx] [Intel-xe] [PATCH 12/42] drm/i915/lnl: Add display definitions

[Jani Nikula]

On Wed, 23 Aug 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
>> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> 
>> Add Lunar Lake platform definitions for i915 display. The support for
>> LNL will be added to the xe driver, with i915 only driving the display
>> side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
>> i915 module.
>> 
>> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  .../gpu/drm/i915/display/intel_display_device.c   | 15 +++++++++++++++
>>  drivers/gpu/drm/i915/i915_drv.h                   |  1 +
>>  2 files changed, 16 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
>> index f87470da25d0..b853cd0c704a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
>> @@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
>>  		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
>>  };
>>  
>> +static const struct intel_display_device_info xe2_lpd_display = {
>> +	XE_LPD_FEATURES,
>> +	.has_cdclk_crawl = 1,
>> +	.has_cdclk_squash = 1,
>
> XE_LPD_FEATURES, crawl, squash, transcoder mask, and port mask are all
> common between Xe_LPD+ and Xe2_LPD.  Maybe we should add an
> XE_LPDP_FEATURES macro first, and then re-use it here so that the deltas
> are smaller and it's more obvious what the key changes are with this new
> IP?
>
>> +
>> +	.__runtime_defaults.ip.ver = 20,
>> +	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
>
> With Xe2, FBC is supported on all pipes now (bspec 68881, 68904).
>
>> +	.__runtime_defaults.cpu_transcoder_mask =
>> +		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>> +	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
>> +		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
>> +};
>> +
>>  __diag_pop();
>>  
>>  #undef INTEL_VGA_DEVICE
>> @@ -795,6 +809,7 @@ static const struct {
>>  	const struct intel_display_device_info *display;
>>  } gmdid_display_map[] = {
>>  	{ 14,  0, &xe_lpdp_display },
>> +	{ 20,  0, &xe2_lpd_display },
>>  };
>>  
>>  static const struct intel_display_device_info *
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 07f79b1028e1..96ac9a9cc155 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>  #define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
>>  #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
>>  #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
>> +#define IS_LUNARLAKE(dev_priv)  0
>
> As noted on the previous patch, we might be able to drop this completely
> if we update the fake PCH and gmbus code to match on display IP.  Given
> that PCH isn't even involved in south display handling anymore, that
> seems like it might be reasonable?  If anything, we're more likely to
> need to match on PICA ID (which has its own GMD_ID register) than base
> platform at some point in the future.

And in any case it's out of place in this patch.

BR,
Jani.

>
>
> Matt
>
>>  
>>  #define IS_METEORLAKE_M(i915) \
>>  	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
>> -- 
>> 2.40.1
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-xe] [PATCH 12/42] drm/i915/lnl: Add display definitions

[Jani Nikula]

On Wed, 23 Aug 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
>> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> 
>> Add Lunar Lake platform definitions for i915 display. The support for
>> LNL will be added to the xe driver, with i915 only driving the display
>> side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
>> i915 module.
>> 
>> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  .../gpu/drm/i915/display/intel_display_device.c   | 15 +++++++++++++++
>>  drivers/gpu/drm/i915/i915_drv.h                   |  1 +
>>  2 files changed, 16 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
>> index f87470da25d0..b853cd0c704a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
>> @@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
>>  		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
>>  };
>>  
>> +static const struct intel_display_device_info xe2_lpd_display = {
>> +	XE_LPD_FEATURES,
>> +	.has_cdclk_crawl = 1,
>> +	.has_cdclk_squash = 1,
>
> XE_LPD_FEATURES, crawl, squash, transcoder mask, and port mask are all
> common between Xe_LPD+ and Xe2_LPD.  Maybe we should add an
> XE_LPDP_FEATURES macro first, and then re-use it here so that the deltas
> are smaller and it's more obvious what the key changes are with this new
> IP?
>
>> +
>> +	.__runtime_defaults.ip.ver = 20,
>> +	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
>
> With Xe2, FBC is supported on all pipes now (bspec 68881, 68904).
>
>> +	.__runtime_defaults.cpu_transcoder_mask =
>> +		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>> +	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
>> +		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
>> +};
>> +
>>  __diag_pop();
>>  
>>  #undef INTEL_VGA_DEVICE
>> @@ -795,6 +809,7 @@ static const struct {
>>  	const struct intel_display_device_info *display;
>>  } gmdid_display_map[] = {
>>  	{ 14,  0, &xe_lpdp_display },
>> +	{ 20,  0, &xe2_lpd_display },
>>  };
>>  
>>  static const struct intel_display_device_info *
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 07f79b1028e1..96ac9a9cc155 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>  #define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
>>  #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
>>  #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
>> +#define IS_LUNARLAKE(dev_priv)  0
>
> As noted on the previous patch, we might be able to drop this completely
> if we update the fake PCH and gmbus code to match on display IP.  Given
> that PCH isn't even involved in south display handling anymore, that
> seems like it might be reasonable?  If anything, we're more likely to
> need to match on PICA ID (which has its own GMD_ID register) than base
> platform at some point in the future.

And in any case it's out of place in this patch.

BR,
Jani.

>
>
> Matt
>
>>  
>>  #define IS_METEORLAKE_M(i915) \
>>  	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
>> -- 
>> 2.40.1
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [Intel-xe] [PATCH 17/42] drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL

[Jani Nikula]

On Wed, 23 Aug 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Display Ver 20 moved the D2D Enable bit to DDI_BUF_CTL(DDI_CTL_DE)
> register. We used multiple variables for HDMI and DisplayPort copies of
> this register. Consolidate the various locations to use
> intel_digital_port saved_port_bits.

All changes like this would be better off in two steps:

1) non-functional moving of the member to another struct

2) adding new stuff on top

The reason is two-fold: it's easier to review each step, and should a
bisect ever point at either of them regressing, it's easier to debug.


BR,
Jani.


>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 40 +++++++++++++-----------
>  drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
>  2 files changed, 22 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a9440c0ecf61..3147ed174d83 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -324,26 +324,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
>  				      const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
>  	/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
> -	intel_dp->DP = dig_port->saved_port_bits |
> +	dig_port->saved_port_bits |=
>  		DDI_PORT_WIDTH(crtc_state->lane_count) |
>  		DDI_BUF_TRANS_SELECT(0);
>  
>  	if (DISPLAY_VER(i915) >= 14) {
>  		if (intel_dp_is_uhbr(crtc_state))
> -			intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
> +			dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
>  		else
> -			intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
> +			dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
>  	}
>  
>  	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> -		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> +		dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
>  		if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> -			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> +			dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>  	}
>  }
>  
> @@ -1449,7 +1448,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
>  		      const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	int level = intel_ddi_level(encoder, crtc_state, 0);
>  	enum port port = encoder->port;
>  	u32 signal_levels;
> @@ -1466,10 +1465,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
>  	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
>  		    signal_levels);
>  
> -	intel_dp->DP &= ~DDI_BUF_EMP_MASK;
> -	intel_dp->DP |= signal_levels;
> +	dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
> +	dig_port->saved_port_bits |= signal_levels;
>  
> -	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> +	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>  	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>  }
>  
> @@ -2355,6 +2354,7 @@ static void
>  mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	enum port port = encoder->port;
>  	i915_reg_t reg;
>  	u32 set_bits, wait_bits;
> @@ -2362,6 +2362,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  	if (DISPLAY_VER(dev_priv) >= 20) {
>  		reg = DDI_BUF_CTL(port);
>  		set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> +		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
>  		reg = XELPDP_PORT_BUF_CTL1(port);
> @@ -2817,6 +2818,7 @@ static void
>  mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	enum port port = encoder->port;
>  	i915_reg_t reg;
>  	u32 clr_bits, wait_bits;
> @@ -2824,6 +2826,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  	if (DISPLAY_VER(dev_priv) >= 20) {
>  		reg = DDI_BUF_CTL(port);
>  		clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> +		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
>  		reg = XELPDP_PORT_BUF_CTL1(port);
> @@ -3162,7 +3165,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>  	struct drm_connector *connector = conn_state->connector;
>  	enum port port = encoder->port;
>  	enum phy phy = intel_port_to_phy(dev_priv, port);
> -	u32 buf_ctl;
>  
>  	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
>  					       crtc_state->hdmi_high_tmds_clock_ratio,
> @@ -3228,7 +3230,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>  	 * is filled with lane count, already set in the crtc_state.
>  	 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
>  	 */
> -	buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
> +	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
>  	if (DISPLAY_VER(dev_priv) >= 14) {
>  		u8  lane_count = mtl_get_port_width(crtc_state->lane_count);
>  		u32 port_buf = 0;
> @@ -3241,13 +3243,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>  		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
>  			     XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
>  
> -		buf_ctl |= DDI_PORT_WIDTH(lane_count);
> +		dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
>  	} else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
>  		drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
> -		buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> +		dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>  	}
>  
> -	intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
> +	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>  
>  	intel_wait_ddi_buf_active(dev_priv, port);
>  
> @@ -3465,8 +3467,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  	mtl_port_buf_ctl_program(encoder, crtc_state);
>  
>  	/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
> -	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> -	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> +	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> +	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>  	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>  
>  	/* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
> @@ -3516,8 +3518,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  	    (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
>  		adlp_tbt_to_dp_alt_switch_wa(encoder);
>  
> -	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> -	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> +	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> +	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>  	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>  
>  	intel_wait_ddi_buf_active(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 84584864511b..334789be0054 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5631,7 +5631,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  	intel_dp->pps.active_pipe = INVALID_PIPE;
>  
>  	/* Preserve the current hw state. */
> -	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
> +	dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
>  	intel_dp->attached_connector = intel_connector;
>  
>  	if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-xe] [PATCH 17/42] drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL

[Jani Nikula]

On Wed, 23 Aug 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Display Ver 20 moved the D2D Enable bit to DDI_BUF_CTL(DDI_CTL_DE)
> register. We used multiple variables for HDMI and DisplayPort copies of
> this register. Consolidate the various locations to use
> intel_digital_port saved_port_bits.

All changes like this would be better off in two steps:

1) non-functional moving of the member to another struct

2) adding new stuff on top

The reason is two-fold: it's easier to review each step, and should a
bisect ever point at either of them regressing, it's easier to debug.


BR,
Jani.


>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 40 +++++++++++++-----------
>  drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
>  2 files changed, 22 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a9440c0ecf61..3147ed174d83 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -324,26 +324,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
>  				      const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
>  	/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
> -	intel_dp->DP = dig_port->saved_port_bits |
> +	dig_port->saved_port_bits |=
>  		DDI_PORT_WIDTH(crtc_state->lane_count) |
>  		DDI_BUF_TRANS_SELECT(0);
>  
>  	if (DISPLAY_VER(i915) >= 14) {
>  		if (intel_dp_is_uhbr(crtc_state))
> -			intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
> +			dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
>  		else
> -			intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
> +			dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
>  	}
>  
>  	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> -		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> +		dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
>  		if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> -			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> +			dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>  	}
>  }
>  
> @@ -1449,7 +1448,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
>  		      const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	int level = intel_ddi_level(encoder, crtc_state, 0);
>  	enum port port = encoder->port;
>  	u32 signal_levels;
> @@ -1466,10 +1465,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
>  	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
>  		    signal_levels);
>  
> -	intel_dp->DP &= ~DDI_BUF_EMP_MASK;
> -	intel_dp->DP |= signal_levels;
> +	dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
> +	dig_port->saved_port_bits |= signal_levels;
>  
> -	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> +	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>  	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>  }
>  
> @@ -2355,6 +2354,7 @@ static void
>  mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	enum port port = encoder->port;
>  	i915_reg_t reg;
>  	u32 set_bits, wait_bits;
> @@ -2362,6 +2362,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  	if (DISPLAY_VER(dev_priv) >= 20) {
>  		reg = DDI_BUF_CTL(port);
>  		set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> +		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
>  		reg = XELPDP_PORT_BUF_CTL1(port);
> @@ -2817,6 +2818,7 @@ static void
>  mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	enum port port = encoder->port;
>  	i915_reg_t reg;
>  	u32 clr_bits, wait_bits;
> @@ -2824,6 +2826,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  	if (DISPLAY_VER(dev_priv) >= 20) {
>  		reg = DDI_BUF_CTL(port);
>  		clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> +		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
>  		reg = XELPDP_PORT_BUF_CTL1(port);
> @@ -3162,7 +3165,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>  	struct drm_connector *connector = conn_state->connector;
>  	enum port port = encoder->port;
>  	enum phy phy = intel_port_to_phy(dev_priv, port);
> -	u32 buf_ctl;
>  
>  	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
>  					       crtc_state->hdmi_high_tmds_clock_ratio,
> @@ -3228,7 +3230,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>  	 * is filled with lane count, already set in the crtc_state.
>  	 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
>  	 */
> -	buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
> +	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
>  	if (DISPLAY_VER(dev_priv) >= 14) {
>  		u8  lane_count = mtl_get_port_width(crtc_state->lane_count);
>  		u32 port_buf = 0;
> @@ -3241,13 +3243,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>  		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
>  			     XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
>  
> -		buf_ctl |= DDI_PORT_WIDTH(lane_count);
> +		dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
>  	} else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
>  		drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
> -		buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> +		dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>  	}
>  
> -	intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
> +	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>  
>  	intel_wait_ddi_buf_active(dev_priv, port);
>  
> @@ -3465,8 +3467,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  	mtl_port_buf_ctl_program(encoder, crtc_state);
>  
>  	/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
> -	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> -	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> +	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> +	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>  	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>  
>  	/* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
> @@ -3516,8 +3518,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  	    (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
>  		adlp_tbt_to_dp_alt_switch_wa(encoder);
>  
> -	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> -	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> +	dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> +	intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>  	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>  
>  	intel_wait_ddi_buf_active(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 84584864511b..334789be0054 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5631,7 +5631,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  	intel_dp->pps.active_pipe = INVALID_PIPE;
>  
>  	/* Preserve the current hw state. */
> -	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
> +	dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
>  	intel_dp->attached_connector = intel_connector;
>  
>  	if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [Intel-xe] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA

[Jani Nikula]

On Wed, 23 Aug 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index cb5d1be2ba19..4b5b9a97142d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -6,13 +6,15 @@
>  #ifndef __INTEL_CX0_PHY_REGS_H__
>  #define __INTEL_CX0_PHY_REGS_H__
>  
> +#include "i915_drv.h"

Please don't do this. Please don't add inline functions that depend on
i915_drv.h etc. being included from headers. This simple headers just
changed to including like half the headers in the entire driver. It's
that bad.

I think the main question is why does anything other than
intel_cx0_phy_regs.c need the helpers? It's probably the division
between that and intel_ddi.c that's wrong in the first place.

That's actually been one of the benefits of splitting the register
macros by area; you can tell what registers are used where, and
sometimes it gives bad code smells about stuff being accessed in the
wrong place.

BR,
Jani.


>  #include "i915_reg_defs.h"
> +#include "intel_display_limits.h"
>  
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A		0x64040
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B		0x64140
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1		0x16F240
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2		0x16F440
> -#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)		_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> @@ -27,7 +29,7 @@
>  #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
>  #define   XELPDP_PORT_M2P_ADDRESS_MASK			REG_GENMASK(11, 0)
>  #define   XELPDP_PORT_M2P_ADDRESS(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
> -#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)	_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> @@ -54,7 +56,7 @@
>  #define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104
>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1			0x16F200
>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2			0x16F400
> -#define XELPDP_PORT_BUF_CTL1(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL1(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -75,7 +77,7 @@
>  #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
>  #define   XELPDP_PORT_WIDTH(val)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
>  
> -#define XELPDP_PORT_BUF_CTL2(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL2(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -95,7 +97,7 @@
>  #define   XELPDP_POWER_STATE_READY_MASK			REG_GENMASK(7, 4)
>  #define   XELPDP_POWER_STATE_READY(val)			REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
>  
> -#define XELPDP_PORT_BUF_CTL3(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL3(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -114,7 +116,7 @@
>  #define _XELPDP_PORT_CLOCK_CTL_B			0x641E0
>  #define _XELPDP_PORT_CLOCK_CTL_USBC1			0x16F260
>  #define _XELPDP_PORT_CLOCK_CTL_USBC2			0x16F460
> -#define XELPDP_PORT_CLOCK_CTL(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_CLOCK_CTL(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_CLOCK_CTL_A, \
>  										 _XELPDP_PORT_CLOCK_CTL_B, \
>  										 _XELPDP_PORT_CLOCK_CTL_USBC1, \
> @@ -271,4 +273,61 @@
>  #define HDMI_DIV_MASK		REG_GENMASK16(2, 0)
>  #define HDMI_DIV(val)		REG_FIELD_PREP16(HDMI_DIV_MASK, val)
>  
> +/*
> + * All registers are in the same IP, with a single range.  However the registers
> + * for TC_PORT come first.
> + */
> +static inline enum port xe2lpd_port_idx(enum port port)
> +{
> +	return port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A;
> +}
> +
> +static inline i915_reg_t xelpdp_port_clock_ctl_reg(struct drm_i915_private *i915,
> +						   enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_CLOCK_CTL(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_CLOCK_CTL(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_buf_ctl3_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL3(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL3(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_buf_ctl2_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL2(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL2(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_buf_ctl1_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL1(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL1(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_m2p_msgbus_ctl_reg(struct drm_i915_private *i915,
> +							enum port port, int lane)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_M2P_MSGBUS_CTL(xe2lpd_port_idx(port), lane) :
> +		XELPDP_PORT_M2P_MSGBUS_CTL(port, lane);
> +}
> +
> +static inline i915_reg_t xelpdp_port_p2m_msgbus_status_reg(struct drm_i915_private *i915,
> +							   enum port port, int lane)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_P2M_MSGBUS_STATUS(xe2lpd_port_idx(port), lane) :
> +		XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane);
> +}
> +
>  #endif /* __INTEL_CX0_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3147ed174d83..3587ddc6d8ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -176,7 +176,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
>  	int ret;
>  
>  	/* FIXME: find out why Bspec's 100us timeout is too short */
> -	ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
> +	ret = wait_for_us((intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port)) &
>  			   XELPDP_PORT_BUF_PHY_IDLE), 10000);
>  	if (ret)
>  		drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
> @@ -224,7 +224,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
>  	}
>  
>  	if (DISPLAY_VER(dev_priv) >= 14)
> -		ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
> +		ret = _wait_for(!(intel_de_read(dev_priv,
> +						xelpdp_port_buf_ctl1_reg(dev_priv, port)) &
> +				  XELPDP_PORT_BUF_PHY_IDLE),
>  				timeout_us, 10, 10);
>  	else
>  		ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
> @@ -2365,7 +2367,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
> -		reg = XELPDP_PORT_BUF_CTL1(port);
> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>  		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>  	}
> @@ -2385,7 +2387,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>  	enum port port = encoder->port;
>  	u32 val;
>  
> -	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
> +	val = intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port));
>  	val &= ~XELPDP_PORT_WIDTH_MASK;
>  	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
>  
> @@ -2398,7 +2400,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>  	if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
>  		val |= XELPDP_PORT_REVERSAL;
>  
> -	intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
> +	intel_de_write(i915, xelpdp_port_buf_ctl1_reg(i915, port), val);
>  }
>  
>  static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
> @@ -2409,7 +2411,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>  
>  	val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
>  	      XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
>  		     XELPDP_PORT_BUF_IO_SELECT_TBT, val);
>  }
>  
> @@ -2829,7 +2831,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
> -		reg = XELPDP_PORT_BUF_CTL1(port);
> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>  		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>  	}
> @@ -2967,7 +2969,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>  
>  	/* De-select Thunderbolt */
>  	if (DISPLAY_VER(dev_priv) >= 14)
> -		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
> +		intel_de_rmw(dev_priv, xelpdp_port_buf_ctl1_reg(dev_priv, encoder->port),
>  			     XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-xe] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA

[Jani Nikula]

On Wed, 23 Aug 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index cb5d1be2ba19..4b5b9a97142d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -6,13 +6,15 @@
>  #ifndef __INTEL_CX0_PHY_REGS_H__
>  #define __INTEL_CX0_PHY_REGS_H__
>  
> +#include "i915_drv.h"

Please don't do this. Please don't add inline functions that depend on
i915_drv.h etc. being included from headers. This simple headers just
changed to including like half the headers in the entire driver. It's
that bad.

I think the main question is why does anything other than
intel_cx0_phy_regs.c need the helpers? It's probably the division
between that and intel_ddi.c that's wrong in the first place.

That's actually been one of the benefits of splitting the register
macros by area; you can tell what registers are used where, and
sometimes it gives bad code smells about stuff being accessed in the
wrong place.

BR,
Jani.


>  #include "i915_reg_defs.h"
> +#include "intel_display_limits.h"
>  
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A		0x64040
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B		0x64140
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1		0x16F240
>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2		0x16F440
> -#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)		_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> @@ -27,7 +29,7 @@
>  #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
>  #define   XELPDP_PORT_M2P_ADDRESS_MASK			REG_GENMASK(11, 0)
>  #define   XELPDP_PORT_M2P_ADDRESS(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
> -#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)	_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> @@ -54,7 +56,7 @@
>  #define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104
>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1			0x16F200
>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2			0x16F400
> -#define XELPDP_PORT_BUF_CTL1(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL1(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -75,7 +77,7 @@
>  #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
>  #define   XELPDP_PORT_WIDTH(val)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
>  
> -#define XELPDP_PORT_BUF_CTL2(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL2(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -95,7 +97,7 @@
>  #define   XELPDP_POWER_STATE_READY_MASK			REG_GENMASK(7, 4)
>  #define   XELPDP_POWER_STATE_READY(val)			REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
>  
> -#define XELPDP_PORT_BUF_CTL3(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_BUF_CTL3(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> @@ -114,7 +116,7 @@
>  #define _XELPDP_PORT_CLOCK_CTL_B			0x641E0
>  #define _XELPDP_PORT_CLOCK_CTL_USBC1			0x16F260
>  #define _XELPDP_PORT_CLOCK_CTL_USBC2			0x16F460
> -#define XELPDP_PORT_CLOCK_CTL(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define XELPDP_PORT_CLOCK_CTL(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_CLOCK_CTL_A, \
>  										 _XELPDP_PORT_CLOCK_CTL_B, \
>  										 _XELPDP_PORT_CLOCK_CTL_USBC1, \
> @@ -271,4 +273,61 @@
>  #define HDMI_DIV_MASK		REG_GENMASK16(2, 0)
>  #define HDMI_DIV(val)		REG_FIELD_PREP16(HDMI_DIV_MASK, val)
>  
> +/*
> + * All registers are in the same IP, with a single range.  However the registers
> + * for TC_PORT come first.
> + */
> +static inline enum port xe2lpd_port_idx(enum port port)
> +{
> +	return port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A;
> +}
> +
> +static inline i915_reg_t xelpdp_port_clock_ctl_reg(struct drm_i915_private *i915,
> +						   enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_CLOCK_CTL(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_CLOCK_CTL(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_buf_ctl3_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL3(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL3(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_buf_ctl2_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL2(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL2(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_buf_ctl1_reg(struct drm_i915_private *i915,
> +						  enum port port)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_BUF_CTL1(xe2lpd_port_idx(port)) :
> +		XELPDP_PORT_BUF_CTL1(port);
> +}
> +
> +static inline i915_reg_t xelpdp_port_m2p_msgbus_ctl_reg(struct drm_i915_private *i915,
> +							enum port port, int lane)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_M2P_MSGBUS_CTL(xe2lpd_port_idx(port), lane) :
> +		XELPDP_PORT_M2P_MSGBUS_CTL(port, lane);
> +}
> +
> +static inline i915_reg_t xelpdp_port_p2m_msgbus_status_reg(struct drm_i915_private *i915,
> +							   enum port port, int lane)
> +{
> +	return DISPLAY_VER(i915) >= 20 ?
> +		XELPDP_PORT_P2M_MSGBUS_STATUS(xe2lpd_port_idx(port), lane) :
> +		XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane);
> +}
> +
>  #endif /* __INTEL_CX0_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3147ed174d83..3587ddc6d8ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -176,7 +176,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
>  	int ret;
>  
>  	/* FIXME: find out why Bspec's 100us timeout is too short */
> -	ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
> +	ret = wait_for_us((intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port)) &
>  			   XELPDP_PORT_BUF_PHY_IDLE), 10000);
>  	if (ret)
>  		drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
> @@ -224,7 +224,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
>  	}
>  
>  	if (DISPLAY_VER(dev_priv) >= 14)
> -		ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
> +		ret = _wait_for(!(intel_de_read(dev_priv,
> +						xelpdp_port_buf_ctl1_reg(dev_priv, port)) &
> +				  XELPDP_PORT_BUF_PHY_IDLE),
>  				timeout_us, 10, 10);
>  	else
>  		ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
> @@ -2365,7 +2367,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
> -		reg = XELPDP_PORT_BUF_CTL1(port);
> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>  		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>  	}
> @@ -2385,7 +2387,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>  	enum port port = encoder->port;
>  	u32 val;
>  
> -	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
> +	val = intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port));
>  	val &= ~XELPDP_PORT_WIDTH_MASK;
>  	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
>  
> @@ -2398,7 +2400,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>  	if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
>  		val |= XELPDP_PORT_REVERSAL;
>  
> -	intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
> +	intel_de_write(i915, xelpdp_port_buf_ctl1_reg(i915, port), val);
>  }
>  
>  static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
> @@ -2409,7 +2411,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>  
>  	val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
>  	      XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
> +	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
>  		     XELPDP_PORT_BUF_IO_SELECT_TBT, val);
>  }
>  
> @@ -2829,7 +2831,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>  	} else {
> -		reg = XELPDP_PORT_BUF_CTL1(port);
> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>  		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>  	}
> @@ -2967,7 +2969,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>  
>  	/* De-select Thunderbolt */
>  	if (DISPLAY_VER(dev_priv) >= 14)
> -		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
> +		intel_de_rmw(dev_priv, xelpdp_port_buf_ctl1_reg(dev_priv, encoder->port),
>  			     XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [Intel-xe] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA

[Lucas De Marchi]

On Thu, Aug 24, 2023 at 11:34:59AM +0300, Jani Nikula wrote:
>On Wed, 23 Aug 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>> index cb5d1be2ba19..4b5b9a97142d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>> @@ -6,13 +6,15 @@
>>  #ifndef __INTEL_CX0_PHY_REGS_H__
>>  #define __INTEL_CX0_PHY_REGS_H__
>>
>> +#include "i915_drv.h"
>
>Please don't do this. Please don't add inline functions that depend on
>i915_drv.h etc. being included from headers. This simple headers just
>changed to including like half the headers in the entire driver. It's
>that bad.
>
>I think the main question is why does anything other than
>intel_cx0_phy_regs.c need the helpers? It's probably the division
>between that and intel_ddi.c that's wrong in the first place.

because on platform N-1 the register was on DDI and on platform N it
moved to the phy. So how would the divide be?

Lucas De Marchi

>
>That's actually been one of the benefits of splitting the register
>macros by area; you can tell what registers are used where, and
>sometimes it gives bad code smells about stuff being accessed in the
>wrong place.
>
>BR,
>Jani.
>
>
>>  #include "i915_reg_defs.h"
>> +#include "intel_display_limits.h"
>>
>>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A		0x64040
>>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B		0x64140
>>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1		0x16F240
>>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2		0x16F440
>> -#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)		_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
>> @@ -27,7 +29,7 @@
>>  #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
>>  #define   XELPDP_PORT_M2P_ADDRESS_MASK			REG_GENMASK(11, 0)
>>  #define   XELPDP_PORT_M2P_ADDRESS(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
>> -#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)	_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
>> @@ -54,7 +56,7 @@
>>  #define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104
>>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1			0x16F200
>>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2			0x16F400
>> -#define XELPDP_PORT_BUF_CTL1(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_BUF_CTL1(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
>> @@ -75,7 +77,7 @@
>>  #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
>>  #define   XELPDP_PORT_WIDTH(val)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
>>
>> -#define XELPDP_PORT_BUF_CTL2(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_BUF_CTL2(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
>> @@ -95,7 +97,7 @@
>>  #define   XELPDP_POWER_STATE_READY_MASK			REG_GENMASK(7, 4)
>>  #define   XELPDP_POWER_STATE_READY(val)			REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
>>
>> -#define XELPDP_PORT_BUF_CTL3(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_BUF_CTL3(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
>> @@ -114,7 +116,7 @@
>>  #define _XELPDP_PORT_CLOCK_CTL_B			0x641E0
>>  #define _XELPDP_PORT_CLOCK_CTL_USBC1			0x16F260
>>  #define _XELPDP_PORT_CLOCK_CTL_USBC2			0x16F460
>> -#define XELPDP_PORT_CLOCK_CTL(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_CLOCK_CTL(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_CLOCK_CTL_A, \
>>  										 _XELPDP_PORT_CLOCK_CTL_B, \
>>  										 _XELPDP_PORT_CLOCK_CTL_USBC1, \
>> @@ -271,4 +273,61 @@
>>  #define HDMI_DIV_MASK		REG_GENMASK16(2, 0)
>>  #define HDMI_DIV(val)		REG_FIELD_PREP16(HDMI_DIV_MASK, val)
>>
>> +/*
>> + * All registers are in the same IP, with a single range.  However the registers
>> + * for TC_PORT come first.
>> + */
>> +static inline enum port xe2lpd_port_idx(enum port port)
>> +{
>> +	return port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A;
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_clock_ctl_reg(struct drm_i915_private *i915,
>> +						   enum port port)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_CLOCK_CTL(xe2lpd_port_idx(port)) :
>> +		XELPDP_PORT_CLOCK_CTL(port);
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_buf_ctl3_reg(struct drm_i915_private *i915,
>> +						  enum port port)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_BUF_CTL3(xe2lpd_port_idx(port)) :
>> +		XELPDP_PORT_BUF_CTL3(port);
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_buf_ctl2_reg(struct drm_i915_private *i915,
>> +						  enum port port)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_BUF_CTL2(xe2lpd_port_idx(port)) :
>> +		XELPDP_PORT_BUF_CTL2(port);
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_buf_ctl1_reg(struct drm_i915_private *i915,
>> +						  enum port port)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_BUF_CTL1(xe2lpd_port_idx(port)) :
>> +		XELPDP_PORT_BUF_CTL1(port);
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_m2p_msgbus_ctl_reg(struct drm_i915_private *i915,
>> +							enum port port, int lane)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_M2P_MSGBUS_CTL(xe2lpd_port_idx(port), lane) :
>> +		XELPDP_PORT_M2P_MSGBUS_CTL(port, lane);
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_p2m_msgbus_status_reg(struct drm_i915_private *i915,
>> +							   enum port port, int lane)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_P2M_MSGBUS_STATUS(xe2lpd_port_idx(port), lane) :
>> +		XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane);
>> +}
>> +
>>  #endif /* __INTEL_CX0_REG_DEFS_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 3147ed174d83..3587ddc6d8ed 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -176,7 +176,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
>>  	int ret;
>>
>>  	/* FIXME: find out why Bspec's 100us timeout is too short */
>> -	ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
>> +	ret = wait_for_us((intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port)) &
>>  			   XELPDP_PORT_BUF_PHY_IDLE), 10000);
>>  	if (ret)
>>  		drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
>> @@ -224,7 +224,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
>>  	}
>>
>>  	if (DISPLAY_VER(dev_priv) >= 14)
>> -		ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
>> +		ret = _wait_for(!(intel_de_read(dev_priv,
>> +						xelpdp_port_buf_ctl1_reg(dev_priv, port)) &
>> +				  XELPDP_PORT_BUF_PHY_IDLE),
>>  				timeout_us, 10, 10);
>>  	else
>>  		ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
>> @@ -2365,7 +2367,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>>  		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>>  	} else {
>> -		reg = XELPDP_PORT_BUF_CTL1(port);
>> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>>  		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>>  	}
>> @@ -2385,7 +2387,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>>  	enum port port = encoder->port;
>>  	u32 val;
>>
>> -	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
>> +	val = intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port));
>>  	val &= ~XELPDP_PORT_WIDTH_MASK;
>>  	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
>>
>> @@ -2398,7 +2400,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>>  	if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
>>  		val |= XELPDP_PORT_REVERSAL;
>>
>> -	intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
>> +	intel_de_write(i915, xelpdp_port_buf_ctl1_reg(i915, port), val);
>>  }
>>
>>  static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>> @@ -2409,7 +2411,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>>
>>  	val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
>>  	      XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
>> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
>> +	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
>>  		     XELPDP_PORT_BUF_IO_SELECT_TBT, val);
>>  }
>>
>> @@ -2829,7 +2831,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>>  		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>>  	} else {
>> -		reg = XELPDP_PORT_BUF_CTL1(port);
>> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>>  		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>>  	}
>> @@ -2967,7 +2969,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>>
>>  	/* De-select Thunderbolt */
>>  	if (DISPLAY_VER(dev_priv) >= 14)
>> -		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
>> +		intel_de_rmw(dev_priv, xelpdp_port_buf_ctl1_reg(dev_priv, encoder->port),
>>  			     XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
>>  }
>
>-- 
>Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-xe] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA

[Lucas De Marchi]

On Thu, Aug 24, 2023 at 11:34:59AM +0300, Jani Nikula wrote:
>On Wed, 23 Aug 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>> index cb5d1be2ba19..4b5b9a97142d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>> @@ -6,13 +6,15 @@
>>  #ifndef __INTEL_CX0_PHY_REGS_H__
>>  #define __INTEL_CX0_PHY_REGS_H__
>>
>> +#include "i915_drv.h"
>
>Please don't do this. Please don't add inline functions that depend on
>i915_drv.h etc. being included from headers. This simple headers just
>changed to including like half the headers in the entire driver. It's
>that bad.
>
>I think the main question is why does anything other than
>intel_cx0_phy_regs.c need the helpers? It's probably the division
>between that and intel_ddi.c that's wrong in the first place.

because on platform N-1 the register was on DDI and on platform N it
moved to the phy. So how would the divide be?

Lucas De Marchi

>
>That's actually been one of the benefits of splitting the register
>macros by area; you can tell what registers are used where, and
>sometimes it gives bad code smells about stuff being accessed in the
>wrong place.
>
>BR,
>Jani.
>
>
>>  #include "i915_reg_defs.h"
>> +#include "intel_display_limits.h"
>>
>>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A		0x64040
>>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B		0x64140
>>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1		0x16F240
>>  #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2		0x16F440
>> -#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)		_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
>> @@ -27,7 +29,7 @@
>>  #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
>>  #define   XELPDP_PORT_M2P_ADDRESS_MASK			REG_GENMASK(11, 0)
>>  #define   XELPDP_PORT_M2P_ADDRESS(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
>> -#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)	_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>>  										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
>> @@ -54,7 +56,7 @@
>>  #define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104
>>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1			0x16F200
>>  #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2			0x16F400
>> -#define XELPDP_PORT_BUF_CTL1(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_BUF_CTL1(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
>> @@ -75,7 +77,7 @@
>>  #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
>>  #define   XELPDP_PORT_WIDTH(val)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
>>
>> -#define XELPDP_PORT_BUF_CTL2(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_BUF_CTL2(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
>> @@ -95,7 +97,7 @@
>>  #define   XELPDP_POWER_STATE_READY_MASK			REG_GENMASK(7, 4)
>>  #define   XELPDP_POWER_STATE_READY(val)			REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
>>
>> -#define XELPDP_PORT_BUF_CTL3(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_BUF_CTL3(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
>>  										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
>> @@ -114,7 +116,7 @@
>>  #define _XELPDP_PORT_CLOCK_CTL_B			0x641E0
>>  #define _XELPDP_PORT_CLOCK_CTL_USBC1			0x16F260
>>  #define _XELPDP_PORT_CLOCK_CTL_USBC2			0x16F460
>> -#define XELPDP_PORT_CLOCK_CTL(port)			_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>> +#define XELPDP_PORT_CLOCK_CTL(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>  										 _XELPDP_PORT_CLOCK_CTL_A, \
>>  										 _XELPDP_PORT_CLOCK_CTL_B, \
>>  										 _XELPDP_PORT_CLOCK_CTL_USBC1, \
>> @@ -271,4 +273,61 @@
>>  #define HDMI_DIV_MASK		REG_GENMASK16(2, 0)
>>  #define HDMI_DIV(val)		REG_FIELD_PREP16(HDMI_DIV_MASK, val)
>>
>> +/*
>> + * All registers are in the same IP, with a single range.  However the registers
>> + * for TC_PORT come first.
>> + */
>> +static inline enum port xe2lpd_port_idx(enum port port)
>> +{
>> +	return port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A;
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_clock_ctl_reg(struct drm_i915_private *i915,
>> +						   enum port port)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_CLOCK_CTL(xe2lpd_port_idx(port)) :
>> +		XELPDP_PORT_CLOCK_CTL(port);
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_buf_ctl3_reg(struct drm_i915_private *i915,
>> +						  enum port port)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_BUF_CTL3(xe2lpd_port_idx(port)) :
>> +		XELPDP_PORT_BUF_CTL3(port);
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_buf_ctl2_reg(struct drm_i915_private *i915,
>> +						  enum port port)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_BUF_CTL2(xe2lpd_port_idx(port)) :
>> +		XELPDP_PORT_BUF_CTL2(port);
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_buf_ctl1_reg(struct drm_i915_private *i915,
>> +						  enum port port)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_BUF_CTL1(xe2lpd_port_idx(port)) :
>> +		XELPDP_PORT_BUF_CTL1(port);
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_m2p_msgbus_ctl_reg(struct drm_i915_private *i915,
>> +							enum port port, int lane)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_M2P_MSGBUS_CTL(xe2lpd_port_idx(port), lane) :
>> +		XELPDP_PORT_M2P_MSGBUS_CTL(port, lane);
>> +}
>> +
>> +static inline i915_reg_t xelpdp_port_p2m_msgbus_status_reg(struct drm_i915_private *i915,
>> +							   enum port port, int lane)
>> +{
>> +	return DISPLAY_VER(i915) >= 20 ?
>> +		XELPDP_PORT_P2M_MSGBUS_STATUS(xe2lpd_port_idx(port), lane) :
>> +		XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane);
>> +}
>> +
>>  #endif /* __INTEL_CX0_REG_DEFS_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 3147ed174d83..3587ddc6d8ed 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -176,7 +176,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
>>  	int ret;
>>
>>  	/* FIXME: find out why Bspec's 100us timeout is too short */
>> -	ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
>> +	ret = wait_for_us((intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port)) &
>>  			   XELPDP_PORT_BUF_PHY_IDLE), 10000);
>>  	if (ret)
>>  		drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
>> @@ -224,7 +224,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
>>  	}
>>
>>  	if (DISPLAY_VER(dev_priv) >= 14)
>> -		ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
>> +		ret = _wait_for(!(intel_de_read(dev_priv,
>> +						xelpdp_port_buf_ctl1_reg(dev_priv, port)) &
>> +				  XELPDP_PORT_BUF_PHY_IDLE),
>>  				timeout_us, 10, 10);
>>  	else
>>  		ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
>> @@ -2365,7 +2367,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>>  		dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>>  	} else {
>> -		reg = XELPDP_PORT_BUF_CTL1(port);
>> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>>  		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>>  	}
>> @@ -2385,7 +2387,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>>  	enum port port = encoder->port;
>>  	u32 val;
>>
>> -	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
>> +	val = intel_de_read(i915, xelpdp_port_buf_ctl1_reg(i915, port));
>>  	val &= ~XELPDP_PORT_WIDTH_MASK;
>>  	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
>>
>> @@ -2398,7 +2400,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>>  	if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
>>  		val |= XELPDP_PORT_REVERSAL;
>>
>> -	intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
>> +	intel_de_write(i915, xelpdp_port_buf_ctl1_reg(i915, port), val);
>>  }
>>
>>  static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>> @@ -2409,7 +2411,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>>
>>  	val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
>>  	      XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
>> -	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
>> +	intel_de_rmw(i915, xelpdp_port_buf_ctl1_reg(i915, encoder->port),
>>  		     XELPDP_PORT_BUF_IO_SELECT_TBT, val);
>>  }
>>
>> @@ -2829,7 +2831,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>>  		dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>>  		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
>>  	} else {
>> -		reg = XELPDP_PORT_BUF_CTL1(port);
>> +		reg = xelpdp_port_buf_ctl1_reg(dev_priv, port);
>>  		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
>>  		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
>>  	}
>> @@ -2967,7 +2969,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>>
>>  	/* De-select Thunderbolt */
>>  	if (DISPLAY_VER(dev_priv) >= 14)
>> -		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
>> +		intel_de_rmw(dev_priv, xelpdp_port_buf_ctl1_reg(dev_priv, encoder->port),
>>  			     XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
>>  }
>
>-- 
>Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

[Coelho, Luciano]

On Thu, 2023-08-24 at 05:43 +0000, Kandpal, Suraj wrote:
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> > De Marchi
> > Sent: Wednesday, August 23, 2023 10:37 PM
> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Coelho, Luciano <luciano.coelho@intel.com>
> > Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the
> > main _max_lane_count() func
> > 
> > From: Luca Coelho <luciano.coelho@intel.com>
> > 
> > This makes the code a bit more symmetric and readable, especially when we
> > start adding more display version-specific alternatives.
> > 
> > Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> > Link: https://lore.kernel.org/r/20230721111121.369227-4-
> > luciano.coelho@intel.com
> > ---
> >  drivers/gpu/drm/i915/display/intel_tc.c | 32 +++++++++++++++----------
> >  1 file changed, 19 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index de848b329f4b..43b8eeba26f8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -311,23 +311,12 @@ static int mtl_tc_port_get_max_lane_count(struct
> > intel_digital_port *dig_port)
> >  	}
> >  }
> > 
> > -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> > +static int intel_tc_port_get_max_lane_count(struct intel_digital_port
> > +*dig_port)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > -	struct intel_tc_port *tc = to_tc_port(dig_port);
> > -	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> >  	intel_wakeref_t wakeref;
> > -	u32 lane_mask;
> > -
> > -	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> > -		return 4;
> > +	u32 lane_mask = 0;
> > 
> > -	assert_tc_cold_blocked(tc);
> > -
> > -	if (DISPLAY_VER(i915) >= 14)
> > -		return mtl_tc_port_get_max_lane_count(dig_port);
> > -
> > -	lane_mask = 0;
> >  	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE,
> > wakeref)
> >  		lane_mask = intel_tc_port_get_lane_mask(dig_port);
> > 
> > @@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct
> > intel_digital_port *dig_port)
> >  	}
> >  }
> 
> Rather than having two functions:
> mtl_tc_port_get_max_lane_count()
> & intel_tc_port_get_max_lane_count() that both call:
> with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
>                 lane_mask = intel_tc_port_get_lane_mask(dig_port);
> to get the lane mask the us directly pass the lane_mask to the above two functions
> and make the call for getting the lane_mask common i.e lets call it in 
> intel_tc_port_fia_max_lane_count().

As I wrote in reply to your previous comment, this changes later, when
we add the special case for LNL.  So I don't think it will help much to
combine this call into a single function.  IMHO it's cleaner to have
them all cleanly separated in different functions, for readability. 
The compiler will certainly optimize all this in its own ways anyway.

Do you agree?

--
Cheers,
Luca.

Re: [Intel-xe] [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

[Coelho, Luciano]

On Thu, 2023-08-24 at 05:43 +0000, Kandpal, Suraj wrote:
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> > De Marchi
> > Sent: Wednesday, August 23, 2023 10:37 PM
> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Coelho, Luciano <luciano.coelho@intel.com>
> > Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the
> > main _max_lane_count() func
> > 
> > From: Luca Coelho <luciano.coelho@intel.com>
> > 
> > This makes the code a bit more symmetric and readable, especially when we
> > start adding more display version-specific alternatives.
> > 
> > Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> > Link: https://lore.kernel.org/r/20230721111121.369227-4-
> > luciano.coelho@intel.com
> > ---
> >  drivers/gpu/drm/i915/display/intel_tc.c | 32 +++++++++++++++----------
> >  1 file changed, 19 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index de848b329f4b..43b8eeba26f8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -311,23 +311,12 @@ static int mtl_tc_port_get_max_lane_count(struct
> > intel_digital_port *dig_port)
> >  	}
> >  }
> > 
> > -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> > +static int intel_tc_port_get_max_lane_count(struct intel_digital_port
> > +*dig_port)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > -	struct intel_tc_port *tc = to_tc_port(dig_port);
> > -	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> >  	intel_wakeref_t wakeref;
> > -	u32 lane_mask;
> > -
> > -	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> > -		return 4;
> > +	u32 lane_mask = 0;
> > 
> > -	assert_tc_cold_blocked(tc);
> > -
> > -	if (DISPLAY_VER(i915) >= 14)
> > -		return mtl_tc_port_get_max_lane_count(dig_port);
> > -
> > -	lane_mask = 0;
> >  	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE,
> > wakeref)
> >  		lane_mask = intel_tc_port_get_lane_mask(dig_port);
> > 
> > @@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct
> > intel_digital_port *dig_port)
> >  	}
> >  }
> 
> Rather than having two functions:
> mtl_tc_port_get_max_lane_count()
> & intel_tc_port_get_max_lane_count() that both call:
> with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
>                 lane_mask = intel_tc_port_get_lane_mask(dig_port);
> to get the lane mask the us directly pass the lane_mask to the above two functions
> and make the call for getting the lane_mask common i.e lets call it in 
> intel_tc_port_fia_max_lane_count().

As I wrote in reply to your previous comment, this changes later, when
we add the special case for LNL.  So I don't think it will help much to
combine this call into a single function.  IMHO it's cleaner to have
them all cleanly separated in different functions, for readability. 
The compiler will certainly optimize all this in its own ways anyway.

Do you agree?

--
Cheers,
Luca.

Re: [Intel-gfx] [Intel-xe] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

[Coelho, Luciano]

On Wed, 2023-08-23 at 13:28 -0700, Matt Roper wrote:
> On Wed, Aug 23, 2023 at 10:07:25AM -0700, Lucas De Marchi wrote:
> > From: Luca Coelho <luciano.coelho@intel.com>
> > 
> > Starting from display version 20, we need to read the pin assignment
> > from the IOM TCSS_DDI_STATUS register instead of reading it from the
> > FIA.
> > 
> > We use the pin assignment to decide the maximum lane count.  So, to
> > support this change, add a new lnl_tc_port_get_max_lane_count() function
> > that reads from the TCSS_DDI_STATUS register and decides the maximum
> > lane count based on that.
> > 
> > BSpec: 69594
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/i915_reg.h         |  1 +
> >  2 files changed, 29 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 3c94bbcb5497..37b0f8529b4f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> >  	       DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
> >  }
> >  
> > +static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > +	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> > +	intel_wakeref_t wakeref;
> > +	u32 val, pin_assignment;
> > +
> > +	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> 
> Do we need this?  I don't think POWER_DOMAIN_DISPLAY_CORE has been tied
> to any power wells since VLV/CHV.
> 
> Hmm, it looks like we actually grab it (and even assert it) in a bunch of
> places on modern platforms that don't make sense to me since it isn't
> tied to anything.
> 
> I guess leaving this here doesn't hurt anything, although we might want
> to go back and take another look at this in the future.
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Thanks, Matt! You have a good point, but as you said, maybe this should
be revisited in all occurrences and changed in one go.  I just kept it
consistent with other usage.

--
Cheers,
Luca.

Re: [Intel-xe] [Intel-gfx] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

[Coelho, Luciano]

On Wed, 2023-08-23 at 13:28 -0700, Matt Roper wrote:
> On Wed, Aug 23, 2023 at 10:07:25AM -0700, Lucas De Marchi wrote:
> > From: Luca Coelho <luciano.coelho@intel.com>
> > 
> > Starting from display version 20, we need to read the pin assignment
> > from the IOM TCSS_DDI_STATUS register instead of reading it from the
> > FIA.
> > 
> > We use the pin assignment to decide the maximum lane count.  So, to
> > support this change, add a new lnl_tc_port_get_max_lane_count() function
> > that reads from the TCSS_DDI_STATUS register and decides the maximum
> > lane count based on that.
> > 
> > BSpec: 69594
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/i915_reg.h         |  1 +
> >  2 files changed, 29 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 3c94bbcb5497..37b0f8529b4f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> >  	       DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
> >  }
> >  
> > +static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > +	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> > +	intel_wakeref_t wakeref;
> > +	u32 val, pin_assignment;
> > +
> > +	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> 
> Do we need this?  I don't think POWER_DOMAIN_DISPLAY_CORE has been tied
> to any power wells since VLV/CHV.
> 
> Hmm, it looks like we actually grab it (and even assert it) in a bunch of
> places on modern platforms that don't make sense to me since it isn't
> tied to anything.
> 
> I guess leaving this here doesn't hurt anything, although we might want
> to go back and take another look at this in the future.
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Thanks, Matt! You have a good point, but as you said, maybe this should
be revisited in all occurrences and changed in one go.  I just kept it
consistent with other usage.

--
Cheers,
Luca.

Re: [Intel-gfx] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

[Coelho, Luciano]

On Wed, 2023-08-23 at 10:07 -0700, Lucas De Marchi wrote:
> From: Luca Coelho <luciano.coelho@intel.com>
> 
> Starting from display version 20, we need to read the pin assignment
> from the IOM TCSS_DDI_STATUS register instead of reading it from the
> FIA.
> 
> We use the pin assignment to decide the maximum lane count.  So, to
> support this change, add a new lnl_tc_port_get_max_lane_count() function
> that reads from the TCSS_DDI_STATUS register and decides the maximum
> lane count based on that.
> 
> BSpec: 69594
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---

Lucas, do you want me to send this together with my patchset with the
preparation for this?

In a way, the 4 patches I sent out can be applied independently of LNL-
related changes, so maybe I could resend just those 4 patches and you
base your entire series on top of my patches after they get applied?
Then this patch, which is really related to LNL could be part of your
series...

Let me know what you prefer.

--
Cheers,
Luca.

Re: [Intel-xe] [Intel-gfx] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

[Coelho, Luciano]

On Wed, 2023-08-23 at 10:07 -0700, Lucas De Marchi wrote:
> From: Luca Coelho <luciano.coelho@intel.com>
> 
> Starting from display version 20, we need to read the pin assignment
> from the IOM TCSS_DDI_STATUS register instead of reading it from the
> FIA.
> 
> We use the pin assignment to decide the maximum lane count.  So, to
> support this change, add a new lnl_tc_port_get_max_lane_count() function
> that reads from the TCSS_DDI_STATUS register and decides the maximum
> lane count based on that.
> 
> BSpec: 69594
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---

Lucas, do you want me to send this together with my patchset with the
preparation for this?

In a way, the 4 patches I sent out can be applied independently of LNL-
related changes, so maybe I could resend just those 4 patches and you
base your entire series on top of my patches after they get applied?
Then this patch, which is really related to LNL could be part of your
series...

Let me know what you prefer.

--
Cheers,
Luca.

Re: [Intel-gfx] [Intel-xe] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

[Lucas De Marchi]

On Thu, Aug 24, 2023 at 11:34:22AM +0000, Coelho, Luciano wrote:
>On Wed, 2023-08-23 at 10:07 -0700, Lucas De Marchi wrote:
>> From: Luca Coelho <luciano.coelho@intel.com>
>>
>> Starting from display version 20, we need to read the pin assignment
>> from the IOM TCSS_DDI_STATUS register instead of reading it from the
>> FIA.
>>
>> We use the pin assignment to decide the maximum lane count.  So, to
>> support this change, add a new lnl_tc_port_get_max_lane_count() function
>> that reads from the TCSS_DDI_STATUS register and decides the maximum
>> lane count based on that.
>>
>> BSpec: 69594
>> Cc: Mika Kahola <mika.kahola@intel.com>
>> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>
>Lucas, do you want me to send this together with my patchset with the
>preparation for this?
>
>In a way, the 4 patches I sent out can be applied independently of LNL-
>related changes, so maybe I could resend just those 4 patches and you
>base your entire series on top of my patches after they get applied?
>Then this patch, which is really related to LNL could be part of your
>series...

Please get the first 4 patches applied. I can keep this one in this
series. Pasting from the cover letter to make clear we are on the same
page:

         3. Patches 7 through 10 can also be ignored: they are not
            applied yet, but being reviewed in other patch series by its
            author[2].

	[2] https://patchwork.freedesktop.org/series/120980/

The only reason I added them here is that since this series will take
some time to be applied, I figured it would be better not to create
unnecessary conflicts.

thanks
Lucas De Marchi

>
>Let me know what you prefer.
>
>--
>Cheers,
>Luca.

Re: [Intel-xe] [Intel-gfx] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

[Lucas De Marchi]

On Thu, Aug 24, 2023 at 11:34:22AM +0000, Coelho, Luciano wrote:
>On Wed, 2023-08-23 at 10:07 -0700, Lucas De Marchi wrote:
>> From: Luca Coelho <luciano.coelho@intel.com>
>>
>> Starting from display version 20, we need to read the pin assignment
>> from the IOM TCSS_DDI_STATUS register instead of reading it from the
>> FIA.
>>
>> We use the pin assignment to decide the maximum lane count.  So, to
>> support this change, add a new lnl_tc_port_get_max_lane_count() function
>> that reads from the TCSS_DDI_STATUS register and decides the maximum
>> lane count based on that.
>>
>> BSpec: 69594
>> Cc: Mika Kahola <mika.kahola@intel.com>
>> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>
>Lucas, do you want me to send this together with my patchset with the
>preparation for this?
>
>In a way, the 4 patches I sent out can be applied independently of LNL-
>related changes, so maybe I could resend just those 4 patches and you
>base your entire series on top of my patches after they get applied?
>Then this patch, which is really related to LNL could be part of your
>series...

Please get the first 4 patches applied. I can keep this one in this
series. Pasting from the cover letter to make clear we are on the same
page:

         3. Patches 7 through 10 can also be ignored: they are not
            applied yet, but being reviewed in other patch series by its
            author[2].

	[2] https://patchwork.freedesktop.org/series/120980/

The only reason I added them here is that since this series will take
some time to be applied, I figured it would be better not to create
unnecessary conflicts.

thanks
Lucas De Marchi

>
>Let me know what you prefer.
>
>--
>Cheers,
>Luca.

Re: [Intel-gfx] [Intel-xe] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

[Lucas De Marchi]

Hi Suraj,

On Thu, Aug 24, 2023 at 05:43:15AM +0000, Kandpal, Suraj wrote:
>
>
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
>> De Marchi
>> Sent: Wednesday, August 23, 2023 10:37 PM
>> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> Cc: Coelho, Luciano <luciano.coelho@intel.com>
>> Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the
>> main _max_lane_count() func
>>
>> From: Luca Coelho <luciano.coelho@intel.com>
>>
>> This makes the code a bit more symmetric and readable, especially when we
>> start adding more display version-specific alternatives.
>>
>> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
>> Link: https://lore.kernel.org/r/20230721111121.369227-4-
>> luciano.coelho@intel.com
>> ---
>>  drivers/gpu/drm/i915/display/intel_tc.c | 32 +++++++++++++++----------
>>  1 file changed, 19 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
>> b/drivers/gpu/drm/i915/display/intel_tc.c
>> index de848b329f4b..43b8eeba26f8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_tc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
>> @@ -311,23 +311,12 @@ static int mtl_tc_port_get_max_lane_count(struct
>> intel_digital_port *dig_port)
>>  	}
>>  }
>>
>> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
>> +static int intel_tc_port_get_max_lane_count(struct intel_digital_port
>> +*dig_port)
>>  {
>>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>> -	struct intel_tc_port *tc = to_tc_port(dig_port);
>> -	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>>  	intel_wakeref_t wakeref;
>> -	u32 lane_mask;
>> -
>> -	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
>> -		return 4;
>> +	u32 lane_mask = 0;
>>
>> -	assert_tc_cold_blocked(tc);
>> -
>> -	if (DISPLAY_VER(i915) >= 14)
>> -		return mtl_tc_port_get_max_lane_count(dig_port);
>> -
>> -	lane_mask = 0;
>>  	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE,
>> wakeref)
>>  		lane_mask = intel_tc_port_get_lane_mask(dig_port);
>>
>> @@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct
>> intel_digital_port *dig_port)
>>  	}
>>  }
>
>Rather than having two functions:
>mtl_tc_port_get_max_lane_count()
>& intel_tc_port_get_max_lane_count() that both call:
>with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
>                lane_mask = intel_tc_port_get_lane_mask(dig_port);
>to get the lane mask the us directly pass the lane_mask to the above two functions
>and make the call for getting the lane_mask common i.e lets call it in
>intel_tc_port_fia_max_lane_count().

Maybe, but I will let this to be decided between you and Luca. Pasting
from the cover letter:

         3. Patches 7 through 10 can also be ignored: they are not
            applied yet, but being reviewed in other patch series by its
            author[2].

         [2] https://patchwork.freedesktop.org/series/120980/

The only reason I added them here is that since this series will take
some time to be applied, I figured it would be better not to create
unnecessary conflicts. I expect these patches to merge soon so I will
just drop them in the next revision of this series.

thanks
Lucas De Marchi

>
>Regards,
>Suraj Kandpal
>>
>> +int intel_tc_port_fia_max_lane_count(struct intel_digital_port
>> +*dig_port) {
>> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>> +	struct intel_tc_port *tc = to_tc_port(dig_port);
>> +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>> +
>> +	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
>> +		return 4;
>> +
>> +	assert_tc_cold_blocked(tc);
>> +
>> +	if (DISPLAY_VER(i915) >= 14)
>> +		return mtl_tc_port_get_max_lane_count(dig_port);
>> +
>> +	return intel_tc_port_get_max_lane_count(dig_port);
>> +}
>> +
>>  void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>>  				      int required_lanes)
>>  {
>> --
>> 2.40.1
>

Re: [Intel-xe] [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

[Lucas De Marchi]

Hi Suraj,

On Thu, Aug 24, 2023 at 05:43:15AM +0000, Kandpal, Suraj wrote:
>
>
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
>> De Marchi
>> Sent: Wednesday, August 23, 2023 10:37 PM
>> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> Cc: Coelho, Luciano <luciano.coelho@intel.com>
>> Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the
>> main _max_lane_count() func
>>
>> From: Luca Coelho <luciano.coelho@intel.com>
>>
>> This makes the code a bit more symmetric and readable, especially when we
>> start adding more display version-specific alternatives.
>>
>> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
>> Link: https://lore.kernel.org/r/20230721111121.369227-4-
>> luciano.coelho@intel.com
>> ---
>>  drivers/gpu/drm/i915/display/intel_tc.c | 32 +++++++++++++++----------
>>  1 file changed, 19 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
>> b/drivers/gpu/drm/i915/display/intel_tc.c
>> index de848b329f4b..43b8eeba26f8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_tc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
>> @@ -311,23 +311,12 @@ static int mtl_tc_port_get_max_lane_count(struct
>> intel_digital_port *dig_port)
>>  	}
>>  }
>>
>> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
>> +static int intel_tc_port_get_max_lane_count(struct intel_digital_port
>> +*dig_port)
>>  {
>>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>> -	struct intel_tc_port *tc = to_tc_port(dig_port);
>> -	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>>  	intel_wakeref_t wakeref;
>> -	u32 lane_mask;
>> -
>> -	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
>> -		return 4;
>> +	u32 lane_mask = 0;
>>
>> -	assert_tc_cold_blocked(tc);
>> -
>> -	if (DISPLAY_VER(i915) >= 14)
>> -		return mtl_tc_port_get_max_lane_count(dig_port);
>> -
>> -	lane_mask = 0;
>>  	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE,
>> wakeref)
>>  		lane_mask = intel_tc_port_get_lane_mask(dig_port);
>>
>> @@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct
>> intel_digital_port *dig_port)
>>  	}
>>  }
>
>Rather than having two functions:
>mtl_tc_port_get_max_lane_count()
>& intel_tc_port_get_max_lane_count() that both call:
>with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
>                lane_mask = intel_tc_port_get_lane_mask(dig_port);
>to get the lane mask the us directly pass the lane_mask to the above two functions
>and make the call for getting the lane_mask common i.e lets call it in
>intel_tc_port_fia_max_lane_count().

Maybe, but I will let this to be decided between you and Luca. Pasting
from the cover letter:

         3. Patches 7 through 10 can also be ignored: they are not
            applied yet, but being reviewed in other patch series by its
            author[2].

         [2] https://patchwork.freedesktop.org/series/120980/

The only reason I added them here is that since this series will take
some time to be applied, I figured it would be better not to create
unnecessary conflicts. I expect these patches to merge soon so I will
just drop them in the next revision of this series.

thanks
Lucas De Marchi

>
>Regards,
>Suraj Kandpal
>>
>> +int intel_tc_port_fia_max_lane_count(struct intel_digital_port
>> +*dig_port) {
>> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>> +	struct intel_tc_port *tc = to_tc_port(dig_port);
>> +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>> +
>> +	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
>> +		return 4;
>> +
>> +	assert_tc_cold_blocked(tc);
>> +
>> +	if (DISPLAY_VER(i915) >= 14)
>> +		return mtl_tc_port_get_max_lane_count(dig_port);
>> +
>> +	return intel_tc_port_get_max_lane_count(dig_port);
>> +}
>> +
>>  void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>>  				      int required_lanes)
>>  {
>> --
>> 2.40.1
>

Re: [Intel-gfx] [Intel-xe] [PATCH 11/42] drm/xe/lnl: Add IS_LUNARLAKE

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 10:55:34AM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:09AM -0700, Lucas De Marchi wrote:
>> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>
>> Add IS_LUNARLAKE in the compat-i915-headers. That macro, to be used by
>> the xe driver, checks for the platform, whereas the macro on the i915
>> side is always false.
>
>Stepping back, do we really need this macro?  Most display code should
>be matching on the display IP rather than the platform going forward.
>Looking at this series, I only see this used for fake PCH and GMBUS,
>both of which I think could probably be checking the display IP rather
>than the platform.

I tweaked a few patches to check IP rather than platform and reworded
the commit messages. But there are still a few patches needing that. If
we move them all and make sure we will not need, then I can drop this
patch.  I will take a look for next iteration

thanks
Lucas De Marchi

>
>
>Matt
>
>>
>> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> ---
>>  drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> index d64d34181790..38b64ff6b9ea 100644
>> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> @@ -79,6 +79,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
>>  #define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, XE_DG2)
>>  #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
>>  #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
>> +#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
>>
>>  #define IS_HSW_ULT(dev_priv) (dev_priv && 0)
>>  #define IS_BDW_ULT(dev_priv) (dev_priv && 0)
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-xe] [PATCH 11/42] drm/xe/lnl: Add IS_LUNARLAKE

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 10:55:34AM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:09AM -0700, Lucas De Marchi wrote:
>> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>
>> Add IS_LUNARLAKE in the compat-i915-headers. That macro, to be used by
>> the xe driver, checks for the platform, whereas the macro on the i915
>> side is always false.
>
>Stepping back, do we really need this macro?  Most display code should
>be matching on the display IP rather than the platform going forward.
>Looking at this series, I only see this used for fake PCH and GMBUS,
>both of which I think could probably be checking the display IP rather
>than the platform.

I tweaked a few patches to check IP rather than platform and reworded
the commit messages. But there are still a few patches needing that. If
we move them all and make sure we will not need, then I can drop this
patch.  I will take a look for next iteration

thanks
Lucas De Marchi

>
>
>Matt
>
>>
>> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> ---
>>  drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> index d64d34181790..38b64ff6b9ea 100644
>> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> @@ -79,6 +79,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
>>  #define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, XE_DG2)
>>  #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
>>  #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
>> +#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
>>
>>  #define IS_HSW_ULT(dev_priv) (dev_priv && 0)
>>  #define IS_BDW_ULT(dev_priv) (dev_priv && 0)
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 12/42] drm/i915/lnl: Add display definitions

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 11:03:42AM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
>> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>
>> Add Lunar Lake platform definitions for i915 display. The support for
>> LNL will be added to the xe driver, with i915 only driving the display
>> side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
>> i915 module.
>>
>> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  .../gpu/drm/i915/display/intel_display_device.c   | 15 +++++++++++++++
>>  drivers/gpu/drm/i915/i915_drv.h                   |  1 +
>>  2 files changed, 16 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
>> index f87470da25d0..b853cd0c704a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
>> @@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
>>  		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
>>  };
>>
>> +static const struct intel_display_device_info xe2_lpd_display = {
>> +	XE_LPD_FEATURES,
>> +	.has_cdclk_crawl = 1,
>> +	.has_cdclk_squash = 1,
>
>XE_LPD_FEATURES, crawl, squash, transcoder mask, and port mask are all
>common between Xe_LPD+ and Xe2_LPD.  Maybe we should add an
>XE_LPDP_FEATURES macro first, and then re-use it here so that the deltas
>are smaller and it's more obvious what the key changes are with this new
>IP?

ack

>
>> +
>> +	.__runtime_defaults.ip.ver = 20,
>> +	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
>
>With Xe2, FBC is supported on all pipes now (bspec 68881, 68904).

intention was to only do this after
"drm/i915/xe2lpd: FBC is now supported on all pipes". I guess I can
reorder the patches to bring that one first and fix it.


>
>> +	.__runtime_defaults.cpu_transcoder_mask =
>> +		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>> +	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
>> +		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
>> +};
>> +
>>  __diag_pop();
>>
>>  #undef INTEL_VGA_DEVICE
>> @@ -795,6 +809,7 @@ static const struct {
>>  	const struct intel_display_device_info *display;
>>  } gmdid_display_map[] = {
>>  	{ 14,  0, &xe_lpdp_display },
>> +	{ 20,  0, &xe2_lpd_display },
>>  };
>>
>>  static const struct intel_display_device_info *
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 07f79b1028e1..96ac9a9cc155 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>  #define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
>>  #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
>>  #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
>> +#define IS_LUNARLAKE(dev_priv)  0
>
>As noted on the previous patch, we might be able to drop this completely
>if we update the fake PCH and gmbus code to match on display IP.  Given
>that PCH isn't even involved in south display handling anymore, that
>seems like it might be reasonable?  If anything, we're more likely to
>need to match on PICA ID (which has its own GMD_ID register) than base
>platform at some point in the future.

ack

thanks
Lucas De Marchi

>
>
>Matt
>
>>
>>  #define IS_METEORLAKE_M(i915) \
>>  	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-xe] [Intel-gfx] [PATCH 12/42] drm/i915/lnl: Add display definitions

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 11:03:42AM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
>> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>
>> Add Lunar Lake platform definitions for i915 display. The support for
>> LNL will be added to the xe driver, with i915 only driving the display
>> side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
>> i915 module.
>>
>> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  .../gpu/drm/i915/display/intel_display_device.c   | 15 +++++++++++++++
>>  drivers/gpu/drm/i915/i915_drv.h                   |  1 +
>>  2 files changed, 16 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
>> index f87470da25d0..b853cd0c704a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
>> @@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
>>  		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
>>  };
>>
>> +static const struct intel_display_device_info xe2_lpd_display = {
>> +	XE_LPD_FEATURES,
>> +	.has_cdclk_crawl = 1,
>> +	.has_cdclk_squash = 1,
>
>XE_LPD_FEATURES, crawl, squash, transcoder mask, and port mask are all
>common between Xe_LPD+ and Xe2_LPD.  Maybe we should add an
>XE_LPDP_FEATURES macro first, and then re-use it here so that the deltas
>are smaller and it's more obvious what the key changes are with this new
>IP?

ack

>
>> +
>> +	.__runtime_defaults.ip.ver = 20,
>> +	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
>
>With Xe2, FBC is supported on all pipes now (bspec 68881, 68904).

intention was to only do this after
"drm/i915/xe2lpd: FBC is now supported on all pipes". I guess I can
reorder the patches to bring that one first and fix it.


>
>> +	.__runtime_defaults.cpu_transcoder_mask =
>> +		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>> +	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
>> +		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
>> +};
>> +
>>  __diag_pop();
>>
>>  #undef INTEL_VGA_DEVICE
>> @@ -795,6 +809,7 @@ static const struct {
>>  	const struct intel_display_device_info *display;
>>  } gmdid_display_map[] = {
>>  	{ 14,  0, &xe_lpdp_display },
>> +	{ 20,  0, &xe2_lpd_display },
>>  };
>>
>>  static const struct intel_display_device_info *
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 07f79b1028e1..96ac9a9cc155 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>  #define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
>>  #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
>>  #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
>> +#define IS_LUNARLAKE(dev_priv)  0
>
>As noted on the previous patch, we might be able to drop this completely
>if we update the fake PCH and gmbus code to match on display IP.  Given
>that PCH isn't even involved in south display handling anymore, that
>seems like it might be reasonable?  If anything, we're more likely to
>need to match on PICA ID (which has its own GMD_ID register) than base
>platform at some point in the future.

ack

thanks
Lucas De Marchi

>
>
>Matt
>
>>
>>  #define IS_METEORLAKE_M(i915) \
>>  	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 23/42] drm/i915/xe2lpd: FBC is now supported on all pipes

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 12:49:36PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:21AM -0700, Lucas De Marchi wrote:
>> From: Matt Roper <matthew.d.roper@intel.com>
>>
>> FBC is no longer limited by pipe.
>
>It looks like we lost the part of this patch that adds this to the
>xe2_lpd_display device info structure.

ack, but I will just move this patch first in the series so when we
introduce xe2_lpd_display we can already add it.

Lucas De Marchi

>
>
>Matt
>
>>
>> Bspec: 68881, 68904
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
>> index 4adb98afe6ff..6720ec8ee8a2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
>> @@ -20,6 +20,8 @@ struct intel_plane_state;
>>  enum intel_fbc_id {
>>  	INTEL_FBC_A,
>>  	INTEL_FBC_B,
>> +	INTEL_FBC_C,
>> +	INTEL_FBC_D,
>>
>>  	I915_MAX_FBCS,
>>  };
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-xe] [PATCH 23/42] drm/i915/xe2lpd: FBC is now supported on all pipes

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 12:49:36PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:21AM -0700, Lucas De Marchi wrote:
>> From: Matt Roper <matthew.d.roper@intel.com>
>>
>> FBC is no longer limited by pipe.
>
>It looks like we lost the part of this patch that adds this to the
>xe2_lpd_display device info structure.

ack, but I will just move this patch first in the series so when we
introduce xe2_lpd_display we can already add it.

Lucas De Marchi

>
>
>Matt
>
>>
>> Bspec: 68881, 68904
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
>> index 4adb98afe6ff..6720ec8ee8a2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
>> @@ -20,6 +20,8 @@ struct intel_plane_state;
>>  enum intel_fbc_id {
>>  	INTEL_FBC_A,
>>  	INTEL_FBC_B,
>> +	INTEL_FBC_C,
>> +	INTEL_FBC_D,
>>
>>  	I915_MAX_FBCS,
>>  };
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 12/42] drm/i915/lnl: Add display definitions

[Matt Roper]

On Thu, Aug 24, 2023 at 08:49:42AM -0700, Lucas De Marchi wrote:
> On Wed, Aug 23, 2023 at 11:03:42AM -0700, Matt Roper wrote:
> > On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
> > > From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > > 
> > > Add Lunar Lake platform definitions for i915 display. The support for
> > > LNL will be added to the xe driver, with i915 only driving the display
> > > side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
> > > i915 module.
> > > 
> > > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  .../gpu/drm/i915/display/intel_display_device.c   | 15 +++++++++++++++
> > >  drivers/gpu/drm/i915/i915_drv.h                   |  1 +
> > >  2 files changed, 16 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> > > index f87470da25d0..b853cd0c704a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> > > @@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
> > >  		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> > >  };
> > > 
> > > +static const struct intel_display_device_info xe2_lpd_display = {
> > > +	XE_LPD_FEATURES,
> > > +	.has_cdclk_crawl = 1,
> > > +	.has_cdclk_squash = 1,
> > 
> > XE_LPD_FEATURES, crawl, squash, transcoder mask, and port mask are all
> > common between Xe_LPD+ and Xe2_LPD.  Maybe we should add an
> > XE_LPDP_FEATURES macro first, and then re-use it here so that the deltas
> > are smaller and it's more obvious what the key changes are with this new
> > IP?
> 
> ack
> 
> > 
> > > +
> > > +	.__runtime_defaults.ip.ver = 20,
> > > +	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> > 
> > With Xe2, FBC is supported on all pipes now (bspec 68881, 68904).
> 
> intention was to only do this after
> "drm/i915/xe2lpd: FBC is now supported on all pipes". I guess I can
> reorder the patches to bring that one first and fix it.

I hadn't noticed that patch yet when I reviewed this one.  But maybe the
best bet is to drop this line in this patch (so you'll inherit the value
from XE_LPD[P]_FEATURES), and then that later patch will update it with
the right value.


Matt

> 
> 
> > 
> > > +	.__runtime_defaults.cpu_transcoder_mask =
> > > +		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> > > +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> > > +	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
> > > +		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> > > +};
> > > +
> > >  __diag_pop();
> > > 
> > >  #undef INTEL_VGA_DEVICE
> > > @@ -795,6 +809,7 @@ static const struct {
> > >  	const struct intel_display_device_info *display;
> > >  } gmdid_display_map[] = {
> > >  	{ 14,  0, &xe_lpdp_display },
> > > +	{ 20,  0, &xe2_lpd_display },
> > >  };
> > > 
> > >  static const struct intel_display_device_info *
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 07f79b1028e1..96ac9a9cc155 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > >  #define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
> > >  #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
> > >  #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
> > > +#define IS_LUNARLAKE(dev_priv)  0
> > 
> > As noted on the previous patch, we might be able to drop this completely
> > if we update the fake PCH and gmbus code to match on display IP.  Given
> > that PCH isn't even involved in south display handling anymore, that
> > seems like it might be reasonable?  If anything, we're more likely to
> > need to match on PICA ID (which has its own GMD_ID register) than base
> > platform at some point in the future.
> 
> ack
> 
> thanks
> Lucas De Marchi
> 
> > 
> > 
> > Matt
> > 
> > > 
> > >  #define IS_METEORLAKE_M(i915) \
> > >  	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> > > --
> > > 2.40.1
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [Intel-gfx] [PATCH 12/42] drm/i915/lnl: Add display definitions

[Matt Roper]

On Thu, Aug 24, 2023 at 08:49:42AM -0700, Lucas De Marchi wrote:
> On Wed, Aug 23, 2023 at 11:03:42AM -0700, Matt Roper wrote:
> > On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
> > > From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > > 
> > > Add Lunar Lake platform definitions for i915 display. The support for
> > > LNL will be added to the xe driver, with i915 only driving the display
> > > side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
> > > i915 module.
> > > 
> > > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  .../gpu/drm/i915/display/intel_display_device.c   | 15 +++++++++++++++
> > >  drivers/gpu/drm/i915/i915_drv.h                   |  1 +
> > >  2 files changed, 16 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> > > index f87470da25d0..b853cd0c704a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> > > @@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
> > >  		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> > >  };
> > > 
> > > +static const struct intel_display_device_info xe2_lpd_display = {
> > > +	XE_LPD_FEATURES,
> > > +	.has_cdclk_crawl = 1,
> > > +	.has_cdclk_squash = 1,
> > 
> > XE_LPD_FEATURES, crawl, squash, transcoder mask, and port mask are all
> > common between Xe_LPD+ and Xe2_LPD.  Maybe we should add an
> > XE_LPDP_FEATURES macro first, and then re-use it here so that the deltas
> > are smaller and it's more obvious what the key changes are with this new
> > IP?
> 
> ack
> 
> > 
> > > +
> > > +	.__runtime_defaults.ip.ver = 20,
> > > +	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> > 
> > With Xe2, FBC is supported on all pipes now (bspec 68881, 68904).
> 
> intention was to only do this after
> "drm/i915/xe2lpd: FBC is now supported on all pipes". I guess I can
> reorder the patches to bring that one first and fix it.

I hadn't noticed that patch yet when I reviewed this one.  But maybe the
best bet is to drop this line in this patch (so you'll inherit the value
from XE_LPD[P]_FEATURES), and then that later patch will update it with
the right value.


Matt

> 
> 
> > 
> > > +	.__runtime_defaults.cpu_transcoder_mask =
> > > +		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> > > +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> > > +	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
> > > +		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> > > +};
> > > +
> > >  __diag_pop();
> > > 
> > >  #undef INTEL_VGA_DEVICE
> > > @@ -795,6 +809,7 @@ static const struct {
> > >  	const struct intel_display_device_info *display;
> > >  } gmdid_display_map[] = {
> > >  	{ 14,  0, &xe_lpdp_display },
> > > +	{ 20,  0, &xe2_lpd_display },
> > >  };
> > > 
> > >  static const struct intel_display_device_info *
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 07f79b1028e1..96ac9a9cc155 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > >  #define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
> > >  #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
> > >  #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
> > > +#define IS_LUNARLAKE(dev_priv)  0
> > 
> > As noted on the previous patch, we might be able to drop this completely
> > if we update the fake PCH and gmbus code to match on display IP.  Given
> > that PCH isn't even involved in south display handling anymore, that
> > seems like it might be reasonable?  If anything, we're more likely to
> > need to match on PICA ID (which has its own GMD_ID register) than base
> > platform at some point in the future.
> 
> ack
> 
> thanks
> Lucas De Marchi
> 
> > 
> > 
> > Matt
> > 
> > > 
> > >  #define IS_METEORLAKE_M(i915) \
> > >  	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> > > --
> > > 2.40.1
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

[Kandpal, Suraj]

> >> Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out
> >> of the main _max_lane_count() func
> >>
> >> From: Luca Coelho <luciano.coelho@intel.com>
> >>
> >> This makes the code a bit more symmetric and readable, especially
> >> when we start adding more display version-specific alternatives.
> >>
> >> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> >> Link: https://lore.kernel.org/r/20230721111121.369227-4-
> >> luciano.coelho@intel.com
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_tc.c | 32
> >> +++++++++++++++----------
> >>  1 file changed, 19 insertions(+), 13 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> >> b/drivers/gpu/drm/i915/display/intel_tc.c
> >> index de848b329f4b..43b8eeba26f8 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> >> @@ -311,23 +311,12 @@ static int
> >> mtl_tc_port_get_max_lane_count(struct
> >> intel_digital_port *dig_port)
> >>  	}
> >>  }
> >>
> >> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> >> *dig_port)
> >> +static int intel_tc_port_get_max_lane_count(struct
> >> +intel_digital_port
> >> +*dig_port)
> >>  {
> >>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> >> -	struct intel_tc_port *tc = to_tc_port(dig_port);
> >> -	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> >>  	intel_wakeref_t wakeref;
> >> -	u32 lane_mask;
> >> -
> >> -	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> >> -		return 4;
> >> +	u32 lane_mask = 0;
> >>
> >> -	assert_tc_cold_blocked(tc);
> >> -
> >> -	if (DISPLAY_VER(i915) >= 14)
> >> -		return mtl_tc_port_get_max_lane_count(dig_port);
> >> -
> >> -	lane_mask = 0;
> >>  	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE,
> >> wakeref)
> >>  		lane_mask = intel_tc_port_get_lane_mask(dig_port);
> >>
> >> @@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct
> >> intel_digital_port *dig_port)
> >>  	}
> >>  }
> >
> >Rather than having two functions:
> >mtl_tc_port_get_max_lane_count()
> >& intel_tc_port_get_max_lane_count() that both call:
> >with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> >                lane_mask = intel_tc_port_get_lane_mask(dig_port);
> >to get the lane mask the us directly pass the lane_mask to the above
> >two functions and make the call for getting the lane_mask common i.e
> >lets call it in intel_tc_port_fia_max_lane_count().
> 
> Maybe, but I will let this to be decided between you and Luca. Pasting from
> the cover letter:
> 
>          3. Patches 7 through 10 can also be ignored: they are not
>             applied yet, but being reviewed in other patch series by its
>             author[2].
> 
>          [2] https://patchwork.freedesktop.org/series/120980/
> 
> The only reason I added them here is that since this series will take some time
> to be applied, I figured it would be better not to create unnecessary conflicts. I
> expect these patches to merge soon so I will just drop them in the next
> revision of this series.
> 
> thanks
> Lucas De Marchi
> 

Ohk got it.

Regards,
Suraj Kandpal
> >
> >Regards,
> >Suraj Kandpal
> >>
> >> +int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> >> +*dig_port) {
> >> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> >> +	struct intel_tc_port *tc = to_tc_port(dig_port);
> >> +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> >> +
> >> +	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> >> +		return 4;
> >> +
> >> +	assert_tc_cold_blocked(tc);
> >> +
> >> +	if (DISPLAY_VER(i915) >= 14)
> >> +		return mtl_tc_port_get_max_lane_count(dig_port);
> >> +
> >> +	return intel_tc_port_get_max_lane_count(dig_port);
> >> +}
> >> +
> >>  void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
> >>  				      int required_lanes)
> >>  {
> >> --
> >> 2.40.1
> >

Re: [Intel-xe] [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

[Kandpal, Suraj]

> >> Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out
> >> of the main _max_lane_count() func
> >>
> >> From: Luca Coelho <luciano.coelho@intel.com>
> >>
> >> This makes the code a bit more symmetric and readable, especially
> >> when we start adding more display version-specific alternatives.
> >>
> >> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> >> Link: https://lore.kernel.org/r/20230721111121.369227-4-
> >> luciano.coelho@intel.com
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_tc.c | 32
> >> +++++++++++++++----------
> >>  1 file changed, 19 insertions(+), 13 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> >> b/drivers/gpu/drm/i915/display/intel_tc.c
> >> index de848b329f4b..43b8eeba26f8 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> >> @@ -311,23 +311,12 @@ static int
> >> mtl_tc_port_get_max_lane_count(struct
> >> intel_digital_port *dig_port)
> >>  	}
> >>  }
> >>
> >> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> >> *dig_port)
> >> +static int intel_tc_port_get_max_lane_count(struct
> >> +intel_digital_port
> >> +*dig_port)
> >>  {
> >>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> >> -	struct intel_tc_port *tc = to_tc_port(dig_port);
> >> -	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> >>  	intel_wakeref_t wakeref;
> >> -	u32 lane_mask;
> >> -
> >> -	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> >> -		return 4;
> >> +	u32 lane_mask = 0;
> >>
> >> -	assert_tc_cold_blocked(tc);
> >> -
> >> -	if (DISPLAY_VER(i915) >= 14)
> >> -		return mtl_tc_port_get_max_lane_count(dig_port);
> >> -
> >> -	lane_mask = 0;
> >>  	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE,
> >> wakeref)
> >>  		lane_mask = intel_tc_port_get_lane_mask(dig_port);
> >>
> >> @@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct
> >> intel_digital_port *dig_port)
> >>  	}
> >>  }
> >
> >Rather than having two functions:
> >mtl_tc_port_get_max_lane_count()
> >& intel_tc_port_get_max_lane_count() that both call:
> >with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> >                lane_mask = intel_tc_port_get_lane_mask(dig_port);
> >to get the lane mask the us directly pass the lane_mask to the above
> >two functions and make the call for getting the lane_mask common i.e
> >lets call it in intel_tc_port_fia_max_lane_count().
> 
> Maybe, but I will let this to be decided between you and Luca. Pasting from
> the cover letter:
> 
>          3. Patches 7 through 10 can also be ignored: they are not
>             applied yet, but being reviewed in other patch series by its
>             author[2].
> 
>          [2] https://patchwork.freedesktop.org/series/120980/
> 
> The only reason I added them here is that since this series will take some time
> to be applied, I figured it would be better not to create unnecessary conflicts. I
> expect these patches to merge soon so I will just drop them in the next
> revision of this series.
> 
> thanks
> Lucas De Marchi
> 

Ohk got it.

Regards,
Suraj Kandpal
> >
> >Regards,
> >Suraj Kandpal
> >>
> >> +int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> >> +*dig_port) {
> >> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> >> +	struct intel_tc_port *tc = to_tc_port(dig_port);
> >> +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> >> +
> >> +	if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> >> +		return 4;
> >> +
> >> +	assert_tc_cold_blocked(tc);
> >> +
> >> +	if (DISPLAY_VER(i915) >= 14)
> >> +		return mtl_tc_port_get_max_lane_count(dig_port);
> >> +
> >> +	return intel_tc_port_get_max_lane_count(dig_port);
> >> +}
> >> +
> >>  void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
> >>  				      int required_lanes)
> >>  {
> >> --
> >> 2.40.1
> >

Re: [Intel-gfx] [Intel-xe] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 12:28:04PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:18AM -0700, Lucas De Marchi wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> Do not read DE_RRMR register after display version 20. This register
>> contains display state information during GFX state dumps.
>>
>> Bspec: 69456
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index 4749f99e6320..fe2fa6f966f2 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -1755,7 +1755,7 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
>>  	struct intel_uncore *uncore = gt->_gt->uncore;
>>  	struct drm_i915_private *i915 = uncore->i915;
>>
>> -	if (GRAPHICS_VER(i915) >= 6)
>> +	if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)
>
>We have IS_DISPLAY_VER() that's slightly simpler for ranges like this.

not sure it's very intuitive for this case though. We want to change the
behavior for display version 20, and would have to write something like
IS_DISPLAY_VER(i915, 6, 14) since the macro is inclusive on the upper
end.  I'd prefer to leave with the check for 20.

Lucas De Marchi

>
>Aside from that,
>
>        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>
>Matt
>
>>  		gt->derrmr = intel_uncore_read(uncore, DERRMR);
>>
>>  	if (GRAPHICS_VER(i915) >= 8)
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-xe] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 12:28:04PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:18AM -0700, Lucas De Marchi wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> Do not read DE_RRMR register after display version 20. This register
>> contains display state information during GFX state dumps.
>>
>> Bspec: 69456
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index 4749f99e6320..fe2fa6f966f2 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -1755,7 +1755,7 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
>>  	struct intel_uncore *uncore = gt->_gt->uncore;
>>  	struct drm_i915_private *i915 = uncore->i915;
>>
>> -	if (GRAPHICS_VER(i915) >= 6)
>> +	if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)
>
>We have IS_DISPLAY_VER() that's slightly simpler for ranges like this.

not sure it's very intuitive for this case though. We want to change the
behavior for display version 20, and would have to write something like
IS_DISPLAY_VER(i915, 6, 14) since the macro is inclusive on the upper
end.  I'd prefer to leave with the check for 20.

Lucas De Marchi

>
>Aside from that,
>
>        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>
>Matt
>
>>  		gt->derrmr = intel_uncore_read(uncore, DERRMR);
>>
>>  	if (GRAPHICS_VER(i915) >= 8)
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 35/42] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:33AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
> between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
> change.
> 
> Previsouly DBuf state and CDCLK were not anyhow coupled together.  Now
> at compute stage when we know which CDCLK/MDCLK we are going to use, we
> need to update the DBuf state with that ratio, being properly encoded,
> so that it gets written to those registers, once DBuf state is being
> update. The criteria for updating DBuf state is also a CDCLK/MDCLK ratio
> change now.
> 
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Bspec: 68864

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c    | 16 +++++++++
>  drivers/gpu/drm/i915/display/skl_watermark.c  | 35 ++++++++++++++++---
>  drivers/gpu/drm/i915/display/skl_watermark.h  |  1 +
>  .../gpu/drm/i915/display/skl_watermark_regs.h |  2 ++
>  4 files changed, 50 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 04937aaabcee..aa1000db3cb9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -37,6 +37,7 @@
>  #include "intel_pci_config.h"
>  #include "intel_pcode.h"
>  #include "intel_psr.h"
> +#include "skl_watermark.h"
>  #include "vlv_sideband.h"
>  
>  /**
> @@ -1827,6 +1828,15 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
>  	return vco == ~0;
>  }
>  
> +static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> +				 const struct intel_cdclk_config *cdclk_config)
> +{
> +	if (DISPLAY_VER(i915) >= 20)
> +		return cdclk_config->mdclk / cdclk_config->cdclk - 1;

Should this be DIV_ROUND_UP?  Bspec 69482 and 69445 both say "If mdclk/cdclk is a
non-integer value, round up the result."

You might want a comment on this function noting that it returns the
register encoding of ratio (i.e., "- 1") rather than the ratio itself.

> +	else
> +		return 1;
> +}
> +
>  static int cdclk_squash_divider(u16 waveform)
>  {
>  	return hweight16(waveform ?: 0xffff);
> @@ -2727,6 +2737,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
>  	struct intel_crtc_state *crtc_state;
>  	int min_cdclk, i;
>  	enum pipe pipe;
> +	struct intel_dbuf_state *dbuf_state;
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
>  		int ret;
> @@ -2760,6 +2771,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
>  		}
>  	}
>  
> +	dbuf_state = intel_atomic_get_new_dbuf_state(state);
> +	if (dbuf_state)
> +		dbuf_state->mdclk_cdclk_ratio =
> +			get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
> +
>  	min_cdclk = max(cdclk_state->force_min_cdclk,
>  			cdclk_state->bw_min_cdclk);
>  	for_each_pipe(dev_priv, pipe)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 64a122d3c9c0..79454b4d99e3 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3472,6 +3472,23 @@ int intel_dbuf_init(struct drm_i915_private *i915)
>  	return 0;
>  }
>  
> +static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> +				      int mdclk_cdclk_ratio,
> +				      int mbus_joined)
> +{
> +	if (DISPLAY_VER(i915) >= 20) {

We can drop this condition.  Since mdclk_cdclk_ratio is already "1" for
pre-20 platforms, the calculations here still come out right (returning
either 3 or 1 depending on joining) there too.


Matt

> +		if (mbus_joined)
> +			return (mdclk_cdclk_ratio << 1) + 1;
> +		else
> +			return mdclk_cdclk_ratio;
> +	}
> +
> +	if (mbus_joined)
> +		return 3;
> +
> +	return 1;
> +}
> +
>  /*
>   * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
>   * update the request state of all DBUS slices.
> @@ -3483,10 +3500,16 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
>  	enum dbuf_slice slice;
>  	const struct intel_dbuf_state *dbuf_state =
>  		intel_atomic_get_new_dbuf_state(state);
> +	int tracker_state_service;
>  
>  	if (!HAS_MBUS_JOINING(i915))
>  		return;
>  
> +	tracker_state_service =
> +		get_mbus_mdclk_cdclk_ratio(i915,
> +					   dbuf_state->mdclk_cdclk_ratio,
> +					   dbuf_state->joined_mbus);
> +
>  	/*
>  	 * TODO: Implement vblank synchronized MBUS joining changes.
>  	 * Must be properly coordinated with dbuf reprogramming.
> @@ -3494,13 +3517,15 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
>  	if (dbuf_state->joined_mbus) {
>  		mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
>  			MBUS_JOIN_PIPE_SELECT_NONE;
> -		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
>  	} else {
>  		mbus_ctl = MBUS_HASHING_MODE_2x2 |
>  			MBUS_JOIN_PIPE_SELECT_NONE;
> -		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
>  	}
>  
> +	dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(tracker_state_service);
> +
> +	mbus_ctl |= MBUS_TRANS_THROTTLE_MIN_SELECT(dbuf_state->mdclk_cdclk_ratio);
> +
>  	intel_de_rmw(i915, MBUS_CTL,
>  		     MBUS_HASHING_MODE_MASK | MBUS_JOIN |
>  		     MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
> @@ -3521,7 +3546,8 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
>  
>  	if (!new_dbuf_state ||
>  	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> -	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> +	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> +	     new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
>  		return;
>  
>  	WARN_ON(!new_dbuf_state->base.changed);
> @@ -3542,7 +3568,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
>  
>  	if (!new_dbuf_state ||
>  	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> -	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> +	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> +	     new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
>  		return;
>  
>  	WARN_ON(!new_dbuf_state->base.changed);
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> index f91a3d4ddc07..54db5c7d517e 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> @@ -56,6 +56,7 @@ struct intel_dbuf_state {
>  	u8 slices[I915_MAX_PIPES];
>  	u8 enabled_slices;
>  	u8 active_pipes;
> +	u8 mdclk_cdclk_ratio;
>  	bool joined_mbus;
>  };
>  
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> index 628c5920ad49..4c820f1d351d 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> @@ -38,6 +38,8 @@
>  #define MBUS_HASHING_MODE_2x2		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
>  #define MBUS_HASHING_MODE_1x4		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
>  #define MBUS_JOIN_PIPE_SELECT_MASK	REG_GENMASK(28, 26)
> +#define MBUS_TRANS_THROTTLE_MIN_MASK	REG_GENMASK(15, 13)
> +#define MBUS_TRANS_THROTTLE_MIN_SELECT(ratio)	REG_FIELD_PREP(MBUS_TRANS_THROTTLE_MIN_MASK, ratio)
>  #define MBUS_JOIN_PIPE_SELECT(pipe)	REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
>  #define MBUS_JOIN_PIPE_SELECT_NONE	MBUS_JOIN_PIPE_SELECT(7)
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 35/42] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:33AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
> between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
> change.
> 
> Previsouly DBuf state and CDCLK were not anyhow coupled together.  Now
> at compute stage when we know which CDCLK/MDCLK we are going to use, we
> need to update the DBuf state with that ratio, being properly encoded,
> so that it gets written to those registers, once DBuf state is being
> update. The criteria for updating DBuf state is also a CDCLK/MDCLK ratio
> change now.
> 
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Bspec: 68864

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c    | 16 +++++++++
>  drivers/gpu/drm/i915/display/skl_watermark.c  | 35 ++++++++++++++++---
>  drivers/gpu/drm/i915/display/skl_watermark.h  |  1 +
>  .../gpu/drm/i915/display/skl_watermark_regs.h |  2 ++
>  4 files changed, 50 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 04937aaabcee..aa1000db3cb9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -37,6 +37,7 @@
>  #include "intel_pci_config.h"
>  #include "intel_pcode.h"
>  #include "intel_psr.h"
> +#include "skl_watermark.h"
>  #include "vlv_sideband.h"
>  
>  /**
> @@ -1827,6 +1828,15 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
>  	return vco == ~0;
>  }
>  
> +static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> +				 const struct intel_cdclk_config *cdclk_config)
> +{
> +	if (DISPLAY_VER(i915) >= 20)
> +		return cdclk_config->mdclk / cdclk_config->cdclk - 1;

Should this be DIV_ROUND_UP?  Bspec 69482 and 69445 both say "If mdclk/cdclk is a
non-integer value, round up the result."

You might want a comment on this function noting that it returns the
register encoding of ratio (i.e., "- 1") rather than the ratio itself.

> +	else
> +		return 1;
> +}
> +
>  static int cdclk_squash_divider(u16 waveform)
>  {
>  	return hweight16(waveform ?: 0xffff);
> @@ -2727,6 +2737,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
>  	struct intel_crtc_state *crtc_state;
>  	int min_cdclk, i;
>  	enum pipe pipe;
> +	struct intel_dbuf_state *dbuf_state;
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
>  		int ret;
> @@ -2760,6 +2771,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
>  		}
>  	}
>  
> +	dbuf_state = intel_atomic_get_new_dbuf_state(state);
> +	if (dbuf_state)
> +		dbuf_state->mdclk_cdclk_ratio =
> +			get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
> +
>  	min_cdclk = max(cdclk_state->force_min_cdclk,
>  			cdclk_state->bw_min_cdclk);
>  	for_each_pipe(dev_priv, pipe)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 64a122d3c9c0..79454b4d99e3 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3472,6 +3472,23 @@ int intel_dbuf_init(struct drm_i915_private *i915)
>  	return 0;
>  }
>  
> +static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> +				      int mdclk_cdclk_ratio,
> +				      int mbus_joined)
> +{
> +	if (DISPLAY_VER(i915) >= 20) {

We can drop this condition.  Since mdclk_cdclk_ratio is already "1" for
pre-20 platforms, the calculations here still come out right (returning
either 3 or 1 depending on joining) there too.


Matt

> +		if (mbus_joined)
> +			return (mdclk_cdclk_ratio << 1) + 1;
> +		else
> +			return mdclk_cdclk_ratio;
> +	}
> +
> +	if (mbus_joined)
> +		return 3;
> +
> +	return 1;
> +}
> +
>  /*
>   * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
>   * update the request state of all DBUS slices.
> @@ -3483,10 +3500,16 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
>  	enum dbuf_slice slice;
>  	const struct intel_dbuf_state *dbuf_state =
>  		intel_atomic_get_new_dbuf_state(state);
> +	int tracker_state_service;
>  
>  	if (!HAS_MBUS_JOINING(i915))
>  		return;
>  
> +	tracker_state_service =
> +		get_mbus_mdclk_cdclk_ratio(i915,
> +					   dbuf_state->mdclk_cdclk_ratio,
> +					   dbuf_state->joined_mbus);
> +
>  	/*
>  	 * TODO: Implement vblank synchronized MBUS joining changes.
>  	 * Must be properly coordinated with dbuf reprogramming.
> @@ -3494,13 +3517,15 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
>  	if (dbuf_state->joined_mbus) {
>  		mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
>  			MBUS_JOIN_PIPE_SELECT_NONE;
> -		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
>  	} else {
>  		mbus_ctl = MBUS_HASHING_MODE_2x2 |
>  			MBUS_JOIN_PIPE_SELECT_NONE;
> -		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
>  	}
>  
> +	dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(tracker_state_service);
> +
> +	mbus_ctl |= MBUS_TRANS_THROTTLE_MIN_SELECT(dbuf_state->mdclk_cdclk_ratio);
> +
>  	intel_de_rmw(i915, MBUS_CTL,
>  		     MBUS_HASHING_MODE_MASK | MBUS_JOIN |
>  		     MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
> @@ -3521,7 +3546,8 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
>  
>  	if (!new_dbuf_state ||
>  	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> -	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> +	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> +	     new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
>  		return;
>  
>  	WARN_ON(!new_dbuf_state->base.changed);
> @@ -3542,7 +3568,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
>  
>  	if (!new_dbuf_state ||
>  	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> -	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> +	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> +	     new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
>  		return;
>  
>  	WARN_ON(!new_dbuf_state->base.changed);
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> index f91a3d4ddc07..54db5c7d517e 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> @@ -56,6 +56,7 @@ struct intel_dbuf_state {
>  	u8 slices[I915_MAX_PIPES];
>  	u8 enabled_slices;
>  	u8 active_pipes;
> +	u8 mdclk_cdclk_ratio;
>  	bool joined_mbus;
>  };
>  
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> index 628c5920ad49..4c820f1d351d 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> @@ -38,6 +38,8 @@
>  #define MBUS_HASHING_MODE_2x2		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
>  #define MBUS_HASHING_MODE_1x4		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
>  #define MBUS_JOIN_PIPE_SELECT_MASK	REG_GENMASK(28, 26)
> +#define MBUS_TRANS_THROTTLE_MIN_MASK	REG_GENMASK(15, 13)
> +#define MBUS_TRANS_THROTTLE_MIN_SELECT(ratio)	REG_FIELD_PREP(MBUS_TRANS_THROTTLE_MIN_MASK, ratio)
>  #define MBUS_JOIN_PIPE_SELECT(pipe)	REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
>  #define MBUS_JOIN_PIPE_SELECT_NONE	MBUS_JOIN_PIPE_SELECT(7)
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 36/42] drm/i915/lnl: Add support for CDCLK initialization sequence

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:34AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> 
> Add CDCLK initialization sequence changes and CDCLK set frequency
> sequence for LNL platform.
> 
> CDCLK frequency change sequence is different for LNL compared to MTL
> when a change in mdclk/cdclk ratio is observed. Below are changes to be
> made:
> 
> 1. In MBUS_CTL register translation Throttle Min value.
> 2. In DBUF_CTL_S* register Min Tracker State Service value.

The previous patch just did these same changes, but made the changes to
the existing functions.  It looks like we wound up with two patches
doing the same thing?

> 
> BSpec: 68846, 68864
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 58 ++++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h            |  2 +
>  2 files changed, 57 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index aa1000db3cb9..4d8b960389ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -38,6 +38,7 @@
>  #include "intel_pcode.h"
>  #include "intel_psr.h"
>  #include "skl_watermark.h"
> +#include "skl_watermark_regs.h"
>  #include "vlv_sideband.h"
>  
>  /**
> @@ -1727,7 +1728,12 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
>  
>  static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  {
> -	if (DISPLAY_VER(dev_priv) >= 12) {
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		if (pipe == INVALID_PIPE)
> +			return LNL_CDCLK_CD2X_PIPE_NONE;
> +		else
> +			return LNL_CDCLK_CD2X_PIPE(pipe);

I don't think this change is correct; see note farther down on the
register definitions.

> +	} else if (DISPLAY_VER(dev_priv) >= 12) {
>  		if (pipe == INVALID_PIPE)
>  			return TGL_CDCLK_CD2X_PIPE_NONE;
>  		else
> @@ -1837,6 +1843,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>  		return 1;
>  }
>  
> +static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
> +				    const struct intel_cdclk_config *cdclk_config)
> +{
> +	int min_throttle_val;
> +	int min_tracker_state;
> +	enum dbuf_slice slice;
> +	int mdclk_cdclk_div_ratio;
> +	int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
> +
> +	mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
> +
> +	min_throttle_val = MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
> +
> +	intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK, min_throttle_val);
> +
> +	if (mbus_join)
> +		mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
> +
> +	min_tracker_state = DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
> +
> +	for_each_dbuf_slice(i915, slice)
> +		intel_de_rmw(i915, DBUF_CTL_S(slice),
> +			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> +			     min_tracker_state);
> +}
> +
> +static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
> +				     const struct intel_cdclk_config *cdclk_config,
> +				     u16 waveform)
> +{
> +	if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
> +		/* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
> +		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
> +
> +	dg2_cdclk_squash_program(i915, waveform);
> +
> +	if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
> +		/* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
> +		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
> +}
> +
>  static int cdclk_squash_divider(u16 waveform)
>  {
>  	return hweight16(waveform ?: 0xffff);
> @@ -1938,8 +1985,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	else
>  		clock = cdclk;
>  
> -	if (HAS_CDCLK_SQUASH(dev_priv))
> -		dg2_cdclk_squash_program(dev_priv, waveform);
> +	if (HAS_CDCLK_SQUASH(dev_priv)) {
> +		if (DISPLAY_VER(dev_priv) >= 20)
> +			lnl_cdclk_squash_program(dev_priv, cdclk_config,
> +						 waveform);
> +		else
> +			dg2_cdclk_squash_program(dev_priv, waveform);
> +	}
>  
>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>  		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d5850761a75a..c9639f0f4f49 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5944,6 +5944,8 @@ enum skl_power_gate {
>  #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
>  #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
>  #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
> +#define  LNL_CDCLK_CD2X_PIPE(pipe)	((pipe) << 19)

This doesn't match what I see on bspec 69090:

Bits 21:19
  000 => Pipe A
  010 => Pipe B
  100 => Pipe C
  110 => Pipe D

So the pipe ID (0-3) should actually be shifted by 20 since bit 19 is
always 0 (except for the "none" case).  I think 


Matt

> +#define  LNL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
>  #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
>  #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
>  #define  TGL_CDCLK_CD2X_PIPE(pipe)	BXT_CDCLK_CD2X_PIPE(pipe)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 36/42] drm/i915/lnl: Add support for CDCLK initialization sequence

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:34AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> 
> Add CDCLK initialization sequence changes and CDCLK set frequency
> sequence for LNL platform.
> 
> CDCLK frequency change sequence is different for LNL compared to MTL
> when a change in mdclk/cdclk ratio is observed. Below are changes to be
> made:
> 
> 1. In MBUS_CTL register translation Throttle Min value.
> 2. In DBUF_CTL_S* register Min Tracker State Service value.

The previous patch just did these same changes, but made the changes to
the existing functions.  It looks like we wound up with two patches
doing the same thing?

> 
> BSpec: 68846, 68864
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 58 ++++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h            |  2 +
>  2 files changed, 57 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index aa1000db3cb9..4d8b960389ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -38,6 +38,7 @@
>  #include "intel_pcode.h"
>  #include "intel_psr.h"
>  #include "skl_watermark.h"
> +#include "skl_watermark_regs.h"
>  #include "vlv_sideband.h"
>  
>  /**
> @@ -1727,7 +1728,12 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
>  
>  static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  {
> -	if (DISPLAY_VER(dev_priv) >= 12) {
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		if (pipe == INVALID_PIPE)
> +			return LNL_CDCLK_CD2X_PIPE_NONE;
> +		else
> +			return LNL_CDCLK_CD2X_PIPE(pipe);

I don't think this change is correct; see note farther down on the
register definitions.

> +	} else if (DISPLAY_VER(dev_priv) >= 12) {
>  		if (pipe == INVALID_PIPE)
>  			return TGL_CDCLK_CD2X_PIPE_NONE;
>  		else
> @@ -1837,6 +1843,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>  		return 1;
>  }
>  
> +static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
> +				    const struct intel_cdclk_config *cdclk_config)
> +{
> +	int min_throttle_val;
> +	int min_tracker_state;
> +	enum dbuf_slice slice;
> +	int mdclk_cdclk_div_ratio;
> +	int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
> +
> +	mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
> +
> +	min_throttle_val = MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
> +
> +	intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK, min_throttle_val);
> +
> +	if (mbus_join)
> +		mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
> +
> +	min_tracker_state = DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
> +
> +	for_each_dbuf_slice(i915, slice)
> +		intel_de_rmw(i915, DBUF_CTL_S(slice),
> +			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> +			     min_tracker_state);
> +}
> +
> +static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
> +				     const struct intel_cdclk_config *cdclk_config,
> +				     u16 waveform)
> +{
> +	if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
> +		/* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
> +		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
> +
> +	dg2_cdclk_squash_program(i915, waveform);
> +
> +	if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
> +		/* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
> +		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
> +}
> +
>  static int cdclk_squash_divider(u16 waveform)
>  {
>  	return hweight16(waveform ?: 0xffff);
> @@ -1938,8 +1985,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	else
>  		clock = cdclk;
>  
> -	if (HAS_CDCLK_SQUASH(dev_priv))
> -		dg2_cdclk_squash_program(dev_priv, waveform);
> +	if (HAS_CDCLK_SQUASH(dev_priv)) {
> +		if (DISPLAY_VER(dev_priv) >= 20)
> +			lnl_cdclk_squash_program(dev_priv, cdclk_config,
> +						 waveform);
> +		else
> +			dg2_cdclk_squash_program(dev_priv, waveform);
> +	}
>  
>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>  		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d5850761a75a..c9639f0f4f49 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5944,6 +5944,8 @@ enum skl_power_gate {
>  #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
>  #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
>  #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
> +#define  LNL_CDCLK_CD2X_PIPE(pipe)	((pipe) << 19)

This doesn't match what I see on bspec 69090:

Bits 21:19
  000 => Pipe A
  010 => Pipe B
  100 => Pipe C
  110 => Pipe D

So the pipe ID (0-3) should actually be shifted by 20 since bit 19 is
always 0 (except for the "none" case).  I think 


Matt

> +#define  LNL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
>  #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
>  #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
>  #define  TGL_CDCLK_CD2X_PIPE(pipe)	BXT_CDCLK_CD2X_PIPE(pipe)
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 39/42] drm/i915/lnl: Add pll table for LNL platform

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:37AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> 
> Add PLL Table for Lunar Lake platform.
> 
> BSpec: 68862

I think this should actually be 74224?

> Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 411 ++++++++++++++++++-
>  1 file changed, 406 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6533ec417806..c8da6985c179 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -697,6 +697,261 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
>  	NULL,
>  };
>  
> +static const struct intel_c10pll_state lnl_c10_dp_rbr = {
> +	.clock = 162000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0xB4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x30,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x26,
> +	.pll[5] = 0xC0,

This one should be 0x0C, not 0xC0.

> +	.pll[6] = 0x98,
> +	.pll[7] = 0x46,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xC0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x2,
> +	.pll[16] = 0x84,
> +	.pll[17] = 0x4F,
> +	.pll[18] = 0xE5,
> +	.pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_dp_hbr1 = {
> +	.clock = 270000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0xF4,

And this one should be 0x4, not 0xF4

> +	.pll[1] = 0,
> +	.pll[2] = 0xF8,

A2

Actually, there are several values that seem to have been updated in the
spec since this patch was first written.  But from a quick skim it
actually looks like the LNL table now matches the same values we already
have in the driver for MTL (for both dp and hdmi).  So maybe this patch
isn't necessary anymore and we can just use MTL's tables (including all
the extra pre-computed ones)?


Matt

> +	.pll[3] = 0x0,
> +	.pll[4] = 0x20,
> +	.pll[5] = 0xA0,
> +	.pll[6] = 0x29,
> +	.pll[7] = 0x10,
> +	.pll[8] = 0x1,   /* Verify */
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xA0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x1,
> +	.pll[16] = 0x84,
> +	.pll[17] = 0x4F,
> +	.pll[18] = 0xE5,
> +	.pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_dp_hbr2 = {
> +	.clock = 540000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0xF4,
> +	.pll[1] = 0,
> +	.pll[2] = 0xF8,
> +	.pll[3] = 0,
> +	.pll[4] = 0x20,
> +	.pll[5] = 0xA0,
> +	.pll[6] = 0x29,
> +	.pll[7] = 0x10,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xA0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0,
> +	.pll[16] = 0x84,
> +	.pll[17] = 0x4F,
> +	.pll[18] = 0xE5,
> +	.pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_dp_hbr3 = {
> +	.clock = 810000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0x34,
> +	.pll[1] = 0,
> +	.pll[2] = 0x84,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x30,
> +	.pll[5] = 0xF0,
> +	.pll[6] = 0x3D,
> +	.pll[7] = 0x98,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xF0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0,
> +	.pll[16] = 0x84,
> +	.pll[17] = 0x0F,
> +	.pll[18] = 0xE5,
> +	.pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_edp_r216 = {
> +	.clock = 216000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0x4,
> +	.pll[1] = 0,
> +	.pll[2] = 0xA2,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x33,
> +	.pll[5] = 0x10,
> +	.pll[6] = 0x75,
> +	.pll[7] = 0xB3,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x2,
> +	.pll[16] = 0x85,
> +	.pll[17] = 0x20,
> +	.pll[18] = 0xE6,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_edp_r243 = {
> +	.clock = 243000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0x34,
> +	.pll[1] = 0,
> +	.pll[2] = 0xDA,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x39,
> +	.pll[5] = 0x12,
> +	.pll[6] = 0xE3,
> +	.pll[7] = 0xE9,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0x20,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x2,
> +	.pll[16] = 0x85,
> +	.pll[17] = 0xA0,
> +	.pll[18] = 0xE6,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_edp_r324 = {
> +	.clock = 324000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0xB4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x30,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x26,
> +	.pll[5] = 0xC0,
> +	.pll[6] = 0x98,
> +	.pll[7] = 0x46,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xC0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x1,
> +	.pll[16] = 0x85,
> +	.pll[17] = 0x60,
> +	.pll[18] = 0xE6,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_edp_r432 = {
> +	.clock = 432000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0x4,
> +	.pll[1] = 0,
> +	.pll[2] = 0xA2,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x33,
> +	.pll[5] = 0x10,
> +	.pll[6] = 0x75,
> +	.pll[7] = 0xB3,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x1,
> +	.pll[16] = 0x85,
> +	.pll[17] = 0x20,
> +	.pll[18] = 0xE6,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_edp_r675 = {
> +	.clock = 675000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0xB4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x3E,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0xA8,
> +	.pll[5] = 0xC8,
> +	.pll[6] = 0x33,
> +	.pll[7] = 0x54,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xC8,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0,
> +	.pll[16] = 0x85,
> +	.pll[17] = 0xA0,
> +	.pll[18] = 0xE6,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state * const lnl_c10_dp_tables[] = {
> +	&lnl_c10_dp_rbr,
> +	&lnl_c10_dp_hbr1,
> +	&lnl_c10_dp_hbr2,
> +	&lnl_c10_dp_hbr3,
> +	NULL,
> +};
> +
> +static const struct intel_c10pll_state * const lnl_c10_edp_tables[] = {
> +	&lnl_c10_dp_rbr,
> +	&lnl_c10_edp_r216,
> +	&lnl_c10_edp_r243,
> +	&lnl_c10_dp_hbr1,
> +	&lnl_c10_edp_r324,
> +	&lnl_c10_edp_r432,
> +	&lnl_c10_dp_hbr2,
> +	&lnl_c10_edp_r675,
> +	&lnl_c10_dp_hbr3,
> +	NULL,
> +};
> +
>  /* C20 basic DP 1.4 tables */
>  static const struct intel_c20pll_state mtl_c20_dp_rbr = {
>  	.link_bit_rate = 162000,
> @@ -1474,6 +1729,140 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
>  	NULL,
>  };
>  
> +/*
> + * HDMI link rates with 38.4 MHz reference clock.
> + */
> +
> +static const struct intel_c10pll_state lnl_c10_hdmi_252 = {
> +	.clock = 25200,
> +	.pll[0] = 0x4,
> +	.pll[1] = 0,
> +	.pll[2] = 0xB2,
> +	.pll[3] = 0,
> +	.pll[4] = 0,
> +	.pll[5] = 0,
> +	.pll[6] = 0,
> +	.pll[7] = 0,
> +	.pll[8] = 0x20,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0xD,
> +	.pll[16] = 0x0A,
> +	.pll[17] = 0xA0,
> +	.pll[18] = 0x87,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_hdmi_27_0 = {
> +	.clock = 27000,
> +	.pll[0] = 0x34,
> +	.pll[1] = 0,
> +	.pll[2] = 0xC0,
> +	.pll[3] = 0,
> +	.pll[4] = 0,
> +	.pll[5] = 0,
> +	.pll[6] = 0,
> +	.pll[7] = 0,
> +	.pll[8] = 0x20,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0x80,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0xD,
> +	.pll[16] = 0x6,
> +	.pll[17] = 0xE0,
> +	.pll[18] = 0x84,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_hdmi_74_2 = {
> +	.clock = 74250,
> +	.pll[0] = 0xF4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x7A,
> +	.pll[3] = 0,
> +	.pll[4] = 0,
> +	.pll[5] = 0,
> +	.pll[6] = 0,
> +	.pll[7] = 0,
> +	.pll[8] = 0x20,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0x58,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0xB,
> +	.pll[16] = 0x6,
> +	.pll[17] = 0x20,
> +	.pll[18] = 0x85,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_hdmi_148_5 = {
> +	.clock = 148500,
> +	.pll[0] = 0xF4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x7A,
> +	.pll[3] = 0,
> +	.pll[4] = 0,
> +	.pll[5] = 0,
> +	.pll[6] = 0,
> +	.pll[7] = 0,
> +	.pll[8] = 0x20,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0x58,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0xA,
> +	.pll[16] = 0x6,
> +	.pll[17] = 0x20,
> +	.pll[18] = 0x85,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_hdmi_594 = {
> +	.clock = 594000,
> +	.pll[0] = 0xF4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x7A,
> +	.pll[3] = 0,
> +	.pll[4] = 0,
> +	.pll[5] = 0,
> +	.pll[6] = 0,
> +	.pll[7] = 0,
> +	.pll[8] = 0x20,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0x58,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x8,
> +	.pll[16] = 0x6,
> +	.pll[17] = 0x20,
> +	.pll[18] = 0x85,
> +	.pll[19] = 0x2F,
> +};
> +
> +/* Consolidated Table */
> +static const struct intel_c10pll_state * const lnl_c10_hdmi_tables[] = {
> +	&lnl_c10_hdmi_252,
> +	&lnl_c10_hdmi_27_0,
> +	&lnl_c10_hdmi_74_2,
> +	&lnl_c10_hdmi_148_5,
> +	&lnl_c10_hdmi_594,
> +	NULL,
> +};
> +
>  static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
>  	.link_bit_rate = 25175,
>  	.clock = 25175,
> @@ -1765,13 +2154,25 @@ static const struct intel_c10pll_state * const *
>  intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
>  			struct intel_encoder *encoder)
>  {
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
>  	if (intel_crtc_has_dp_encoder(crtc_state)) {
> -		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> -			return mtl_c10_edp_tables;
> -		else
> -			return mtl_c10_dp_tables;
> +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +			if (DISPLAY_VER(i915) >= 20)
> +				return lnl_c10_edp_tables;
> +			else
> +				return mtl_c10_edp_tables;
> +		} else {
> +			if (DISPLAY_VER(i915) >= 20)
> +				return lnl_c10_dp_tables;
> +			else
> +				return mtl_c10_dp_tables;
> +		}
>  	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> -		return mtl_c10_hdmi_tables;
> +		if (DISPLAY_VER(i915) >= 20)
> +			return lnl_c10_hdmi_tables;
> +		else
> +			return mtl_c10_hdmi_tables;
>  	}
>  
>  	MISSING_CASE(encoder->type);
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 39/42] drm/i915/lnl: Add pll table for LNL platform

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:37AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> 
> Add PLL Table for Lunar Lake platform.
> 
> BSpec: 68862

I think this should actually be 74224?

> Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 411 ++++++++++++++++++-
>  1 file changed, 406 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6533ec417806..c8da6985c179 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -697,6 +697,261 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
>  	NULL,
>  };
>  
> +static const struct intel_c10pll_state lnl_c10_dp_rbr = {
> +	.clock = 162000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0xB4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x30,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x26,
> +	.pll[5] = 0xC0,

This one should be 0x0C, not 0xC0.

> +	.pll[6] = 0x98,
> +	.pll[7] = 0x46,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xC0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x2,
> +	.pll[16] = 0x84,
> +	.pll[17] = 0x4F,
> +	.pll[18] = 0xE5,
> +	.pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_dp_hbr1 = {
> +	.clock = 270000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0xF4,

And this one should be 0x4, not 0xF4

> +	.pll[1] = 0,
> +	.pll[2] = 0xF8,

A2

Actually, there are several values that seem to have been updated in the
spec since this patch was first written.  But from a quick skim it
actually looks like the LNL table now matches the same values we already
have in the driver for MTL (for both dp and hdmi).  So maybe this patch
isn't necessary anymore and we can just use MTL's tables (including all
the extra pre-computed ones)?


Matt

> +	.pll[3] = 0x0,
> +	.pll[4] = 0x20,
> +	.pll[5] = 0xA0,
> +	.pll[6] = 0x29,
> +	.pll[7] = 0x10,
> +	.pll[8] = 0x1,   /* Verify */
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xA0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x1,
> +	.pll[16] = 0x84,
> +	.pll[17] = 0x4F,
> +	.pll[18] = 0xE5,
> +	.pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_dp_hbr2 = {
> +	.clock = 540000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0xF4,
> +	.pll[1] = 0,
> +	.pll[2] = 0xF8,
> +	.pll[3] = 0,
> +	.pll[4] = 0x20,
> +	.pll[5] = 0xA0,
> +	.pll[6] = 0x29,
> +	.pll[7] = 0x10,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xA0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0,
> +	.pll[16] = 0x84,
> +	.pll[17] = 0x4F,
> +	.pll[18] = 0xE5,
> +	.pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_dp_hbr3 = {
> +	.clock = 810000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0x34,
> +	.pll[1] = 0,
> +	.pll[2] = 0x84,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x30,
> +	.pll[5] = 0xF0,
> +	.pll[6] = 0x3D,
> +	.pll[7] = 0x98,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xF0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0,
> +	.pll[16] = 0x84,
> +	.pll[17] = 0x0F,
> +	.pll[18] = 0xE5,
> +	.pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_edp_r216 = {
> +	.clock = 216000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0x4,
> +	.pll[1] = 0,
> +	.pll[2] = 0xA2,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x33,
> +	.pll[5] = 0x10,
> +	.pll[6] = 0x75,
> +	.pll[7] = 0xB3,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x2,
> +	.pll[16] = 0x85,
> +	.pll[17] = 0x20,
> +	.pll[18] = 0xE6,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_edp_r243 = {
> +	.clock = 243000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0x34,
> +	.pll[1] = 0,
> +	.pll[2] = 0xDA,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x39,
> +	.pll[5] = 0x12,
> +	.pll[6] = 0xE3,
> +	.pll[7] = 0xE9,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0x20,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x2,
> +	.pll[16] = 0x85,
> +	.pll[17] = 0xA0,
> +	.pll[18] = 0xE6,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_edp_r324 = {
> +	.clock = 324000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0xB4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x30,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x26,
> +	.pll[5] = 0xC0,
> +	.pll[6] = 0x98,
> +	.pll[7] = 0x46,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xC0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x1,
> +	.pll[16] = 0x85,
> +	.pll[17] = 0x60,
> +	.pll[18] = 0xE6,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_edp_r432 = {
> +	.clock = 432000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0x4,
> +	.pll[1] = 0,
> +	.pll[2] = 0xA2,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0x33,
> +	.pll[5] = 0x10,
> +	.pll[6] = 0x75,
> +	.pll[7] = 0xB3,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x1,
> +	.pll[16] = 0x85,
> +	.pll[17] = 0x20,
> +	.pll[18] = 0xE6,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_edp_r675 = {
> +	.clock = 675000,
> +	.tx = 0x10,
> +	.cmn = 0x21,
> +	.pll[0] = 0xB4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x3E,
> +	.pll[3] = 0x1,
> +	.pll[4] = 0xA8,
> +	.pll[5] = 0xC8,
> +	.pll[6] = 0x33,
> +	.pll[7] = 0x54,
> +	.pll[8] = 0x1,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0xC8,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0,
> +	.pll[16] = 0x85,
> +	.pll[17] = 0xA0,
> +	.pll[18] = 0xE6,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state * const lnl_c10_dp_tables[] = {
> +	&lnl_c10_dp_rbr,
> +	&lnl_c10_dp_hbr1,
> +	&lnl_c10_dp_hbr2,
> +	&lnl_c10_dp_hbr3,
> +	NULL,
> +};
> +
> +static const struct intel_c10pll_state * const lnl_c10_edp_tables[] = {
> +	&lnl_c10_dp_rbr,
> +	&lnl_c10_edp_r216,
> +	&lnl_c10_edp_r243,
> +	&lnl_c10_dp_hbr1,
> +	&lnl_c10_edp_r324,
> +	&lnl_c10_edp_r432,
> +	&lnl_c10_dp_hbr2,
> +	&lnl_c10_edp_r675,
> +	&lnl_c10_dp_hbr3,
> +	NULL,
> +};
> +
>  /* C20 basic DP 1.4 tables */
>  static const struct intel_c20pll_state mtl_c20_dp_rbr = {
>  	.link_bit_rate = 162000,
> @@ -1474,6 +1729,140 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
>  	NULL,
>  };
>  
> +/*
> + * HDMI link rates with 38.4 MHz reference clock.
> + */
> +
> +static const struct intel_c10pll_state lnl_c10_hdmi_252 = {
> +	.clock = 25200,
> +	.pll[0] = 0x4,
> +	.pll[1] = 0,
> +	.pll[2] = 0xB2,
> +	.pll[3] = 0,
> +	.pll[4] = 0,
> +	.pll[5] = 0,
> +	.pll[6] = 0,
> +	.pll[7] = 0,
> +	.pll[8] = 0x20,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0xD,
> +	.pll[16] = 0x0A,
> +	.pll[17] = 0xA0,
> +	.pll[18] = 0x87,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_hdmi_27_0 = {
> +	.clock = 27000,
> +	.pll[0] = 0x34,
> +	.pll[1] = 0,
> +	.pll[2] = 0xC0,
> +	.pll[3] = 0,
> +	.pll[4] = 0,
> +	.pll[5] = 0,
> +	.pll[6] = 0,
> +	.pll[7] = 0,
> +	.pll[8] = 0x20,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0x80,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0xD,
> +	.pll[16] = 0x6,
> +	.pll[17] = 0xE0,
> +	.pll[18] = 0x84,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_hdmi_74_2 = {
> +	.clock = 74250,
> +	.pll[0] = 0xF4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x7A,
> +	.pll[3] = 0,
> +	.pll[4] = 0,
> +	.pll[5] = 0,
> +	.pll[6] = 0,
> +	.pll[7] = 0,
> +	.pll[8] = 0x20,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0x58,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0xB,
> +	.pll[16] = 0x6,
> +	.pll[17] = 0x20,
> +	.pll[18] = 0x85,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_hdmi_148_5 = {
> +	.clock = 148500,
> +	.pll[0] = 0xF4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x7A,
> +	.pll[3] = 0,
> +	.pll[4] = 0,
> +	.pll[5] = 0,
> +	.pll[6] = 0,
> +	.pll[7] = 0,
> +	.pll[8] = 0x20,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0x58,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0xA,
> +	.pll[16] = 0x6,
> +	.pll[17] = 0x20,
> +	.pll[18] = 0x85,
> +	.pll[19] = 0x2F,
> +};
> +
> +static const struct intel_c10pll_state lnl_c10_hdmi_594 = {
> +	.clock = 594000,
> +	.pll[0] = 0xF4,
> +	.pll[1] = 0,
> +	.pll[2] = 0x7A,
> +	.pll[3] = 0,
> +	.pll[4] = 0,
> +	.pll[5] = 0,
> +	.pll[6] = 0,
> +	.pll[7] = 0,
> +	.pll[8] = 0x20,
> +	.pll[9] = 0x1,
> +	.pll[10] = 0,
> +	.pll[11] = 0,
> +	.pll[12] = 0x58,
> +	.pll[13] = 0,
> +	.pll[14] = 0,
> +	.pll[15] = 0x8,
> +	.pll[16] = 0x6,
> +	.pll[17] = 0x20,
> +	.pll[18] = 0x85,
> +	.pll[19] = 0x2F,
> +};
> +
> +/* Consolidated Table */
> +static const struct intel_c10pll_state * const lnl_c10_hdmi_tables[] = {
> +	&lnl_c10_hdmi_252,
> +	&lnl_c10_hdmi_27_0,
> +	&lnl_c10_hdmi_74_2,
> +	&lnl_c10_hdmi_148_5,
> +	&lnl_c10_hdmi_594,
> +	NULL,
> +};
> +
>  static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
>  	.link_bit_rate = 25175,
>  	.clock = 25175,
> @@ -1765,13 +2154,25 @@ static const struct intel_c10pll_state * const *
>  intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
>  			struct intel_encoder *encoder)
>  {
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
>  	if (intel_crtc_has_dp_encoder(crtc_state)) {
> -		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> -			return mtl_c10_edp_tables;
> -		else
> -			return mtl_c10_dp_tables;
> +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +			if (DISPLAY_VER(i915) >= 20)
> +				return lnl_c10_edp_tables;
> +			else
> +				return mtl_c10_edp_tables;
> +		} else {
> +			if (DISPLAY_VER(i915) >= 20)
> +				return lnl_c10_dp_tables;
> +			else
> +				return mtl_c10_dp_tables;
> +		}
>  	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> -		return mtl_c10_hdmi_tables;
> +		if (DISPLAY_VER(i915) >= 20)
> +			return lnl_c10_hdmi_tables;
> +		else
> +			return mtl_c10_hdmi_tables;
>  	}
>  
>  	MISSING_CASE(encoder->type);
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 40/42] drm/i915/lnl: Add support to check c10 phy link rate

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:38AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> 
> Add support to check c10 phy link rate for LNL in
> intel_c10_phy_check_hdmi_link_rate() function.

If it turns out the LNL tables from the previous patch aren't necessary,
then we should be able to drop this one as well.


Matt

> 
> BSpec: 68862
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index c8da6985c179..d9c43f3b4f34 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2137,11 +2137,16 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
>  	NULL,
>  };
>  
> -static int intel_c10_phy_check_hdmi_link_rate(int clock)
> +static int intel_c10_phy_check_hdmi_link_rate(struct drm_i915_private *i915, int clock)
>  {
> -	const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
> +	const struct intel_c10pll_state * const *tables;
>  	int i;
>  
> +	if (DISPLAY_VER(i915) >= 20)
> +		tables = lnl_c10_hdmi_tables;
> +	else
> +		tables = mtl_c10_hdmi_tables;
> +
>  	for (i = 0; tables[i]; i++) {
>  		if (clock == tables[i]->clock)
>  			return MODE_OK;
> @@ -2414,7 +2419,7 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
>  	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>  
>  	if (intel_is_c10phy(i915, phy))
> -		return intel_c10_phy_check_hdmi_link_rate(clock);
> +		return intel_c10_phy_check_hdmi_link_rate(i915, clock);
>  	return intel_c20_phy_check_hdmi_link_rate(clock);
>  }
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 40/42] drm/i915/lnl: Add support to check c10 phy link rate

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:38AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> 
> Add support to check c10 phy link rate for LNL in
> intel_c10_phy_check_hdmi_link_rate() function.

If it turns out the LNL tables from the previous patch aren't necessary,
then we should be able to drop this one as well.


Matt

> 
> BSpec: 68862
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index c8da6985c179..d9c43f3b4f34 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2137,11 +2137,16 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
>  	NULL,
>  };
>  
> -static int intel_c10_phy_check_hdmi_link_rate(int clock)
> +static int intel_c10_phy_check_hdmi_link_rate(struct drm_i915_private *i915, int clock)
>  {
> -	const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
> +	const struct intel_c10pll_state * const *tables;
>  	int i;
>  
> +	if (DISPLAY_VER(i915) >= 20)
> +		tables = lnl_c10_hdmi_tables;
> +	else
> +		tables = mtl_c10_hdmi_tables;
> +
>  	for (i = 0; tables[i]; i++) {
>  		if (clock == tables[i]->clock)
>  			return MODE_OK;
> @@ -2414,7 +2419,7 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
>  	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>  
>  	if (intel_is_c10phy(i915, phy))
> -		return intel_c10_phy_check_hdmi_link_rate(clock);
> +		return intel_c10_phy_check_hdmi_link_rate(i915, clock);
>  	return intel_c20_phy_check_hdmi_link_rate(clock);
>  }
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 42/42] drm/xe/lnl: Enable the display support

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:40AM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> Enable the display support for LUNARLAKE
> 
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_pci.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 7fb00ea410a6..f723e19e8ca5 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -337,6 +337,7 @@ static const struct xe_device_desc mtl_desc = {
>  
>  static const struct xe_device_desc lnl_desc = {
>  	PLATFORM(XE_LUNARLAKE),
> +	.has_display = true,
>  	.require_force_probe = true,
>  };
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 42/42] drm/xe/lnl: Enable the display support

[Matt Roper]

On Wed, Aug 23, 2023 at 10:07:40AM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> Enable the display support for LUNARLAKE
> 
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_pci.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 7fb00ea410a6..f723e19e8ca5 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -337,6 +337,7 @@ static const struct xe_device_desc mtl_desc = {
>  
>  static const struct xe_device_desc lnl_desc = {
>  	PLATFORM(XE_LUNARLAKE),
> +	.has_display = true,
>  	.require_force_probe = true,
>  };
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 01:49:21PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote:
>> LNL's south display uses the same table as MTP. Check for LNL's fake PCH
>> to make it consistent with the other checks.
>>
>> The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
>> other cases, uses the same as the previous platform.
>>
>> Bspec: 68971, 20124
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bios.c  | 2 +-
>>  drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
>>  2 files changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>> index 097c1f23d3ae..3772b91e155c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> @@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
>>  	const u8 *ddc_pin_map;
>>  	int i, n_entries;
>>
>> -	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
>> +	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {
>
>The LUNARLAKE here vs PCH_LNL below seems inconsistent.  Either way, we
>should probably put the newer platform first in the condition.
>
>Aside from those

If we drop IS_LUNARLAKE, then we need to check for something else here.
What about doing this?


	if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {

?

>
>        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>>  		ddc_pin_map = adlp_ddc_pin_map;
>>  		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
>>  	} else if (IS_ALDERLAKE_S(i915)) {
>> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
>> index e95ddb580ef6..801fabbccf7e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
>> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
>> @@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
>>  	const struct gmbus_pin *pins;
>>  	size_t size;
>>
>> -	if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
>> +	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
>> +		pins = gmbus_pins_mtp;
>> +		size = ARRAY_SIZE(gmbus_pins_mtp);
>> +	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
>>  		pins = gmbus_pins_dg2;
>>  		size = ARRAY_SIZE(gmbus_pins_dg2);
>>  	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 01:49:21PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote:
>> LNL's south display uses the same table as MTP. Check for LNL's fake PCH
>> to make it consistent with the other checks.
>>
>> The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
>> other cases, uses the same as the previous platform.
>>
>> Bspec: 68971, 20124
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bios.c  | 2 +-
>>  drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
>>  2 files changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>> index 097c1f23d3ae..3772b91e155c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> @@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
>>  	const u8 *ddc_pin_map;
>>  	int i, n_entries;
>>
>> -	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
>> +	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {
>
>The LUNARLAKE here vs PCH_LNL below seems inconsistent.  Either way, we
>should probably put the newer platform first in the condition.
>
>Aside from those

If we drop IS_LUNARLAKE, then we need to check for something else here.
What about doing this?


	if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {

?

>
>        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>>  		ddc_pin_map = adlp_ddc_pin_map;
>>  		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
>>  	} else if (IS_ALDERLAKE_S(i915)) {
>> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
>> index e95ddb580ef6..801fabbccf7e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
>> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
>> @@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
>>  	const struct gmbus_pin *pins;
>>  	size_t size;
>>
>> -	if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
>> +	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
>> +		pins = gmbus_pins_mtp;
>> +		size = ARRAY_SIZE(gmbus_pins_mtp);
>> +	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
>>  		pins = gmbus_pins_dg2;
>>  		size = ARRAY_SIZE(gmbus_pins_dg2);
>>  	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-gfx] [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane

[Kahola, Mika]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Wednesday, August 23, 2023 8:08 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>; Kahola, Mika <mika.kahola@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
> 
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> Previously we always updated DBuf MBUS CTL and DBUF CTL regs after CDCLK has been changed(CDCLK_CTL), however for Xe2-
> LPD we can't do like that anymore. According to BSpec, we have to first update DBuf regs and then write CDCLK regs, when CDCLK
> is decreased, which we do in post plane.
> 
> So now we do CDCLK post plane update only after DBuf regs are written (CDCLK/MDCLK separation requires MDCLK/CDCLK ratio
> to be written to DBuf regs).
> 
> Cc: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f9eda7ad892e..de813831a5cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7113,7 +7113,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>  	dev_priv->display.funcs.display->commit_modeset_enables(state);
> 
> -	if (state->modeset)
> +	if (state->modeset && DISPLAY_VER(dev_priv) < 20)
>  		intel_set_cdclk_post_plane_update(state);
> 
>  	intel_wait_for_vblank_workers(state);
> @@ -7160,6 +7160,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	intel_dbuf_post_plane_update(state);
>  	intel_psr_post_plane_update(state);
> 
> +	if (state->modeset && DISPLAY_VER(dev_priv) >= 20)
> +		intel_set_cdclk_post_plane_update(state);
> +
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>  		intel_post_plane_update(state, crtc);
> 
> --
> 2.40.1

Re: [Intel-xe] [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane

[Kahola, Mika]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Wednesday, August 23, 2023 8:08 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>; Kahola, Mika <mika.kahola@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
> 
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> Previously we always updated DBuf MBUS CTL and DBUF CTL regs after CDCLK has been changed(CDCLK_CTL), however for Xe2-
> LPD we can't do like that anymore. According to BSpec, we have to first update DBuf regs and then write CDCLK regs, when CDCLK
> is decreased, which we do in post plane.
> 
> So now we do CDCLK post plane update only after DBuf regs are written (CDCLK/MDCLK separation requires MDCLK/CDCLK ratio
> to be written to DBuf regs).
> 
> Cc: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f9eda7ad892e..de813831a5cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7113,7 +7113,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>  	dev_priv->display.funcs.display->commit_modeset_enables(state);
> 
> -	if (state->modeset)
> +	if (state->modeset && DISPLAY_VER(dev_priv) < 20)
>  		intel_set_cdclk_post_plane_update(state);
> 
>  	intel_wait_for_vblank_workers(state);
> @@ -7160,6 +7160,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	intel_dbuf_post_plane_update(state);
>  	intel_psr_post_plane_update(state);
> 
> +	if (state->modeset && DISPLAY_VER(dev_priv) >= 20)
> +		intel_set_cdclk_post_plane_update(state);
> +
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>  		intel_post_plane_update(state, crtc);
> 
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates

[Kahola, Mika]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Wednesday, August 23, 2023 8:08 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>; Kahola, Mika <mika.kahola@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates
> 
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> According to BSpec we need to write the MBUS CTL and DBUF CTL both for increasing CDCLK case (pre plane) and for decreasing
> CDCLK case (post plane). Make sure those updates are in place for Xe2-LPD.
> 
> Since the mbus update is not only on pre-enable anymore, also rename the function accordingly.
> 
> Cc: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 79454b4d99e3..77a4c85538c2 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3493,7 +3493,7 @@ static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>   * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
>   * update the request state of all DBUS slices.
>   */
> -static void update_mbus_pre_enable(struct intel_atomic_state *state)
> +static void update_mbus(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	u32 mbus_ctl, dbuf_min_tracker_val;
> @@ -3552,7 +3552,7 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> 
>  	WARN_ON(!new_dbuf_state->base.changed);
> 
> -	update_mbus_pre_enable(state);
> +	update_mbus(state);
>  	gen9_dbuf_slices_update(i915,
>  				old_dbuf_state->enabled_slices |
>  				new_dbuf_state->enabled_slices);
> @@ -3574,6 +3574,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> 
>  	WARN_ON(!new_dbuf_state->base.changed);
> 
> +	if (DISPLAY_VER(i915) >= 20)
> +		update_mbus(state);
> +
>  	gen9_dbuf_slices_update(i915,
>  				new_dbuf_state->enabled_slices);
>  }
> --
> 2.40.1

Re: [Intel-xe] [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates

[Kahola, Mika]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Wednesday, August 23, 2023 8:08 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>; Kahola, Mika <mika.kahola@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates
> 
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> According to BSpec we need to write the MBUS CTL and DBUF CTL both for increasing CDCLK case (pre plane) and for decreasing
> CDCLK case (post plane). Make sure those updates are in place for Xe2-LPD.
> 
> Since the mbus update is not only on pre-enable anymore, also rename the function accordingly.
> 
> Cc: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 79454b4d99e3..77a4c85538c2 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3493,7 +3493,7 @@ static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>   * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
>   * update the request state of all DBUS slices.
>   */
> -static void update_mbus_pre_enable(struct intel_atomic_state *state)
> +static void update_mbus(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	u32 mbus_ctl, dbuf_min_tracker_val;
> @@ -3552,7 +3552,7 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> 
>  	WARN_ON(!new_dbuf_state->base.changed);
> 
> -	update_mbus_pre_enable(state);
> +	update_mbus(state);
>  	gen9_dbuf_slices_update(i915,
>  				old_dbuf_state->enabled_slices |
>  				new_dbuf_state->enabled_slices);
> @@ -3574,6 +3574,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> 
>  	WARN_ON(!new_dbuf_state->base.changed);
> 
> +	if (DISPLAY_VER(i915) >= 20)
> +		update_mbus(state);
> +
>  	gen9_dbuf_slices_update(i915,
>  				new_dbuf_state->enabled_slices);
>  }
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 19/42] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas De
> Marchi
> Sent: Wednesday, August 23, 2023 10:07 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [Intel-gfx] [PATCH 19/42] drm/i915/xe2lpd: Don't try to program
> PLANE_AUX_DIST
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers like
> PLANE_AUX_DIST.  However we currently have HAS_FLAT_CCS hardcoded to 0
> since compression isn't ready; we need to make sure this doesn't cause the
> display code to go back to trying to write this register.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>	
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 3c212d8401c8..4dfd8b627147 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1254,7 +1254,7 @@ icl_plane_update_noarm(struct intel_plane *plane,
>  	}
> 
>  	/* FLAT CCS doesn't need to program AUX_DIST */
> -	if (!HAS_FLAT_CCS(dev_priv))
> +	if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20)
>  		intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
>  				  skl_plane_aux_dist(plane_state, color_plane));
> 
> --
> 2.40.1

Re: [Intel-xe] [Intel-gfx] [PATCH 19/42] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas De
> Marchi
> Sent: Wednesday, August 23, 2023 10:07 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [Intel-gfx] [PATCH 19/42] drm/i915/xe2lpd: Don't try to program
> PLANE_AUX_DIST
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers like
> PLANE_AUX_DIST.  However we currently have HAS_FLAT_CCS hardcoded to 0
> since compression isn't ready; we need to make sure this doesn't cause the
> display code to go back to trying to write this register.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>	
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 3c212d8401c8..4dfd8b627147 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1254,7 +1254,7 @@ icl_plane_update_noarm(struct intel_plane *plane,
>  	}
> 
>  	/* FLAT CCS doesn't need to program AUX_DIST */
> -	if (!HAS_FLAT_CCS(dev_priv))
> +	if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20)
>  		intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
>  				  skl_plane_aux_dist(plane_state, color_plane));
> 
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 22/42] drm/i915/xe2lpd: Add DC state support

[Srivatsa, Anusha]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Wednesday, August 23, 2023 10:07 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D <matthew.d.roper@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: [PATCH 22/42] drm/i915/xe2lpd: Add DC state support
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists).  The overall
> programming and requirements to enter DC states are similar to those of
> Xe_LPD+ although AUX transactions do not require DC5/DC6 exit as they did
> previously.
> 
> Bspec: 68851, 68857, 68886, 69115
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>	

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  .../drm/i915/display/intel_display_power.c    |  4 +++-
>  .../i915/display/intel_display_power_map.c    | 19 +++++++++++++++++++
>  2 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7e2059abae9a..508a3225d9f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -944,7 +944,9 @@ static u32 get_allowed_dc_mask(const struct
> drm_i915_private *dev_priv,
>  	if (!HAS_DISPLAY(dev_priv))
>  		return 0;
> 
> -	if (IS_DG2(dev_priv))
> +	if (DISPLAY_VER(dev_priv) >= 20)
> +		max_dc = 2;
> +	else if (IS_DG2(dev_priv))
>  		max_dc = 1;
>  	else if (IS_DG1(dev_priv))
>  		max_dc = 3;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index cef3b313c9f5..d74a742437c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1570,9 +1570,28 @@ static const struct i915_power_well_desc
> xe2lpd_power_wells_pica[] = {
>  	},
>  };
> 
> +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off,
> +	POWER_DOMAIN_DC_OFF,
> +	XELPD_PW_C_POWER_DOMAINS,
> +	XELPD_PW_D_POWER_DOMAINS,
> +	POWER_DOMAIN_AUDIO_MMIO,
> +	POWER_DOMAIN_MODESET,
> +	POWER_DOMAIN_INIT);
> +
> +static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = {
> +	{
> +		.instances = &I915_PW_INSTANCES(
> +			I915_PW("DC_off", &xe2lpd_pwdoms_dc_off,
> +				.id = SKL_DISP_DC_OFF),
> +		),
> +		.ops = &gen9_dc_off_power_well_ops,
> +	},
> +};
> +
>  static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
>  	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
>  	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> +	I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff),
>  	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
>  	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
>  };
> --
> 2.40.1

Re: [Intel-xe] [PATCH 22/42] drm/i915/xe2lpd: Add DC state support

[Srivatsa, Anusha]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Wednesday, August 23, 2023 10:07 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D <matthew.d.roper@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: [PATCH 22/42] drm/i915/xe2lpd: Add DC state support
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists).  The overall
> programming and requirements to enter DC states are similar to those of
> Xe_LPD+ although AUX transactions do not require DC5/DC6 exit as they did
> previously.
> 
> Bspec: 68851, 68857, 68886, 69115
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>	

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  .../drm/i915/display/intel_display_power.c    |  4 +++-
>  .../i915/display/intel_display_power_map.c    | 19 +++++++++++++++++++
>  2 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7e2059abae9a..508a3225d9f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -944,7 +944,9 @@ static u32 get_allowed_dc_mask(const struct
> drm_i915_private *dev_priv,
>  	if (!HAS_DISPLAY(dev_priv))
>  		return 0;
> 
> -	if (IS_DG2(dev_priv))
> +	if (DISPLAY_VER(dev_priv) >= 20)
> +		max_dc = 2;
> +	else if (IS_DG2(dev_priv))
>  		max_dc = 1;
>  	else if (IS_DG1(dev_priv))
>  		max_dc = 3;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index cef3b313c9f5..d74a742437c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1570,9 +1570,28 @@ static const struct i915_power_well_desc
> xe2lpd_power_wells_pica[] = {
>  	},
>  };
> 
> +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off,
> +	POWER_DOMAIN_DC_OFF,
> +	XELPD_PW_C_POWER_DOMAINS,
> +	XELPD_PW_D_POWER_DOMAINS,
> +	POWER_DOMAIN_AUDIO_MMIO,
> +	POWER_DOMAIN_MODESET,
> +	POWER_DOMAIN_INIT);
> +
> +static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = {
> +	{
> +		.instances = &I915_PW_INSTANCES(
> +			I915_PW("DC_off", &xe2lpd_pwdoms_dc_off,
> +				.id = SKL_DISP_DC_OFF),
> +		),
> +		.ops = &gen9_dc_off_power_well_ops,
> +	},
> +};
> +
>  static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
>  	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
>  	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> +	I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff),
>  	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
>  	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
>  };
> --
> 2.40.1

Re: [Intel-gfx] [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

[Matt Roper]

On Thu, Aug 24, 2023 at 09:25:54PM -0700, Lucas De Marchi wrote:
> On Wed, Aug 23, 2023 at 01:49:21PM -0700, Matt Roper wrote:
> > On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote:
> > > LNL's south display uses the same table as MTP. Check for LNL's fake PCH
> > > to make it consistent with the other checks.
> > > 
> > > The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
> > > other cases, uses the same as the previous platform.
> > > 
> > > Bspec: 68971, 20124
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_bios.c  | 2 +-
> > >  drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
> > >  2 files changed, 5 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> > > index 097c1f23d3ae..3772b91e155c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > > @@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
> > >  	const u8 *ddc_pin_map;
> > >  	int i, n_entries;
> > > 
> > > -	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
> > > +	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {
> > 
> > The LUNARLAKE here vs PCH_LNL below seems inconsistent.  Either way, we
> > should probably put the newer platform first in the condition.
> > 
> > Aside from those
> 
> If we drop IS_LUNARLAKE, then we need to check for something else here.
> What about doing this?
> 
> 
> 	if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
> 
> ?

Yeah, that's fine in the short term.  Although I wonder if moving
PCH_LNL before the discrete GPUs might simplify the various conditions
that need to match on SDE behavior since it's probably closer to the MTL
SDE than to the discrete SDEs?  I haven't looked through all the
conditions to see which order is simplest overall.

Longer term I think we need to replace the whole intel_pch enum with an
intel_sde enum or something since this stuff generally isn't related to
PCH anymore, and we should be looking at different things to determine
the exact version of the SDE logic.

 - For MTL, both NDE and SDE live on the same die (SOC); PCH isn't
   involved.
 - For LNL, NDE lives on the compute die and SDE lives on the SOC die
   (as does the PICA, so the PICA ID can be used to fingerprint a
   specific version).


Matt

> 
> > 
> >        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > 
> > >  		ddc_pin_map = adlp_ddc_pin_map;
> > >  		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
> > >  	} else if (IS_ALDERLAKE_S(i915)) {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > > index e95ddb580ef6..801fabbccf7e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > > @@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
> > >  	const struct gmbus_pin *pins;
> > >  	size_t size;
> > > 
> > > -	if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
> > > +	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
> > > +		pins = gmbus_pins_mtp;
> > > +		size = ARRAY_SIZE(gmbus_pins_mtp);
> > > +	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
> > >  		pins = gmbus_pins_dg2;
> > >  		size = ARRAY_SIZE(gmbus_pins_dg2);
> > >  	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> > > --
> > > 2.40.1
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

[Matt Roper]

On Thu, Aug 24, 2023 at 09:25:54PM -0700, Lucas De Marchi wrote:
> On Wed, Aug 23, 2023 at 01:49:21PM -0700, Matt Roper wrote:
> > On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote:
> > > LNL's south display uses the same table as MTP. Check for LNL's fake PCH
> > > to make it consistent with the other checks.
> > > 
> > > The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
> > > other cases, uses the same as the previous platform.
> > > 
> > > Bspec: 68971, 20124
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_bios.c  | 2 +-
> > >  drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
> > >  2 files changed, 5 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> > > index 097c1f23d3ae..3772b91e155c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > > @@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
> > >  	const u8 *ddc_pin_map;
> > >  	int i, n_entries;
> > > 
> > > -	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
> > > +	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {
> > 
> > The LUNARLAKE here vs PCH_LNL below seems inconsistent.  Either way, we
> > should probably put the newer platform first in the condition.
> > 
> > Aside from those
> 
> If we drop IS_LUNARLAKE, then we need to check for something else here.
> What about doing this?
> 
> 
> 	if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
> 
> ?

Yeah, that's fine in the short term.  Although I wonder if moving
PCH_LNL before the discrete GPUs might simplify the various conditions
that need to match on SDE behavior since it's probably closer to the MTL
SDE than to the discrete SDEs?  I haven't looked through all the
conditions to see which order is simplest overall.

Longer term I think we need to replace the whole intel_pch enum with an
intel_sde enum or something since this stuff generally isn't related to
PCH anymore, and we should be looking at different things to determine
the exact version of the SDE logic.

 - For MTL, both NDE and SDE live on the same die (SOC); PCH isn't
   involved.
 - For LNL, NDE lives on the compute die and SDE lives on the SOC die
   (as does the PICA, so the PICA ID can be used to fingerprint a
   specific version).


Matt

> 
> > 
> >        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > 
> > >  		ddc_pin_map = adlp_ddc_pin_map;
> > >  		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
> > >  	} else if (IS_ALDERLAKE_S(i915)) {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > > index e95ddb580ef6..801fabbccf7e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > > @@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
> > >  	const struct gmbus_pin *pins;
> > >  	size_t size;
> > > 
> > > -	if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
> > > +	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
> > > +		pins = gmbus_pins_mtp;
> > > +		size = ARRAY_SIZE(gmbus_pins_mtp);
> > > +	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
> > >  		pins = gmbus_pins_dg2;
> > >  		size = ARRAY_SIZE(gmbus_pins_dg2);
> > >  	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> > > --
> > > 2.40.1
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

[Lucas De Marchi]

On Fri, Aug 25, 2023 at 02:55:33PM -0700, Matt Roper wrote:
>On Thu, Aug 24, 2023 at 09:25:54PM -0700, Lucas De Marchi wrote:
>> On Wed, Aug 23, 2023 at 01:49:21PM -0700, Matt Roper wrote:
>> > On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote:
>> > > LNL's south display uses the same table as MTP. Check for LNL's fake PCH
>> > > to make it consistent with the other checks.
>> > >
>> > > The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
>> > > other cases, uses the same as the previous platform.
>> > >
>> > > Bspec: 68971, 20124
>> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > >  drivers/gpu/drm/i915/display/intel_bios.c  | 2 +-
>> > >  drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
>> > >  2 files changed, 5 insertions(+), 2 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>> > > index 097c1f23d3ae..3772b91e155c 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> > > @@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
>> > >  	const u8 *ddc_pin_map;
>> > >  	int i, n_entries;
>> > >
>> > > -	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
>> > > +	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {
>> >
>> > The LUNARLAKE here vs PCH_LNL below seems inconsistent.  Either way, we
>> > should probably put the newer platform first in the condition.
>> >
>> > Aside from those
>>
>> If we drop IS_LUNARLAKE, then we need to check for something else here.
>> What about doing this?
>>
>>
>> 	if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
>>
>> ?
>
>Yeah, that's fine in the short term.  Although I wonder if moving
>PCH_LNL before the discrete GPUs might simplify the various conditions
>that need to match on SDE behavior since it's probably closer to the MTL
>SDE than to the discrete SDEs?  I haven't looked through all the
>conditions to see which order is simplest overall.
>
>Longer term I think we need to replace the whole intel_pch enum with an
>intel_sde enum or something since this stuff generally isn't related to
>PCH anymore, and we should be looking at different things to determine
>the exact version of the SDE logic.
>
> - For MTL, both NDE and SDE live on the same die (SOC); PCH isn't
>   involved.
> - For LNL, NDE lives on the compute die and SDE lives on the SOC die
>   (as does the PICA, so the PICA ID can be used to fingerprint a
>   specific version).

Yeah, agreed.

Lucas De Marchi

>
>
>Matt
>
>>
>> >
>> >        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>> >
>> > >  		ddc_pin_map = adlp_ddc_pin_map;
>> > >  		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
>> > >  	} else if (IS_ALDERLAKE_S(i915)) {
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
>> > > index e95ddb580ef6..801fabbccf7e 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
>> > > @@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
>> > >  	const struct gmbus_pin *pins;
>> > >  	size_t size;
>> > >
>> > > -	if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
>> > > +	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
>> > > +		pins = gmbus_pins_mtp;
>> > > +		size = ARRAY_SIZE(gmbus_pins_mtp);
>> > > +	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
>> > >  		pins = gmbus_pins_dg2;
>> > >  		size = ARRAY_SIZE(gmbus_pins_dg2);
>> > >  	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
>> > > --
>> > > 2.40.1
>> > >
>> >
>> > --
>> > Matt Roper
>> > Graphics Software Engineer
>> > Linux GPU Platform Enablement
>> > Intel Corporation
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

[Lucas De Marchi]

On Fri, Aug 25, 2023 at 02:55:33PM -0700, Matt Roper wrote:
>On Thu, Aug 24, 2023 at 09:25:54PM -0700, Lucas De Marchi wrote:
>> On Wed, Aug 23, 2023 at 01:49:21PM -0700, Matt Roper wrote:
>> > On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote:
>> > > LNL's south display uses the same table as MTP. Check for LNL's fake PCH
>> > > to make it consistent with the other checks.
>> > >
>> > > The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
>> > > other cases, uses the same as the previous platform.
>> > >
>> > > Bspec: 68971, 20124
>> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > >  drivers/gpu/drm/i915/display/intel_bios.c  | 2 +-
>> > >  drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
>> > >  2 files changed, 5 insertions(+), 2 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>> > > index 097c1f23d3ae..3772b91e155c 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> > > @@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
>> > >  	const u8 *ddc_pin_map;
>> > >  	int i, n_entries;
>> > >
>> > > -	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
>> > > +	if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {
>> >
>> > The LUNARLAKE here vs PCH_LNL below seems inconsistent.  Either way, we
>> > should probably put the newer platform first in the condition.
>> >
>> > Aside from those
>>
>> If we drop IS_LUNARLAKE, then we need to check for something else here.
>> What about doing this?
>>
>>
>> 	if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
>>
>> ?
>
>Yeah, that's fine in the short term.  Although I wonder if moving
>PCH_LNL before the discrete GPUs might simplify the various conditions
>that need to match on SDE behavior since it's probably closer to the MTL
>SDE than to the discrete SDEs?  I haven't looked through all the
>conditions to see which order is simplest overall.
>
>Longer term I think we need to replace the whole intel_pch enum with an
>intel_sde enum or something since this stuff generally isn't related to
>PCH anymore, and we should be looking at different things to determine
>the exact version of the SDE logic.
>
> - For MTL, both NDE and SDE live on the same die (SOC); PCH isn't
>   involved.
> - For LNL, NDE lives on the compute die and SDE lives on the SOC die
>   (as does the PICA, so the PICA ID can be used to fingerprint a
>   specific version).

Yeah, agreed.

Lucas De Marchi

>
>
>Matt
>
>>
>> >
>> >        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>> >
>> > >  		ddc_pin_map = adlp_ddc_pin_map;
>> > >  		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
>> > >  	} else if (IS_ALDERLAKE_S(i915)) {
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
>> > > index e95ddb580ef6..801fabbccf7e 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
>> > > @@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
>> > >  	const struct gmbus_pin *pins;
>> > >  	size_t size;
>> > >
>> > > -	if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
>> > > +	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
>> > > +		pins = gmbus_pins_mtp;
>> > > +		size = ARRAY_SIZE(gmbus_pins_mtp);
>> > > +	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
>> > >  		pins = gmbus_pins_dg2;
>> > >  		size = ARRAY_SIZE(gmbus_pins_dg2);
>> > >  	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
>> > > --
>> > > 2.40.1
>> > >
>> >
>> > --
>> > Matt Roper
>> > Graphics Software Engineer
>> > Linux GPU Platform Enablement
>> > Intel Corporation
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 02:14:39PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:30AM -0700, Lucas De Marchi wrote:
>> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>
>> In Lunar Lake we now separate MDCLK from CDLCK, which used to be before
>> always 2 times CDCLK.  Now we might afford lower CDCLK, while having
>> higher memory clock, so improving bandwidth and power consumption at the
>> same time.  This is prep work required to enable that.
>>
>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 30 ++++++++++++++++++++++
>>  drivers/gpu/drm/i915/display/intel_cdclk.h |  2 +-
>>  2 files changed, 31 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index fdd8d04fe12c..3e566f45996d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -1223,6 +1223,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>>
>>  struct intel_cdclk_vals {
>>  	u32 cdclk;
>> +	u32 mdclk;
>>  	u16 refclk;
>>  	u16 waveform;
>>  	u8 divider;	/* CD2X divider * 2 */
>> @@ -1524,6 +1525,8 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
>>  static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>>  			  struct intel_cdclk_config *cdclk_config)
>>  {
>> +	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
>> +	int i, ratio, tbl_waveform = 0;
>>  	u32 squash_ctl = 0;
>>  	u32 divider;
>>  	int div;
>> @@ -1574,10 +1577,36 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>>
>>  		cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
>>  							cdclk_config->vco, size * div);
>> +		tbl_waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
>>  	} else {
>>  		cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
>>  	}
>>
>> +	ratio = cdclk_config->vco / cdclk_config->ref;
>> +
>> +	for (i = 0; table[i].refclk; i++) {
>> +		if (table[i].refclk != cdclk_config->ref)
>> +			continue;
>> +
>> +		if (table[i].divider != div)
>> +			continue;
>> +
>> +		if (table[i].waveform != tbl_waveform)
>> +			continue;
>> +
>> +		if (table[i].ratio != ratio)
>> +			continue;
>> +
>> +		/*
>> +		 * Supported from LunarLake HW onwards, however considering that
>> +		 * besides this the whole procedure is the same, we keep this
>> +		 * for all the platforms.
>> +		 */
>> +		cdclk_config->mdclk = table[i].mdclk;
>> +
>> +		break;
>> +	}
>
>I might be misunderstanding something, but from bspec 68861, is looks
>like the mdclk frequency is always just "ratio * refclk."  Which is the
>value we already have stored in cdclk_config->vco.  Do we need to do
>this extra lookup or track this value separately?

It seems it could be different based on the source of the clock.
CDCLK_CTL has the config and could select the clock to be configured
either from CDCLK or CD2XCLK. However the LNL table has all the entries
with CDCLK as the source, so indeed it seems redundant.  And even if we
had a cd2xclk source, it seems a waste of space to add this field to the
table that could easily be computed.

I will drop this patch in v2.

thanks
Lucas De Marchi

>
>
>Matt
>
>> +
>>   out:
>>  	/*
>>  	 * Can't read this out :( Let's assume it's
>> @@ -2191,6 +2220,7 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
>>  			       const struct intel_cdclk_config *b)
>>  {
>>  	return a->cdclk != b->cdclk ||
>> +		a->mdclk != b->mdclk ||
>>  		a->vco != b->vco ||
>>  		a->ref != b->ref;
>>  }
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
>> index 48fd7d39e0cd..3e7eabd4d7b6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
>> @@ -16,7 +16,7 @@ struct intel_atomic_state;
>>  struct intel_crtc_state;
>>
>>  struct intel_cdclk_config {
>> -	unsigned int cdclk, vco, ref, bypass;
>> +	unsigned int cdclk, mdclk, vco, ref, bypass;
>>  	u8 voltage_level;
>>  };
>>
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-xe] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 02:14:39PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:30AM -0700, Lucas De Marchi wrote:
>> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>
>> In Lunar Lake we now separate MDCLK from CDLCK, which used to be before
>> always 2 times CDCLK.  Now we might afford lower CDCLK, while having
>> higher memory clock, so improving bandwidth and power consumption at the
>> same time.  This is prep work required to enable that.
>>
>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 30 ++++++++++++++++++++++
>>  drivers/gpu/drm/i915/display/intel_cdclk.h |  2 +-
>>  2 files changed, 31 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index fdd8d04fe12c..3e566f45996d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -1223,6 +1223,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>>
>>  struct intel_cdclk_vals {
>>  	u32 cdclk;
>> +	u32 mdclk;
>>  	u16 refclk;
>>  	u16 waveform;
>>  	u8 divider;	/* CD2X divider * 2 */
>> @@ -1524,6 +1525,8 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
>>  static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>>  			  struct intel_cdclk_config *cdclk_config)
>>  {
>> +	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
>> +	int i, ratio, tbl_waveform = 0;
>>  	u32 squash_ctl = 0;
>>  	u32 divider;
>>  	int div;
>> @@ -1574,10 +1577,36 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>>
>>  		cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
>>  							cdclk_config->vco, size * div);
>> +		tbl_waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
>>  	} else {
>>  		cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
>>  	}
>>
>> +	ratio = cdclk_config->vco / cdclk_config->ref;
>> +
>> +	for (i = 0; table[i].refclk; i++) {
>> +		if (table[i].refclk != cdclk_config->ref)
>> +			continue;
>> +
>> +		if (table[i].divider != div)
>> +			continue;
>> +
>> +		if (table[i].waveform != tbl_waveform)
>> +			continue;
>> +
>> +		if (table[i].ratio != ratio)
>> +			continue;
>> +
>> +		/*
>> +		 * Supported from LunarLake HW onwards, however considering that
>> +		 * besides this the whole procedure is the same, we keep this
>> +		 * for all the platforms.
>> +		 */
>> +		cdclk_config->mdclk = table[i].mdclk;
>> +
>> +		break;
>> +	}
>
>I might be misunderstanding something, but from bspec 68861, is looks
>like the mdclk frequency is always just "ratio * refclk."  Which is the
>value we already have stored in cdclk_config->vco.  Do we need to do
>this extra lookup or track this value separately?

It seems it could be different based on the source of the clock.
CDCLK_CTL has the config and could select the clock to be configured
either from CDCLK or CD2XCLK. However the LNL table has all the entries
with CDCLK as the source, so indeed it seems redundant.  And even if we
had a cd2xclk source, it seems a waste of space to add this field to the
table that could easily be computed.

I will drop this patch in v2.

thanks
Lucas De Marchi

>
>
>Matt
>
>> +
>>   out:
>>  	/*
>>  	 * Can't read this out :( Let's assume it's
>> @@ -2191,6 +2220,7 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
>>  			       const struct intel_cdclk_config *b)
>>  {
>>  	return a->cdclk != b->cdclk ||
>> +		a->mdclk != b->mdclk ||
>>  		a->vco != b->vco ||
>>  		a->ref != b->ref;
>>  }
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
>> index 48fd7d39e0cd..3e7eabd4d7b6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
>> @@ -16,7 +16,7 @@ struct intel_atomic_state;
>>  struct intel_crtc_state;
>>
>>  struct intel_cdclk_config {
>> -	unsigned int cdclk, vco, ref, bypass;
>> +	unsigned int cdclk, mdclk, vco, ref, bypass;
>>  	u8 voltage_level;
>>  };
>>
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 03:01:37PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:32AM -0700, Lucas De Marchi wrote:
>> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>
>> Introduce correspondent definitions and for choosing between CD2X CDCLK
>> and PLL CDCLK as a source.
>>
>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++--
>>  drivers/gpu/drm/i915/i915_reg.h            |  3 +++
>>  2 files changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index ed45a2cf5c9a..04937aaabcee 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -1932,8 +1932,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>  		dg2_cdclk_squash_program(dev_priv, waveform);
>>
>>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>> -		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
>> -		skl_cdclk_decimal(cdclk);
>> +		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
>>
>>  	/*
>>  	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
>> @@ -1942,6 +1941,17 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>  	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
>>  	    cdclk >= 500000)
>>  		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
>> +
>> +	if (DISPLAY_VER(dev_priv) >= 20)
>> +		/*
>> +		 * Using CDCLK through PLL seems to be always better option when
>> +		 * its supported, both in terms of performance and power
>> +		 * consumption.
>> +		 */
>
>I'm not sure what this comment is based on.  But the table on bspec
>68861 specifically tells us to set this bit for the cdclk table we
>implemented in the last patch, so the logic is correct regardless.

I think this is more a justification for having the entries in the
table. I agree there is no need for it here as the driver is simply
implementing what is the spec.

>
>> +		val |= CDCLK_SOURCE_SEL_CDCLK_PLL;
>> +	else
>> +		val |= skl_cdclk_decimal(cdclk);
>> +
>>  	intel_de_write(dev_priv, CDCLK_CTL, val);
>>
>>  	if (pipe != INVALID_PIPE)
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index fa85530afac3..d5850761a75a 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5933,6 +5933,9 @@ enum skl_power_gate {
>>  #define  CDCLK_FREQ_540		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
>>  #define  CDCLK_FREQ_337_308		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
>>  #define  CDCLK_FREQ_675_617		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
>> +#define  CDCLK_SOURCE_SEL_MASK		REG_BIT(25)
>> +#define  CDCLK_SOURCE_SEL_CD2X		REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 0)
>
>No need to make a single-bit "mask" or define the unused
>CDCLK_SOURCE_SEL_CD2X here.  We can just define
>CDCLK_SOURCE_SEL_CDCLK_PLL as REG_BIT(25) directly.

will change in v2.

thanks
Lucas De Marchi

>
>
>Matt
>
>> +#define  CDCLK_SOURCE_SEL_CDCLK_PLL	REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 1)
>>  #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	REG_GENMASK(23, 22)
>>  #define  BXT_CDCLK_CD2X_DIV_SEL_1	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
>>  #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-xe] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 03:01:37PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:32AM -0700, Lucas De Marchi wrote:
>> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>
>> Introduce correspondent definitions and for choosing between CD2X CDCLK
>> and PLL CDCLK as a source.
>>
>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++--
>>  drivers/gpu/drm/i915/i915_reg.h            |  3 +++
>>  2 files changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index ed45a2cf5c9a..04937aaabcee 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -1932,8 +1932,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>  		dg2_cdclk_squash_program(dev_priv, waveform);
>>
>>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>> -		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
>> -		skl_cdclk_decimal(cdclk);
>> +		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
>>
>>  	/*
>>  	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
>> @@ -1942,6 +1941,17 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>  	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
>>  	    cdclk >= 500000)
>>  		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
>> +
>> +	if (DISPLAY_VER(dev_priv) >= 20)
>> +		/*
>> +		 * Using CDCLK through PLL seems to be always better option when
>> +		 * its supported, both in terms of performance and power
>> +		 * consumption.
>> +		 */
>
>I'm not sure what this comment is based on.  But the table on bspec
>68861 specifically tells us to set this bit for the cdclk table we
>implemented in the last patch, so the logic is correct regardless.

I think this is more a justification for having the entries in the
table. I agree there is no need for it here as the driver is simply
implementing what is the spec.

>
>> +		val |= CDCLK_SOURCE_SEL_CDCLK_PLL;
>> +	else
>> +		val |= skl_cdclk_decimal(cdclk);
>> +
>>  	intel_de_write(dev_priv, CDCLK_CTL, val);
>>
>>  	if (pipe != INVALID_PIPE)
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index fa85530afac3..d5850761a75a 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5933,6 +5933,9 @@ enum skl_power_gate {
>>  #define  CDCLK_FREQ_540		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
>>  #define  CDCLK_FREQ_337_308		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
>>  #define  CDCLK_FREQ_675_617		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
>> +#define  CDCLK_SOURCE_SEL_MASK		REG_BIT(25)
>> +#define  CDCLK_SOURCE_SEL_CD2X		REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 0)
>
>No need to make a single-bit "mask" or define the unused
>CDCLK_SOURCE_SEL_CD2X here.  We can just define
>CDCLK_SOURCE_SEL_CDCLK_PLL as REG_BIT(25) directly.

will change in v2.

thanks
Lucas De Marchi

>
>
>Matt
>
>> +#define  CDCLK_SOURCE_SEL_CDCLK_PLL	REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 1)
>>  #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	REG_GENMASK(23, 22)
>>  #define  BXT_CDCLK_CD2X_DIV_SEL_1	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
>>  #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-gfx] [Intel-xe] [PATCH 36/42] drm/i915/lnl: Add support for CDCLK initialization sequence

[Lucas De Marchi]

On Thu, Aug 24, 2023 at 04:54:57PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:34AM -0700, Lucas De Marchi wrote:
>> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>>
>> Add CDCLK initialization sequence changes and CDCLK set frequency
>> sequence for LNL platform.
>>
>> CDCLK frequency change sequence is different for LNL compared to MTL
>> when a change in mdclk/cdclk ratio is observed. Below are changes to be
>> made:
>>
>> 1. In MBUS_CTL register translation Throttle Min value.
>> 2. In DBUF_CTL_S* register Min Tracker State Service value.
>
>The previous patch just did these same changes, but made the changes to
>the existing functions.  It looks like we wound up with two patches
>doing the same thing?

The change here is because now during the squash phase there is
extra programming steps touching DBUF_CTL_S and MBUS_CTL. It doesn't
seem good we have this in 2 different places though.  Ravi / Stan, any
comment here?

Lucas De Marchi

>
>>
>> BSpec: 68846, 68864
>> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 58 ++++++++++++++++++++--
>>  drivers/gpu/drm/i915/i915_reg.h            |  2 +
>>  2 files changed, 57 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index aa1000db3cb9..4d8b960389ec 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -38,6 +38,7 @@
>>  #include "intel_pcode.h"
>>  #include "intel_psr.h"
>>  #include "skl_watermark.h"
>> +#include "skl_watermark_regs.h"
>>  #include "vlv_sideband.h"
>>
>>  /**
>> @@ -1727,7 +1728,12 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
>>
>>  static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>>  {
>> -	if (DISPLAY_VER(dev_priv) >= 12) {
>> +	if (DISPLAY_VER(dev_priv) >= 20) {
>> +		if (pipe == INVALID_PIPE)
>> +			return LNL_CDCLK_CD2X_PIPE_NONE;
>> +		else
>> +			return LNL_CDCLK_CD2X_PIPE(pipe);
>
>I don't think this change is correct; see note farther down on the
>register definitions.
>
>> +	} else if (DISPLAY_VER(dev_priv) >= 12) {
>>  		if (pipe == INVALID_PIPE)
>>  			return TGL_CDCLK_CD2X_PIPE_NONE;
>>  		else
>> @@ -1837,6 +1843,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>>  		return 1;
>>  }
>>
>> +static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
>> +				    const struct intel_cdclk_config *cdclk_config)
>> +{
>> +	int min_throttle_val;
>> +	int min_tracker_state;
>> +	enum dbuf_slice slice;
>> +	int mdclk_cdclk_div_ratio;
>> +	int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
>> +
>> +	mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
>> +
>> +	min_throttle_val = MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
>> +
>> +	intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK, min_throttle_val);
>> +
>> +	if (mbus_join)
>> +		mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
>> +
>> +	min_tracker_state = DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
>> +
>> +	for_each_dbuf_slice(i915, slice)
>> +		intel_de_rmw(i915, DBUF_CTL_S(slice),
>> +			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
>> +			     min_tracker_state);
>> +}
>> +
>> +static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
>> +				     const struct intel_cdclk_config *cdclk_config,
>> +				     u16 waveform)
>> +{
>> +	if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
>> +		/* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
>> +		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
>> +
>> +	dg2_cdclk_squash_program(i915, waveform);
>> +
>> +	if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
>> +		/* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
>> +		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
>> +}
>> +
>>  static int cdclk_squash_divider(u16 waveform)
>>  {
>>  	return hweight16(waveform ?: 0xffff);
>> @@ -1938,8 +1985,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>  	else
>>  		clock = cdclk;
>>
>> -	if (HAS_CDCLK_SQUASH(dev_priv))
>> -		dg2_cdclk_squash_program(dev_priv, waveform);
>> +	if (HAS_CDCLK_SQUASH(dev_priv)) {
>> +		if (DISPLAY_VER(dev_priv) >= 20)
>> +			lnl_cdclk_squash_program(dev_priv, cdclk_config,
>> +						 waveform);
>> +		else
>> +			dg2_cdclk_squash_program(dev_priv, waveform);
>> +	}
>>
>>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>>  		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d5850761a75a..c9639f0f4f49 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5944,6 +5944,8 @@ enum skl_power_gate {
>>  #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
>>  #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
>>  #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
>> +#define  LNL_CDCLK_CD2X_PIPE(pipe)	((pipe) << 19)
>
>This doesn't match what I see on bspec 69090:
>
>Bits 21:19
>  000 => Pipe A
>  010 => Pipe B
>  100 => Pipe C
>  110 => Pipe D
>
>So the pipe ID (0-3) should actually be shifted by 20 since bit 19 is
>always 0 (except for the "none" case).  I think
>
>
>Matt
>
>> +#define  LNL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
>>  #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
>>  #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
>>  #define  TGL_CDCLK_CD2X_PIPE(pipe)	BXT_CDCLK_CD2X_PIPE(pipe)
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-xe] [PATCH 36/42] drm/i915/lnl: Add support for CDCLK initialization sequence

[Lucas De Marchi]

On Thu, Aug 24, 2023 at 04:54:57PM -0700, Matt Roper wrote:
>On Wed, Aug 23, 2023 at 10:07:34AM -0700, Lucas De Marchi wrote:
>> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>>
>> Add CDCLK initialization sequence changes and CDCLK set frequency
>> sequence for LNL platform.
>>
>> CDCLK frequency change sequence is different for LNL compared to MTL
>> when a change in mdclk/cdclk ratio is observed. Below are changes to be
>> made:
>>
>> 1. In MBUS_CTL register translation Throttle Min value.
>> 2. In DBUF_CTL_S* register Min Tracker State Service value.
>
>The previous patch just did these same changes, but made the changes to
>the existing functions.  It looks like we wound up with two patches
>doing the same thing?

The change here is because now during the squash phase there is
extra programming steps touching DBUF_CTL_S and MBUS_CTL. It doesn't
seem good we have this in 2 different places though.  Ravi / Stan, any
comment here?

Lucas De Marchi

>
>>
>> BSpec: 68846, 68864
>> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 58 ++++++++++++++++++++--
>>  drivers/gpu/drm/i915/i915_reg.h            |  2 +
>>  2 files changed, 57 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index aa1000db3cb9..4d8b960389ec 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -38,6 +38,7 @@
>>  #include "intel_pcode.h"
>>  #include "intel_psr.h"
>>  #include "skl_watermark.h"
>> +#include "skl_watermark_regs.h"
>>  #include "vlv_sideband.h"
>>
>>  /**
>> @@ -1727,7 +1728,12 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
>>
>>  static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>>  {
>> -	if (DISPLAY_VER(dev_priv) >= 12) {
>> +	if (DISPLAY_VER(dev_priv) >= 20) {
>> +		if (pipe == INVALID_PIPE)
>> +			return LNL_CDCLK_CD2X_PIPE_NONE;
>> +		else
>> +			return LNL_CDCLK_CD2X_PIPE(pipe);
>
>I don't think this change is correct; see note farther down on the
>register definitions.
>
>> +	} else if (DISPLAY_VER(dev_priv) >= 12) {
>>  		if (pipe == INVALID_PIPE)
>>  			return TGL_CDCLK_CD2X_PIPE_NONE;
>>  		else
>> @@ -1837,6 +1843,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>>  		return 1;
>>  }
>>
>> +static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
>> +				    const struct intel_cdclk_config *cdclk_config)
>> +{
>> +	int min_throttle_val;
>> +	int min_tracker_state;
>> +	enum dbuf_slice slice;
>> +	int mdclk_cdclk_div_ratio;
>> +	int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
>> +
>> +	mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
>> +
>> +	min_throttle_val = MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
>> +
>> +	intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK, min_throttle_val);
>> +
>> +	if (mbus_join)
>> +		mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
>> +
>> +	min_tracker_state = DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
>> +
>> +	for_each_dbuf_slice(i915, slice)
>> +		intel_de_rmw(i915, DBUF_CTL_S(slice),
>> +			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
>> +			     min_tracker_state);
>> +}
>> +
>> +static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
>> +				     const struct intel_cdclk_config *cdclk_config,
>> +				     u16 waveform)
>> +{
>> +	if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
>> +		/* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
>> +		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
>> +
>> +	dg2_cdclk_squash_program(i915, waveform);
>> +
>> +	if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
>> +		/* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
>> +		lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
>> +}
>> +
>>  static int cdclk_squash_divider(u16 waveform)
>>  {
>>  	return hweight16(waveform ?: 0xffff);
>> @@ -1938,8 +1985,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>  	else
>>  		clock = cdclk;
>>
>> -	if (HAS_CDCLK_SQUASH(dev_priv))
>> -		dg2_cdclk_squash_program(dev_priv, waveform);
>> +	if (HAS_CDCLK_SQUASH(dev_priv)) {
>> +		if (DISPLAY_VER(dev_priv) >= 20)
>> +			lnl_cdclk_squash_program(dev_priv, cdclk_config,
>> +						 waveform);
>> +		else
>> +			dg2_cdclk_squash_program(dev_priv, waveform);
>> +	}
>>
>>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>>  		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d5850761a75a..c9639f0f4f49 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5944,6 +5944,8 @@ enum skl_power_gate {
>>  #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
>>  #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
>>  #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
>> +#define  LNL_CDCLK_CD2X_PIPE(pipe)	((pipe) << 19)
>
>This doesn't match what I see on bspec 69090:
>
>Bits 21:19
>  000 => Pipe A
>  010 => Pipe B
>  100 => Pipe C
>  110 => Pipe D
>
>So the pipe ID (0-3) should actually be shifted by 20 since bit 19 is
>always 0 (except for the "none" case).  I think
>
>
>Matt
>
>> +#define  LNL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
>>  #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
>>  #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
>>  #define  TGL_CDCLK_CD2X_PIPE(pipe)	BXT_CDCLK_CD2X_PIPE(pipe)
>> --
>> 2.40.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [Intel-gfx] [PATCH 38/42] drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 10:07:36AM -0700, Lucas De Marchi wrote:
>From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
>mdclk_cdclk_ratio is a part of dbuf_state and if it changes, it requires
>hw to be poked, so we must serialize the global state in that case.
>
>Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++++++++++++----
> 1 file changed, 15 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 4d8b960389ec..38a9c47e4ae1 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2789,7 +2789,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> 	struct intel_crtc_state *crtc_state;
> 	int min_cdclk, i;
> 	enum pipe pipe;
>-	struct intel_dbuf_state *dbuf_state;
>+	struct intel_dbuf_state *new_dbuf_state;
>+	struct intel_dbuf_state *old_dbuf_state;
>
> 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> 		int ret;
>@@ -2823,11 +2824,21 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> 		}
> 	}
>
>-	dbuf_state = intel_atomic_get_new_dbuf_state(state);
>-	if (dbuf_state)
>-		dbuf_state->mdclk_cdclk_ratio =
>+	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
>+	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);

humn... it looks like this should actually be squashed in one of the
previous patches that added this.

Lucas De Marchi

>+	if (new_dbuf_state && old_dbuf_state) {
>+		new_dbuf_state->mdclk_cdclk_ratio =
> 			get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
>
>+		if (new_dbuf_state->mdclk_cdclk_ratio != old_dbuf_state->mdclk_cdclk_ratio) {
>+			int ret;
>+
>+			ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
>+			if (ret)
>+				return ret;
>+		}
>+	}
>+
> 	min_cdclk = max(cdclk_state->force_min_cdclk,
> 			cdclk_state->bw_min_cdclk);
> 	for_each_pipe(dev_priv, pipe)
>-- 
>2.40.1
>

Re: [Intel-xe] [Intel-gfx] [PATCH 38/42] drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.

[Lucas De Marchi]

On Wed, Aug 23, 2023 at 10:07:36AM -0700, Lucas De Marchi wrote:
>From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
>mdclk_cdclk_ratio is a part of dbuf_state and if it changes, it requires
>hw to be poked, so we must serialize the global state in that case.
>
>Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++++++++++++----
> 1 file changed, 15 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 4d8b960389ec..38a9c47e4ae1 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2789,7 +2789,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> 	struct intel_crtc_state *crtc_state;
> 	int min_cdclk, i;
> 	enum pipe pipe;
>-	struct intel_dbuf_state *dbuf_state;
>+	struct intel_dbuf_state *new_dbuf_state;
>+	struct intel_dbuf_state *old_dbuf_state;
>
> 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> 		int ret;
>@@ -2823,11 +2824,21 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> 		}
> 	}
>
>-	dbuf_state = intel_atomic_get_new_dbuf_state(state);
>-	if (dbuf_state)
>-		dbuf_state->mdclk_cdclk_ratio =
>+	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
>+	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);

humn... it looks like this should actually be squashed in one of the
previous patches that added this.

Lucas De Marchi

>+	if (new_dbuf_state && old_dbuf_state) {
>+		new_dbuf_state->mdclk_cdclk_ratio =
> 			get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
>
>+		if (new_dbuf_state->mdclk_cdclk_ratio != old_dbuf_state->mdclk_cdclk_ratio) {
>+			int ret;
>+
>+			ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
>+			if (ret)
>+				return ret;
>+		}
>+	}
>+
> 	min_cdclk = max(cdclk_state->force_min_cdclk,
> 			cdclk_state->bw_min_cdclk);
> 	for_each_pipe(dev_priv, pipe)
>-- 
>2.40.1
>