* [PATCH v2 0/2] arm64: dts: renesas: r8a779f0: Add PCIe support
@ 2023-08-28 4:14 Yoshihiro Shimoda
2023-08-28 4:14 ` [PATCH v2 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
2023-08-28 4:14 ` [PATCH v2 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
0 siblings, 2 replies; 5+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-28 4:14 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Add PCIe support for R-Car S4-8 (r8a779f0). The dt-bindings
doc patches are merged into pci.git repo:
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=controller/rcar
Changes from v1:
https://lore.kernel.org/all/20230414072717.2931212-1-yoshihiro.shimoda.uh@renesas.com/
- Rebased on the latest renesas-devel tag (renesas-devel-2023-08-21-v6.5-rc7).
- Fix the nodes for the latest dt-bindings docs.
Yoshihiro Shimoda (2):
arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes
arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0
.../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 24 ++++
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 128 ++++++++++++++++++
2 files changed, 152 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes
2023-08-28 4:14 [PATCH v2 0/2] arm64: dts: renesas: r8a779f0: Add PCIe support Yoshihiro Shimoda
@ 2023-08-28 4:14 ` Yoshihiro Shimoda
2023-08-31 15:04 ` Geert Uytterhoeven
2023-08-28 4:14 ` [PATCH v2 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
1 sibling, 1 reply; 5+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-28 4:14 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Add PCIe Host and Endpoint nodes for R-Car S4-8 (R8A779F0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 128 ++++++++++++++++++++++
1 file changed, 128 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 0059c9c580f3..a95e45bc791f 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -262,6 +262,20 @@ extalr_clk: extalr {
clock-frequency = <0>;
};
+ pcie0_clkref: pcie0_clkref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ pcie1_clkref: pcie1_clkref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
pmu_a55 {
compatible = "arm,cortex-a55-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -726,6 +740,120 @@ hscif3: serial@e66a0000 {
status = "disabled";
};
+ pciec0: pcie@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie",
+ "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
+ <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+ <0 0xe65d6200 0 0x1100>, <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma", "sft_ce", "app";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ reset-names = "pwr";
+ num-lanes = <2>;
+ snps,enable-cdm-check;
+ max-link-speed = <4>;
+ status = "disabled";
+ };
+
+ pciec1: pcie@e65d8000 {
+ compatible = "renesas,r8a779f0-pcie",
+ "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
+ <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
+ <0 0xe65de200 0 0x1100>, <0 0xee900000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
+ interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma", "sft_ce", "app";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ reset-names = "pwr";
+ num-lanes = <2>;
+ snps,enable-cdm-check;
+ max-link-speed = <4>;
+ status = "disabled";
+ };
+
+ pciec0_ep: pcie-ep@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie-ep",
+ "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
+ <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+ <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space";
+ interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ reset-names = "pwr";
+ num-lanes = <2>;
+ max-link-speed = <4>;
+ max-functions = /bits/ 8 <2>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@e65d8000 {
+ compatible = "renesas,r8a779f0-pcie-ep",
+ "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
+ <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
+ <0 0xe65de200 0 0x0e00>, <0 0xee900000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space";
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ reset-names = "pwr";
+ num-lanes = <2>;
+ max-link-speed = <4>;
+ max-functions = /bits/ 8 <2>;
+ status = "disabled";
+ };
+
ufs: ufs@e6860000 {
compatible = "renesas,r8a779f0-ufs";
reg = <0 0xe6860000 0 0x100>;
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0
2023-08-28 4:14 [PATCH v2 0/2] arm64: dts: renesas: r8a779f0: Add PCIe support Yoshihiro Shimoda
2023-08-28 4:14 ` [PATCH v2 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
@ 2023-08-28 4:14 ` Yoshihiro Shimoda
2023-08-31 13:48 ` Geert Uytterhoeven
1 sibling, 1 reply; 5+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-28 4:14 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Enable PCIe Host controller channel 0 on R-Car S4-8 Spider board.
Since this board has an Oculink connector, CLKREQ# pin of PFC for PCIe
should not be used. So, using a GPIO is used to output the clock instead.
Otherwise the controller cannot detect a PCIe device.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
.../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
index 76a94812875e..48fb79aac32f 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -53,6 +53,12 @@ memory@480000000 {
reg = <0x4 0x80000000 0x0 0x80000000>;
};
+ rc21012_pci: clk-rc21012-pci {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ #clock-cells = <0>;
+ };
+
rc21012_ufs: clk-rc21012-ufs {
compatible = "fixed-clock";
clock-frequency = <38400000>;
@@ -106,6 +112,12 @@ gpio_exp_20: gpio@20 {
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
+
+ rc21012-gpio2-hog {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ output-high;
+ };
};
};
@@ -145,6 +157,11 @@ &mmc0 {
status = "okay";
};
+&pciec0 {
+ reset-gpio = <&gpio_exp_20 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
@@ -202,6 +219,13 @@ &ufs {
status = "okay";
};
+&pcie0_clkref {
+ compatible = "gpio-gate-clock";
+ clocks = <&rc21012_pci>;
+ enable-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ /delete-property/ clock-frequency;
+};
+
&ufs30_clk {
compatible = "gpio-gate-clock";
clocks = <&rc21012_ufs>;
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0
2023-08-28 4:14 ` [PATCH v2 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
@ 2023-08-31 13:48 ` Geert Uytterhoeven
0 siblings, 0 replies; 5+ messages in thread
From: Geert Uytterhoeven @ 2023-08-31 13:48 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: geert+renesas, magnus.damm, linux-renesas-soc
Hi Shimoda-san,
On Mon, Aug 28, 2023 at 6:14 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Enable PCIe Host controller channel 0 on R-Car S4-8 Spider board.
>
> Since this board has an Oculink connector, CLKREQ# pin of PFC for PCIe
> should not be used. So, using a GPIO is used to output the clock instead.
> Otherwise the controller cannot detect a PCIe device.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
> @@ -145,6 +157,11 @@ &mmc0 {
> status = "okay";
> };
>
> +&pciec0 {
> + reset-gpio = <&gpio_exp_20 0 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> &pfc {
> pinctrl-0 = <&scif_clk_pins>;
> pinctrl-names = "default";
> @@ -202,6 +219,13 @@ &ufs {
> status = "okay";
> };
>
> +&pcie0_clkref {
Please move this node up to preserve alphabetical sort order.
> + compatible = "gpio-gate-clock";
> + clocks = <&rc21012_pci>;
> + enable-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
> + /delete-property/ clock-frequency;
> +};
> +
> &ufs30_clk {
> compatible = "gpio-gate-clock";
> clocks = <&rc21012_ufs>;
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes
2023-08-28 4:14 ` [PATCH v2 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
@ 2023-08-31 15:04 ` Geert Uytterhoeven
0 siblings, 0 replies; 5+ messages in thread
From: Geert Uytterhoeven @ 2023-08-31 15:04 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: magnus.damm, linux-renesas-soc
Hi Shimoda-san,
On Mon, Aug 28, 2023 at 6:14 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add PCIe Host and Endpoint nodes for R-Car S4-8 (R8A779F0).
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> @@ -262,6 +262,20 @@ extalr_clk: extalr {
> clock-frequency = <0>;
> };
>
> + pcie0_clkref: pcie0_clkref {
Please no underscores in node names.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + pcie1_clkref: pcie1_clkref {
Likewise.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> pmu_a55 {
> compatible = "arm,cortex-a55-pmu";
> interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> @@ -726,6 +740,120 @@ hscif3: serial@e66a0000 {
> status = "disabled";
> };
>
> + pciec0: pcie@e65d0000 {
> + compatible = "renesas,r8a779f0-pcie",
> + "renesas,rcar-gen4-pcie";
> + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
> + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
> + <0 0xe65d6200 0 0x1100>, <0 0xfe000000 0 0x400000>;
Shouldn't that 0x1100 be 0x0e00, like in the EP nodes?
And missing <0 0xe65d7000 0 0x1100> for "phy"?
> + reg-names = "dbi", "dbi2", "atu", "dma", "app", "config";
Same comments for the other instance.
The rest LGTM, modulo my comments on the bindings.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-08-31 15:05 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2023-08-28 4:14 [PATCH v2 0/2] arm64: dts: renesas: r8a779f0: Add PCIe support Yoshihiro Shimoda
2023-08-28 4:14 ` [PATCH v2 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
2023-08-31 15:04 ` Geert Uytterhoeven
2023-08-28 4:14 ` [PATCH v2 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
2023-08-31 13:48 ` Geert Uytterhoeven
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