* Re: [Intel-gfx] [PATCH v3 19/29] drm/i915/xe2lpd: Read pin assignment from IOM
@ 2023-09-13 1:34 kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2023-09-13 1:34 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp, Dan Carpenter
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20230912044837.1672060-20-lucas.demarchi@intel.com>
References: <20230912044837.1672060-20-lucas.demarchi@intel.com>
TO: Lucas De Marchi <lucas.demarchi@intel.com>
TO: intel-xe@lists.freedesktop.org
TO: intel-gfx@lists.freedesktop.org
CC: Lucas De Marchi <lucas.demarchi@intel.com>
CC: Matt Roper <matthew.d.roper@intel.com>
CC: Luca Coelho <luciano.coelho@intel.com>
Hi Lucas,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Lucas-De-Marchi/drm-i915-xelpdp-Add-XE_LPDP_FEATURES/20230912-125100
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230912044837.1672060-20-lucas.demarchi%40intel.com
patch subject: [Intel-gfx] [PATCH v3 19/29] drm/i915/xe2lpd: Read pin assignment from IOM
:::::: branch date: 21 hours ago
:::::: commit date: 21 hours ago
config: x86_64-randconfig-161-20230912 (https://download.01.org/0day-ci/archive/20230913/202309130932.j4thdtBS-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce: (https://download.01.org/0day-ci/archive/20230913/202309130932.j4thdtBS-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202309130932.j4thdtBS-lkp@intel.com/
New smatch warnings:
drivers/gpu/drm/i915/display/intel_tc.c:304 lnl_tc_port_get_max_lane_count() error: uninitialized symbol 'val'.
Old smatch warnings:
drivers/gpu/drm/i915/display/intel_tc.c:327 mtl_tc_port_get_max_lane_count() error: uninitialized symbol 'pin_mask'.
drivers/gpu/drm/i915/display/intel_tc.c:500 icl_tc_phy_hpd_live_status() error: uninitialized symbol 'fia_isr'.
drivers/gpu/drm/i915/display/intel_tc.c:512 icl_tc_phy_hpd_live_status() error: uninitialized symbol 'pch_isr'.
drivers/gpu/drm/i915/display/intel_tc.c:736 tgl_tc_phy_init() error: uninitialized symbol 'val'.
drivers/gpu/drm/i915/display/intel_tc.c:785 adlp_tc_phy_hpd_live_status() error: uninitialized symbol 'cpu_isr'.
drivers/gpu/drm/i915/display/intel_tc.c:790 adlp_tc_phy_hpd_live_status() error: uninitialized symbol 'pch_isr'.
drivers/gpu/drm/i915/display/intel_tc.c:973 xelpdp_tc_phy_hpd_live_status() error: uninitialized symbol 'pica_isr'.
drivers/gpu/drm/i915/display/intel_tc.c:978 xelpdp_tc_phy_hpd_live_status() error: uninitialized symbol 'pch_isr'.
vim +/val +304 drivers/gpu/drm/i915/display/intel_tc.c
3b51be4e4061bd Clinton A Taylor 2019-09-26 292
636a73ea93158b Luca Coelho 2023-09-11 293 static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
636a73ea93158b Luca Coelho 2023-09-11 294 {
636a73ea93158b Luca Coelho 2023-09-11 295 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
636a73ea93158b Luca Coelho 2023-09-11 296 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
636a73ea93158b Luca Coelho 2023-09-11 297 intel_wakeref_t wakeref;
636a73ea93158b Luca Coelho 2023-09-11 298 u32 val, pin_assignment;
636a73ea93158b Luca Coelho 2023-09-11 299
636a73ea93158b Luca Coelho 2023-09-11 300 with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
636a73ea93158b Luca Coelho 2023-09-11 301 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
636a73ea93158b Luca Coelho 2023-09-11 302
636a73ea93158b Luca Coelho 2023-09-11 303 pin_assignment =
636a73ea93158b Luca Coelho 2023-09-11 @304 REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
636a73ea93158b Luca Coelho 2023-09-11 305
636a73ea93158b Luca Coelho 2023-09-11 306 switch (pin_assignment) {
636a73ea93158b Luca Coelho 2023-09-11 307 default:
636a73ea93158b Luca Coelho 2023-09-11 308 MISSING_CASE(pin_assignment);
636a73ea93158b Luca Coelho 2023-09-11 309 fallthrough;
636a73ea93158b Luca Coelho 2023-09-11 310 case DP_PIN_ASSIGNMENT_D:
636a73ea93158b Luca Coelho 2023-09-11 311 return 2;
636a73ea93158b Luca Coelho 2023-09-11 312 case DP_PIN_ASSIGNMENT_C:
636a73ea93158b Luca Coelho 2023-09-11 313 case DP_PIN_ASSIGNMENT_E:
636a73ea93158b Luca Coelho 2023-09-11 314 return 4;
636a73ea93158b Luca Coelho 2023-09-11 315 }
636a73ea93158b Luca Coelho 2023-09-11 316 }
636a73ea93158b Luca Coelho 2023-09-11 317
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 2+ messages in thread
* [Intel-gfx] [PATCH v3 19/29] drm/i915/xe2lpd: Read pin assignment from IOM
2023-09-12 4:48 [Intel-gfx] [PATCH v3 00/29] Enable Lunar Lake display Lucas De Marchi
@ 2023-09-12 4:48 ` Lucas De Marchi
0 siblings, 0 replies; 2+ messages in thread
From: Lucas De Marchi @ 2023-09-12 4:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi, Matt Roper, Luca Coelho
From: Luca Coelho <luciano.coelho@intel.com>
Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.
We use the pin assignment to decide the maximum lane count. So, to
support this change, add a new lnl_tc_port_get_max_lane_count() function
that reads from the TCSS_DDI_STATUS register and decides the maximum
lane count based on that.
BSpec: 69594
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 678693978892..e9ced251c170 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
}
+static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ intel_wakeref_t wakeref;
+ u32 val, pin_assignment;
+
+ with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+ val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
+
+ pin_assignment =
+ REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
+
+ switch (pin_assignment) {
+ default:
+ MISSING_CASE(pin_assignment);
+ fallthrough;
+ case DP_PIN_ASSIGNMENT_D:
+ return 2;
+ case DP_PIN_ASSIGNMENT_C:
+ case DP_PIN_ASSIGNMENT_E:
+ return 4;
+ }
+}
+
static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -348,6 +373,9 @@ int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
assert_tc_cold_blocked(tc);
+ if (DISPLAY_VER(i915) >= 20)
+ return lnl_tc_port_get_max_lane_count(dig_port);
+
if (DISPLAY_VER(i915) >= 14)
return mtl_tc_port_get_max_lane_count(dig_port);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f115d339913..efcf1461988f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6351,6 +6351,7 @@ enum skl_power_gate {
#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
_TCSS_DDI_STATUS_1, \
_TCSS_DDI_STATUS_2))
+#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
#define TCSS_DDI_STATUS_READY REG_BIT(2)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
--
2.40.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
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2023-09-13 1:34 [Intel-gfx] [PATCH v3 19/29] drm/i915/xe2lpd: Read pin assignment from IOM kernel test robot
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2023-09-12 4:48 [Intel-gfx] [PATCH v3 00/29] Enable Lunar Lake display Lucas De Marchi
2023-09-12 4:48 ` [Intel-gfx] [PATCH v3 19/29] drm/i915/xe2lpd: Read pin assignment from IOM Lucas De Marchi
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