* [PATCH v1 0/2] HWCAP for FEAT_LRCPC3
@ 2023-09-19 16:27 Joey Gouly
2023-09-19 16:27 ` [PATCH v1 1/2] arm64: add FEAT_LRCPC3 HWCAP Joey Gouly
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Joey Gouly @ 2023-09-19 16:27 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: nd, catalin.marinas, joey.gouly, will
Hi,
Small patches to add a HWCAP for FEAT_LRCPC3 and a test.
Based on arm64 for-next/fixes, so that it wouldn't conflict with the recent HBC
doc fix, hope that was the right thing to do!
Thanks,
Joey
Joey Gouly (2):
arm64: add FEAT_LRCPC3 HWCAP
selftests/arm64: add HWCAP2_LRCPC3 test
Documentation/arch/arm64/elf_hwcaps.rst | 3 +++
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/include/uapi/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 1 +
arch/arm64/kernel/cpuinfo.c | 1 +
arch/arm64/tools/sysreg | 1 +
tools/testing/selftests/arm64/abi/hwcap.c | 20 ++++++++++++++++++++
7 files changed, 28 insertions(+)
--
2.25.1
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v1 1/2] arm64: add FEAT_LRCPC3 HWCAP
2023-09-19 16:27 [PATCH v1 0/2] HWCAP for FEAT_LRCPC3 Joey Gouly
@ 2023-09-19 16:27 ` Joey Gouly
2023-09-19 16:27 ` [PATCH v1 2/2] selftests/arm64: add HWCAP2_LRCPC3 test Joey Gouly
2023-10-13 18:44 ` [PATCH v1 0/2] HWCAP for FEAT_LRCPC3 Catalin Marinas
2 siblings, 0 replies; 4+ messages in thread
From: Joey Gouly @ 2023-09-19 16:27 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: nd, catalin.marinas, joey.gouly, will
FEAT_LRCPC3 adds more instructions to support the Release Consistency model.
Add a HWCAP so that userspace can make decisions about instructions it can use.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
Documentation/arch/arm64/elf_hwcaps.rst | 3 +++
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/include/uapi/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 1 +
arch/arm64/kernel/cpuinfo.c | 1 +
arch/arm64/tools/sysreg | 1 +
6 files changed, 8 insertions(+)
diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst
index 76ff9d7398fd..3cc1d7662f0a 100644
--- a/Documentation/arch/arm64/elf_hwcaps.rst
+++ b/Documentation/arch/arm64/elf_hwcaps.rst
@@ -308,6 +308,9 @@ HWCAP2_MOPS
HWCAP2_HBC
Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.
+HWCAP2_LRCPC3
+ Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.
+
4. Unused AT_HWCAP bits
-----------------------
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 521267478d18..802e74cdb6ad 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -139,6 +139,7 @@
#define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16)
#define KERNEL_HWCAP_MOPS __khwcap2_feature(MOPS)
#define KERNEL_HWCAP_HBC __khwcap2_feature(HBC)
+#define KERNEL_HWCAP_LRCPC3 __khwcap2_feature(LRCPC3)
/*
* This yields a mask that user programs can use to figure out what
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index 53026f45a509..5d24fdc8f5b4 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -104,5 +104,6 @@
#define HWCAP2_SME_F16F16 (1UL << 42)
#define HWCAP2_MOPS (1UL << 43)
#define HWCAP2_HBC (1UL << 44)
+#define HWCAP2_LRCPC3 (1UL << 45)
#endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 444a73c2e638..5f6c8389ff43 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2807,6 +2807,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA),
HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
+ HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3),
HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT),
HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB),
HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16),
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 98fda8500535..4b8a06c9cbe3 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -127,6 +127,7 @@ static const char *const hwcap_str[] = {
[KERNEL_HWCAP_SME_F16F16] = "smef16f16",
[KERNEL_HWCAP_MOPS] = "mops",
[KERNEL_HWCAP_HBC] = "hbc",
+ [KERNEL_HWCAP_LRCPC3] = "lrcpc3",
};
#ifdef CONFIG_COMPAT
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 76ce150e7347..aa701aa56c0f 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1305,6 +1305,7 @@ UnsignedEnum 23:20 LRCPC
0b0000 NI
0b0001 IMP
0b0010 LRCPC2
+ 0b0011 LRCPC3
EndEnum
UnsignedEnum 19:16 FCMA
0b0000 NI
--
2.25.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v1 2/2] selftests/arm64: add HWCAP2_LRCPC3 test
2023-09-19 16:27 [PATCH v1 0/2] HWCAP for FEAT_LRCPC3 Joey Gouly
2023-09-19 16:27 ` [PATCH v1 1/2] arm64: add FEAT_LRCPC3 HWCAP Joey Gouly
@ 2023-09-19 16:27 ` Joey Gouly
2023-10-13 18:44 ` [PATCH v1 0/2] HWCAP for FEAT_LRCPC3 Catalin Marinas
2 siblings, 0 replies; 4+ messages in thread
From: Joey Gouly @ 2023-09-19 16:27 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: nd, catalin.marinas, joey.gouly, will
Add a test for the newly added HWCAP2_LRCPC3.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
tools/testing/selftests/arm64/abi/hwcap.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c
index e3d262831d91..19d548b74111 100644
--- a/tools/testing/selftests/arm64/abi/hwcap.c
+++ b/tools/testing/selftests/arm64/abi/hwcap.c
@@ -289,6 +289,19 @@ static void uscat_sigbus(void)
asm volatile(".inst 0xb820003f" : : : );
}
+static void lrcpc3_sigill(void)
+{
+ int data[2] = { 1, 2 };
+
+ register int *src asm ("x0") = data;
+ register int data0 asm ("w2") = 0;
+ register int data1 asm ("w3") = 0;
+
+ /* LDIAPP w2, w3, [x0] */
+ asm volatile(".inst 0x99431802"
+ : "=r" (data0), "=r" (data1) : "r" (src) :);
+}
+
static const struct hwcap_data {
const char *name;
unsigned long at_hwcap;
@@ -348,6 +361,13 @@ static const struct hwcap_data {
.cpuinfo = "ilrcpc",
.sigill_fn = ilrcpc_sigill,
},
+ {
+ .name = "LRCPC3",
+ .at_hwcap = AT_HWCAP2,
+ .hwcap_bit = HWCAP2_LRCPC3,
+ .cpuinfo = "lrcpc3",
+ .sigill_fn = lrcpc3_sigill,
+ },
{
.name = "LSE",
.at_hwcap = AT_HWCAP,
--
2.25.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v1 0/2] HWCAP for FEAT_LRCPC3
2023-09-19 16:27 [PATCH v1 0/2] HWCAP for FEAT_LRCPC3 Joey Gouly
2023-09-19 16:27 ` [PATCH v1 1/2] arm64: add FEAT_LRCPC3 HWCAP Joey Gouly
2023-09-19 16:27 ` [PATCH v1 2/2] selftests/arm64: add HWCAP2_LRCPC3 test Joey Gouly
@ 2023-10-13 18:44 ` Catalin Marinas
2 siblings, 0 replies; 4+ messages in thread
From: Catalin Marinas @ 2023-10-13 18:44 UTC (permalink / raw)
To: linux-arm-kernel, Joey Gouly; +Cc: Will Deacon, nd
On Tue, 19 Sep 2023 17:27:55 +0100, Joey Gouly wrote:
> Small patches to add a HWCAP for FEAT_LRCPC3 and a test.
>
> Based on arm64 for-next/fixes, so that it wouldn't conflict with the recent HBC
> doc fix, hope that was the right thing to do!
>
> Thanks,
> Joey
>
> [...]
Applied to arm64 (for-next/feat_lrcpc3), thanks!
I changes the HWCAP numbers as we had some patches already queued from
Mark Brown.
[1/2] arm64: add FEAT_LRCPC3 HWCAP
https://git.kernel.org/arm64/c/338a835f40a8
[2/2] selftests/arm64: add HWCAP2_LRCPC3 test
https://git.kernel.org/arm64/c/80652cc0c048
--
Catalin
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-10-13 18:45 UTC | newest]
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2023-09-19 16:27 [PATCH v1 0/2] HWCAP for FEAT_LRCPC3 Joey Gouly
2023-09-19 16:27 ` [PATCH v1 1/2] arm64: add FEAT_LRCPC3 HWCAP Joey Gouly
2023-09-19 16:27 ` [PATCH v1 2/2] selftests/arm64: add HWCAP2_LRCPC3 test Joey Gouly
2023-10-13 18:44 ` [PATCH v1 0/2] HWCAP for FEAT_LRCPC3 Catalin Marinas
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