* [PATCH v3 0/2] riscv: correct pt_level name via pgtable_l5/4_enabled
@ 2023-09-25 15:22 Palmer Dabbelt
2023-09-25 15:22 ` [PATCH v3 1/2] RISC-V: Provide pgtable_l5_enabled on rv32 Palmer Dabbelt
2023-09-25 15:22 ` Palmer Dabbelt
0 siblings, 2 replies; 5+ messages in thread
From: Palmer Dabbelt @ 2023-09-25 15:22 UTC (permalink / raw)
To: linux-riscv
Looks like I forgot about the v2, there was just the one style issue.
Changes since v2 <20230830044129.11481-1-palmer@rivosinc.com>:
* Don't initialize static const with = 0.
Changes since v1 <20230712115740.943324-1-suagrfillet@gmail.com>:
* Fix the rv32 build with patch #1.
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 1/2] RISC-V: Provide pgtable_l5_enabled on rv32
2023-09-25 15:22 [PATCH v3 0/2] riscv: correct pt_level name via pgtable_l5/4_enabled Palmer Dabbelt
@ 2023-09-25 15:22 ` Palmer Dabbelt
2023-09-28 8:13 ` Alexandre Ghiti
2023-09-25 15:22 ` Palmer Dabbelt
1 sibling, 1 reply; 5+ messages in thread
From: Palmer Dabbelt @ 2023-09-25 15:22 UTC (permalink / raw)
To: linux-riscv; +Cc: Palmer Dabbelt
A few of the other page table level helpers are defined on rv32, but not
pgtable_l5_enabled. This adds the definition as a constant and converts
pgtable_l4_enabled to a constant as well.
Link: https://lore.kernel.org/r/20230830044129.11481-2-palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
arch/riscv/include/asm/pgtable-32.h | 3 +++
arch/riscv/include/asm/pgtable.h | 1 -
arch/riscv/mm/init.c | 2 ++
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index 59ba1fbaf784..00f3369570a8 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -33,4 +33,7 @@
_PAGE_WRITE | _PAGE_EXEC | \
_PAGE_USER | _PAGE_GLOBAL))
+static const __maybe_unused int pgtable_l4_enabled;
+static const __maybe_unused int pgtable_l5_enabled;
+
#endif /* _ASM_RISCV_PGTABLE_32_H */
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index b2ba3f79cfe9..e05e5c8f6526 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -914,7 +914,6 @@ extern uintptr_t _dtb_early_pa;
#define dtb_early_pa _dtb_early_pa
#endif /* CONFIG_XIP_KERNEL */
extern u64 satp_mode;
-extern bool pgtable_l4_enabled;
void paging_init(void);
void misc_mem_init(void);
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 0798bd861dcb..eed1758720c9 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -49,10 +49,12 @@ u64 satp_mode __ro_after_init = SATP_MODE_32;
#endif
EXPORT_SYMBOL(satp_mode);
+#ifdef CONFIG_64BIT
bool pgtable_l4_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL);
bool pgtable_l5_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL);
EXPORT_SYMBOL(pgtable_l4_enabled);
EXPORT_SYMBOL(pgtable_l5_enabled);
+#endif
phys_addr_t phys_ram_base __ro_after_init;
EXPORT_SYMBOL(phys_ram_base);
--
2.42.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 2/2] riscv: correct pt_level name via pgtable_l5/4_enabled
2023-09-25 15:22 [PATCH v3 0/2] riscv: correct pt_level name via pgtable_l5/4_enabled Palmer Dabbelt
@ 2023-09-25 15:22 ` Palmer Dabbelt
2023-09-25 15:22 ` Palmer Dabbelt
1 sibling, 0 replies; 5+ messages in thread
From: Palmer Dabbelt @ 2023-09-25 15:22 UTC (permalink / raw)
To: linux-riscv; +Cc: Song Shuai, Alexandre Ghiti, stable, Palmer Dabbelt
From: Song Shuai <suagrfillet@gmail.com>
The pt_level uses CONFIG_PGTABLE_LEVELS to display page table names.
But if page mode is downgraded from kernel cmdline or restricted by
the hardware in 64BIT, it will give a wrong name.
Like, using no4lvl for sv39, ptdump named the 1G-mapping as "PUD"
that should be "PGD":
0xffffffd840000000-0xffffffd900000000 0x00000000c0000000 3G PUD D A G . . W R V
So select "P4D/PUD" or "PGD" via pgtable_l5/4_enabled to correct it.
Fixes: e8a62cc26ddf ("riscv: Implement sv48 support")
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Song Shuai <suagrfillet@gmail.com>
Link: https://lore.kernel.org/r/20230712115740.943324-1-suagrfillet@gmail.com
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20230830044129.11481-3-palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
arch/riscv/mm/ptdump.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index 20a9f991a6d7..e9090b38f811 100644
--- a/arch/riscv/mm/ptdump.c
+++ b/arch/riscv/mm/ptdump.c
@@ -384,6 +384,9 @@ static int __init ptdump_init(void)
kernel_ptd_info.base_addr = KERN_VIRT_START;
+ pg_level[1].name = pgtable_l5_enabled ? "P4D" : "PGD";
+ pg_level[2].name = pgtable_l4_enabled ? "PUD" : "PGD";
+
for (i = 0; i < ARRAY_SIZE(pg_level); i++)
for (j = 0; j < ARRAY_SIZE(pte_bits); j++)
pg_level[i].mask |= pte_bits[j].mask;
--
2.42.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 2/2] riscv: correct pt_level name via pgtable_l5/4_enabled
@ 2023-09-25 15:22 ` Palmer Dabbelt
0 siblings, 0 replies; 5+ messages in thread
From: Palmer Dabbelt @ 2023-09-25 15:22 UTC (permalink / raw)
To: linux-riscv; +Cc: Song Shuai, Alexandre Ghiti, stable, Palmer Dabbelt
From: Song Shuai <suagrfillet@gmail.com>
The pt_level uses CONFIG_PGTABLE_LEVELS to display page table names.
But if page mode is downgraded from kernel cmdline or restricted by
the hardware in 64BIT, it will give a wrong name.
Like, using no4lvl for sv39, ptdump named the 1G-mapping as "PUD"
that should be "PGD":
0xffffffd840000000-0xffffffd900000000 0x00000000c0000000 3G PUD D A G . . W R V
So select "P4D/PUD" or "PGD" via pgtable_l5/4_enabled to correct it.
Fixes: e8a62cc26ddf ("riscv: Implement sv48 support")
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Song Shuai <suagrfillet@gmail.com>
Link: https://lore.kernel.org/r/20230712115740.943324-1-suagrfillet@gmail.com
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20230830044129.11481-3-palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
arch/riscv/mm/ptdump.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index 20a9f991a6d7..e9090b38f811 100644
--- a/arch/riscv/mm/ptdump.c
+++ b/arch/riscv/mm/ptdump.c
@@ -384,6 +384,9 @@ static int __init ptdump_init(void)
kernel_ptd_info.base_addr = KERN_VIRT_START;
+ pg_level[1].name = pgtable_l5_enabled ? "P4D" : "PGD";
+ pg_level[2].name = pgtable_l4_enabled ? "PUD" : "PGD";
+
for (i = 0; i < ARRAY_SIZE(pg_level); i++)
for (j = 0; j < ARRAY_SIZE(pte_bits); j++)
pg_level[i].mask |= pte_bits[j].mask;
--
2.42.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 1/2] RISC-V: Provide pgtable_l5_enabled on rv32
2023-09-25 15:22 ` [PATCH v3 1/2] RISC-V: Provide pgtable_l5_enabled on rv32 Palmer Dabbelt
@ 2023-09-28 8:13 ` Alexandre Ghiti
0 siblings, 0 replies; 5+ messages in thread
From: Alexandre Ghiti @ 2023-09-28 8:13 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv
Hi Palmer,
On 25/09/2023 17:22, Palmer Dabbelt wrote:
> A few of the other page table level helpers are defined on rv32, but not
> pgtable_l5_enabled. This adds the definition as a constant and converts
> pgtable_l4_enabled to a constant as well.
>
> Link: https://lore.kernel.org/r/20230830044129.11481-2-palmer@rivosinc.com
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> arch/riscv/include/asm/pgtable-32.h | 3 +++
> arch/riscv/include/asm/pgtable.h | 1 -
> arch/riscv/mm/init.c | 2 ++
> 3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
> index 59ba1fbaf784..00f3369570a8 100644
> --- a/arch/riscv/include/asm/pgtable-32.h
> +++ b/arch/riscv/include/asm/pgtable-32.h
> @@ -33,4 +33,7 @@
> _PAGE_WRITE | _PAGE_EXEC | \
> _PAGE_USER | _PAGE_GLOBAL))
>
> +static const __maybe_unused int pgtable_l4_enabled;
> +static const __maybe_unused int pgtable_l5_enabled;
pgtable_l4_enabled and pgtable_l5_enabled are boolean, not int.
> +
> #endif /* _ASM_RISCV_PGTABLE_32_H */
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index b2ba3f79cfe9..e05e5c8f6526 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -914,7 +914,6 @@ extern uintptr_t _dtb_early_pa;
> #define dtb_early_pa _dtb_early_pa
> #endif /* CONFIG_XIP_KERNEL */
> extern u64 satp_mode;
> -extern bool pgtable_l4_enabled;
Isn't it easier to add pgtable_l5_enabled here ^
>
> void paging_init(void);
> void misc_mem_init(void);
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index 0798bd861dcb..eed1758720c9 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -49,10 +49,12 @@ u64 satp_mode __ro_after_init = SATP_MODE_32;
> #endif
> EXPORT_SYMBOL(satp_mode);
>
> +#ifdef CONFIG_64BIT
> bool pgtable_l4_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL);
> bool pgtable_l5_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL);
> EXPORT_SYMBOL(pgtable_l4_enabled);
> EXPORT_SYMBOL(pgtable_l5_enabled);
> +#endif
>
And remove the #ifdef?
> phys_addr_t phys_ram_base __ro_after_init;
> EXPORT_SYMBOL(phys_ram_base);
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-09-28 8:13 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2023-09-25 15:22 [PATCH v3 0/2] riscv: correct pt_level name via pgtable_l5/4_enabled Palmer Dabbelt
2023-09-25 15:22 ` [PATCH v3 1/2] RISC-V: Provide pgtable_l5_enabled on rv32 Palmer Dabbelt
2023-09-28 8:13 ` Alexandre Ghiti
2023-09-25 15:22 ` [PATCH v3 2/2] riscv: correct pt_level name via pgtable_l5/4_enabled Palmer Dabbelt
2023-09-25 15:22 ` Palmer Dabbelt
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