* Re: [PATCH 09/11] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT
@ 2023-10-02 9:01 kernel test robot
0 siblings, 0 replies; 3+ messages in thread
From: kernel test robot @ 2023-10-02 9:01 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp, Dan Carpenter
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20230922213032.1770590-10-david.e.box@linux.intel.com>
References: <20230922213032.1770590-10-david.e.box@linux.intel.com>
TO: "David E. Box" <david.e.box@linux.intel.com>
Hi David,
kernel test robot noticed the following build warnings:
[auto build test WARNING on acce85a7dd28eac3858d44230f4c65985d0f271c]
url: https://github.com/intel-lab-lkp/linux/commits/David-E-Box/platform-x86-intel-vsec-Add-intel_vsec_register/20230923-053226
base: acce85a7dd28eac3858d44230f4c65985d0f271c
patch link: https://lore.kernel.org/r/20230922213032.1770590-10-david.e.box%40linux.intel.com
patch subject: [PATCH 09/11] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT
:::::: branch date: 9 days ago
:::::: commit date: 9 days ago
config: x86_64-randconfig-161-20231002 (https://download.01.org/0day-ci/archive/20231002/202310021646.7rGtnqrS-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce: (https://download.01.org/0day-ci/archive/20231002/202310021646.7rGtnqrS-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202310021646.7rGtnqrS-lkp@intel.com/
smatch warnings:
drivers/platform/x86/intel/pmc/core_ssram.c:138 pmc_core_get_lpm_req() error: uninitialized symbol 'ret'.
vim +/ret +138 drivers/platform/x86/intel/pmc/core_ssram.c
4210a66b03fca8 Xi Pardee 2023-09-22 39
4210a66b03fca8 Xi Pardee 2023-09-22 40 static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc)
4210a66b03fca8 Xi Pardee 2023-09-22 41 {
4210a66b03fca8 Xi Pardee 2023-09-22 42 struct telem_endpoint *ep;
4210a66b03fca8 Xi Pardee 2023-09-22 43 const u8 *lpm_indices;
4210a66b03fca8 Xi Pardee 2023-09-22 44 int num_maps, mode_offset = 0;
4210a66b03fca8 Xi Pardee 2023-09-22 45 int ret, mode, i;
4210a66b03fca8 Xi Pardee 2023-09-22 46 int lpm_size;
4210a66b03fca8 Xi Pardee 2023-09-22 47 u32 guid;
4210a66b03fca8 Xi Pardee 2023-09-22 48
4210a66b03fca8 Xi Pardee 2023-09-22 49 lpm_indices = pmc->map->lpm_reg_index;
4210a66b03fca8 Xi Pardee 2023-09-22 50 num_maps = pmc->map->lpm_num_maps;
4210a66b03fca8 Xi Pardee 2023-09-22 51 lpm_size = LPM_MAX_NUM_MODES * num_maps;
4210a66b03fca8 Xi Pardee 2023-09-22 52
4210a66b03fca8 Xi Pardee 2023-09-22 53 guid = pmc_core_find_guid(pmcdev->regmap_list, pmc->map);
4210a66b03fca8 Xi Pardee 2023-09-22 54 if (!guid)
4210a66b03fca8 Xi Pardee 2023-09-22 55 return -ENXIO;
4210a66b03fca8 Xi Pardee 2023-09-22 56
4210a66b03fca8 Xi Pardee 2023-09-22 57 ep = pmt_telem_find_and_register_endpoint(pmcdev->ssram_pcidev, guid, 0);
4210a66b03fca8 Xi Pardee 2023-09-22 58 if (IS_ERR(ep)) {
4210a66b03fca8 Xi Pardee 2023-09-22 59 dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %ld",
4210a66b03fca8 Xi Pardee 2023-09-22 60 PTR_ERR(ep));
4210a66b03fca8 Xi Pardee 2023-09-22 61 return -EPROBE_DEFER;
4210a66b03fca8 Xi Pardee 2023-09-22 62 }
4210a66b03fca8 Xi Pardee 2023-09-22 63
4210a66b03fca8 Xi Pardee 2023-09-22 64 pmc->lpm_req_regs = devm_kzalloc(&pmcdev->pdev->dev,
4210a66b03fca8 Xi Pardee 2023-09-22 65 lpm_size * sizeof(u32),
4210a66b03fca8 Xi Pardee 2023-09-22 66 GFP_KERNEL);
4210a66b03fca8 Xi Pardee 2023-09-22 67 if (!pmc->lpm_req_regs) {
4210a66b03fca8 Xi Pardee 2023-09-22 68 ret = -ENOMEM;
4210a66b03fca8 Xi Pardee 2023-09-22 69 goto unregister_ep;
4210a66b03fca8 Xi Pardee 2023-09-22 70 }
4210a66b03fca8 Xi Pardee 2023-09-22 71
4210a66b03fca8 Xi Pardee 2023-09-22 72 /*
4210a66b03fca8 Xi Pardee 2023-09-22 73 * PMC Low Power Mode (LPM) requirements table
4210a66b03fca8 Xi Pardee 2023-09-22 74 *
4210a66b03fca8 Xi Pardee 2023-09-22 75 * In telemetry space, the LPM table contains a 4 byte header followed
4210a66b03fca8 Xi Pardee 2023-09-22 76 * by 8 consecutive mode blocks (one for each LPM mode). Each block
4210a66b03fca8 Xi Pardee 2023-09-22 77 * has a 4 byte header followed by a set of registers that describe the
4210a66b03fca8 Xi Pardee 2023-09-22 78 * IP state requirements for the given mode. The IP mapping is platform
4210a66b03fca8 Xi Pardee 2023-09-22 79 * specific but the same for each block, making for easy analysis.
4210a66b03fca8 Xi Pardee 2023-09-22 80 * Platforms only use a subset of the space to track the requirements
4210a66b03fca8 Xi Pardee 2023-09-22 81 * for their IPs. Callers provide the requirement registers they use as
4210a66b03fca8 Xi Pardee 2023-09-22 82 * a list of indices. Each requirement register is associated with an
4210a66b03fca8 Xi Pardee 2023-09-22 83 * IP map that's maintained by the caller.
4210a66b03fca8 Xi Pardee 2023-09-22 84 *
4210a66b03fca8 Xi Pardee 2023-09-22 85 * Header
4210a66b03fca8 Xi Pardee 2023-09-22 86 * +----+----------------------------+----------------------------+
4210a66b03fca8 Xi Pardee 2023-09-22 87 * | 0 | REVISION | ENABLED MODES |
4210a66b03fca8 Xi Pardee 2023-09-22 88 * +----+--------------+-------------+-------------+--------------+
4210a66b03fca8 Xi Pardee 2023-09-22 89 *
4210a66b03fca8 Xi Pardee 2023-09-22 90 * Low Power Mode 0 Block
4210a66b03fca8 Xi Pardee 2023-09-22 91 * +----+--------------+-------------+-------------+--------------+
4210a66b03fca8 Xi Pardee 2023-09-22 92 * | 1 | SUB ID | SIZE | MAJOR | MINOR |
4210a66b03fca8 Xi Pardee 2023-09-22 93 * +----+--------------+-------------+-------------+--------------+
4210a66b03fca8 Xi Pardee 2023-09-22 94 * | 2 | LPM0 Requirements 0 |
4210a66b03fca8 Xi Pardee 2023-09-22 95 * +----+---------------------------------------------------------+
4210a66b03fca8 Xi Pardee 2023-09-22 96 * | | ... |
4210a66b03fca8 Xi Pardee 2023-09-22 97 * +----+---------------------------------------------------------+
4210a66b03fca8 Xi Pardee 2023-09-22 98 * | 29 | LPM0 Requirements 27 |
4210a66b03fca8 Xi Pardee 2023-09-22 99 * +----+---------------------------------------------------------+
4210a66b03fca8 Xi Pardee 2023-09-22 100 *
4210a66b03fca8 Xi Pardee 2023-09-22 101 * ...
4210a66b03fca8 Xi Pardee 2023-09-22 102 *
4210a66b03fca8 Xi Pardee 2023-09-22 103 * Low Power Mode 7 Block
4210a66b03fca8 Xi Pardee 2023-09-22 104 * +----+--------------+-------------+-------------+--------------+
4210a66b03fca8 Xi Pardee 2023-09-22 105 * | | SUB ID | SIZE | MAJOR | MINOR |
4210a66b03fca8 Xi Pardee 2023-09-22 106 * +----+--------------+-------------+-------------+--------------+
4210a66b03fca8 Xi Pardee 2023-09-22 107 * | 60 | LPM7 Requirements 0 |
4210a66b03fca8 Xi Pardee 2023-09-22 108 * +----+---------------------------------------------------------+
4210a66b03fca8 Xi Pardee 2023-09-22 109 * | | ... |
4210a66b03fca8 Xi Pardee 2023-09-22 110 * +----+---------------------------------------------------------+
4210a66b03fca8 Xi Pardee 2023-09-22 111 * | 87 | LPM7 Requirements 27 |
4210a66b03fca8 Xi Pardee 2023-09-22 112 * +----+---------------------------------------------------------+
4210a66b03fca8 Xi Pardee 2023-09-22 113 *
4210a66b03fca8 Xi Pardee 2023-09-22 114 */
4210a66b03fca8 Xi Pardee 2023-09-22 115 mode_offset = LPM_HEADER_OFFSET + LPM_MODE_OFFSET;
4210a66b03fca8 Xi Pardee 2023-09-22 116 pmc_for_each_mode(i, mode, pmcdev) {
4210a66b03fca8 Xi Pardee 2023-09-22 117 u32 *req_offset = pmc->lpm_req_regs + (mode * num_maps);
4210a66b03fca8 Xi Pardee 2023-09-22 118 int m;
4210a66b03fca8 Xi Pardee 2023-09-22 119
4210a66b03fca8 Xi Pardee 2023-09-22 120 for (m = 0; m < num_maps; m++) {
4210a66b03fca8 Xi Pardee 2023-09-22 121 u8 sample_id = lpm_indices[m] + mode_offset;
4210a66b03fca8 Xi Pardee 2023-09-22 122
4210a66b03fca8 Xi Pardee 2023-09-22 123 ret = pmt_telem_read32(ep, sample_id, req_offset, 1);
4210a66b03fca8 Xi Pardee 2023-09-22 124 if (ret) {
4210a66b03fca8 Xi Pardee 2023-09-22 125 dev_err(&pmcdev->pdev->dev,
4210a66b03fca8 Xi Pardee 2023-09-22 126 "couldn't read Low Power Mode requirements: %d\n", ret);
4210a66b03fca8 Xi Pardee 2023-09-22 127 devm_kfree(&pmcdev->pdev->dev, pmc->lpm_req_regs);
4210a66b03fca8 Xi Pardee 2023-09-22 128 goto unregister_ep;
4210a66b03fca8 Xi Pardee 2023-09-22 129 }
4210a66b03fca8 Xi Pardee 2023-09-22 130 ++req_offset;
4210a66b03fca8 Xi Pardee 2023-09-22 131 }
4210a66b03fca8 Xi Pardee 2023-09-22 132 mode_offset += (LPM_REG_COUNT + LPM_MODE_OFFSET);
4210a66b03fca8 Xi Pardee 2023-09-22 133 }
4210a66b03fca8 Xi Pardee 2023-09-22 134
4210a66b03fca8 Xi Pardee 2023-09-22 135 unregister_ep:
4210a66b03fca8 Xi Pardee 2023-09-22 136 pmt_telem_unregister_endpoint(ep);
4210a66b03fca8 Xi Pardee 2023-09-22 137
4210a66b03fca8 Xi Pardee 2023-09-22 @138 return ret;
4210a66b03fca8 Xi Pardee 2023-09-22 139 }
4210a66b03fca8 Xi Pardee 2023-09-22 140
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 09/11] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT
2023-09-22 21:30 ` [PATCH 09/11] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT David E. Box
@ 2023-09-26 16:07 ` Ilpo Järvinen
0 siblings, 0 replies; 3+ messages in thread
From: Ilpo Järvinen @ 2023-09-26 16:07 UTC (permalink / raw)
To: David E. Box; +Cc: LKML, platform-driver-x86, rajvi.jingar
On Fri, 22 Sep 2023, David E. Box wrote:
> From: Xi Pardee <xi.pardee@intel.com>
>
> On supported platforms, the low power mode (LPM) requirements for entering
> each idle substate are described in Platform Monitoring Technology (PMT)
> telemetry entries. Provide a function for platform code to attempt to find
> and read the requirements from the telemetry entries.
>
> Signed-off-by: Xi Pardee <xi.pardee@intel.com>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> ---
> drivers/platform/x86/intel/pmc/core.h | 3 +
> drivers/platform/x86/intel/pmc/core_ssram.c | 135 ++++++++++++++++++++
> 2 files changed, 138 insertions(+)
>
> diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
> index edaa70067e41..85b6f6ae4995 100644
> --- a/drivers/platform/x86/intel/pmc/core.h
> +++ b/drivers/platform/x86/intel/pmc/core.h
> @@ -320,6 +320,7 @@ struct pmc_reg_map {
> const u32 lpm_status_offset;
> const u32 lpm_live_status_offset;
> const u32 etr3_offset;
> + const u8 *lpm_reg_index;
> };
>
> /**
> @@ -329,6 +330,7 @@ struct pmc_reg_map {
> * specific attributes
> */
> struct pmc_info {
> + u32 guid;
> u16 devid;
> const struct pmc_reg_map *map;
> };
> @@ -486,6 +488,7 @@ extern const struct pmc_bit_map *mtl_ioem_lpm_maps[];
> extern const struct pmc_reg_map mtl_ioem_reg_map;
>
> extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
> +extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev);
> extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value);
>
> int pmc_core_resume_common(struct pmc_dev *pmcdev);
> diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c
> index b2abaf106bc5..a0ce4e8b1b6d 100644
> --- a/drivers/platform/x86/intel/pmc/core_ssram.c
> +++ b/drivers/platform/x86/intel/pmc/core_ssram.c
> @@ -23,6 +23,140 @@
> #define SSRAM_IOE_OFFSET 0x68
> #define SSRAM_DEVID_OFFSET 0x70
>
> +/* PCH query */
> +#define LPM_HEADER_OFFSET 1
> +#define LPM_REG_COUNT 28
> +#define LPM_MODE_OFFSET 1
> +
> +static u32 pmc_core_find_guid(struct pmc_info *list, const struct pmc_reg_map *map)
> +{
> + for (; list->map; ++list)
> + if (list->map == map)
> + return list->guid;
> +
> + return 0;
> +}
> +
> +static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc)
> +{
> + struct telem_endpoint *ep;
> + const u8 *lpm_indices;
> + int num_maps, mode_offset = 0;
> + int ret, mode, i;
> + int lpm_size;
> + u32 guid;
> +
> + lpm_indices = pmc->map->lpm_reg_index;
> + num_maps = pmc->map->lpm_num_maps;
> + lpm_size = LPM_MAX_NUM_MODES * num_maps;
> +
> + guid = pmc_core_find_guid(pmcdev->regmap_list, pmc->map);
> + if (!guid)
> + return -ENXIO;
> +
> + ep = pmt_telem_find_and_register_endpoint(pmcdev->ssram_pcidev, guid, 0);
> + if (IS_ERR(ep)) {
> + dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %ld",
> + PTR_ERR(ep));
> + return -EPROBE_DEFER;
> + }
> +
> + pmc->lpm_req_regs = devm_kzalloc(&pmcdev->pdev->dev,
> + lpm_size * sizeof(u32),
> + GFP_KERNEL);
> + if (!pmc->lpm_req_regs) {
> + ret = -ENOMEM;
> + goto unregister_ep;
> + }
> +
> + /*
> + * PMC Low Power Mode (LPM) requirements table
> + *
> + * In telemetry space, the LPM table contains a 4 byte header followed
> + * by 8 consecutive mode blocks (one for each LPM mode). Each block
> + * has a 4 byte header followed by a set of registers that describe the
> + * IP state requirements for the given mode. The IP mapping is platform
> + * specific but the same for each block, making for easy analysis.
> + * Platforms only use a subset of the space to track the requirements
> + * for their IPs. Callers provide the requirement registers they use as
> + * a list of indices. Each requirement register is associated with an
> + * IP map that's maintained by the caller.
> + *
> + * Header
> + * +----+----------------------------+----------------------------+
> + * | 0 | REVISION | ENABLED MODES |
> + * +----+--------------+-------------+-------------+--------------+
> + *
> + * Low Power Mode 0 Block
> + * +----+--------------+-------------+-------------+--------------+
> + * | 1 | SUB ID | SIZE | MAJOR | MINOR |
> + * +----+--------------+-------------+-------------+--------------+
> + * | 2 | LPM0 Requirements 0 |
> + * +----+---------------------------------------------------------+
> + * | | ... |
> + * +----+---------------------------------------------------------+
> + * | 29 | LPM0 Requirements 27 |
> + * +----+---------------------------------------------------------+
> + *
> + * ...
> + *
> + * Low Power Mode 7 Block
> + * +----+--------------+-------------+-------------+--------------+
> + * | | SUB ID | SIZE | MAJOR | MINOR |
> + * +----+--------------+-------------+-------------+--------------+
> + * | 60 | LPM7 Requirements 0 |
> + * +----+---------------------------------------------------------+
> + * | | ... |
> + * +----+---------------------------------------------------------+
> + * | 87 | LPM7 Requirements 27 |
> + * +----+---------------------------------------------------------+
> + *
> + */
> + mode_offset = LPM_HEADER_OFFSET + LPM_MODE_OFFSET;
> + pmc_for_each_mode(i, mode, pmcdev) {
> + u32 *req_offset = pmc->lpm_req_regs + (mode * num_maps);
> + int m;
> +
> + for (m = 0; m < num_maps; m++) {
> + u8 sample_id = lpm_indices[m] + mode_offset;
> +
> + ret = pmt_telem_read32(ep, sample_id, req_offset, 1);
> + if (ret) {
> + dev_err(&pmcdev->pdev->dev,
> + "couldn't read Low Power Mode requirements: %d\n", ret);
> + devm_kfree(&pmcdev->pdev->dev, pmc->lpm_req_regs);
> + goto unregister_ep;
> + }
> + ++req_offset;
> + }
> + mode_offset += (LPM_REG_COUNT + LPM_MODE_OFFSET);
Unnecessary parenthesis.
--
i.
> + }
> +
> +unregister_ep:
> + pmt_telem_unregister_endpoint(ep);
> +
> + return ret;
> +}
> +
> +int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev)
> +{
> + int ret, i;
> +
> + if (!pmcdev->ssram_pcidev)
> + return -ENODEV;
> +
> + for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
> + if (!pmcdev->pmcs[i])
> + continue;
> +
> + ret = pmc_core_get_lpm_req(pmcdev, pmcdev->pmcs[i]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static void
> pmc_add_pmt(struct pmc_dev *pmcdev, u64 ssram_base, void __iomem *ssram)
> {
> @@ -234,3 +368,4 @@ int pmc_core_ssram_init(struct pmc_dev *pmcdev)
> return ret;
> }
> MODULE_IMPORT_NS(INTEL_VSEC);
> +MODULE_IMPORT_NS(INTEL_PMT_TELEMETRY);
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 09/11] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT
2023-09-22 21:30 [PATCH 00/11] intel_pmc: Add telemetry API to read counters David E. Box
@ 2023-09-22 21:30 ` David E. Box
2023-09-26 16:07 ` Ilpo Järvinen
0 siblings, 1 reply; 3+ messages in thread
From: David E. Box @ 2023-09-22 21:30 UTC (permalink / raw)
To: linux-kernel, david.e.box, platform-driver-x86, ilpo.jarvinen,
rajvi.jingar
From: Xi Pardee <xi.pardee@intel.com>
On supported platforms, the low power mode (LPM) requirements for entering
each idle substate are described in Platform Monitoring Technology (PMT)
telemetry entries. Provide a function for platform code to attempt to find
and read the requirements from the telemetry entries.
Signed-off-by: Xi Pardee <xi.pardee@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
---
drivers/platform/x86/intel/pmc/core.h | 3 +
drivers/platform/x86/intel/pmc/core_ssram.c | 135 ++++++++++++++++++++
2 files changed, 138 insertions(+)
diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index edaa70067e41..85b6f6ae4995 100644
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -320,6 +320,7 @@ struct pmc_reg_map {
const u32 lpm_status_offset;
const u32 lpm_live_status_offset;
const u32 etr3_offset;
+ const u8 *lpm_reg_index;
};
/**
@@ -329,6 +330,7 @@ struct pmc_reg_map {
* specific attributes
*/
struct pmc_info {
+ u32 guid;
u16 devid;
const struct pmc_reg_map *map;
};
@@ -486,6 +488,7 @@ extern const struct pmc_bit_map *mtl_ioem_lpm_maps[];
extern const struct pmc_reg_map mtl_ioem_reg_map;
extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
+extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev);
extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value);
int pmc_core_resume_common(struct pmc_dev *pmcdev);
diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c
index b2abaf106bc5..a0ce4e8b1b6d 100644
--- a/drivers/platform/x86/intel/pmc/core_ssram.c
+++ b/drivers/platform/x86/intel/pmc/core_ssram.c
@@ -23,6 +23,140 @@
#define SSRAM_IOE_OFFSET 0x68
#define SSRAM_DEVID_OFFSET 0x70
+/* PCH query */
+#define LPM_HEADER_OFFSET 1
+#define LPM_REG_COUNT 28
+#define LPM_MODE_OFFSET 1
+
+static u32 pmc_core_find_guid(struct pmc_info *list, const struct pmc_reg_map *map)
+{
+ for (; list->map; ++list)
+ if (list->map == map)
+ return list->guid;
+
+ return 0;
+}
+
+static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc)
+{
+ struct telem_endpoint *ep;
+ const u8 *lpm_indices;
+ int num_maps, mode_offset = 0;
+ int ret, mode, i;
+ int lpm_size;
+ u32 guid;
+
+ lpm_indices = pmc->map->lpm_reg_index;
+ num_maps = pmc->map->lpm_num_maps;
+ lpm_size = LPM_MAX_NUM_MODES * num_maps;
+
+ guid = pmc_core_find_guid(pmcdev->regmap_list, pmc->map);
+ if (!guid)
+ return -ENXIO;
+
+ ep = pmt_telem_find_and_register_endpoint(pmcdev->ssram_pcidev, guid, 0);
+ if (IS_ERR(ep)) {
+ dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %ld",
+ PTR_ERR(ep));
+ return -EPROBE_DEFER;
+ }
+
+ pmc->lpm_req_regs = devm_kzalloc(&pmcdev->pdev->dev,
+ lpm_size * sizeof(u32),
+ GFP_KERNEL);
+ if (!pmc->lpm_req_regs) {
+ ret = -ENOMEM;
+ goto unregister_ep;
+ }
+
+ /*
+ * PMC Low Power Mode (LPM) requirements table
+ *
+ * In telemetry space, the LPM table contains a 4 byte header followed
+ * by 8 consecutive mode blocks (one for each LPM mode). Each block
+ * has a 4 byte header followed by a set of registers that describe the
+ * IP state requirements for the given mode. The IP mapping is platform
+ * specific but the same for each block, making for easy analysis.
+ * Platforms only use a subset of the space to track the requirements
+ * for their IPs. Callers provide the requirement registers they use as
+ * a list of indices. Each requirement register is associated with an
+ * IP map that's maintained by the caller.
+ *
+ * Header
+ * +----+----------------------------+----------------------------+
+ * | 0 | REVISION | ENABLED MODES |
+ * +----+--------------+-------------+-------------+--------------+
+ *
+ * Low Power Mode 0 Block
+ * +----+--------------+-------------+-------------+--------------+
+ * | 1 | SUB ID | SIZE | MAJOR | MINOR |
+ * +----+--------------+-------------+-------------+--------------+
+ * | 2 | LPM0 Requirements 0 |
+ * +----+---------------------------------------------------------+
+ * | | ... |
+ * +----+---------------------------------------------------------+
+ * | 29 | LPM0 Requirements 27 |
+ * +----+---------------------------------------------------------+
+ *
+ * ...
+ *
+ * Low Power Mode 7 Block
+ * +----+--------------+-------------+-------------+--------------+
+ * | | SUB ID | SIZE | MAJOR | MINOR |
+ * +----+--------------+-------------+-------------+--------------+
+ * | 60 | LPM7 Requirements 0 |
+ * +----+---------------------------------------------------------+
+ * | | ... |
+ * +----+---------------------------------------------------------+
+ * | 87 | LPM7 Requirements 27 |
+ * +----+---------------------------------------------------------+
+ *
+ */
+ mode_offset = LPM_HEADER_OFFSET + LPM_MODE_OFFSET;
+ pmc_for_each_mode(i, mode, pmcdev) {
+ u32 *req_offset = pmc->lpm_req_regs + (mode * num_maps);
+ int m;
+
+ for (m = 0; m < num_maps; m++) {
+ u8 sample_id = lpm_indices[m] + mode_offset;
+
+ ret = pmt_telem_read32(ep, sample_id, req_offset, 1);
+ if (ret) {
+ dev_err(&pmcdev->pdev->dev,
+ "couldn't read Low Power Mode requirements: %d\n", ret);
+ devm_kfree(&pmcdev->pdev->dev, pmc->lpm_req_regs);
+ goto unregister_ep;
+ }
+ ++req_offset;
+ }
+ mode_offset += (LPM_REG_COUNT + LPM_MODE_OFFSET);
+ }
+
+unregister_ep:
+ pmt_telem_unregister_endpoint(ep);
+
+ return ret;
+}
+
+int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev)
+{
+ int ret, i;
+
+ if (!pmcdev->ssram_pcidev)
+ return -ENODEV;
+
+ for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
+ if (!pmcdev->pmcs[i])
+ continue;
+
+ ret = pmc_core_get_lpm_req(pmcdev, pmcdev->pmcs[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static void
pmc_add_pmt(struct pmc_dev *pmcdev, u64 ssram_base, void __iomem *ssram)
{
@@ -234,3 +368,4 @@ int pmc_core_ssram_init(struct pmc_dev *pmcdev)
return ret;
}
MODULE_IMPORT_NS(INTEL_VSEC);
+MODULE_IMPORT_NS(INTEL_PMT_TELEMETRY);
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-10-02 9:02 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-10-02 9:01 [PATCH 09/11] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT kernel test robot
-- strict thread matches above, loose matches on Subject: below --
2023-09-22 21:30 [PATCH 00/11] intel_pmc: Add telemetry API to read counters David E. Box
2023-09-22 21:30 ` [PATCH 09/11] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT David E. Box
2023-09-26 16:07 ` Ilpo Järvinen
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