[PATCH 1/2] drm/amdgpu/umsch: correct IP version format

[PATCH 1/2] drm/amdgpu/umsch: correct IP version format

[Lang Yu]

FW uses IP_VERSION_MAJ_MIN_REV format.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index 63917e2b51b4..8e7b763cfdb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -285,15 +285,18 @@ static int umsch_mm_v4_0_set_hw_resources(struct amdgpu_umsch_mm *umsch)
 
 	memcpy(set_hw_resources.mmhub_base, adev->reg_offset[MMHUB_HWIP][0],
 	       sizeof(uint32_t) * 5);
-	set_hw_resources.mmhub_version = amdgpu_ip_version(adev, MMHUB_HWIP, 0);
+	set_hw_resources.mmhub_version =
+		IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, MMHUB_HWIP, 0));
 
 	memcpy(set_hw_resources.osssys_base, adev->reg_offset[OSSSYS_HWIP][0],
 	       sizeof(uint32_t) * 5);
 	set_hw_resources.osssys_version =
-		amdgpu_ip_version(adev, OSSSYS_HWIP, 0);
+		IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, OSSSYS_HWIP, 0));
 
-	set_hw_resources.vcn_version = amdgpu_ip_version(adev, VCN_HWIP, 0);
-	set_hw_resources.vpe_version = amdgpu_ip_version(adev, VPE_HWIP, 0);
+	set_hw_resources.vcn_version =
+		IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCN_HWIP, 0));
+	set_hw_resources.vpe_version =
+		IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0));
 
 	set_hw_resources.api_status.api_completion_fence_addr = umsch->ring.fence_drv.gpu_addr;
 	set_hw_resources.api_status.api_completion_fence_value = ++umsch->ring.fence_drv.sync_seq;
-- 
2.25.1

[PATCH 2/2] drm/amdgpu/umsch: fix missing stuff during rebase

[Lang Yu]

These are missed during rebase.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 771ef8017a98..3713d0749813 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -674,6 +674,8 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
 		return "UMSCH_MM_UCODE";
 	case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
 		return "UMSCH_MM_DATA";
+	case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER:
+		return "UMSCH_MM_CMD_BUFFER";
 	default:
 		return "UNKNOWN UCODE";
 	}
@@ -806,6 +808,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
 	sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
 	imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
 	vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data;
+	umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data;
 
 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 		switch (ucode->ucode_id) {
-- 
2.25.1

RE: [PATCH 2/2] drm/amdgpu/umsch: fix missing stuff during rebase

[Gopalakrishnan, Veerabadhran (Veera)]

[AMD Official Use Only - General]

The series is Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>

-Veera

-----Original Message-----
From: Yu, Lang <Lang.Yu@amd.com>
Sent: Thursday, October 12, 2023 1:05 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Gopalakrishnan, Veerabadhran (Veera) <Veerabadhran.Gopalakrishnan@amd.com>; Yu, Lang <Lang.Yu@amd.com>
Subject: [PATCH 2/2] drm/amdgpu/umsch: fix missing stuff during rebase

These are missed during rebase.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 771ef8017a98..3713d0749813 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -674,6 +674,8 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
                return "UMSCH_MM_UCODE";
        case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
                return "UMSCH_MM_DATA";
+       case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER:
+               return "UMSCH_MM_CMD_BUFFER";
        default:
                return "UNKNOWN UCODE";
        }
@@ -806,6 +808,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
        sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
        imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
        vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data;
+       umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data;

        if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
                switch (ucode->ucode_id) {
--
2.25.1