[Buildroot] [PATCH v5 01/10] package/binutils-bare-metal: new package

[Buildroot] [PATCH v5 01/10] package/binutils-bare-metal: new package

[Neal Frager via buildroot]

This patch adds a new package for building binutils for a bare-metal toolchain.
The cpu architecture is defined by a toolchain-bare-metal virtual package.
While any cpu architecture could be used, the default configuration will be a
Xilinx microblaze little endian architecture, so that buildroot will be able
to build the microblaze firmware applications for zynqmp and versal.

In order to build the zynqmp pmufw and versal plm applications without error,
binutils version 2.41 or higher is required with the following patches.  All
five of these patches have been submitted upstream with four of them already
applied.

0003-opcodes-microblaze-Add-wdc-instructions.patch:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=a4045fdf2e859a23b7817f6dd5b18a1f6d22fc49

0004-opcodes-microblaze-Add-suspend-instructions.patch:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=6487710babec2e7dcae997f79e03b9ec7d78e1c3

0005-opcodes-microblaze-Add-address-entension-instructions.patch:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=b90eb3e5b25c22ec6ee476e500aa902f77b43349

0006-opcodes-microblaze-Add-new-bit-field-instructions.patch:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=bb0d05ff74fda6b8f3f83712ebba3ea36bff1426

0007-bfd-microblaze-Add-32_NONE-reloc-type.patch:
https://patchwork.sourceware.org/project/binutils/patch/20231017084007.229397-1-neal.frager@amd.com/

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
---
V1->V2:
 - removed default enable to be replaced with toolchain select config
V2->V3:
 - no changes
V3->V4:
 - split tar instruction into multiple lines
 - replaced unnecessary =? with = for assignments
 - changed xlnx-rel-v2023.1.tar.gz hash to sha256
 - improved menuconfig help comment
V4->V5:
 - moved to upstream version 2.41 with needed patches
 - reduced all lines to <80 chars
---
 DEVELOPERS                                    |   4 +
 .../2.41/0001-sh-conf.patch                   |   1 +
 .../2.41/0002-poison-system-directories.patch |   1 +
 ...odes-microblaze-Add-wdc-instructions.patch |  83 ++++++
 ...-microblaze-Add-suspend-instructions.patch |  24 ++
 ...e-Add-address-entension-instructions.patch |  78 ++++++
 ...blaze-Add-new-bit-field-instructions.patch | 265 ++++++++++++++++++
 ...fd-microblaze-Add-32_NONE-reloc-type.patch | 220 +++++++++++++++
 package/binutils-bare-metal/Config.in.host    |  15 +
 .../binutils-bare-metal.hash                  |   6 +
 .../binutils-bare-metal.mk                    |  39 +++
 11 files changed, 736 insertions(+)
 create mode 120000 package/binutils-bare-metal/2.41/0001-sh-conf.patch
 create mode 120000 package/binutils-bare-metal/2.41/0002-poison-system-directories.patch
 create mode 100644 package/binutils-bare-metal/2.41/0003-opcodes-microblaze-Add-wdc-instructions.patch
 create mode 100644 package/binutils-bare-metal/2.41/0004-opcodes-microblaze-Add-suspend-instructions.patch
 create mode 100644 package/binutils-bare-metal/2.41/0005-opcodes-microblaze-Add-address-entension-instructions.patch
 create mode 100644 package/binutils-bare-metal/2.41/0006-opcodes-microblaze-Add-new-bit-field-instructions.patch
 create mode 100644 package/binutils-bare-metal/2.41/0007-bfd-microblaze-Add-32_NONE-reloc-type.patch
 create mode 100644 package/binutils-bare-metal/Config.in.host
 create mode 100644 package/binutils-bare-metal/binutils-bare-metal.hash
 create mode 100644 package/binutils-bare-metal/binutils-bare-metal.mk

diff --git a/DEVELOPERS b/DEVELOPERS
index 57015e245e..9c2b664426 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -1366,6 +1366,9 @@ F:	package/mrp/
 N:	Ian Haylock <haylocki@yahoo.co.uk>
 F:	package/python-rpi-gpio/
 
+N:	Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
+F:	package/binutils-bare-metal/
+
 N:	Ignacy Gawędzki <ignacy.gawedzki@green-communications.fr>
 F:	package/angularjs/
 
@@ -2197,6 +2200,7 @@ F:	configs/zynq_zc706_defconfig
 F:	configs/zynqmp_kria_kv260_defconfig
 F:	configs/zynqmp_zcu102_defconfig
 F:	configs/zynqmp_zcu106_defconfig
+F:	package/binutils-bare-metal/
 F:	package/bootgen/
 F:	package/versal-firmware/
 
diff --git a/package/binutils-bare-metal/2.41/0001-sh-conf.patch b/package/binutils-bare-metal/2.41/0001-sh-conf.patch
new file mode 120000
index 0000000000..26dff99523
--- /dev/null
+++ b/package/binutils-bare-metal/2.41/0001-sh-conf.patch
@@ -0,0 +1 @@
+../../binutils/2.41/0001-sh-conf.patch
\ No newline at end of file
diff --git a/package/binutils-bare-metal/2.41/0002-poison-system-directories.patch b/package/binutils-bare-metal/2.41/0002-poison-system-directories.patch
new file mode 120000
index 0000000000..9979f954a9
--- /dev/null
+++ b/package/binutils-bare-metal/2.41/0002-poison-system-directories.patch
@@ -0,0 +1 @@
+../../binutils/2.41/0002-poison-system-directories.patch
\ No newline at end of file
diff --git a/package/binutils-bare-metal/2.41/0003-opcodes-microblaze-Add-wdc-instructions.patch b/package/binutils-bare-metal/2.41/0003-opcodes-microblaze-Add-wdc-instructions.patch
new file mode 100644
index 0000000000..db102aacaf
--- /dev/null
+++ b/package/binutils-bare-metal/2.41/0003-opcodes-microblaze-Add-wdc-instructions.patch
@@ -0,0 +1,83 @@
+From a4045fdf2e859a23b7817f6dd5b18a1f6d22fc49 Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager@amd.com>
+Date: Wed, 27 Sep 2023 14:47:01 +0100
+Subject: [PATCH] opcodes: microblaze: Add wdc.ext.clear and wdc.ext.flush
+ insns
+
+---
+ opcodes/microblaze-opc.h  | 31 +++++++++++++++++--------------
+ opcodes/microblaze-opcm.h |  4 ++--
+ 2 files changed, 19 insertions(+), 16 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 94048e67551..7c70c80a27b 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -74,24 +74,25 @@
+ #define IMMVAL_MASK_MTS 0x4000
+ #define IMMVAL_MASK_MFS 0x0000
+ 
+-#define OPCODE_MASK_H   0xFC000000  /* High 6 bits only.  */
+-#define OPCODE_MASK_H1  0xFFE00000  /* High 11 bits.  */
+-#define OPCODE_MASK_H2  0xFC1F0000  /* High 6 and bits 20-16.  */
+-#define OPCODE_MASK_H12 0xFFFF0000  /* High 16.  */
+-#define OPCODE_MASK_H4  0xFC0007FF  /* High 6 and low 11 bits.  */
+-#define OPCODE_MASK_H13S 0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits
++#define OPCODE_MASK_H     0xFC000000 /* High 6 bits only.  */
++#define OPCODE_MASK_H1    0xFFE00000 /* High 11 bits.  */
++#define OPCODE_MASK_H2    0xFC1F0000 /* High 6 and bits 20-16.  */
++#define OPCODE_MASK_H12   0xFFFF0000 /* High 16.  */
++#define OPCODE_MASK_H4    0xFC0007FF /* High 6 and low 11 bits.  */
++#define OPCODE_MASK_H13S  0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits
+                                        and last nibble of last byte for spr.  */
+-#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last
++#define OPCODE_MASK_H23S  0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last
+ 				       nibble of last byte for spr.  */
+-#define OPCODE_MASK_H34 0xFC00FFFF  /* High 6 and low 16 bits.  */
+-#define OPCODE_MASK_H14 0xFFE007FF  /* High 11 and low 11 bits.  */
+-#define OPCODE_MASK_H24 0xFC1F07FF  /* High 6, bits 20-16 and low 11 bits.  */
++#define OPCODE_MASK_H34   0xFC00FFFF /* High 6 and low 16 bits.  */
++#define OPCODE_MASK_H14   0xFFE007FF /* High 11 and low 11 bits.  */
++#define OPCODE_MASK_H24   0xFC1F07FF /* High 6, bits 20-16 and low 11 bits.  */
+ #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+-#define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
+-#define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
+-#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
+-#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
++#define OPCODE_MASK_H3    0xFC000600 /* High 6 bits and bits 21, 22.  */
++#define OPCODE_MASK_H32   0xFC00FC00 /* High 6 bits and bit 16-21.  */
++#define OPCODE_MASK_H34B  0xFC0000FF /* High 6 bits and low 8 bits.  */
++#define OPCODE_MASK_H35B  0xFC0004FF /* High 6 bits and low 9 bits.  */
++#define OPCODE_MASK_H34C  0xFC0007E0 /* High 6 bits and bits 21-26.  */
+ 
+ /* New Mask for msrset, msrclr insns.  */
+ #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+@@ -174,7 +175,9 @@ const struct op_code_struct
+   {"wic",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+   {"wdc",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+   {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
++  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
++  {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 4cf6f077219..92c245dc0fd 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,8 +33,8 @@ enum microblaze_instr
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+-  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+-  brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
++  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
++  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+   bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+-- 
+2.39.3
+
diff --git a/package/binutils-bare-metal/2.41/0004-opcodes-microblaze-Add-suspend-instructions.patch b/package/binutils-bare-metal/2.41/0004-opcodes-microblaze-Add-suspend-instructions.patch
new file mode 100644
index 0000000000..9f791bfb8a
--- /dev/null
+++ b/package/binutils-bare-metal/2.41/0004-opcodes-microblaze-Add-suspend-instructions.patch
@@ -0,0 +1,24 @@
+From 6487710babec2e7dcae997f79e03b9ec7d78e1c3 Mon Sep 17 00:00:00 2001
+From: Neal frager <neal.frager@amd.com>
+Date: Wed, 4 Oct 2023 16:35:44 +0100
+Subject: [PATCH] opcodes: microblaze: Add hibernate and suspend instructions
+
+---
+ opcodes/microblaze-opc.h  | 2 ++
+ 1 files changed, 2 insertions(+)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 7c70c80a27b..6b9701bb67c 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -405,6 +405,8 @@ const struct op_code_struct
+   {"clz",       INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34,  clz,       special_inst },
+   {"mbar",      INST_TYPE_IMM5,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN,   mbar,      special_inst },
+   {"sleep",     INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 16.  */
++  {"hibernate", INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 8.   */
++  {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
+   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
+   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
+   {NULL, 0, 0, 0, 0, 0, 0, 0, 0},
+-- 
+2.39.3
diff --git a/package/binutils-bare-metal/2.41/0005-opcodes-microblaze-Add-address-entension-instructions.patch b/package/binutils-bare-metal/2.41/0005-opcodes-microblaze-Add-address-entension-instructions.patch
new file mode 100644
index 0000000000..dd92bd0d3f
--- /dev/null
+++ b/package/binutils-bare-metal/2.41/0005-opcodes-microblaze-Add-address-entension-instructions.patch
@@ -0,0 +1,78 @@
+From b90eb3e5b25c22ec6ee476e500aa902f77b43349 Mon Sep 17 00:00:00 2001
+From: Neal frager <neal.frager@amd.com>
+Date: Thu, 5 Oct 2023 10:59:03 +0100
+Subject: [PATCH] microblaze: Add address extension instructions
+
+  * microblaze-opcm.h (struct op_code_struct): Add address extension entries.
+  * microblaze-opc.h: Add address extension instructions.
+---
+ opcodes/microblaze-opc.h  | 9 +++++++++
+ opcodes/microblaze-opcm.h | 10 +++++-----
+ 2 files changed, 14 insertions(+), 5 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 6b9701bb67c..7398e9e246a 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -178,8 +178,11 @@ const struct op_code_struct
+   {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+   {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
++  {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
+   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
++  {"mtse",  INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
+   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
++  {"mfse",  INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
+   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+   {"brd",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
+   {"brld",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
+@@ -229,18 +232,24 @@ const struct op_code_struct
+   {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
+   {"lbu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
+   {"lbur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
++  {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
+   {"lhu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
+   {"lhur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
++  {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
+   {"lw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
+   {"lwr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
+   {"lwx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
++  {"lwea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
+   {"sb",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
+   {"sbr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
++  {"sbea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
+   {"sh",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
+   {"shr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
++  {"shea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
+   {"sw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
+   {"swr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
+   {"swx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
++  {"swea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
+   {"lbui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
+   {"lhui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
+   {"lwi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 9d1df0814d9..c91b002d951 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,13 +33,13 @@ enum microblaze_instr
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+-  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
+-  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+-  bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
++  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
++  mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
++  bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+-  bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+-  shr, sw, swr, swx, lbui, lhui, lwi,
++  bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
++  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+   sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
+   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+   /* 'fsqrt' is a glibc:math.h symbol.  */
+-- 
+2.39.3
diff --git a/package/binutils-bare-metal/2.41/0006-opcodes-microblaze-Add-new-bit-field-instructions.patch b/package/binutils-bare-metal/2.41/0006-opcodes-microblaze-Add-new-bit-field-instructions.patch
new file mode 100644
index 0000000000..12168737b0
--- /dev/null
+++ b/package/binutils-bare-metal/2.41/0006-opcodes-microblaze-Add-new-bit-field-instructions.patch
@@ -0,0 +1,265 @@
+From bb0d05ff74fda6b8f3f83712ebba3ea36bff1426 Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager@amd.com>
+Date: Fri, 13 Oct 2023 08:28:55 +0100
+Subject: [PATCH] opcodes: microblaze: Add new bit-field instructions
+
+This patches adds new bsefi and bsifi instructions.
+BSEFI- The instruction shall extract a bit field from a
+register and place it right-adjusted in the destination register.
+The other bits in the destination register shall be set to zero.
+BSIFI- The instruction shall insert a right-adjusted bit field
+from a register at another position in the destination register.
+The rest of the bits in the destination register shall be unchanged.
+
+Further documentation of these instructions can be found here:
+https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref
+
+With version 6 of the patch, no new relocation types are added as
+this was unnecessary for adding the bsefi and bsifi instructions.
+
+FIXED: Segfault caused by incorrect termination of microblaze_opcodes.
+
+Signed-off-by: nagaraju <nagaraju.mekala@amd.com>
+Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
+Signed-off-by: Neal Frager <neal.frager@amd.com>
+Signed-off-by: Michael J. Eager <eager@eagercon.com>
+---
+ gas/config/tc-microblaze.c | 83 +++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c   | 23 +++++++++++
+ opcodes/microblaze-opc.h   | 13 +++++-
+ opcodes/microblaze-opcm.h  |  6 ++-
+ 4 files changed, 121 insertions(+), 4 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index d900a9e1d05..b510da95024 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -915,7 +915,7 @@ md_assemble (char * str)
+   unsigned reg2;
+   unsigned reg3;
+   unsigned isize;
+-  unsigned int immed = 0, temp;
++  unsigned int immed = 0, immed2 = 0, temp;
+   expressionS exp;
+   char name[20];
+ 
+@@ -1177,6 +1177,87 @@ md_assemble (char * str)
+       inst |= (immed << IMM_LOW) & IMM5_MASK;
+       break;
+ 
++    case INST_TYPE_RD_R1_IMMW_IMMS:
++      if (strcmp (op_end, ""))
++	op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
++      else
++	{
++	  as_fatal (_("Error in statement syntax"));
++	  reg1 = 0;
++	}
++
++      if (strcmp (op_end, ""))
++	op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
++      else
++	{
++	  as_fatal (_("Error in statement syntax"));
++	  reg2 = 0;
++	}
++
++      /* Check for spl registers.  */
++      if (check_spl_reg (&reg1))
++	as_fatal (_("Cannot use special register with this instruction"));
++      if (check_spl_reg (&reg2))
++	as_fatal (_("Cannot use special register with this instruction"));
++
++      /* Width immediate value.  */
++      if (strcmp (op_end, ""))
++	op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
++      else
++	as_fatal (_("Error in statement syntax"));
++
++      if (exp.X_op != O_constant)
++	{
++	  as_warn (_(
++	  "Symbol used as immediate width value for bit field instruction"));
++	  immed = 1;
++	}
++      else
++	immed = exp.X_add_number;
++
++      if (opcode->instr == bsefi && immed > 31)
++	as_fatal (_("Width value must be less than 32"));
++
++      /* Shift immediate value.  */
++      if (strcmp (op_end, ""))
++	op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
++      else
++	as_fatal (_("Error in statement syntax"));
++
++      if (exp.X_op != O_constant)
++	{
++	  as_warn (_(
++	  "Symbol used as immediate shift value for bit field instruction"));
++	  immed2 = 0;
++	}
++      else
++	{
++	  output = frag_more (isize);
++	  immed2 = exp.X_add_number;
++	}
++
++      if (immed2 != (immed2 % 32))
++	{
++	  as_warn (_("Shift value greater than 32. using <value %% 32>"));
++	  immed2 = immed2 % 32;
++	}
++
++      /* Check combined value.  */
++      if (immed + immed2 > 32)
++	as_fatal (_("Width value + shift value must not be greater than 32"));
++
++      inst |= (reg1 << RD_LOW) & RD_MASK;
++      inst |= (reg2 << RA_LOW) & RA_MASK;
++
++      if (opcode->instr == bsefi)
++	inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
++      else
++	inst |= ((immed + immed2 - 1) & IMM5_MASK)
++		<< IMM_WIDTH_LOW; /* bsifi */
++
++      inst |= (immed2 << IMM_LOW) & IMM5_MASK;
++      break;
++
+     case INST_TYPE_R1_R2:
+       if (strcmp (op_end, ""))
+         op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 12981abfea1..468797befc7 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -90,6 +90,21 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
+   return p;
+ }
+ 
++static char *
++get_field_immw (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  if (instr & 0x00004000)
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK)
++				>> IMM_WIDTH_LOW))); /* bsefi */
++  else
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >>
++				IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >>
++				IMM_LOW) + 1)); /* bsifi */
++  return p;
++}
++
+ static char *
+ get_field_rfsl (struct string_buf *buf, long instr)
+ {
+@@ -427,6 +442,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ 	  /* For mbar 16 or sleep insn.  */
+ 	case INST_TYPE_NONE:
+ 	  break;
++	  /* For bit field insns.  */
++	case INST_TYPE_RD_R1_IMMW_IMMS:
++	  print_func (stream, "\t%s, %s, %s, %s",
++		      get_field_rd (&buf, inst),
++		      get_field_r1 (&buf, inst),
++		      get_field_immw (&buf, inst),
++		      get_field_imm5 (&buf, inst));
++	  break;
+ 	  /* For tuqula instruction */
+ 	case INST_TYPE_RD:
+ 	  print_func (stream, "\t%s", get_field_rd (&buf, inst));
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 7398e9e246a..811b5cbeb0f 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -59,6 +59,9 @@
+ /* For mbar.  */
+ #define INST_TYPE_IMM5 20
+ 
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
++
+ #define INST_TYPE_NONE 25
+ 
+ 
+@@ -90,6 +93,7 @@
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+ #define OPCODE_MASK_H3    0xFC000600 /* High 6 bits and bits 21, 22.  */
+ #define OPCODE_MASK_H32   0xFC00FC00 /* High 6 bits and bit 16-21.  */
++#define OPCODE_MASK_H32B  0xFC00C000 /* High 6 bits and bit 16, 17.  */
+ #define OPCODE_MASK_H34B  0xFC0000FF /* High 6 bits and low 8 bits.  */
+ #define OPCODE_MASK_H35B  0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C  0xFC0007E0 /* High 6 bits and bits 21-26.  */
+@@ -102,7 +106,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 289
++#define MAX_OPCODES 291
+ 
+ const struct op_code_struct
+ {
+@@ -159,6 +163,8 @@ const struct op_code_struct
+   {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+   {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+   {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++  {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++  {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -418,7 +424,7 @@ const struct op_code_struct
+   {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
+   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
+   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
+-  {"", 0, 0, 0, 0, 0, 0, 0, 0},
++  {NULL, 0, 0, 0, 0, 0, 0, 0, 0},
+ };
+ 
+ /* Prefix for register names.  */
+@@ -438,5 +444,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5  ((int) 0x00000000)
+ #define MAX_IMM5  ((int) 0x0000001f)
+ 
++#define MIN_IMM_WIDTH  ((int) 0x00000001)
++#define MAX_IMM_WIDTH  ((int) 0x00000020)
++
+ #endif /* MICROBLAZE_OPC */
+ 
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index c91b002d951..3c4f8948c76 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -29,7 +29,7 @@ enum microblaze_instr
+   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+   mulh, mulhu, mulhsu, swapb, swaph,
+   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+-  ncget, ncput, muli, bslli, bsrai, bsrli, mului,
++  ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+@@ -130,6 +130,7 @@ enum microblaze_instr_type
+ #define RB_LOW  11 /* Low bit for RB.  */
+ #define IMM_LOW  0 /* Low bit for immediate.  */
+ #define IMM_MBAR 21 /* low bit for mbar instruction.  */
++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
+ 
+ #define RD_MASK 0x03E00000
+ #define RA_MASK 0x001F0000
+@@ -142,6 +143,9 @@ enum microblaze_instr_type
+ /* Imm mask for mbar.  */
+ #define IMM5_MBAR_MASK 0x03E00000
+ 
++/* Imm mask for extract/insert width. */
++#define IMM5_WIDTH_MASK 0x000007C0
++
+ /* FSL imm mask for get, put instructions.  */
+ #define  RFSL_MASK 0x000000F
+ 
+-- 
+2.39.3
diff --git a/package/binutils-bare-metal/2.41/0007-bfd-microblaze-Add-32_NONE-reloc-type.patch b/package/binutils-bare-metal/2.41/0007-bfd-microblaze-Add-32_NONE-reloc-type.patch
new file mode 100644
index 0000000000..48ea4e0794
--- /dev/null
+++ b/package/binutils-bare-metal/2.41/0007-bfd-microblaze-Add-32_NONE-reloc-type.patch
@@ -0,0 +1,220 @@
+From aea4f3261d558017e9168f85dd200a0fc975e65d Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager@amd.com>
+Date: Mon, 16 Oct 2023 18:27:05 +0100
+Subject: [PATCH v1 1/1] bfd: microblaze: Add 32_NONE reloc type
+
+This patch adds the R_MICROBLAZE_32_NONE relocation type.
+This is a 32-bit reloc that stores the 32-bit pc relative
+value in two words (with an imm instruction).
+
+This patch does not cause any regressions.  Below are the
+testsuite results before and after application of this patch:
+
+./configure --disable-nls --disable-gdb --disable-gdbserver \
+            --disable-gprofng --disable-libbacktrace \
+            --disable-libdecnumber --disable-readline \
+            --disable-sim --enable-obsolete --enable-plugins \
+            --build=powerpc64le-linux --target=microblaze-xilinx-elf
+
+		=== binutils Summary ===
+
+ # of expected passes		220
+ # of expected failures		2
+ # of untested testcases		17
+ # of unsupported tests		14
+
+		=== gas Summary ===
+
+ # of expected passes		272
+ # of unexpected failures	1
+ # of expected failures		1
+ # of unsupported tests		8
+
+		=== ld Summary ===
+
+ # of expected passes		379
+ # of unexpected failures	4
+ # of expected failures		13
+ # of untested testcases		26
+ # of unsupported tests		217
+
+		=== libctf Summary ===
+
+ # of expected passes		5
+ # of unsupported tests		3
+
+		=== libsframe Summary ===
+
+ # of expected passes		57
+
+Signed-off-by: Neal Frager <neal.frager@amd.com>
+---
+ bfd/bfd-in2.h              |  5 +++++
+ bfd/elf32-microblaze.c     | 25 +++++++++++++++++++++++--
+ bfd/libbfd.h               |  1 +
+ bfd/reloc.c                |  6 ++++++
+ binutils/readelf.c         |  4 ++++
+ gas/config/tc-microblaze.c |  3 +++
+ include/elf/microblaze.h   |  1 +
+ 7 files changed, 43 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index c1fe48bb2f1..fb0ead46aba 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -6463,6 +6463,11 @@ value relative to the read-write small data area anchor  */
+ expressions of the form "Symbol Op Symbol"  */
+   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+ 
++/* This is a 32 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction).No relocation is 
++done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_32_NONE,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index a7e81c70fc8..c10278cde31 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -174,6 +174,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 	  0x0000ffff,		/* Dest Mask.  */
+ 	  false),		/* PC relative offset?  */
+ 
++   /* This reloc does nothing.	Used for relaxation.  */
++   HOWTO (R_MICROBLAZE_32_NONE,	/* Type.  */
++	0,			/* Rightshift.  */
++	2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++	32,			/* Bitsize.  */
++	true,			/* PC_relative.  */
++	0,			/* Bitpos.  */
++	complain_overflow_bitfield, /* Complain on overflow.  */
++	NULL,			/* Special Function.  */
++	"R_MICROBLAZE_32_NONE", /* Name.  */
++	false,			/* Partial Inplace.  */
++	0,			/* Source Mask.  */
++	0,			/* Dest Mask.  */
++	false),		/* PC relative offset?  */
++
+    /* This reloc does nothing.	Used for relaxation.  */
+    HOWTO (R_MICROBLAZE_64_NONE,	/* Type.  */
+ 	  0,			/* Rightshift.  */
+@@ -560,6 +575,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_NONE:
+       microblaze_reloc = R_MICROBLAZE_NONE;
+       break;
++    case BFD_RELOC_MICROBLAZE_32_NONE:
++      microblaze_reloc = R_MICROBLAZE_32_NONE;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_NONE:
+       microblaze_reloc = R_MICROBLAZE_64_NONE;
+       break;
+@@ -1954,6 +1972,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ 		}
+ 	      break;
+ 	    case R_MICROBLAZE_NONE:
++	    case R_MICROBLAZE_32_NONE:
+ 	      {
+ 		/* This was a PC-relative instruction that was
+ 		   completely resolved.  */
+@@ -2009,7 +2028,9 @@ microblaze_elf_relax_section (bfd *abfd,
+ 	  irelscanend = irelocs + o->reloc_count;
+ 	  for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ 	    {
+-	      if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
++	      if ((ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) ||
++		  (ELF32_R_TYPE (irelscan->r_info) ==
++		  (int) R_MICROBLAZE_32_NONE))
+ 		{
+ 		  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+@@ -2068,7 +2089,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ 			      elf_section_data (o)->this_hdr.contents = ocontents;
+ 			    }
+ 			}
+-		      irelscan->r_addend -= calc_fixup (irel->r_addend
++		      irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ 							+ isym->st_value,
+ 							0,
+ 							sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index d5f42f22c08..d729dc48e7c 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -3010,6 +3010,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_ROSDA",
+   "BFD_RELOC_MICROBLAZE_32_RWSDA",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++  "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 2ac883d0eac..3ea2afc0d4e 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6694,6 +6694,12 @@ ENUM
+ ENUMDOC
+   This is a 32 bit reloc for the microblaze to handle
+   expressions of the form "Symbol Op Symbol"
++ENUM
++  BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++  This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  No relocation is
++  done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+diff --git a/binutils/readelf.c b/binutils/readelf.c
+index c9b6210e229..17fd7066b83 100644
+--- a/binutils/readelf.c
++++ b/binutils/readelf.c
+@@ -15279,6 +15279,10 @@ is_8bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
+       return reloc_type == 54; /* R_RISCV_SET8.  */
+     case EM_Z80:
+       return reloc_type == 1;  /* R_Z80_8.  */
++    case EM_MICROBLAZE:
++      return reloc_type == 33 /* R_MICROBLAZE_32_NONE.  */
++		|| reloc_type == 0 /* R_MICROBLAZE_NONE.  */
++		|| reloc_type == 9; /* R_MICROBLAZE_64_NONE.  */
+     default:
+       return false;
+     }
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index b510da95024..604cc935da9 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2290,6 +2290,8 @@ md_apply_fix (fixS *   fixP,
+ 	 moves code around due to relaxing.  */
+       if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+ 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++      else if (fixP->fx_r_type == BFD_RELOC_32)
++	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+       else
+ 	fixP->fx_r_type = BFD_RELOC_NONE;
+       fixP->fx_addsy = section_symbol (absolute_section);
+@@ -2513,6 +2515,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+   switch (fixp->fx_r_type)
+     {
+     case BFD_RELOC_NONE:
++    case BFD_RELOC_MICROBLAZE_32_NONE:
+     case BFD_RELOC_MICROBLAZE_64_NONE:
+     case BFD_RELOC_32:
+     case BFD_RELOC_MICROBLAZE_32_LO:
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index fecdd7e4831..164b36d0978 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -61,6 +61,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+   RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30)  /* PC-relative TEXT offset.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
++  RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+ 
+ /* Global base address names.  */
+-- 
+2.25.1
+
diff --git a/package/binutils-bare-metal/Config.in.host b/package/binutils-bare-metal/Config.in.host
new file mode 100644
index 0000000000..e70bee8fa2
--- /dev/null
+++ b/package/binutils-bare-metal/Config.in.host
@@ -0,0 +1,15 @@
+config BR2_PACKAGE_HOST_BINUTILS_BARE_METAL
+	bool "host binutils-bare-metal"
+	help
+	  Build GNU binutils for a bare-metal toolchain
+
+if BR2_PACKAGE_HOST_BINUTILS_BARE_METAL
+
+config BR2_PACKAGE_HOST_BINUTILS_BARE_METAL_VERSION
+	string
+	default "2.41"
+	help
+	  Xilinx zynqmp-firmware and versal-firmware
+	  require binutils-bare-metal version >= 2.41
+
+endif #BR2_PACKAGE_HOST_BINUTILS_BARE_METAL
diff --git a/package/binutils-bare-metal/binutils-bare-metal.hash b/package/binutils-bare-metal/binutils-bare-metal.hash
new file mode 100644
index 0000000000..3aab4d433d
--- /dev/null
+++ b/package/binutils-bare-metal/binutils-bare-metal.hash
@@ -0,0 +1,6 @@
+# From https://gcc.gnu.org/pub/binutils/releases/sha512.sum
+sha512  5df45d0bd6ddabdce4f35878c041e46a92deef01e7dea5facc97fd65cc06b59abc6fba0eb454b68e571c7e14038dc823fe7f2263843e6e627b7444eaf0fe9374  binutils-2.41.tar.xz
+
+# locally calculated
+sha256  8ceb4b9ee5adedde47b31e975c1d90c73ad27b6b165a1dcd80c7c545eb65b903  COPYING3
+sha256  56bdea73b6145ef6ac5259b3da390b981d840c24cb03b8e1cbc678de7ecfa18d  COPYING.LIB
diff --git a/package/binutils-bare-metal/binutils-bare-metal.mk b/package/binutils-bare-metal/binutils-bare-metal.mk
new file mode 100644
index 0000000000..16caf47cb7
--- /dev/null
+++ b/package/binutils-bare-metal/binutils-bare-metal.mk
@@ -0,0 +1,39 @@
+################################################################################
+#
+# binutils-bare-metal
+#
+################################################################################
+
+HOST_BINUTILS_BARE_METAL_VERSION = \
+	$(call qstrip,$(BR2_PACKAGE_HOST_BINUTILS_BARE_METAL_VERSION))
+ifeq ($(HOST_BINUTILS_BARE_METAL_VERSION),)
+HOST_BINUTILS_BARE_METAL_VERSION = 2.41
+endif # BINUTILS_VERSION
+
+HOST_BINUTILS_BARE_METAL_SITE = $(BR2_GNU_MIRROR)/binutils
+HOST_BINUTILS_BARE_METAL_SOURCE = \
+	binutils-$(HOST_BINUTILS_BARE_METAL_VERSION).tar.xz
+
+HOST_BINUTILS_BARE_METAL_LICENSE = GPL-3.0+, libiberty LGPL-2.1+
+HOST_BINUTILS_BARE_METAL_LICENSE_FILES = COPYING3 COPYING.LIB
+HOST_BINUTILS_BARE_METAL_CPE_ID_VENDOR = gnu
+
+HOST_BINUTILS_BARE_METAL_DEPENDENCIES = host-zlib
+
+# Don't build documentation. It takes up extra space / build time,
+# and sometimes needs specific makeinfo versions to work
+HOST_BINUTILS_BARE_METAL_CONF_ENV += MAKEINFO=true
+HOST_BINUTILS_BARE_METAL_MAKE_OPTS += MAKEINFO=true
+HOST_BINUTILS_BARE_METAL_INSTALL_OPTS += MAKEINFO=true install
+
+HOST_BINUTILS_BARE_METAL_CONF_OPTS = \
+	--target=$(BR2_PACKAGE_HOST_TOOLCHAIN_BARE_METAL_ARCH)-elf \
+	--disable-gprof \
+	--disable-shared \
+	--enable-lto \
+	--enable-static \
+	--disable-initfini-array \
+	--disable-multilib \
+	--disable-werror
+
+$(eval $(host-autotools-package))
-- 
2.25.1

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[Buildroot] [PATCH v5 02/10] package/gcc-bare-metal: new package

[Neal Frager via buildroot]

This patch adds a new package for building gcc for a bare-metal toolchain.
The cpu architecture is defined by a toolchain-bare-metal virtual package.
While any cpu architecture could be used, the default configuration will be a
Xilinx microblaze little endian architecture, so that buildroot will be able
to build the microblaze firmware applications for zynqmp and versal.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
---
V1->V2:
 - removed default enable to be replaced with toolchain select config
V2->V3:
 - no changes
V3->V4:
 - split tar instruction into multiple lines
 - replaced unnecessary =? with = for assignments
 - changed xlnx-rel-v2023.1.tar.gz hash to sha256
 - improved menuconfig help comment
V4->V5:
 - moved to upstream gcc without any xilinx patches
 - reduced all lines to <80 chars
 - added license files
---
 DEVELOPERS                                    |  2 +
 ...le-split-stack-for-non-thread-builds.patch |  1 +
 ...ISC-V-fix-build-issue-with-gcc-4.9.x.patch |  1 +
 package/gcc-bare-metal/Config.in.host         | 12 ++++
 package/gcc-bare-metal/gcc-bare-metal.hash    |  9 +++
 package/gcc-bare-metal/gcc-bare-metal.mk      | 68 +++++++++++++++++++
 6 files changed, 93 insertions(+)
 create mode 120000 package/gcc-bare-metal/13.2.0/0001-disable-split-stack-for-non-thread-builds.patch
 create mode 120000 package/gcc-bare-metal/13.2.0/0002-RISC-V-fix-build-issue-with-gcc-4.9.x.patch
 create mode 100644 package/gcc-bare-metal/Config.in.host
 create mode 100644 package/gcc-bare-metal/gcc-bare-metal.hash
 create mode 100644 package/gcc-bare-metal/gcc-bare-metal.mk

diff --git a/DEVELOPERS b/DEVELOPERS
index 9c2b664426..922a74e426 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -1368,6 +1368,7 @@ F:	package/python-rpi-gpio/
 
 N:	Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
 F:	package/binutils-bare-metal/
+F:	package/gcc-bare-metal/
 
 N:	Ignacy Gawędzki <ignacy.gawedzki@green-communications.fr>
 F:	package/angularjs/
@@ -2202,6 +2203,7 @@ F:	configs/zynqmp_zcu102_defconfig
 F:	configs/zynqmp_zcu106_defconfig
 F:	package/binutils-bare-metal/
 F:	package/bootgen/
+F:	package/gcc-bare-metal/
 F:	package/versal-firmware/
 
 N:	Nicola Di Lieto <nicola.dilieto@gmail.com>
diff --git a/package/gcc-bare-metal/13.2.0/0001-disable-split-stack-for-non-thread-builds.patch b/package/gcc-bare-metal/13.2.0/0001-disable-split-stack-for-non-thread-builds.patch
new file mode 120000
index 0000000000..b1eadfb821
--- /dev/null
+++ b/package/gcc-bare-metal/13.2.0/0001-disable-split-stack-for-non-thread-builds.patch
@@ -0,0 +1 @@
+../../gcc/13.2.0/0001-disable-split-stack-for-non-thread-builds.patch
\ No newline at end of file
diff --git a/package/gcc-bare-metal/13.2.0/0002-RISC-V-fix-build-issue-with-gcc-4.9.x.patch b/package/gcc-bare-metal/13.2.0/0002-RISC-V-fix-build-issue-with-gcc-4.9.x.patch
new file mode 120000
index 0000000000..30e3b16e16
--- /dev/null
+++ b/package/gcc-bare-metal/13.2.0/0002-RISC-V-fix-build-issue-with-gcc-4.9.x.patch
@@ -0,0 +1 @@
+../../gcc/13.2.0/0002-RISC-V-fix-build-issue-with-gcc-4.9.x.patch
\ No newline at end of file
diff --git a/package/gcc-bare-metal/Config.in.host b/package/gcc-bare-metal/Config.in.host
new file mode 100644
index 0000000000..ca7735340c
--- /dev/null
+++ b/package/gcc-bare-metal/Config.in.host
@@ -0,0 +1,12 @@
+config BR2_PACKAGE_HOST_GCC_BARE_METAL
+	bool "host gcc-bare-metal"
+	help
+	  Build GCC for a bare-metal toolchain
+
+if BR2_PACKAGE_HOST_GCC_BARE_METAL
+
+config BR2_PACKAGE_HOST_GCC_BARE_METAL_VERSION
+	string
+	default "13.2.0"
+
+endif #BR2_PACKAGE_HOST_GCC_BARE_METAL
diff --git a/package/gcc-bare-metal/gcc-bare-metal.hash b/package/gcc-bare-metal/gcc-bare-metal.hash
new file mode 100644
index 0000000000..5c5c28fa7e
--- /dev/null
+++ b/package/gcc-bare-metal/gcc-bare-metal.hash
@@ -0,0 +1,9 @@
+# From https://gcc.gnu.org/pub/gcc/releases/gcc-13.2.0/sha512.sum
+sha512  d99e4826a70db04504467e349e9fbaedaa5870766cda7c5cab50cdebedc4be755ebca5b789e1232a34a20be1a0b60097de9280efe47bdb71c73251e30b0862a2  gcc-13.2.0.tar.xz
+
+# Locally calculated
+sha256  231f7edcc7352d7734a96eef0b8030f77982678c516876fcb81e25b32d68564c  COPYING
+sha256  8ceb4b9ee5adedde47b31e975c1d90c73ad27b6b165a1dcd80c7c545eb65b903  COPYING3
+sha256  a853c2ffec17057872340eee242ae4d96cbf2b520ae27d903e1b2fef1a5f9d1c  COPYING3.LIB
+sha256  a9bdde5616ecdd1e980b44f360600ee8783b1f99b8cc83a2beb163a0a390e861  COPYING.LIB
+sha256  9d6b43ce4d8de0c878bf16b54d8e7a10d9bd42b75178153e3af6a815bdc90f74  COPYING.RUNTIME
diff --git a/package/gcc-bare-metal/gcc-bare-metal.mk b/package/gcc-bare-metal/gcc-bare-metal.mk
new file mode 100644
index 0000000000..6c783327cd
--- /dev/null
+++ b/package/gcc-bare-metal/gcc-bare-metal.mk
@@ -0,0 +1,68 @@
+################################################################################
+#
+# gcc-bare-metal
+#
+################################################################################
+
+HOST_GCC_BARE_METAL_VERSION = \
+	$(call qstrip,$(BR2_PACKAGE_HOST_GCC_BARE_METAL_VERSION))
+ifeq ($(HOST_GCC_BARE_METAL_VERSION),)
+HOST_GCC_BARE_METAL_VERSION = 13.2.0
+endif
+
+HOST_GCC_BARE_METAL_SITE = \
+	https://ftp.gnu.org/gnu/gcc/gcc-$(HOST_GCC_BARE_METAL_VERSION)
+HOST_GCC_BARE_METAL_SOURCE = gcc-$(HOST_GCC_BARE_METAL_VERSION).tar.xz
+
+HOST_GCC_BARE_METAL_LICENSE = GPL-2.0, GPL-3.0, LGPL-2.1, LGPL-3.0
+HOST_GCC_BARE_METAL_LICENSE_FILES = COPYING COPYING3 COPYING.LIB COPYING3.LIB
+
+HOST_GCC_BARE_METAL_DEPENDENCIES = \
+	host-binutils-bare-metal \
+	host-gmp \
+	host-mpc \
+	host-mpfr \
+	host-isl
+
+# gcc doesn't support in-tree build, so we create a 'build'
+# subdirectory in the gcc sources, and build from there.
+define GCC_BARE_METAL_CONFIGURE_SYMLINK
+	mkdir -p $(@D)/build
+	ln -sf ../configure $(@D)/build/configure
+endef
+
+HOST_GCC_BARE_METAL_PRE_CONFIGURE_HOOKS += GCC_BARE_METAL_CONFIGURE_SYMLINK
+HOST_GCC_BARE_METAL_SUBDIR = build
+
+HOST_GCC_BARE_METAL_MAKE_OPTS = \
+	$(HOST_GCC_COMMON_MAKE_OPTS) \
+	all-gcc \
+	all-target-libgcc
+
+HOST_GCC_BARE_METAL_INSTALL_OPTS = install-gcc install-target-libgcc
+
+GCC_BARE_METAL_ARCH = \
+	$(call qstrip,$(BR2_PACKAGE_HOST_TOOLCHAIN_BARE_METAL_ARCH))
+
+HOST_GCC_BARE_METAL_CONF_OPTS = \
+	--target=$(GCC_BARE_METAL_ARCH)-elf \
+	--disable-initfini_array \
+	--disable-__cxa_atexit \
+	--disable-libstdcxx-pch \
+	--with-newlib \
+	--disable-threads \
+	--enable-plugins \
+	--with-gnu-as \
+	--disable-libitm \
+	--without-long-double-128 \
+	--without-headers \
+	--enable-languages=c \
+	--disable-multilib \
+	--with-gmp=$(HOST_DIR) \
+	--with-mpc=$(HOST_DIR) \
+	--with-mpfr=$(HOST_DIR) \
+	--with-isl=$(HOST_DIR) \
+	AR_FOR_TARGET=$(O)/host/bin/$(GCC_BARE_METAL_ARCH)-elf-ar \
+	RANLIB_FOR_TARGET=$(O)/host/bin/$(GCC_BARE_METAL_ARCH)-elf-ranlib
+
+$(eval $(host-autotools-package))
-- 
2.25.1

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[Buildroot] [PATCH v5 03/10] package/newlib-bare-metal: new package

[Neal Frager via buildroot]

This patch adds a new package for building newlib for a bare-metal toolchain.
The cpu architecture is defined by a toolchain-bare-metal virtual package.
While any cpu architecture could be used, the default configuration will be a
Xilinx microblaze little endian architecture, so that buildroot will be able
to build the microblaze firmware applications for zynqmp and versal.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
---
V1->V2:
 - removed default enable to be replaced with toolchain select config
V2->V3:
 - no changes
V3->V4:
 - replaced unnecessary =? with = for assignments
 - improved menuconfig help comment
V4->V5:
 - added license files
 - reduced all lines to <80 chars
---
 DEVELOPERS                                    |  2 ++
 package/newlib-bare-metal/Config.in.host      | 12 +++++++
 .../newlib-bare-metal/newlib-bare-metal.hash  |  8 +++++
 .../newlib-bare-metal/newlib-bare-metal.mk    | 36 +++++++++++++++++++
 4 files changed, 58 insertions(+)
 create mode 100644 package/newlib-bare-metal/Config.in.host
 create mode 100644 package/newlib-bare-metal/newlib-bare-metal.hash
 create mode 100644 package/newlib-bare-metal/newlib-bare-metal.mk

diff --git a/DEVELOPERS b/DEVELOPERS
index 922a74e426..677b8f09bd 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -1369,6 +1369,7 @@ F:	package/python-rpi-gpio/
 N:	Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
 F:	package/binutils-bare-metal/
 F:	package/gcc-bare-metal/
+F:	package/newlib-bare-metal/
 
 N:	Ignacy Gawędzki <ignacy.gawedzki@green-communications.fr>
 F:	package/angularjs/
@@ -2204,6 +2205,7 @@ F:	configs/zynqmp_zcu106_defconfig
 F:	package/binutils-bare-metal/
 F:	package/bootgen/
 F:	package/gcc-bare-metal/
+F:	package/newlib-bare-metal/
 F:	package/versal-firmware/
 
 N:	Nicola Di Lieto <nicola.dilieto@gmail.com>
diff --git a/package/newlib-bare-metal/Config.in.host b/package/newlib-bare-metal/Config.in.host
new file mode 100644
index 0000000000..be92a1d6a6
--- /dev/null
+++ b/package/newlib-bare-metal/Config.in.host
@@ -0,0 +1,12 @@
+config BR2_PACKAGE_HOST_NEWLIB_BARE_METAL
+	bool "host newlib-bare-metal"
+	help
+	  Build the newlib C library for a bare-metal toolchain
+
+if BR2_PACKAGE_HOST_NEWLIB_BARE_METAL
+
+config BR2_PACKAGE_HOST_NEWLIB_BARE_METAL_VERSION
+	string
+	default "4.1.0"
+
+endif #BR2_PACKAGE_HOST_NEWLIB_BARE_METAL
diff --git a/package/newlib-bare-metal/newlib-bare-metal.hash b/package/newlib-bare-metal/newlib-bare-metal.hash
new file mode 100644
index 0000000000..1a681ecf77
--- /dev/null
+++ b/package/newlib-bare-metal/newlib-bare-metal.hash
@@ -0,0 +1,8 @@
+# Locally calculated
+sha256  f296e372f51324224d387cc116dc37a6bd397198756746f93a2b02e9a5d40154  newlib-4.1.0.tar.gz
+
+# Hashes for license files locally calculated
+sha256  231f7edcc7352d7734a96eef0b8030f77982678c516876fcb81e25b32d68564c  COPYING
+sha256  a9bdde5616ecdd1e980b44f360600ee8783b1f99b8cc83a2beb163a0a390e861  COPYING.LIB
+sha256  f3b7f3e4426b1fa6f60198dae7adfedd94b77b28db2d108adc0253575011e0ff  COPYING.LIBGLOSS
+sha256  422aa40293093fb54fc66e692a0d68fd0b24ed5602e5d1d33ad05ba3909057e9  COPYING.NEWLIB
diff --git a/package/newlib-bare-metal/newlib-bare-metal.mk b/package/newlib-bare-metal/newlib-bare-metal.mk
new file mode 100644
index 0000000000..69e7efb298
--- /dev/null
+++ b/package/newlib-bare-metal/newlib-bare-metal.mk
@@ -0,0 +1,36 @@
+################################################################################
+#
+# newlib-bare-metal
+#
+################################################################################
+
+HOST_NEWLIB_BARE_METAL_VERSION = \
+	$(call qstrip,$(BR2_PACKAGE_HOST_NEWLIB_BARE_METAL_VERSION))
+ifeq ($(HOST_NEWLIB_BARE_METAL_VERSION),)
+HOST_NEWLIB_BARE_METAL_VERSION = 4.1.0
+endif
+
+HOST_NEWLIB_BARE_METAL_SITE = ftp://sourceware.org/pub/newlib
+HOST_NEWLIB_BARE_METAL_SOURCE = newlib-$(HOST_NEWLIB_BARE_METAL_VERSION).tar.gz
+HOST_NEWLIB_BARE_METAL_DEPENDENCIES = host-gcc-bare-metal
+
+HOST_NEWLIB_BARE_METAL_LICENSE = GPL-2.0, GPL-3.0, LGPL-2.1, LGPL-3.0
+HOST_NEWLIB_BARE_METAL_LICENSE_FILES = COPYING \
+	COPYING.LIB \
+	COPYING.LIBGLOSS \
+	COPYING.NEWLIB
+
+NEWLIB_ARCH = $(call qstrip,$(BR2_PACKAGE_HOST_TOOLCHAIN_BARE_METAL_ARCH))
+
+HOST_NEWLIB_BARE_METAL_CONF_OPTS = \
+	--target=$(NEWLIB_ARCH)-elf \
+	CC_FOR_TARGET=$(HOST_DIR)/bin/$(NEWLIB_ARCH)-elf-gcc \
+	AR_FOR_TARGET=$(HOST_DIR)/bin/$(NEWLIB_ARCH)-elf-ar \
+	RANLIB_FOR_TARGET=$(HOST_DIR)/bin/$(NEWLIB_ARCH)-elf-ranlib \
+	--enable-newlib-io-c99-formats \
+	--enable-newlib-io-long-long \
+	--enable-newlib-io-float \
+	--enable-newlib-io-long-double \
+	--disable-multilib
+
+$(eval $(host-autotools-package))
-- 
2.25.1

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[Buildroot] [PATCH v5 04/10] toolchain/toolchain-bare-metal: new toolchain

[Neal Frager via buildroot]

This patch adds a new virtual package for adding a bare-metal toolchain to
buildroot.  By default, this package will configure a bare-metal toolchain
for the Xilinx microblaze little endian architecture.  When configured for
the Xilinx microblaze architecture, this toolchain can be used to build the
microblaze firmware applications for zynqmp and versal.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
---
V1->V2:
 - adds select option to bring in all packages needed for toolchain-bare-metal
V2->V3:
 - no changes
V3->V4:
 - moved from package to toolchain directory
 - improved menuconfig help comment
V4->V5:
 - no changes
---
 DEVELOPERS                                    |  2 ++
 toolchain/Config.in                           |  1 +
 toolchain/toolchain-bare-metal/Config.in      | 21 +++++++++++++++++++
 .../toolchain-bare-metal.mk                   |  7 +++++++
 4 files changed, 31 insertions(+)
 create mode 100644 toolchain/toolchain-bare-metal/Config.in
 create mode 100644 toolchain/toolchain-bare-metal/toolchain-bare-metal.mk

diff --git a/DEVELOPERS b/DEVELOPERS
index 677b8f09bd..7149c65b4e 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -1370,6 +1370,7 @@ N:	Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
 F:	package/binutils-bare-metal/
 F:	package/gcc-bare-metal/
 F:	package/newlib-bare-metal/
+F:	toolchain/toolchain-bare-metal/
 
 N:	Ignacy Gawędzki <ignacy.gawedzki@green-communications.fr>
 F:	package/angularjs/
@@ -2207,6 +2208,7 @@ F:	package/bootgen/
 F:	package/gcc-bare-metal/
 F:	package/newlib-bare-metal/
 F:	package/versal-firmware/
+F:	toolchain/toolchain-bare-metal/
 
 N:	Nicola Di Lieto <nicola.dilieto@gmail.com>
 F:	package/uacme/
diff --git a/toolchain/Config.in b/toolchain/Config.in
index d8081f1b9d..ed0d6333f9 100644
--- a/toolchain/Config.in
+++ b/toolchain/Config.in
@@ -59,6 +59,7 @@ config BR2_TOOLCHAIN_EXTERNAL
 
 endchoice
 
+source "toolchain/toolchain-bare-metal/Config.in"
 source "toolchain/toolchain-buildroot/Config.in"
 source "toolchain/toolchain-external/Config.in"
 
diff --git a/toolchain/toolchain-bare-metal/Config.in b/toolchain/toolchain-bare-metal/Config.in
new file mode 100644
index 0000000000..ddd6d3c253
--- /dev/null
+++ b/toolchain/toolchain-bare-metal/Config.in
@@ -0,0 +1,21 @@
+config BR2_PACKAGE_HOST_TOOLCHAIN_BARE_METAL
+	bool "host toolchain-bare-metal"
+	select BR2_PACKAGE_HOST_BINUTILS_BARE_METAL
+	select BR2_PACKAGE_HOST_GCC_BARE_METAL
+	select BR2_PACKAGE_HOST_NEWLIB_BARE_METAL
+	help
+	  Build a bare-metal toolchain in addition to the main Linux toolchain
+
+if BR2_PACKAGE_HOST_TOOLCHAIN_BARE_METAL
+
+config BR2_PACKAGE_HOST_TOOLCHAIN_BARE_METAL_ARCH
+	string
+	default "microblazeel-xilinx"
+	help
+	  select architecture for bare-metal toolchain
+
+source "package/binutils-bare-metal/Config.in.host"
+source "package/gcc-bare-metal/Config.in.host"
+source "package/newlib-bare-metal/Config.in.host"
+
+endif #BR2_PACKAGE_HOST_TOOLCHAIN_BARE_METAL
diff --git a/toolchain/toolchain-bare-metal/toolchain-bare-metal.mk b/toolchain/toolchain-bare-metal/toolchain-bare-metal.mk
new file mode 100644
index 0000000000..407ad4ea33
--- /dev/null
+++ b/toolchain/toolchain-bare-metal/toolchain-bare-metal.mk
@@ -0,0 +1,7 @@
+################################################################################
+#
+# toolchain-bare-metal
+#
+################################################################################
+
+(eval $(host-virtual-package))
-- 
2.25.1

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[Buildroot] [PATCH v5 05/10] boot/zynqmp-firmware: new boot firmware

[Neal Frager via buildroot]

This patch adds a new boot firmware to buildroot for building the zynqmp pmufw.
It requires the toolchain-bare-metal package that includes a bare-metal
binutils, gcc and newlib which can be built for the microblaze architecture.

A patch is required to enable parallel building of the pmufw.  This patch has
been submitted upstream internally at AMD / Xilinx and will be included with
the 2023.2 release of the embeddedsw repository.

Signed-off-by: Neal Frager <neal.frager@amd.com>
---
V1->V2:
 - builds a bare-metal gcc toolchain instead of requiring an external
   microblaze toolchain
V2->V3:
 - corrected custom cflags option
 - added support for xilinx_v2022.2 version
 - added zynqmp-firmware.hash
V3->V4:
 - no changes
V4->V5:
 - reduced all lines to <80 chars
---
 DEVELOPERS                                    |   1 +
 boot/Config.in                                |   1 +
 boot/zynqmp-firmware/Config.in                |  22 ++++
 ...akefile-specify-sequential-Makefiles.patch |   1 +
 ...akefile-specify-sequential-Makefiles.patch | 115 ++++++++++++++++++
 boot/zynqmp-firmware/zynqmp-firmware.hash     |   3 +
 boot/zynqmp-firmware/zynqmp-firmware.mk       |  33 +++++
 7 files changed, 176 insertions(+)
 create mode 100644 boot/zynqmp-firmware/Config.in
 create mode 120000 boot/zynqmp-firmware/xilinx_v2022.2/0001-pmufw-misc-Makefile-specify-sequential-Makefiles.patch
 create mode 100644 boot/zynqmp-firmware/xilinx_v2023.1/0001-pmufw-misc-Makefile-specify-sequential-Makefiles.patch
 create mode 100644 boot/zynqmp-firmware/zynqmp-firmware.hash
 create mode 100644 boot/zynqmp-firmware/zynqmp-firmware.mk

diff --git a/DEVELOPERS b/DEVELOPERS
index 7149c65b4e..c8e8038d44 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -2198,6 +2198,7 @@ N:	Neal Frager <neal.frager@amd.com>
 F:	board/versal/
 F:	board/zynq/
 F:	board/zynqmp/
+F:	boot/zynqmp-firmware/
 F:	configs/versal_vck190_defconfig
 F:	configs/zynq_zc706_defconfig
 F:	configs/zynqmp_kria_kv260_defconfig
diff --git a/boot/Config.in b/boot/Config.in
index e5fdf7ad43..c7478fef2e 100644
--- a/boot/Config.in
+++ b/boot/Config.in
@@ -24,5 +24,6 @@ source "boot/ti-k3-image-gen/Config.in"
 source "boot/ti-k3-r5-loader/Config.in"
 source "boot/uboot/Config.in"
 source "boot/vexpress-firmware/Config.in"
+source "boot/zynqmp-firmware/Config.in"
 
 endmenu
diff --git a/boot/zynqmp-firmware/Config.in b/boot/zynqmp-firmware/Config.in
new file mode 100644
index 0000000000..480400a789
--- /dev/null
+++ b/boot/zynqmp-firmware/Config.in
@@ -0,0 +1,22 @@
+config BR2_TARGET_ZYNQMP_FIRMWARE
+	bool "zynqmp-firmware"
+	select BR2_PACKAGE_HOST_TOOLCHAIN_BARE_METAL
+	help
+	  This package builds the PMU Firmware application required
+	  to run U-Boot and Linux in the Zynq MPSoC devices.
+
+if BR2_TARGET_ZYNQMP_FIRMWARE
+
+config BR2_TARGET_ZYNQMP_FIRMWARE_VERSION
+	string "firmware version"
+	default "xilinx_v2023.1"
+	help
+	  Release version of zynqmp firmware.
+	  Only versions xilinx_v2022.2 and newer are supported.
+
+config BR2_TARGET_ZYNQMP_FIRMWARE_CUSTOM_CFLAGS
+	string "custom cflags"
+	help
+	  Adds additional CFLAGS for building zynqmp firmware.
+
+endif # BR2_TARGET_ZYNQMP_FIRMWARE
diff --git a/boot/zynqmp-firmware/xilinx_v2022.2/0001-pmufw-misc-Makefile-specify-sequential-Makefiles.patch b/boot/zynqmp-firmware/xilinx_v2022.2/0001-pmufw-misc-Makefile-specify-sequential-Makefiles.patch
new file mode 120000
index 0000000000..51cb8a6ae0
--- /dev/null
+++ b/boot/zynqmp-firmware/xilinx_v2022.2/0001-pmufw-misc-Makefile-specify-sequential-Makefiles.patch
@@ -0,0 +1 @@
+../xilinx_v2023.1/0001-pmufw-misc-Makefile-specify-sequential-Makefiles.patch
\ No newline at end of file
diff --git a/boot/zynqmp-firmware/xilinx_v2023.1/0001-pmufw-misc-Makefile-specify-sequential-Makefiles.patch b/boot/zynqmp-firmware/xilinx_v2023.1/0001-pmufw-misc-Makefile-specify-sequential-Makefiles.patch
new file mode 100644
index 0000000000..29c652d6ef
--- /dev/null
+++ b/boot/zynqmp-firmware/xilinx_v2023.1/0001-pmufw-misc-Makefile-specify-sequential-Makefiles.patch
@@ -0,0 +1,115 @@
+From 23002defd462845db376425a7b7d975f3deba83d Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager@amd.com>
+Date: Mon, 24 Apr 2023 12:53:25 +0100
+Subject: [PATCH v1 1/1] pmufw: misc/Makefile: specify sequential Makefiles
+
+The BSP_SEQUENTIAL_MAKEFILES variable is not properly assigned and exported
+from copy_bsp.sh.
+
+Because of this, no library is built sequentially even if it was desired to
+build them sequentially by assigning to BSP_SEQUENTIAL_MAKEFILES. All the
+libraries are built in parallel.
+
+This patch resolves this issue, so that libraries that must be built
+sequentially are indeed built sequentially.
+
+Signed-off-by: Neal Frager <neal.frager@amd.com>
+---
+ lib/sw_apps/zynqmp_pmufw/misc/Makefile    | 10 +++++++++-
+ lib/sw_apps/zynqmp_pmufw/misc/copy_bsp.sh |  7 -------
+ lib/sw_apps/zynqmp_pmufw/src/Makefile     |  2 ++
+ 3 files changed, 11 insertions(+), 8 deletions(-)
+
+diff --git a/lib/sw_apps/zynqmp_pmufw/misc/Makefile b/lib/sw_apps/zynqmp_pmufw/misc/Makefile
+index a773498512..fe2d23c965 100644
+--- a/lib/sw_apps/zynqmp_pmufw/misc/Makefile
++++ b/lib/sw_apps/zynqmp_pmufw/misc/Makefile
+@@ -7,6 +7,14 @@ PROCESSOR = psu_pmu_0
+ LIBRARIES = ${PROCESSOR}/lib/libxil.a
+ BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
+ SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
++DRIVERS_LIST=../drivers.txt
++SEQUENTIAL_MAKEFILES := $(shell cat ${DRIVERS_LIST})
++BSP_SEQUENTIAL_MAKEFILES = $(patsubst %, ${PROCESSOR}/libsrc/%/src/Makefile, $(SEQUENTIAL_MAKEFILES))
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/xilskey/src/Makefile
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/xilfpga/src/Makefile
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/xilsecure/src/Makefile
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/dppsu/src/Makefile
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/dpdma/src/Makefile
+ BSP_PARALLEL_MAKEFILES := $(filter-out $(BSP_SEQUENTIAL_MAKEFILES),$(BSP_MAKEFILES))
+ SEQ_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_SEQUENTIAL_MAKEFILES))
+ PAR_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_PARALLEL_MAKEFILES))
+@@ -16,7 +24,7 @@ ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ endif
+ 
+ all:
+-	$(MAKE) --no-print-directory seq_libs
++	$(MAKE) -j1 --no-print-directory seq_libs
+ 	$(MAKE) -j --no-print-directory par_libs
+ 	$(MAKE) --no-print-directory archive
+ 	@echo 'Finished building libraries'
+diff --git a/lib/sw_apps/zynqmp_pmufw/misc/copy_bsp.sh b/lib/sw_apps/zynqmp_pmufw/misc/copy_bsp.sh
+index 197f7af844..ac8dd8249e 100755
+--- a/lib/sw_apps/zynqmp_pmufw/misc/copy_bsp.sh
++++ b/lib/sw_apps/zynqmp_pmufw/misc/copy_bsp.sh
+@@ -29,8 +29,6 @@ STANDALONE_DIR=$EMBEDDED_SW_DIR/lib/bsp/standalone/src
+ # libraries dir
+ SERVICES_DIR=$EMBEDDED_SW_DIR/lib/sw_services
+ 
+-BSP_SEQUENTIAL_MAKEFILES=
+-
+ # creation of BSP folders required
+ if [ -d $BSP_DIR ]; then
+ 	echo "BSP directory already exists"
+@@ -55,14 +53,12 @@ cp -r $SERVICES_DIR/xilfpga/src/interface/zynqmp/xilfpga_pcap.c $BSP_DIR/libsrc/
+ cp -r $SERVICES_DIR/xilfpga/src/*.h $BSP_DIR/include/
+ cp -r $SERVICES_DIR/xilfpga/src/interface/zynqmp/*.h $BSP_DIR/include/
+ rm -r $BSP_DIR/libsrc/xilfpga/src/interface/
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilfpga/src/Makefile"
+ mkdir -p $BSP_DIR/libsrc/xilsecure/src/
+ cp -r $SERVICES_DIR/xilsecure/src/Makefile $BSP_DIR/libsrc/xilsecure/src/
+ cp -r $SERVICES_DIR/xilsecure/src/common/all/* $BSP_DIR/libsrc/xilsecure/src/
+ cp -r $SERVICES_DIR/xilsecure/src/zynqmp/* $BSP_DIR/libsrc/xilsecure/src/
+ cp -r $SERVICES_DIR/xilsecure/src/common/all/*.h $BSP_DIR/include/
+ cp -r $SERVICES_DIR/xilsecure/src/zynqmp/*.h $BSP_DIR/include/
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilsecure/src/Makefile"
+ cp -r $SERVICES_DIR/xilskey/ $BSP_DIR/libsrc/
+ 
+ # remove the xilskey library files which are not required for PMU
+@@ -84,7 +80,6 @@ rm -r $BSP_DIR/libsrc/xilskey/src/include/xilskey_bbram.h
+ # copy the xilskey library header files to include directory
+ cp -r $BSP_DIR/libsrc/xilskey/src/*.h $BSP_DIR/include/
+ cp -r $BSP_DIR/libsrc/xilskey/src/include/*.h $BSP_DIR/include/
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilskey/src/Makefile"
+ 
+ # copy bsp standalone code
+ cp -r $STANDALONE_DIR/common/*  $BSP_DIR/libsrc/standalone/src/
+@@ -113,7 +108,6 @@ do
+ 	if [ $line != "avbuf" ] && [ $line != "video_common" ]; then
+ 		cp $WORKING_DIR/x"$line"_g.c $BSP_DIR/libsrc/$line/src/
+ 	fi
+-	BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/$line/src/Makefile"
+ 
+ done < $DRIVERS_LIST
+ 
+@@ -136,4 +130,3 @@ cp $STANDALONE_DIR/profile/*.h  $BSP_DIR/include/
+ 
+ # no inbyte and outbyte present in standalone
+ cp $WORKING_DIR/inbyte.c $WORKING_DIR/outbyte.c  $BSP_DIR/libsrc/standalone/src/
+-export BSP_SEQUENTIAL_MAKEFILES
+diff --git a/lib/sw_apps/zynqmp_pmufw/src/Makefile b/lib/sw_apps/zynqmp_pmufw/src/Makefile
+index 1750c0a329..8747db5cdf 100644
+--- a/lib/sw_apps/zynqmp_pmufw/src/Makefile
++++ b/lib/sw_apps/zynqmp_pmufw/src/Makefile
+@@ -27,6 +27,8 @@ all: $(EXEC)
+ $(EXEC): $(LIBS) $(OBJS) $(INCLUDES)
+ 	$(CC) -o $@ $(OBJS) $(CC_FLAGS) $(CFLAGS) $(LN_FLAGS) $(LIBPATH) $(LSCRIPT)
+ 
++$(OBJS): $(LIBS)
++
+ $(LIBS):
+ 	echo "Copying BSP files"
+ 	../misc/copy_bsp.sh
+-- 
+2.17.1
+
diff --git a/boot/zynqmp-firmware/zynqmp-firmware.hash b/boot/zynqmp-firmware/zynqmp-firmware.hash
new file mode 100644
index 0000000000..ee2d656110
--- /dev/null
+++ b/boot/zynqmp-firmware/zynqmp-firmware.hash
@@ -0,0 +1,3 @@
+# locally computed
+sha256  fc0e86027bdba53f5df373bcb38a171d61704db4ff1b4671f3886a87ceec7068  zynqmp-firmware-xilinx_v2022.2.tar.gz
+sha256  9850f893113936b9959cc76cc3e9152e30f815ff1acaa4b45f7a60fe3e1836f0  zynqmp-firmware-xilinx_v2023.1.tar.gz
diff --git a/boot/zynqmp-firmware/zynqmp-firmware.mk b/boot/zynqmp-firmware/zynqmp-firmware.mk
new file mode 100644
index 0000000000..be49cb197d
--- /dev/null
+++ b/boot/zynqmp-firmware/zynqmp-firmware.mk
@@ -0,0 +1,33 @@
+################################################################################
+#
+# zynqmp-firmware
+#
+################################################################################
+
+ZYNQMP_FIRMWARE_VERSION = $(call qstrip,$(BR2_TARGET_ZYNQMP_FIRMWARE_VERSION))
+ZYNQMP_FIRMWARE_SITE = \
+	$(call github,Xilinx,embeddedsw,$(ZYNQMP_FIRMWARE_VERSION))
+ZYNQMP_FIRMWARE_LICENSE = MIT
+ZYNQMP_FIRMWARE_LICENSE_FILES = license.txt
+ZYNQMP_FIRMWARE_INSTALL_IMAGES = YES
+ZYNQMP_FIRMWARE_INSTALL_TARGET = NO
+ZYNQMP_FIRMWARE_DEPENDENCIES = host-newlib-bare-metal
+
+CUSTOM_CFLAGS = $(call qstrip,$(BR2_TARGET_ZYNQMP_FIRMWARE_CUSTOM_CFLAGS))
+ZYNQMP_CFLAGS = "-Os -flto -ffat-lto-objects $(CUSTOM_CFLAGS)"
+
+define ZYNQMP_FIRMWARE_BUILD_CMDS
+	$(MAKE) -C $(@D)/lib/sw_apps/zynqmp_pmufw/src \
+		COMPILER=$(HOST_DIR)/bin/microblazeel-xilinx-elf-gcc \
+		ARCHIVER=$(HOST_DIR)/bin/microblazeel-xilinx-elf-gcc-ar \
+		CC=$(HOST_DIR)/bin/microblazeel-xilinx-elf-gcc \
+		CFLAGS=$(ZYNQMP_CFLAGS)
+endef
+
+PMUFW_PATH = $(@D)/lib/sw_apps/zynqmp_pmufw/src/executable.elf
+
+define ZYNQMP_FIRMWARE_INSTALL_IMAGES_CMDS
+	$(INSTALL) -D -m 0755 $(PMUFW_PATH) $(BINARIES_DIR)/pmufw.elf
+endef
+
+$(eval $(generic-package))
-- 
2.25.1

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[Buildroot] [PATCH v5 06/10] boot/uboot.mk: new zynqmp pmufw build option

[Neal Frager via buildroot]

The new BR2_TARGET_UBOOT_ZYNQMP_PMUFW_SOURCE option will enable u-boot to
use the zynqmp-firmware package for building a pmufw.elf that gets included in
the generated boot.bin.

If the BR2_TARGET_UBOOT_ZYNQMP_PMUFW_SOURCE option is enabled, then the
BR2_TARGET_UBOOT_ZYNQMP_PMUFW config for downloading a prebuilt pmufw will
be ignored.

Signed-off-by: Neal Frager <neal.frager@amd.com>
---
V1->V2:
 - patch is now backwards compatible for users already using the
   BR2_TARGET_UBOOT_ZYNQMP_PMUFW config for downloading a prebuilt pmufw
V2->V3:
 - no changes
V3->V4:
 - BR2_TARGET_UBOOT_ZYNQMP_PMUFW removed when
   BR2_TARGET_UBOOT_ZYNQMP_PMUFW_SOURCE selected
V4->V5:
 - no changes
---
 boot/uboot/Config.in | 19 +++++++++++++++++--
 boot/uboot/uboot.mk  |  5 +++++
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/boot/uboot/Config.in b/boot/uboot/Config.in
index 21f19db890..ef9e811764 100644
--- a/boot/uboot/Config.in
+++ b/boot/uboot/Config.in
@@ -514,11 +514,26 @@ config BR2_TARGET_UBOOT_ZYNQMP
 
 if BR2_TARGET_UBOOT_ZYNQMP
 
+config BR2_TARGET_UBOOT_ZYNQMP_PMUFW_SOURCE
+	bool "Build zynqmp PMU firmware from source"
+	select BR2_TARGET_ZYNQMP_FIRMWARE
+	depends on BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG
+	help
+	  This option instructs u-boot to build the zynqmp pmufw using
+	  the zynqmp-firmware package.  u-boot will then include this
+	  pmufw.elf in the generated boot.bin.
+	  
+	  If this option is selected, the BR2_TARGET_UBOOT_ZYNQMP_PMUFW
+	  prebuilt option will be ignored.
+
+	  This feature requires U-Boot >= 2018.07.
+
 config BR2_TARGET_UBOOT_ZYNQMP_PMUFW
-	string "PMU firmware location"
+	string "Pre-built zynqmp PMU firmware location"
 	depends on BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG
+	depends on !BR2_TARGET_UBOOT_ZYNQMP_PMUFW_SOURCE
 	help
-	  Location of a PMU firmware binary.
+	  Location of a pre-built PMU firmware binary.
 
 	  If not empty, instructs the U-Boot build process to generate
 	  a boot.bin (to be loaded by the ZynqMP boot ROM) containing
diff --git a/boot/uboot/uboot.mk b/boot/uboot/uboot.mk
index dda606a880..c11e3d89f7 100644
--- a/boot/uboot/uboot.mk
+++ b/boot/uboot/uboot.mk
@@ -416,7 +416,12 @@ endef
 
 ifeq ($(BR2_TARGET_UBOOT_ZYNQMP),y)
 
+ifeq ($(BR2_TARGET_UBOOT_ZYNQMP_PMUFW_SOURCE),y)
+UBOOT_DEPENDENCIES += zynqmp-firmware
+UBOOT_ZYNQMP_PMUFW = $(BINARIES_DIR)/pmufw.elf
+else
 UBOOT_ZYNQMP_PMUFW = $(call qstrip,$(BR2_TARGET_UBOOT_ZYNQMP_PMUFW))
+endif #BR2_TARGET_UBOOT_ZYNQMP_PMUFW_SOURCE
 
 ifneq ($(findstring ://,$(UBOOT_ZYNQMP_PMUFW)),)
 UBOOT_EXTRA_DOWNLOADS += $(UBOOT_ZYNQMP_PMUFW)
-- 
2.25.1

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[Buildroot] [PATCH v5 07/10] configs/zynqmp*: build pmufw source

[Neal Frager via buildroot]

This patch migrates the zynqmp config files to use the new
zynqmp-firmware package for building the zynqmp pmufw from source.

Signed-off-by: Neal Frager <neal.frager@amd.com>
---
V4->V5:
 - no changes
---
 configs/zynqmp_kria_kv260_defconfig | 4 +++-
 configs/zynqmp_zcu102_defconfig     | 3 ++-
 configs/zynqmp_zcu106_defconfig     | 3 ++-
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/configs/zynqmp_kria_kv260_defconfig b/configs/zynqmp_kria_kv260_defconfig
index 78b62a9ff8..5e0c820ba7 100644
--- a/configs/zynqmp_kria_kv260_defconfig
+++ b/configs/zynqmp_kria_kv260_defconfig
@@ -32,7 +32,9 @@ BR2_TARGET_UBOOT_NEEDS_GNUTLS=y
 BR2_TARGET_UBOOT_SPL=y
 BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
 BR2_TARGET_UBOOT_ZYNQMP=y
-BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/soc-prebuilt-firmware/raw/xilinx_v2023.1/kv260-kria/pmufw.elf"
+BR2_TARGET_UBOOT_ZYNQMP_PMUFW_SOURCE=y
+BR2_TARGET_ZYNQMP_FIRMWARE_VERSION="xilinx_v2023.1"
+BR2_TARGET_ZYNQMP_FIRMWARE_CUSTOM_CFLAGS="-DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 -DENABLE_EM -DENABLE_MOD_OVERTEMP -DENABLE_DYNAMIC_MIO_CONFIG -DENABLE_IOCTL -DCONNECT_PMU_GPO_2_VAL=0"
 BR2_TARGET_UBOOT_ZYNQMP_PM_CFG="board/zynqmp/kria/kv260/pm_cfg_obj.c"
 BR2_TARGET_UBOOT_FORMAT_ITB=y
 BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y
diff --git a/configs/zynqmp_zcu102_defconfig b/configs/zynqmp_zcu102_defconfig
index 18230cf89b..6674fc6dfb 100644
--- a/configs/zynqmp_zcu102_defconfig
+++ b/configs/zynqmp_zcu102_defconfig
@@ -30,7 +30,8 @@ BR2_TARGET_UBOOT_NEEDS_GNUTLS=y
 BR2_TARGET_UBOOT_SPL=y
 BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
 BR2_TARGET_UBOOT_ZYNQMP=y
-BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/soc-prebuilt-firmware/raw/xilinx_v2023.1/zcu102-zynqmp/pmufw.elf"
+BR2_TARGET_UBOOT_ZYNQMP_PMUFW_SOURCE=y
+BR2_TARGET_ZYNQMP_FIRMWARE_VERSION="xilinx_v2023.1"
 BR2_TARGET_UBOOT_ZYNQMP_PM_CFG="board/zynqmp/zcu102/pm_cfg_obj.c"
 BR2_TARGET_UBOOT_FORMAT_ITB=y
 BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y
diff --git a/configs/zynqmp_zcu106_defconfig b/configs/zynqmp_zcu106_defconfig
index 21f41a2d8f..201d3daeda 100644
--- a/configs/zynqmp_zcu106_defconfig
+++ b/configs/zynqmp_zcu106_defconfig
@@ -30,7 +30,8 @@ BR2_TARGET_UBOOT_NEEDS_GNUTLS=y
 BR2_TARGET_UBOOT_SPL=y
 BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
 BR2_TARGET_UBOOT_ZYNQMP=y
-BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/soc-prebuilt-firmware/raw/xilinx_v2023.1/zcu106-zynqmp/pmufw.elf"
+BR2_TARGET_UBOOT_ZYNQMP_PMUFW_SOURCE=y
+BR2_TARGET_ZYNQMP_FIRMWARE_VERSION="xilinx_v2023.1"
 BR2_TARGET_UBOOT_ZYNQMP_PM_CFG="board/zynqmp/zcu106/pm_cfg_obj.c"
 BR2_TARGET_UBOOT_FORMAT_ITB=y
 BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y
-- 
2.25.1

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[Buildroot] [PATCH v5 08/10] boot/versal-firmware: new boot firmware

[Neal Frager via buildroot]

This patch adds a new boot firmware to buildroot for building the versal plm
and psmfw.  It requires the toolchain-bare-metal package that includes a
bare-metal binutils, gcc and newlib which can be built for the microblaze
architecture.

Patches are required to enable parallel building of the versal plm and psmfw
applications.  These two patches have been submitted upstream internally at
AMD / Xilinx and will be included with the 2023.2 release of the embeddedsw
repository.

Signed-off-by: Neal Frager <neal.frager@amd.com>
---
V4->V5:
 - automatically select bootgen as a needed tool
 - reduce all lines to <80 chars
 - add help for PDI file location which could be URL or local
---
 DEVELOPERS                                    |   1 +
 boot/Config.in                                |   1 +
 boot/versal-firmware/Config.in                |  38 +++++
 boot/versal-firmware/versal-firmware.hash     |   2 +
 boot/versal-firmware/versal-firmware.mk       |  52 ++++++
 ...al_plm-add-support-of-parallel-build.patch | 157 ++++++++++++++++++
 ..._psmfw-add-support-of-parallel-build.patch |  48 ++++++
 7 files changed, 299 insertions(+)
 create mode 100644 boot/versal-firmware/Config.in
 create mode 100644 boot/versal-firmware/versal-firmware.hash
 create mode 100644 boot/versal-firmware/versal-firmware.mk
 create mode 100644 boot/versal-firmware/xilinx_v2023.1/0001-sw_apps-versal_plm-add-support-of-parallel-build.patch
 create mode 100644 boot/versal-firmware/xilinx_v2023.1/0002-sw_apps-versal_psmfw-add-support-of-parallel-build.patch

diff --git a/DEVELOPERS b/DEVELOPERS
index c8e8038d44..9f9e36c674 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -2198,6 +2198,7 @@ N:	Neal Frager <neal.frager@amd.com>
 F:	board/versal/
 F:	board/zynq/
 F:	board/zynqmp/
+F:	boot/versal-firmware/
 F:	boot/zynqmp-firmware/
 F:	configs/versal_vck190_defconfig
 F:	configs/zynq_zc706_defconfig
diff --git a/boot/Config.in b/boot/Config.in
index c7478fef2e..da5ccb6b9c 100644
--- a/boot/Config.in
+++ b/boot/Config.in
@@ -23,6 +23,7 @@ source "boot/ti-k3-boot-firmware/Config.in"
 source "boot/ti-k3-image-gen/Config.in"
 source "boot/ti-k3-r5-loader/Config.in"
 source "boot/uboot/Config.in"
+source "boot/versal-firmware/Config.in"
 source "boot/vexpress-firmware/Config.in"
 source "boot/zynqmp-firmware/Config.in"
 
diff --git a/boot/versal-firmware/Config.in b/boot/versal-firmware/Config.in
new file mode 100644
index 0000000000..8714c51788
--- /dev/null
+++ b/boot/versal-firmware/Config.in
@@ -0,0 +1,38 @@
+config BR2_TARGET_VERSAL_FIRMWARE
+	bool "versal-firmware"
+	select BR2_PACKAGE_HOST_TOOLCHAIN_BARE_METAL
+	select BR2_PACKAGE_HOST_BOOTGEN
+	help
+	  This package builds the boot firmware apps for Xilinx versal
+	  boards, so that they can boot u-boot and Linux.
+
+if BR2_TARGET_VERSAL_FIRMWARE
+
+config BR2_TARGET_VERSAL_FIRMWARE_VERSION
+	string "firmware version"
+	default "xilinx_v2023.1"
+	help
+	  Release version of versal firmware.
+	  Only versions xilinx_v2023.1 and newer are supported.
+	  
+config BR2_TARGET_VERSAL_FIRMWARE_CUSTOM_CFLAGS
+	string "custom cflags"
+	help
+	  Adds additional CFLAGS for building versal firmware.
+
+config BR2_TARGET_VERSAL_FIRMWARE_PDI
+	string "pdi file location"
+	default "https://github.com/Xilinx/soc-prebuilt-firmware/raw/xilinx_v2023.1/vck190-versal/vpl_gen_fixed.pdi"
+	help
+	  The PDI file defines everything which is board specific for versal.
+	  It gets parsed by the plm.elf during boot.  To boot a custom target
+	  based on versal, this should be configured to point to your Vivado
+	  generated PDI file.
+	  
+	  The location of the PDI can be either a URL for download or a file
+	  in the local repository.
+	  
+	  This config should never be undefined, so default configuration is
+	  for the vck190 evaluation board.
+
+endif # BR2_TARGET_VERSAL_FIRMWARE
diff --git a/boot/versal-firmware/versal-firmware.hash b/boot/versal-firmware/versal-firmware.hash
new file mode 100644
index 0000000000..3a03f9c3ff
--- /dev/null
+++ b/boot/versal-firmware/versal-firmware.hash
@@ -0,0 +1,2 @@
+# locally computed
+sha256  9850f893113936b9959cc76cc3e9152e30f815ff1acaa4b45f7a60fe3e1836f0  versal-firmware-xilinx_v2023.1.tar.gz
diff --git a/boot/versal-firmware/versal-firmware.mk b/boot/versal-firmware/versal-firmware.mk
new file mode 100644
index 0000000000..6d49a52d37
--- /dev/null
+++ b/boot/versal-firmware/versal-firmware.mk
@@ -0,0 +1,52 @@
+################################################################################
+#
+# versal-firmware
+#
+################################################################################
+
+VERSAL_FIRMWARE_VERSION = $(call qstrip,$(BR2_TARGET_VERSAL_FIRMWARE_VERSION))
+VERSAL_FIRMWARE_SITE = \
+	$(call github,Xilinx,embeddedsw,$(VERSAL_FIRMWARE_VERSION))
+VERSAL_FIRMWARE_LICENSE = MIT
+VERSAL_FIRMWARE_LICENSE_FILES = license.txt
+VERSAL_FIRMWARE_INSTALL_IMAGES = YES
+VERSAL_FIRMWARE_INSTALL_TARGET = NO
+VERSAL_FIRMWARE_DEPENDENCIES = host-newlib-bare-metal
+
+CUSTOM_CFLAGS = $(call qstrip,$(BR2_TARGET_VERSAL_FIRMWARE_CUSTOM_CFLAGS))
+VERSAL_CFLAGS = "-Os -flto -ffat-lto-objects $(CUSTOM_CFLAGS)"
+
+VERSAL_FIRMWARE_PDI = $(call qstrip,$(BR2_TARGET_VERSAL_FIRMWARE_PDI))
+
+ifneq ($(findstring ://,$(VERSAL_FIRMWARE_PDI)),)
+VERSAL_FIRMWARE_EXTRA_DOWNLOADS = $(VERSAL_FIRMWARE_PDI)
+BR_NO_CHECK_HASH_FOR += $(notdir $(VERSAL_FIRMWARE_PDI))
+PDI_PATH = $(VERSAL_FIRMWARE_DL_DIR)/$(notdir $(VERSAL_FIRMWARE_PDI))
+else ifneq ($(VERSAL_FIRMWARE_PDI),)
+PDI_PATH = $(shell readlink -f $(VERSAL_FIRMWARE_PDI))
+endif #VERSAL_FIRMWARE_PDI
+
+define VERSAL_FIRMWARE_BUILD_CMDS
+	$(MAKE) -C $(@D)/lib/sw_apps/versal_plm/src/versal \
+		COMPILER=$(HOST_DIR)/bin/microblazeel-xilinx-elf-gcc \
+		ARCHIVER=$(HOST_DIR)/bin/microblazeel-xilinx-elf-gcc-ar \
+		CC=$(HOST_DIR)/bin/microblazeel-xilinx-elf-gcc \
+		CFLAGS=$(VERSAL_CFLAGS)
+		
+	$(MAKE) -C $(@D)/lib/sw_apps/versal_psmfw/src/versal \
+		COMPILER=$(HOST_DIR)/bin/microblazeel-xilinx-elf-gcc \
+		ARCHIVER=$(HOST_DIR)/bin/microblazeel-xilinx-elf-gcc-ar \
+		CC=$(HOST_DIR)/bin/microblazeel-xilinx-elf-gcc \
+		CFLAGS=$(VERSAL_CFLAGS)
+endef
+
+PLM_PATH = $(@D)/lib/sw_apps/versal_plm/src/versal/plm.elf
+PSMFW_PATH = $(@D)/lib/sw_apps/versal_psmfw/src/versal/psmfw.elf
+
+define VERSAL_FIRMWARE_INSTALL_IMAGES_CMDS
+	$(INSTALL) -D -m 0755 $(PLM_PATH) $(BINARIES_DIR)/plm.elf
+	$(INSTALL) -D -m 0755 $(PSMFW_PATH) $(BINARIES_DIR)/psmfw.elf
+	$(INSTALL) -D -m 0755 $(PDI_PATH) $(BINARIES_DIR)/vpl_gen_fixed.pdi
+endef
+
+$(eval $(generic-package))
diff --git a/boot/versal-firmware/xilinx_v2023.1/0001-sw_apps-versal_plm-add-support-of-parallel-build.patch b/boot/versal-firmware/xilinx_v2023.1/0001-sw_apps-versal_plm-add-support-of-parallel-build.patch
new file mode 100644
index 0000000000..84fffc1d82
--- /dev/null
+++ b/boot/versal-firmware/xilinx_v2023.1/0001-sw_apps-versal_plm-add-support-of-parallel-build.patch
@@ -0,0 +1,157 @@
+From 245509f87776c7727973480f08ead6f293a2f3b2 Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager@amd.com>
+Date: Mon, 4 Sep 2023 07:08:02 +0100
+Subject: [PATCH 1/2] sw_apps:versal_plm: add support of parallel build
+
+The build fails when make command is invoked with -j option.
+The root cause is, BSP_SEQUENTIAL_MAKEFILES variable is not assigned
+and exported properly in copy_bsp.sh file. Also, the 'all' target in
+src/Makefile tries to compile the source code before bsp copy was
+finished when -j option is enabled during build.
+
+Added BSP_SEQUENTIAL_MAKEFILES in the misc/Makefile to resolve the
+export issue and corrected dependency in the src/Makefile to let the bsp
+copy finished before compiling the source.
+
+Signed-off-by: Duvvi Divya <Duvvi.Divya@xilinx.com>
+Acked-by: Sreedhar Kundella <sreedhar.k@xilinx.com>
+---
+ lib/sw_apps/versal_plm/misc/versal/Makefile    | 12 +++++++++++-
+ lib/sw_apps/versal_plm/misc/versal/copy_bsp.sh | 11 -----------
+ lib/sw_apps/versal_plm/src/versal/Makefile     |  2 ++
+ 3 files changed, 13 insertions(+), 12 deletions(-)
+
+diff --git a/lib/sw_apps/versal_plm/misc/versal/Makefile b/lib/sw_apps/versal_plm/misc/versal/Makefile
+index 5c8e719e9c..d735f64530 100644
+--- a/lib/sw_apps/versal_plm/misc/versal/Makefile
++++ b/lib/sw_apps/versal_plm/misc/versal/Makefile
+@@ -7,6 +7,16 @@ PROCESSOR = psv_pmc_0
+ LIBRARIES = ${PROCESSOR}/lib/libxil.a
+ BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
+ SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
++DRIVERS_LIST=../drivers.txt
++SEQUENTIAL_MAKEFILES := $(shell cat ${DRIVERS_LIST})
++BSP_SEQUENTIAL_MAKEFILES = $(patsubst %, ${PROCESSOR}/libsrc/%/src/Makefile, $(SEQUENTIAL_MAKEFILES))
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/xilffs/src/Makefile
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/xilpdi/src/Makefile
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/xilplmi/src/Makefile
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/xilpuf/src/Makefile
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/xilloader/src/Makefile
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/xilnvm/src/Makefile
++BSP_SEQUENTIAL_MAKEFILES += ${PROCESSOR}/libsrc/xilsecure/src/Makefile
+ BSP_PARALLEL_MAKEFILES := $(filter-out $(BSP_SEQUENTIAL_MAKEFILES),$(BSP_MAKEFILES))
+ SEQ_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_SEQUENTIAL_MAKEFILES))
+ PAR_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_PARALLEL_MAKEFILES))
+@@ -16,7 +26,7 @@ ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ endif
+ 
+ all:
+-	$(MAKE) --no-print-directory seq_libs
++	$(MAKE) -j1 --no-print-directory seq_libs
+ 	$(MAKE) -j --no-print-directory par_libs
+ 	$(MAKE) --no-print-directory archive
+ 	@echo 'Finished building libraries'
+diff --git a/lib/sw_apps/versal_plm/misc/versal/copy_bsp.sh b/lib/sw_apps/versal_plm/misc/versal/copy_bsp.sh
+index 404e588ae2..244d36e2ee 100755
+--- a/lib/sw_apps/versal_plm/misc/versal/copy_bsp.sh
++++ b/lib/sw_apps/versal_plm/misc/versal/copy_bsp.sh
+@@ -29,7 +29,6 @@ STANDALONE_DIR=$EMBEDDED_SW_DIR/lib/bsp/standalone/src
+ 
+ # libraries dir
+ SERVICES_DIR=$EMBEDDED_SW_DIR/lib/sw_services
+-BSP_SEQUENTIAL_MAKEFILES=
+ 
+ # creation of BSP folders required
+ if [ -d $BSP_DIR ]; then
+@@ -52,7 +51,6 @@ fi
+ mkdir -p $BSP_DIR/libsrc/xilffs
+ cp -r $SERVICES_DIR/xilffs/src $BSP_DIR/libsrc/xilffs/
+ cp -r $SERVICES_DIR/xilffs/src/include/* $BSP_DIR/include/
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilffs/src/Makefile"
+ 
+ mkdir -p $BSP_DIR/libsrc/xilpdi/src
+ cp -r $SERVICES_DIR/xilpdi/src/Makefile $BSP_DIR/libsrc/xilpdi/src
+@@ -60,7 +58,6 @@ cp -r $SERVICES_DIR/xilpdi/src/versal/* $BSP_DIR/libsrc/xilpdi/src/
+ cp -r $SERVICES_DIR/xilpdi/src/versal/*.h $BSP_DIR/include/
+ cp -r $SERVICES_DIR/xilpdi/src/common/* $BSP_DIR/libsrc/xilpdi/src/
+ cp -r $SERVICES_DIR/xilpdi/src/common/*.h $BSP_DIR/include/
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilpdi/src/Makefile"
+ 
+ mkdir -p $BSP_DIR/libsrc/xilplmi/src
+ cp -r $SERVICES_DIR/xilplmi/src/Makefile $BSP_DIR/libsrc/xilplmi/src
+@@ -68,14 +65,12 @@ cp -r $SERVICES_DIR/xilplmi/src/versal/* $BSP_DIR/libsrc/xilplmi/src/
+ cp -r $SERVICES_DIR/xilplmi/src/versal/*.h $BSP_DIR/include/
+ cp -r $SERVICES_DIR/xilplmi/src/common/* $BSP_DIR/libsrc/xilplmi/src/
+ cp -r $SERVICES_DIR/xilplmi/src/common/*.h $BSP_DIR/include/
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilplmi/src/Makefile"
+ 
+ mkdir -p $BSP_DIR/libsrc/xilpuf/src
+ cp -r $SERVICES_DIR/xilpuf/src/Makefile $BSP_DIR/libsrc/xilpuf/src
+ cp -r $SERVICES_DIR/xilpuf/src/common/* $BSP_DIR/libsrc/xilpuf/src
+ cp -r $SERVICES_DIR/xilpuf/src/server/* $BSP_DIR/libsrc/xilpuf/src
+ cp -r $BSP_DIR/libsrc/xilpuf/src/*.h $BSP_DIR/include/
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilpuf/src/Makefile"
+ 
+ mkdir -p $BSP_DIR/libsrc/xilloader/src
+ cp -r $SERVICES_DIR/xilloader/src/Makefile $BSP_DIR/libsrc/xilloader/src
+@@ -83,7 +78,6 @@ cp -r $SERVICES_DIR/xilloader/src/versal/* $BSP_DIR/libsrc/xilloader/src/
+ cp -r $SERVICES_DIR/xilloader/src/versal/*.h $BSP_DIR/include/
+ cp -r $SERVICES_DIR/xilloader/src/common/* $BSP_DIR/libsrc/xilloader/src/
+ cp -r $SERVICES_DIR/xilloader/src/common/*.h $BSP_DIR/include/
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilloader/src/Makefile"
+ 
+ mkdir -p $BSP_DIR/libsrc/xilpm/src/
+ cp -r $SERVICES_DIR/xilpm/src/versal/common/* $BSP_DIR/libsrc/xilpm/src/
+@@ -94,7 +88,6 @@ cp -r $SERVICES_DIR/xilpm/src/versal_common/server/* $BSP_DIR/libsrc/xilpm/src/
+ cp -r $SERVICES_DIR/xilpm/src/versal_common/server/*.h $BSP_DIR/include/
+ cp -r $SERVICES_DIR/xilpm/src/versal_common/common/*.h $BSP_DIR/include/
+ cp -r $SERVICES_DIR/xilpm/src/versal_common/common/* $BSP_DIR/libsrc/xilpm/src/
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilpm/src/versal/common/Makefile"
+ 
+ mkdir -p $BSP_DIR/libsrc/xilnvm/src
+ cp -r $SERVICES_DIR/xilnvm/src/Makefile $BSP_DIR/libsrc/xilnvm/src
+@@ -103,7 +96,6 @@ cp -r $SERVICES_DIR/xilnvm/src/versal/server/* $BSP_DIR/libsrc/xilnvm/src/
+ cp -r $SERVICES_DIR/xilnvm/src/common/server/* $BSP_DIR/libsrc/xilnvm/src/
+ cp -r $SERVICES_DIR/xilnvm/src/common/* $BSP_DIR/libsrc/xilnvm/src/
+ cp $BSP_DIR/libsrc/xilnvm/src/*.h $BSP_DIR/include/
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilnvm/src/Makefile"
+ 
+ mkdir -p $BSP_DIR/libsrc/xilsecure/src
+ cp -r $SERVICES_DIR/xilsecure/src/Makefile $BSP_DIR/libsrc/xilsecure/src
+@@ -115,7 +107,6 @@ cp -r $SERVICES_DIR/xilsecure/src/versal/common/* $BSP_DIR/libsrc/xilsecure/src/
+ cp $BSP_DIR/libsrc/xilsecure/src/*.h $BSP_DIR/include/
+ mv $BSP_DIR/libsrc/xilsecure/src/libxilsecure_pmc.a $BSP_DIR/libsrc/xilsecure/src/libxilsecure.a
+ rm -f $BSP_DIR/libsrc/xilsecure/src/libxilsecure_*.a
+-BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/xilsecure/src/Makefile"
+ 
+ # copy bsp standalone code
+ cp -r $STANDALONE_DIR/common/*  $BSP_DIR/libsrc/standalone/src/
+@@ -144,7 +135,6 @@ do
+     cp -r $DRIVERS_DIR/$line/src/*.h $BSP_DIR/include/
+ # copy all the HSM generated driver files DRIVER_g.c
+ 	cp $WORKING_DIR/x"$line"_g.c $BSP_DIR/libsrc/$line/src/
+-	BSP_SEQUENTIAL_MAKEFILES="$BSP_SEQUENTIAL_MAKEFILES $BSP_DIR/libsrc/$line/src/Makefile"
+ done < $DRIVERS_LIST
+ 
+ #copy the processor code.
+@@ -176,4 +166,3 @@ cp $STANDALONE_DIR/microblaze/*.h  $BSP_DIR/include/
+ 
+ # no inbyte and outbyte present in standalone
+ cp $WORKING_DIR/inbyte.c $WORKING_DIR/outbyte.c  $BSP_DIR/libsrc/standalone/src/
+-export BSP_SEQUENTIAL_MAKEFILES
+diff --git a/lib/sw_apps/versal_plm/src/versal/Makefile b/lib/sw_apps/versal_plm/src/versal/Makefile
+index 15956c8a14..a944225845 100644
+--- a/lib/sw_apps/versal_plm/src/versal/Makefile
++++ b/lib/sw_apps/versal_plm/src/versal/Makefile
+@@ -32,6 +32,8 @@ all: $(EXEC)
+ $(EXEC): $(LIBS) $(OBJS) $(INCLUDES)
+ 	$(CC) -o $@ $(OBJS) $(CC_FLAGS) $(CFLAGS) $(LN_FLAGS) $(LIBPATH) $(LSCRIPT)
+ 
++$(OBJS): $(LIBS)
++
+ $(LIBS):
+ 	echo "Copying BSP files"
+ 	../../misc/versal/copy_bsp.sh
+-- 
+2.25.1
+
diff --git a/boot/versal-firmware/xilinx_v2023.1/0002-sw_apps-versal_psmfw-add-support-of-parallel-build.patch b/boot/versal-firmware/xilinx_v2023.1/0002-sw_apps-versal_psmfw-add-support-of-parallel-build.patch
new file mode 100644
index 0000000000..7918f20946
--- /dev/null
+++ b/boot/versal-firmware/xilinx_v2023.1/0002-sw_apps-versal_psmfw-add-support-of-parallel-build.patch
@@ -0,0 +1,48 @@
+From 2ed864ef5965b7466fb145f479ce0747123f2ce0 Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager@amd.com>
+Date: Mon, 4 Sep 2023 07:14:38 +0100
+Subject: [PATCH 2/2] sw_apps:versal_psmfw: add support of parallel build
+
+The PSMFW build fails when make command is invoked with -j option.
+The root cause is, the 'all' target in src/Makefile tries to compile
+the source code before bsp copy was finished when -j option is
+enabled during build.
+
+Corrected dependency in the src/Makefile to let the bsp copy
+finished before compiling the source.
+
+Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
+---
+ lib/sw_apps/versal_psmfw/misc/Makefile       | 2 +-
+ lib/sw_apps/versal_psmfw/src/versal/Makefile | 2 ++
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/lib/sw_apps/versal_psmfw/misc/Makefile b/lib/sw_apps/versal_psmfw/misc/Makefile
+index 02d85e492e..92d95d0896 100644
+--- a/lib/sw_apps/versal_psmfw/misc/Makefile
++++ b/lib/sw_apps/versal_psmfw/misc/Makefile
+@@ -17,7 +17,7 @@ ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ endif
+ 
+ all:
+-	$(MAKE) --no-print-directory seq_libs
++	$(MAKE) -j1 --no-print-directory seq_libs
+ 	$(MAKE) -j --no-print-directory par_libs
+ 	$(MAKE) --no-print-directory archive
+ 	@echo 'Finished building libraries'
+diff --git a/lib/sw_apps/versal_psmfw/src/versal/Makefile b/lib/sw_apps/versal_psmfw/src/versal/Makefile
+index 1572bbbca9..3f1589283b 100644
+--- a/lib/sw_apps/versal_psmfw/src/versal/Makefile
++++ b/lib/sw_apps/versal_psmfw/src/versal/Makefile
+@@ -33,6 +33,8 @@ all: $(EXEC)
+ $(EXEC): $(LIBS) $(OBJS) $(INCLUDES)
+ 	$(CC) -o $@ $(OBJS) $(CC_FLAGS) $(CFLAGS) $(LN_FLAGS) $(LIBPATH) $(LSCRIPT)
+ 
++$(OBJS): $(LIBS)
++
+ $(LIBS):
+ 	echo "Copying BSP files"
+ 	../../misc/copy_bsp.sh
+-- 
+2.25.1
+
-- 
2.25.1

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[Buildroot] [PATCH v5 09/10] configs/versal_vck190_defconfig: build plm and psmfw source

[Neal Frager via buildroot]

This patch migrates the versal_vck190_defconfig to use the new
versal-firmware package for building the versal plm and psmfw from source.

Signed-off-by: Neal Frager <neal.frager@amd.com>
---
V4->V5:
 - bootgen is selected automatically now
---
 configs/versal_vck190_defconfig | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/configs/versal_vck190_defconfig b/configs/versal_vck190_defconfig
index e30bb35b74..1e2fa6d21f 100644
--- a/configs/versal_vck190_defconfig
+++ b/configs/versal_vck190_defconfig
@@ -32,11 +32,10 @@ BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
 BR2_TARGET_UBOOT_NEEDS_GNUTLS=y
 BR2_TARGET_UBOOT_FORMAT_REMAKE_ELF=y
 BR2_TARGET_UBOOT_FORMAT_DTB=y
-BR2_PACKAGE_VERSAL_FIRMWARE=y
-BR2_PACKAGE_VERSAL_FIRMWARE_VERSION="xilinx_v2023.1"
-BR2_PACKAGE_VERSAL_FIRMWARE_BOARD="vck190"
+BR2_TARGET_VERSAL_FIRMWARE=y
+BR2_TARGET_VERSAL_FIRMWARE_VERSION="xilinx_v2023.1"
+BR2_TARGET_VERSAL_FIRMWARE_PDI="https://github.com/Xilinx/soc-prebuilt-firmware/raw/xilinx_v2023.1/vck190-versal/vpl_gen_fixed.pdi"
 BR2_PACKAGE_HOST_DOSFSTOOLS=y
 BR2_PACKAGE_HOST_GENIMAGE=y
 BR2_PACKAGE_HOST_MTOOLS=y
-BR2_PACKAGE_HOST_BOOTGEN=y
 BR2_GLOBAL_PATCH_DIR="board/versal/patches"
-- 
2.25.1

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[Buildroot] [PATCH v5 10/10] package/versal-firmware: remove package

[Neal Frager via buildroot]

This patch removes the package/versal-firmware as this package is replaced
by the boot/versal-firmware target boot firmware package for versal.

Signed-off-by: Neal Frager <neal.frager@amd.com>
---
V4->V5:
 - no changes
---
 DEVELOPERS                                 |  1 -
 package/Config.in                          |  1 -
 package/versal-firmware/Config.in          | 24 ----------------------
 package/versal-firmware/versal-firmware.mk | 21 -------------------
 4 files changed, 47 deletions(-)
 delete mode 100644 package/versal-firmware/Config.in
 delete mode 100644 package/versal-firmware/versal-firmware.mk

diff --git a/DEVELOPERS b/DEVELOPERS
index 9f9e36c674..fc16d24c73 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -2209,7 +2209,6 @@ F:	package/binutils-bare-metal/
 F:	package/bootgen/
 F:	package/gcc-bare-metal/
 F:	package/newlib-bare-metal/
-F:	package/versal-firmware/
 F:	toolchain/toolchain-bare-metal/
 
 N:	Nicola Di Lieto <nicola.dilieto@gmail.com>
diff --git a/package/Config.in b/package/Config.in
index 4e489c4706..228e9e2416 100644
--- a/package/Config.in
+++ b/package/Config.in
@@ -454,7 +454,6 @@ menu "Firmware"
 	source "package/sunxi-boards/Config.in"
 	source "package/ts4900-fpga/Config.in"
 	source "package/ux500-firmware/Config.in"
-	source "package/versal-firmware/Config.in"
 	source "package/wilc-firmware/Config.in"
 	source "package/wilink-bt-firmware/Config.in"
 	source "package/zd1211-firmware/Config.in"
diff --git a/package/versal-firmware/Config.in b/package/versal-firmware/Config.in
deleted file mode 100644
index 01daefd204..0000000000
--- a/package/versal-firmware/Config.in
+++ /dev/null
@@ -1,24 +0,0 @@
-config BR2_PACKAGE_VERSAL_FIRMWARE
-	bool "versal-firmware"
-	depends on BR2_aarch64
-	help
-	  Pre-built firmware files for Xilinx Versal boards.
-
-	  https://github.com/Xilinx/soc-prebuilt-firmware
-
-if BR2_PACKAGE_VERSAL_FIRMWARE
-
-config BR2_PACKAGE_VERSAL_FIRMWARE_VERSION
-	string "firmware version"
-	default "xilinx_v2023.1"
-	help
-	  Release version of Versal firmware.
-
-config BR2_PACKAGE_VERSAL_FIRMWARE_BOARD
-	string "board name"
-	default "vck190"
-	help
-	  Name of Versal target board.
-	  Used for installing the appropriate firmware.
-
-endif # BR2_PACKAGE_VERSAL_FIRMWARE
diff --git a/package/versal-firmware/versal-firmware.mk b/package/versal-firmware/versal-firmware.mk
deleted file mode 100644
index 1ced259be1..0000000000
--- a/package/versal-firmware/versal-firmware.mk
+++ /dev/null
@@ -1,21 +0,0 @@
-################################################################################
-#
-# versal-firmware
-#
-################################################################################
-
-VERSAL_FIRMWARE_VERSION = $(call qstrip,$(BR2_PACKAGE_VERSAL_FIRMWARE_VERSION))
-VERSAL_FIRMWARE_SITE = $(call github,Xilinx,soc-prebuilt-firmware,$(VERSAL_FIRMWARE_VERSION))
-VERSAL_FIRMWARE_LICENSE = MIT
-VERSAL_FIRMWARE_LICENSE_FILES = LICENSE
-VERSAL_FIRMWARE_INSTALL_TARGET = NO
-VERSAL_FIRMWARE_INSTALL_IMAGES = YES
-
-define VERSAL_FIRMWARE_INSTALL_IMAGES_CMDS
-	$(foreach f,plm.elf psmfw.elf vpl_gen_fixed.pdi,\
-		$(INSTALL) -D -m 0755 $(@D)/$(BR2_PACKAGE_VERSAL_FIRMWARE_BOARD)-versal/$(f) \
-			$(BINARIES_DIR)/$(f)
-	)
-endef
-
-$(eval $(generic-package))
-- 
2.25.1

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