From: Alexandre Mergnat <amergnat@baylibre.com> To: "Chun-Kuang Hu" <chunkuang.hu@kernel.org>, "Philipp Zabel" <p.zabel@pengutronix.de>, "Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>, "Maxime Ripard" <mripard@kernel.org>, "Thomas Zimmermann" <tzimmermann@suse.de>, "David Airlie" <airlied@gmail.com>, "Daniel Vetter" <daniel@ffwll.ch>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Conor Dooley" <conor+dt@kernel.org>, "Matthias Brugger" <matthias.bgg@gmail.com>, "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>, "Jitao Shi" <jitao.shi@mediatek.com>, "CK Hu" <ck.hu@mediatek.com>, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Michael Turquette" <mturquette@baylibre.com>, "Stephen Boyd" <sboyd@kernel.org>, "Fabien Parent" <fparent@baylibre.com>, "Markus Schneider-Pargmann" <msp@baylibre.com>, "Catalin Marinas" <catalin.marinas@arm.com>, "Will Deacon" <will@kernel.org> Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, linux-clk@vger.kernel.org, Alexandre Mergnat <amergnat@baylibre.com> Subject: [PATCH v3 16/17] arm64: dts: mediatek: add display blocks support for the MT8365 SoC Date: Thu, 18 Apr 2024 16:17:04 +0200 [thread overview] Message-ID: <20231023-display-support-v3-16-53388f3ed34b@baylibre.com> (raw) In-Reply-To: <20231023-display-support-v3-0-53388f3ed34b@baylibre.com> - Add aliases for each display components to help display drivers. - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals for the LED driver of mobile LCM. - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane output) - Add the display mutex support. - Add the following display component support: - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 133 +++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 24581f7410aa..d34519a33c90 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/mediatek,mt8365-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/memory/mediatek,mt8365-larb-port.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/power/mediatek,mt8365-power.h> @@ -17,6 +18,19 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + aal0 = &aal0; + ccorr0 = &ccorr0; + color0 = &color0; + dither0 = &dither0; + dpi0 = &dpi0; + dsi0 = &dsi0; + gamma0 = &gamma0; + ovl0 = &ovl0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -607,6 +621,15 @@ spi: spi@1100a000 { status = "disabled"; }; + disp_pwm: pwm@1100e000 { + compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + clock-names = "main", "mm"; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -703,6 +726,15 @@ ethernet: ethernet@112a0000 { status = "disabled"; }; + mipi_tx0: dsi-phy@11c00000 { + compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c00000 0 0x800>; + clock-output-names = "mipi_tx0_pll"; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; @@ -732,6 +764,13 @@ mmsys: syscon@14000000 { #clock-cells = <1>; }; + mutex: mutex@14001000 { + compatible = "mediatek,mt8365-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + smi_common: smi@14002000 { compatible = "mediatek,mt8365-smi-common"; reg = <0 0x14002000 0 0x1000>; @@ -755,6 +794,100 @@ larb0: larb@14003000 { mediatek,larb-id = <0>; }; + ovl0: ovl@1400b000 { + compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma0: rdma@1400d000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + color0: color@1400f000 { + compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + ccorr0: ccorr@14010000 { + compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + aal0: aal@14011000 { + compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x14011000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + gamma0: gamma@14012000 { + compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dither0: dither@14013000 { + compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + clock-names = "engine", "digital", "hs"; + clocks = <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; + phy-names = "dphy"; + phys = <&mipi_tx0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x14016000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size = <2048>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dpi0: dpi@14018000 { + compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; + reg = <0 0x14018000 0 0x1000>; + clocks = <&mmsys CLK_MM_DPI0_DPI0>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>; + clock-names = "pixel", "engine", "pll"; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + status = "disabled"; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Mergnat <amergnat@baylibre.com> To: "Chun-Kuang Hu" <chunkuang.hu@kernel.org>, "Philipp Zabel" <p.zabel@pengutronix.de>, "Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>, "Maxime Ripard" <mripard@kernel.org>, "Thomas Zimmermann" <tzimmermann@suse.de>, "David Airlie" <airlied@gmail.com>, "Daniel Vetter" <daniel@ffwll.ch>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Conor Dooley" <conor+dt@kernel.org>, "Matthias Brugger" <matthias.bgg@gmail.com>, "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>, "Jitao Shi" <jitao.shi@mediatek.com>, "CK Hu" <ck.hu@mediatek.com>, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Michael Turquette" <mturquette@baylibre.com>, "Stephen Boyd" <sboyd@kernel.org>, "Fabien Parent" <fparent@baylibre.com>, "Markus Schneider-Pargmann" <msp@baylibre.com>, "Catalin Marinas" <catalin.marinas@arm.com>, "Will Deacon" <will@kernel.org> Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, linux-clk@vger.kernel.org, Alexandre Mergnat <amergnat@baylibre.com> Subject: [PATCH v3 16/17] arm64: dts: mediatek: add display blocks support for the MT8365 SoC Date: Thu, 18 Apr 2024 16:17:04 +0200 [thread overview] Message-ID: <20231023-display-support-v3-16-53388f3ed34b@baylibre.com> (raw) In-Reply-To: <20231023-display-support-v3-0-53388f3ed34b@baylibre.com> - Add aliases for each display components to help display drivers. - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals for the LED driver of mobile LCM. - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane output) - Add the display mutex support. - Add the following display component support: - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 133 +++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 24581f7410aa..d34519a33c90 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/mediatek,mt8365-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/memory/mediatek,mt8365-larb-port.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/power/mediatek,mt8365-power.h> @@ -17,6 +18,19 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + aal0 = &aal0; + ccorr0 = &ccorr0; + color0 = &color0; + dither0 = &dither0; + dpi0 = &dpi0; + dsi0 = &dsi0; + gamma0 = &gamma0; + ovl0 = &ovl0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -607,6 +621,15 @@ spi: spi@1100a000 { status = "disabled"; }; + disp_pwm: pwm@1100e000 { + compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + clock-names = "main", "mm"; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -703,6 +726,15 @@ ethernet: ethernet@112a0000 { status = "disabled"; }; + mipi_tx0: dsi-phy@11c00000 { + compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c00000 0 0x800>; + clock-output-names = "mipi_tx0_pll"; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; @@ -732,6 +764,13 @@ mmsys: syscon@14000000 { #clock-cells = <1>; }; + mutex: mutex@14001000 { + compatible = "mediatek,mt8365-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + smi_common: smi@14002000 { compatible = "mediatek,mt8365-smi-common"; reg = <0 0x14002000 0 0x1000>; @@ -755,6 +794,100 @@ larb0: larb@14003000 { mediatek,larb-id = <0>; }; + ovl0: ovl@1400b000 { + compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma0: rdma@1400d000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + color0: color@1400f000 { + compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + ccorr0: ccorr@14010000 { + compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + aal0: aal@14011000 { + compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x14011000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + gamma0: gamma@14012000 { + compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dither0: dither@14013000 { + compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + clock-names = "engine", "digital", "hs"; + clocks = <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; + phy-names = "dphy"; + phys = <&mipi_tx0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x14016000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size = <2048>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dpi0: dpi@14018000 { + compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; + reg = <0 0x14018000 0 0x1000>; + clocks = <&mmsys CLK_MM_DPI0_DPI0>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>; + clock-names = "pixel", "engine", "pll"; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + status = "disabled"; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-04-18 14:17 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-18 14:16 [PATCH v3 00/17] Add display support for the MT8365-EVK board Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-18 14:16 ` [PATCH v3 01/17] dt-bindings: display: mediatek: aal: add compatible for MT8365 SoC Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-18 14:16 ` [PATCH v3 02/17] dt-bindings: display: mediatek: ccorr: " Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-18 14:16 ` [PATCH v3 03/17] dt-bindings: display: mediatek: color: " Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-18 14:16 ` [PATCH v3 04/17] dt-bindings: display: mediatek: dither: " Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-18 14:16 ` [PATCH v3 05/17] dt-bindings: display: mediatek: dsi: " Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-18 14:16 ` [PATCH v3 06/17] dt-bindings: display: mediatek: dpi: add power-domains property amergnat 2024-04-18 14:16 ` amergnat 2024-04-18 14:16 ` [PATCH v3 07/17] dt-bindings: display: mediatek: dpi: add compatible for MT8365 Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-19 7:27 ` AngeloGioacchino Del Regno 2024-04-19 7:27 ` AngeloGioacchino Del Regno 2024-04-22 13:39 ` Rob Herring 2024-04-22 13:39 ` Rob Herring 2024-04-18 14:16 ` [PATCH v3 08/17] dt-bindings: display: mediatek: gamma: add compatible for MT8365 SoC Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-18 14:16 ` [PATCH v3 09/17] dt-bindings: display: mediatek: ovl: " Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-18 14:16 ` [PATCH v3 10/17] dt-bindings: display: mediatek: rdma: " Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-18 14:16 ` [PATCH v3 11/17] dt-bindings: pwm: mediatek,pwm-disp: add compatible for mt8365 SoC Alexandre Mergnat 2024-04-18 14:16 ` Alexandre Mergnat 2024-04-18 15:57 ` Uwe Kleine-König 2024-04-18 15:57 ` Uwe Kleine-König 2024-04-18 14:17 ` [PATCH v3 12/17] clk: mediatek: mt8365-mm: fix DPI0 parent Alexandre Mergnat 2024-04-18 14:17 ` Alexandre Mergnat 2024-04-19 7:34 ` AngeloGioacchino Del Regno 2024-04-19 7:34 ` AngeloGioacchino Del Regno 2024-04-20 1:53 ` Stephen Boyd 2024-04-20 1:53 ` Stephen Boyd 2024-04-18 14:17 ` [PATCH v3 13/17] drm/mediatek: dsi: Improves the DSI lane setup robustness Alexandre Mergnat 2024-04-18 14:17 ` Alexandre Mergnat 2024-04-18 14:17 ` [PATCH v3 14/17] drm/mediatek: add MT8365 SoC support amergnat 2024-04-18 14:17 ` amergnat 2024-04-19 8:01 ` AngeloGioacchino Del Regno 2024-04-19 8:01 ` AngeloGioacchino Del Regno 2024-04-19 9:22 ` Alexandre Mergnat 2024-04-19 9:22 ` Alexandre Mergnat 2024-04-18 14:17 ` [PATCH v3 15/17] arm64: defconfig: enable display connector support Alexandre Mergnat 2024-04-18 14:17 ` Alexandre Mergnat 2024-04-18 14:17 ` Alexandre Mergnat [this message] 2024-04-18 14:17 ` [PATCH v3 16/17] arm64: dts: mediatek: add display blocks support for the MT8365 SoC Alexandre Mergnat 2024-04-18 14:17 ` [PATCH v3 17/17] arm64: dts: mediatek: add display support for mt8365-evk Alexandre Mergnat 2024-04-18 14:17 ` Alexandre Mergnat
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